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drm/i915: Check whether the LVDS downclock is found in VBT
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include "drmP.h"
32 #include "intel_drv.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "intel_dp.h"
36
37 #include "drm_crtc_helper.h"
38
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
40
41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
42 static void intel_update_watermarks(struct drm_device *dev);
43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
44
45 typedef struct {
46 /* given values */
47 int n;
48 int m1, m2;
49 int p1, p2;
50 /* derived values */
51 int dot;
52 int vco;
53 int m;
54 int p;
55 } intel_clock_t;
56
57 typedef struct {
58 int min, max;
59 } intel_range_t;
60
61 typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64 } intel_p2_t;
65
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t;
68 struct intel_limit {
69 intel_range_t dot, vco, n, m, m1, m2, p, p1;
70 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
73 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
75 };
76
77 #define I8XX_DOT_MIN 25000
78 #define I8XX_DOT_MAX 350000
79 #define I8XX_VCO_MIN 930000
80 #define I8XX_VCO_MAX 1400000
81 #define I8XX_N_MIN 3
82 #define I8XX_N_MAX 16
83 #define I8XX_M_MIN 96
84 #define I8XX_M_MAX 140
85 #define I8XX_M1_MIN 18
86 #define I8XX_M1_MAX 26
87 #define I8XX_M2_MIN 6
88 #define I8XX_M2_MAX 16
89 #define I8XX_P_MIN 4
90 #define I8XX_P_MAX 128
91 #define I8XX_P1_MIN 2
92 #define I8XX_P1_MAX 33
93 #define I8XX_P1_LVDS_MIN 1
94 #define I8XX_P1_LVDS_MAX 6
95 #define I8XX_P2_SLOW 4
96 #define I8XX_P2_FAST 2
97 #define I8XX_P2_LVDS_SLOW 14
98 #define I8XX_P2_LVDS_FAST 7
99 #define I8XX_P2_SLOW_LIMIT 165000
100
101 #define I9XX_DOT_MIN 20000
102 #define I9XX_DOT_MAX 400000
103 #define I9XX_VCO_MIN 1400000
104 #define I9XX_VCO_MAX 2800000
105 #define IGD_VCO_MIN 1700000
106 #define IGD_VCO_MAX 3500000
107 #define I9XX_N_MIN 1
108 #define I9XX_N_MAX 6
109 /* IGD's Ncounter is a ring counter */
110 #define IGD_N_MIN 3
111 #define IGD_N_MAX 6
112 #define I9XX_M_MIN 70
113 #define I9XX_M_MAX 120
114 #define IGD_M_MIN 2
115 #define IGD_M_MAX 256
116 #define I9XX_M1_MIN 10
117 #define I9XX_M1_MAX 22
118 #define I9XX_M2_MIN 5
119 #define I9XX_M2_MAX 9
120 /* IGD M1 is reserved, and must be 0 */
121 #define IGD_M1_MIN 0
122 #define IGD_M1_MAX 0
123 #define IGD_M2_MIN 0
124 #define IGD_M2_MAX 254
125 #define I9XX_P_SDVO_DAC_MIN 5
126 #define I9XX_P_SDVO_DAC_MAX 80
127 #define I9XX_P_LVDS_MIN 7
128 #define I9XX_P_LVDS_MAX 98
129 #define IGD_P_LVDS_MIN 7
130 #define IGD_P_LVDS_MAX 112
131 #define I9XX_P1_MIN 1
132 #define I9XX_P1_MAX 8
133 #define I9XX_P2_SDVO_DAC_SLOW 10
134 #define I9XX_P2_SDVO_DAC_FAST 5
135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
136 #define I9XX_P2_LVDS_SLOW 14
137 #define I9XX_P2_LVDS_FAST 7
138 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
139
140 /*The parameter is for SDVO on G4x platform*/
141 #define G4X_DOT_SDVO_MIN 25000
142 #define G4X_DOT_SDVO_MAX 270000
143 #define G4X_VCO_MIN 1750000
144 #define G4X_VCO_MAX 3500000
145 #define G4X_N_SDVO_MIN 1
146 #define G4X_N_SDVO_MAX 4
147 #define G4X_M_SDVO_MIN 104
148 #define G4X_M_SDVO_MAX 138
149 #define G4X_M1_SDVO_MIN 17
150 #define G4X_M1_SDVO_MAX 23
151 #define G4X_M2_SDVO_MIN 5
152 #define G4X_M2_SDVO_MAX 11
153 #define G4X_P_SDVO_MIN 10
154 #define G4X_P_SDVO_MAX 30
155 #define G4X_P1_SDVO_MIN 1
156 #define G4X_P1_SDVO_MAX 3
157 #define G4X_P2_SDVO_SLOW 10
158 #define G4X_P2_SDVO_FAST 10
159 #define G4X_P2_SDVO_LIMIT 270000
160
161 /*The parameter is for HDMI_DAC on G4x platform*/
162 #define G4X_DOT_HDMI_DAC_MIN 22000
163 #define G4X_DOT_HDMI_DAC_MAX 400000
164 #define G4X_N_HDMI_DAC_MIN 1
165 #define G4X_N_HDMI_DAC_MAX 4
166 #define G4X_M_HDMI_DAC_MIN 104
167 #define G4X_M_HDMI_DAC_MAX 138
168 #define G4X_M1_HDMI_DAC_MIN 16
169 #define G4X_M1_HDMI_DAC_MAX 23
170 #define G4X_M2_HDMI_DAC_MIN 5
171 #define G4X_M2_HDMI_DAC_MAX 11
172 #define G4X_P_HDMI_DAC_MIN 5
173 #define G4X_P_HDMI_DAC_MAX 80
174 #define G4X_P1_HDMI_DAC_MIN 1
175 #define G4X_P1_HDMI_DAC_MAX 8
176 #define G4X_P2_HDMI_DAC_SLOW 10
177 #define G4X_P2_HDMI_DAC_FAST 5
178 #define G4X_P2_HDMI_DAC_LIMIT 165000
179
180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198
199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217
218 /*The parameter is for DISPLAY PORT on G4x platform*/
219 #define G4X_DOT_DISPLAY_PORT_MIN 161670
220 #define G4X_DOT_DISPLAY_PORT_MAX 227000
221 #define G4X_N_DISPLAY_PORT_MIN 1
222 #define G4X_N_DISPLAY_PORT_MAX 2
223 #define G4X_M_DISPLAY_PORT_MIN 97
224 #define G4X_M_DISPLAY_PORT_MAX 108
225 #define G4X_M1_DISPLAY_PORT_MIN 0x10
226 #define G4X_M1_DISPLAY_PORT_MAX 0x12
227 #define G4X_M2_DISPLAY_PORT_MIN 0x05
228 #define G4X_M2_DISPLAY_PORT_MAX 0x06
229 #define G4X_P_DISPLAY_PORT_MIN 10
230 #define G4X_P_DISPLAY_PORT_MAX 20
231 #define G4X_P1_DISPLAY_PORT_MIN 1
232 #define G4X_P1_DISPLAY_PORT_MAX 2
233 #define G4X_P2_DISPLAY_PORT_SLOW 10
234 #define G4X_P2_DISPLAY_PORT_FAST 10
235 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236
237 /* IGDNG */
238 /* as we calculate clock using (register_value + 2) for
239 N/M1/M2, so here the range value for them is (actual_value-2).
240 */
241 #define IGDNG_DOT_MIN 25000
242 #define IGDNG_DOT_MAX 350000
243 #define IGDNG_VCO_MIN 1760000
244 #define IGDNG_VCO_MAX 3510000
245 #define IGDNG_N_MIN 1
246 #define IGDNG_N_MAX 5
247 #define IGDNG_M_MIN 79
248 #define IGDNG_M_MAX 118
249 #define IGDNG_M1_MIN 12
250 #define IGDNG_M1_MAX 23
251 #define IGDNG_M2_MIN 5
252 #define IGDNG_M2_MAX 9
253 #define IGDNG_P_SDVO_DAC_MIN 5
254 #define IGDNG_P_SDVO_DAC_MAX 80
255 #define IGDNG_P_LVDS_MIN 28
256 #define IGDNG_P_LVDS_MAX 112
257 #define IGDNG_P1_MIN 1
258 #define IGDNG_P1_MAX 8
259 #define IGDNG_P2_SDVO_DAC_SLOW 10
260 #define IGDNG_P2_SDVO_DAC_FAST 5
261 #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
262 #define IGDNG_P2_LVDS_FAST 7 /* double channel */
263 #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
264
265 static bool
266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
267 int target, int refclk, intel_clock_t *best_clock);
268 static bool
269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271 static bool
272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock);
274 static bool
275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
277
278 static bool
279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock);
281 static bool
282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock);
284
285 static const intel_limit_t intel_limits_i8xx_dvo = {
286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
287 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
288 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
289 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
290 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
291 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
292 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
293 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
296 .find_pll = intel_find_best_PLL,
297 .find_reduced_pll = intel_find_best_reduced_PLL,
298 };
299
300 static const intel_limit_t intel_limits_i8xx_lvds = {
301 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
302 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
303 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
304 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
305 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
306 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
307 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
308 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
309 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
310 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
311 .find_pll = intel_find_best_PLL,
312 .find_reduced_pll = intel_find_best_reduced_PLL,
313 };
314
315 static const intel_limit_t intel_limits_i9xx_sdvo = {
316 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
317 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
318 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
319 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
320 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
321 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
322 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
323 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
324 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
325 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
326 .find_pll = intel_find_best_PLL,
327 .find_reduced_pll = intel_find_best_reduced_PLL,
328 };
329
330 static const intel_limit_t intel_limits_i9xx_lvds = {
331 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
332 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
333 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
334 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
335 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
336 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
337 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
338 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
339 /* The single-channel range is 25-112Mhz, and dual-channel
340 * is 80-224Mhz. Prefer single channel as much as possible.
341 */
342 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
343 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
344 .find_pll = intel_find_best_PLL,
345 .find_reduced_pll = intel_find_best_reduced_PLL,
346 };
347
348 /* below parameter and function is for G4X Chipset Family*/
349 static const intel_limit_t intel_limits_g4x_sdvo = {
350 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
351 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
352 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
353 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
354 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
355 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
356 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
357 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
358 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
359 .p2_slow = G4X_P2_SDVO_SLOW,
360 .p2_fast = G4X_P2_SDVO_FAST
361 },
362 .find_pll = intel_g4x_find_best_PLL,
363 .find_reduced_pll = intel_g4x_find_best_PLL,
364 };
365
366 static const intel_limit_t intel_limits_g4x_hdmi = {
367 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
368 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
369 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
370 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
371 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
372 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
373 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
374 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
375 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
376 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
377 .p2_fast = G4X_P2_HDMI_DAC_FAST
378 },
379 .find_pll = intel_g4x_find_best_PLL,
380 .find_reduced_pll = intel_g4x_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
384 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
385 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
386 .vco = { .min = G4X_VCO_MIN,
387 .max = G4X_VCO_MAX },
388 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
389 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
390 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
391 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
392 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
393 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
394 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
395 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
396 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
397 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
398 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
399 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
400 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
401 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
402 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
403 },
404 .find_pll = intel_g4x_find_best_PLL,
405 .find_reduced_pll = intel_g4x_find_best_PLL,
406 };
407
408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
409 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
410 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
411 .vco = { .min = G4X_VCO_MIN,
412 .max = G4X_VCO_MAX },
413 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
414 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
415 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
416 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
417 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
418 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
419 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
420 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
421 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
422 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
423 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
424 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
425 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
426 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
427 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
428 },
429 .find_pll = intel_g4x_find_best_PLL,
430 .find_reduced_pll = intel_g4x_find_best_PLL,
431 };
432
433 static const intel_limit_t intel_limits_g4x_display_port = {
434 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
435 .max = G4X_DOT_DISPLAY_PORT_MAX },
436 .vco = { .min = G4X_VCO_MIN,
437 .max = G4X_VCO_MAX},
438 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
439 .max = G4X_N_DISPLAY_PORT_MAX },
440 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
441 .max = G4X_M_DISPLAY_PORT_MAX },
442 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
443 .max = G4X_M1_DISPLAY_PORT_MAX },
444 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
445 .max = G4X_M2_DISPLAY_PORT_MAX },
446 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
447 .max = G4X_P_DISPLAY_PORT_MAX },
448 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
449 .max = G4X_P1_DISPLAY_PORT_MAX},
450 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
451 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
452 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
453 .find_pll = intel_find_pll_g4x_dp,
454 };
455
456 static const intel_limit_t intel_limits_igd_sdvo = {
457 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
458 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
459 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
460 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
461 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
462 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
463 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
464 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
465 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
466 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
467 .find_pll = intel_find_best_PLL,
468 .find_reduced_pll = intel_find_best_reduced_PLL,
469 };
470
471 static const intel_limit_t intel_limits_igd_lvds = {
472 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
473 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
474 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
475 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
476 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
477 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
478 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
479 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
480 /* IGD only supports single-channel mode. */
481 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
482 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
483 .find_pll = intel_find_best_PLL,
484 .find_reduced_pll = intel_find_best_reduced_PLL,
485 };
486
487 static const intel_limit_t intel_limits_igdng_sdvo = {
488 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
489 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
490 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
491 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
492 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
493 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
494 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
495 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
496 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
497 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
498 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
499 .find_pll = intel_igdng_find_best_PLL,
500 };
501
502 static const intel_limit_t intel_limits_igdng_lvds = {
503 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
504 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
505 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
506 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
507 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
508 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
509 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
510 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
511 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
512 .p2_slow = IGDNG_P2_LVDS_SLOW,
513 .p2_fast = IGDNG_P2_LVDS_FAST },
514 .find_pll = intel_igdng_find_best_PLL,
515 };
516
517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
518 {
519 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
521 limit = &intel_limits_igdng_lvds;
522 else
523 limit = &intel_limits_igdng_sdvo;
524
525 return limit;
526 }
527
528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
529 {
530 struct drm_device *dev = crtc->dev;
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 const intel_limit_t *limit;
533
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
535 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
536 LVDS_CLKB_POWER_UP)
537 /* LVDS with dual channel */
538 limit = &intel_limits_g4x_dual_channel_lvds;
539 else
540 /* LVDS with dual channel */
541 limit = &intel_limits_g4x_single_channel_lvds;
542 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
543 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
544 limit = &intel_limits_g4x_hdmi;
545 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
546 limit = &intel_limits_g4x_sdvo;
547 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
548 limit = &intel_limits_g4x_display_port;
549 } else /* The option is for other outputs */
550 limit = &intel_limits_i9xx_sdvo;
551
552 return limit;
553 }
554
555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
556 {
557 struct drm_device *dev = crtc->dev;
558 const intel_limit_t *limit;
559
560 if (IS_IGDNG(dev))
561 limit = intel_igdng_limit(crtc);
562 else if (IS_G4X(dev)) {
563 limit = intel_g4x_limit(crtc);
564 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
566 limit = &intel_limits_i9xx_lvds;
567 else
568 limit = &intel_limits_i9xx_sdvo;
569 } else if (IS_IGD(dev)) {
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
571 limit = &intel_limits_igd_lvds;
572 else
573 limit = &intel_limits_igd_sdvo;
574 } else {
575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
576 limit = &intel_limits_i8xx_lvds;
577 else
578 limit = &intel_limits_i8xx_dvo;
579 }
580 return limit;
581 }
582
583 /* m1 is reserved as 0 in IGD, n is a ring counter */
584 static void igd_clock(int refclk, intel_clock_t *clock)
585 {
586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 clock->vco = refclk * clock->m / clock->n;
589 clock->dot = clock->vco / clock->p;
590 }
591
592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
593 {
594 if (IS_IGD(dev)) {
595 igd_clock(refclk, clock);
596 return;
597 }
598 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
599 clock->p = clock->p1 * clock->p2;
600 clock->vco = refclk * clock->m / (clock->n + 2);
601 clock->dot = clock->vco / clock->p;
602 }
603
604 /**
605 * Returns whether any output on the specified pipe is of the specified type
606 */
607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
608 {
609 struct drm_device *dev = crtc->dev;
610 struct drm_mode_config *mode_config = &dev->mode_config;
611 struct drm_connector *l_entry;
612
613 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
614 if (l_entry->encoder &&
615 l_entry->encoder->crtc == crtc) {
616 struct intel_output *intel_output = to_intel_output(l_entry);
617 if (intel_output->type == type)
618 return true;
619 }
620 }
621 return false;
622 }
623
624 struct drm_connector *
625 intel_pipe_get_output (struct drm_crtc *crtc)
626 {
627 struct drm_device *dev = crtc->dev;
628 struct drm_mode_config *mode_config = &dev->mode_config;
629 struct drm_connector *l_entry, *ret = NULL;
630
631 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
632 if (l_entry->encoder &&
633 l_entry->encoder->crtc == crtc) {
634 ret = l_entry;
635 break;
636 }
637 }
638 return ret;
639 }
640
641 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
642 /**
643 * Returns whether the given set of divisors are valid for a given refclk with
644 * the given connectors.
645 */
646
647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
648 {
649 const intel_limit_t *limit = intel_limit (crtc);
650 struct drm_device *dev = crtc->dev;
651
652 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
653 INTELPllInvalid ("p1 out of range\n");
654 if (clock->p < limit->p.min || limit->p.max < clock->p)
655 INTELPllInvalid ("p out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid ("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid ("m1 out of range\n");
660 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
661 INTELPllInvalid ("m1 <= m2\n");
662 if (clock->m < limit->m.min || limit->m.max < clock->m)
663 INTELPllInvalid ("m out of range\n");
664 if (clock->n < limit->n.min || limit->n.max < clock->n)
665 INTELPllInvalid ("n out of range\n");
666 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
667 INTELPllInvalid ("vco out of range\n");
668 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
669 * connector, etc., rather than just a single range.
670 */
671 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
672 INTELPllInvalid ("dot out of range\n");
673
674 return true;
675 }
676
677 static bool
678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *best_clock)
680
681 {
682 struct drm_device *dev = crtc->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 intel_clock_t clock;
685 int err = target;
686
687 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
688 (I915_READ(LVDS)) != 0) {
689 /*
690 * For LVDS, if the panel is on, just rely on its current
691 * settings for dual-channel. We haven't figured out how to
692 * reliably set up different single/dual channel state, if we
693 * even can.
694 */
695 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
696 LVDS_CLKB_POWER_UP)
697 clock.p2 = limit->p2.p2_fast;
698 else
699 clock.p2 = limit->p2.p2_slow;
700 } else {
701 if (target < limit->p2.dot_limit)
702 clock.p2 = limit->p2.p2_slow;
703 else
704 clock.p2 = limit->p2.p2_fast;
705 }
706
707 memset (best_clock, 0, sizeof (*best_clock));
708
709 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
711 clock.m1++) {
712 for (clock.m2 = limit->m2.min;
713 clock.m2 <= limit->m2.max; clock.m2++) {
714 /* m1 is always 0 in IGD */
715 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
716 break;
717 for (clock.n = limit->n.min;
718 clock.n <= limit->n.max; clock.n++) {
719 int this_err;
720
721 intel_clock(dev, refclk, &clock);
722
723 if (!intel_PLL_is_valid(crtc, &clock))
724 continue;
725
726 this_err = abs(clock.dot - target);
727 if (this_err < err) {
728 *best_clock = clock;
729 err = this_err;
730 }
731 }
732 }
733 }
734 }
735
736 return (err != target);
737 }
738
739
740 static bool
741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *best_clock)
743
744 {
745 struct drm_device *dev = crtc->dev;
746 intel_clock_t clock;
747 int err = target;
748 bool found = false;
749
750 memcpy(&clock, best_clock, sizeof(intel_clock_t));
751
752 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
753 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
754 /* m1 is always 0 in IGD */
755 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
756 break;
757 for (clock.n = limit->n.min; clock.n <= limit->n.max;
758 clock.n++) {
759 int this_err;
760
761 intel_clock(dev, refclk, &clock);
762
763 if (!intel_PLL_is_valid(crtc, &clock))
764 continue;
765
766 this_err = abs(clock.dot - target);
767 if (this_err < err) {
768 *best_clock = clock;
769 err = this_err;
770 found = true;
771 }
772 }
773 }
774 }
775
776 return found;
777 }
778
779 static bool
780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
781 int target, int refclk, intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->dev;
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 intel_clock_t clock;
786 int max_n;
787 bool found;
788 /* approximately equals target * 0.00488 */
789 int err_most = (target >> 8) + (target >> 10);
790 found = false;
791
792 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
793 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
794 LVDS_CLKB_POWER_UP)
795 clock.p2 = limit->p2.p2_fast;
796 else
797 clock.p2 = limit->p2.p2_slow;
798 } else {
799 if (target < limit->p2.dot_limit)
800 clock.p2 = limit->p2.p2_slow;
801 else
802 clock.p2 = limit->p2.p2_fast;
803 }
804
805 memset(best_clock, 0, sizeof(*best_clock));
806 max_n = limit->n.max;
807 /* based on hardware requriment prefer smaller n to precision */
808 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
809 /* based on hardware requirment prefere larger m1,m2 */
810 for (clock.m1 = limit->m1.max;
811 clock.m1 >= limit->m1.min; clock.m1--) {
812 for (clock.m2 = limit->m2.max;
813 clock.m2 >= limit->m2.min; clock.m2--) {
814 for (clock.p1 = limit->p1.max;
815 clock.p1 >= limit->p1.min; clock.p1--) {
816 int this_err;
817
818 intel_clock(dev, refclk, &clock);
819 if (!intel_PLL_is_valid(crtc, &clock))
820 continue;
821 this_err = abs(clock.dot - target) ;
822 if (this_err < err_most) {
823 *best_clock = clock;
824 err_most = this_err;
825 max_n = clock.n;
826 found = true;
827 }
828 }
829 }
830 }
831 }
832 return found;
833 }
834
835 static bool
836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *best_clock)
838 {
839 struct drm_device *dev = crtc->dev;
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.n = 1;
843 clock.p1 = 2;
844 clock.p2 = 10;
845 clock.m1 = 12;
846 clock.m2 = 9;
847 } else {
848 clock.n = 2;
849 clock.p1 = 1;
850 clock.p2 = 10;
851 clock.m1 = 14;
852 clock.m2 = 8;
853 }
854 intel_clock(dev, refclk, &clock);
855 memcpy(best_clock, &clock, sizeof(intel_clock_t));
856 return true;
857 }
858
859 static bool
860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock)
862 {
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock;
866 int err_most = 47;
867 int err_min = 10000;
868
869 /* eDP has only 2 clock choice, no n/m/p setting */
870 if (HAS_eDP)
871 return true;
872
873 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
874 return intel_find_pll_igdng_dp(limit, crtc, target,
875 refclk, best_clock);
876
877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
878 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
879 LVDS_CLKB_POWER_UP)
880 clock.p2 = limit->p2.p2_fast;
881 else
882 clock.p2 = limit->p2.p2_slow;
883 } else {
884 if (target < limit->p2.dot_limit)
885 clock.p2 = limit->p2.p2_slow;
886 else
887 clock.p2 = limit->p2.p2_fast;
888 }
889
890 memset(best_clock, 0, sizeof(*best_clock));
891 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
892 /* based on hardware requriment prefer smaller n to precision */
893 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
894 /* based on hardware requirment prefere larger m1,m2 */
895 for (clock.m1 = limit->m1.max;
896 clock.m1 >= limit->m1.min; clock.m1--) {
897 for (clock.m2 = limit->m2.max;
898 clock.m2 >= limit->m2.min; clock.m2--) {
899 int this_err;
900
901 intel_clock(dev, refclk, &clock);
902 if (!intel_PLL_is_valid(crtc, &clock))
903 continue;
904 this_err = abs((10000 - (target*10000/clock.dot)));
905 if (this_err < err_most) {
906 *best_clock = clock;
907 /* found on first matching */
908 goto out;
909 } else if (this_err < err_min) {
910 *best_clock = clock;
911 err_min = this_err;
912 }
913 }
914 }
915 }
916 }
917 out:
918 return true;
919 }
920
921 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
922 static bool
923 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
924 int target, int refclk, intel_clock_t *best_clock)
925 {
926 intel_clock_t clock;
927 if (target < 200000) {
928 clock.p1 = 2;
929 clock.p2 = 10;
930 clock.n = 2;
931 clock.m1 = 23;
932 clock.m2 = 8;
933 } else {
934 clock.p1 = 1;
935 clock.p2 = 10;
936 clock.n = 1;
937 clock.m1 = 14;
938 clock.m2 = 2;
939 }
940 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
941 clock.p = (clock.p1 * clock.p2);
942 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
943 clock.vco = 0;
944 memcpy(best_clock, &clock, sizeof(intel_clock_t));
945 return true;
946 }
947
948 void
949 intel_wait_for_vblank(struct drm_device *dev)
950 {
951 /* Wait for 20ms, i.e. one cycle at 50hz. */
952 mdelay(20);
953 }
954
955 /* Parameters have changed, update FBC info */
956 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
957 {
958 struct drm_device *dev = crtc->dev;
959 struct drm_i915_private *dev_priv = dev->dev_private;
960 struct drm_framebuffer *fb = crtc->fb;
961 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
962 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
964 int plane, i;
965 u32 fbc_ctl, fbc_ctl2;
966
967 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
968
969 if (fb->pitch < dev_priv->cfb_pitch)
970 dev_priv->cfb_pitch = fb->pitch;
971
972 /* FBC_CTL wants 64B units */
973 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
974 dev_priv->cfb_fence = obj_priv->fence_reg;
975 dev_priv->cfb_plane = intel_crtc->plane;
976 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
977
978 /* Clear old tags */
979 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
980 I915_WRITE(FBC_TAG + (i * 4), 0);
981
982 /* Set it up... */
983 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
984 if (obj_priv->tiling_mode != I915_TILING_NONE)
985 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
986 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
987 I915_WRITE(FBC_FENCE_OFF, crtc->y);
988
989 /* enable it... */
990 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
991 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
992 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
993 if (obj_priv->tiling_mode != I915_TILING_NONE)
994 fbc_ctl |= dev_priv->cfb_fence;
995 I915_WRITE(FBC_CONTROL, fbc_ctl);
996
997 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
998 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
999 }
1000
1001 void i8xx_disable_fbc(struct drm_device *dev)
1002 {
1003 struct drm_i915_private *dev_priv = dev->dev_private;
1004 u32 fbc_ctl;
1005
1006 if (!I915_HAS_FBC(dev))
1007 return;
1008
1009 /* Disable compression */
1010 fbc_ctl = I915_READ(FBC_CONTROL);
1011 fbc_ctl &= ~FBC_CTL_EN;
1012 I915_WRITE(FBC_CONTROL, fbc_ctl);
1013
1014 /* Wait for compressing bit to clear */
1015 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1016 ; /* nothing */
1017
1018 intel_wait_for_vblank(dev);
1019
1020 DRM_DEBUG_KMS("disabled FBC\n");
1021 }
1022
1023 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1024 {
1025 struct drm_device *dev = crtc->dev;
1026 struct drm_i915_private *dev_priv = dev->dev_private;
1027
1028 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1029 }
1030
1031 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1032 {
1033 struct drm_device *dev = crtc->dev;
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1035 struct drm_framebuffer *fb = crtc->fb;
1036 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1037 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1039 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1040 DPFC_CTL_PLANEB);
1041 unsigned long stall_watermark = 200;
1042 u32 dpfc_ctl;
1043
1044 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1045 dev_priv->cfb_fence = obj_priv->fence_reg;
1046 dev_priv->cfb_plane = intel_crtc->plane;
1047
1048 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1049 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1050 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1051 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1052 } else {
1053 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1054 }
1055
1056 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1057 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1058 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1059 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1060 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1061
1062 /* enable it... */
1063 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1064
1065 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1066 }
1067
1068 void g4x_disable_fbc(struct drm_device *dev)
1069 {
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 u32 dpfc_ctl;
1072
1073 /* Disable compression */
1074 dpfc_ctl = I915_READ(DPFC_CONTROL);
1075 dpfc_ctl &= ~DPFC_CTL_EN;
1076 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1077 intel_wait_for_vblank(dev);
1078
1079 DRM_DEBUG_KMS("disabled FBC\n");
1080 }
1081
1082 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1083 {
1084 struct drm_device *dev = crtc->dev;
1085 struct drm_i915_private *dev_priv = dev->dev_private;
1086
1087 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1088 }
1089
1090 /**
1091 * intel_update_fbc - enable/disable FBC as needed
1092 * @crtc: CRTC to point the compressor at
1093 * @mode: mode in use
1094 *
1095 * Set up the framebuffer compression hardware at mode set time. We
1096 * enable it if possible:
1097 * - plane A only (on pre-965)
1098 * - no pixel mulitply/line duplication
1099 * - no alpha buffer discard
1100 * - no dual wide
1101 * - framebuffer <= 2048 in width, 1536 in height
1102 *
1103 * We can't assume that any compression will take place (worst case),
1104 * so the compressed buffer has to be the same size as the uncompressed
1105 * one. It also must reside (along with the line length buffer) in
1106 * stolen memory.
1107 *
1108 * We need to enable/disable FBC on a global basis.
1109 */
1110 static void intel_update_fbc(struct drm_crtc *crtc,
1111 struct drm_display_mode *mode)
1112 {
1113 struct drm_device *dev = crtc->dev;
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 struct drm_framebuffer *fb = crtc->fb;
1116 struct intel_framebuffer *intel_fb;
1117 struct drm_i915_gem_object *obj_priv;
1118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1119 int plane = intel_crtc->plane;
1120
1121 if (!i915_powersave)
1122 return;
1123
1124 if (!dev_priv->display.fbc_enabled ||
1125 !dev_priv->display.enable_fbc ||
1126 !dev_priv->display.disable_fbc)
1127 return;
1128
1129 if (!crtc->fb)
1130 return;
1131
1132 intel_fb = to_intel_framebuffer(fb);
1133 obj_priv = intel_fb->obj->driver_private;
1134
1135 /*
1136 * If FBC is already on, we just have to verify that we can
1137 * keep it that way...
1138 * Need to disable if:
1139 * - changing FBC params (stride, fence, mode)
1140 * - new fb is too large to fit in compressed buffer
1141 * - going to an unsupported config (interlace, pixel multiply, etc.)
1142 */
1143 if (intel_fb->obj->size > dev_priv->cfb_size) {
1144 DRM_DEBUG_KMS("framebuffer too large, disabling "
1145 "compression\n");
1146 goto out_disable;
1147 }
1148 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1149 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1150 DRM_DEBUG_KMS("mode incompatible with compression, "
1151 "disabling\n");
1152 goto out_disable;
1153 }
1154 if ((mode->hdisplay > 2048) ||
1155 (mode->vdisplay > 1536)) {
1156 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1157 goto out_disable;
1158 }
1159 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1160 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1161 goto out_disable;
1162 }
1163 if (obj_priv->tiling_mode != I915_TILING_X) {
1164 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1165 goto out_disable;
1166 }
1167
1168 if (dev_priv->display.fbc_enabled(crtc)) {
1169 /* We can re-enable it in this case, but need to update pitch */
1170 if (fb->pitch > dev_priv->cfb_pitch)
1171 dev_priv->display.disable_fbc(dev);
1172 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1173 dev_priv->display.disable_fbc(dev);
1174 if (plane != dev_priv->cfb_plane)
1175 dev_priv->display.disable_fbc(dev);
1176 }
1177
1178 if (!dev_priv->display.fbc_enabled(crtc)) {
1179 /* Now try to turn it back on if possible */
1180 dev_priv->display.enable_fbc(crtc, 500);
1181 }
1182
1183 return;
1184
1185 out_disable:
1186 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1187 /* Multiple disables should be harmless */
1188 if (dev_priv->display.fbc_enabled(crtc))
1189 dev_priv->display.disable_fbc(dev);
1190 }
1191
1192 static int
1193 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1194 struct drm_framebuffer *old_fb)
1195 {
1196 struct drm_device *dev = crtc->dev;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 struct drm_i915_master_private *master_priv;
1199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1200 struct intel_framebuffer *intel_fb;
1201 struct drm_i915_gem_object *obj_priv;
1202 struct drm_gem_object *obj;
1203 int pipe = intel_crtc->pipe;
1204 int plane = intel_crtc->plane;
1205 unsigned long Start, Offset;
1206 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1207 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1208 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1209 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1210 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1211 u32 dspcntr, alignment;
1212 int ret;
1213
1214 /* no fb bound */
1215 if (!crtc->fb) {
1216 DRM_DEBUG_KMS("No FB bound\n");
1217 return 0;
1218 }
1219
1220 switch (plane) {
1221 case 0:
1222 case 1:
1223 break;
1224 default:
1225 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1226 return -EINVAL;
1227 }
1228
1229 intel_fb = to_intel_framebuffer(crtc->fb);
1230 obj = intel_fb->obj;
1231 obj_priv = obj->driver_private;
1232
1233 switch (obj_priv->tiling_mode) {
1234 case I915_TILING_NONE:
1235 alignment = 64 * 1024;
1236 break;
1237 case I915_TILING_X:
1238 /* pin() will align the object as required by fence */
1239 alignment = 0;
1240 break;
1241 case I915_TILING_Y:
1242 /* FIXME: Is this true? */
1243 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1244 return -EINVAL;
1245 default:
1246 BUG();
1247 }
1248
1249 mutex_lock(&dev->struct_mutex);
1250 ret = i915_gem_object_pin(obj, alignment);
1251 if (ret != 0) {
1252 mutex_unlock(&dev->struct_mutex);
1253 return ret;
1254 }
1255
1256 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1257 if (ret != 0) {
1258 i915_gem_object_unpin(obj);
1259 mutex_unlock(&dev->struct_mutex);
1260 return ret;
1261 }
1262
1263 /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1264 * whereas 965+ only requires a fence if using framebuffer compression.
1265 * For simplicity, we always install a fence as the cost is not that onerous.
1266 */
1267 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1268 obj_priv->tiling_mode != I915_TILING_NONE) {
1269 ret = i915_gem_object_get_fence_reg(obj);
1270 if (ret != 0) {
1271 i915_gem_object_unpin(obj);
1272 mutex_unlock(&dev->struct_mutex);
1273 return ret;
1274 }
1275 }
1276
1277 dspcntr = I915_READ(dspcntr_reg);
1278 /* Mask out pixel format bits in case we change it */
1279 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1280 switch (crtc->fb->bits_per_pixel) {
1281 case 8:
1282 dspcntr |= DISPPLANE_8BPP;
1283 break;
1284 case 16:
1285 if (crtc->fb->depth == 15)
1286 dspcntr |= DISPPLANE_15_16BPP;
1287 else
1288 dspcntr |= DISPPLANE_16BPP;
1289 break;
1290 case 24:
1291 case 32:
1292 if (crtc->fb->depth == 30)
1293 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1294 else
1295 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1296 break;
1297 default:
1298 DRM_ERROR("Unknown color depth\n");
1299 i915_gem_object_unpin(obj);
1300 mutex_unlock(&dev->struct_mutex);
1301 return -EINVAL;
1302 }
1303 if (IS_I965G(dev)) {
1304 if (obj_priv->tiling_mode != I915_TILING_NONE)
1305 dspcntr |= DISPPLANE_TILED;
1306 else
1307 dspcntr &= ~DISPPLANE_TILED;
1308 }
1309
1310 if (IS_IGDNG(dev))
1311 /* must disable */
1312 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1313
1314 I915_WRITE(dspcntr_reg, dspcntr);
1315
1316 Start = obj_priv->gtt_offset;
1317 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1318
1319 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1320 I915_WRITE(dspstride, crtc->fb->pitch);
1321 if (IS_I965G(dev)) {
1322 I915_WRITE(dspbase, Offset);
1323 I915_READ(dspbase);
1324 I915_WRITE(dspsurf, Start);
1325 I915_READ(dspsurf);
1326 I915_WRITE(dsptileoff, (y << 16) | x);
1327 } else {
1328 I915_WRITE(dspbase, Start + Offset);
1329 I915_READ(dspbase);
1330 }
1331
1332 if ((IS_I965G(dev) || plane == 0))
1333 intel_update_fbc(crtc, &crtc->mode);
1334
1335 intel_wait_for_vblank(dev);
1336
1337 if (old_fb) {
1338 intel_fb = to_intel_framebuffer(old_fb);
1339 obj_priv = intel_fb->obj->driver_private;
1340 i915_gem_object_unpin(intel_fb->obj);
1341 }
1342 intel_increase_pllclock(crtc, true);
1343
1344 mutex_unlock(&dev->struct_mutex);
1345
1346 if (!dev->primary->master)
1347 return 0;
1348
1349 master_priv = dev->primary->master->driver_priv;
1350 if (!master_priv->sarea_priv)
1351 return 0;
1352
1353 if (pipe) {
1354 master_priv->sarea_priv->pipeB_x = x;
1355 master_priv->sarea_priv->pipeB_y = y;
1356 } else {
1357 master_priv->sarea_priv->pipeA_x = x;
1358 master_priv->sarea_priv->pipeA_y = y;
1359 }
1360
1361 return 0;
1362 }
1363
1364 /* Disable the VGA plane that we never use */
1365 static void i915_disable_vga (struct drm_device *dev)
1366 {
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 u8 sr1;
1369 u32 vga_reg;
1370
1371 if (IS_IGDNG(dev))
1372 vga_reg = CPU_VGACNTRL;
1373 else
1374 vga_reg = VGACNTRL;
1375
1376 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1377 return;
1378
1379 I915_WRITE8(VGA_SR_INDEX, 1);
1380 sr1 = I915_READ8(VGA_SR_DATA);
1381 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1382 udelay(100);
1383
1384 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1385 }
1386
1387 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1388 {
1389 struct drm_device *dev = crtc->dev;
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 u32 dpa_ctl;
1392
1393 DRM_DEBUG_KMS("\n");
1394 dpa_ctl = I915_READ(DP_A);
1395 dpa_ctl &= ~DP_PLL_ENABLE;
1396 I915_WRITE(DP_A, dpa_ctl);
1397 }
1398
1399 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1400 {
1401 struct drm_device *dev = crtc->dev;
1402 struct drm_i915_private *dev_priv = dev->dev_private;
1403 u32 dpa_ctl;
1404
1405 dpa_ctl = I915_READ(DP_A);
1406 dpa_ctl |= DP_PLL_ENABLE;
1407 I915_WRITE(DP_A, dpa_ctl);
1408 udelay(200);
1409 }
1410
1411
1412 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1413 {
1414 struct drm_device *dev = crtc->dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 u32 dpa_ctl;
1417
1418 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1419 dpa_ctl = I915_READ(DP_A);
1420 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1421
1422 if (clock < 200000) {
1423 u32 temp;
1424 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1425 /* workaround for 160Mhz:
1426 1) program 0x4600c bits 15:0 = 0x8124
1427 2) program 0x46010 bit 0 = 1
1428 3) program 0x46034 bit 24 = 1
1429 4) program 0x64000 bit 14 = 1
1430 */
1431 temp = I915_READ(0x4600c);
1432 temp &= 0xffff0000;
1433 I915_WRITE(0x4600c, temp | 0x8124);
1434
1435 temp = I915_READ(0x46010);
1436 I915_WRITE(0x46010, temp | 1);
1437
1438 temp = I915_READ(0x46034);
1439 I915_WRITE(0x46034, temp | (1 << 24));
1440 } else {
1441 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1442 }
1443 I915_WRITE(DP_A, dpa_ctl);
1444
1445 udelay(500);
1446 }
1447
1448 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1449 {
1450 struct drm_device *dev = crtc->dev;
1451 struct drm_i915_private *dev_priv = dev->dev_private;
1452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1453 int pipe = intel_crtc->pipe;
1454 int plane = intel_crtc->plane;
1455 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1456 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1457 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1458 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1459 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1460 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1461 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1462 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1463 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1464 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1465 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1466 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1467 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1468 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1469 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1470 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1471 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1472 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1473 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1474 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1475 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1476 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1477 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1478 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1479 u32 temp;
1480 int tries = 5, j, n;
1481
1482 /* XXX: When our outputs are all unaware of DPMS modes other than off
1483 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1484 */
1485 switch (mode) {
1486 case DRM_MODE_DPMS_ON:
1487 case DRM_MODE_DPMS_STANDBY:
1488 case DRM_MODE_DPMS_SUSPEND:
1489 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1490 if (HAS_eDP) {
1491 /* enable eDP PLL */
1492 igdng_enable_pll_edp(crtc);
1493 } else {
1494 /* enable PCH DPLL */
1495 temp = I915_READ(pch_dpll_reg);
1496 if ((temp & DPLL_VCO_ENABLE) == 0) {
1497 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1498 I915_READ(pch_dpll_reg);
1499 }
1500
1501 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1502 temp = I915_READ(fdi_rx_reg);
1503 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1504 FDI_SEL_PCDCLK |
1505 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1506 I915_READ(fdi_rx_reg);
1507 udelay(200);
1508
1509 /* Enable CPU FDI TX PLL, always on for IGDNG */
1510 temp = I915_READ(fdi_tx_reg);
1511 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1512 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1513 I915_READ(fdi_tx_reg);
1514 udelay(100);
1515 }
1516 }
1517
1518 /* Enable panel fitting for LVDS */
1519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1520 temp = I915_READ(pf_ctl_reg);
1521 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1522
1523 /* currently full aspect */
1524 I915_WRITE(pf_win_pos, 0);
1525
1526 I915_WRITE(pf_win_size,
1527 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1528 (dev_priv->panel_fixed_mode->vdisplay));
1529 }
1530
1531 /* Enable CPU pipe */
1532 temp = I915_READ(pipeconf_reg);
1533 if ((temp & PIPEACONF_ENABLE) == 0) {
1534 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1535 I915_READ(pipeconf_reg);
1536 udelay(100);
1537 }
1538
1539 /* configure and enable CPU plane */
1540 temp = I915_READ(dspcntr_reg);
1541 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1542 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1543 /* Flush the plane changes */
1544 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1545 }
1546
1547 if (!HAS_eDP) {
1548 /* enable CPU FDI TX and PCH FDI RX */
1549 temp = I915_READ(fdi_tx_reg);
1550 temp |= FDI_TX_ENABLE;
1551 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1552 temp &= ~FDI_LINK_TRAIN_NONE;
1553 temp |= FDI_LINK_TRAIN_PATTERN_1;
1554 I915_WRITE(fdi_tx_reg, temp);
1555 I915_READ(fdi_tx_reg);
1556
1557 temp = I915_READ(fdi_rx_reg);
1558 temp &= ~FDI_LINK_TRAIN_NONE;
1559 temp |= FDI_LINK_TRAIN_PATTERN_1;
1560 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1561 I915_READ(fdi_rx_reg);
1562
1563 udelay(150);
1564
1565 /* Train FDI. */
1566 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1567 for train result */
1568 temp = I915_READ(fdi_rx_imr_reg);
1569 temp &= ~FDI_RX_SYMBOL_LOCK;
1570 temp &= ~FDI_RX_BIT_LOCK;
1571 I915_WRITE(fdi_rx_imr_reg, temp);
1572 I915_READ(fdi_rx_imr_reg);
1573 udelay(150);
1574
1575 temp = I915_READ(fdi_rx_iir_reg);
1576 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1577
1578 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1579 for (j = 0; j < tries; j++) {
1580 temp = I915_READ(fdi_rx_iir_reg);
1581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1582 temp);
1583 if (temp & FDI_RX_BIT_LOCK)
1584 break;
1585 udelay(200);
1586 }
1587 if (j != tries)
1588 I915_WRITE(fdi_rx_iir_reg,
1589 temp | FDI_RX_BIT_LOCK);
1590 else
1591 DRM_DEBUG_KMS("train 1 fail\n");
1592 } else {
1593 I915_WRITE(fdi_rx_iir_reg,
1594 temp | FDI_RX_BIT_LOCK);
1595 DRM_DEBUG_KMS("train 1 ok 2!\n");
1596 }
1597 temp = I915_READ(fdi_tx_reg);
1598 temp &= ~FDI_LINK_TRAIN_NONE;
1599 temp |= FDI_LINK_TRAIN_PATTERN_2;
1600 I915_WRITE(fdi_tx_reg, temp);
1601
1602 temp = I915_READ(fdi_rx_reg);
1603 temp &= ~FDI_LINK_TRAIN_NONE;
1604 temp |= FDI_LINK_TRAIN_PATTERN_2;
1605 I915_WRITE(fdi_rx_reg, temp);
1606
1607 udelay(150);
1608
1609 temp = I915_READ(fdi_rx_iir_reg);
1610 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1611
1612 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1613 for (j = 0; j < tries; j++) {
1614 temp = I915_READ(fdi_rx_iir_reg);
1615 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1616 temp);
1617 if (temp & FDI_RX_SYMBOL_LOCK)
1618 break;
1619 udelay(200);
1620 }
1621 if (j != tries) {
1622 I915_WRITE(fdi_rx_iir_reg,
1623 temp | FDI_RX_SYMBOL_LOCK);
1624 DRM_DEBUG_KMS("train 2 ok 1!\n");
1625 } else
1626 DRM_DEBUG_KMS("train 2 fail\n");
1627 } else {
1628 I915_WRITE(fdi_rx_iir_reg,
1629 temp | FDI_RX_SYMBOL_LOCK);
1630 DRM_DEBUG_KMS("train 2 ok 2!\n");
1631 }
1632 DRM_DEBUG_KMS("train done\n");
1633
1634 /* set transcoder timing */
1635 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1636 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1637 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1638
1639 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1640 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1641 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1642
1643 /* enable PCH transcoder */
1644 temp = I915_READ(transconf_reg);
1645 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1646 I915_READ(transconf_reg);
1647
1648 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1649 ;
1650
1651 /* enable normal */
1652
1653 temp = I915_READ(fdi_tx_reg);
1654 temp &= ~FDI_LINK_TRAIN_NONE;
1655 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1656 FDI_TX_ENHANCE_FRAME_ENABLE);
1657 I915_READ(fdi_tx_reg);
1658
1659 temp = I915_READ(fdi_rx_reg);
1660 temp &= ~FDI_LINK_TRAIN_NONE;
1661 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1662 FDI_RX_ENHANCE_FRAME_ENABLE);
1663 I915_READ(fdi_rx_reg);
1664
1665 /* wait one idle pattern time */
1666 udelay(100);
1667
1668 }
1669
1670 intel_crtc_load_lut(crtc);
1671
1672 break;
1673 case DRM_MODE_DPMS_OFF:
1674 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1675
1676 i915_disable_vga(dev);
1677
1678 /* Disable display plane */
1679 temp = I915_READ(dspcntr_reg);
1680 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1681 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1682 /* Flush the plane changes */
1683 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1684 I915_READ(dspbase_reg);
1685 }
1686
1687 /* disable cpu pipe, disable after all planes disabled */
1688 temp = I915_READ(pipeconf_reg);
1689 if ((temp & PIPEACONF_ENABLE) != 0) {
1690 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1691 I915_READ(pipeconf_reg);
1692 n = 0;
1693 /* wait for cpu pipe off, pipe state */
1694 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1695 n++;
1696 if (n < 60) {
1697 udelay(500);
1698 continue;
1699 } else {
1700 DRM_DEBUG_KMS("pipe %d off delay\n",
1701 pipe);
1702 break;
1703 }
1704 }
1705 } else
1706 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1707
1708 if (HAS_eDP) {
1709 igdng_disable_pll_edp(crtc);
1710 }
1711
1712 /* disable CPU FDI tx and PCH FDI rx */
1713 temp = I915_READ(fdi_tx_reg);
1714 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1715 I915_READ(fdi_tx_reg);
1716
1717 temp = I915_READ(fdi_rx_reg);
1718 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1719 I915_READ(fdi_rx_reg);
1720
1721 udelay(100);
1722
1723 /* still set train pattern 1 */
1724 temp = I915_READ(fdi_tx_reg);
1725 temp &= ~FDI_LINK_TRAIN_NONE;
1726 temp |= FDI_LINK_TRAIN_PATTERN_1;
1727 I915_WRITE(fdi_tx_reg, temp);
1728
1729 temp = I915_READ(fdi_rx_reg);
1730 temp &= ~FDI_LINK_TRAIN_NONE;
1731 temp |= FDI_LINK_TRAIN_PATTERN_1;
1732 I915_WRITE(fdi_rx_reg, temp);
1733
1734 udelay(100);
1735
1736 /* disable PCH transcoder */
1737 temp = I915_READ(transconf_reg);
1738 if ((temp & TRANS_ENABLE) != 0) {
1739 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1740 I915_READ(transconf_reg);
1741 n = 0;
1742 /* wait for PCH transcoder off, transcoder state */
1743 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1744 n++;
1745 if (n < 60) {
1746 udelay(500);
1747 continue;
1748 } else {
1749 DRM_DEBUG_KMS("transcoder %d off "
1750 "delay\n", pipe);
1751 break;
1752 }
1753 }
1754 }
1755
1756 /* disable PCH DPLL */
1757 temp = I915_READ(pch_dpll_reg);
1758 if ((temp & DPLL_VCO_ENABLE) != 0) {
1759 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1760 I915_READ(pch_dpll_reg);
1761 }
1762
1763 temp = I915_READ(fdi_rx_reg);
1764 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1765 temp &= ~FDI_SEL_PCDCLK;
1766 temp &= ~FDI_RX_PLL_ENABLE;
1767 I915_WRITE(fdi_rx_reg, temp);
1768 I915_READ(fdi_rx_reg);
1769 }
1770
1771 /* Disable CPU FDI TX PLL */
1772 temp = I915_READ(fdi_tx_reg);
1773 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1774 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1775 I915_READ(fdi_tx_reg);
1776 udelay(100);
1777 }
1778
1779 /* Disable PF */
1780 temp = I915_READ(pf_ctl_reg);
1781 if ((temp & PF_ENABLE) != 0) {
1782 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1783 I915_READ(pf_ctl_reg);
1784 }
1785 I915_WRITE(pf_win_size, 0);
1786
1787 /* Wait for the clocks to turn off. */
1788 udelay(150);
1789 break;
1790 }
1791 }
1792
1793 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1794 {
1795 struct intel_overlay *overlay;
1796 int ret;
1797
1798 if (!enable && intel_crtc->overlay) {
1799 overlay = intel_crtc->overlay;
1800 mutex_lock(&overlay->dev->struct_mutex);
1801 for (;;) {
1802 ret = intel_overlay_switch_off(overlay);
1803 if (ret == 0)
1804 break;
1805
1806 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1807 if (ret != 0) {
1808 /* overlay doesn't react anymore. Usually
1809 * results in a black screen and an unkillable
1810 * X server. */
1811 BUG();
1812 overlay->hw_wedged = HW_WEDGED;
1813 break;
1814 }
1815 }
1816 mutex_unlock(&overlay->dev->struct_mutex);
1817 }
1818 /* Let userspace switch the overlay on again. In most cases userspace
1819 * has to recompute where to put it anyway. */
1820
1821 return;
1822 }
1823
1824 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1825 {
1826 struct drm_device *dev = crtc->dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1829 int pipe = intel_crtc->pipe;
1830 int plane = intel_crtc->plane;
1831 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1832 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1833 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1834 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1835 u32 temp;
1836
1837 /* XXX: When our outputs are all unaware of DPMS modes other than off
1838 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1839 */
1840 switch (mode) {
1841 case DRM_MODE_DPMS_ON:
1842 case DRM_MODE_DPMS_STANDBY:
1843 case DRM_MODE_DPMS_SUSPEND:
1844 intel_update_watermarks(dev);
1845
1846 /* Enable the DPLL */
1847 temp = I915_READ(dpll_reg);
1848 if ((temp & DPLL_VCO_ENABLE) == 0) {
1849 I915_WRITE(dpll_reg, temp);
1850 I915_READ(dpll_reg);
1851 /* Wait for the clocks to stabilize. */
1852 udelay(150);
1853 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1854 I915_READ(dpll_reg);
1855 /* Wait for the clocks to stabilize. */
1856 udelay(150);
1857 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1858 I915_READ(dpll_reg);
1859 /* Wait for the clocks to stabilize. */
1860 udelay(150);
1861 }
1862
1863 /* Enable the pipe */
1864 temp = I915_READ(pipeconf_reg);
1865 if ((temp & PIPEACONF_ENABLE) == 0)
1866 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1867
1868 /* Enable the plane */
1869 temp = I915_READ(dspcntr_reg);
1870 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1871 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1872 /* Flush the plane changes */
1873 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1874 }
1875
1876 intel_crtc_load_lut(crtc);
1877
1878 if ((IS_I965G(dev) || plane == 0))
1879 intel_update_fbc(crtc, &crtc->mode);
1880
1881 /* Give the overlay scaler a chance to enable if it's on this pipe */
1882 intel_crtc_dpms_overlay(intel_crtc, true);
1883 break;
1884 case DRM_MODE_DPMS_OFF:
1885 intel_update_watermarks(dev);
1886
1887 /* Give the overlay scaler a chance to disable if it's on this pipe */
1888 intel_crtc_dpms_overlay(intel_crtc, false);
1889
1890 if (dev_priv->cfb_plane == plane &&
1891 dev_priv->display.disable_fbc)
1892 dev_priv->display.disable_fbc(dev);
1893
1894 /* Disable the VGA plane that we never use */
1895 i915_disable_vga(dev);
1896
1897 /* Disable display plane */
1898 temp = I915_READ(dspcntr_reg);
1899 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1900 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1901 /* Flush the plane changes */
1902 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1903 I915_READ(dspbase_reg);
1904 }
1905
1906 if (!IS_I9XX(dev)) {
1907 /* Wait for vblank for the disable to take effect */
1908 intel_wait_for_vblank(dev);
1909 }
1910
1911 /* Next, disable display pipes */
1912 temp = I915_READ(pipeconf_reg);
1913 if ((temp & PIPEACONF_ENABLE) != 0) {
1914 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1915 I915_READ(pipeconf_reg);
1916 }
1917
1918 /* Wait for vblank for the disable to take effect. */
1919 intel_wait_for_vblank(dev);
1920
1921 temp = I915_READ(dpll_reg);
1922 if ((temp & DPLL_VCO_ENABLE) != 0) {
1923 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1924 I915_READ(dpll_reg);
1925 }
1926
1927 /* Wait for the clocks to turn off. */
1928 udelay(150);
1929 break;
1930 }
1931 }
1932
1933 /**
1934 * Sets the power management mode of the pipe and plane.
1935 *
1936 * This code should probably grow support for turning the cursor off and back
1937 * on appropriately at the same time as we're turning the pipe off/on.
1938 */
1939 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1940 {
1941 struct drm_device *dev = crtc->dev;
1942 struct drm_i915_private *dev_priv = dev->dev_private;
1943 struct drm_i915_master_private *master_priv;
1944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1945 int pipe = intel_crtc->pipe;
1946 bool enabled;
1947
1948 dev_priv->display.dpms(crtc, mode);
1949
1950 intel_crtc->dpms_mode = mode;
1951
1952 if (!dev->primary->master)
1953 return;
1954
1955 master_priv = dev->primary->master->driver_priv;
1956 if (!master_priv->sarea_priv)
1957 return;
1958
1959 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1960
1961 switch (pipe) {
1962 case 0:
1963 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1964 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1965 break;
1966 case 1:
1967 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1968 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1969 break;
1970 default:
1971 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1972 break;
1973 }
1974 }
1975
1976 static void intel_crtc_prepare (struct drm_crtc *crtc)
1977 {
1978 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1979 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1980 }
1981
1982 static void intel_crtc_commit (struct drm_crtc *crtc)
1983 {
1984 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1985 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1986 }
1987
1988 void intel_encoder_prepare (struct drm_encoder *encoder)
1989 {
1990 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1991 /* lvds has its own version of prepare see intel_lvds_prepare */
1992 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1993 }
1994
1995 void intel_encoder_commit (struct drm_encoder *encoder)
1996 {
1997 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1998 /* lvds has its own version of commit see intel_lvds_commit */
1999 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2000 }
2001
2002 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2003 struct drm_display_mode *mode,
2004 struct drm_display_mode *adjusted_mode)
2005 {
2006 struct drm_device *dev = crtc->dev;
2007 if (IS_IGDNG(dev)) {
2008 /* FDI link clock is fixed at 2.7G */
2009 if (mode->clock * 3 > 27000 * 4)
2010 return MODE_CLOCK_HIGH;
2011 }
2012 return true;
2013 }
2014
2015 static int i945_get_display_clock_speed(struct drm_device *dev)
2016 {
2017 return 400000;
2018 }
2019
2020 static int i915_get_display_clock_speed(struct drm_device *dev)
2021 {
2022 return 333000;
2023 }
2024
2025 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2026 {
2027 return 200000;
2028 }
2029
2030 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2031 {
2032 u16 gcfgc = 0;
2033
2034 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2035
2036 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2037 return 133000;
2038 else {
2039 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2040 case GC_DISPLAY_CLOCK_333_MHZ:
2041 return 333000;
2042 default:
2043 case GC_DISPLAY_CLOCK_190_200_MHZ:
2044 return 190000;
2045 }
2046 }
2047 }
2048
2049 static int i865_get_display_clock_speed(struct drm_device *dev)
2050 {
2051 return 266000;
2052 }
2053
2054 static int i855_get_display_clock_speed(struct drm_device *dev)
2055 {
2056 u16 hpllcc = 0;
2057 /* Assume that the hardware is in the high speed state. This
2058 * should be the default.
2059 */
2060 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2061 case GC_CLOCK_133_200:
2062 case GC_CLOCK_100_200:
2063 return 200000;
2064 case GC_CLOCK_166_250:
2065 return 250000;
2066 case GC_CLOCK_100_133:
2067 return 133000;
2068 }
2069
2070 /* Shouldn't happen */
2071 return 0;
2072 }
2073
2074 static int i830_get_display_clock_speed(struct drm_device *dev)
2075 {
2076 return 133000;
2077 }
2078
2079 /**
2080 * Return the pipe currently connected to the panel fitter,
2081 * or -1 if the panel fitter is not present or not in use
2082 */
2083 int intel_panel_fitter_pipe (struct drm_device *dev)
2084 {
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 u32 pfit_control;
2087
2088 /* i830 doesn't have a panel fitter */
2089 if (IS_I830(dev))
2090 return -1;
2091
2092 pfit_control = I915_READ(PFIT_CONTROL);
2093
2094 /* See if the panel fitter is in use */
2095 if ((pfit_control & PFIT_ENABLE) == 0)
2096 return -1;
2097
2098 /* 965 can place panel fitter on either pipe */
2099 if (IS_I965G(dev))
2100 return (pfit_control >> 29) & 0x3;
2101
2102 /* older chips can only use pipe 1 */
2103 return 1;
2104 }
2105
2106 struct fdi_m_n {
2107 u32 tu;
2108 u32 gmch_m;
2109 u32 gmch_n;
2110 u32 link_m;
2111 u32 link_n;
2112 };
2113
2114 static void
2115 fdi_reduce_ratio(u32 *num, u32 *den)
2116 {
2117 while (*num > 0xffffff || *den > 0xffffff) {
2118 *num >>= 1;
2119 *den >>= 1;
2120 }
2121 }
2122
2123 #define DATA_N 0x800000
2124 #define LINK_N 0x80000
2125
2126 static void
2127 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2128 int pixel_clock, int link_clock,
2129 struct fdi_m_n *m_n)
2130 {
2131 u64 temp;
2132
2133 m_n->tu = 64; /* default size */
2134
2135 temp = (u64) DATA_N * pixel_clock;
2136 temp = div_u64(temp, link_clock);
2137 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2138 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2139 m_n->gmch_n = DATA_N;
2140 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2141
2142 temp = (u64) LINK_N * pixel_clock;
2143 m_n->link_m = div_u64(temp, link_clock);
2144 m_n->link_n = LINK_N;
2145 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2146 }
2147
2148
2149 struct intel_watermark_params {
2150 unsigned long fifo_size;
2151 unsigned long max_wm;
2152 unsigned long default_wm;
2153 unsigned long guard_size;
2154 unsigned long cacheline_size;
2155 };
2156
2157 /* IGD has different values for various configs */
2158 static struct intel_watermark_params igd_display_wm = {
2159 IGD_DISPLAY_FIFO,
2160 IGD_MAX_WM,
2161 IGD_DFT_WM,
2162 IGD_GUARD_WM,
2163 IGD_FIFO_LINE_SIZE
2164 };
2165 static struct intel_watermark_params igd_display_hplloff_wm = {
2166 IGD_DISPLAY_FIFO,
2167 IGD_MAX_WM,
2168 IGD_DFT_HPLLOFF_WM,
2169 IGD_GUARD_WM,
2170 IGD_FIFO_LINE_SIZE
2171 };
2172 static struct intel_watermark_params igd_cursor_wm = {
2173 IGD_CURSOR_FIFO,
2174 IGD_CURSOR_MAX_WM,
2175 IGD_CURSOR_DFT_WM,
2176 IGD_CURSOR_GUARD_WM,
2177 IGD_FIFO_LINE_SIZE,
2178 };
2179 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2180 IGD_CURSOR_FIFO,
2181 IGD_CURSOR_MAX_WM,
2182 IGD_CURSOR_DFT_WM,
2183 IGD_CURSOR_GUARD_WM,
2184 IGD_FIFO_LINE_SIZE
2185 };
2186 static struct intel_watermark_params g4x_wm_info = {
2187 G4X_FIFO_SIZE,
2188 G4X_MAX_WM,
2189 G4X_MAX_WM,
2190 2,
2191 G4X_FIFO_LINE_SIZE,
2192 };
2193 static struct intel_watermark_params i945_wm_info = {
2194 I945_FIFO_SIZE,
2195 I915_MAX_WM,
2196 1,
2197 2,
2198 I915_FIFO_LINE_SIZE
2199 };
2200 static struct intel_watermark_params i915_wm_info = {
2201 I915_FIFO_SIZE,
2202 I915_MAX_WM,
2203 1,
2204 2,
2205 I915_FIFO_LINE_SIZE
2206 };
2207 static struct intel_watermark_params i855_wm_info = {
2208 I855GM_FIFO_SIZE,
2209 I915_MAX_WM,
2210 1,
2211 2,
2212 I830_FIFO_LINE_SIZE
2213 };
2214 static struct intel_watermark_params i830_wm_info = {
2215 I830_FIFO_SIZE,
2216 I915_MAX_WM,
2217 1,
2218 2,
2219 I830_FIFO_LINE_SIZE
2220 };
2221
2222 /**
2223 * intel_calculate_wm - calculate watermark level
2224 * @clock_in_khz: pixel clock
2225 * @wm: chip FIFO params
2226 * @pixel_size: display pixel size
2227 * @latency_ns: memory latency for the platform
2228 *
2229 * Calculate the watermark level (the level at which the display plane will
2230 * start fetching from memory again). Each chip has a different display
2231 * FIFO size and allocation, so the caller needs to figure that out and pass
2232 * in the correct intel_watermark_params structure.
2233 *
2234 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2235 * on the pixel size. When it reaches the watermark level, it'll start
2236 * fetching FIFO line sized based chunks from memory until the FIFO fills
2237 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2238 * will occur, and a display engine hang could result.
2239 */
2240 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2241 struct intel_watermark_params *wm,
2242 int pixel_size,
2243 unsigned long latency_ns)
2244 {
2245 long entries_required, wm_size;
2246
2247 /*
2248 * Note: we need to make sure we don't overflow for various clock &
2249 * latency values.
2250 * clocks go from a few thousand to several hundred thousand.
2251 * latency is usually a few thousand
2252 */
2253 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2254 1000;
2255 entries_required /= wm->cacheline_size;
2256
2257 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2258
2259 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2260
2261 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2262
2263 /* Don't promote wm_size to unsigned... */
2264 if (wm_size > (long)wm->max_wm)
2265 wm_size = wm->max_wm;
2266 if (wm_size <= 0)
2267 wm_size = wm->default_wm;
2268 return wm_size;
2269 }
2270
2271 struct cxsr_latency {
2272 int is_desktop;
2273 unsigned long fsb_freq;
2274 unsigned long mem_freq;
2275 unsigned long display_sr;
2276 unsigned long display_hpll_disable;
2277 unsigned long cursor_sr;
2278 unsigned long cursor_hpll_disable;
2279 };
2280
2281 static struct cxsr_latency cxsr_latency_table[] = {
2282 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2283 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2284 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2285
2286 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2287 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2288 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2289
2290 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2291 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2292 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2293
2294 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2295 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2296 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2297
2298 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2299 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2300 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2301
2302 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2303 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2304 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2305 };
2306
2307 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2308 int mem)
2309 {
2310 int i;
2311 struct cxsr_latency *latency;
2312
2313 if (fsb == 0 || mem == 0)
2314 return NULL;
2315
2316 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2317 latency = &cxsr_latency_table[i];
2318 if (is_desktop == latency->is_desktop &&
2319 fsb == latency->fsb_freq && mem == latency->mem_freq)
2320 return latency;
2321 }
2322
2323 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2324
2325 return NULL;
2326 }
2327
2328 static void igd_disable_cxsr(struct drm_device *dev)
2329 {
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 u32 reg;
2332
2333 /* deactivate cxsr */
2334 reg = I915_READ(DSPFW3);
2335 reg &= ~(IGD_SELF_REFRESH_EN);
2336 I915_WRITE(DSPFW3, reg);
2337 DRM_INFO("Big FIFO is disabled\n");
2338 }
2339
2340 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2341 int pixel_size)
2342 {
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 u32 reg;
2345 unsigned long wm;
2346 struct cxsr_latency *latency;
2347
2348 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2349 dev_priv->mem_freq);
2350 if (!latency) {
2351 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2352 igd_disable_cxsr(dev);
2353 return;
2354 }
2355
2356 /* Display SR */
2357 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2358 latency->display_sr);
2359 reg = I915_READ(DSPFW1);
2360 reg &= 0x7fffff;
2361 reg |= wm << 23;
2362 I915_WRITE(DSPFW1, reg);
2363 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2364
2365 /* cursor SR */
2366 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2367 latency->cursor_sr);
2368 reg = I915_READ(DSPFW3);
2369 reg &= ~(0x3f << 24);
2370 reg |= (wm & 0x3f) << 24;
2371 I915_WRITE(DSPFW3, reg);
2372
2373 /* Display HPLL off SR */
2374 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2375 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2376 reg = I915_READ(DSPFW3);
2377 reg &= 0xfffffe00;
2378 reg |= wm & 0x1ff;
2379 I915_WRITE(DSPFW3, reg);
2380
2381 /* cursor HPLL off SR */
2382 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2383 latency->cursor_hpll_disable);
2384 reg = I915_READ(DSPFW3);
2385 reg &= ~(0x3f << 16);
2386 reg |= (wm & 0x3f) << 16;
2387 I915_WRITE(DSPFW3, reg);
2388 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2389
2390 /* activate cxsr */
2391 reg = I915_READ(DSPFW3);
2392 reg |= IGD_SELF_REFRESH_EN;
2393 I915_WRITE(DSPFW3, reg);
2394
2395 DRM_INFO("Big FIFO is enabled\n");
2396
2397 return;
2398 }
2399
2400 /*
2401 * Latency for FIFO fetches is dependent on several factors:
2402 * - memory configuration (speed, channels)
2403 * - chipset
2404 * - current MCH state
2405 * It can be fairly high in some situations, so here we assume a fairly
2406 * pessimal value. It's a tradeoff between extra memory fetches (if we
2407 * set this value too high, the FIFO will fetch frequently to stay full)
2408 * and power consumption (set it too low to save power and we might see
2409 * FIFO underruns and display "flicker").
2410 *
2411 * A value of 5us seems to be a good balance; safe for very low end
2412 * platforms but not overly aggressive on lower latency configs.
2413 */
2414 const static int latency_ns = 5000;
2415
2416 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2417 {
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 uint32_t dsparb = I915_READ(DSPARB);
2420 int size;
2421
2422 if (plane == 0)
2423 size = dsparb & 0x7f;
2424 else
2425 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2426 (dsparb & 0x7f);
2427
2428 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2429 plane ? "B" : "A", size);
2430
2431 return size;
2432 }
2433
2434 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2435 {
2436 struct drm_i915_private *dev_priv = dev->dev_private;
2437 uint32_t dsparb = I915_READ(DSPARB);
2438 int size;
2439
2440 if (plane == 0)
2441 size = dsparb & 0x1ff;
2442 else
2443 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2444 (dsparb & 0x1ff);
2445 size >>= 1; /* Convert to cachelines */
2446
2447 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2448 plane ? "B" : "A", size);
2449
2450 return size;
2451 }
2452
2453 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2454 {
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 uint32_t dsparb = I915_READ(DSPARB);
2457 int size;
2458
2459 size = dsparb & 0x7f;
2460 size >>= 2; /* Convert to cachelines */
2461
2462 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2463 plane ? "B" : "A",
2464 size);
2465
2466 return size;
2467 }
2468
2469 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2470 {
2471 struct drm_i915_private *dev_priv = dev->dev_private;
2472 uint32_t dsparb = I915_READ(DSPARB);
2473 int size;
2474
2475 size = dsparb & 0x7f;
2476 size >>= 1; /* Convert to cachelines */
2477
2478 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2479 plane ? "B" : "A", size);
2480
2481 return size;
2482 }
2483
2484 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2485 int planeb_clock, int sr_hdisplay, int pixel_size)
2486 {
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2488 int total_size, cacheline_size;
2489 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2490 struct intel_watermark_params planea_params, planeb_params;
2491 unsigned long line_time_us;
2492 int sr_clock, sr_entries = 0, entries_required;
2493
2494 /* Create copies of the base settings for each pipe */
2495 planea_params = planeb_params = g4x_wm_info;
2496
2497 /* Grab a couple of global values before we overwrite them */
2498 total_size = planea_params.fifo_size;
2499 cacheline_size = planea_params.cacheline_size;
2500
2501 /*
2502 * Note: we need to make sure we don't overflow for various clock &
2503 * latency values.
2504 * clocks go from a few thousand to several hundred thousand.
2505 * latency is usually a few thousand
2506 */
2507 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2508 1000;
2509 entries_required /= G4X_FIFO_LINE_SIZE;
2510 planea_wm = entries_required + planea_params.guard_size;
2511
2512 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2513 1000;
2514 entries_required /= G4X_FIFO_LINE_SIZE;
2515 planeb_wm = entries_required + planeb_params.guard_size;
2516
2517 cursora_wm = cursorb_wm = 16;
2518 cursor_sr = 32;
2519
2520 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2521
2522 /* Calc sr entries for one plane configs */
2523 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2524 /* self-refresh has much higher latency */
2525 const static int sr_latency_ns = 12000;
2526
2527 sr_clock = planea_clock ? planea_clock : planeb_clock;
2528 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2529
2530 /* Use ns/us then divide to preserve precision */
2531 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2532 pixel_size * sr_hdisplay) / 1000;
2533 sr_entries = roundup(sr_entries / cacheline_size, 1);
2534 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2535 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2536 }
2537
2538 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2539 planea_wm, planeb_wm, sr_entries);
2540
2541 planea_wm &= 0x3f;
2542 planeb_wm &= 0x3f;
2543
2544 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2545 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2546 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2547 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2548 (cursora_wm << DSPFW_CURSORA_SHIFT));
2549 /* HPLL off in SR has some issues on G4x... disable it */
2550 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2551 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2552 }
2553
2554 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2555 int planeb_clock, int sr_hdisplay, int pixel_size)
2556 {
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 unsigned long line_time_us;
2559 int sr_clock, sr_entries, srwm = 1;
2560
2561 /* Calc sr entries for one plane configs */
2562 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2563 /* self-refresh has much higher latency */
2564 const static int sr_latency_ns = 12000;
2565
2566 sr_clock = planea_clock ? planea_clock : planeb_clock;
2567 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2568
2569 /* Use ns/us then divide to preserve precision */
2570 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2571 pixel_size * sr_hdisplay) / 1000;
2572 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2573 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2574 srwm = I945_FIFO_SIZE - sr_entries;
2575 if (srwm < 0)
2576 srwm = 1;
2577 srwm &= 0x3f;
2578 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2579 }
2580
2581 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2582 srwm);
2583
2584 /* 965 has limitations... */
2585 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2586 (8 << 0));
2587 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2588 }
2589
2590 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2591 int planeb_clock, int sr_hdisplay, int pixel_size)
2592 {
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2594 uint32_t fwater_lo;
2595 uint32_t fwater_hi;
2596 int total_size, cacheline_size, cwm, srwm = 1;
2597 int planea_wm, planeb_wm;
2598 struct intel_watermark_params planea_params, planeb_params;
2599 unsigned long line_time_us;
2600 int sr_clock, sr_entries = 0;
2601
2602 /* Create copies of the base settings for each pipe */
2603 if (IS_I965GM(dev) || IS_I945GM(dev))
2604 planea_params = planeb_params = i945_wm_info;
2605 else if (IS_I9XX(dev))
2606 planea_params = planeb_params = i915_wm_info;
2607 else
2608 planea_params = planeb_params = i855_wm_info;
2609
2610 /* Grab a couple of global values before we overwrite them */
2611 total_size = planea_params.fifo_size;
2612 cacheline_size = planea_params.cacheline_size;
2613
2614 /* Update per-plane FIFO sizes */
2615 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2616 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2617
2618 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2619 pixel_size, latency_ns);
2620 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2621 pixel_size, latency_ns);
2622 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2623
2624 /*
2625 * Overlay gets an aggressive default since video jitter is bad.
2626 */
2627 cwm = 2;
2628
2629 /* Calc sr entries for one plane configs */
2630 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2631 (!planea_clock || !planeb_clock)) {
2632 /* self-refresh has much higher latency */
2633 const static int sr_latency_ns = 6000;
2634
2635 sr_clock = planea_clock ? planea_clock : planeb_clock;
2636 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2637
2638 /* Use ns/us then divide to preserve precision */
2639 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2640 pixel_size * sr_hdisplay) / 1000;
2641 sr_entries = roundup(sr_entries / cacheline_size, 1);
2642 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2643 srwm = total_size - sr_entries;
2644 if (srwm < 0)
2645 srwm = 1;
2646 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2647 }
2648
2649 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2650 planea_wm, planeb_wm, cwm, srwm);
2651
2652 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2653 fwater_hi = (cwm & 0x1f);
2654
2655 /* Set request length to 8 cachelines per fetch */
2656 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2657 fwater_hi = fwater_hi | (1 << 8);
2658
2659 I915_WRITE(FW_BLC, fwater_lo);
2660 I915_WRITE(FW_BLC2, fwater_hi);
2661 }
2662
2663 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2664 int unused2, int pixel_size)
2665 {
2666 struct drm_i915_private *dev_priv = dev->dev_private;
2667 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2668 int planea_wm;
2669
2670 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2671
2672 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2673 pixel_size, latency_ns);
2674 fwater_lo |= (3<<8) | planea_wm;
2675
2676 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2677
2678 I915_WRITE(FW_BLC, fwater_lo);
2679 }
2680
2681 /**
2682 * intel_update_watermarks - update FIFO watermark values based on current modes
2683 *
2684 * Calculate watermark values for the various WM regs based on current mode
2685 * and plane configuration.
2686 *
2687 * There are several cases to deal with here:
2688 * - normal (i.e. non-self-refresh)
2689 * - self-refresh (SR) mode
2690 * - lines are large relative to FIFO size (buffer can hold up to 2)
2691 * - lines are small relative to FIFO size (buffer can hold more than 2
2692 * lines), so need to account for TLB latency
2693 *
2694 * The normal calculation is:
2695 * watermark = dotclock * bytes per pixel * latency
2696 * where latency is platform & configuration dependent (we assume pessimal
2697 * values here).
2698 *
2699 * The SR calculation is:
2700 * watermark = (trunc(latency/line time)+1) * surface width *
2701 * bytes per pixel
2702 * where
2703 * line time = htotal / dotclock
2704 * and latency is assumed to be high, as above.
2705 *
2706 * The final value programmed to the register should always be rounded up,
2707 * and include an extra 2 entries to account for clock crossings.
2708 *
2709 * We don't use the sprite, so we can ignore that. And on Crestline we have
2710 * to set the non-SR watermarks to 8.
2711 */
2712 static void intel_update_watermarks(struct drm_device *dev)
2713 {
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 struct drm_crtc *crtc;
2716 struct intel_crtc *intel_crtc;
2717 int sr_hdisplay = 0;
2718 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2719 int enabled = 0, pixel_size = 0;
2720
2721 if (!dev_priv->display.update_wm)
2722 return;
2723
2724 /* Get the clock config from both planes */
2725 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2726 intel_crtc = to_intel_crtc(crtc);
2727 if (crtc->enabled) {
2728 enabled++;
2729 if (intel_crtc->plane == 0) {
2730 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2731 intel_crtc->pipe, crtc->mode.clock);
2732 planea_clock = crtc->mode.clock;
2733 } else {
2734 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2735 intel_crtc->pipe, crtc->mode.clock);
2736 planeb_clock = crtc->mode.clock;
2737 }
2738 sr_hdisplay = crtc->mode.hdisplay;
2739 sr_clock = crtc->mode.clock;
2740 if (crtc->fb)
2741 pixel_size = crtc->fb->bits_per_pixel / 8;
2742 else
2743 pixel_size = 4; /* by default */
2744 }
2745 }
2746
2747 if (enabled <= 0)
2748 return;
2749
2750 /* Single plane configs can enable self refresh */
2751 if (enabled == 1 && IS_IGD(dev))
2752 igd_enable_cxsr(dev, sr_clock, pixel_size);
2753 else if (IS_IGD(dev))
2754 igd_disable_cxsr(dev);
2755
2756 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2757 sr_hdisplay, pixel_size);
2758 }
2759
2760 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2761 struct drm_display_mode *mode,
2762 struct drm_display_mode *adjusted_mode,
2763 int x, int y,
2764 struct drm_framebuffer *old_fb)
2765 {
2766 struct drm_device *dev = crtc->dev;
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769 int pipe = intel_crtc->pipe;
2770 int plane = intel_crtc->plane;
2771 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2772 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2773 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2774 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2775 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2776 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2777 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2778 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2779 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2780 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2781 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2782 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2783 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2784 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2785 int refclk, num_outputs = 0;
2786 intel_clock_t clock, reduced_clock;
2787 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2788 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2789 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2790 bool is_edp = false;
2791 struct drm_mode_config *mode_config = &dev->mode_config;
2792 struct drm_connector *connector;
2793 const intel_limit_t *limit;
2794 int ret;
2795 struct fdi_m_n m_n = {0};
2796 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2797 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2798 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2799 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2800 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2801 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2802 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2803 int lvds_reg = LVDS;
2804 u32 temp;
2805 int sdvo_pixel_multiply;
2806 int target_clock;
2807
2808 drm_vblank_pre_modeset(dev, pipe);
2809
2810 list_for_each_entry(connector, &mode_config->connector_list, head) {
2811 struct intel_output *intel_output = to_intel_output(connector);
2812
2813 if (!connector->encoder || connector->encoder->crtc != crtc)
2814 continue;
2815
2816 switch (intel_output->type) {
2817 case INTEL_OUTPUT_LVDS:
2818 is_lvds = true;
2819 break;
2820 case INTEL_OUTPUT_SDVO:
2821 case INTEL_OUTPUT_HDMI:
2822 is_sdvo = true;
2823 if (intel_output->needs_tv_clock)
2824 is_tv = true;
2825 break;
2826 case INTEL_OUTPUT_DVO:
2827 is_dvo = true;
2828 break;
2829 case INTEL_OUTPUT_TVOUT:
2830 is_tv = true;
2831 break;
2832 case INTEL_OUTPUT_ANALOG:
2833 is_crt = true;
2834 break;
2835 case INTEL_OUTPUT_DISPLAYPORT:
2836 is_dp = true;
2837 break;
2838 case INTEL_OUTPUT_EDP:
2839 is_edp = true;
2840 break;
2841 }
2842
2843 num_outputs++;
2844 }
2845
2846 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2847 refclk = dev_priv->lvds_ssc_freq * 1000;
2848 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2849 refclk / 1000);
2850 } else if (IS_I9XX(dev)) {
2851 refclk = 96000;
2852 if (IS_IGDNG(dev))
2853 refclk = 120000; /* 120Mhz refclk */
2854 } else {
2855 refclk = 48000;
2856 }
2857
2858
2859 /*
2860 * Returns a set of divisors for the desired target clock with the given
2861 * refclk, or FALSE. The returned values represent the clock equation:
2862 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2863 */
2864 limit = intel_limit(crtc);
2865 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2866 if (!ok) {
2867 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2868 drm_vblank_post_modeset(dev, pipe);
2869 return -EINVAL;
2870 }
2871
2872 if (is_lvds && limit->find_reduced_pll &&
2873 dev_priv->lvds_downclock_avail) {
2874 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2875 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2876 dev_priv->lvds_downclock,
2877 refclk,
2878 &reduced_clock);
2879 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2880 /*
2881 * If the different P is found, it means that we can't
2882 * switch the display clock by using the FP0/FP1.
2883 * In such case we will disable the LVDS downclock
2884 * feature.
2885 */
2886 DRM_DEBUG_KMS("Different P is found for "
2887 "LVDS clock/downclock\n");
2888 has_reduced_clock = 0;
2889 }
2890 }
2891 /* SDVO TV has fixed PLL values depend on its clock range,
2892 this mirrors vbios setting. */
2893 if (is_sdvo && is_tv) {
2894 if (adjusted_mode->clock >= 100000
2895 && adjusted_mode->clock < 140500) {
2896 clock.p1 = 2;
2897 clock.p2 = 10;
2898 clock.n = 3;
2899 clock.m1 = 16;
2900 clock.m2 = 8;
2901 } else if (adjusted_mode->clock >= 140500
2902 && adjusted_mode->clock <= 200000) {
2903 clock.p1 = 1;
2904 clock.p2 = 10;
2905 clock.n = 6;
2906 clock.m1 = 12;
2907 clock.m2 = 8;
2908 }
2909 }
2910
2911 /* FDI link */
2912 if (IS_IGDNG(dev)) {
2913 int lane, link_bw, bpp;
2914 /* eDP doesn't require FDI link, so just set DP M/N
2915 according to current link config */
2916 if (is_edp) {
2917 struct drm_connector *edp;
2918 target_clock = mode->clock;
2919 edp = intel_pipe_get_output(crtc);
2920 intel_edp_link_config(to_intel_output(edp),
2921 &lane, &link_bw);
2922 } else {
2923 /* DP over FDI requires target mode clock
2924 instead of link clock */
2925 if (is_dp)
2926 target_clock = mode->clock;
2927 else
2928 target_clock = adjusted_mode->clock;
2929 lane = 4;
2930 link_bw = 270000;
2931 }
2932
2933 /* determine panel color depth */
2934 temp = I915_READ(pipeconf_reg);
2935
2936 switch (temp & PIPE_BPC_MASK) {
2937 case PIPE_8BPC:
2938 bpp = 24;
2939 break;
2940 case PIPE_10BPC:
2941 bpp = 30;
2942 break;
2943 case PIPE_6BPC:
2944 bpp = 18;
2945 break;
2946 case PIPE_12BPC:
2947 bpp = 36;
2948 break;
2949 default:
2950 DRM_ERROR("unknown pipe bpc value\n");
2951 bpp = 24;
2952 }
2953
2954 igdng_compute_m_n(bpp, lane, target_clock,
2955 link_bw, &m_n);
2956 }
2957
2958 /* Ironlake: try to setup display ref clock before DPLL
2959 * enabling. This is only under driver's control after
2960 * PCH B stepping, previous chipset stepping should be
2961 * ignoring this setting.
2962 */
2963 if (IS_IGDNG(dev)) {
2964 temp = I915_READ(PCH_DREF_CONTROL);
2965 /* Always enable nonspread source */
2966 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2967 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2968 I915_WRITE(PCH_DREF_CONTROL, temp);
2969 POSTING_READ(PCH_DREF_CONTROL);
2970
2971 temp &= ~DREF_SSC_SOURCE_MASK;
2972 temp |= DREF_SSC_SOURCE_ENABLE;
2973 I915_WRITE(PCH_DREF_CONTROL, temp);
2974 POSTING_READ(PCH_DREF_CONTROL);
2975
2976 udelay(200);
2977
2978 if (is_edp) {
2979 if (dev_priv->lvds_use_ssc) {
2980 temp |= DREF_SSC1_ENABLE;
2981 I915_WRITE(PCH_DREF_CONTROL, temp);
2982 POSTING_READ(PCH_DREF_CONTROL);
2983
2984 udelay(200);
2985
2986 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2987 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2988 I915_WRITE(PCH_DREF_CONTROL, temp);
2989 POSTING_READ(PCH_DREF_CONTROL);
2990 } else {
2991 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2992 I915_WRITE(PCH_DREF_CONTROL, temp);
2993 POSTING_READ(PCH_DREF_CONTROL);
2994 }
2995 }
2996 }
2997
2998 if (IS_IGD(dev)) {
2999 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3000 if (has_reduced_clock)
3001 fp2 = (1 << reduced_clock.n) << 16 |
3002 reduced_clock.m1 << 8 | reduced_clock.m2;
3003 } else {
3004 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3005 if (has_reduced_clock)
3006 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3007 reduced_clock.m2;
3008 }
3009
3010 if (!IS_IGDNG(dev))
3011 dpll = DPLL_VGA_MODE_DIS;
3012
3013 if (IS_I9XX(dev)) {
3014 if (is_lvds)
3015 dpll |= DPLLB_MODE_LVDS;
3016 else
3017 dpll |= DPLLB_MODE_DAC_SERIAL;
3018 if (is_sdvo) {
3019 dpll |= DPLL_DVO_HIGH_SPEED;
3020 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3021 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3022 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3023 else if (IS_IGDNG(dev))
3024 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3025 }
3026 if (is_dp)
3027 dpll |= DPLL_DVO_HIGH_SPEED;
3028
3029 /* compute bitmask from p1 value */
3030 if (IS_IGD(dev))
3031 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
3032 else {
3033 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3034 /* also FPA1 */
3035 if (IS_IGDNG(dev))
3036 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3037 if (IS_G4X(dev) && has_reduced_clock)
3038 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3039 }
3040 switch (clock.p2) {
3041 case 5:
3042 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3043 break;
3044 case 7:
3045 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3046 break;
3047 case 10:
3048 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3049 break;
3050 case 14:
3051 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3052 break;
3053 }
3054 if (IS_I965G(dev) && !IS_IGDNG(dev))
3055 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3056 } else {
3057 if (is_lvds) {
3058 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3059 } else {
3060 if (clock.p1 == 2)
3061 dpll |= PLL_P1_DIVIDE_BY_TWO;
3062 else
3063 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3064 if (clock.p2 == 4)
3065 dpll |= PLL_P2_DIVIDE_BY_4;
3066 }
3067 }
3068
3069 if (is_sdvo && is_tv)
3070 dpll |= PLL_REF_INPUT_TVCLKINBC;
3071 else if (is_tv)
3072 /* XXX: just matching BIOS for now */
3073 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3074 dpll |= 3;
3075 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3076 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3077 else
3078 dpll |= PLL_REF_INPUT_DREFCLK;
3079
3080 /* setup pipeconf */
3081 pipeconf = I915_READ(pipeconf_reg);
3082
3083 /* Set up the display plane register */
3084 dspcntr = DISPPLANE_GAMMA_ENABLE;
3085
3086 /* IGDNG's plane is forced to pipe, bit 24 is to
3087 enable color space conversion */
3088 if (!IS_IGDNG(dev)) {
3089 if (pipe == 0)
3090 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3091 else
3092 dspcntr |= DISPPLANE_SEL_PIPE_B;
3093 }
3094
3095 if (pipe == 0 && !IS_I965G(dev)) {
3096 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3097 * core speed.
3098 *
3099 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3100 * pipe == 0 check?
3101 */
3102 if (mode->clock >
3103 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3104 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3105 else
3106 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3107 }
3108
3109 dspcntr |= DISPLAY_PLANE_ENABLE;
3110 pipeconf |= PIPEACONF_ENABLE;
3111 dpll |= DPLL_VCO_ENABLE;
3112
3113
3114 /* Disable the panel fitter if it was on our pipe */
3115 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3116 I915_WRITE(PFIT_CONTROL, 0);
3117
3118 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3119 drm_mode_debug_printmodeline(mode);
3120
3121 /* assign to IGDNG registers */
3122 if (IS_IGDNG(dev)) {
3123 fp_reg = pch_fp_reg;
3124 dpll_reg = pch_dpll_reg;
3125 }
3126
3127 if (is_edp) {
3128 igdng_disable_pll_edp(crtc);
3129 } else if ((dpll & DPLL_VCO_ENABLE)) {
3130 I915_WRITE(fp_reg, fp);
3131 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3132 I915_READ(dpll_reg);
3133 udelay(150);
3134 }
3135
3136 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3137 * This is an exception to the general rule that mode_set doesn't turn
3138 * things on.
3139 */
3140 if (is_lvds) {
3141 u32 lvds;
3142
3143 if (IS_IGDNG(dev))
3144 lvds_reg = PCH_LVDS;
3145
3146 lvds = I915_READ(lvds_reg);
3147 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3148 /* set the corresponsding LVDS_BORDER bit */
3149 lvds |= dev_priv->lvds_border_bits;
3150 /* Set the B0-B3 data pairs corresponding to whether we're going to
3151 * set the DPLLs for dual-channel mode or not.
3152 */
3153 if (clock.p2 == 7)
3154 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3155 else
3156 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3157
3158 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3159 * appropriately here, but we need to look more thoroughly into how
3160 * panels behave in the two modes.
3161 */
3162
3163 I915_WRITE(lvds_reg, lvds);
3164 I915_READ(lvds_reg);
3165 }
3166 if (is_dp)
3167 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3168
3169 if (!is_edp) {
3170 I915_WRITE(fp_reg, fp);
3171 I915_WRITE(dpll_reg, dpll);
3172 I915_READ(dpll_reg);
3173 /* Wait for the clocks to stabilize. */
3174 udelay(150);
3175
3176 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3177 if (is_sdvo) {
3178 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3179 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3180 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3181 } else
3182 I915_WRITE(dpll_md_reg, 0);
3183 } else {
3184 /* write it again -- the BIOS does, after all */
3185 I915_WRITE(dpll_reg, dpll);
3186 }
3187 I915_READ(dpll_reg);
3188 /* Wait for the clocks to stabilize. */
3189 udelay(150);
3190 }
3191
3192 if (is_lvds && has_reduced_clock && i915_powersave) {
3193 I915_WRITE(fp_reg + 4, fp2);
3194 intel_crtc->lowfreq_avail = true;
3195 if (HAS_PIPE_CXSR(dev)) {
3196 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3197 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3198 }
3199 } else {
3200 I915_WRITE(fp_reg + 4, fp);
3201 intel_crtc->lowfreq_avail = false;
3202 if (HAS_PIPE_CXSR(dev)) {
3203 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3204 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3205 }
3206 }
3207
3208 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3209 ((adjusted_mode->crtc_htotal - 1) << 16));
3210 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3211 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3212 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3213 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3214 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3215 ((adjusted_mode->crtc_vtotal - 1) << 16));
3216 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3217 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3218 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3219 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3220 /* pipesrc and dspsize control the size that is scaled from, which should
3221 * always be the user's requested size.
3222 */
3223 if (!IS_IGDNG(dev)) {
3224 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3225 (mode->hdisplay - 1));
3226 I915_WRITE(dsppos_reg, 0);
3227 }
3228 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3229
3230 if (IS_IGDNG(dev)) {
3231 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3232 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3233 I915_WRITE(link_m1_reg, m_n.link_m);
3234 I915_WRITE(link_n1_reg, m_n.link_n);
3235
3236 if (is_edp) {
3237 igdng_set_pll_edp(crtc, adjusted_mode->clock);
3238 } else {
3239 /* enable FDI RX PLL too */
3240 temp = I915_READ(fdi_rx_reg);
3241 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3242 udelay(200);
3243 }
3244 }
3245
3246 I915_WRITE(pipeconf_reg, pipeconf);
3247 I915_READ(pipeconf_reg);
3248
3249 intel_wait_for_vblank(dev);
3250
3251 if (IS_IGDNG(dev)) {
3252 /* enable address swizzle for tiling buffer */
3253 temp = I915_READ(DISP_ARB_CTL);
3254 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3255 }
3256
3257 I915_WRITE(dspcntr_reg, dspcntr);
3258
3259 /* Flush the plane changes */
3260 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3261
3262 if ((IS_I965G(dev) || plane == 0))
3263 intel_update_fbc(crtc, &crtc->mode);
3264
3265 intel_update_watermarks(dev);
3266
3267 drm_vblank_post_modeset(dev, pipe);
3268
3269 return ret;
3270 }
3271
3272 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3273 void intel_crtc_load_lut(struct drm_crtc *crtc)
3274 {
3275 struct drm_device *dev = crtc->dev;
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3278 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3279 int i;
3280
3281 /* The clocks have to be on to load the palette. */
3282 if (!crtc->enabled)
3283 return;
3284
3285 /* use legacy palette for IGDNG */
3286 if (IS_IGDNG(dev))
3287 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3288 LGC_PALETTE_B;
3289
3290 for (i = 0; i < 256; i++) {
3291 I915_WRITE(palreg + 4 * i,
3292 (intel_crtc->lut_r[i] << 16) |
3293 (intel_crtc->lut_g[i] << 8) |
3294 intel_crtc->lut_b[i]);
3295 }
3296 }
3297
3298 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3299 struct drm_file *file_priv,
3300 uint32_t handle,
3301 uint32_t width, uint32_t height)
3302 {
3303 struct drm_device *dev = crtc->dev;
3304 struct drm_i915_private *dev_priv = dev->dev_private;
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306 struct drm_gem_object *bo;
3307 struct drm_i915_gem_object *obj_priv;
3308 int pipe = intel_crtc->pipe;
3309 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3310 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3311 uint32_t temp = I915_READ(control);
3312 size_t addr;
3313 int ret;
3314
3315 DRM_DEBUG_KMS("\n");
3316
3317 /* if we want to turn off the cursor ignore width and height */
3318 if (!handle) {
3319 DRM_DEBUG_KMS("cursor off\n");
3320 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3321 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3322 temp |= CURSOR_MODE_DISABLE;
3323 } else {
3324 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3325 }
3326 addr = 0;
3327 bo = NULL;
3328 mutex_lock(&dev->struct_mutex);
3329 goto finish;
3330 }
3331
3332 /* Currently we only support 64x64 cursors */
3333 if (width != 64 || height != 64) {
3334 DRM_ERROR("we currently only support 64x64 cursors\n");
3335 return -EINVAL;
3336 }
3337
3338 bo = drm_gem_object_lookup(dev, file_priv, handle);
3339 if (!bo)
3340 return -ENOENT;
3341
3342 obj_priv = bo->driver_private;
3343
3344 if (bo->size < width * height * 4) {
3345 DRM_ERROR("buffer is to small\n");
3346 ret = -ENOMEM;
3347 goto fail;
3348 }
3349
3350 /* we only need to pin inside GTT if cursor is non-phy */
3351 mutex_lock(&dev->struct_mutex);
3352 if (!dev_priv->cursor_needs_physical) {
3353 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3354 if (ret) {
3355 DRM_ERROR("failed to pin cursor bo\n");
3356 goto fail_locked;
3357 }
3358 addr = obj_priv->gtt_offset;
3359 } else {
3360 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3361 if (ret) {
3362 DRM_ERROR("failed to attach phys object\n");
3363 goto fail_locked;
3364 }
3365 addr = obj_priv->phys_obj->handle->busaddr;
3366 }
3367
3368 if (!IS_I9XX(dev))
3369 I915_WRITE(CURSIZE, (height << 12) | width);
3370
3371 /* Hooray for CUR*CNTR differences */
3372 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3373 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3374 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3375 temp |= (pipe << 28); /* Connect to correct pipe */
3376 } else {
3377 temp &= ~(CURSOR_FORMAT_MASK);
3378 temp |= CURSOR_ENABLE;
3379 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3380 }
3381
3382 finish:
3383 I915_WRITE(control, temp);
3384 I915_WRITE(base, addr);
3385
3386 if (intel_crtc->cursor_bo) {
3387 if (dev_priv->cursor_needs_physical) {
3388 if (intel_crtc->cursor_bo != bo)
3389 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3390 } else
3391 i915_gem_object_unpin(intel_crtc->cursor_bo);
3392 drm_gem_object_unreference(intel_crtc->cursor_bo);
3393 }
3394
3395 mutex_unlock(&dev->struct_mutex);
3396
3397 intel_crtc->cursor_addr = addr;
3398 intel_crtc->cursor_bo = bo;
3399
3400 return 0;
3401 fail:
3402 mutex_lock(&dev->struct_mutex);
3403 fail_locked:
3404 drm_gem_object_unreference(bo);
3405 mutex_unlock(&dev->struct_mutex);
3406 return ret;
3407 }
3408
3409 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3410 {
3411 struct drm_device *dev = crtc->dev;
3412 struct drm_i915_private *dev_priv = dev->dev_private;
3413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3414 struct intel_framebuffer *intel_fb;
3415 int pipe = intel_crtc->pipe;
3416 uint32_t temp = 0;
3417 uint32_t adder;
3418
3419 if (crtc->fb) {
3420 intel_fb = to_intel_framebuffer(crtc->fb);
3421 intel_mark_busy(dev, intel_fb->obj);
3422 }
3423
3424 if (x < 0) {
3425 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3426 x = -x;
3427 }
3428 if (y < 0) {
3429 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3430 y = -y;
3431 }
3432
3433 temp |= x << CURSOR_X_SHIFT;
3434 temp |= y << CURSOR_Y_SHIFT;
3435
3436 adder = intel_crtc->cursor_addr;
3437 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3438 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3439
3440 return 0;
3441 }
3442
3443 /** Sets the color ramps on behalf of RandR */
3444 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3445 u16 blue, int regno)
3446 {
3447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3448
3449 intel_crtc->lut_r[regno] = red >> 8;
3450 intel_crtc->lut_g[regno] = green >> 8;
3451 intel_crtc->lut_b[regno] = blue >> 8;
3452 }
3453
3454 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3455 u16 *blue, int regno)
3456 {
3457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3458
3459 *red = intel_crtc->lut_r[regno] << 8;
3460 *green = intel_crtc->lut_g[regno] << 8;
3461 *blue = intel_crtc->lut_b[regno] << 8;
3462 }
3463
3464 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3465 u16 *blue, uint32_t size)
3466 {
3467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3468 int i;
3469
3470 if (size != 256)
3471 return;
3472
3473 for (i = 0; i < 256; i++) {
3474 intel_crtc->lut_r[i] = red[i] >> 8;
3475 intel_crtc->lut_g[i] = green[i] >> 8;
3476 intel_crtc->lut_b[i] = blue[i] >> 8;
3477 }
3478
3479 intel_crtc_load_lut(crtc);
3480 }
3481
3482 /**
3483 * Get a pipe with a simple mode set on it for doing load-based monitor
3484 * detection.
3485 *
3486 * It will be up to the load-detect code to adjust the pipe as appropriate for
3487 * its requirements. The pipe will be connected to no other outputs.
3488 *
3489 * Currently this code will only succeed if there is a pipe with no outputs
3490 * configured for it. In the future, it could choose to temporarily disable
3491 * some outputs to free up a pipe for its use.
3492 *
3493 * \return crtc, or NULL if no pipes are available.
3494 */
3495
3496 /* VESA 640x480x72Hz mode to set on the pipe */
3497 static struct drm_display_mode load_detect_mode = {
3498 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3499 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3500 };
3501
3502 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3503 struct drm_display_mode *mode,
3504 int *dpms_mode)
3505 {
3506 struct intel_crtc *intel_crtc;
3507 struct drm_crtc *possible_crtc;
3508 struct drm_crtc *supported_crtc =NULL;
3509 struct drm_encoder *encoder = &intel_output->enc;
3510 struct drm_crtc *crtc = NULL;
3511 struct drm_device *dev = encoder->dev;
3512 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3513 struct drm_crtc_helper_funcs *crtc_funcs;
3514 int i = -1;
3515
3516 /*
3517 * Algorithm gets a little messy:
3518 * - if the connector already has an assigned crtc, use it (but make
3519 * sure it's on first)
3520 * - try to find the first unused crtc that can drive this connector,
3521 * and use that if we find one
3522 * - if there are no unused crtcs available, try to use the first
3523 * one we found that supports the connector
3524 */
3525
3526 /* See if we already have a CRTC for this connector */
3527 if (encoder->crtc) {
3528 crtc = encoder->crtc;
3529 /* Make sure the crtc and connector are running */
3530 intel_crtc = to_intel_crtc(crtc);
3531 *dpms_mode = intel_crtc->dpms_mode;
3532 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3533 crtc_funcs = crtc->helper_private;
3534 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3535 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3536 }
3537 return crtc;
3538 }
3539
3540 /* Find an unused one (if possible) */
3541 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3542 i++;
3543 if (!(encoder->possible_crtcs & (1 << i)))
3544 continue;
3545 if (!possible_crtc->enabled) {
3546 crtc = possible_crtc;
3547 break;
3548 }
3549 if (!supported_crtc)
3550 supported_crtc = possible_crtc;
3551 }
3552
3553 /*
3554 * If we didn't find an unused CRTC, don't use any.
3555 */
3556 if (!crtc) {
3557 return NULL;
3558 }
3559
3560 encoder->crtc = crtc;
3561 intel_output->base.encoder = encoder;
3562 intel_output->load_detect_temp = true;
3563
3564 intel_crtc = to_intel_crtc(crtc);
3565 *dpms_mode = intel_crtc->dpms_mode;
3566
3567 if (!crtc->enabled) {
3568 if (!mode)
3569 mode = &load_detect_mode;
3570 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3571 } else {
3572 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3573 crtc_funcs = crtc->helper_private;
3574 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3575 }
3576
3577 /* Add this connector to the crtc */
3578 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3579 encoder_funcs->commit(encoder);
3580 }
3581 /* let the connector get through one full cycle before testing */
3582 intel_wait_for_vblank(dev);
3583
3584 return crtc;
3585 }
3586
3587 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3588 {
3589 struct drm_encoder *encoder = &intel_output->enc;
3590 struct drm_device *dev = encoder->dev;
3591 struct drm_crtc *crtc = encoder->crtc;
3592 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3593 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3594
3595 if (intel_output->load_detect_temp) {
3596 encoder->crtc = NULL;
3597 intel_output->base.encoder = NULL;
3598 intel_output->load_detect_temp = false;
3599 crtc->enabled = drm_helper_crtc_in_use(crtc);
3600 drm_helper_disable_unused_functions(dev);
3601 }
3602
3603 /* Switch crtc and output back off if necessary */
3604 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3605 if (encoder->crtc == crtc)
3606 encoder_funcs->dpms(encoder, dpms_mode);
3607 crtc_funcs->dpms(crtc, dpms_mode);
3608 }
3609 }
3610
3611 /* Returns the clock of the currently programmed mode of the given pipe. */
3612 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3613 {
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616 int pipe = intel_crtc->pipe;
3617 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3618 u32 fp;
3619 intel_clock_t clock;
3620
3621 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3622 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3623 else
3624 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3625
3626 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3627 if (IS_IGD(dev)) {
3628 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3629 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3630 } else {
3631 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3632 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3633 }
3634
3635 if (IS_I9XX(dev)) {
3636 if (IS_IGD(dev))
3637 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3638 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3639 else
3640 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3641 DPLL_FPA01_P1_POST_DIV_SHIFT);
3642
3643 switch (dpll & DPLL_MODE_MASK) {
3644 case DPLLB_MODE_DAC_SERIAL:
3645 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3646 5 : 10;
3647 break;
3648 case DPLLB_MODE_LVDS:
3649 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3650 7 : 14;
3651 break;
3652 default:
3653 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3654 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3655 return 0;
3656 }
3657
3658 /* XXX: Handle the 100Mhz refclk */
3659 intel_clock(dev, 96000, &clock);
3660 } else {
3661 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3662
3663 if (is_lvds) {
3664 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3665 DPLL_FPA01_P1_POST_DIV_SHIFT);
3666 clock.p2 = 14;
3667
3668 if ((dpll & PLL_REF_INPUT_MASK) ==
3669 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3670 /* XXX: might not be 66MHz */
3671 intel_clock(dev, 66000, &clock);
3672 } else
3673 intel_clock(dev, 48000, &clock);
3674 } else {
3675 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3676 clock.p1 = 2;
3677 else {
3678 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3679 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3680 }
3681 if (dpll & PLL_P2_DIVIDE_BY_4)
3682 clock.p2 = 4;
3683 else
3684 clock.p2 = 2;
3685
3686 intel_clock(dev, 48000, &clock);
3687 }
3688 }
3689
3690 /* XXX: It would be nice to validate the clocks, but we can't reuse
3691 * i830PllIsValid() because it relies on the xf86_config connector
3692 * configuration being accurate, which it isn't necessarily.
3693 */
3694
3695 return clock.dot;
3696 }
3697
3698 /** Returns the currently programmed mode of the given pipe. */
3699 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3700 struct drm_crtc *crtc)
3701 {
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3704 int pipe = intel_crtc->pipe;
3705 struct drm_display_mode *mode;
3706 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3707 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3708 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3709 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3710
3711 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3712 if (!mode)
3713 return NULL;
3714
3715 mode->clock = intel_crtc_clock_get(dev, crtc);
3716 mode->hdisplay = (htot & 0xffff) + 1;
3717 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3718 mode->hsync_start = (hsync & 0xffff) + 1;
3719 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3720 mode->vdisplay = (vtot & 0xffff) + 1;
3721 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3722 mode->vsync_start = (vsync & 0xffff) + 1;
3723 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3724
3725 drm_mode_set_name(mode);
3726 drm_mode_set_crtcinfo(mode, 0);
3727
3728 return mode;
3729 }
3730
3731 #define GPU_IDLE_TIMEOUT 500 /* ms */
3732
3733 /* When this timer fires, we've been idle for awhile */
3734 static void intel_gpu_idle_timer(unsigned long arg)
3735 {
3736 struct drm_device *dev = (struct drm_device *)arg;
3737 drm_i915_private_t *dev_priv = dev->dev_private;
3738
3739 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3740
3741 dev_priv->busy = false;
3742
3743 queue_work(dev_priv->wq, &dev_priv->idle_work);
3744 }
3745
3746 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3747 {
3748 drm_i915_private_t *dev_priv = dev->dev_private;
3749
3750 if (IS_IGDNG(dev))
3751 return;
3752
3753 if (!dev_priv->render_reclock_avail) {
3754 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3755 return;
3756 }
3757
3758 /* Restore render clock frequency to original value */
3759 if (IS_G4X(dev) || IS_I9XX(dev))
3760 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3761 else if (IS_I85X(dev))
3762 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3763 DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3764
3765 /* Schedule downclock */
3766 if (schedule)
3767 mod_timer(&dev_priv->idle_timer, jiffies +
3768 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3769 }
3770
3771 void intel_decrease_renderclock(struct drm_device *dev)
3772 {
3773 drm_i915_private_t *dev_priv = dev->dev_private;
3774
3775 if (IS_IGDNG(dev))
3776 return;
3777
3778 if (!dev_priv->render_reclock_avail) {
3779 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3780 return;
3781 }
3782
3783 if (IS_G4X(dev)) {
3784 u16 gcfgc;
3785
3786 /* Adjust render clock... */
3787 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3788
3789 /* Down to minimum... */
3790 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3791 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3792
3793 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3794 } else if (IS_I965G(dev)) {
3795 u16 gcfgc;
3796
3797 /* Adjust render clock... */
3798 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3799
3800 /* Down to minimum... */
3801 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3802 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3803
3804 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3805 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3806 u16 gcfgc;
3807
3808 /* Adjust render clock... */
3809 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3810
3811 /* Down to minimum... */
3812 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3813 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3814
3815 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3816 } else if (IS_I915G(dev)) {
3817 u16 gcfgc;
3818
3819 /* Adjust render clock... */
3820 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3821
3822 /* Down to minimum... */
3823 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3824 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3825
3826 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3827 } else if (IS_I85X(dev)) {
3828 u16 hpllcc;
3829
3830 /* Adjust render clock... */
3831 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3832
3833 /* Up to maximum... */
3834 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3835 hpllcc |= GC_CLOCK_133_200;
3836
3837 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3838 }
3839 DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3840 }
3841
3842 /* Note that no increase function is needed for this - increase_renderclock()
3843 * will also rewrite these bits
3844 */
3845 void intel_decrease_displayclock(struct drm_device *dev)
3846 {
3847 if (IS_IGDNG(dev))
3848 return;
3849
3850 if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3851 IS_I915GM(dev)) {
3852 u16 gcfgc;
3853
3854 /* Adjust render clock... */
3855 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3856
3857 /* Down to minimum... */
3858 gcfgc &= ~0xf0;
3859 gcfgc |= 0x80;
3860
3861 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3862 }
3863 }
3864
3865 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3866
3867 static void intel_crtc_idle_timer(unsigned long arg)
3868 {
3869 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3870 struct drm_crtc *crtc = &intel_crtc->base;
3871 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3872
3873 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3874
3875 intel_crtc->busy = false;
3876
3877 queue_work(dev_priv->wq, &dev_priv->idle_work);
3878 }
3879
3880 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3881 {
3882 struct drm_device *dev = crtc->dev;
3883 drm_i915_private_t *dev_priv = dev->dev_private;
3884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3885 int pipe = intel_crtc->pipe;
3886 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3887 int dpll = I915_READ(dpll_reg);
3888
3889 if (IS_IGDNG(dev))
3890 return;
3891
3892 if (!dev_priv->lvds_downclock_avail)
3893 return;
3894
3895 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3896 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3897
3898 /* Unlock panel regs */
3899 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3900
3901 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3902 I915_WRITE(dpll_reg, dpll);
3903 dpll = I915_READ(dpll_reg);
3904 intel_wait_for_vblank(dev);
3905 dpll = I915_READ(dpll_reg);
3906 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3907 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3908
3909 /* ...and lock them again */
3910 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3911 }
3912
3913 /* Schedule downclock */
3914 if (schedule)
3915 mod_timer(&intel_crtc->idle_timer, jiffies +
3916 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3917 }
3918
3919 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3920 {
3921 struct drm_device *dev = crtc->dev;
3922 drm_i915_private_t *dev_priv = dev->dev_private;
3923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3924 int pipe = intel_crtc->pipe;
3925 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3926 int dpll = I915_READ(dpll_reg);
3927
3928 if (IS_IGDNG(dev))
3929 return;
3930
3931 if (!dev_priv->lvds_downclock_avail)
3932 return;
3933
3934 /*
3935 * Since this is called by a timer, we should never get here in
3936 * the manual case.
3937 */
3938 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3939 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3940
3941 /* Unlock panel regs */
3942 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3943
3944 dpll |= DISPLAY_RATE_SELECT_FPA1;
3945 I915_WRITE(dpll_reg, dpll);
3946 dpll = I915_READ(dpll_reg);
3947 intel_wait_for_vblank(dev);
3948 dpll = I915_READ(dpll_reg);
3949 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3950 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3951
3952 /* ...and lock them again */
3953 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3954 }
3955
3956 }
3957
3958 /**
3959 * intel_idle_update - adjust clocks for idleness
3960 * @work: work struct
3961 *
3962 * Either the GPU or display (or both) went idle. Check the busy status
3963 * here and adjust the CRTC and GPU clocks as necessary.
3964 */
3965 static void intel_idle_update(struct work_struct *work)
3966 {
3967 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3968 idle_work);
3969 struct drm_device *dev = dev_priv->dev;
3970 struct drm_crtc *crtc;
3971 struct intel_crtc *intel_crtc;
3972
3973 if (!i915_powersave)
3974 return;
3975
3976 mutex_lock(&dev->struct_mutex);
3977
3978 /* GPU isn't processing, downclock it. */
3979 if (!dev_priv->busy) {
3980 intel_decrease_renderclock(dev);
3981 intel_decrease_displayclock(dev);
3982 }
3983
3984 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3985 /* Skip inactive CRTCs */
3986 if (!crtc->fb)
3987 continue;
3988
3989 intel_crtc = to_intel_crtc(crtc);
3990 if (!intel_crtc->busy)
3991 intel_decrease_pllclock(crtc);
3992 }
3993
3994 mutex_unlock(&dev->struct_mutex);
3995 }
3996
3997 /**
3998 * intel_mark_busy - mark the GPU and possibly the display busy
3999 * @dev: drm device
4000 * @obj: object we're operating on
4001 *
4002 * Callers can use this function to indicate that the GPU is busy processing
4003 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4004 * buffer), we'll also mark the display as busy, so we know to increase its
4005 * clock frequency.
4006 */
4007 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4008 {
4009 drm_i915_private_t *dev_priv = dev->dev_private;
4010 struct drm_crtc *crtc = NULL;
4011 struct intel_framebuffer *intel_fb;
4012 struct intel_crtc *intel_crtc;
4013
4014 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4015 return;
4016
4017 dev_priv->busy = true;
4018 intel_increase_renderclock(dev, true);
4019
4020 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4021 if (!crtc->fb)
4022 continue;
4023
4024 intel_crtc = to_intel_crtc(crtc);
4025 intel_fb = to_intel_framebuffer(crtc->fb);
4026 if (intel_fb->obj == obj) {
4027 if (!intel_crtc->busy) {
4028 /* Non-busy -> busy, upclock */
4029 intel_increase_pllclock(crtc, true);
4030 intel_crtc->busy = true;
4031 } else {
4032 /* Busy -> busy, put off timer */
4033 mod_timer(&intel_crtc->idle_timer, jiffies +
4034 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4035 }
4036 }
4037 }
4038 }
4039
4040 static void intel_crtc_destroy(struct drm_crtc *crtc)
4041 {
4042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4043
4044 drm_crtc_cleanup(crtc);
4045 kfree(intel_crtc);
4046 }
4047
4048 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4049 .dpms = intel_crtc_dpms,
4050 .mode_fixup = intel_crtc_mode_fixup,
4051 .mode_set = intel_crtc_mode_set,
4052 .mode_set_base = intel_pipe_set_base,
4053 .prepare = intel_crtc_prepare,
4054 .commit = intel_crtc_commit,
4055 .load_lut = intel_crtc_load_lut,
4056 };
4057
4058 static const struct drm_crtc_funcs intel_crtc_funcs = {
4059 .cursor_set = intel_crtc_cursor_set,
4060 .cursor_move = intel_crtc_cursor_move,
4061 .gamma_set = intel_crtc_gamma_set,
4062 .set_config = drm_crtc_helper_set_config,
4063 .destroy = intel_crtc_destroy,
4064 };
4065
4066
4067 static void intel_crtc_init(struct drm_device *dev, int pipe)
4068 {
4069 struct intel_crtc *intel_crtc;
4070 int i;
4071
4072 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4073 if (intel_crtc == NULL)
4074 return;
4075
4076 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4077
4078 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4079 intel_crtc->pipe = pipe;
4080 intel_crtc->plane = pipe;
4081 for (i = 0; i < 256; i++) {
4082 intel_crtc->lut_r[i] = i;
4083 intel_crtc->lut_g[i] = i;
4084 intel_crtc->lut_b[i] = i;
4085 }
4086
4087 /* Swap pipes & planes for FBC on pre-965 */
4088 intel_crtc->pipe = pipe;
4089 intel_crtc->plane = pipe;
4090 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4091 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4092 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4093 }
4094
4095 intel_crtc->cursor_addr = 0;
4096 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4097 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4098
4099 intel_crtc->busy = false;
4100
4101 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4102 (unsigned long)intel_crtc);
4103 }
4104
4105 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4106 struct drm_file *file_priv)
4107 {
4108 drm_i915_private_t *dev_priv = dev->dev_private;
4109 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4110 struct drm_mode_object *drmmode_obj;
4111 struct intel_crtc *crtc;
4112
4113 if (!dev_priv) {
4114 DRM_ERROR("called with no initialization\n");
4115 return -EINVAL;
4116 }
4117
4118 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4119 DRM_MODE_OBJECT_CRTC);
4120
4121 if (!drmmode_obj) {
4122 DRM_ERROR("no such CRTC id\n");
4123 return -EINVAL;
4124 }
4125
4126 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4127 pipe_from_crtc_id->pipe = crtc->pipe;
4128
4129 return 0;
4130 }
4131
4132 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4133 {
4134 struct drm_crtc *crtc = NULL;
4135
4136 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4138 if (intel_crtc->pipe == pipe)
4139 break;
4140 }
4141 return crtc;
4142 }
4143
4144 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4145 {
4146 int index_mask = 0;
4147 struct drm_connector *connector;
4148 int entry = 0;
4149
4150 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4151 struct intel_output *intel_output = to_intel_output(connector);
4152 if (type_mask & intel_output->clone_mask)
4153 index_mask |= (1 << entry);
4154 entry++;
4155 }
4156 return index_mask;
4157 }
4158
4159
4160 static void intel_setup_outputs(struct drm_device *dev)
4161 {
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct drm_connector *connector;
4164
4165 intel_crt_init(dev);
4166
4167 /* Set up integrated LVDS */
4168 if (IS_MOBILE(dev) && !IS_I830(dev))
4169 intel_lvds_init(dev);
4170
4171 if (IS_IGDNG(dev)) {
4172 int found;
4173
4174 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4175 intel_dp_init(dev, DP_A);
4176
4177 if (I915_READ(HDMIB) & PORT_DETECTED) {
4178 /* check SDVOB */
4179 /* found = intel_sdvo_init(dev, HDMIB); */
4180 found = 0;
4181 if (!found)
4182 intel_hdmi_init(dev, HDMIB);
4183 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4184 intel_dp_init(dev, PCH_DP_B);
4185 }
4186
4187 if (I915_READ(HDMIC) & PORT_DETECTED)
4188 intel_hdmi_init(dev, HDMIC);
4189
4190 if (I915_READ(HDMID) & PORT_DETECTED)
4191 intel_hdmi_init(dev, HDMID);
4192
4193 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4194 intel_dp_init(dev, PCH_DP_C);
4195
4196 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4197 intel_dp_init(dev, PCH_DP_D);
4198
4199 } else if (IS_I9XX(dev)) {
4200 bool found = false;
4201
4202 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4203 found = intel_sdvo_init(dev, SDVOB);
4204 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4205 intel_hdmi_init(dev, SDVOB);
4206
4207 if (!found && SUPPORTS_INTEGRATED_DP(dev))
4208 intel_dp_init(dev, DP_B);
4209 }
4210
4211 /* Before G4X SDVOC doesn't have its own detect register */
4212
4213 if (I915_READ(SDVOB) & SDVO_DETECTED)
4214 found = intel_sdvo_init(dev, SDVOC);
4215
4216 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4217
4218 if (SUPPORTS_INTEGRATED_HDMI(dev))
4219 intel_hdmi_init(dev, SDVOC);
4220 if (SUPPORTS_INTEGRATED_DP(dev))
4221 intel_dp_init(dev, DP_C);
4222 }
4223
4224 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4225 intel_dp_init(dev, DP_D);
4226 } else
4227 intel_dvo_init(dev);
4228
4229 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4230 intel_tv_init(dev);
4231
4232 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4233 struct intel_output *intel_output = to_intel_output(connector);
4234 struct drm_encoder *encoder = &intel_output->enc;
4235
4236 encoder->possible_crtcs = intel_output->crtc_mask;
4237 encoder->possible_clones = intel_connector_clones(dev,
4238 intel_output->clone_mask);
4239 }
4240 }
4241
4242 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4243 {
4244 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4245 struct drm_device *dev = fb->dev;
4246
4247 if (fb->fbdev)
4248 intelfb_remove(dev, fb);
4249
4250 drm_framebuffer_cleanup(fb);
4251 mutex_lock(&dev->struct_mutex);
4252 drm_gem_object_unreference(intel_fb->obj);
4253 mutex_unlock(&dev->struct_mutex);
4254
4255 kfree(intel_fb);
4256 }
4257
4258 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4259 struct drm_file *file_priv,
4260 unsigned int *handle)
4261 {
4262 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4263 struct drm_gem_object *object = intel_fb->obj;
4264
4265 return drm_gem_handle_create(file_priv, object, handle);
4266 }
4267
4268 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4269 .destroy = intel_user_framebuffer_destroy,
4270 .create_handle = intel_user_framebuffer_create_handle,
4271 };
4272
4273 int intel_framebuffer_create(struct drm_device *dev,
4274 struct drm_mode_fb_cmd *mode_cmd,
4275 struct drm_framebuffer **fb,
4276 struct drm_gem_object *obj)
4277 {
4278 struct intel_framebuffer *intel_fb;
4279 int ret;
4280
4281 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4282 if (!intel_fb)
4283 return -ENOMEM;
4284
4285 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4286 if (ret) {
4287 DRM_ERROR("framebuffer init failed %d\n", ret);
4288 return ret;
4289 }
4290
4291 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4292
4293 intel_fb->obj = obj;
4294
4295 *fb = &intel_fb->base;
4296
4297 return 0;
4298 }
4299
4300
4301 static struct drm_framebuffer *
4302 intel_user_framebuffer_create(struct drm_device *dev,
4303 struct drm_file *filp,
4304 struct drm_mode_fb_cmd *mode_cmd)
4305 {
4306 struct drm_gem_object *obj;
4307 struct drm_framebuffer *fb;
4308 int ret;
4309
4310 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4311 if (!obj)
4312 return NULL;
4313
4314 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4315 if (ret) {
4316 mutex_lock(&dev->struct_mutex);
4317 drm_gem_object_unreference(obj);
4318 mutex_unlock(&dev->struct_mutex);
4319 return NULL;
4320 }
4321
4322 return fb;
4323 }
4324
4325 static const struct drm_mode_config_funcs intel_mode_funcs = {
4326 .fb_create = intel_user_framebuffer_create,
4327 .fb_changed = intelfb_probe,
4328 };
4329
4330 void intel_init_clock_gating(struct drm_device *dev)
4331 {
4332 struct drm_i915_private *dev_priv = dev->dev_private;
4333
4334 /*
4335 * Disable clock gating reported to work incorrectly according to the
4336 * specs, but enable as much else as we can.
4337 */
4338 if (IS_IGDNG(dev)) {
4339 return;
4340 } else if (IS_G4X(dev)) {
4341 uint32_t dspclk_gate;
4342 I915_WRITE(RENCLK_GATE_D1, 0);
4343 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4344 GS_UNIT_CLOCK_GATE_DISABLE |
4345 CL_UNIT_CLOCK_GATE_DISABLE);
4346 I915_WRITE(RAMCLK_GATE_D, 0);
4347 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4348 OVRUNIT_CLOCK_GATE_DISABLE |
4349 OVCUNIT_CLOCK_GATE_DISABLE;
4350 if (IS_GM45(dev))
4351 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4352 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4353 } else if (IS_I965GM(dev)) {
4354 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4355 I915_WRITE(RENCLK_GATE_D2, 0);
4356 I915_WRITE(DSPCLK_GATE_D, 0);
4357 I915_WRITE(RAMCLK_GATE_D, 0);
4358 I915_WRITE16(DEUC, 0);
4359 } else if (IS_I965G(dev)) {
4360 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4361 I965_RCC_CLOCK_GATE_DISABLE |
4362 I965_RCPB_CLOCK_GATE_DISABLE |
4363 I965_ISC_CLOCK_GATE_DISABLE |
4364 I965_FBC_CLOCK_GATE_DISABLE);
4365 I915_WRITE(RENCLK_GATE_D2, 0);
4366 } else if (IS_I9XX(dev)) {
4367 u32 dstate = I915_READ(D_STATE);
4368
4369 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4370 DSTATE_DOT_CLOCK_GATING;
4371 I915_WRITE(D_STATE, dstate);
4372 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4373 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4374 } else if (IS_I830(dev)) {
4375 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4376 }
4377
4378 /*
4379 * GPU can automatically power down the render unit if given a page
4380 * to save state.
4381 */
4382 if (I915_HAS_RC6(dev)) {
4383 struct drm_gem_object *pwrctx;
4384 struct drm_i915_gem_object *obj_priv;
4385 int ret;
4386
4387 pwrctx = drm_gem_object_alloc(dev, 4096);
4388 if (!pwrctx) {
4389 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4390 goto out;
4391 }
4392
4393 ret = i915_gem_object_pin(pwrctx, 4096);
4394 if (ret) {
4395 DRM_ERROR("failed to pin power context: %d\n", ret);
4396 drm_gem_object_unreference(pwrctx);
4397 goto out;
4398 }
4399
4400 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4401
4402 obj_priv = pwrctx->driver_private;
4403
4404 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4405 I915_WRITE(MCHBAR_RENDER_STANDBY,
4406 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4407
4408 dev_priv->pwrctx = pwrctx;
4409 }
4410
4411 out:
4412 return;
4413 }
4414
4415 /* Set up chip specific display functions */
4416 static void intel_init_display(struct drm_device *dev)
4417 {
4418 struct drm_i915_private *dev_priv = dev->dev_private;
4419
4420 /* We always want a DPMS function */
4421 if (IS_IGDNG(dev))
4422 dev_priv->display.dpms = igdng_crtc_dpms;
4423 else
4424 dev_priv->display.dpms = i9xx_crtc_dpms;
4425
4426 /* Only mobile has FBC, leave pointers NULL for other chips */
4427 if (IS_MOBILE(dev)) {
4428 if (IS_GM45(dev)) {
4429 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4430 dev_priv->display.enable_fbc = g4x_enable_fbc;
4431 dev_priv->display.disable_fbc = g4x_disable_fbc;
4432 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4433 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4434 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4435 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4436 }
4437 /* 855GM needs testing */
4438 }
4439
4440 /* Returns the core display clock speed */
4441 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_IGDGM(dev)))
4442 dev_priv->display.get_display_clock_speed =
4443 i945_get_display_clock_speed;
4444 else if (IS_I915G(dev))
4445 dev_priv->display.get_display_clock_speed =
4446 i915_get_display_clock_speed;
4447 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4448 dev_priv->display.get_display_clock_speed =
4449 i9xx_misc_get_display_clock_speed;
4450 else if (IS_I915GM(dev))
4451 dev_priv->display.get_display_clock_speed =
4452 i915gm_get_display_clock_speed;
4453 else if (IS_I865G(dev))
4454 dev_priv->display.get_display_clock_speed =
4455 i865_get_display_clock_speed;
4456 else if (IS_I85X(dev))
4457 dev_priv->display.get_display_clock_speed =
4458 i855_get_display_clock_speed;
4459 else /* 852, 830 */
4460 dev_priv->display.get_display_clock_speed =
4461 i830_get_display_clock_speed;
4462
4463 /* For FIFO watermark updates */
4464 if (IS_IGDNG(dev))
4465 dev_priv->display.update_wm = NULL;
4466 else if (IS_G4X(dev))
4467 dev_priv->display.update_wm = g4x_update_wm;
4468 else if (IS_I965G(dev))
4469 dev_priv->display.update_wm = i965_update_wm;
4470 else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4471 dev_priv->display.update_wm = i9xx_update_wm;
4472 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4473 } else {
4474 if (IS_I85X(dev))
4475 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4476 else if (IS_845G(dev))
4477 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4478 else
4479 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4480 dev_priv->display.update_wm = i830_update_wm;
4481 }
4482 }
4483
4484 void intel_modeset_init(struct drm_device *dev)
4485 {
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 int num_pipe;
4488 int i;
4489
4490 drm_mode_config_init(dev);
4491
4492 dev->mode_config.min_width = 0;
4493 dev->mode_config.min_height = 0;
4494
4495 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4496
4497 intel_init_display(dev);
4498
4499 if (IS_I965G(dev)) {
4500 dev->mode_config.max_width = 8192;
4501 dev->mode_config.max_height = 8192;
4502 } else if (IS_I9XX(dev)) {
4503 dev->mode_config.max_width = 4096;
4504 dev->mode_config.max_height = 4096;
4505 } else {
4506 dev->mode_config.max_width = 2048;
4507 dev->mode_config.max_height = 2048;
4508 }
4509
4510 /* set memory base */
4511 if (IS_I9XX(dev))
4512 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4513 else
4514 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4515
4516 if (IS_MOBILE(dev) || IS_I9XX(dev))
4517 num_pipe = 2;
4518 else
4519 num_pipe = 1;
4520 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4521 num_pipe, num_pipe > 1 ? "s" : "");
4522
4523 if (IS_I85X(dev))
4524 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4525 else if (IS_I9XX(dev) || IS_G4X(dev))
4526 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4527
4528 for (i = 0; i < num_pipe; i++) {
4529 intel_crtc_init(dev, i);
4530 }
4531
4532 intel_setup_outputs(dev);
4533
4534 intel_init_clock_gating(dev);
4535
4536 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4537 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4538 (unsigned long)dev);
4539
4540 intel_setup_overlay(dev);
4541 }
4542
4543 void intel_modeset_cleanup(struct drm_device *dev)
4544 {
4545 struct drm_i915_private *dev_priv = dev->dev_private;
4546 struct drm_crtc *crtc;
4547 struct intel_crtc *intel_crtc;
4548
4549 mutex_lock(&dev->struct_mutex);
4550
4551 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4552 /* Skip inactive CRTCs */
4553 if (!crtc->fb)
4554 continue;
4555
4556 intel_crtc = to_intel_crtc(crtc);
4557 intel_increase_pllclock(crtc, false);
4558 del_timer_sync(&intel_crtc->idle_timer);
4559 }
4560
4561 intel_increase_renderclock(dev, false);
4562 del_timer_sync(&dev_priv->idle_timer);
4563
4564 mutex_unlock(&dev->struct_mutex);
4565
4566 if (dev_priv->display.disable_fbc)
4567 dev_priv->display.disable_fbc(dev);
4568
4569 if (dev_priv->pwrctx) {
4570 i915_gem_object_unpin(dev_priv->pwrctx);
4571 drm_gem_object_unreference(dev_priv->pwrctx);
4572 }
4573
4574 drm_mode_config_cleanup(dev);
4575 }
4576
4577
4578 /* current intel driver doesn't take advantage of encoders
4579 always give back the encoder for the connector
4580 */
4581 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4582 {
4583 struct intel_output *intel_output = to_intel_output(connector);
4584
4585 return &intel_output->enc;
4586 }
4587
4588 /*
4589 * set vga decode state - true == enable VGA decode
4590 */
4591 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4592 {
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 u16 gmch_ctrl;
4595
4596 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4597 if (state)
4598 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4599 else
4600 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4601 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4602 return 0;
4603 }
Linux kernel - Deliverables
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