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drm/i915: don't limit Haswell CRT encoder to pipe A
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
76 };
77
78 /* FDI */
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
81 int
82 intel_pch_rawclk(struct drm_device *dev)
83 {
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89 }
90
91 static bool
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
95 static bool
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99
100 static bool
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
104 static bool
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static bool
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
116 {
117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
122 }
123
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
136 };
137
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
150 };
151
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
164 };
165
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
178 };
179
180
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
193 },
194 .find_pll = intel_g4x_find_best_PLL,
195 };
196
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
209 };
210
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
222 },
223 .find_pll = intel_g4x_find_best_PLL,
224 };
225
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
237 },
238 .find_pll = intel_g4x_find_best_PLL,
239 };
240
241 static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
253 };
254
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
269 };
270
271 static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
283 };
284
285 /* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
290 static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
302 };
303
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
316 };
317
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
330 };
331
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
359 };
360
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
373 };
374
375 static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387 };
388
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401 };
402
403 static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415 };
416
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418 {
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437 out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440 }
441
442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444 {
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460 out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462 }
463
464 static void vlv_init_dpio(struct drm_device *dev)
465 {
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473 }
474
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476 {
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479 }
480
481 static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491 };
492
493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495 {
496 unsigned int val;
497
498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519 }
520
521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
523 {
524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 const intel_limit_t *limit;
527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530 /* LVDS dual channel */
531 if (refclk == 100000)
532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
536 if (refclk == 100000)
537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543 limit = &intel_limits_ironlake_display_port;
544 else
545 limit = &intel_limits_ironlake_dac;
546
547 return limit;
548 }
549
550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551 {
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 if (is_dual_link_lvds(dev_priv, LVDS))
558 /* LVDS with dual channel */
559 limit = &intel_limits_g4x_dual_channel_lvds;
560 else
561 /* LVDS with dual channel */
562 limit = &intel_limits_g4x_single_channel_lvds;
563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565 limit = &intel_limits_g4x_hdmi;
566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567 limit = &intel_limits_g4x_sdvo;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569 limit = &intel_limits_g4x_display_port;
570 } else /* The option is for other outputs */
571 limit = &intel_limits_i9xx_sdvo;
572
573 return limit;
574 }
575
576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
577 {
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
581 if (HAS_PCH_SPLIT(dev))
582 limit = intel_ironlake_limit(crtc, refclk);
583 else if (IS_G4X(dev)) {
584 limit = intel_g4x_limit(crtc);
585 } else if (IS_PINEVIEW(dev)) {
586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587 limit = &intel_limits_pineview_lvds;
588 else
589 limit = &intel_limits_pineview_sdvo;
590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604 limit = &intel_limits_i8xx_lvds;
605 else
606 limit = &intel_limits_i8xx_dvo;
607 }
608 return limit;
609 }
610
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk, intel_clock_t *clock)
613 {
614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618 }
619
620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621 {
622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
624 return;
625 }
626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630 }
631
632 /**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct intel_encoder *encoder;
639
640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
642 return true;
643
644 return false;
645 }
646
647 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
648 /**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
653 static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
656 {
657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
658 INTELPllInvalid("p1 out of range\n");
659 if (clock->p < limit->p.min || limit->p.max < clock->p)
660 INTELPllInvalid("p out of range\n");
661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
662 INTELPllInvalid("m2 out of range\n");
663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
664 INTELPllInvalid("m1 out of range\n");
665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666 INTELPllInvalid("m1 <= m2\n");
667 if (clock->m < limit->m.min || limit->m.max < clock->m)
668 INTELPllInvalid("m out of range\n");
669 if (clock->n < limit->n.min || limit->n.max < clock->n)
670 INTELPllInvalid("n out of range\n");
671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672 INTELPllInvalid("vco out of range\n");
673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677 INTELPllInvalid("dot out of range\n");
678
679 return true;
680 }
681
682 static bool
683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
686
687 {
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
691 int err = target;
692
693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694 (I915_READ(LVDS)) != 0) {
695 /*
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
699 * even can.
700 */
701 if (is_dual_link_lvds(dev_priv, LVDS))
702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
712 memset(best_clock, 0, sizeof(*best_clock));
713
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
720 break;
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
725 int this_err;
726
727 intel_clock(dev, refclk, &clock);
728 if (!intel_PLL_is_valid(dev, limit,
729 &clock))
730 continue;
731 if (match_clock &&
732 clock.p != match_clock->p)
733 continue;
734
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
737 *best_clock = clock;
738 err = this_err;
739 }
740 }
741 }
742 }
743 }
744
745 return (err != target);
746 }
747
748 static bool
749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
752 {
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 intel_clock_t clock;
756 int max_n;
757 bool found;
758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
760 found = false;
761
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
763 int lvds_reg;
764
765 if (HAS_PCH_SPLIT(dev))
766 lvds_reg = PCH_LVDS;
767 else
768 lvds_reg = LVDS;
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
770 LVDS_CLKB_POWER_UP)
771 clock.p2 = limit->p2.p2_fast;
772 else
773 clock.p2 = limit->p2.p2_slow;
774 } else {
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
777 else
778 clock.p2 = limit->p2.p2_fast;
779 }
780
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
783 /* based on hardware requirement, prefer smaller n to precision */
784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785 /* based on hardware requirement, prefere larger m1,m2 */
786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
792 int this_err;
793
794 intel_clock(dev, refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
797 continue;
798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
801
802 this_err = abs(clock.dot - target);
803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813 return found;
814 }
815
816 static bool
817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
820 {
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
823
824 if (target < 200000) {
825 clock.n = 1;
826 clock.p1 = 2;
827 clock.p2 = 10;
828 clock.m1 = 12;
829 clock.m2 = 9;
830 } else {
831 clock.n = 2;
832 clock.p1 = 1;
833 clock.p2 = 10;
834 clock.m1 = 14;
835 clock.m2 = 8;
836 }
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 return true;
840 }
841
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
843 static bool
844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
847 {
848 intel_clock_t clock;
849 if (target < 200000) {
850 clock.p1 = 2;
851 clock.p2 = 10;
852 clock.n = 2;
853 clock.m1 = 23;
854 clock.m2 = 8;
855 } else {
856 clock.p1 = 1;
857 clock.p2 = 10;
858 clock.n = 1;
859 clock.m1 = 14;
860 clock.m2 = 2;
861 }
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865 clock.vco = 0;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
867 return true;
868 }
869 static bool
870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
873 {
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875 u32 m, n, fastclk;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
878 int dotclk, flag;
879
880 flag = 0;
881 dotclk = target * 1000;
882 bestppm = 1000000;
883 ppm = absppm = 0;
884 fastclk = dotclk / (2*100);
885 updrate = 0;
886 minupdate = 19200;
887 fracbits = 1;
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896 if (p2 > 10)
897 p2 = p2 - 1;
898 p = p1 * p2;
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
903 m = m1 * m2;
904 vco = updrate * m;
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909 bestppm = 0;
910 flag = 1;
911 }
912 if (absppm < bestppm - 10) {
913 bestppm = absppm;
914 flag = 1;
915 }
916 if (flag) {
917 bestn = n;
918 bestm1 = m1;
919 bestm2 = m2;
920 bestp1 = p1;
921 bestp2 = p2;
922 flag = 0;
923 }
924 }
925 }
926 }
927 }
928 }
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
934
935 return true;
936 }
937
938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939 enum pipe pipe)
940 {
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944 return intel_crtc->cpu_transcoder;
945 }
946
947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948 {
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
951
952 frame = I915_READ(frame_reg);
953
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
956 }
957
958 /**
959 * intel_wait_for_vblank - wait for vblank on a given pipe
960 * @dev: drm device
961 * @pipe: pipe to wait for
962 *
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
964 * mode setting code.
965 */
966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
967 {
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 int pipestat_reg = PIPESTAT(pipe);
970
971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
973 return;
974 }
975
976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
978 *
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
985 * vblanks...
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
988 */
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
992 /* Wait for vblank interrupt bit to set */
993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
995 50))
996 DRM_DEBUG_KMS("vblank wait timed out\n");
997 }
998
999 /*
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
1001 * @dev: drm device
1002 * @pipe: pipe to wait for
1003 *
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1007 *
1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1010 *
1011 * Otherwise:
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
1014 *
1015 */
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1017 {
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020 pipe);
1021
1022 if (INTEL_INFO(dev)->gen >= 4) {
1023 int reg = PIPECONF(cpu_transcoder);
1024
1025 /* Wait for the Pipe State to go off */
1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027 100))
1028 WARN(1, "pipe_off wait timed out\n");
1029 } else {
1030 u32 last_line, line_mask;
1031 int reg = PIPEDSL(pipe);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034 if (IS_GEN2(dev))
1035 line_mask = DSL_LINEMASK_GEN2;
1036 else
1037 line_mask = DSL_LINEMASK_GEN3;
1038
1039 /* Wait for the display line to settle */
1040 do {
1041 last_line = I915_READ(reg) & line_mask;
1042 mdelay(5);
1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
1046 WARN(1, "pipe_off wait timed out\n");
1047 }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1077 bool state)
1078 {
1079 u32 val;
1080 bool cur_state;
1081
1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 return;
1085 }
1086
1087 if (WARN (!pll,
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089 return;
1090
1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099 u32 pch_dpll;
1100
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1111 crtc->pipe,
1112 val);
1113 }
1114 }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121 {
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126 pipe);
1127
1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133 } else {
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
1152 reg = FDI_RX_CTL(pipe);
1153 val = I915_READ(reg);
1154 cur_state = !!(val & FDI_RX_ENABLE);
1155 WARN(cur_state != state,
1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1157 state_string(state), state_string(cur_state));
1158 }
1159 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164 {
1165 int reg;
1166 u32 val;
1167
1168 /* ILK FDI PLL is always enabled */
1169 if (dev_priv->info->gen == 5)
1170 return;
1171
1172 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173 if (IS_HASWELL(dev_priv->dev))
1174 return;
1175
1176 reg = FDI_TX_CTL(pipe);
1177 val = I915_READ(reg);
1178 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
1183 {
1184 int reg;
1185 u32 val;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194 {
1195 int pp_reg, lvds_reg;
1196 u32 val;
1197 enum pipe panel_pipe = PIPE_A;
1198 bool locked = true;
1199
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1203 } else {
1204 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS;
1206 }
1207
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211 locked = false;
1212
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
1218 pipe_name(pipe));
1219 }
1220
1221 void assert_pipe(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223 {
1224 int reg;
1225 u32 val;
1226 bool cur_state;
1227 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 pipe);
1229
1230 /* if we need the pipe A quirk it must be always on */
1231 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232 state = true;
1233
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 WARN(cur_state != state,
1238 "pipe %c assertion failure (expected %s, current %s)\n",
1239 pipe_name(pipe), state_string(state), state_string(cur_state));
1240 }
1241
1242 static void assert_plane(struct drm_i915_private *dev_priv,
1243 enum plane plane, bool state)
1244 {
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248
1249 reg = DSPCNTR(plane);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252 WARN(cur_state != state,
1253 "plane %c assertion failure (expected %s, current %s)\n",
1254 plane_name(plane), state_string(state), state_string(cur_state));
1255 }
1256
1257 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
1260 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262 {
1263 int reg, i;
1264 u32 val;
1265 int cur_pipe;
1266
1267 /* Planes are fixed to pipes on ILK+ */
1268 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269 reg = DSPCNTR(pipe);
1270 val = I915_READ(reg);
1271 WARN((val & DISPLAY_PLANE_ENABLE),
1272 "plane %c assertion failure, should be disabled but not\n",
1273 plane_name(pipe));
1274 return;
1275 }
1276
1277 /* Need to check both planes against the pipe */
1278 for (i = 0; i < 2; i++) {
1279 reg = DSPCNTR(i);
1280 val = I915_READ(reg);
1281 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282 DISPPLANE_SEL_PIPE_SHIFT;
1283 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1284 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285 plane_name(i), pipe_name(pipe));
1286 }
1287 }
1288
1289 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290 {
1291 u32 val;
1292 bool enabled;
1293
1294 if (HAS_PCH_LPT(dev_priv->dev)) {
1295 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296 return;
1297 }
1298
1299 val = I915_READ(PCH_DREF_CONTROL);
1300 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301 DREF_SUPERSPREAD_SOURCE_MASK));
1302 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303 }
1304
1305 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe)
1307 {
1308 int reg;
1309 u32 val;
1310 bool enabled;
1311
1312 reg = TRANSCONF(pipe);
1313 val = I915_READ(reg);
1314 enabled = !!(val & TRANS_ENABLE);
1315 WARN(enabled,
1316 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317 pipe_name(pipe));
1318 }
1319
1320 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 port_sel, u32 val)
1322 {
1323 if ((val & DP_PORT_EN) == 0)
1324 return false;
1325
1326 if (HAS_PCH_CPT(dev_priv->dev)) {
1327 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330 return false;
1331 } else {
1332 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333 return false;
1334 }
1335 return true;
1336 }
1337
1338 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, u32 val)
1340 {
1341 if ((val & PORT_ENABLE) == 0)
1342 return false;
1343
1344 if (HAS_PCH_CPT(dev_priv->dev)) {
1345 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346 return false;
1347 } else {
1348 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349 return false;
1350 }
1351 return true;
1352 }
1353
1354 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe, u32 val)
1356 {
1357 if ((val & LVDS_PORT_EN) == 0)
1358 return false;
1359
1360 if (HAS_PCH_CPT(dev_priv->dev)) {
1361 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362 return false;
1363 } else {
1364 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365 return false;
1366 }
1367 return true;
1368 }
1369
1370 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372 {
1373 if ((val & ADPA_DAC_ENABLE) == 0)
1374 return false;
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377 return false;
1378 } else {
1379 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380 return false;
1381 }
1382 return true;
1383 }
1384
1385 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, int reg, u32 port_sel)
1387 {
1388 u32 val = I915_READ(reg);
1389 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1390 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391 reg, pipe_name(pipe));
1392
1393 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394 && (val & DP_PIPEB_SELECT),
1395 "IBX PCH dp port still using transcoder B\n");
1396 }
1397
1398 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe, int reg)
1400 {
1401 u32 val = I915_READ(reg);
1402 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1403 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404 reg, pipe_name(pipe));
1405
1406 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407 && (val & SDVO_PIPE_B_SELECT),
1408 "IBX PCH hdmi port still using transcoder B\n");
1409 }
1410
1411 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413 {
1414 int reg;
1415 u32 val;
1416
1417 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1420
1421 reg = PCH_ADPA;
1422 val = I915_READ(reg);
1423 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1424 "PCH VGA enabled on transcoder %c, should be disabled\n",
1425 pipe_name(pipe));
1426
1427 reg = PCH_LVDS;
1428 val = I915_READ(reg);
1429 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1430 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1431 pipe_name(pipe));
1432
1433 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436 }
1437
1438 /**
1439 * intel_enable_pll - enable a PLL
1440 * @dev_priv: i915 private structure
1441 * @pipe: pipe PLL to enable
1442 *
1443 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444 * make sure the PLL reg is writable first though, since the panel write
1445 * protect mechanism may be enabled.
1446 *
1447 * Note! This is for pre-ILK only.
1448 *
1449 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1450 */
1451 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452 {
1453 int reg;
1454 u32 val;
1455
1456 /* No really, not for ILK+ */
1457 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1458
1459 /* PLL is protected by panel, make sure we can write it */
1460 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461 assert_panel_unlocked(dev_priv, pipe);
1462
1463 reg = DPLL(pipe);
1464 val = I915_READ(reg);
1465 val |= DPLL_VCO_ENABLE;
1466
1467 /* We do this three times for luck */
1468 I915_WRITE(reg, val);
1469 POSTING_READ(reg);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg, val);
1472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg, val);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477 }
1478
1479 /**
1480 * intel_disable_pll - disable a PLL
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe PLL to disable
1483 *
1484 * Disable the PLL for @pipe, making sure the pipe is off first.
1485 *
1486 * Note! This is for pre-ILK only.
1487 */
1488 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489 {
1490 int reg;
1491 u32 val;
1492
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495 return;
1496
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 reg = DPLL(pipe);
1501 val = I915_READ(reg);
1502 val &= ~DPLL_VCO_ENABLE;
1503 I915_WRITE(reg, val);
1504 POSTING_READ(reg);
1505 }
1506
1507 /* SBI access */
1508 static void
1509 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1510 {
1511 unsigned long flags;
1512
1513 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1514 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to become ready\n");
1517 goto out_unlock;
1518 }
1519
1520 I915_WRITE(SBI_ADDR,
1521 (reg << 16));
1522 I915_WRITE(SBI_DATA,
1523 value);
1524 I915_WRITE(SBI_CTL_STAT,
1525 SBI_BUSY |
1526 SBI_CTL_OP_CRWR);
1527
1528 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1529 100)) {
1530 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1531 goto out_unlock;
1532 }
1533
1534 out_unlock:
1535 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1536 }
1537
1538 static u32
1539 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1540 {
1541 unsigned long flags;
1542 u32 value = 0;
1543
1544 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1545 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1546 100)) {
1547 DRM_ERROR("timeout waiting for SBI to become ready\n");
1548 goto out_unlock;
1549 }
1550
1551 I915_WRITE(SBI_ADDR,
1552 (reg << 16));
1553 I915_WRITE(SBI_CTL_STAT,
1554 SBI_BUSY |
1555 SBI_CTL_OP_CRRD);
1556
1557 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1558 100)) {
1559 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1560 goto out_unlock;
1561 }
1562
1563 value = I915_READ(SBI_DATA);
1564
1565 out_unlock:
1566 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1567 return value;
1568 }
1569
1570 /**
1571 * ironlake_enable_pch_pll - enable PCH PLL
1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
1578 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1579 {
1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1581 struct intel_pch_pll *pll;
1582 int reg;
1583 u32 val;
1584
1585 /* PCH PLLs only available on ILK, SNB and IVB */
1586 BUG_ON(dev_priv->info->gen < 5);
1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
1601 if (pll->active++ && pll->on) {
1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
1614
1615 pll->on = true;
1616 }
1617
1618 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1619 {
1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1622 int reg;
1623 u32 val;
1624
1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
1627 if (pll == NULL)
1628 return;
1629
1630 if (WARN_ON(pll->refcount == 0))
1631 return;
1632
1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
1636
1637 if (WARN_ON(pll->active == 0)) {
1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
1639 return;
1640 }
1641
1642 if (--pll->active) {
1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
1644 return;
1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1651
1652 reg = pll->pll_reg;
1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
1658
1659 pll->on = false;
1660 }
1661
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
1664 {
1665 struct drm_device *dev = dev_priv->dev;
1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1667 uint32_t reg, val, pipeconf_val;
1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1688 }
1689
1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
1692 pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
1699 val &= ~PIPE_BPC_MASK;
1700 val |= pipeconf_val & PIPE_BPC_MASK;
1701 }
1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716 }
1717
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1719 enum transcoder cpu_transcoder)
1720 {
1721 u32 val, pipeconf_val;
1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1729
1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
1735 val = TRANS_ENABLE;
1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1737
1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
1740 val |= TRANS_INTERLACED;
1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
1747 }
1748
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
1751 {
1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
1777 }
1778
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1780 {
1781 u32 val;
1782
1783 val = I915_READ(_TRANSACONF);
1784 val &= ~TRANS_ENABLE;
1785 I915_WRITE(_TRANSACONF, val);
1786 /* wait for PCH transcoder off, transcoder state */
1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1793 I915_WRITE(_TRANSA_CHICKEN2, val);
1794 }
1795
1796 /**
1797 * intel_enable_pipe - enable a pipe, asserting requirements
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
1810 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
1812 {
1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1815 int reg;
1816 u32 val;
1817
1818 /*
1819 * A pipe without a PLL won't actually be able to drive bits from
1820 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1821 * need the check.
1822 */
1823 if (!HAS_PCH_SPLIT(dev_priv->dev))
1824 assert_pll_enabled(dev_priv, pipe);
1825 else {
1826 if (pch_port) {
1827 /* if driving the PCH, we need FDI enabled */
1828 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1829 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1830 }
1831 /* FIXME: assert CPU port conditions for SNB+ */
1832 }
1833
1834 reg = PIPECONF(cpu_transcoder);
1835 val = I915_READ(reg);
1836 if (val & PIPECONF_ENABLE)
1837 return;
1838
1839 I915_WRITE(reg, val | PIPECONF_ENABLE);
1840 intel_wait_for_vblank(dev_priv->dev, pipe);
1841 }
1842
1843 /**
1844 * intel_disable_pipe - disable a pipe, asserting requirements
1845 * @dev_priv: i915 private structure
1846 * @pipe: pipe to disable
1847 *
1848 * Disable @pipe, making sure that various hardware specific requirements
1849 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1850 *
1851 * @pipe should be %PIPE_A or %PIPE_B.
1852 *
1853 * Will wait until the pipe has shut down before returning.
1854 */
1855 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1856 enum pipe pipe)
1857 {
1858 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1859 pipe);
1860 int reg;
1861 u32 val;
1862
1863 /*
1864 * Make sure planes won't keep trying to pump pixels to us,
1865 * or we might hang the display.
1866 */
1867 assert_planes_disabled(dev_priv, pipe);
1868
1869 /* Don't disable pipe A or pipe A PLLs if needed */
1870 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1871 return;
1872
1873 reg = PIPECONF(cpu_transcoder);
1874 val = I915_READ(reg);
1875 if ((val & PIPECONF_ENABLE) == 0)
1876 return;
1877
1878 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1879 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1880 }
1881
1882 /*
1883 * Plane regs are double buffered, going from enabled->disabled needs a
1884 * trigger in order to latch. The display address reg provides this.
1885 */
1886 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1887 enum plane plane)
1888 {
1889 if (dev_priv->info->gen >= 4)
1890 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1891 else
1892 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1893 }
1894
1895 /**
1896 * intel_enable_plane - enable a display plane on a given pipe
1897 * @dev_priv: i915 private structure
1898 * @plane: plane to enable
1899 * @pipe: pipe being fed
1900 *
1901 * Enable @plane on @pipe, making sure that @pipe is running first.
1902 */
1903 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1904 enum plane plane, enum pipe pipe)
1905 {
1906 int reg;
1907 u32 val;
1908
1909 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1910 assert_pipe_enabled(dev_priv, pipe);
1911
1912 reg = DSPCNTR(plane);
1913 val = I915_READ(reg);
1914 if (val & DISPLAY_PLANE_ENABLE)
1915 return;
1916
1917 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1918 intel_flush_display_plane(dev_priv, plane);
1919 intel_wait_for_vblank(dev_priv->dev, pipe);
1920 }
1921
1922 /**
1923 * intel_disable_plane - disable a display plane
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to disable
1926 * @pipe: pipe consuming the data
1927 *
1928 * Disable @plane; should be an independent operation.
1929 */
1930 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932 {
1933 int reg;
1934 u32 val;
1935
1936 reg = DSPCNTR(plane);
1937 val = I915_READ(reg);
1938 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1939 return;
1940
1941 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1942 intel_flush_display_plane(dev_priv, plane);
1943 intel_wait_for_vblank(dev_priv->dev, pipe);
1944 }
1945
1946 int
1947 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1948 struct drm_i915_gem_object *obj,
1949 struct intel_ring_buffer *pipelined)
1950 {
1951 struct drm_i915_private *dev_priv = dev->dev_private;
1952 u32 alignment;
1953 int ret;
1954
1955 switch (obj->tiling_mode) {
1956 case I915_TILING_NONE:
1957 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1958 alignment = 128 * 1024;
1959 else if (INTEL_INFO(dev)->gen >= 4)
1960 alignment = 4 * 1024;
1961 else
1962 alignment = 64 * 1024;
1963 break;
1964 case I915_TILING_X:
1965 /* pin() will align the object as required by fence */
1966 alignment = 0;
1967 break;
1968 case I915_TILING_Y:
1969 /* FIXME: Is this true? */
1970 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1971 return -EINVAL;
1972 default:
1973 BUG();
1974 }
1975
1976 dev_priv->mm.interruptible = false;
1977 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1978 if (ret)
1979 goto err_interruptible;
1980
1981 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1982 * fence, whereas 965+ only requires a fence if using
1983 * framebuffer compression. For simplicity, we always install
1984 * a fence as the cost is not that onerous.
1985 */
1986 ret = i915_gem_object_get_fence(obj);
1987 if (ret)
1988 goto err_unpin;
1989
1990 i915_gem_object_pin_fence(obj);
1991
1992 dev_priv->mm.interruptible = true;
1993 return 0;
1994
1995 err_unpin:
1996 i915_gem_object_unpin(obj);
1997 err_interruptible:
1998 dev_priv->mm.interruptible = true;
1999 return ret;
2000 }
2001
2002 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2003 {
2004 i915_gem_object_unpin_fence(obj);
2005 i915_gem_object_unpin(obj);
2006 }
2007
2008 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2009 * is assumed to be a power-of-two. */
2010 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2011 unsigned int bpp,
2012 unsigned int pitch)
2013 {
2014 int tile_rows, tiles;
2015
2016 tile_rows = *y / 8;
2017 *y %= 8;
2018 tiles = *x / (512/bpp);
2019 *x %= 512/bpp;
2020
2021 return tile_rows * pitch * 8 + tiles * 4096;
2022 }
2023
2024 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2025 int x, int y)
2026 {
2027 struct drm_device *dev = crtc->dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030 struct intel_framebuffer *intel_fb;
2031 struct drm_i915_gem_object *obj;
2032 int plane = intel_crtc->plane;
2033 unsigned long linear_offset;
2034 u32 dspcntr;
2035 u32 reg;
2036
2037 switch (plane) {
2038 case 0:
2039 case 1:
2040 break;
2041 default:
2042 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2043 return -EINVAL;
2044 }
2045
2046 intel_fb = to_intel_framebuffer(fb);
2047 obj = intel_fb->obj;
2048
2049 reg = DSPCNTR(plane);
2050 dspcntr = I915_READ(reg);
2051 /* Mask out pixel format bits in case we change it */
2052 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2053 switch (fb->pixel_format) {
2054 case DRM_FORMAT_C8:
2055 dspcntr |= DISPPLANE_8BPP;
2056 break;
2057 case DRM_FORMAT_XRGB1555:
2058 case DRM_FORMAT_ARGB1555:
2059 dspcntr |= DISPPLANE_BGRX555;
2060 break;
2061 case DRM_FORMAT_RGB565:
2062 dspcntr |= DISPPLANE_BGRX565;
2063 break;
2064 case DRM_FORMAT_XRGB8888:
2065 case DRM_FORMAT_ARGB8888:
2066 dspcntr |= DISPPLANE_BGRX888;
2067 break;
2068 case DRM_FORMAT_XBGR8888:
2069 case DRM_FORMAT_ABGR8888:
2070 dspcntr |= DISPPLANE_RGBX888;
2071 break;
2072 case DRM_FORMAT_XRGB2101010:
2073 case DRM_FORMAT_ARGB2101010:
2074 dspcntr |= DISPPLANE_BGRX101010;
2075 break;
2076 case DRM_FORMAT_XBGR2101010:
2077 case DRM_FORMAT_ABGR2101010:
2078 dspcntr |= DISPPLANE_RGBX101010;
2079 break;
2080 default:
2081 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2082 return -EINVAL;
2083 }
2084
2085 if (INTEL_INFO(dev)->gen >= 4) {
2086 if (obj->tiling_mode != I915_TILING_NONE)
2087 dspcntr |= DISPPLANE_TILED;
2088 else
2089 dspcntr &= ~DISPPLANE_TILED;
2090 }
2091
2092 I915_WRITE(reg, dspcntr);
2093
2094 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2095
2096 if (INTEL_INFO(dev)->gen >= 4) {
2097 intel_crtc->dspaddr_offset =
2098 intel_gen4_compute_offset_xtiled(&x, &y,
2099 fb->bits_per_pixel / 8,
2100 fb->pitches[0]);
2101 linear_offset -= intel_crtc->dspaddr_offset;
2102 } else {
2103 intel_crtc->dspaddr_offset = linear_offset;
2104 }
2105
2106 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2107 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2108 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2109 if (INTEL_INFO(dev)->gen >= 4) {
2110 I915_MODIFY_DISPBASE(DSPSURF(plane),
2111 obj->gtt_offset + intel_crtc->dspaddr_offset);
2112 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2113 I915_WRITE(DSPLINOFF(plane), linear_offset);
2114 } else
2115 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2116 POSTING_READ(reg);
2117
2118 return 0;
2119 }
2120
2121 static int ironlake_update_plane(struct drm_crtc *crtc,
2122 struct drm_framebuffer *fb, int x, int y)
2123 {
2124 struct drm_device *dev = crtc->dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127 struct intel_framebuffer *intel_fb;
2128 struct drm_i915_gem_object *obj;
2129 int plane = intel_crtc->plane;
2130 unsigned long linear_offset;
2131 u32 dspcntr;
2132 u32 reg;
2133
2134 switch (plane) {
2135 case 0:
2136 case 1:
2137 case 2:
2138 break;
2139 default:
2140 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2141 return -EINVAL;
2142 }
2143
2144 intel_fb = to_intel_framebuffer(fb);
2145 obj = intel_fb->obj;
2146
2147 reg = DSPCNTR(plane);
2148 dspcntr = I915_READ(reg);
2149 /* Mask out pixel format bits in case we change it */
2150 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2151 switch (fb->pixel_format) {
2152 case DRM_FORMAT_C8:
2153 dspcntr |= DISPPLANE_8BPP;
2154 break;
2155 case DRM_FORMAT_RGB565:
2156 dspcntr |= DISPPLANE_BGRX565;
2157 break;
2158 case DRM_FORMAT_XRGB8888:
2159 case DRM_FORMAT_ARGB8888:
2160 dspcntr |= DISPPLANE_BGRX888;
2161 break;
2162 case DRM_FORMAT_XBGR8888:
2163 case DRM_FORMAT_ABGR8888:
2164 dspcntr |= DISPPLANE_RGBX888;
2165 break;
2166 case DRM_FORMAT_XRGB2101010:
2167 case DRM_FORMAT_ARGB2101010:
2168 dspcntr |= DISPPLANE_BGRX101010;
2169 break;
2170 case DRM_FORMAT_XBGR2101010:
2171 case DRM_FORMAT_ABGR2101010:
2172 dspcntr |= DISPPLANE_RGBX101010;
2173 break;
2174 default:
2175 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2176 return -EINVAL;
2177 }
2178
2179 if (obj->tiling_mode != I915_TILING_NONE)
2180 dspcntr |= DISPPLANE_TILED;
2181 else
2182 dspcntr &= ~DISPPLANE_TILED;
2183
2184 /* must disable */
2185 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2186
2187 I915_WRITE(reg, dspcntr);
2188
2189 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2190 intel_crtc->dspaddr_offset =
2191 intel_gen4_compute_offset_xtiled(&x, &y,
2192 fb->bits_per_pixel / 8,
2193 fb->pitches[0]);
2194 linear_offset -= intel_crtc->dspaddr_offset;
2195
2196 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2197 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2198 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2199 I915_MODIFY_DISPBASE(DSPSURF(plane),
2200 obj->gtt_offset + intel_crtc->dspaddr_offset);
2201 if (IS_HASWELL(dev)) {
2202 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2203 } else {
2204 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2205 I915_WRITE(DSPLINOFF(plane), linear_offset);
2206 }
2207 POSTING_READ(reg);
2208
2209 return 0;
2210 }
2211
2212 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2213 static int
2214 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2215 int x, int y, enum mode_set_atomic state)
2216 {
2217 struct drm_device *dev = crtc->dev;
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2219
2220 if (dev_priv->display.disable_fbc)
2221 dev_priv->display.disable_fbc(dev);
2222 intel_increase_pllclock(crtc);
2223
2224 return dev_priv->display.update_plane(crtc, fb, x, y);
2225 }
2226
2227 static int
2228 intel_finish_fb(struct drm_framebuffer *old_fb)
2229 {
2230 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2231 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2232 bool was_interruptible = dev_priv->mm.interruptible;
2233 int ret;
2234
2235 wait_event(dev_priv->pending_flip_queue,
2236 atomic_read(&dev_priv->mm.wedged) ||
2237 atomic_read(&obj->pending_flip) == 0);
2238
2239 /* Big Hammer, we also need to ensure that any pending
2240 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2241 * current scanout is retired before unpinning the old
2242 * framebuffer.
2243 *
2244 * This should only fail upon a hung GPU, in which case we
2245 * can safely continue.
2246 */
2247 dev_priv->mm.interruptible = false;
2248 ret = i915_gem_object_finish_gpu(obj);
2249 dev_priv->mm.interruptible = was_interruptible;
2250
2251 return ret;
2252 }
2253
2254 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2255 {
2256 struct drm_device *dev = crtc->dev;
2257 struct drm_i915_master_private *master_priv;
2258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2259
2260 if (!dev->primary->master)
2261 return;
2262
2263 master_priv = dev->primary->master->driver_priv;
2264 if (!master_priv->sarea_priv)
2265 return;
2266
2267 switch (intel_crtc->pipe) {
2268 case 0:
2269 master_priv->sarea_priv->pipeA_x = x;
2270 master_priv->sarea_priv->pipeA_y = y;
2271 break;
2272 case 1:
2273 master_priv->sarea_priv->pipeB_x = x;
2274 master_priv->sarea_priv->pipeB_y = y;
2275 break;
2276 default:
2277 break;
2278 }
2279 }
2280
2281 static int
2282 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2283 struct drm_framebuffer *fb)
2284 {
2285 struct drm_device *dev = crtc->dev;
2286 struct drm_i915_private *dev_priv = dev->dev_private;
2287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2288 struct drm_framebuffer *old_fb;
2289 int ret;
2290
2291 /* no fb bound */
2292 if (!fb) {
2293 DRM_ERROR("No FB bound\n");
2294 return 0;
2295 }
2296
2297 if(intel_crtc->plane > dev_priv->num_pipe) {
2298 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2299 intel_crtc->plane,
2300 dev_priv->num_pipe);
2301 return -EINVAL;
2302 }
2303
2304 mutex_lock(&dev->struct_mutex);
2305 ret = intel_pin_and_fence_fb_obj(dev,
2306 to_intel_framebuffer(fb)->obj,
2307 NULL);
2308 if (ret != 0) {
2309 mutex_unlock(&dev->struct_mutex);
2310 DRM_ERROR("pin & fence failed\n");
2311 return ret;
2312 }
2313
2314 if (crtc->fb)
2315 intel_finish_fb(crtc->fb);
2316
2317 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2318 if (ret) {
2319 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2320 mutex_unlock(&dev->struct_mutex);
2321 DRM_ERROR("failed to update base address\n");
2322 return ret;
2323 }
2324
2325 old_fb = crtc->fb;
2326 crtc->fb = fb;
2327 crtc->x = x;
2328 crtc->y = y;
2329
2330 if (old_fb) {
2331 intel_wait_for_vblank(dev, intel_crtc->pipe);
2332 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2333 }
2334
2335 intel_update_fbc(dev);
2336 mutex_unlock(&dev->struct_mutex);
2337
2338 intel_crtc_update_sarea_pos(crtc, x, y);
2339
2340 return 0;
2341 }
2342
2343 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2344 {
2345 struct drm_device *dev = crtc->dev;
2346 struct drm_i915_private *dev_priv = dev->dev_private;
2347 u32 dpa_ctl;
2348
2349 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2350 dpa_ctl = I915_READ(DP_A);
2351 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2352
2353 if (clock < 200000) {
2354 u32 temp;
2355 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2356 /* workaround for 160Mhz:
2357 1) program 0x4600c bits 15:0 = 0x8124
2358 2) program 0x46010 bit 0 = 1
2359 3) program 0x46034 bit 24 = 1
2360 4) program 0x64000 bit 14 = 1
2361 */
2362 temp = I915_READ(0x4600c);
2363 temp &= 0xffff0000;
2364 I915_WRITE(0x4600c, temp | 0x8124);
2365
2366 temp = I915_READ(0x46010);
2367 I915_WRITE(0x46010, temp | 1);
2368
2369 temp = I915_READ(0x46034);
2370 I915_WRITE(0x46034, temp | (1 << 24));
2371 } else {
2372 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2373 }
2374 I915_WRITE(DP_A, dpa_ctl);
2375
2376 POSTING_READ(DP_A);
2377 udelay(500);
2378 }
2379
2380 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2381 {
2382 struct drm_device *dev = crtc->dev;
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385 int pipe = intel_crtc->pipe;
2386 u32 reg, temp;
2387
2388 /* enable normal train */
2389 reg = FDI_TX_CTL(pipe);
2390 temp = I915_READ(reg);
2391 if (IS_IVYBRIDGE(dev)) {
2392 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2393 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2394 } else {
2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2397 }
2398 I915_WRITE(reg, temp);
2399
2400 reg = FDI_RX_CTL(pipe);
2401 temp = I915_READ(reg);
2402 if (HAS_PCH_CPT(dev)) {
2403 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2404 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2405 } else {
2406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_NONE;
2408 }
2409 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2410
2411 /* wait one idle pattern time */
2412 POSTING_READ(reg);
2413 udelay(1000);
2414
2415 /* IVB wants error correction enabled */
2416 if (IS_IVYBRIDGE(dev))
2417 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2418 FDI_FE_ERRC_ENABLE);
2419 }
2420
2421 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2422 {
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 u32 flags = I915_READ(SOUTH_CHICKEN1);
2425
2426 flags |= FDI_PHASE_SYNC_OVR(pipe);
2427 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2428 flags |= FDI_PHASE_SYNC_EN(pipe);
2429 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2430 POSTING_READ(SOUTH_CHICKEN1);
2431 }
2432
2433 static void ivb_modeset_global_resources(struct drm_device *dev)
2434 {
2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 struct intel_crtc *pipe_B_crtc =
2437 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2438 struct intel_crtc *pipe_C_crtc =
2439 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2440 uint32_t temp;
2441
2442 /* When everything is off disable fdi C so that we could enable fdi B
2443 * with all lanes. XXX: This misses the case where a pipe is not using
2444 * any pch resources and so doesn't need any fdi lanes. */
2445 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448
2449 temp = I915_READ(SOUTH_CHICKEN1);
2450 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1, temp);
2453 }
2454 }
2455
2456 /* The FDI link training functions for ILK/Ibexpeak. */
2457 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458 {
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
2463 int plane = intel_crtc->plane;
2464 u32 reg, temp, tries;
2465
2466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv, pipe);
2468 assert_plane_enabled(dev_priv, plane);
2469
2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 for train result */
2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
2476 I915_WRITE(reg, temp);
2477 I915_READ(reg);
2478 udelay(150);
2479
2480 /* enable CPU FDI TX and PCH FDI RX */
2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~(7 << 19);
2484 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
2487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2488
2489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2494
2495 POSTING_READ(reg);
2496 udelay(150);
2497
2498 /* Ironlake workaround, enable clock pointer after FDI enable*/
2499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501 FDI_RX_PHASE_SYNC_POINTER_EN);
2502
2503 reg = FDI_RX_IIR(pipe);
2504 for (tries = 0; tries < 5; tries++) {
2505 temp = I915_READ(reg);
2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508 if ((temp & FDI_RX_BIT_LOCK)) {
2509 DRM_DEBUG_KMS("FDI train 1 done.\n");
2510 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2511 break;
2512 }
2513 }
2514 if (tries == 5)
2515 DRM_ERROR("FDI train 1 fail!\n");
2516
2517 /* Train 2 */
2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
2522 I915_WRITE(reg, temp);
2523
2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
2528 I915_WRITE(reg, temp);
2529
2530 POSTING_READ(reg);
2531 udelay(150);
2532
2533 reg = FDI_RX_IIR(pipe);
2534 for (tries = 0; tries < 5; tries++) {
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_SYMBOL_LOCK) {
2539 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2540 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541 break;
2542 }
2543 }
2544 if (tries == 5)
2545 DRM_ERROR("FDI train 2 fail!\n");
2546
2547 DRM_DEBUG_KMS("FDI train done\n");
2548
2549 }
2550
2551 static const int snb_b_fdi_train_param[] = {
2552 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2553 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2554 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2555 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2556 };
2557
2558 /* The FDI link training functions for SNB/Cougarpoint. */
2559 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2560 {
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
2565 u32 reg, temp, i, retry;
2566
2567 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2568 for train result */
2569 reg = FDI_RX_IMR(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_RX_SYMBOL_LOCK;
2572 temp &= ~FDI_RX_BIT_LOCK;
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(150);
2577
2578 /* enable CPU FDI TX and PCH FDI RX */
2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
2581 temp &= ~(7 << 19);
2582 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1;
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 /* SNB-B */
2587 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2588 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2589
2590 I915_WRITE(FDI_RX_MISC(pipe),
2591 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2592
2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_1;
2601 }
2602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604 POSTING_READ(reg);
2605 udelay(150);
2606
2607 cpt_phase_pointer_enable(dev, pipe);
2608
2609 for (i = 0; i < 4; i++) {
2610 reg = FDI_TX_CTL(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613 temp |= snb_b_fdi_train_param[i];
2614 I915_WRITE(reg, temp);
2615
2616 POSTING_READ(reg);
2617 udelay(500);
2618
2619 for (retry = 0; retry < 5; retry++) {
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623 if (temp & FDI_RX_BIT_LOCK) {
2624 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2625 DRM_DEBUG_KMS("FDI train 1 done.\n");
2626 break;
2627 }
2628 udelay(50);
2629 }
2630 if (retry < 5)
2631 break;
2632 }
2633 if (i == 4)
2634 DRM_ERROR("FDI train 1 fail!\n");
2635
2636 /* Train 2 */
2637 reg = FDI_TX_CTL(pipe);
2638 temp = I915_READ(reg);
2639 temp &= ~FDI_LINK_TRAIN_NONE;
2640 temp |= FDI_LINK_TRAIN_PATTERN_2;
2641 if (IS_GEN6(dev)) {
2642 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643 /* SNB-B */
2644 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2645 }
2646 I915_WRITE(reg, temp);
2647
2648 reg = FDI_RX_CTL(pipe);
2649 temp = I915_READ(reg);
2650 if (HAS_PCH_CPT(dev)) {
2651 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2652 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2653 } else {
2654 temp &= ~FDI_LINK_TRAIN_NONE;
2655 temp |= FDI_LINK_TRAIN_PATTERN_2;
2656 }
2657 I915_WRITE(reg, temp);
2658
2659 POSTING_READ(reg);
2660 udelay(150);
2661
2662 for (i = 0; i < 4; i++) {
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666 temp |= snb_b_fdi_train_param[i];
2667 I915_WRITE(reg, temp);
2668
2669 POSTING_READ(reg);
2670 udelay(500);
2671
2672 for (retry = 0; retry < 5; retry++) {
2673 reg = FDI_RX_IIR(pipe);
2674 temp = I915_READ(reg);
2675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2676 if (temp & FDI_RX_SYMBOL_LOCK) {
2677 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2678 DRM_DEBUG_KMS("FDI train 2 done.\n");
2679 break;
2680 }
2681 udelay(50);
2682 }
2683 if (retry < 5)
2684 break;
2685 }
2686 if (i == 4)
2687 DRM_ERROR("FDI train 2 fail!\n");
2688
2689 DRM_DEBUG_KMS("FDI train done.\n");
2690 }
2691
2692 /* Manual link training for Ivy Bridge A0 parts */
2693 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2694 {
2695 struct drm_device *dev = crtc->dev;
2696 struct drm_i915_private *dev_priv = dev->dev_private;
2697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2698 int pipe = intel_crtc->pipe;
2699 u32 reg, temp, i;
2700
2701 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2702 for train result */
2703 reg = FDI_RX_IMR(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_RX_SYMBOL_LOCK;
2706 temp &= ~FDI_RX_BIT_LOCK;
2707 I915_WRITE(reg, temp);
2708
2709 POSTING_READ(reg);
2710 udelay(150);
2711
2712 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2713 I915_READ(FDI_RX_IIR(pipe)));
2714
2715 /* enable CPU FDI TX and PCH FDI RX */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(7 << 19);
2719 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2720 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2721 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2722 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2723 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2724 temp |= FDI_COMPOSITE_SYNC;
2725 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2726
2727 I915_WRITE(FDI_RX_MISC(pipe),
2728 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2729
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~FDI_LINK_TRAIN_AUTO;
2733 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2735 temp |= FDI_COMPOSITE_SYNC;
2736 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2737
2738 POSTING_READ(reg);
2739 udelay(150);
2740
2741 cpt_phase_pointer_enable(dev, pipe);
2742
2743 for (i = 0; i < 4; i++) {
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2747 temp |= snb_b_fdi_train_param[i];
2748 I915_WRITE(reg, temp);
2749
2750 POSTING_READ(reg);
2751 udelay(500);
2752
2753 reg = FDI_RX_IIR(pipe);
2754 temp = I915_READ(reg);
2755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2756
2757 if (temp & FDI_RX_BIT_LOCK ||
2758 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2761 break;
2762 }
2763 }
2764 if (i == 4)
2765 DRM_ERROR("FDI train 1 fail!\n");
2766
2767 /* Train 2 */
2768 reg = FDI_TX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2771 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2772 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2773 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2774 I915_WRITE(reg, temp);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2779 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2780 I915_WRITE(reg, temp);
2781
2782 POSTING_READ(reg);
2783 udelay(150);
2784
2785 for (i = 0; i < 4; i++) {
2786 reg = FDI_TX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2789 temp |= snb_b_fdi_train_param[i];
2790 I915_WRITE(reg, temp);
2791
2792 POSTING_READ(reg);
2793 udelay(500);
2794
2795 reg = FDI_RX_IIR(pipe);
2796 temp = I915_READ(reg);
2797 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2798
2799 if (temp & FDI_RX_SYMBOL_LOCK) {
2800 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2801 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2802 break;
2803 }
2804 }
2805 if (i == 4)
2806 DRM_ERROR("FDI train 2 fail!\n");
2807
2808 DRM_DEBUG_KMS("FDI train done.\n");
2809 }
2810
2811 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2812 {
2813 struct drm_device *dev = intel_crtc->base.dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 int pipe = intel_crtc->pipe;
2816 u32 reg, temp;
2817
2818
2819 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2820 reg = FDI_RX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 temp &= ~((0x7 << 19) | (0x7 << 16));
2823 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2826
2827 POSTING_READ(reg);
2828 udelay(200);
2829
2830 /* Switch from Rawclk to PCDclk */
2831 temp = I915_READ(reg);
2832 I915_WRITE(reg, temp | FDI_PCDCLK);
2833
2834 POSTING_READ(reg);
2835 udelay(200);
2836
2837 /* On Haswell, the PLL configuration for ports and pipes is handled
2838 * separately, as part of DDI setup */
2839 if (!IS_HASWELL(dev)) {
2840 /* Enable CPU FDI TX PLL, always on for Ironlake */
2841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2844 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2845
2846 POSTING_READ(reg);
2847 udelay(100);
2848 }
2849 }
2850 }
2851
2852 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2853 {
2854 struct drm_device *dev = intel_crtc->base.dev;
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856 int pipe = intel_crtc->pipe;
2857 u32 reg, temp;
2858
2859 /* Switch from PCDclk to Rawclk */
2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2863
2864 /* Disable CPU FDI TX PLL */
2865 reg = FDI_TX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871
2872 reg = FDI_RX_CTL(pipe);
2873 temp = I915_READ(reg);
2874 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2875
2876 /* Wait for the clocks to turn off. */
2877 POSTING_READ(reg);
2878 udelay(100);
2879 }
2880
2881 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2882 {
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 u32 flags = I915_READ(SOUTH_CHICKEN1);
2885
2886 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2887 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2888 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2889 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2890 POSTING_READ(SOUTH_CHICKEN1);
2891 }
2892 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2893 {
2894 struct drm_device *dev = crtc->dev;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2897 int pipe = intel_crtc->pipe;
2898 u32 reg, temp;
2899
2900 /* disable CPU FDI tx and PCH FDI rx */
2901 reg = FDI_TX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2904 POSTING_READ(reg);
2905
2906 reg = FDI_RX_CTL(pipe);
2907 temp = I915_READ(reg);
2908 temp &= ~(0x7 << 16);
2909 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2910 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2911
2912 POSTING_READ(reg);
2913 udelay(100);
2914
2915 /* Ironlake workaround, disable clock pointer after downing FDI */
2916 if (HAS_PCH_IBX(dev)) {
2917 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2918 } else if (HAS_PCH_CPT(dev)) {
2919 cpt_phase_pointer_disable(dev, pipe);
2920 }
2921
2922 /* still set train pattern 1 */
2923 reg = FDI_TX_CTL(pipe);
2924 temp = I915_READ(reg);
2925 temp &= ~FDI_LINK_TRAIN_NONE;
2926 temp |= FDI_LINK_TRAIN_PATTERN_1;
2927 I915_WRITE(reg, temp);
2928
2929 reg = FDI_RX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 if (HAS_PCH_CPT(dev)) {
2932 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2933 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2934 } else {
2935 temp &= ~FDI_LINK_TRAIN_NONE;
2936 temp |= FDI_LINK_TRAIN_PATTERN_1;
2937 }
2938 /* BPC in FDI rx is consistent with that in PIPECONF */
2939 temp &= ~(0x07 << 16);
2940 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2941 I915_WRITE(reg, temp);
2942
2943 POSTING_READ(reg);
2944 udelay(100);
2945 }
2946
2947 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2948 {
2949 struct drm_device *dev = crtc->dev;
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2951 unsigned long flags;
2952 bool pending;
2953
2954 if (atomic_read(&dev_priv->mm.wedged))
2955 return false;
2956
2957 spin_lock_irqsave(&dev->event_lock, flags);
2958 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2959 spin_unlock_irqrestore(&dev->event_lock, flags);
2960
2961 return pending;
2962 }
2963
2964 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2965 {
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968
2969 if (crtc->fb == NULL)
2970 return;
2971
2972 wait_event(dev_priv->pending_flip_queue,
2973 !intel_crtc_has_pending_flip(crtc));
2974
2975 mutex_lock(&dev->struct_mutex);
2976 intel_finish_fb(crtc->fb);
2977 mutex_unlock(&dev->struct_mutex);
2978 }
2979
2980 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2981 {
2982 struct drm_device *dev = crtc->dev;
2983 struct intel_encoder *intel_encoder;
2984
2985 /*
2986 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2987 * must be driven by its own crtc; no sharing is possible.
2988 */
2989 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2990 switch (intel_encoder->type) {
2991 case INTEL_OUTPUT_EDP:
2992 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2993 return false;
2994 continue;
2995 }
2996 }
2997
2998 return true;
2999 }
3000
3001 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3002 {
3003 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3004 }
3005
3006 /* Program iCLKIP clock to the desired frequency */
3007 static void lpt_program_iclkip(struct drm_crtc *crtc)
3008 {
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3012 u32 temp;
3013
3014 /* It is necessary to ungate the pixclk gate prior to programming
3015 * the divisors, and gate it back when it is done.
3016 */
3017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3018
3019 /* Disable SSCCTL */
3020 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3021 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3022 SBI_SSCCTL_DISABLE);
3023
3024 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3025 if (crtc->mode.clock == 20000) {
3026 auxdiv = 1;
3027 divsel = 0x41;
3028 phaseinc = 0x20;
3029 } else {
3030 /* The iCLK virtual clock root frequency is in MHz,
3031 * but the crtc->mode.clock in in KHz. To get the divisors,
3032 * it is necessary to divide one by another, so we
3033 * convert the virtual clock precision to KHz here for higher
3034 * precision.
3035 */
3036 u32 iclk_virtual_root_freq = 172800 * 1000;
3037 u32 iclk_pi_range = 64;
3038 u32 desired_divisor, msb_divisor_value, pi_value;
3039
3040 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3041 msb_divisor_value = desired_divisor / iclk_pi_range;
3042 pi_value = desired_divisor % iclk_pi_range;
3043
3044 auxdiv = 0;
3045 divsel = msb_divisor_value - 2;
3046 phaseinc = pi_value;
3047 }
3048
3049 /* This should not happen with any sane values */
3050 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3051 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3052 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3053 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3054
3055 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3056 crtc->mode.clock,
3057 auxdiv,
3058 divsel,
3059 phasedir,
3060 phaseinc);
3061
3062 /* Program SSCDIVINTPHASE6 */
3063 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3064 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3065 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3066 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3067 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3068 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3069 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3070
3071 intel_sbi_write(dev_priv,
3072 SBI_SSCDIVINTPHASE6,
3073 temp);
3074
3075 /* Program SSCAUXDIV */
3076 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3077 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3078 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3079 intel_sbi_write(dev_priv,
3080 SBI_SSCAUXDIV6,
3081 temp);
3082
3083
3084 /* Enable modulator and associated divider */
3085 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3086 temp &= ~SBI_SSCCTL_DISABLE;
3087 intel_sbi_write(dev_priv,
3088 SBI_SSCCTL6,
3089 temp);
3090
3091 /* Wait for initialization time */
3092 udelay(24);
3093
3094 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3095 }
3096
3097 /*
3098 * Enable PCH resources required for PCH ports:
3099 * - PCH PLLs
3100 * - FDI training & RX/TX
3101 * - update transcoder timings
3102 * - DP transcoding bits
3103 * - transcoder
3104 */
3105 static void ironlake_pch_enable(struct drm_crtc *crtc)
3106 {
3107 struct drm_device *dev = crtc->dev;
3108 struct drm_i915_private *dev_priv = dev->dev_private;
3109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3110 int pipe = intel_crtc->pipe;
3111 u32 reg, temp;
3112
3113 assert_transcoder_disabled(dev_priv, pipe);
3114
3115 /* Write the TU size bits before fdi link training, so that error
3116 * detection works. */
3117 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3118 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3119
3120 /* For PCH output, training FDI link */
3121 dev_priv->display.fdi_link_train(crtc);
3122
3123 /* XXX: pch pll's can be enabled any time before we enable the PCH
3124 * transcoder, and we actually should do this to not upset any PCH
3125 * transcoder that already use the clock when we share it.
3126 *
3127 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3128 * unconditionally resets the pll - we need that to have the right LVDS
3129 * enable sequence. */
3130 ironlake_enable_pch_pll(intel_crtc);
3131
3132 if (HAS_PCH_CPT(dev)) {
3133 u32 sel;
3134
3135 temp = I915_READ(PCH_DPLL_SEL);
3136 switch (pipe) {
3137 default:
3138 case 0:
3139 temp |= TRANSA_DPLL_ENABLE;
3140 sel = TRANSA_DPLLB_SEL;
3141 break;
3142 case 1:
3143 temp |= TRANSB_DPLL_ENABLE;
3144 sel = TRANSB_DPLLB_SEL;
3145 break;
3146 case 2:
3147 temp |= TRANSC_DPLL_ENABLE;
3148 sel = TRANSC_DPLLB_SEL;
3149 break;
3150 }
3151 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3152 temp |= sel;
3153 else
3154 temp &= ~sel;
3155 I915_WRITE(PCH_DPLL_SEL, temp);
3156 }
3157
3158 /* set transcoder timing, panel must allow it */
3159 assert_panel_unlocked(dev_priv, pipe);
3160 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3161 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3162 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3163
3164 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3165 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3166 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3167 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3168
3169 intel_fdi_normal_train(crtc);
3170
3171 /* For PCH DP, enable TRANS_DP_CTL */
3172 if (HAS_PCH_CPT(dev) &&
3173 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3174 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3175 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3176 reg = TRANS_DP_CTL(pipe);
3177 temp = I915_READ(reg);
3178 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3179 TRANS_DP_SYNC_MASK |
3180 TRANS_DP_BPC_MASK);
3181 temp |= (TRANS_DP_OUTPUT_ENABLE |
3182 TRANS_DP_ENH_FRAMING);
3183 temp |= bpc << 9; /* same format but at 11:9 */
3184
3185 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3186 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3187 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3188 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3189
3190 switch (intel_trans_dp_port_sel(crtc)) {
3191 case PCH_DP_B:
3192 temp |= TRANS_DP_PORT_SEL_B;
3193 break;
3194 case PCH_DP_C:
3195 temp |= TRANS_DP_PORT_SEL_C;
3196 break;
3197 case PCH_DP_D:
3198 temp |= TRANS_DP_PORT_SEL_D;
3199 break;
3200 default:
3201 BUG();
3202 }
3203
3204 I915_WRITE(reg, temp);
3205 }
3206
3207 ironlake_enable_pch_transcoder(dev_priv, pipe);
3208 }
3209
3210 static void lpt_pch_enable(struct drm_crtc *crtc)
3211 {
3212 struct drm_device *dev = crtc->dev;
3213 struct drm_i915_private *dev_priv = dev->dev_private;
3214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3216
3217 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3218
3219 lpt_program_iclkip(crtc);
3220
3221 /* Set transcoder timing. */
3222 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3223 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3224 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3225
3226 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3227 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3228 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3229 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3230
3231 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3232 }
3233
3234 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3235 {
3236 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3237
3238 if (pll == NULL)
3239 return;
3240
3241 if (pll->refcount == 0) {
3242 WARN(1, "bad PCH PLL refcount\n");
3243 return;
3244 }
3245
3246 --pll->refcount;
3247 intel_crtc->pch_pll = NULL;
3248 }
3249
3250 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3251 {
3252 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3253 struct intel_pch_pll *pll;
3254 int i;
3255
3256 pll = intel_crtc->pch_pll;
3257 if (pll) {
3258 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3259 intel_crtc->base.base.id, pll->pll_reg);
3260 goto prepare;
3261 }
3262
3263 if (HAS_PCH_IBX(dev_priv->dev)) {
3264 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3265 i = intel_crtc->pipe;
3266 pll = &dev_priv->pch_plls[i];
3267
3268 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3269 intel_crtc->base.base.id, pll->pll_reg);
3270
3271 goto found;
3272 }
3273
3274 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3275 pll = &dev_priv->pch_plls[i];
3276
3277 /* Only want to check enabled timings first */
3278 if (pll->refcount == 0)
3279 continue;
3280
3281 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3282 fp == I915_READ(pll->fp0_reg)) {
3283 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3284 intel_crtc->base.base.id,
3285 pll->pll_reg, pll->refcount, pll->active);
3286
3287 goto found;
3288 }
3289 }
3290
3291 /* Ok no matching timings, maybe there's a free one? */
3292 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3293 pll = &dev_priv->pch_plls[i];
3294 if (pll->refcount == 0) {
3295 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3296 intel_crtc->base.base.id, pll->pll_reg);
3297 goto found;
3298 }
3299 }
3300
3301 return NULL;
3302
3303 found:
3304 intel_crtc->pch_pll = pll;
3305 pll->refcount++;
3306 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3307 prepare: /* separate function? */
3308 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3309
3310 /* Wait for the clocks to stabilize before rewriting the regs */
3311 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3312 POSTING_READ(pll->pll_reg);
3313 udelay(150);
3314
3315 I915_WRITE(pll->fp0_reg, fp);
3316 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3317 pll->on = false;
3318 return pll;
3319 }
3320
3321 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3322 {
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 int dslreg = PIPEDSL(pipe);
3325 u32 temp;
3326
3327 temp = I915_READ(dslreg);
3328 udelay(500);
3329 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3330 if (wait_for(I915_READ(dslreg) != temp, 5))
3331 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3332 }
3333 }
3334
3335 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3336 {
3337 struct drm_device *dev = crtc->dev;
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3340 struct intel_encoder *encoder;
3341 int pipe = intel_crtc->pipe;
3342 int plane = intel_crtc->plane;
3343 u32 temp;
3344 bool is_pch_port;
3345
3346 WARN_ON(!crtc->enabled);
3347
3348 if (intel_crtc->active)
3349 return;
3350
3351 intel_crtc->active = true;
3352 intel_update_watermarks(dev);
3353
3354 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3355 temp = I915_READ(PCH_LVDS);
3356 if ((temp & LVDS_PORT_EN) == 0)
3357 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3358 }
3359
3360 is_pch_port = ironlake_crtc_driving_pch(crtc);
3361
3362 if (is_pch_port) {
3363 /* Note: FDI PLL enabling _must_ be done before we enable the
3364 * cpu pipes, hence this is separate from all the other fdi/pch
3365 * enabling. */
3366 ironlake_fdi_pll_enable(intel_crtc);
3367 } else {
3368 assert_fdi_tx_disabled(dev_priv, pipe);
3369 assert_fdi_rx_disabled(dev_priv, pipe);
3370 }
3371
3372 for_each_encoder_on_crtc(dev, crtc, encoder)
3373 if (encoder->pre_enable)
3374 encoder->pre_enable(encoder);
3375
3376 /* Enable panel fitting for LVDS */
3377 if (dev_priv->pch_pf_size &&
3378 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3379 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3380 /* Force use of hard-coded filter coefficients
3381 * as some pre-programmed values are broken,
3382 * e.g. x201.
3383 */
3384 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3385 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3386 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3387 }
3388
3389 /*
3390 * On ILK+ LUT must be loaded before the pipe is running but with
3391 * clocks enabled
3392 */
3393 intel_crtc_load_lut(crtc);
3394
3395 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3396 intel_enable_plane(dev_priv, plane, pipe);
3397
3398 if (is_pch_port)
3399 ironlake_pch_enable(crtc);
3400
3401 mutex_lock(&dev->struct_mutex);
3402 intel_update_fbc(dev);
3403 mutex_unlock(&dev->struct_mutex);
3404
3405 intel_crtc_update_cursor(crtc, true);
3406
3407 for_each_encoder_on_crtc(dev, crtc, encoder)
3408 encoder->enable(encoder);
3409
3410 if (HAS_PCH_CPT(dev))
3411 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3412
3413 /*
3414 * There seems to be a race in PCH platform hw (at least on some
3415 * outputs) where an enabled pipe still completes any pageflip right
3416 * away (as if the pipe is off) instead of waiting for vblank. As soon
3417 * as the first vblank happend, everything works as expected. Hence just
3418 * wait for one vblank before returning to avoid strange things
3419 * happening.
3420 */
3421 intel_wait_for_vblank(dev, intel_crtc->pipe);
3422 }
3423
3424 static void haswell_crtc_enable(struct drm_crtc *crtc)
3425 {
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429 struct intel_encoder *encoder;
3430 int pipe = intel_crtc->pipe;
3431 int plane = intel_crtc->plane;
3432 bool is_pch_port;
3433
3434 WARN_ON(!crtc->enabled);
3435
3436 if (intel_crtc->active)
3437 return;
3438
3439 intel_crtc->active = true;
3440 intel_update_watermarks(dev);
3441
3442 is_pch_port = haswell_crtc_driving_pch(crtc);
3443
3444 if (is_pch_port)
3445 dev_priv->display.fdi_link_train(crtc);
3446
3447 for_each_encoder_on_crtc(dev, crtc, encoder)
3448 if (encoder->pre_enable)
3449 encoder->pre_enable(encoder);
3450
3451 intel_ddi_enable_pipe_clock(intel_crtc);
3452
3453 /* Enable panel fitting for eDP */
3454 if (dev_priv->pch_pf_size &&
3455 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3456 /* Force use of hard-coded filter coefficients
3457 * as some pre-programmed values are broken,
3458 * e.g. x201.
3459 */
3460 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3461 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3462 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3463 }
3464
3465 /*
3466 * On ILK+ LUT must be loaded before the pipe is running but with
3467 * clocks enabled
3468 */
3469 intel_crtc_load_lut(crtc);
3470
3471 intel_ddi_set_pipe_settings(crtc);
3472 intel_ddi_enable_pipe_func(crtc);
3473
3474 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3475 intel_enable_plane(dev_priv, plane, pipe);
3476
3477 if (is_pch_port)
3478 lpt_pch_enable(crtc);
3479
3480 mutex_lock(&dev->struct_mutex);
3481 intel_update_fbc(dev);
3482 mutex_unlock(&dev->struct_mutex);
3483
3484 intel_crtc_update_cursor(crtc, true);
3485
3486 for_each_encoder_on_crtc(dev, crtc, encoder)
3487 encoder->enable(encoder);
3488
3489 /*
3490 * There seems to be a race in PCH platform hw (at least on some
3491 * outputs) where an enabled pipe still completes any pageflip right
3492 * away (as if the pipe is off) instead of waiting for vblank. As soon
3493 * as the first vblank happend, everything works as expected. Hence just
3494 * wait for one vblank before returning to avoid strange things
3495 * happening.
3496 */
3497 intel_wait_for_vblank(dev, intel_crtc->pipe);
3498 }
3499
3500 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3501 {
3502 struct drm_device *dev = crtc->dev;
3503 struct drm_i915_private *dev_priv = dev->dev_private;
3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3505 struct intel_encoder *encoder;
3506 int pipe = intel_crtc->pipe;
3507 int plane = intel_crtc->plane;
3508 u32 reg, temp;
3509
3510
3511 if (!intel_crtc->active)
3512 return;
3513
3514 for_each_encoder_on_crtc(dev, crtc, encoder)
3515 encoder->disable(encoder);
3516
3517 intel_crtc_wait_for_pending_flips(crtc);
3518 drm_vblank_off(dev, pipe);
3519 intel_crtc_update_cursor(crtc, false);
3520
3521 intel_disable_plane(dev_priv, plane, pipe);
3522
3523 if (dev_priv->cfb_plane == plane)
3524 intel_disable_fbc(dev);
3525
3526 intel_disable_pipe(dev_priv, pipe);
3527
3528 /* Disable PF */
3529 I915_WRITE(PF_CTL(pipe), 0);
3530 I915_WRITE(PF_WIN_SZ(pipe), 0);
3531
3532 for_each_encoder_on_crtc(dev, crtc, encoder)
3533 if (encoder->post_disable)
3534 encoder->post_disable(encoder);
3535
3536 ironlake_fdi_disable(crtc);
3537
3538 ironlake_disable_pch_transcoder(dev_priv, pipe);
3539
3540 if (HAS_PCH_CPT(dev)) {
3541 /* disable TRANS_DP_CTL */
3542 reg = TRANS_DP_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3545 temp |= TRANS_DP_PORT_SEL_NONE;
3546 I915_WRITE(reg, temp);
3547
3548 /* disable DPLL_SEL */
3549 temp = I915_READ(PCH_DPLL_SEL);
3550 switch (pipe) {
3551 case 0:
3552 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3553 break;
3554 case 1:
3555 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3556 break;
3557 case 2:
3558 /* C shares PLL A or B */
3559 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3560 break;
3561 default:
3562 BUG(); /* wtf */
3563 }
3564 I915_WRITE(PCH_DPLL_SEL, temp);
3565 }
3566
3567 /* disable PCH DPLL */
3568 intel_disable_pch_pll(intel_crtc);
3569
3570 ironlake_fdi_pll_disable(intel_crtc);
3571
3572 intel_crtc->active = false;
3573 intel_update_watermarks(dev);
3574
3575 mutex_lock(&dev->struct_mutex);
3576 intel_update_fbc(dev);
3577 mutex_unlock(&dev->struct_mutex);
3578 }
3579
3580 static void haswell_crtc_disable(struct drm_crtc *crtc)
3581 {
3582 struct drm_device *dev = crtc->dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3585 struct intel_encoder *encoder;
3586 int pipe = intel_crtc->pipe;
3587 int plane = intel_crtc->plane;
3588 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3589 bool is_pch_port;
3590
3591 if (!intel_crtc->active)
3592 return;
3593
3594 is_pch_port = haswell_crtc_driving_pch(crtc);
3595
3596 for_each_encoder_on_crtc(dev, crtc, encoder)
3597 encoder->disable(encoder);
3598
3599 intel_crtc_wait_for_pending_flips(crtc);
3600 drm_vblank_off(dev, pipe);
3601 intel_crtc_update_cursor(crtc, false);
3602
3603 intel_disable_plane(dev_priv, plane, pipe);
3604
3605 if (dev_priv->cfb_plane == plane)
3606 intel_disable_fbc(dev);
3607
3608 intel_disable_pipe(dev_priv, pipe);
3609
3610 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3611
3612 /* Disable PF */
3613 I915_WRITE(PF_CTL(pipe), 0);
3614 I915_WRITE(PF_WIN_SZ(pipe), 0);
3615
3616 intel_ddi_disable_pipe_clock(intel_crtc);
3617
3618 for_each_encoder_on_crtc(dev, crtc, encoder)
3619 if (encoder->post_disable)
3620 encoder->post_disable(encoder);
3621
3622 if (is_pch_port) {
3623 lpt_disable_pch_transcoder(dev_priv);
3624 intel_ddi_fdi_disable(crtc);
3625 }
3626
3627 intel_crtc->active = false;
3628 intel_update_watermarks(dev);
3629
3630 mutex_lock(&dev->struct_mutex);
3631 intel_update_fbc(dev);
3632 mutex_unlock(&dev->struct_mutex);
3633 }
3634
3635 static void ironlake_crtc_off(struct drm_crtc *crtc)
3636 {
3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638 intel_put_pch_pll(intel_crtc);
3639 }
3640
3641 static void haswell_crtc_off(struct drm_crtc *crtc)
3642 {
3643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644
3645 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3646 * start using it. */
3647 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3648
3649 intel_ddi_put_crtc_pll(crtc);
3650 }
3651
3652 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3653 {
3654 if (!enable && intel_crtc->overlay) {
3655 struct drm_device *dev = intel_crtc->base.dev;
3656 struct drm_i915_private *dev_priv = dev->dev_private;
3657
3658 mutex_lock(&dev->struct_mutex);
3659 dev_priv->mm.interruptible = false;
3660 (void) intel_overlay_switch_off(intel_crtc->overlay);
3661 dev_priv->mm.interruptible = true;
3662 mutex_unlock(&dev->struct_mutex);
3663 }
3664
3665 /* Let userspace switch the overlay on again. In most cases userspace
3666 * has to recompute where to put it anyway.
3667 */
3668 }
3669
3670 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3671 {
3672 struct drm_device *dev = crtc->dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3675 struct intel_encoder *encoder;
3676 int pipe = intel_crtc->pipe;
3677 int plane = intel_crtc->plane;
3678
3679 WARN_ON(!crtc->enabled);
3680
3681 if (intel_crtc->active)
3682 return;
3683
3684 intel_crtc->active = true;
3685 intel_update_watermarks(dev);
3686
3687 intel_enable_pll(dev_priv, pipe);
3688 intel_enable_pipe(dev_priv, pipe, false);
3689 intel_enable_plane(dev_priv, plane, pipe);
3690
3691 intel_crtc_load_lut(crtc);
3692 intel_update_fbc(dev);
3693
3694 /* Give the overlay scaler a chance to enable if it's on this pipe */
3695 intel_crtc_dpms_overlay(intel_crtc, true);
3696 intel_crtc_update_cursor(crtc, true);
3697
3698 for_each_encoder_on_crtc(dev, crtc, encoder)
3699 encoder->enable(encoder);
3700 }
3701
3702 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3703 {
3704 struct drm_device *dev = crtc->dev;
3705 struct drm_i915_private *dev_priv = dev->dev_private;
3706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3707 struct intel_encoder *encoder;
3708 int pipe = intel_crtc->pipe;
3709 int plane = intel_crtc->plane;
3710
3711
3712 if (!intel_crtc->active)
3713 return;
3714
3715 for_each_encoder_on_crtc(dev, crtc, encoder)
3716 encoder->disable(encoder);
3717
3718 /* Give the overlay scaler a chance to disable if it's on this pipe */
3719 intel_crtc_wait_for_pending_flips(crtc);
3720 drm_vblank_off(dev, pipe);
3721 intel_crtc_dpms_overlay(intel_crtc, false);
3722 intel_crtc_update_cursor(crtc, false);
3723
3724 if (dev_priv->cfb_plane == plane)
3725 intel_disable_fbc(dev);
3726
3727 intel_disable_plane(dev_priv, plane, pipe);
3728 intel_disable_pipe(dev_priv, pipe);
3729 intel_disable_pll(dev_priv, pipe);
3730
3731 intel_crtc->active = false;
3732 intel_update_fbc(dev);
3733 intel_update_watermarks(dev);
3734 }
3735
3736 static void i9xx_crtc_off(struct drm_crtc *crtc)
3737 {
3738 }
3739
3740 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3741 bool enabled)
3742 {
3743 struct drm_device *dev = crtc->dev;
3744 struct drm_i915_master_private *master_priv;
3745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3746 int pipe = intel_crtc->pipe;
3747
3748 if (!dev->primary->master)
3749 return;
3750
3751 master_priv = dev->primary->master->driver_priv;
3752 if (!master_priv->sarea_priv)
3753 return;
3754
3755 switch (pipe) {
3756 case 0:
3757 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3758 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3759 break;
3760 case 1:
3761 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3762 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3763 break;
3764 default:
3765 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3766 break;
3767 }
3768 }
3769
3770 /**
3771 * Sets the power management mode of the pipe and plane.
3772 */
3773 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3774 {
3775 struct drm_device *dev = crtc->dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 struct intel_encoder *intel_encoder;
3778 bool enable = false;
3779
3780 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3781 enable |= intel_encoder->connectors_active;
3782
3783 if (enable)
3784 dev_priv->display.crtc_enable(crtc);
3785 else
3786 dev_priv->display.crtc_disable(crtc);
3787
3788 intel_crtc_update_sarea(crtc, enable);
3789 }
3790
3791 static void intel_crtc_noop(struct drm_crtc *crtc)
3792 {
3793 }
3794
3795 static void intel_crtc_disable(struct drm_crtc *crtc)
3796 {
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_connector *connector;
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800
3801 /* crtc should still be enabled when we disable it. */
3802 WARN_ON(!crtc->enabled);
3803
3804 dev_priv->display.crtc_disable(crtc);
3805 intel_crtc_update_sarea(crtc, false);
3806 dev_priv->display.off(crtc);
3807
3808 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3809 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3810
3811 if (crtc->fb) {
3812 mutex_lock(&dev->struct_mutex);
3813 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3814 mutex_unlock(&dev->struct_mutex);
3815 crtc->fb = NULL;
3816 }
3817
3818 /* Update computed state. */
3819 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3820 if (!connector->encoder || !connector->encoder->crtc)
3821 continue;
3822
3823 if (connector->encoder->crtc != crtc)
3824 continue;
3825
3826 connector->dpms = DRM_MODE_DPMS_OFF;
3827 to_intel_encoder(connector->encoder)->connectors_active = false;
3828 }
3829 }
3830
3831 void intel_modeset_disable(struct drm_device *dev)
3832 {
3833 struct drm_crtc *crtc;
3834
3835 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3836 if (crtc->enabled)
3837 intel_crtc_disable(crtc);
3838 }
3839 }
3840
3841 void intel_encoder_noop(struct drm_encoder *encoder)
3842 {
3843 }
3844
3845 void intel_encoder_destroy(struct drm_encoder *encoder)
3846 {
3847 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3848
3849 drm_encoder_cleanup(encoder);
3850 kfree(intel_encoder);
3851 }
3852
3853 /* Simple dpms helper for encodres with just one connector, no cloning and only
3854 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3855 * state of the entire output pipe. */
3856 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3857 {
3858 if (mode == DRM_MODE_DPMS_ON) {
3859 encoder->connectors_active = true;
3860
3861 intel_crtc_update_dpms(encoder->base.crtc);
3862 } else {
3863 encoder->connectors_active = false;
3864
3865 intel_crtc_update_dpms(encoder->base.crtc);
3866 }
3867 }
3868
3869 /* Cross check the actual hw state with our own modeset state tracking (and it's
3870 * internal consistency). */
3871 static void intel_connector_check_state(struct intel_connector *connector)
3872 {
3873 if (connector->get_hw_state(connector)) {
3874 struct intel_encoder *encoder = connector->encoder;
3875 struct drm_crtc *crtc;
3876 bool encoder_enabled;
3877 enum pipe pipe;
3878
3879 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3880 connector->base.base.id,
3881 drm_get_connector_name(&connector->base));
3882
3883 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3884 "wrong connector dpms state\n");
3885 WARN(connector->base.encoder != &encoder->base,
3886 "active connector not linked to encoder\n");
3887 WARN(!encoder->connectors_active,
3888 "encoder->connectors_active not set\n");
3889
3890 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3891 WARN(!encoder_enabled, "encoder not enabled\n");
3892 if (WARN_ON(!encoder->base.crtc))
3893 return;
3894
3895 crtc = encoder->base.crtc;
3896
3897 WARN(!crtc->enabled, "crtc not enabled\n");
3898 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3899 WARN(pipe != to_intel_crtc(crtc)->pipe,
3900 "encoder active on the wrong pipe\n");
3901 }
3902 }
3903
3904 /* Even simpler default implementation, if there's really no special case to
3905 * consider. */
3906 void intel_connector_dpms(struct drm_connector *connector, int mode)
3907 {
3908 struct intel_encoder *encoder = intel_attached_encoder(connector);
3909
3910 /* All the simple cases only support two dpms states. */
3911 if (mode != DRM_MODE_DPMS_ON)
3912 mode = DRM_MODE_DPMS_OFF;
3913
3914 if (mode == connector->dpms)
3915 return;
3916
3917 connector->dpms = mode;
3918
3919 /* Only need to change hw state when actually enabled */
3920 if (encoder->base.crtc)
3921 intel_encoder_dpms(encoder, mode);
3922 else
3923 WARN_ON(encoder->connectors_active != false);
3924
3925 intel_modeset_check_state(connector->dev);
3926 }
3927
3928 /* Simple connector->get_hw_state implementation for encoders that support only
3929 * one connector and no cloning and hence the encoder state determines the state
3930 * of the connector. */
3931 bool intel_connector_get_hw_state(struct intel_connector *connector)
3932 {
3933 enum pipe pipe = 0;
3934 struct intel_encoder *encoder = connector->encoder;
3935
3936 return encoder->get_hw_state(encoder, &pipe);
3937 }
3938
3939 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3940 const struct drm_display_mode *mode,
3941 struct drm_display_mode *adjusted_mode)
3942 {
3943 struct drm_device *dev = crtc->dev;
3944
3945 if (HAS_PCH_SPLIT(dev)) {
3946 /* FDI link clock is fixed at 2.7G */
3947 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3948 return false;
3949 }
3950
3951 /* All interlaced capable intel hw wants timings in frames. Note though
3952 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3953 * timings, so we need to be careful not to clobber these.*/
3954 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3955 drm_mode_set_crtcinfo(adjusted_mode, 0);
3956
3957 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3958 * with a hsync front porch of 0.
3959 */
3960 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3961 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3962 return false;
3963
3964 return true;
3965 }
3966
3967 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3968 {
3969 return 400000; /* FIXME */
3970 }
3971
3972 static int i945_get_display_clock_speed(struct drm_device *dev)
3973 {
3974 return 400000;
3975 }
3976
3977 static int i915_get_display_clock_speed(struct drm_device *dev)
3978 {
3979 return 333000;
3980 }
3981
3982 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3983 {
3984 return 200000;
3985 }
3986
3987 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3988 {
3989 u16 gcfgc = 0;
3990
3991 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3992
3993 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3994 return 133000;
3995 else {
3996 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3997 case GC_DISPLAY_CLOCK_333_MHZ:
3998 return 333000;
3999 default:
4000 case GC_DISPLAY_CLOCK_190_200_MHZ:
4001 return 190000;
4002 }
4003 }
4004 }
4005
4006 static int i865_get_display_clock_speed(struct drm_device *dev)
4007 {
4008 return 266000;
4009 }
4010
4011 static int i855_get_display_clock_speed(struct drm_device *dev)
4012 {
4013 u16 hpllcc = 0;
4014 /* Assume that the hardware is in the high speed state. This
4015 * should be the default.
4016 */
4017 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4018 case GC_CLOCK_133_200:
4019 case GC_CLOCK_100_200:
4020 return 200000;
4021 case GC_CLOCK_166_250:
4022 return 250000;
4023 case GC_CLOCK_100_133:
4024 return 133000;
4025 }
4026
4027 /* Shouldn't happen */
4028 return 0;
4029 }
4030
4031 static int i830_get_display_clock_speed(struct drm_device *dev)
4032 {
4033 return 133000;
4034 }
4035
4036 struct fdi_m_n {
4037 u32 tu;
4038 u32 gmch_m;
4039 u32 gmch_n;
4040 u32 link_m;
4041 u32 link_n;
4042 };
4043
4044 static void
4045 fdi_reduce_ratio(u32 *num, u32 *den)
4046 {
4047 while (*num > 0xffffff || *den > 0xffffff) {
4048 *num >>= 1;
4049 *den >>= 1;
4050 }
4051 }
4052
4053 static void
4054 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4055 int link_clock, struct fdi_m_n *m_n)
4056 {
4057 m_n->tu = 64; /* default size */
4058
4059 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4060 m_n->gmch_m = bits_per_pixel * pixel_clock;
4061 m_n->gmch_n = link_clock * nlanes * 8;
4062 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4063
4064 m_n->link_m = pixel_clock;
4065 m_n->link_n = link_clock;
4066 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4067 }
4068
4069 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4070 {
4071 if (i915_panel_use_ssc >= 0)
4072 return i915_panel_use_ssc != 0;
4073 return dev_priv->lvds_use_ssc
4074 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4075 }
4076
4077 /**
4078 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4079 * @crtc: CRTC structure
4080 * @mode: requested mode
4081 *
4082 * A pipe may be connected to one or more outputs. Based on the depth of the
4083 * attached framebuffer, choose a good color depth to use on the pipe.
4084 *
4085 * If possible, match the pipe depth to the fb depth. In some cases, this
4086 * isn't ideal, because the connected output supports a lesser or restricted
4087 * set of depths. Resolve that here:
4088 * LVDS typically supports only 6bpc, so clamp down in that case
4089 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4090 * Displays may support a restricted set as well, check EDID and clamp as
4091 * appropriate.
4092 * DP may want to dither down to 6bpc to fit larger modes
4093 *
4094 * RETURNS:
4095 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4096 * true if they don't match).
4097 */
4098 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4099 struct drm_framebuffer *fb,
4100 unsigned int *pipe_bpp,
4101 struct drm_display_mode *mode)
4102 {
4103 struct drm_device *dev = crtc->dev;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 struct drm_connector *connector;
4106 struct intel_encoder *intel_encoder;
4107 unsigned int display_bpc = UINT_MAX, bpc;
4108
4109 /* Walk the encoders & connectors on this crtc, get min bpc */
4110 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4111
4112 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4113 unsigned int lvds_bpc;
4114
4115 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4116 LVDS_A3_POWER_UP)
4117 lvds_bpc = 8;
4118 else
4119 lvds_bpc = 6;
4120
4121 if (lvds_bpc < display_bpc) {
4122 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4123 display_bpc = lvds_bpc;
4124 }
4125 continue;
4126 }
4127
4128 /* Not one of the known troublemakers, check the EDID */
4129 list_for_each_entry(connector, &dev->mode_config.connector_list,
4130 head) {
4131 if (connector->encoder != &intel_encoder->base)
4132 continue;
4133
4134 /* Don't use an invalid EDID bpc value */
4135 if (connector->display_info.bpc &&
4136 connector->display_info.bpc < display_bpc) {
4137 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4138 display_bpc = connector->display_info.bpc;
4139 }
4140 }
4141
4142 /*
4143 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4144 * through, clamp it down. (Note: >12bpc will be caught below.)
4145 */
4146 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4147 if (display_bpc > 8 && display_bpc < 12) {
4148 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4149 display_bpc = 12;
4150 } else {
4151 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4152 display_bpc = 8;
4153 }
4154 }
4155 }
4156
4157 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4158 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4159 display_bpc = 6;
4160 }
4161
4162 /*
4163 * We could just drive the pipe at the highest bpc all the time and
4164 * enable dithering as needed, but that costs bandwidth. So choose
4165 * the minimum value that expresses the full color range of the fb but
4166 * also stays within the max display bpc discovered above.
4167 */
4168
4169 switch (fb->depth) {
4170 case 8:
4171 bpc = 8; /* since we go through a colormap */
4172 break;
4173 case 15:
4174 case 16:
4175 bpc = 6; /* min is 18bpp */
4176 break;
4177 case 24:
4178 bpc = 8;
4179 break;
4180 case 30:
4181 bpc = 10;
4182 break;
4183 case 48:
4184 bpc = 12;
4185 break;
4186 default:
4187 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4188 bpc = min((unsigned int)8, display_bpc);
4189 break;
4190 }
4191
4192 display_bpc = min(display_bpc, bpc);
4193
4194 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4195 bpc, display_bpc);
4196
4197 *pipe_bpp = display_bpc * 3;
4198
4199 return display_bpc != bpc;
4200 }
4201
4202 static int vlv_get_refclk(struct drm_crtc *crtc)
4203 {
4204 struct drm_device *dev = crtc->dev;
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206 int refclk = 27000; /* for DP & HDMI */
4207
4208 return 100000; /* only one validated so far */
4209
4210 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4211 refclk = 96000;
4212 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4213 if (intel_panel_use_ssc(dev_priv))
4214 refclk = 100000;
4215 else
4216 refclk = 96000;
4217 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4218 refclk = 100000;
4219 }
4220
4221 return refclk;
4222 }
4223
4224 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4225 {
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 int refclk;
4229
4230 if (IS_VALLEYVIEW(dev)) {
4231 refclk = vlv_get_refclk(crtc);
4232 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4233 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4234 refclk = dev_priv->lvds_ssc_freq * 1000;
4235 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4236 refclk / 1000);
4237 } else if (!IS_GEN2(dev)) {
4238 refclk = 96000;
4239 } else {
4240 refclk = 48000;
4241 }
4242
4243 return refclk;
4244 }
4245
4246 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4247 intel_clock_t *clock)
4248 {
4249 /* SDVO TV has fixed PLL values depend on its clock range,
4250 this mirrors vbios setting. */
4251 if (adjusted_mode->clock >= 100000
4252 && adjusted_mode->clock < 140500) {
4253 clock->p1 = 2;
4254 clock->p2 = 10;
4255 clock->n = 3;
4256 clock->m1 = 16;
4257 clock->m2 = 8;
4258 } else if (adjusted_mode->clock >= 140500
4259 && adjusted_mode->clock <= 200000) {
4260 clock->p1 = 1;
4261 clock->p2 = 10;
4262 clock->n = 6;
4263 clock->m1 = 12;
4264 clock->m2 = 8;
4265 }
4266 }
4267
4268 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4269 intel_clock_t *clock,
4270 intel_clock_t *reduced_clock)
4271 {
4272 struct drm_device *dev = crtc->dev;
4273 struct drm_i915_private *dev_priv = dev->dev_private;
4274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4275 int pipe = intel_crtc->pipe;
4276 u32 fp, fp2 = 0;
4277
4278 if (IS_PINEVIEW(dev)) {
4279 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4280 if (reduced_clock)
4281 fp2 = (1 << reduced_clock->n) << 16 |
4282 reduced_clock->m1 << 8 | reduced_clock->m2;
4283 } else {
4284 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4285 if (reduced_clock)
4286 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4287 reduced_clock->m2;
4288 }
4289
4290 I915_WRITE(FP0(pipe), fp);
4291
4292 intel_crtc->lowfreq_avail = false;
4293 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4294 reduced_clock && i915_powersave) {
4295 I915_WRITE(FP1(pipe), fp2);
4296 intel_crtc->lowfreq_avail = true;
4297 } else {
4298 I915_WRITE(FP1(pipe), fp);
4299 }
4300 }
4301
4302 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4303 struct drm_display_mode *adjusted_mode)
4304 {
4305 struct drm_device *dev = crtc->dev;
4306 struct drm_i915_private *dev_priv = dev->dev_private;
4307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4308 int pipe = intel_crtc->pipe;
4309 u32 temp;
4310
4311 temp = I915_READ(LVDS);
4312 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4313 if (pipe == 1) {
4314 temp |= LVDS_PIPEB_SELECT;
4315 } else {
4316 temp &= ~LVDS_PIPEB_SELECT;
4317 }
4318 /* set the corresponsding LVDS_BORDER bit */
4319 temp |= dev_priv->lvds_border_bits;
4320 /* Set the B0-B3 data pairs corresponding to whether we're going to
4321 * set the DPLLs for dual-channel mode or not.
4322 */
4323 if (clock->p2 == 7)
4324 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4325 else
4326 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4327
4328 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4329 * appropriately here, but we need to look more thoroughly into how
4330 * panels behave in the two modes.
4331 */
4332 /* set the dithering flag on LVDS as needed */
4333 if (INTEL_INFO(dev)->gen >= 4) {
4334 if (dev_priv->lvds_dither)
4335 temp |= LVDS_ENABLE_DITHER;
4336 else
4337 temp &= ~LVDS_ENABLE_DITHER;
4338 }
4339 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4340 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4341 temp |= LVDS_HSYNC_POLARITY;
4342 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4343 temp |= LVDS_VSYNC_POLARITY;
4344 I915_WRITE(LVDS, temp);
4345 }
4346
4347 static void vlv_update_pll(struct drm_crtc *crtc,
4348 struct drm_display_mode *mode,
4349 struct drm_display_mode *adjusted_mode,
4350 intel_clock_t *clock, intel_clock_t *reduced_clock,
4351 int num_connectors)
4352 {
4353 struct drm_device *dev = crtc->dev;
4354 struct drm_i915_private *dev_priv = dev->dev_private;
4355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4356 int pipe = intel_crtc->pipe;
4357 u32 dpll, mdiv, pdiv;
4358 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4359 bool is_sdvo;
4360 u32 temp;
4361
4362 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4363 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4364
4365 dpll = DPLL_VGA_MODE_DIS;
4366 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4367 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4368 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4369
4370 I915_WRITE(DPLL(pipe), dpll);
4371 POSTING_READ(DPLL(pipe));
4372
4373 bestn = clock->n;
4374 bestm1 = clock->m1;
4375 bestm2 = clock->m2;
4376 bestp1 = clock->p1;
4377 bestp2 = clock->p2;
4378
4379 /*
4380 * In Valleyview PLL and program lane counter registers are exposed
4381 * through DPIO interface
4382 */
4383 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4384 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4385 mdiv |= ((bestn << DPIO_N_SHIFT));
4386 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4387 mdiv |= (1 << DPIO_K_SHIFT);
4388 mdiv |= DPIO_ENABLE_CALIBRATION;
4389 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4390
4391 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4392
4393 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4394 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4395 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4396 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4397 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4398
4399 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4400
4401 dpll |= DPLL_VCO_ENABLE;
4402 I915_WRITE(DPLL(pipe), dpll);
4403 POSTING_READ(DPLL(pipe));
4404 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4405 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4406
4407 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4408
4409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4410 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4411
4412 I915_WRITE(DPLL(pipe), dpll);
4413
4414 /* Wait for the clocks to stabilize. */
4415 POSTING_READ(DPLL(pipe));
4416 udelay(150);
4417
4418 temp = 0;
4419 if (is_sdvo) {
4420 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4421 if (temp > 1)
4422 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4423 else
4424 temp = 0;
4425 }
4426 I915_WRITE(DPLL_MD(pipe), temp);
4427 POSTING_READ(DPLL_MD(pipe));
4428
4429 /* Now program lane control registers */
4430 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4431 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4432 {
4433 temp = 0x1000C4;
4434 if(pipe == 1)
4435 temp |= (1 << 21);
4436 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4437 }
4438 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4439 {
4440 temp = 0x1000C4;
4441 if(pipe == 1)
4442 temp |= (1 << 21);
4443 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4444 }
4445 }
4446
4447 static void i9xx_update_pll(struct drm_crtc *crtc,
4448 struct drm_display_mode *mode,
4449 struct drm_display_mode *adjusted_mode,
4450 intel_clock_t *clock, intel_clock_t *reduced_clock,
4451 int num_connectors)
4452 {
4453 struct drm_device *dev = crtc->dev;
4454 struct drm_i915_private *dev_priv = dev->dev_private;
4455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4456 int pipe = intel_crtc->pipe;
4457 u32 dpll;
4458 bool is_sdvo;
4459
4460 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4461
4462 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4463 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4464
4465 dpll = DPLL_VGA_MODE_DIS;
4466
4467 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4468 dpll |= DPLLB_MODE_LVDS;
4469 else
4470 dpll |= DPLLB_MODE_DAC_SERIAL;
4471 if (is_sdvo) {
4472 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4473 if (pixel_multiplier > 1) {
4474 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4475 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4476 }
4477 dpll |= DPLL_DVO_HIGH_SPEED;
4478 }
4479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4480 dpll |= DPLL_DVO_HIGH_SPEED;
4481
4482 /* compute bitmask from p1 value */
4483 if (IS_PINEVIEW(dev))
4484 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4485 else {
4486 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4487 if (IS_G4X(dev) && reduced_clock)
4488 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4489 }
4490 switch (clock->p2) {
4491 case 5:
4492 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4493 break;
4494 case 7:
4495 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4496 break;
4497 case 10:
4498 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4499 break;
4500 case 14:
4501 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4502 break;
4503 }
4504 if (INTEL_INFO(dev)->gen >= 4)
4505 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4506
4507 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4508 dpll |= PLL_REF_INPUT_TVCLKINBC;
4509 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4510 /* XXX: just matching BIOS for now */
4511 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4512 dpll |= 3;
4513 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4514 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4515 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4516 else
4517 dpll |= PLL_REF_INPUT_DREFCLK;
4518
4519 dpll |= DPLL_VCO_ENABLE;
4520 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4521 POSTING_READ(DPLL(pipe));
4522 udelay(150);
4523
4524 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4525 * This is an exception to the general rule that mode_set doesn't turn
4526 * things on.
4527 */
4528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4529 intel_update_lvds(crtc, clock, adjusted_mode);
4530
4531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4532 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4533
4534 I915_WRITE(DPLL(pipe), dpll);
4535
4536 /* Wait for the clocks to stabilize. */
4537 POSTING_READ(DPLL(pipe));
4538 udelay(150);
4539
4540 if (INTEL_INFO(dev)->gen >= 4) {
4541 u32 temp = 0;
4542 if (is_sdvo) {
4543 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4544 if (temp > 1)
4545 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4546 else
4547 temp = 0;
4548 }
4549 I915_WRITE(DPLL_MD(pipe), temp);
4550 } else {
4551 /* The pixel multiplier can only be updated once the
4552 * DPLL is enabled and the clocks are stable.
4553 *
4554 * So write it again.
4555 */
4556 I915_WRITE(DPLL(pipe), dpll);
4557 }
4558 }
4559
4560 static void i8xx_update_pll(struct drm_crtc *crtc,
4561 struct drm_display_mode *adjusted_mode,
4562 intel_clock_t *clock, intel_clock_t *reduced_clock,
4563 int num_connectors)
4564 {
4565 struct drm_device *dev = crtc->dev;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4568 int pipe = intel_crtc->pipe;
4569 u32 dpll;
4570
4571 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4572
4573 dpll = DPLL_VGA_MODE_DIS;
4574
4575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4576 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4577 } else {
4578 if (clock->p1 == 2)
4579 dpll |= PLL_P1_DIVIDE_BY_TWO;
4580 else
4581 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4582 if (clock->p2 == 4)
4583 dpll |= PLL_P2_DIVIDE_BY_4;
4584 }
4585
4586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4587 /* XXX: just matching BIOS for now */
4588 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4589 dpll |= 3;
4590 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4591 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4592 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4593 else
4594 dpll |= PLL_REF_INPUT_DREFCLK;
4595
4596 dpll |= DPLL_VCO_ENABLE;
4597 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4598 POSTING_READ(DPLL(pipe));
4599 udelay(150);
4600
4601 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4602 * This is an exception to the general rule that mode_set doesn't turn
4603 * things on.
4604 */
4605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4606 intel_update_lvds(crtc, clock, adjusted_mode);
4607
4608 I915_WRITE(DPLL(pipe), dpll);
4609
4610 /* Wait for the clocks to stabilize. */
4611 POSTING_READ(DPLL(pipe));
4612 udelay(150);
4613
4614 /* The pixel multiplier can only be updated once the
4615 * DPLL is enabled and the clocks are stable.
4616 *
4617 * So write it again.
4618 */
4619 I915_WRITE(DPLL(pipe), dpll);
4620 }
4621
4622 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4623 struct drm_display_mode *mode,
4624 struct drm_display_mode *adjusted_mode)
4625 {
4626 struct drm_device *dev = intel_crtc->base.dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 enum pipe pipe = intel_crtc->pipe;
4629 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4630 uint32_t vsyncshift;
4631
4632 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4633 /* the chip adds 2 halflines automatically */
4634 adjusted_mode->crtc_vtotal -= 1;
4635 adjusted_mode->crtc_vblank_end -= 1;
4636 vsyncshift = adjusted_mode->crtc_hsync_start
4637 - adjusted_mode->crtc_htotal / 2;
4638 } else {
4639 vsyncshift = 0;
4640 }
4641
4642 if (INTEL_INFO(dev)->gen > 3)
4643 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4644
4645 I915_WRITE(HTOTAL(cpu_transcoder),
4646 (adjusted_mode->crtc_hdisplay - 1) |
4647 ((adjusted_mode->crtc_htotal - 1) << 16));
4648 I915_WRITE(HBLANK(cpu_transcoder),
4649 (adjusted_mode->crtc_hblank_start - 1) |
4650 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4651 I915_WRITE(HSYNC(cpu_transcoder),
4652 (adjusted_mode->crtc_hsync_start - 1) |
4653 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4654
4655 I915_WRITE(VTOTAL(cpu_transcoder),
4656 (adjusted_mode->crtc_vdisplay - 1) |
4657 ((adjusted_mode->crtc_vtotal - 1) << 16));
4658 I915_WRITE(VBLANK(cpu_transcoder),
4659 (adjusted_mode->crtc_vblank_start - 1) |
4660 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4661 I915_WRITE(VSYNC(cpu_transcoder),
4662 (adjusted_mode->crtc_vsync_start - 1) |
4663 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4664
4665 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4666 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4667 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4668 * bits. */
4669 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4670 (pipe == PIPE_B || pipe == PIPE_C))
4671 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4672
4673 /* pipesrc controls the size that is scaled from, which should
4674 * always be the user's requested size.
4675 */
4676 I915_WRITE(PIPESRC(pipe),
4677 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4678 }
4679
4680 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4681 struct drm_display_mode *mode,
4682 struct drm_display_mode *adjusted_mode,
4683 int x, int y,
4684 struct drm_framebuffer *fb)
4685 {
4686 struct drm_device *dev = crtc->dev;
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4689 int pipe = intel_crtc->pipe;
4690 int plane = intel_crtc->plane;
4691 int refclk, num_connectors = 0;
4692 intel_clock_t clock, reduced_clock;
4693 u32 dspcntr, pipeconf;
4694 bool ok, has_reduced_clock = false, is_sdvo = false;
4695 bool is_lvds = false, is_tv = false, is_dp = false;
4696 struct intel_encoder *encoder;
4697 const intel_limit_t *limit;
4698 int ret;
4699
4700 for_each_encoder_on_crtc(dev, crtc, encoder) {
4701 switch (encoder->type) {
4702 case INTEL_OUTPUT_LVDS:
4703 is_lvds = true;
4704 break;
4705 case INTEL_OUTPUT_SDVO:
4706 case INTEL_OUTPUT_HDMI:
4707 is_sdvo = true;
4708 if (encoder->needs_tv_clock)
4709 is_tv = true;
4710 break;
4711 case INTEL_OUTPUT_TVOUT:
4712 is_tv = true;
4713 break;
4714 case INTEL_OUTPUT_DISPLAYPORT:
4715 is_dp = true;
4716 break;
4717 }
4718
4719 num_connectors++;
4720 }
4721
4722 refclk = i9xx_get_refclk(crtc, num_connectors);
4723
4724 /*
4725 * Returns a set of divisors for the desired target clock with the given
4726 * refclk, or FALSE. The returned values represent the clock equation:
4727 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4728 */
4729 limit = intel_limit(crtc, refclk);
4730 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4731 &clock);
4732 if (!ok) {
4733 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4734 return -EINVAL;
4735 }
4736
4737 /* Ensure that the cursor is valid for the new mode before changing... */
4738 intel_crtc_update_cursor(crtc, true);
4739
4740 if (is_lvds && dev_priv->lvds_downclock_avail) {
4741 /*
4742 * Ensure we match the reduced clock's P to the target clock.
4743 * If the clocks don't match, we can't switch the display clock
4744 * by using the FP0/FP1. In such case we will disable the LVDS
4745 * downclock feature.
4746 */
4747 has_reduced_clock = limit->find_pll(limit, crtc,
4748 dev_priv->lvds_downclock,
4749 refclk,
4750 &clock,
4751 &reduced_clock);
4752 }
4753
4754 if (is_sdvo && is_tv)
4755 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4756
4757 if (IS_GEN2(dev))
4758 i8xx_update_pll(crtc, adjusted_mode, &clock,
4759 has_reduced_clock ? &reduced_clock : NULL,
4760 num_connectors);
4761 else if (IS_VALLEYVIEW(dev))
4762 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4763 has_reduced_clock ? &reduced_clock : NULL,
4764 num_connectors);
4765 else
4766 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4767 has_reduced_clock ? &reduced_clock : NULL,
4768 num_connectors);
4769
4770 /* setup pipeconf */
4771 pipeconf = I915_READ(PIPECONF(pipe));
4772
4773 /* Set up the display plane register */
4774 dspcntr = DISPPLANE_GAMMA_ENABLE;
4775
4776 if (pipe == 0)
4777 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4778 else
4779 dspcntr |= DISPPLANE_SEL_PIPE_B;
4780
4781 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4782 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4783 * core speed.
4784 *
4785 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4786 * pipe == 0 check?
4787 */
4788 if (mode->clock >
4789 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4790 pipeconf |= PIPECONF_DOUBLE_WIDE;
4791 else
4792 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4793 }
4794
4795 /* default to 8bpc */
4796 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4797 if (is_dp) {
4798 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4799 pipeconf |= PIPECONF_BPP_6 |
4800 PIPECONF_DITHER_EN |
4801 PIPECONF_DITHER_TYPE_SP;
4802 }
4803 }
4804
4805 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4806 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4807 pipeconf |= PIPECONF_BPP_6 |
4808 PIPECONF_ENABLE |
4809 I965_PIPECONF_ACTIVE;
4810 }
4811 }
4812
4813 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4814 drm_mode_debug_printmodeline(mode);
4815
4816 if (HAS_PIPE_CXSR(dev)) {
4817 if (intel_crtc->lowfreq_avail) {
4818 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4819 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4820 } else {
4821 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4822 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4823 }
4824 }
4825
4826 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4827 if (!IS_GEN2(dev) &&
4828 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4829 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4830 else
4831 pipeconf |= PIPECONF_PROGRESSIVE;
4832
4833 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4834
4835 /* pipesrc and dspsize control the size that is scaled from,
4836 * which should always be the user's requested size.
4837 */
4838 I915_WRITE(DSPSIZE(plane),
4839 ((mode->vdisplay - 1) << 16) |
4840 (mode->hdisplay - 1));
4841 I915_WRITE(DSPPOS(plane), 0);
4842
4843 I915_WRITE(PIPECONF(pipe), pipeconf);
4844 POSTING_READ(PIPECONF(pipe));
4845 intel_enable_pipe(dev_priv, pipe, false);
4846
4847 intel_wait_for_vblank(dev, pipe);
4848
4849 I915_WRITE(DSPCNTR(plane), dspcntr);
4850 POSTING_READ(DSPCNTR(plane));
4851
4852 ret = intel_pipe_set_base(crtc, x, y, fb);
4853
4854 intel_update_watermarks(dev);
4855
4856 return ret;
4857 }
4858
4859 /*
4860 * Initialize reference clocks when the driver loads
4861 */
4862 void ironlake_init_pch_refclk(struct drm_device *dev)
4863 {
4864 struct drm_i915_private *dev_priv = dev->dev_private;
4865 struct drm_mode_config *mode_config = &dev->mode_config;
4866 struct intel_encoder *encoder;
4867 u32 temp;
4868 bool has_lvds = false;
4869 bool has_cpu_edp = false;
4870 bool has_pch_edp = false;
4871 bool has_panel = false;
4872 bool has_ck505 = false;
4873 bool can_ssc = false;
4874
4875 /* We need to take the global config into account */
4876 list_for_each_entry(encoder, &mode_config->encoder_list,
4877 base.head) {
4878 switch (encoder->type) {
4879 case INTEL_OUTPUT_LVDS:
4880 has_panel = true;
4881 has_lvds = true;
4882 break;
4883 case INTEL_OUTPUT_EDP:
4884 has_panel = true;
4885 if (intel_encoder_is_pch_edp(&encoder->base))
4886 has_pch_edp = true;
4887 else
4888 has_cpu_edp = true;
4889 break;
4890 }
4891 }
4892
4893 if (HAS_PCH_IBX(dev)) {
4894 has_ck505 = dev_priv->display_clock_mode;
4895 can_ssc = has_ck505;
4896 } else {
4897 has_ck505 = false;
4898 can_ssc = true;
4899 }
4900
4901 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4902 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4903 has_ck505);
4904
4905 /* Ironlake: try to setup display ref clock before DPLL
4906 * enabling. This is only under driver's control after
4907 * PCH B stepping, previous chipset stepping should be
4908 * ignoring this setting.
4909 */
4910 temp = I915_READ(PCH_DREF_CONTROL);
4911 /* Always enable nonspread source */
4912 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4913
4914 if (has_ck505)
4915 temp |= DREF_NONSPREAD_CK505_ENABLE;
4916 else
4917 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4918
4919 if (has_panel) {
4920 temp &= ~DREF_SSC_SOURCE_MASK;
4921 temp |= DREF_SSC_SOURCE_ENABLE;
4922
4923 /* SSC must be turned on before enabling the CPU output */
4924 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4925 DRM_DEBUG_KMS("Using SSC on panel\n");
4926 temp |= DREF_SSC1_ENABLE;
4927 } else
4928 temp &= ~DREF_SSC1_ENABLE;
4929
4930 /* Get SSC going before enabling the outputs */
4931 I915_WRITE(PCH_DREF_CONTROL, temp);
4932 POSTING_READ(PCH_DREF_CONTROL);
4933 udelay(200);
4934
4935 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4936
4937 /* Enable CPU source on CPU attached eDP */
4938 if (has_cpu_edp) {
4939 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4940 DRM_DEBUG_KMS("Using SSC on eDP\n");
4941 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4942 }
4943 else
4944 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4945 } else
4946 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4947
4948 I915_WRITE(PCH_DREF_CONTROL, temp);
4949 POSTING_READ(PCH_DREF_CONTROL);
4950 udelay(200);
4951 } else {
4952 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4953
4954 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4955
4956 /* Turn off CPU output */
4957 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4958
4959 I915_WRITE(PCH_DREF_CONTROL, temp);
4960 POSTING_READ(PCH_DREF_CONTROL);
4961 udelay(200);
4962
4963 /* Turn off the SSC source */
4964 temp &= ~DREF_SSC_SOURCE_MASK;
4965 temp |= DREF_SSC_SOURCE_DISABLE;
4966
4967 /* Turn off SSC1 */
4968 temp &= ~ DREF_SSC1_ENABLE;
4969
4970 I915_WRITE(PCH_DREF_CONTROL, temp);
4971 POSTING_READ(PCH_DREF_CONTROL);
4972 udelay(200);
4973 }
4974 }
4975
4976 static int ironlake_get_refclk(struct drm_crtc *crtc)
4977 {
4978 struct drm_device *dev = crtc->dev;
4979 struct drm_i915_private *dev_priv = dev->dev_private;
4980 struct intel_encoder *encoder;
4981 struct intel_encoder *edp_encoder = NULL;
4982 int num_connectors = 0;
4983 bool is_lvds = false;
4984
4985 for_each_encoder_on_crtc(dev, crtc, encoder) {
4986 switch (encoder->type) {
4987 case INTEL_OUTPUT_LVDS:
4988 is_lvds = true;
4989 break;
4990 case INTEL_OUTPUT_EDP:
4991 edp_encoder = encoder;
4992 break;
4993 }
4994 num_connectors++;
4995 }
4996
4997 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4998 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4999 dev_priv->lvds_ssc_freq);
5000 return dev_priv->lvds_ssc_freq * 1000;
5001 }
5002
5003 return 120000;
5004 }
5005
5006 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5007 struct drm_display_mode *adjusted_mode,
5008 bool dither)
5009 {
5010 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012 int pipe = intel_crtc->pipe;
5013 uint32_t val;
5014
5015 val = I915_READ(PIPECONF(pipe));
5016
5017 val &= ~PIPE_BPC_MASK;
5018 switch (intel_crtc->bpp) {
5019 case 18:
5020 val |= PIPE_6BPC;
5021 break;
5022 case 24:
5023 val |= PIPE_8BPC;
5024 break;
5025 case 30:
5026 val |= PIPE_10BPC;
5027 break;
5028 case 36:
5029 val |= PIPE_12BPC;
5030 break;
5031 default:
5032 /* Case prevented by intel_choose_pipe_bpp_dither. */
5033 BUG();
5034 }
5035
5036 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5037 if (dither)
5038 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5039
5040 val &= ~PIPECONF_INTERLACE_MASK;
5041 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5042 val |= PIPECONF_INTERLACED_ILK;
5043 else
5044 val |= PIPECONF_PROGRESSIVE;
5045
5046 I915_WRITE(PIPECONF(pipe), val);
5047 POSTING_READ(PIPECONF(pipe));
5048 }
5049
5050 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5051 struct drm_display_mode *adjusted_mode,
5052 bool dither)
5053 {
5054 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5056 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5057 uint32_t val;
5058
5059 val = I915_READ(PIPECONF(cpu_transcoder));
5060
5061 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5062 if (dither)
5063 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5064
5065 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5066 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5067 val |= PIPECONF_INTERLACED_ILK;
5068 else
5069 val |= PIPECONF_PROGRESSIVE;
5070
5071 I915_WRITE(PIPECONF(cpu_transcoder), val);
5072 POSTING_READ(PIPECONF(cpu_transcoder));
5073 }
5074
5075 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5076 struct drm_display_mode *adjusted_mode,
5077 intel_clock_t *clock,
5078 bool *has_reduced_clock,
5079 intel_clock_t *reduced_clock)
5080 {
5081 struct drm_device *dev = crtc->dev;
5082 struct drm_i915_private *dev_priv = dev->dev_private;
5083 struct intel_encoder *intel_encoder;
5084 int refclk;
5085 const intel_limit_t *limit;
5086 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5087
5088 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5089 switch (intel_encoder->type) {
5090 case INTEL_OUTPUT_LVDS:
5091 is_lvds = true;
5092 break;
5093 case INTEL_OUTPUT_SDVO:
5094 case INTEL_OUTPUT_HDMI:
5095 is_sdvo = true;
5096 if (intel_encoder->needs_tv_clock)
5097 is_tv = true;
5098 break;
5099 case INTEL_OUTPUT_TVOUT:
5100 is_tv = true;
5101 break;
5102 }
5103 }
5104
5105 refclk = ironlake_get_refclk(crtc);
5106
5107 /*
5108 * Returns a set of divisors for the desired target clock with the given
5109 * refclk, or FALSE. The returned values represent the clock equation:
5110 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5111 */
5112 limit = intel_limit(crtc, refclk);
5113 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5114 clock);
5115 if (!ret)
5116 return false;
5117
5118 if (is_lvds && dev_priv->lvds_downclock_avail) {
5119 /*
5120 * Ensure we match the reduced clock's P to the target clock.
5121 * If the clocks don't match, we can't switch the display clock
5122 * by using the FP0/FP1. In such case we will disable the LVDS
5123 * downclock feature.
5124 */
5125 *has_reduced_clock = limit->find_pll(limit, crtc,
5126 dev_priv->lvds_downclock,
5127 refclk,
5128 clock,
5129 reduced_clock);
5130 }
5131
5132 if (is_sdvo && is_tv)
5133 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5134
5135 return true;
5136 }
5137
5138 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5139 {
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 uint32_t temp;
5142
5143 temp = I915_READ(SOUTH_CHICKEN1);
5144 if (temp & FDI_BC_BIFURCATION_SELECT)
5145 return;
5146
5147 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5148 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5149
5150 temp |= FDI_BC_BIFURCATION_SELECT;
5151 DRM_DEBUG_KMS("enabling fdi C rx\n");
5152 I915_WRITE(SOUTH_CHICKEN1, temp);
5153 POSTING_READ(SOUTH_CHICKEN1);
5154 }
5155
5156 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5157 {
5158 struct drm_device *dev = intel_crtc->base.dev;
5159 struct drm_i915_private *dev_priv = dev->dev_private;
5160 struct intel_crtc *pipe_B_crtc =
5161 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5162
5163 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5164 intel_crtc->pipe, intel_crtc->fdi_lanes);
5165 if (intel_crtc->fdi_lanes > 4) {
5166 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5167 intel_crtc->pipe, intel_crtc->fdi_lanes);
5168 /* Clamp lanes to avoid programming the hw with bogus values. */
5169 intel_crtc->fdi_lanes = 4;
5170
5171 return false;
5172 }
5173
5174 if (dev_priv->num_pipe == 2)
5175 return true;
5176
5177 switch (intel_crtc->pipe) {
5178 case PIPE_A:
5179 return true;
5180 case PIPE_B:
5181 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5182 intel_crtc->fdi_lanes > 2) {
5183 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5184 intel_crtc->pipe, intel_crtc->fdi_lanes);
5185 /* Clamp lanes to avoid programming the hw with bogus values. */
5186 intel_crtc->fdi_lanes = 2;
5187
5188 return false;
5189 }
5190
5191 if (intel_crtc->fdi_lanes > 2)
5192 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5193 else
5194 cpt_enable_fdi_bc_bifurcation(dev);
5195
5196 return true;
5197 case PIPE_C:
5198 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5199 if (intel_crtc->fdi_lanes > 2) {
5200 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5201 intel_crtc->pipe, intel_crtc->fdi_lanes);
5202 /* Clamp lanes to avoid programming the hw with bogus values. */
5203 intel_crtc->fdi_lanes = 2;
5204
5205 return false;
5206 }
5207 } else {
5208 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5209 return false;
5210 }
5211
5212 cpt_enable_fdi_bc_bifurcation(dev);
5213
5214 return true;
5215 default:
5216 BUG();
5217 }
5218 }
5219
5220 static void ironlake_set_m_n(struct drm_crtc *crtc,
5221 struct drm_display_mode *mode,
5222 struct drm_display_mode *adjusted_mode)
5223 {
5224 struct drm_device *dev = crtc->dev;
5225 struct drm_i915_private *dev_priv = dev->dev_private;
5226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5227 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5228 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5229 struct fdi_m_n m_n = {0};
5230 int target_clock, pixel_multiplier, lane, link_bw;
5231 bool is_dp = false, is_cpu_edp = false;
5232
5233 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5234 switch (intel_encoder->type) {
5235 case INTEL_OUTPUT_DISPLAYPORT:
5236 is_dp = true;
5237 break;
5238 case INTEL_OUTPUT_EDP:
5239 is_dp = true;
5240 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5241 is_cpu_edp = true;
5242 edp_encoder = intel_encoder;
5243 break;
5244 }
5245 }
5246
5247 /* FDI link */
5248 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5249 lane = 0;
5250 /* CPU eDP doesn't require FDI link, so just set DP M/N
5251 according to current link config */
5252 if (is_cpu_edp) {
5253 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5254 } else {
5255 /* FDI is a binary signal running at ~2.7GHz, encoding
5256 * each output octet as 10 bits. The actual frequency
5257 * is stored as a divider into a 100MHz clock, and the
5258 * mode pixel clock is stored in units of 1KHz.
5259 * Hence the bw of each lane in terms of the mode signal
5260 * is:
5261 */
5262 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5263 }
5264
5265 /* [e]DP over FDI requires target mode clock instead of link clock. */
5266 if (edp_encoder)
5267 target_clock = intel_edp_target_clock(edp_encoder, mode);
5268 else if (is_dp)
5269 target_clock = mode->clock;
5270 else
5271 target_clock = adjusted_mode->clock;
5272
5273 if (!lane) {
5274 /*
5275 * Account for spread spectrum to avoid
5276 * oversubscribing the link. Max center spread
5277 * is 2.5%; use 5% for safety's sake.
5278 */
5279 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5280 lane = bps / (link_bw * 8) + 1;
5281 }
5282
5283 intel_crtc->fdi_lanes = lane;
5284
5285 if (pixel_multiplier > 1)
5286 link_bw *= pixel_multiplier;
5287 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5288 &m_n);
5289
5290 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5291 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5292 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5293 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5294 }
5295
5296 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5297 struct drm_display_mode *adjusted_mode,
5298 intel_clock_t *clock, u32 fp)
5299 {
5300 struct drm_crtc *crtc = &intel_crtc->base;
5301 struct drm_device *dev = crtc->dev;
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 struct intel_encoder *intel_encoder;
5304 uint32_t dpll;
5305 int factor, pixel_multiplier, num_connectors = 0;
5306 bool is_lvds = false, is_sdvo = false, is_tv = false;
5307 bool is_dp = false, is_cpu_edp = false;
5308
5309 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5310 switch (intel_encoder->type) {
5311 case INTEL_OUTPUT_LVDS:
5312 is_lvds = true;
5313 break;
5314 case INTEL_OUTPUT_SDVO:
5315 case INTEL_OUTPUT_HDMI:
5316 is_sdvo = true;
5317 if (intel_encoder->needs_tv_clock)
5318 is_tv = true;
5319 break;
5320 case INTEL_OUTPUT_TVOUT:
5321 is_tv = true;
5322 break;
5323 case INTEL_OUTPUT_DISPLAYPORT:
5324 is_dp = true;
5325 break;
5326 case INTEL_OUTPUT_EDP:
5327 is_dp = true;
5328 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5329 is_cpu_edp = true;
5330 break;
5331 }
5332
5333 num_connectors++;
5334 }
5335
5336 /* Enable autotuning of the PLL clock (if permissible) */
5337 factor = 21;
5338 if (is_lvds) {
5339 if ((intel_panel_use_ssc(dev_priv) &&
5340 dev_priv->lvds_ssc_freq == 100) ||
5341 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5342 factor = 25;
5343 } else if (is_sdvo && is_tv)
5344 factor = 20;
5345
5346 if (clock->m < factor * clock->n)
5347 fp |= FP_CB_TUNE;
5348
5349 dpll = 0;
5350
5351 if (is_lvds)
5352 dpll |= DPLLB_MODE_LVDS;
5353 else
5354 dpll |= DPLLB_MODE_DAC_SERIAL;
5355 if (is_sdvo) {
5356 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5357 if (pixel_multiplier > 1) {
5358 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5359 }
5360 dpll |= DPLL_DVO_HIGH_SPEED;
5361 }
5362 if (is_dp && !is_cpu_edp)
5363 dpll |= DPLL_DVO_HIGH_SPEED;
5364
5365 /* compute bitmask from p1 value */
5366 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5367 /* also FPA1 */
5368 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5369
5370 switch (clock->p2) {
5371 case 5:
5372 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5373 break;
5374 case 7:
5375 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5376 break;
5377 case 10:
5378 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5379 break;
5380 case 14:
5381 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5382 break;
5383 }
5384
5385 if (is_sdvo && is_tv)
5386 dpll |= PLL_REF_INPUT_TVCLKINBC;
5387 else if (is_tv)
5388 /* XXX: just matching BIOS for now */
5389 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5390 dpll |= 3;
5391 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5392 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5393 else
5394 dpll |= PLL_REF_INPUT_DREFCLK;
5395
5396 return dpll;
5397 }
5398
5399 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5400 struct drm_display_mode *mode,
5401 struct drm_display_mode *adjusted_mode,
5402 int x, int y,
5403 struct drm_framebuffer *fb)
5404 {
5405 struct drm_device *dev = crtc->dev;
5406 struct drm_i915_private *dev_priv = dev->dev_private;
5407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5408 int pipe = intel_crtc->pipe;
5409 int plane = intel_crtc->plane;
5410 int num_connectors = 0;
5411 intel_clock_t clock, reduced_clock;
5412 u32 dpll, fp = 0, fp2 = 0;
5413 bool ok, has_reduced_clock = false;
5414 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5415 struct intel_encoder *encoder;
5416 u32 temp;
5417 int ret;
5418 bool dither, fdi_config_ok;
5419
5420 for_each_encoder_on_crtc(dev, crtc, encoder) {
5421 switch (encoder->type) {
5422 case INTEL_OUTPUT_LVDS:
5423 is_lvds = true;
5424 break;
5425 case INTEL_OUTPUT_DISPLAYPORT:
5426 is_dp = true;
5427 break;
5428 case INTEL_OUTPUT_EDP:
5429 is_dp = true;
5430 if (!intel_encoder_is_pch_edp(&encoder->base))
5431 is_cpu_edp = true;
5432 break;
5433 }
5434
5435 num_connectors++;
5436 }
5437
5438 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5439 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5440
5441 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5442 &has_reduced_clock, &reduced_clock);
5443 if (!ok) {
5444 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5445 return -EINVAL;
5446 }
5447
5448 /* Ensure that the cursor is valid for the new mode before changing... */
5449 intel_crtc_update_cursor(crtc, true);
5450
5451 /* determine panel color depth */
5452 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5453 adjusted_mode);
5454 if (is_lvds && dev_priv->lvds_dither)
5455 dither = true;
5456
5457 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5458 if (has_reduced_clock)
5459 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5460 reduced_clock.m2;
5461
5462 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5463
5464 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5465 drm_mode_debug_printmodeline(mode);
5466
5467 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5468 if (!is_cpu_edp) {
5469 struct intel_pch_pll *pll;
5470
5471 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5472 if (pll == NULL) {
5473 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5474 pipe);
5475 return -EINVAL;
5476 }
5477 } else
5478 intel_put_pch_pll(intel_crtc);
5479
5480 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5481 * This is an exception to the general rule that mode_set doesn't turn
5482 * things on.
5483 */
5484 if (is_lvds) {
5485 temp = I915_READ(PCH_LVDS);
5486 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5487 if (HAS_PCH_CPT(dev)) {
5488 temp &= ~PORT_TRANS_SEL_MASK;
5489 temp |= PORT_TRANS_SEL_CPT(pipe);
5490 } else {
5491 if (pipe == 1)
5492 temp |= LVDS_PIPEB_SELECT;
5493 else
5494 temp &= ~LVDS_PIPEB_SELECT;
5495 }
5496
5497 /* set the corresponsding LVDS_BORDER bit */
5498 temp |= dev_priv->lvds_border_bits;
5499 /* Set the B0-B3 data pairs corresponding to whether we're going to
5500 * set the DPLLs for dual-channel mode or not.
5501 */
5502 if (clock.p2 == 7)
5503 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5504 else
5505 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5506
5507 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5508 * appropriately here, but we need to look more thoroughly into how
5509 * panels behave in the two modes.
5510 */
5511 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5512 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5513 temp |= LVDS_HSYNC_POLARITY;
5514 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5515 temp |= LVDS_VSYNC_POLARITY;
5516 I915_WRITE(PCH_LVDS, temp);
5517 }
5518
5519 if (is_dp && !is_cpu_edp) {
5520 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5521 } else {
5522 /* For non-DP output, clear any trans DP clock recovery setting.*/
5523 I915_WRITE(TRANSDATA_M1(pipe), 0);
5524 I915_WRITE(TRANSDATA_N1(pipe), 0);
5525 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5526 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5527 }
5528
5529 if (intel_crtc->pch_pll) {
5530 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5531
5532 /* Wait for the clocks to stabilize. */
5533 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5534 udelay(150);
5535
5536 /* The pixel multiplier can only be updated once the
5537 * DPLL is enabled and the clocks are stable.
5538 *
5539 * So write it again.
5540 */
5541 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5542 }
5543
5544 intel_crtc->lowfreq_avail = false;
5545 if (intel_crtc->pch_pll) {
5546 if (is_lvds && has_reduced_clock && i915_powersave) {
5547 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5548 intel_crtc->lowfreq_avail = true;
5549 } else {
5550 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5551 }
5552 }
5553
5554 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5555
5556 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5557 * ironlake_check_fdi_lanes. */
5558 ironlake_set_m_n(crtc, mode, adjusted_mode);
5559
5560 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5561
5562 if (is_cpu_edp)
5563 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5564
5565 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5566
5567 intel_wait_for_vblank(dev, pipe);
5568
5569 /* Set up the display plane register */
5570 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5571 POSTING_READ(DSPCNTR(plane));
5572
5573 ret = intel_pipe_set_base(crtc, x, y, fb);
5574
5575 intel_update_watermarks(dev);
5576
5577 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5578
5579 return fdi_config_ok ? ret : -EINVAL;
5580 }
5581
5582 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5583 struct drm_display_mode *mode,
5584 struct drm_display_mode *adjusted_mode,
5585 int x, int y,
5586 struct drm_framebuffer *fb)
5587 {
5588 struct drm_device *dev = crtc->dev;
5589 struct drm_i915_private *dev_priv = dev->dev_private;
5590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5591 int pipe = intel_crtc->pipe;
5592 int plane = intel_crtc->plane;
5593 int num_connectors = 0;
5594 intel_clock_t clock, reduced_clock;
5595 u32 dpll = 0, fp = 0, fp2 = 0;
5596 bool ok, has_reduced_clock = false;
5597 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5598 struct intel_encoder *encoder;
5599 u32 temp;
5600 int ret;
5601 bool dither;
5602
5603 for_each_encoder_on_crtc(dev, crtc, encoder) {
5604 switch (encoder->type) {
5605 case INTEL_OUTPUT_LVDS:
5606 is_lvds = true;
5607 break;
5608 case INTEL_OUTPUT_DISPLAYPORT:
5609 is_dp = true;
5610 break;
5611 case INTEL_OUTPUT_EDP:
5612 is_dp = true;
5613 if (!intel_encoder_is_pch_edp(&encoder->base))
5614 is_cpu_edp = true;
5615 break;
5616 }
5617
5618 num_connectors++;
5619 }
5620
5621 if (is_cpu_edp)
5622 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5623 else
5624 intel_crtc->cpu_transcoder = pipe;
5625
5626 /* We are not sure yet this won't happen. */
5627 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5628 INTEL_PCH_TYPE(dev));
5629
5630 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5631 num_connectors, pipe_name(pipe));
5632
5633 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5634 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5635
5636 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5637
5638 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5639 return -EINVAL;
5640
5641 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5642 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5643 &has_reduced_clock,
5644 &reduced_clock);
5645 if (!ok) {
5646 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5647 return -EINVAL;
5648 }
5649 }
5650
5651 /* Ensure that the cursor is valid for the new mode before changing... */
5652 intel_crtc_update_cursor(crtc, true);
5653
5654 /* determine panel color depth */
5655 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5656 adjusted_mode);
5657 if (is_lvds && dev_priv->lvds_dither)
5658 dither = true;
5659
5660 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5661 drm_mode_debug_printmodeline(mode);
5662
5663 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5664 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5665 if (has_reduced_clock)
5666 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5667 reduced_clock.m2;
5668
5669 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5670 fp);
5671
5672 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5673 * own on pre-Haswell/LPT generation */
5674 if (!is_cpu_edp) {
5675 struct intel_pch_pll *pll;
5676
5677 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5678 if (pll == NULL) {
5679 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5680 pipe);
5681 return -EINVAL;
5682 }
5683 } else
5684 intel_put_pch_pll(intel_crtc);
5685
5686 /* The LVDS pin pair needs to be on before the DPLLs are
5687 * enabled. This is an exception to the general rule that
5688 * mode_set doesn't turn things on.
5689 */
5690 if (is_lvds) {
5691 temp = I915_READ(PCH_LVDS);
5692 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5693 if (HAS_PCH_CPT(dev)) {
5694 temp &= ~PORT_TRANS_SEL_MASK;
5695 temp |= PORT_TRANS_SEL_CPT(pipe);
5696 } else {
5697 if (pipe == 1)
5698 temp |= LVDS_PIPEB_SELECT;
5699 else
5700 temp &= ~LVDS_PIPEB_SELECT;
5701 }
5702
5703 /* set the corresponsding LVDS_BORDER bit */
5704 temp |= dev_priv->lvds_border_bits;
5705 /* Set the B0-B3 data pairs corresponding to whether
5706 * we're going to set the DPLLs for dual-channel mode or
5707 * not.
5708 */
5709 if (clock.p2 == 7)
5710 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5711 else
5712 temp &= ~(LVDS_B0B3_POWER_UP |
5713 LVDS_CLKB_POWER_UP);
5714
5715 /* It would be nice to set 24 vs 18-bit mode
5716 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5717 * look more thoroughly into how panels behave in the
5718 * two modes.
5719 */
5720 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5721 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5722 temp |= LVDS_HSYNC_POLARITY;
5723 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5724 temp |= LVDS_VSYNC_POLARITY;
5725 I915_WRITE(PCH_LVDS, temp);
5726 }
5727 }
5728
5729 if (is_dp && !is_cpu_edp) {
5730 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5731 } else {
5732 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5733 /* For non-DP output, clear any trans DP clock recovery
5734 * setting.*/
5735 I915_WRITE(TRANSDATA_M1(pipe), 0);
5736 I915_WRITE(TRANSDATA_N1(pipe), 0);
5737 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5738 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5739 }
5740 }
5741
5742 intel_crtc->lowfreq_avail = false;
5743 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5744 if (intel_crtc->pch_pll) {
5745 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5746
5747 /* Wait for the clocks to stabilize. */
5748 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5749 udelay(150);
5750
5751 /* The pixel multiplier can only be updated once the
5752 * DPLL is enabled and the clocks are stable.
5753 *
5754 * So write it again.
5755 */
5756 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5757 }
5758
5759 if (intel_crtc->pch_pll) {
5760 if (is_lvds && has_reduced_clock && i915_powersave) {
5761 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5762 intel_crtc->lowfreq_avail = true;
5763 } else {
5764 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5765 }
5766 }
5767 }
5768
5769 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5770
5771 if (!is_dp || is_cpu_edp)
5772 ironlake_set_m_n(crtc, mode, adjusted_mode);
5773
5774 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5775 if (is_cpu_edp)
5776 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5777
5778 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5779
5780 /* Set up the display plane register */
5781 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5782 POSTING_READ(DSPCNTR(plane));
5783
5784 ret = intel_pipe_set_base(crtc, x, y, fb);
5785
5786 intel_update_watermarks(dev);
5787
5788 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5789
5790 return ret;
5791 }
5792
5793 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5794 struct drm_display_mode *mode,
5795 struct drm_display_mode *adjusted_mode,
5796 int x, int y,
5797 struct drm_framebuffer *fb)
5798 {
5799 struct drm_device *dev = crtc->dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 struct drm_encoder_helper_funcs *encoder_funcs;
5802 struct intel_encoder *encoder;
5803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5804 int pipe = intel_crtc->pipe;
5805 int ret;
5806
5807 drm_vblank_pre_modeset(dev, pipe);
5808
5809 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5810 x, y, fb);
5811 drm_vblank_post_modeset(dev, pipe);
5812
5813 if (ret != 0)
5814 return ret;
5815
5816 for_each_encoder_on_crtc(dev, crtc, encoder) {
5817 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5818 encoder->base.base.id,
5819 drm_get_encoder_name(&encoder->base),
5820 mode->base.id, mode->name);
5821 encoder_funcs = encoder->base.helper_private;
5822 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5823 }
5824
5825 return 0;
5826 }
5827
5828 static bool intel_eld_uptodate(struct drm_connector *connector,
5829 int reg_eldv, uint32_t bits_eldv,
5830 int reg_elda, uint32_t bits_elda,
5831 int reg_edid)
5832 {
5833 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5834 uint8_t *eld = connector->eld;
5835 uint32_t i;
5836
5837 i = I915_READ(reg_eldv);
5838 i &= bits_eldv;
5839
5840 if (!eld[0])
5841 return !i;
5842
5843 if (!i)
5844 return false;
5845
5846 i = I915_READ(reg_elda);
5847 i &= ~bits_elda;
5848 I915_WRITE(reg_elda, i);
5849
5850 for (i = 0; i < eld[2]; i++)
5851 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5852 return false;
5853
5854 return true;
5855 }
5856
5857 static void g4x_write_eld(struct drm_connector *connector,
5858 struct drm_crtc *crtc)
5859 {
5860 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5861 uint8_t *eld = connector->eld;
5862 uint32_t eldv;
5863 uint32_t len;
5864 uint32_t i;
5865
5866 i = I915_READ(G4X_AUD_VID_DID);
5867
5868 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5869 eldv = G4X_ELDV_DEVCL_DEVBLC;
5870 else
5871 eldv = G4X_ELDV_DEVCTG;
5872
5873 if (intel_eld_uptodate(connector,
5874 G4X_AUD_CNTL_ST, eldv,
5875 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5876 G4X_HDMIW_HDMIEDID))
5877 return;
5878
5879 i = I915_READ(G4X_AUD_CNTL_ST);
5880 i &= ~(eldv | G4X_ELD_ADDR);
5881 len = (i >> 9) & 0x1f; /* ELD buffer size */
5882 I915_WRITE(G4X_AUD_CNTL_ST, i);
5883
5884 if (!eld[0])
5885 return;
5886
5887 len = min_t(uint8_t, eld[2], len);
5888 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5889 for (i = 0; i < len; i++)
5890 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5891
5892 i = I915_READ(G4X_AUD_CNTL_ST);
5893 i |= eldv;
5894 I915_WRITE(G4X_AUD_CNTL_ST, i);
5895 }
5896
5897 static void haswell_write_eld(struct drm_connector *connector,
5898 struct drm_crtc *crtc)
5899 {
5900 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5901 uint8_t *eld = connector->eld;
5902 struct drm_device *dev = crtc->dev;
5903 uint32_t eldv;
5904 uint32_t i;
5905 int len;
5906 int pipe = to_intel_crtc(crtc)->pipe;
5907 int tmp;
5908
5909 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5910 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5911 int aud_config = HSW_AUD_CFG(pipe);
5912 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5913
5914
5915 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5916
5917 /* Audio output enable */
5918 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5919 tmp = I915_READ(aud_cntrl_st2);
5920 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5921 I915_WRITE(aud_cntrl_st2, tmp);
5922
5923 /* Wait for 1 vertical blank */
5924 intel_wait_for_vblank(dev, pipe);
5925
5926 /* Set ELD valid state */
5927 tmp = I915_READ(aud_cntrl_st2);
5928 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5929 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5930 I915_WRITE(aud_cntrl_st2, tmp);
5931 tmp = I915_READ(aud_cntrl_st2);
5932 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5933
5934 /* Enable HDMI mode */
5935 tmp = I915_READ(aud_config);
5936 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5937 /* clear N_programing_enable and N_value_index */
5938 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5939 I915_WRITE(aud_config, tmp);
5940
5941 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5942
5943 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5944
5945 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5946 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5947 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5948 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5949 } else
5950 I915_WRITE(aud_config, 0);
5951
5952 if (intel_eld_uptodate(connector,
5953 aud_cntrl_st2, eldv,
5954 aud_cntl_st, IBX_ELD_ADDRESS,
5955 hdmiw_hdmiedid))
5956 return;
5957
5958 i = I915_READ(aud_cntrl_st2);
5959 i &= ~eldv;
5960 I915_WRITE(aud_cntrl_st2, i);
5961
5962 if (!eld[0])
5963 return;
5964
5965 i = I915_READ(aud_cntl_st);
5966 i &= ~IBX_ELD_ADDRESS;
5967 I915_WRITE(aud_cntl_st, i);
5968 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5969 DRM_DEBUG_DRIVER("port num:%d\n", i);
5970
5971 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5972 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5973 for (i = 0; i < len; i++)
5974 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5975
5976 i = I915_READ(aud_cntrl_st2);
5977 i |= eldv;
5978 I915_WRITE(aud_cntrl_st2, i);
5979
5980 }
5981
5982 static void ironlake_write_eld(struct drm_connector *connector,
5983 struct drm_crtc *crtc)
5984 {
5985 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5986 uint8_t *eld = connector->eld;
5987 uint32_t eldv;
5988 uint32_t i;
5989 int len;
5990 int hdmiw_hdmiedid;
5991 int aud_config;
5992 int aud_cntl_st;
5993 int aud_cntrl_st2;
5994 int pipe = to_intel_crtc(crtc)->pipe;
5995
5996 if (HAS_PCH_IBX(connector->dev)) {
5997 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5998 aud_config = IBX_AUD_CFG(pipe);
5999 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6000 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6001 } else {
6002 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6003 aud_config = CPT_AUD_CFG(pipe);
6004 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6005 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6006 }
6007
6008 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6009
6010 i = I915_READ(aud_cntl_st);
6011 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6012 if (!i) {
6013 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6014 /* operate blindly on all ports */
6015 eldv = IBX_ELD_VALIDB;
6016 eldv |= IBX_ELD_VALIDB << 4;
6017 eldv |= IBX_ELD_VALIDB << 8;
6018 } else {
6019 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6020 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6021 }
6022
6023 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6024 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6025 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6026 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6027 } else
6028 I915_WRITE(aud_config, 0);
6029
6030 if (intel_eld_uptodate(connector,
6031 aud_cntrl_st2, eldv,
6032 aud_cntl_st, IBX_ELD_ADDRESS,
6033 hdmiw_hdmiedid))
6034 return;
6035
6036 i = I915_READ(aud_cntrl_st2);
6037 i &= ~eldv;
6038 I915_WRITE(aud_cntrl_st2, i);
6039
6040 if (!eld[0])
6041 return;
6042
6043 i = I915_READ(aud_cntl_st);
6044 i &= ~IBX_ELD_ADDRESS;
6045 I915_WRITE(aud_cntl_st, i);
6046
6047 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6048 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6049 for (i = 0; i < len; i++)
6050 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6051
6052 i = I915_READ(aud_cntrl_st2);
6053 i |= eldv;
6054 I915_WRITE(aud_cntrl_st2, i);
6055 }
6056
6057 void intel_write_eld(struct drm_encoder *encoder,
6058 struct drm_display_mode *mode)
6059 {
6060 struct drm_crtc *crtc = encoder->crtc;
6061 struct drm_connector *connector;
6062 struct drm_device *dev = encoder->dev;
6063 struct drm_i915_private *dev_priv = dev->dev_private;
6064
6065 connector = drm_select_eld(encoder, mode);
6066 if (!connector)
6067 return;
6068
6069 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6070 connector->base.id,
6071 drm_get_connector_name(connector),
6072 connector->encoder->base.id,
6073 drm_get_encoder_name(connector->encoder));
6074
6075 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6076
6077 if (dev_priv->display.write_eld)
6078 dev_priv->display.write_eld(connector, crtc);
6079 }
6080
6081 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6082 void intel_crtc_load_lut(struct drm_crtc *crtc)
6083 {
6084 struct drm_device *dev = crtc->dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6087 int palreg = PALETTE(intel_crtc->pipe);
6088 int i;
6089
6090 /* The clocks have to be on to load the palette. */
6091 if (!crtc->enabled || !intel_crtc->active)
6092 return;
6093
6094 /* use legacy palette for Ironlake */
6095 if (HAS_PCH_SPLIT(dev))
6096 palreg = LGC_PALETTE(intel_crtc->pipe);
6097
6098 for (i = 0; i < 256; i++) {
6099 I915_WRITE(palreg + 4 * i,
6100 (intel_crtc->lut_r[i] << 16) |
6101 (intel_crtc->lut_g[i] << 8) |
6102 intel_crtc->lut_b[i]);
6103 }
6104 }
6105
6106 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6107 {
6108 struct drm_device *dev = crtc->dev;
6109 struct drm_i915_private *dev_priv = dev->dev_private;
6110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6111 bool visible = base != 0;
6112 u32 cntl;
6113
6114 if (intel_crtc->cursor_visible == visible)
6115 return;
6116
6117 cntl = I915_READ(_CURACNTR);
6118 if (visible) {
6119 /* On these chipsets we can only modify the base whilst
6120 * the cursor is disabled.
6121 */
6122 I915_WRITE(_CURABASE, base);
6123
6124 cntl &= ~(CURSOR_FORMAT_MASK);
6125 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6126 cntl |= CURSOR_ENABLE |
6127 CURSOR_GAMMA_ENABLE |
6128 CURSOR_FORMAT_ARGB;
6129 } else
6130 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6131 I915_WRITE(_CURACNTR, cntl);
6132
6133 intel_crtc->cursor_visible = visible;
6134 }
6135
6136 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6137 {
6138 struct drm_device *dev = crtc->dev;
6139 struct drm_i915_private *dev_priv = dev->dev_private;
6140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6141 int pipe = intel_crtc->pipe;
6142 bool visible = base != 0;
6143
6144 if (intel_crtc->cursor_visible != visible) {
6145 uint32_t cntl = I915_READ(CURCNTR(pipe));
6146 if (base) {
6147 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6148 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6149 cntl |= pipe << 28; /* Connect to correct pipe */
6150 } else {
6151 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6152 cntl |= CURSOR_MODE_DISABLE;
6153 }
6154 I915_WRITE(CURCNTR(pipe), cntl);
6155
6156 intel_crtc->cursor_visible = visible;
6157 }
6158 /* and commit changes on next vblank */
6159 I915_WRITE(CURBASE(pipe), base);
6160 }
6161
6162 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6163 {
6164 struct drm_device *dev = crtc->dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167 int pipe = intel_crtc->pipe;
6168 bool visible = base != 0;
6169
6170 if (intel_crtc->cursor_visible != visible) {
6171 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6172 if (base) {
6173 cntl &= ~CURSOR_MODE;
6174 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6175 } else {
6176 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6177 cntl |= CURSOR_MODE_DISABLE;
6178 }
6179 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6180
6181 intel_crtc->cursor_visible = visible;
6182 }
6183 /* and commit changes on next vblank */
6184 I915_WRITE(CURBASE_IVB(pipe), base);
6185 }
6186
6187 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6188 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6189 bool on)
6190 {
6191 struct drm_device *dev = crtc->dev;
6192 struct drm_i915_private *dev_priv = dev->dev_private;
6193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6194 int pipe = intel_crtc->pipe;
6195 int x = intel_crtc->cursor_x;
6196 int y = intel_crtc->cursor_y;
6197 u32 base, pos;
6198 bool visible;
6199
6200 pos = 0;
6201
6202 if (on && crtc->enabled && crtc->fb) {
6203 base = intel_crtc->cursor_addr;
6204 if (x > (int) crtc->fb->width)
6205 base = 0;
6206
6207 if (y > (int) crtc->fb->height)
6208 base = 0;
6209 } else
6210 base = 0;
6211
6212 if (x < 0) {
6213 if (x + intel_crtc->cursor_width < 0)
6214 base = 0;
6215
6216 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6217 x = -x;
6218 }
6219 pos |= x << CURSOR_X_SHIFT;
6220
6221 if (y < 0) {
6222 if (y + intel_crtc->cursor_height < 0)
6223 base = 0;
6224
6225 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6226 y = -y;
6227 }
6228 pos |= y << CURSOR_Y_SHIFT;
6229
6230 visible = base != 0;
6231 if (!visible && !intel_crtc->cursor_visible)
6232 return;
6233
6234 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6235 I915_WRITE(CURPOS_IVB(pipe), pos);
6236 ivb_update_cursor(crtc, base);
6237 } else {
6238 I915_WRITE(CURPOS(pipe), pos);
6239 if (IS_845G(dev) || IS_I865G(dev))
6240 i845_update_cursor(crtc, base);
6241 else
6242 i9xx_update_cursor(crtc, base);
6243 }
6244 }
6245
6246 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6247 struct drm_file *file,
6248 uint32_t handle,
6249 uint32_t width, uint32_t height)
6250 {
6251 struct drm_device *dev = crtc->dev;
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254 struct drm_i915_gem_object *obj;
6255 uint32_t addr;
6256 int ret;
6257
6258 /* if we want to turn off the cursor ignore width and height */
6259 if (!handle) {
6260 DRM_DEBUG_KMS("cursor off\n");
6261 addr = 0;
6262 obj = NULL;
6263 mutex_lock(&dev->struct_mutex);
6264 goto finish;
6265 }
6266
6267 /* Currently we only support 64x64 cursors */
6268 if (width != 64 || height != 64) {
6269 DRM_ERROR("we currently only support 64x64 cursors\n");
6270 return -EINVAL;
6271 }
6272
6273 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6274 if (&obj->base == NULL)
6275 return -ENOENT;
6276
6277 if (obj->base.size < width * height * 4) {
6278 DRM_ERROR("buffer is to small\n");
6279 ret = -ENOMEM;
6280 goto fail;
6281 }
6282
6283 /* we only need to pin inside GTT if cursor is non-phy */
6284 mutex_lock(&dev->struct_mutex);
6285 if (!dev_priv->info->cursor_needs_physical) {
6286 if (obj->tiling_mode) {
6287 DRM_ERROR("cursor cannot be tiled\n");
6288 ret = -EINVAL;
6289 goto fail_locked;
6290 }
6291
6292 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6293 if (ret) {
6294 DRM_ERROR("failed to move cursor bo into the GTT\n");
6295 goto fail_locked;
6296 }
6297
6298 ret = i915_gem_object_put_fence(obj);
6299 if (ret) {
6300 DRM_ERROR("failed to release fence for cursor");
6301 goto fail_unpin;
6302 }
6303
6304 addr = obj->gtt_offset;
6305 } else {
6306 int align = IS_I830(dev) ? 16 * 1024 : 256;
6307 ret = i915_gem_attach_phys_object(dev, obj,
6308 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6309 align);
6310 if (ret) {
6311 DRM_ERROR("failed to attach phys object\n");
6312 goto fail_locked;
6313 }
6314 addr = obj->phys_obj->handle->busaddr;
6315 }
6316
6317 if (IS_GEN2(dev))
6318 I915_WRITE(CURSIZE, (height << 12) | width);
6319
6320 finish:
6321 if (intel_crtc->cursor_bo) {
6322 if (dev_priv->info->cursor_needs_physical) {
6323 if (intel_crtc->cursor_bo != obj)
6324 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6325 } else
6326 i915_gem_object_unpin(intel_crtc->cursor_bo);
6327 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6328 }
6329
6330 mutex_unlock(&dev->struct_mutex);
6331
6332 intel_crtc->cursor_addr = addr;
6333 intel_crtc->cursor_bo = obj;
6334 intel_crtc->cursor_width = width;
6335 intel_crtc->cursor_height = height;
6336
6337 intel_crtc_update_cursor(crtc, true);
6338
6339 return 0;
6340 fail_unpin:
6341 i915_gem_object_unpin(obj);
6342 fail_locked:
6343 mutex_unlock(&dev->struct_mutex);
6344 fail:
6345 drm_gem_object_unreference_unlocked(&obj->base);
6346 return ret;
6347 }
6348
6349 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6350 {
6351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6352
6353 intel_crtc->cursor_x = x;
6354 intel_crtc->cursor_y = y;
6355
6356 intel_crtc_update_cursor(crtc, true);
6357
6358 return 0;
6359 }
6360
6361 /** Sets the color ramps on behalf of RandR */
6362 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6363 u16 blue, int regno)
6364 {
6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6366
6367 intel_crtc->lut_r[regno] = red >> 8;
6368 intel_crtc->lut_g[regno] = green >> 8;
6369 intel_crtc->lut_b[regno] = blue >> 8;
6370 }
6371
6372 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6373 u16 *blue, int regno)
6374 {
6375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376
6377 *red = intel_crtc->lut_r[regno] << 8;
6378 *green = intel_crtc->lut_g[regno] << 8;
6379 *blue = intel_crtc->lut_b[regno] << 8;
6380 }
6381
6382 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6383 u16 *blue, uint32_t start, uint32_t size)
6384 {
6385 int end = (start + size > 256) ? 256 : start + size, i;
6386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387
6388 for (i = start; i < end; i++) {
6389 intel_crtc->lut_r[i] = red[i] >> 8;
6390 intel_crtc->lut_g[i] = green[i] >> 8;
6391 intel_crtc->lut_b[i] = blue[i] >> 8;
6392 }
6393
6394 intel_crtc_load_lut(crtc);
6395 }
6396
6397 /**
6398 * Get a pipe with a simple mode set on it for doing load-based monitor
6399 * detection.
6400 *
6401 * It will be up to the load-detect code to adjust the pipe as appropriate for
6402 * its requirements. The pipe will be connected to no other encoders.
6403 *
6404 * Currently this code will only succeed if there is a pipe with no encoders
6405 * configured for it. In the future, it could choose to temporarily disable
6406 * some outputs to free up a pipe for its use.
6407 *
6408 * \return crtc, or NULL if no pipes are available.
6409 */
6410
6411 /* VESA 640x480x72Hz mode to set on the pipe */
6412 static struct drm_display_mode load_detect_mode = {
6413 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6414 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6415 };
6416
6417 static struct drm_framebuffer *
6418 intel_framebuffer_create(struct drm_device *dev,
6419 struct drm_mode_fb_cmd2 *mode_cmd,
6420 struct drm_i915_gem_object *obj)
6421 {
6422 struct intel_framebuffer *intel_fb;
6423 int ret;
6424
6425 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6426 if (!intel_fb) {
6427 drm_gem_object_unreference_unlocked(&obj->base);
6428 return ERR_PTR(-ENOMEM);
6429 }
6430
6431 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6432 if (ret) {
6433 drm_gem_object_unreference_unlocked(&obj->base);
6434 kfree(intel_fb);
6435 return ERR_PTR(ret);
6436 }
6437
6438 return &intel_fb->base;
6439 }
6440
6441 static u32
6442 intel_framebuffer_pitch_for_width(int width, int bpp)
6443 {
6444 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6445 return ALIGN(pitch, 64);
6446 }
6447
6448 static u32
6449 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6450 {
6451 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6452 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6453 }
6454
6455 static struct drm_framebuffer *
6456 intel_framebuffer_create_for_mode(struct drm_device *dev,
6457 struct drm_display_mode *mode,
6458 int depth, int bpp)
6459 {
6460 struct drm_i915_gem_object *obj;
6461 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6462
6463 obj = i915_gem_alloc_object(dev,
6464 intel_framebuffer_size_for_mode(mode, bpp));
6465 if (obj == NULL)
6466 return ERR_PTR(-ENOMEM);
6467
6468 mode_cmd.width = mode->hdisplay;
6469 mode_cmd.height = mode->vdisplay;
6470 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6471 bpp);
6472 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6473
6474 return intel_framebuffer_create(dev, &mode_cmd, obj);
6475 }
6476
6477 static struct drm_framebuffer *
6478 mode_fits_in_fbdev(struct drm_device *dev,
6479 struct drm_display_mode *mode)
6480 {
6481 struct drm_i915_private *dev_priv = dev->dev_private;
6482 struct drm_i915_gem_object *obj;
6483 struct drm_framebuffer *fb;
6484
6485 if (dev_priv->fbdev == NULL)
6486 return NULL;
6487
6488 obj = dev_priv->fbdev->ifb.obj;
6489 if (obj == NULL)
6490 return NULL;
6491
6492 fb = &dev_priv->fbdev->ifb.base;
6493 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6494 fb->bits_per_pixel))
6495 return NULL;
6496
6497 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6498 return NULL;
6499
6500 return fb;
6501 }
6502
6503 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6504 struct drm_display_mode *mode,
6505 struct intel_load_detect_pipe *old)
6506 {
6507 struct intel_crtc *intel_crtc;
6508 struct intel_encoder *intel_encoder =
6509 intel_attached_encoder(connector);
6510 struct drm_crtc *possible_crtc;
6511 struct drm_encoder *encoder = &intel_encoder->base;
6512 struct drm_crtc *crtc = NULL;
6513 struct drm_device *dev = encoder->dev;
6514 struct drm_framebuffer *fb;
6515 int i = -1;
6516
6517 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6518 connector->base.id, drm_get_connector_name(connector),
6519 encoder->base.id, drm_get_encoder_name(encoder));
6520
6521 /*
6522 * Algorithm gets a little messy:
6523 *
6524 * - if the connector already has an assigned crtc, use it (but make
6525 * sure it's on first)
6526 *
6527 * - try to find the first unused crtc that can drive this connector,
6528 * and use that if we find one
6529 */
6530
6531 /* See if we already have a CRTC for this connector */
6532 if (encoder->crtc) {
6533 crtc = encoder->crtc;
6534
6535 old->dpms_mode = connector->dpms;
6536 old->load_detect_temp = false;
6537
6538 /* Make sure the crtc and connector are running */
6539 if (connector->dpms != DRM_MODE_DPMS_ON)
6540 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6541
6542 return true;
6543 }
6544
6545 /* Find an unused one (if possible) */
6546 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6547 i++;
6548 if (!(encoder->possible_crtcs & (1 << i)))
6549 continue;
6550 if (!possible_crtc->enabled) {
6551 crtc = possible_crtc;
6552 break;
6553 }
6554 }
6555
6556 /*
6557 * If we didn't find an unused CRTC, don't use any.
6558 */
6559 if (!crtc) {
6560 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6561 return false;
6562 }
6563
6564 intel_encoder->new_crtc = to_intel_crtc(crtc);
6565 to_intel_connector(connector)->new_encoder = intel_encoder;
6566
6567 intel_crtc = to_intel_crtc(crtc);
6568 old->dpms_mode = connector->dpms;
6569 old->load_detect_temp = true;
6570 old->release_fb = NULL;
6571
6572 if (!mode)
6573 mode = &load_detect_mode;
6574
6575 /* We need a framebuffer large enough to accommodate all accesses
6576 * that the plane may generate whilst we perform load detection.
6577 * We can not rely on the fbcon either being present (we get called
6578 * during its initialisation to detect all boot displays, or it may
6579 * not even exist) or that it is large enough to satisfy the
6580 * requested mode.
6581 */
6582 fb = mode_fits_in_fbdev(dev, mode);
6583 if (fb == NULL) {
6584 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6585 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6586 old->release_fb = fb;
6587 } else
6588 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6589 if (IS_ERR(fb)) {
6590 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6591 return false;
6592 }
6593
6594 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6595 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6596 if (old->release_fb)
6597 old->release_fb->funcs->destroy(old->release_fb);
6598 return false;
6599 }
6600
6601 /* let the connector get through one full cycle before testing */
6602 intel_wait_for_vblank(dev, intel_crtc->pipe);
6603 return true;
6604 }
6605
6606 void intel_release_load_detect_pipe(struct drm_connector *connector,
6607 struct intel_load_detect_pipe *old)
6608 {
6609 struct intel_encoder *intel_encoder =
6610 intel_attached_encoder(connector);
6611 struct drm_encoder *encoder = &intel_encoder->base;
6612
6613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6614 connector->base.id, drm_get_connector_name(connector),
6615 encoder->base.id, drm_get_encoder_name(encoder));
6616
6617 if (old->load_detect_temp) {
6618 struct drm_crtc *crtc = encoder->crtc;
6619
6620 to_intel_connector(connector)->new_encoder = NULL;
6621 intel_encoder->new_crtc = NULL;
6622 intel_set_mode(crtc, NULL, 0, 0, NULL);
6623
6624 if (old->release_fb)
6625 old->release_fb->funcs->destroy(old->release_fb);
6626
6627 return;
6628 }
6629
6630 /* Switch crtc and encoder back off if necessary */
6631 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6632 connector->funcs->dpms(connector, old->dpms_mode);
6633 }
6634
6635 /* Returns the clock of the currently programmed mode of the given pipe. */
6636 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6637 {
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6640 int pipe = intel_crtc->pipe;
6641 u32 dpll = I915_READ(DPLL(pipe));
6642 u32 fp;
6643 intel_clock_t clock;
6644
6645 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6646 fp = I915_READ(FP0(pipe));
6647 else
6648 fp = I915_READ(FP1(pipe));
6649
6650 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6651 if (IS_PINEVIEW(dev)) {
6652 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6653 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6654 } else {
6655 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6656 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6657 }
6658
6659 if (!IS_GEN2(dev)) {
6660 if (IS_PINEVIEW(dev))
6661 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6662 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6663 else
6664 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6665 DPLL_FPA01_P1_POST_DIV_SHIFT);
6666
6667 switch (dpll & DPLL_MODE_MASK) {
6668 case DPLLB_MODE_DAC_SERIAL:
6669 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6670 5 : 10;
6671 break;
6672 case DPLLB_MODE_LVDS:
6673 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6674 7 : 14;
6675 break;
6676 default:
6677 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6678 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6679 return 0;
6680 }
6681
6682 /* XXX: Handle the 100Mhz refclk */
6683 intel_clock(dev, 96000, &clock);
6684 } else {
6685 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6686
6687 if (is_lvds) {
6688 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6689 DPLL_FPA01_P1_POST_DIV_SHIFT);
6690 clock.p2 = 14;
6691
6692 if ((dpll & PLL_REF_INPUT_MASK) ==
6693 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6694 /* XXX: might not be 66MHz */
6695 intel_clock(dev, 66000, &clock);
6696 } else
6697 intel_clock(dev, 48000, &clock);
6698 } else {
6699 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6700 clock.p1 = 2;
6701 else {
6702 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6703 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6704 }
6705 if (dpll & PLL_P2_DIVIDE_BY_4)
6706 clock.p2 = 4;
6707 else
6708 clock.p2 = 2;
6709
6710 intel_clock(dev, 48000, &clock);
6711 }
6712 }
6713
6714 /* XXX: It would be nice to validate the clocks, but we can't reuse
6715 * i830PllIsValid() because it relies on the xf86_config connector
6716 * configuration being accurate, which it isn't necessarily.
6717 */
6718
6719 return clock.dot;
6720 }
6721
6722 /** Returns the currently programmed mode of the given pipe. */
6723 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6724 struct drm_crtc *crtc)
6725 {
6726 struct drm_i915_private *dev_priv = dev->dev_private;
6727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6728 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6729 struct drm_display_mode *mode;
6730 int htot = I915_READ(HTOTAL(cpu_transcoder));
6731 int hsync = I915_READ(HSYNC(cpu_transcoder));
6732 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6733 int vsync = I915_READ(VSYNC(cpu_transcoder));
6734
6735 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6736 if (!mode)
6737 return NULL;
6738
6739 mode->clock = intel_crtc_clock_get(dev, crtc);
6740 mode->hdisplay = (htot & 0xffff) + 1;
6741 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6742 mode->hsync_start = (hsync & 0xffff) + 1;
6743 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6744 mode->vdisplay = (vtot & 0xffff) + 1;
6745 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6746 mode->vsync_start = (vsync & 0xffff) + 1;
6747 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6748
6749 drm_mode_set_name(mode);
6750
6751 return mode;
6752 }
6753
6754 static void intel_increase_pllclock(struct drm_crtc *crtc)
6755 {
6756 struct drm_device *dev = crtc->dev;
6757 drm_i915_private_t *dev_priv = dev->dev_private;
6758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6759 int pipe = intel_crtc->pipe;
6760 int dpll_reg = DPLL(pipe);
6761 int dpll;
6762
6763 if (HAS_PCH_SPLIT(dev))
6764 return;
6765
6766 if (!dev_priv->lvds_downclock_avail)
6767 return;
6768
6769 dpll = I915_READ(dpll_reg);
6770 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6771 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6772
6773 assert_panel_unlocked(dev_priv, pipe);
6774
6775 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6776 I915_WRITE(dpll_reg, dpll);
6777 intel_wait_for_vblank(dev, pipe);
6778
6779 dpll = I915_READ(dpll_reg);
6780 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6781 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6782 }
6783 }
6784
6785 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6786 {
6787 struct drm_device *dev = crtc->dev;
6788 drm_i915_private_t *dev_priv = dev->dev_private;
6789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6790
6791 if (HAS_PCH_SPLIT(dev))
6792 return;
6793
6794 if (!dev_priv->lvds_downclock_avail)
6795 return;
6796
6797 /*
6798 * Since this is called by a timer, we should never get here in
6799 * the manual case.
6800 */
6801 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6802 int pipe = intel_crtc->pipe;
6803 int dpll_reg = DPLL(pipe);
6804 int dpll;
6805
6806 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6807
6808 assert_panel_unlocked(dev_priv, pipe);
6809
6810 dpll = I915_READ(dpll_reg);
6811 dpll |= DISPLAY_RATE_SELECT_FPA1;
6812 I915_WRITE(dpll_reg, dpll);
6813 intel_wait_for_vblank(dev, pipe);
6814 dpll = I915_READ(dpll_reg);
6815 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6816 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6817 }
6818
6819 }
6820
6821 void intel_mark_busy(struct drm_device *dev)
6822 {
6823 i915_update_gfx_val(dev->dev_private);
6824 }
6825
6826 void intel_mark_idle(struct drm_device *dev)
6827 {
6828 }
6829
6830 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6831 {
6832 struct drm_device *dev = obj->base.dev;
6833 struct drm_crtc *crtc;
6834
6835 if (!i915_powersave)
6836 return;
6837
6838 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6839 if (!crtc->fb)
6840 continue;
6841
6842 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6843 intel_increase_pllclock(crtc);
6844 }
6845 }
6846
6847 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6848 {
6849 struct drm_device *dev = obj->base.dev;
6850 struct drm_crtc *crtc;
6851
6852 if (!i915_powersave)
6853 return;
6854
6855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6856 if (!crtc->fb)
6857 continue;
6858
6859 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6860 intel_decrease_pllclock(crtc);
6861 }
6862 }
6863
6864 static void intel_crtc_destroy(struct drm_crtc *crtc)
6865 {
6866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6867 struct drm_device *dev = crtc->dev;
6868 struct intel_unpin_work *work;
6869 unsigned long flags;
6870
6871 spin_lock_irqsave(&dev->event_lock, flags);
6872 work = intel_crtc->unpin_work;
6873 intel_crtc->unpin_work = NULL;
6874 spin_unlock_irqrestore(&dev->event_lock, flags);
6875
6876 if (work) {
6877 cancel_work_sync(&work->work);
6878 kfree(work);
6879 }
6880
6881 drm_crtc_cleanup(crtc);
6882
6883 kfree(intel_crtc);
6884 }
6885
6886 static void intel_unpin_work_fn(struct work_struct *__work)
6887 {
6888 struct intel_unpin_work *work =
6889 container_of(__work, struct intel_unpin_work, work);
6890 struct drm_device *dev = work->crtc->dev;
6891
6892 mutex_lock(&dev->struct_mutex);
6893 intel_unpin_fb_obj(work->old_fb_obj);
6894 drm_gem_object_unreference(&work->pending_flip_obj->base);
6895 drm_gem_object_unreference(&work->old_fb_obj->base);
6896
6897 intel_update_fbc(dev);
6898 mutex_unlock(&dev->struct_mutex);
6899
6900 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6901 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6902
6903 kfree(work);
6904 }
6905
6906 static void do_intel_finish_page_flip(struct drm_device *dev,
6907 struct drm_crtc *crtc)
6908 {
6909 drm_i915_private_t *dev_priv = dev->dev_private;
6910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6911 struct intel_unpin_work *work;
6912 struct drm_i915_gem_object *obj;
6913 struct drm_pending_vblank_event *e;
6914 struct timeval tvbl;
6915 unsigned long flags;
6916
6917 /* Ignore early vblank irqs */
6918 if (intel_crtc == NULL)
6919 return;
6920
6921 spin_lock_irqsave(&dev->event_lock, flags);
6922 work = intel_crtc->unpin_work;
6923 if (work == NULL || !work->pending) {
6924 spin_unlock_irqrestore(&dev->event_lock, flags);
6925 return;
6926 }
6927
6928 intel_crtc->unpin_work = NULL;
6929
6930 if (work->event) {
6931 e = work->event;
6932 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6933
6934 e->event.tv_sec = tvbl.tv_sec;
6935 e->event.tv_usec = tvbl.tv_usec;
6936
6937 list_add_tail(&e->base.link,
6938 &e->base.file_priv->event_list);
6939 wake_up_interruptible(&e->base.file_priv->event_wait);
6940 }
6941
6942 drm_vblank_put(dev, intel_crtc->pipe);
6943
6944 spin_unlock_irqrestore(&dev->event_lock, flags);
6945
6946 obj = work->old_fb_obj;
6947
6948 atomic_clear_mask(1 << intel_crtc->plane,
6949 &obj->pending_flip.counter);
6950 wake_up(&dev_priv->pending_flip_queue);
6951
6952 queue_work(dev_priv->wq, &work->work);
6953
6954 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6955 }
6956
6957 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6958 {
6959 drm_i915_private_t *dev_priv = dev->dev_private;
6960 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6961
6962 do_intel_finish_page_flip(dev, crtc);
6963 }
6964
6965 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6966 {
6967 drm_i915_private_t *dev_priv = dev->dev_private;
6968 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6969
6970 do_intel_finish_page_flip(dev, crtc);
6971 }
6972
6973 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6974 {
6975 drm_i915_private_t *dev_priv = dev->dev_private;
6976 struct intel_crtc *intel_crtc =
6977 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6978 unsigned long flags;
6979
6980 spin_lock_irqsave(&dev->event_lock, flags);
6981 if (intel_crtc->unpin_work) {
6982 if ((++intel_crtc->unpin_work->pending) > 1)
6983 DRM_ERROR("Prepared flip multiple times\n");
6984 } else {
6985 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6986 }
6987 spin_unlock_irqrestore(&dev->event_lock, flags);
6988 }
6989
6990 static int intel_gen2_queue_flip(struct drm_device *dev,
6991 struct drm_crtc *crtc,
6992 struct drm_framebuffer *fb,
6993 struct drm_i915_gem_object *obj)
6994 {
6995 struct drm_i915_private *dev_priv = dev->dev_private;
6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6997 u32 flip_mask;
6998 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6999 int ret;
7000
7001 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7002 if (ret)
7003 goto err;
7004
7005 ret = intel_ring_begin(ring, 6);
7006 if (ret)
7007 goto err_unpin;
7008
7009 /* Can't queue multiple flips, so wait for the previous
7010 * one to finish before executing the next.
7011 */
7012 if (intel_crtc->plane)
7013 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7014 else
7015 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7016 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7017 intel_ring_emit(ring, MI_NOOP);
7018 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7019 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7020 intel_ring_emit(ring, fb->pitches[0]);
7021 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7022 intel_ring_emit(ring, 0); /* aux display base address, unused */
7023 intel_ring_advance(ring);
7024 return 0;
7025
7026 err_unpin:
7027 intel_unpin_fb_obj(obj);
7028 err:
7029 return ret;
7030 }
7031
7032 static int intel_gen3_queue_flip(struct drm_device *dev,
7033 struct drm_crtc *crtc,
7034 struct drm_framebuffer *fb,
7035 struct drm_i915_gem_object *obj)
7036 {
7037 struct drm_i915_private *dev_priv = dev->dev_private;
7038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7039 u32 flip_mask;
7040 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7041 int ret;
7042
7043 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7044 if (ret)
7045 goto err;
7046
7047 ret = intel_ring_begin(ring, 6);
7048 if (ret)
7049 goto err_unpin;
7050
7051 if (intel_crtc->plane)
7052 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7053 else
7054 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7055 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7056 intel_ring_emit(ring, MI_NOOP);
7057 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7058 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7059 intel_ring_emit(ring, fb->pitches[0]);
7060 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7061 intel_ring_emit(ring, MI_NOOP);
7062
7063 intel_ring_advance(ring);
7064 return 0;
7065
7066 err_unpin:
7067 intel_unpin_fb_obj(obj);
7068 err:
7069 return ret;
7070 }
7071
7072 static int intel_gen4_queue_flip(struct drm_device *dev,
7073 struct drm_crtc *crtc,
7074 struct drm_framebuffer *fb,
7075 struct drm_i915_gem_object *obj)
7076 {
7077 struct drm_i915_private *dev_priv = dev->dev_private;
7078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079 uint32_t pf, pipesrc;
7080 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7081 int ret;
7082
7083 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7084 if (ret)
7085 goto err;
7086
7087 ret = intel_ring_begin(ring, 4);
7088 if (ret)
7089 goto err_unpin;
7090
7091 /* i965+ uses the linear or tiled offsets from the
7092 * Display Registers (which do not change across a page-flip)
7093 * so we need only reprogram the base address.
7094 */
7095 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7096 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7097 intel_ring_emit(ring, fb->pitches[0]);
7098 intel_ring_emit(ring,
7099 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7100 obj->tiling_mode);
7101
7102 /* XXX Enabling the panel-fitter across page-flip is so far
7103 * untested on non-native modes, so ignore it for now.
7104 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7105 */
7106 pf = 0;
7107 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7108 intel_ring_emit(ring, pf | pipesrc);
7109 intel_ring_advance(ring);
7110 return 0;
7111
7112 err_unpin:
7113 intel_unpin_fb_obj(obj);
7114 err:
7115 return ret;
7116 }
7117
7118 static int intel_gen6_queue_flip(struct drm_device *dev,
7119 struct drm_crtc *crtc,
7120 struct drm_framebuffer *fb,
7121 struct drm_i915_gem_object *obj)
7122 {
7123 struct drm_i915_private *dev_priv = dev->dev_private;
7124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7125 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7126 uint32_t pf, pipesrc;
7127 int ret;
7128
7129 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7130 if (ret)
7131 goto err;
7132
7133 ret = intel_ring_begin(ring, 4);
7134 if (ret)
7135 goto err_unpin;
7136
7137 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7138 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7139 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7140 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7141
7142 /* Contrary to the suggestions in the documentation,
7143 * "Enable Panel Fitter" does not seem to be required when page
7144 * flipping with a non-native mode, and worse causes a normal
7145 * modeset to fail.
7146 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7147 */
7148 pf = 0;
7149 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7150 intel_ring_emit(ring, pf | pipesrc);
7151 intel_ring_advance(ring);
7152 return 0;
7153
7154 err_unpin:
7155 intel_unpin_fb_obj(obj);
7156 err:
7157 return ret;
7158 }
7159
7160 /*
7161 * On gen7 we currently use the blit ring because (in early silicon at least)
7162 * the render ring doesn't give us interrpts for page flip completion, which
7163 * means clients will hang after the first flip is queued. Fortunately the
7164 * blit ring generates interrupts properly, so use it instead.
7165 */
7166 static int intel_gen7_queue_flip(struct drm_device *dev,
7167 struct drm_crtc *crtc,
7168 struct drm_framebuffer *fb,
7169 struct drm_i915_gem_object *obj)
7170 {
7171 struct drm_i915_private *dev_priv = dev->dev_private;
7172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7173 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7174 uint32_t plane_bit = 0;
7175 int ret;
7176
7177 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7178 if (ret)
7179 goto err;
7180
7181 switch(intel_crtc->plane) {
7182 case PLANE_A:
7183 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7184 break;
7185 case PLANE_B:
7186 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7187 break;
7188 case PLANE_C:
7189 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7190 break;
7191 default:
7192 WARN_ONCE(1, "unknown plane in flip command\n");
7193 ret = -ENODEV;
7194 goto err_unpin;
7195 }
7196
7197 ret = intel_ring_begin(ring, 4);
7198 if (ret)
7199 goto err_unpin;
7200
7201 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7202 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7203 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7204 intel_ring_emit(ring, (MI_NOOP));
7205 intel_ring_advance(ring);
7206 return 0;
7207
7208 err_unpin:
7209 intel_unpin_fb_obj(obj);
7210 err:
7211 return ret;
7212 }
7213
7214 static int intel_default_queue_flip(struct drm_device *dev,
7215 struct drm_crtc *crtc,
7216 struct drm_framebuffer *fb,
7217 struct drm_i915_gem_object *obj)
7218 {
7219 return -ENODEV;
7220 }
7221
7222 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7223 struct drm_framebuffer *fb,
7224 struct drm_pending_vblank_event *event)
7225 {
7226 struct drm_device *dev = crtc->dev;
7227 struct drm_i915_private *dev_priv = dev->dev_private;
7228 struct intel_framebuffer *intel_fb;
7229 struct drm_i915_gem_object *obj;
7230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231 struct intel_unpin_work *work;
7232 unsigned long flags;
7233 int ret;
7234
7235 /* Can't change pixel format via MI display flips. */
7236 if (fb->pixel_format != crtc->fb->pixel_format)
7237 return -EINVAL;
7238
7239 /*
7240 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7241 * Note that pitch changes could also affect these register.
7242 */
7243 if (INTEL_INFO(dev)->gen > 3 &&
7244 (fb->offsets[0] != crtc->fb->offsets[0] ||
7245 fb->pitches[0] != crtc->fb->pitches[0]))
7246 return -EINVAL;
7247
7248 work = kzalloc(sizeof *work, GFP_KERNEL);
7249 if (work == NULL)
7250 return -ENOMEM;
7251
7252 work->event = event;
7253 work->crtc = crtc;
7254 intel_fb = to_intel_framebuffer(crtc->fb);
7255 work->old_fb_obj = intel_fb->obj;
7256 INIT_WORK(&work->work, intel_unpin_work_fn);
7257
7258 ret = drm_vblank_get(dev, intel_crtc->pipe);
7259 if (ret)
7260 goto free_work;
7261
7262 /* We borrow the event spin lock for protecting unpin_work */
7263 spin_lock_irqsave(&dev->event_lock, flags);
7264 if (intel_crtc->unpin_work) {
7265 spin_unlock_irqrestore(&dev->event_lock, flags);
7266 kfree(work);
7267 drm_vblank_put(dev, intel_crtc->pipe);
7268
7269 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7270 return -EBUSY;
7271 }
7272 intel_crtc->unpin_work = work;
7273 spin_unlock_irqrestore(&dev->event_lock, flags);
7274
7275 intel_fb = to_intel_framebuffer(fb);
7276 obj = intel_fb->obj;
7277
7278 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7279 flush_workqueue(dev_priv->wq);
7280
7281 ret = i915_mutex_lock_interruptible(dev);
7282 if (ret)
7283 goto cleanup;
7284
7285 /* Reference the objects for the scheduled work. */
7286 drm_gem_object_reference(&work->old_fb_obj->base);
7287 drm_gem_object_reference(&obj->base);
7288
7289 crtc->fb = fb;
7290
7291 work->pending_flip_obj = obj;
7292
7293 work->enable_stall_check = true;
7294
7295 /* Block clients from rendering to the new back buffer until
7296 * the flip occurs and the object is no longer visible.
7297 */
7298 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7299 atomic_inc(&intel_crtc->unpin_work_count);
7300
7301 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7302 if (ret)
7303 goto cleanup_pending;
7304
7305 intel_disable_fbc(dev);
7306 intel_mark_fb_busy(obj);
7307 mutex_unlock(&dev->struct_mutex);
7308
7309 trace_i915_flip_request(intel_crtc->plane, obj);
7310
7311 return 0;
7312
7313 cleanup_pending:
7314 atomic_dec(&intel_crtc->unpin_work_count);
7315 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7316 drm_gem_object_unreference(&work->old_fb_obj->base);
7317 drm_gem_object_unreference(&obj->base);
7318 mutex_unlock(&dev->struct_mutex);
7319
7320 cleanup:
7321 spin_lock_irqsave(&dev->event_lock, flags);
7322 intel_crtc->unpin_work = NULL;
7323 spin_unlock_irqrestore(&dev->event_lock, flags);
7324
7325 drm_vblank_put(dev, intel_crtc->pipe);
7326 free_work:
7327 kfree(work);
7328
7329 return ret;
7330 }
7331
7332 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7333 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7334 .load_lut = intel_crtc_load_lut,
7335 .disable = intel_crtc_noop,
7336 };
7337
7338 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7339 {
7340 struct intel_encoder *other_encoder;
7341 struct drm_crtc *crtc = &encoder->new_crtc->base;
7342
7343 if (WARN_ON(!crtc))
7344 return false;
7345
7346 list_for_each_entry(other_encoder,
7347 &crtc->dev->mode_config.encoder_list,
7348 base.head) {
7349
7350 if (&other_encoder->new_crtc->base != crtc ||
7351 encoder == other_encoder)
7352 continue;
7353 else
7354 return true;
7355 }
7356
7357 return false;
7358 }
7359
7360 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7361 struct drm_crtc *crtc)
7362 {
7363 struct drm_device *dev;
7364 struct drm_crtc *tmp;
7365 int crtc_mask = 1;
7366
7367 WARN(!crtc, "checking null crtc?\n");
7368
7369 dev = crtc->dev;
7370
7371 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7372 if (tmp == crtc)
7373 break;
7374 crtc_mask <<= 1;
7375 }
7376
7377 if (encoder->possible_crtcs & crtc_mask)
7378 return true;
7379 return false;
7380 }
7381
7382 /**
7383 * intel_modeset_update_staged_output_state
7384 *
7385 * Updates the staged output configuration state, e.g. after we've read out the
7386 * current hw state.
7387 */
7388 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7389 {
7390 struct intel_encoder *encoder;
7391 struct intel_connector *connector;
7392
7393 list_for_each_entry(connector, &dev->mode_config.connector_list,
7394 base.head) {
7395 connector->new_encoder =
7396 to_intel_encoder(connector->base.encoder);
7397 }
7398
7399 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7400 base.head) {
7401 encoder->new_crtc =
7402 to_intel_crtc(encoder->base.crtc);
7403 }
7404 }
7405
7406 /**
7407 * intel_modeset_commit_output_state
7408 *
7409 * This function copies the stage display pipe configuration to the real one.
7410 */
7411 static void intel_modeset_commit_output_state(struct drm_device *dev)
7412 {
7413 struct intel_encoder *encoder;
7414 struct intel_connector *connector;
7415
7416 list_for_each_entry(connector, &dev->mode_config.connector_list,
7417 base.head) {
7418 connector->base.encoder = &connector->new_encoder->base;
7419 }
7420
7421 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7422 base.head) {
7423 encoder->base.crtc = &encoder->new_crtc->base;
7424 }
7425 }
7426
7427 static struct drm_display_mode *
7428 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7429 struct drm_display_mode *mode)
7430 {
7431 struct drm_device *dev = crtc->dev;
7432 struct drm_display_mode *adjusted_mode;
7433 struct drm_encoder_helper_funcs *encoder_funcs;
7434 struct intel_encoder *encoder;
7435
7436 adjusted_mode = drm_mode_duplicate(dev, mode);
7437 if (!adjusted_mode)
7438 return ERR_PTR(-ENOMEM);
7439
7440 /* Pass our mode to the connectors and the CRTC to give them a chance to
7441 * adjust it according to limitations or connector properties, and also
7442 * a chance to reject the mode entirely.
7443 */
7444 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7445 base.head) {
7446
7447 if (&encoder->new_crtc->base != crtc)
7448 continue;
7449 encoder_funcs = encoder->base.helper_private;
7450 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7451 adjusted_mode))) {
7452 DRM_DEBUG_KMS("Encoder fixup failed\n");
7453 goto fail;
7454 }
7455 }
7456
7457 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7458 DRM_DEBUG_KMS("CRTC fixup failed\n");
7459 goto fail;
7460 }
7461 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7462
7463 return adjusted_mode;
7464 fail:
7465 drm_mode_destroy(dev, adjusted_mode);
7466 return ERR_PTR(-EINVAL);
7467 }
7468
7469 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7470 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7471 static void
7472 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7473 unsigned *prepare_pipes, unsigned *disable_pipes)
7474 {
7475 struct intel_crtc *intel_crtc;
7476 struct drm_device *dev = crtc->dev;
7477 struct intel_encoder *encoder;
7478 struct intel_connector *connector;
7479 struct drm_crtc *tmp_crtc;
7480
7481 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7482
7483 /* Check which crtcs have changed outputs connected to them, these need
7484 * to be part of the prepare_pipes mask. We don't (yet) support global
7485 * modeset across multiple crtcs, so modeset_pipes will only have one
7486 * bit set at most. */
7487 list_for_each_entry(connector, &dev->mode_config.connector_list,
7488 base.head) {
7489 if (connector->base.encoder == &connector->new_encoder->base)
7490 continue;
7491
7492 if (connector->base.encoder) {
7493 tmp_crtc = connector->base.encoder->crtc;
7494
7495 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7496 }
7497
7498 if (connector->new_encoder)
7499 *prepare_pipes |=
7500 1 << connector->new_encoder->new_crtc->pipe;
7501 }
7502
7503 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7504 base.head) {
7505 if (encoder->base.crtc == &encoder->new_crtc->base)
7506 continue;
7507
7508 if (encoder->base.crtc) {
7509 tmp_crtc = encoder->base.crtc;
7510
7511 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7512 }
7513
7514 if (encoder->new_crtc)
7515 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7516 }
7517
7518 /* Check for any pipes that will be fully disabled ... */
7519 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7520 base.head) {
7521 bool used = false;
7522
7523 /* Don't try to disable disabled crtcs. */
7524 if (!intel_crtc->base.enabled)
7525 continue;
7526
7527 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7528 base.head) {
7529 if (encoder->new_crtc == intel_crtc)
7530 used = true;
7531 }
7532
7533 if (!used)
7534 *disable_pipes |= 1 << intel_crtc->pipe;
7535 }
7536
7537
7538 /* set_mode is also used to update properties on life display pipes. */
7539 intel_crtc = to_intel_crtc(crtc);
7540 if (crtc->enabled)
7541 *prepare_pipes |= 1 << intel_crtc->pipe;
7542
7543 /* We only support modeset on one single crtc, hence we need to do that
7544 * only for the passed in crtc iff we change anything else than just
7545 * disable crtcs.
7546 *
7547 * This is actually not true, to be fully compatible with the old crtc
7548 * helper we automatically disable _any_ output (i.e. doesn't need to be
7549 * connected to the crtc we're modesetting on) if it's disconnected.
7550 * Which is a rather nutty api (since changed the output configuration
7551 * without userspace's explicit request can lead to confusion), but
7552 * alas. Hence we currently need to modeset on all pipes we prepare. */
7553 if (*prepare_pipes)
7554 *modeset_pipes = *prepare_pipes;
7555
7556 /* ... and mask these out. */
7557 *modeset_pipes &= ~(*disable_pipes);
7558 *prepare_pipes &= ~(*disable_pipes);
7559 }
7560
7561 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7562 {
7563 struct drm_encoder *encoder;
7564 struct drm_device *dev = crtc->dev;
7565
7566 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7567 if (encoder->crtc == crtc)
7568 return true;
7569
7570 return false;
7571 }
7572
7573 static void
7574 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7575 {
7576 struct intel_encoder *intel_encoder;
7577 struct intel_crtc *intel_crtc;
7578 struct drm_connector *connector;
7579
7580 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7581 base.head) {
7582 if (!intel_encoder->base.crtc)
7583 continue;
7584
7585 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7586
7587 if (prepare_pipes & (1 << intel_crtc->pipe))
7588 intel_encoder->connectors_active = false;
7589 }
7590
7591 intel_modeset_commit_output_state(dev);
7592
7593 /* Update computed state. */
7594 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7595 base.head) {
7596 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7597 }
7598
7599 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7600 if (!connector->encoder || !connector->encoder->crtc)
7601 continue;
7602
7603 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7604
7605 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7606 struct drm_property *dpms_property =
7607 dev->mode_config.dpms_property;
7608
7609 connector->dpms = DRM_MODE_DPMS_ON;
7610 drm_connector_property_set_value(connector,
7611 dpms_property,
7612 DRM_MODE_DPMS_ON);
7613
7614 intel_encoder = to_intel_encoder(connector->encoder);
7615 intel_encoder->connectors_active = true;
7616 }
7617 }
7618
7619 }
7620
7621 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7622 list_for_each_entry((intel_crtc), \
7623 &(dev)->mode_config.crtc_list, \
7624 base.head) \
7625 if (mask & (1 <<(intel_crtc)->pipe)) \
7626
7627 void
7628 intel_modeset_check_state(struct drm_device *dev)
7629 {
7630 struct intel_crtc *crtc;
7631 struct intel_encoder *encoder;
7632 struct intel_connector *connector;
7633
7634 list_for_each_entry(connector, &dev->mode_config.connector_list,
7635 base.head) {
7636 /* This also checks the encoder/connector hw state with the
7637 * ->get_hw_state callbacks. */
7638 intel_connector_check_state(connector);
7639
7640 WARN(&connector->new_encoder->base != connector->base.encoder,
7641 "connector's staged encoder doesn't match current encoder\n");
7642 }
7643
7644 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7645 base.head) {
7646 bool enabled = false;
7647 bool active = false;
7648 enum pipe pipe, tracked_pipe;
7649
7650 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7651 encoder->base.base.id,
7652 drm_get_encoder_name(&encoder->base));
7653
7654 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7655 "encoder's stage crtc doesn't match current crtc\n");
7656 WARN(encoder->connectors_active && !encoder->base.crtc,
7657 "encoder's active_connectors set, but no crtc\n");
7658
7659 list_for_each_entry(connector, &dev->mode_config.connector_list,
7660 base.head) {
7661 if (connector->base.encoder != &encoder->base)
7662 continue;
7663 enabled = true;
7664 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7665 active = true;
7666 }
7667 WARN(!!encoder->base.crtc != enabled,
7668 "encoder's enabled state mismatch "
7669 "(expected %i, found %i)\n",
7670 !!encoder->base.crtc, enabled);
7671 WARN(active && !encoder->base.crtc,
7672 "active encoder with no crtc\n");
7673
7674 WARN(encoder->connectors_active != active,
7675 "encoder's computed active state doesn't match tracked active state "
7676 "(expected %i, found %i)\n", active, encoder->connectors_active);
7677
7678 active = encoder->get_hw_state(encoder, &pipe);
7679 WARN(active != encoder->connectors_active,
7680 "encoder's hw state doesn't match sw tracking "
7681 "(expected %i, found %i)\n",
7682 encoder->connectors_active, active);
7683
7684 if (!encoder->base.crtc)
7685 continue;
7686
7687 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7688 WARN(active && pipe != tracked_pipe,
7689 "active encoder's pipe doesn't match"
7690 "(expected %i, found %i)\n",
7691 tracked_pipe, pipe);
7692
7693 }
7694
7695 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7696 base.head) {
7697 bool enabled = false;
7698 bool active = false;
7699
7700 DRM_DEBUG_KMS("[CRTC:%d]\n",
7701 crtc->base.base.id);
7702
7703 WARN(crtc->active && !crtc->base.enabled,
7704 "active crtc, but not enabled in sw tracking\n");
7705
7706 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7707 base.head) {
7708 if (encoder->base.crtc != &crtc->base)
7709 continue;
7710 enabled = true;
7711 if (encoder->connectors_active)
7712 active = true;
7713 }
7714 WARN(active != crtc->active,
7715 "crtc's computed active state doesn't match tracked active state "
7716 "(expected %i, found %i)\n", active, crtc->active);
7717 WARN(enabled != crtc->base.enabled,
7718 "crtc's computed enabled state doesn't match tracked enabled state "
7719 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7720
7721 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7722 }
7723 }
7724
7725 bool intel_set_mode(struct drm_crtc *crtc,
7726 struct drm_display_mode *mode,
7727 int x, int y, struct drm_framebuffer *fb)
7728 {
7729 struct drm_device *dev = crtc->dev;
7730 drm_i915_private_t *dev_priv = dev->dev_private;
7731 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7732 struct intel_crtc *intel_crtc;
7733 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7734 bool ret = true;
7735
7736 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7737 &prepare_pipes, &disable_pipes);
7738
7739 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7740 modeset_pipes, prepare_pipes, disable_pipes);
7741
7742 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7743 intel_crtc_disable(&intel_crtc->base);
7744
7745 saved_hwmode = crtc->hwmode;
7746 saved_mode = crtc->mode;
7747
7748 /* Hack: Because we don't (yet) support global modeset on multiple
7749 * crtcs, we don't keep track of the new mode for more than one crtc.
7750 * Hence simply check whether any bit is set in modeset_pipes in all the
7751 * pieces of code that are not yet converted to deal with mutliple crtcs
7752 * changing their mode at the same time. */
7753 adjusted_mode = NULL;
7754 if (modeset_pipes) {
7755 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7756 if (IS_ERR(adjusted_mode)) {
7757 return false;
7758 }
7759 }
7760
7761 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7762 if (intel_crtc->base.enabled)
7763 dev_priv->display.crtc_disable(&intel_crtc->base);
7764 }
7765
7766 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7767 * to set it here already despite that we pass it down the callchain.
7768 */
7769 if (modeset_pipes)
7770 crtc->mode = *mode;
7771
7772 /* Only after disabling all output pipelines that will be changed can we
7773 * update the the output configuration. */
7774 intel_modeset_update_state(dev, prepare_pipes);
7775
7776 if (dev_priv->display.modeset_global_resources)
7777 dev_priv->display.modeset_global_resources(dev);
7778
7779 /* Set up the DPLL and any encoders state that needs to adjust or depend
7780 * on the DPLL.
7781 */
7782 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7783 ret = !intel_crtc_mode_set(&intel_crtc->base,
7784 mode, adjusted_mode,
7785 x, y, fb);
7786 if (!ret)
7787 goto done;
7788 }
7789
7790 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7791 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7792 dev_priv->display.crtc_enable(&intel_crtc->base);
7793
7794 if (modeset_pipes) {
7795 /* Store real post-adjustment hardware mode. */
7796 crtc->hwmode = *adjusted_mode;
7797
7798 /* Calculate and store various constants which
7799 * are later needed by vblank and swap-completion
7800 * timestamping. They are derived from true hwmode.
7801 */
7802 drm_calc_timestamping_constants(crtc);
7803 }
7804
7805 /* FIXME: add subpixel order */
7806 done:
7807 drm_mode_destroy(dev, adjusted_mode);
7808 if (!ret && crtc->enabled) {
7809 crtc->hwmode = saved_hwmode;
7810 crtc->mode = saved_mode;
7811 } else {
7812 intel_modeset_check_state(dev);
7813 }
7814
7815 return ret;
7816 }
7817
7818 #undef for_each_intel_crtc_masked
7819
7820 static void intel_set_config_free(struct intel_set_config *config)
7821 {
7822 if (!config)
7823 return;
7824
7825 kfree(config->save_connector_encoders);
7826 kfree(config->save_encoder_crtcs);
7827 kfree(config);
7828 }
7829
7830 static int intel_set_config_save_state(struct drm_device *dev,
7831 struct intel_set_config *config)
7832 {
7833 struct drm_encoder *encoder;
7834 struct drm_connector *connector;
7835 int count;
7836
7837 config->save_encoder_crtcs =
7838 kcalloc(dev->mode_config.num_encoder,
7839 sizeof(struct drm_crtc *), GFP_KERNEL);
7840 if (!config->save_encoder_crtcs)
7841 return -ENOMEM;
7842
7843 config->save_connector_encoders =
7844 kcalloc(dev->mode_config.num_connector,
7845 sizeof(struct drm_encoder *), GFP_KERNEL);
7846 if (!config->save_connector_encoders)
7847 return -ENOMEM;
7848
7849 /* Copy data. Note that driver private data is not affected.
7850 * Should anything bad happen only the expected state is
7851 * restored, not the drivers personal bookkeeping.
7852 */
7853 count = 0;
7854 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7855 config->save_encoder_crtcs[count++] = encoder->crtc;
7856 }
7857
7858 count = 0;
7859 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7860 config->save_connector_encoders[count++] = connector->encoder;
7861 }
7862
7863 return 0;
7864 }
7865
7866 static void intel_set_config_restore_state(struct drm_device *dev,
7867 struct intel_set_config *config)
7868 {
7869 struct intel_encoder *encoder;
7870 struct intel_connector *connector;
7871 int count;
7872
7873 count = 0;
7874 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7875 encoder->new_crtc =
7876 to_intel_crtc(config->save_encoder_crtcs[count++]);
7877 }
7878
7879 count = 0;
7880 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7881 connector->new_encoder =
7882 to_intel_encoder(config->save_connector_encoders[count++]);
7883 }
7884 }
7885
7886 static void
7887 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7888 struct intel_set_config *config)
7889 {
7890
7891 /* We should be able to check here if the fb has the same properties
7892 * and then just flip_or_move it */
7893 if (set->crtc->fb != set->fb) {
7894 /* If we have no fb then treat it as a full mode set */
7895 if (set->crtc->fb == NULL) {
7896 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7897 config->mode_changed = true;
7898 } else if (set->fb == NULL) {
7899 config->mode_changed = true;
7900 } else if (set->fb->depth != set->crtc->fb->depth) {
7901 config->mode_changed = true;
7902 } else if (set->fb->bits_per_pixel !=
7903 set->crtc->fb->bits_per_pixel) {
7904 config->mode_changed = true;
7905 } else
7906 config->fb_changed = true;
7907 }
7908
7909 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7910 config->fb_changed = true;
7911
7912 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7913 DRM_DEBUG_KMS("modes are different, full mode set\n");
7914 drm_mode_debug_printmodeline(&set->crtc->mode);
7915 drm_mode_debug_printmodeline(set->mode);
7916 config->mode_changed = true;
7917 }
7918 }
7919
7920 static int
7921 intel_modeset_stage_output_state(struct drm_device *dev,
7922 struct drm_mode_set *set,
7923 struct intel_set_config *config)
7924 {
7925 struct drm_crtc *new_crtc;
7926 struct intel_connector *connector;
7927 struct intel_encoder *encoder;
7928 int count, ro;
7929
7930 /* The upper layers ensure that we either disabl a crtc or have a list
7931 * of connectors. For paranoia, double-check this. */
7932 WARN_ON(!set->fb && (set->num_connectors != 0));
7933 WARN_ON(set->fb && (set->num_connectors == 0));
7934
7935 count = 0;
7936 list_for_each_entry(connector, &dev->mode_config.connector_list,
7937 base.head) {
7938 /* Otherwise traverse passed in connector list and get encoders
7939 * for them. */
7940 for (ro = 0; ro < set->num_connectors; ro++) {
7941 if (set->connectors[ro] == &connector->base) {
7942 connector->new_encoder = connector->encoder;
7943 break;
7944 }
7945 }
7946
7947 /* If we disable the crtc, disable all its connectors. Also, if
7948 * the connector is on the changing crtc but not on the new
7949 * connector list, disable it. */
7950 if ((!set->fb || ro == set->num_connectors) &&
7951 connector->base.encoder &&
7952 connector->base.encoder->crtc == set->crtc) {
7953 connector->new_encoder = NULL;
7954
7955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7956 connector->base.base.id,
7957 drm_get_connector_name(&connector->base));
7958 }
7959
7960
7961 if (&connector->new_encoder->base != connector->base.encoder) {
7962 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7963 config->mode_changed = true;
7964 }
7965
7966 /* Disable all disconnected encoders. */
7967 if (connector->base.status == connector_status_disconnected)
7968 connector->new_encoder = NULL;
7969 }
7970 /* connector->new_encoder is now updated for all connectors. */
7971
7972 /* Update crtc of enabled connectors. */
7973 count = 0;
7974 list_for_each_entry(connector, &dev->mode_config.connector_list,
7975 base.head) {
7976 if (!connector->new_encoder)
7977 continue;
7978
7979 new_crtc = connector->new_encoder->base.crtc;
7980
7981 for (ro = 0; ro < set->num_connectors; ro++) {
7982 if (set->connectors[ro] == &connector->base)
7983 new_crtc = set->crtc;
7984 }
7985
7986 /* Make sure the new CRTC will work with the encoder */
7987 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7988 new_crtc)) {
7989 return -EINVAL;
7990 }
7991 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7992
7993 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7994 connector->base.base.id,
7995 drm_get_connector_name(&connector->base),
7996 new_crtc->base.id);
7997 }
7998
7999 /* Check for any encoders that needs to be disabled. */
8000 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8001 base.head) {
8002 list_for_each_entry(connector,
8003 &dev->mode_config.connector_list,
8004 base.head) {
8005 if (connector->new_encoder == encoder) {
8006 WARN_ON(!connector->new_encoder->new_crtc);
8007
8008 goto next_encoder;
8009 }
8010 }
8011 encoder->new_crtc = NULL;
8012 next_encoder:
8013 /* Only now check for crtc changes so we don't miss encoders
8014 * that will be disabled. */
8015 if (&encoder->new_crtc->base != encoder->base.crtc) {
8016 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8017 config->mode_changed = true;
8018 }
8019 }
8020 /* Now we've also updated encoder->new_crtc for all encoders. */
8021
8022 return 0;
8023 }
8024
8025 static int intel_crtc_set_config(struct drm_mode_set *set)
8026 {
8027 struct drm_device *dev;
8028 struct drm_mode_set save_set;
8029 struct intel_set_config *config;
8030 int ret;
8031
8032 BUG_ON(!set);
8033 BUG_ON(!set->crtc);
8034 BUG_ON(!set->crtc->helper_private);
8035
8036 if (!set->mode)
8037 set->fb = NULL;
8038
8039 /* The fb helper likes to play gross jokes with ->mode_set_config.
8040 * Unfortunately the crtc helper doesn't do much at all for this case,
8041 * so we have to cope with this madness until the fb helper is fixed up. */
8042 if (set->fb && set->num_connectors == 0)
8043 return 0;
8044
8045 if (set->fb) {
8046 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8047 set->crtc->base.id, set->fb->base.id,
8048 (int)set->num_connectors, set->x, set->y);
8049 } else {
8050 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8051 }
8052
8053 dev = set->crtc->dev;
8054
8055 ret = -ENOMEM;
8056 config = kzalloc(sizeof(*config), GFP_KERNEL);
8057 if (!config)
8058 goto out_config;
8059
8060 ret = intel_set_config_save_state(dev, config);
8061 if (ret)
8062 goto out_config;
8063
8064 save_set.crtc = set->crtc;
8065 save_set.mode = &set->crtc->mode;
8066 save_set.x = set->crtc->x;
8067 save_set.y = set->crtc->y;
8068 save_set.fb = set->crtc->fb;
8069
8070 /* Compute whether we need a full modeset, only an fb base update or no
8071 * change at all. In the future we might also check whether only the
8072 * mode changed, e.g. for LVDS where we only change the panel fitter in
8073 * such cases. */
8074 intel_set_config_compute_mode_changes(set, config);
8075
8076 ret = intel_modeset_stage_output_state(dev, set, config);
8077 if (ret)
8078 goto fail;
8079
8080 if (config->mode_changed) {
8081 if (set->mode) {
8082 DRM_DEBUG_KMS("attempting to set mode from"
8083 " userspace\n");
8084 drm_mode_debug_printmodeline(set->mode);
8085 }
8086
8087 if (!intel_set_mode(set->crtc, set->mode,
8088 set->x, set->y, set->fb)) {
8089 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8090 set->crtc->base.id);
8091 ret = -EINVAL;
8092 goto fail;
8093 }
8094 } else if (config->fb_changed) {
8095 ret = intel_pipe_set_base(set->crtc,
8096 set->x, set->y, set->fb);
8097 }
8098
8099 intel_set_config_free(config);
8100
8101 return 0;
8102
8103 fail:
8104 intel_set_config_restore_state(dev, config);
8105
8106 /* Try to restore the config */
8107 if (config->mode_changed &&
8108 !intel_set_mode(save_set.crtc, save_set.mode,
8109 save_set.x, save_set.y, save_set.fb))
8110 DRM_ERROR("failed to restore config after modeset failure\n");
8111
8112 out_config:
8113 intel_set_config_free(config);
8114 return ret;
8115 }
8116
8117 static const struct drm_crtc_funcs intel_crtc_funcs = {
8118 .cursor_set = intel_crtc_cursor_set,
8119 .cursor_move = intel_crtc_cursor_move,
8120 .gamma_set = intel_crtc_gamma_set,
8121 .set_config = intel_crtc_set_config,
8122 .destroy = intel_crtc_destroy,
8123 .page_flip = intel_crtc_page_flip,
8124 };
8125
8126 static void intel_cpu_pll_init(struct drm_device *dev)
8127 {
8128 if (IS_HASWELL(dev))
8129 intel_ddi_pll_init(dev);
8130 }
8131
8132 static void intel_pch_pll_init(struct drm_device *dev)
8133 {
8134 drm_i915_private_t *dev_priv = dev->dev_private;
8135 int i;
8136
8137 if (dev_priv->num_pch_pll == 0) {
8138 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8139 return;
8140 }
8141
8142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8143 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8144 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8145 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8146 }
8147 }
8148
8149 static void intel_crtc_init(struct drm_device *dev, int pipe)
8150 {
8151 drm_i915_private_t *dev_priv = dev->dev_private;
8152 struct intel_crtc *intel_crtc;
8153 int i;
8154
8155 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8156 if (intel_crtc == NULL)
8157 return;
8158
8159 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8160
8161 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8162 for (i = 0; i < 256; i++) {
8163 intel_crtc->lut_r[i] = i;
8164 intel_crtc->lut_g[i] = i;
8165 intel_crtc->lut_b[i] = i;
8166 }
8167
8168 /* Swap pipes & planes for FBC on pre-965 */
8169 intel_crtc->pipe = pipe;
8170 intel_crtc->plane = pipe;
8171 intel_crtc->cpu_transcoder = pipe;
8172 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8173 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8174 intel_crtc->plane = !pipe;
8175 }
8176
8177 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8178 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8179 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8180 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8181
8182 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8183
8184 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8185 }
8186
8187 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8188 struct drm_file *file)
8189 {
8190 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8191 struct drm_mode_object *drmmode_obj;
8192 struct intel_crtc *crtc;
8193
8194 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8195 return -ENODEV;
8196
8197 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8198 DRM_MODE_OBJECT_CRTC);
8199
8200 if (!drmmode_obj) {
8201 DRM_ERROR("no such CRTC id\n");
8202 return -EINVAL;
8203 }
8204
8205 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8206 pipe_from_crtc_id->pipe = crtc->pipe;
8207
8208 return 0;
8209 }
8210
8211 static int intel_encoder_clones(struct intel_encoder *encoder)
8212 {
8213 struct drm_device *dev = encoder->base.dev;
8214 struct intel_encoder *source_encoder;
8215 int index_mask = 0;
8216 int entry = 0;
8217
8218 list_for_each_entry(source_encoder,
8219 &dev->mode_config.encoder_list, base.head) {
8220
8221 if (encoder == source_encoder)
8222 index_mask |= (1 << entry);
8223
8224 /* Intel hw has only one MUX where enocoders could be cloned. */
8225 if (encoder->cloneable && source_encoder->cloneable)
8226 index_mask |= (1 << entry);
8227
8228 entry++;
8229 }
8230
8231 return index_mask;
8232 }
8233
8234 static bool has_edp_a(struct drm_device *dev)
8235 {
8236 struct drm_i915_private *dev_priv = dev->dev_private;
8237
8238 if (!IS_MOBILE(dev))
8239 return false;
8240
8241 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8242 return false;
8243
8244 if (IS_GEN5(dev) &&
8245 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8246 return false;
8247
8248 return true;
8249 }
8250
8251 static void intel_setup_outputs(struct drm_device *dev)
8252 {
8253 struct drm_i915_private *dev_priv = dev->dev_private;
8254 struct intel_encoder *encoder;
8255 bool dpd_is_edp = false;
8256 bool has_lvds;
8257
8258 has_lvds = intel_lvds_init(dev);
8259 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8260 /* disable the panel fitter on everything but LVDS */
8261 I915_WRITE(PFIT_CONTROL, 0);
8262 }
8263
8264 intel_crt_init(dev);
8265
8266 if (IS_HASWELL(dev)) {
8267 int found;
8268
8269 /* Haswell uses DDI functions to detect digital outputs */
8270 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8271 /* DDI A only supports eDP */
8272 if (found)
8273 intel_ddi_init(dev, PORT_A);
8274
8275 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8276 * register */
8277 found = I915_READ(SFUSE_STRAP);
8278
8279 if (found & SFUSE_STRAP_DDIB_DETECTED)
8280 intel_ddi_init(dev, PORT_B);
8281 if (found & SFUSE_STRAP_DDIC_DETECTED)
8282 intel_ddi_init(dev, PORT_C);
8283 if (found & SFUSE_STRAP_DDID_DETECTED)
8284 intel_ddi_init(dev, PORT_D);
8285 } else if (HAS_PCH_SPLIT(dev)) {
8286 int found;
8287 dpd_is_edp = intel_dpd_is_edp(dev);
8288
8289 if (has_edp_a(dev))
8290 intel_dp_init(dev, DP_A, PORT_A);
8291
8292 if (I915_READ(HDMIB) & PORT_DETECTED) {
8293 /* PCH SDVOB multiplex with HDMIB */
8294 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8295 if (!found)
8296 intel_hdmi_init(dev, HDMIB, PORT_B);
8297 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8298 intel_dp_init(dev, PCH_DP_B, PORT_B);
8299 }
8300
8301 if (I915_READ(HDMIC) & PORT_DETECTED)
8302 intel_hdmi_init(dev, HDMIC, PORT_C);
8303
8304 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8305 intel_hdmi_init(dev, HDMID, PORT_D);
8306
8307 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8308 intel_dp_init(dev, PCH_DP_C, PORT_C);
8309
8310 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8311 intel_dp_init(dev, PCH_DP_D, PORT_D);
8312 } else if (IS_VALLEYVIEW(dev)) {
8313 int found;
8314
8315 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8316 if (I915_READ(DP_C) & DP_DETECTED)
8317 intel_dp_init(dev, DP_C, PORT_C);
8318
8319 if (I915_READ(SDVOB) & PORT_DETECTED) {
8320 /* SDVOB multiplex with HDMIB */
8321 found = intel_sdvo_init(dev, SDVOB, true);
8322 if (!found)
8323 intel_hdmi_init(dev, SDVOB, PORT_B);
8324 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8325 intel_dp_init(dev, DP_B, PORT_B);
8326 }
8327
8328 if (I915_READ(SDVOC) & PORT_DETECTED)
8329 intel_hdmi_init(dev, SDVOC, PORT_C);
8330
8331 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8332 bool found = false;
8333
8334 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8335 DRM_DEBUG_KMS("probing SDVOB\n");
8336 found = intel_sdvo_init(dev, SDVOB, true);
8337 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8338 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8339 intel_hdmi_init(dev, SDVOB, PORT_B);
8340 }
8341
8342 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8343 DRM_DEBUG_KMS("probing DP_B\n");
8344 intel_dp_init(dev, DP_B, PORT_B);
8345 }
8346 }
8347
8348 /* Before G4X SDVOC doesn't have its own detect register */
8349
8350 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8351 DRM_DEBUG_KMS("probing SDVOC\n");
8352 found = intel_sdvo_init(dev, SDVOC, false);
8353 }
8354
8355 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8356
8357 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8358 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8359 intel_hdmi_init(dev, SDVOC, PORT_C);
8360 }
8361 if (SUPPORTS_INTEGRATED_DP(dev)) {
8362 DRM_DEBUG_KMS("probing DP_C\n");
8363 intel_dp_init(dev, DP_C, PORT_C);
8364 }
8365 }
8366
8367 if (SUPPORTS_INTEGRATED_DP(dev) &&
8368 (I915_READ(DP_D) & DP_DETECTED)) {
8369 DRM_DEBUG_KMS("probing DP_D\n");
8370 intel_dp_init(dev, DP_D, PORT_D);
8371 }
8372 } else if (IS_GEN2(dev))
8373 intel_dvo_init(dev);
8374
8375 if (SUPPORTS_TV(dev))
8376 intel_tv_init(dev);
8377
8378 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8379 encoder->base.possible_crtcs = encoder->crtc_mask;
8380 encoder->base.possible_clones =
8381 intel_encoder_clones(encoder);
8382 }
8383
8384 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8385 ironlake_init_pch_refclk(dev);
8386
8387 drm_helper_move_panel_connectors_to_head(dev);
8388 }
8389
8390 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8391 {
8392 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8393
8394 drm_framebuffer_cleanup(fb);
8395 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8396
8397 kfree(intel_fb);
8398 }
8399
8400 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8401 struct drm_file *file,
8402 unsigned int *handle)
8403 {
8404 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8405 struct drm_i915_gem_object *obj = intel_fb->obj;
8406
8407 return drm_gem_handle_create(file, &obj->base, handle);
8408 }
8409
8410 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8411 .destroy = intel_user_framebuffer_destroy,
8412 .create_handle = intel_user_framebuffer_create_handle,
8413 };
8414
8415 int intel_framebuffer_init(struct drm_device *dev,
8416 struct intel_framebuffer *intel_fb,
8417 struct drm_mode_fb_cmd2 *mode_cmd,
8418 struct drm_i915_gem_object *obj)
8419 {
8420 int ret;
8421
8422 if (obj->tiling_mode == I915_TILING_Y)
8423 return -EINVAL;
8424
8425 if (mode_cmd->pitches[0] & 63)
8426 return -EINVAL;
8427
8428 /* FIXME <= Gen4 stride limits are bit unclear */
8429 if (mode_cmd->pitches[0] > 32768)
8430 return -EINVAL;
8431
8432 if (obj->tiling_mode != I915_TILING_NONE &&
8433 mode_cmd->pitches[0] != obj->stride)
8434 return -EINVAL;
8435
8436 /* Reject formats not supported by any plane early. */
8437 switch (mode_cmd->pixel_format) {
8438 case DRM_FORMAT_C8:
8439 case DRM_FORMAT_RGB565:
8440 case DRM_FORMAT_XRGB8888:
8441 case DRM_FORMAT_ARGB8888:
8442 break;
8443 case DRM_FORMAT_XRGB1555:
8444 case DRM_FORMAT_ARGB1555:
8445 if (INTEL_INFO(dev)->gen > 3)
8446 return -EINVAL;
8447 break;
8448 case DRM_FORMAT_XBGR8888:
8449 case DRM_FORMAT_ABGR8888:
8450 case DRM_FORMAT_XRGB2101010:
8451 case DRM_FORMAT_ARGB2101010:
8452 case DRM_FORMAT_XBGR2101010:
8453 case DRM_FORMAT_ABGR2101010:
8454 if (INTEL_INFO(dev)->gen < 4)
8455 return -EINVAL;
8456 break;
8457 case DRM_FORMAT_YUYV:
8458 case DRM_FORMAT_UYVY:
8459 case DRM_FORMAT_YVYU:
8460 case DRM_FORMAT_VYUY:
8461 if (INTEL_INFO(dev)->gen < 6)
8462 return -EINVAL;
8463 break;
8464 default:
8465 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8466 return -EINVAL;
8467 }
8468
8469 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8470 if (mode_cmd->offsets[0] != 0)
8471 return -EINVAL;
8472
8473 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8474 if (ret) {
8475 DRM_ERROR("framebuffer init failed %d\n", ret);
8476 return ret;
8477 }
8478
8479 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8480 intel_fb->obj = obj;
8481 return 0;
8482 }
8483
8484 static struct drm_framebuffer *
8485 intel_user_framebuffer_create(struct drm_device *dev,
8486 struct drm_file *filp,
8487 struct drm_mode_fb_cmd2 *mode_cmd)
8488 {
8489 struct drm_i915_gem_object *obj;
8490
8491 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8492 mode_cmd->handles[0]));
8493 if (&obj->base == NULL)
8494 return ERR_PTR(-ENOENT);
8495
8496 return intel_framebuffer_create(dev, mode_cmd, obj);
8497 }
8498
8499 static const struct drm_mode_config_funcs intel_mode_funcs = {
8500 .fb_create = intel_user_framebuffer_create,
8501 .output_poll_changed = intel_fb_output_poll_changed,
8502 };
8503
8504 /* Set up chip specific display functions */
8505 static void intel_init_display(struct drm_device *dev)
8506 {
8507 struct drm_i915_private *dev_priv = dev->dev_private;
8508
8509 /* We always want a DPMS function */
8510 if (IS_HASWELL(dev)) {
8511 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8512 dev_priv->display.crtc_enable = haswell_crtc_enable;
8513 dev_priv->display.crtc_disable = haswell_crtc_disable;
8514 dev_priv->display.off = haswell_crtc_off;
8515 dev_priv->display.update_plane = ironlake_update_plane;
8516 } else if (HAS_PCH_SPLIT(dev)) {
8517 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8518 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8519 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8520 dev_priv->display.off = ironlake_crtc_off;
8521 dev_priv->display.update_plane = ironlake_update_plane;
8522 } else {
8523 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8524 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8525 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8526 dev_priv->display.off = i9xx_crtc_off;
8527 dev_priv->display.update_plane = i9xx_update_plane;
8528 }
8529
8530 /* Returns the core display clock speed */
8531 if (IS_VALLEYVIEW(dev))
8532 dev_priv->display.get_display_clock_speed =
8533 valleyview_get_display_clock_speed;
8534 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8535 dev_priv->display.get_display_clock_speed =
8536 i945_get_display_clock_speed;
8537 else if (IS_I915G(dev))
8538 dev_priv->display.get_display_clock_speed =
8539 i915_get_display_clock_speed;
8540 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8541 dev_priv->display.get_display_clock_speed =
8542 i9xx_misc_get_display_clock_speed;
8543 else if (IS_I915GM(dev))
8544 dev_priv->display.get_display_clock_speed =
8545 i915gm_get_display_clock_speed;
8546 else if (IS_I865G(dev))
8547 dev_priv->display.get_display_clock_speed =
8548 i865_get_display_clock_speed;
8549 else if (IS_I85X(dev))
8550 dev_priv->display.get_display_clock_speed =
8551 i855_get_display_clock_speed;
8552 else /* 852, 830 */
8553 dev_priv->display.get_display_clock_speed =
8554 i830_get_display_clock_speed;
8555
8556 if (HAS_PCH_SPLIT(dev)) {
8557 if (IS_GEN5(dev)) {
8558 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8559 dev_priv->display.write_eld = ironlake_write_eld;
8560 } else if (IS_GEN6(dev)) {
8561 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8562 dev_priv->display.write_eld = ironlake_write_eld;
8563 } else if (IS_IVYBRIDGE(dev)) {
8564 /* FIXME: detect B0+ stepping and use auto training */
8565 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8566 dev_priv->display.write_eld = ironlake_write_eld;
8567 dev_priv->display.modeset_global_resources =
8568 ivb_modeset_global_resources;
8569 } else if (IS_HASWELL(dev)) {
8570 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8571 dev_priv->display.write_eld = haswell_write_eld;
8572 } else
8573 dev_priv->display.update_wm = NULL;
8574 } else if (IS_G4X(dev)) {
8575 dev_priv->display.write_eld = g4x_write_eld;
8576 }
8577
8578 /* Default just returns -ENODEV to indicate unsupported */
8579 dev_priv->display.queue_flip = intel_default_queue_flip;
8580
8581 switch (INTEL_INFO(dev)->gen) {
8582 case 2:
8583 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8584 break;
8585
8586 case 3:
8587 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8588 break;
8589
8590 case 4:
8591 case 5:
8592 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8593 break;
8594
8595 case 6:
8596 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8597 break;
8598 case 7:
8599 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8600 break;
8601 }
8602 }
8603
8604 /*
8605 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8606 * resume, or other times. This quirk makes sure that's the case for
8607 * affected systems.
8608 */
8609 static void quirk_pipea_force(struct drm_device *dev)
8610 {
8611 struct drm_i915_private *dev_priv = dev->dev_private;
8612
8613 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8614 DRM_INFO("applying pipe a force quirk\n");
8615 }
8616
8617 /*
8618 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8619 */
8620 static void quirk_ssc_force_disable(struct drm_device *dev)
8621 {
8622 struct drm_i915_private *dev_priv = dev->dev_private;
8623 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8624 DRM_INFO("applying lvds SSC disable quirk\n");
8625 }
8626
8627 /*
8628 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8629 * brightness value
8630 */
8631 static void quirk_invert_brightness(struct drm_device *dev)
8632 {
8633 struct drm_i915_private *dev_priv = dev->dev_private;
8634 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8635 DRM_INFO("applying inverted panel brightness quirk\n");
8636 }
8637
8638 struct intel_quirk {
8639 int device;
8640 int subsystem_vendor;
8641 int subsystem_device;
8642 void (*hook)(struct drm_device *dev);
8643 };
8644
8645 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8646 struct intel_dmi_quirk {
8647 void (*hook)(struct drm_device *dev);
8648 const struct dmi_system_id (*dmi_id_list)[];
8649 };
8650
8651 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8652 {
8653 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8654 return 1;
8655 }
8656
8657 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8658 {
8659 .dmi_id_list = &(const struct dmi_system_id[]) {
8660 {
8661 .callback = intel_dmi_reverse_brightness,
8662 .ident = "NCR Corporation",
8663 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8664 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8665 },
8666 },
8667 { } /* terminating entry */
8668 },
8669 .hook = quirk_invert_brightness,
8670 },
8671 };
8672
8673 static struct intel_quirk intel_quirks[] = {
8674 /* HP Mini needs pipe A force quirk (LP: #322104) */
8675 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8676
8677 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8678 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8679
8680 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8681 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8682
8683 /* 830/845 need to leave pipe A & dpll A up */
8684 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8685 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8686
8687 /* Lenovo U160 cannot use SSC on LVDS */
8688 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8689
8690 /* Sony Vaio Y cannot use SSC on LVDS */
8691 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8692
8693 /* Acer Aspire 5734Z must invert backlight brightness */
8694 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8695 };
8696
8697 static void intel_init_quirks(struct drm_device *dev)
8698 {
8699 struct pci_dev *d = dev->pdev;
8700 int i;
8701
8702 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8703 struct intel_quirk *q = &intel_quirks[i];
8704
8705 if (d->device == q->device &&
8706 (d->subsystem_vendor == q->subsystem_vendor ||
8707 q->subsystem_vendor == PCI_ANY_ID) &&
8708 (d->subsystem_device == q->subsystem_device ||
8709 q->subsystem_device == PCI_ANY_ID))
8710 q->hook(dev);
8711 }
8712 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8713 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8714 intel_dmi_quirks[i].hook(dev);
8715 }
8716 }
8717
8718 /* Disable the VGA plane that we never use */
8719 static void i915_disable_vga(struct drm_device *dev)
8720 {
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8722 u8 sr1;
8723 u32 vga_reg;
8724
8725 if (HAS_PCH_SPLIT(dev))
8726 vga_reg = CPU_VGACNTRL;
8727 else
8728 vga_reg = VGACNTRL;
8729
8730 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8731 outb(SR01, VGA_SR_INDEX);
8732 sr1 = inb(VGA_SR_DATA);
8733 outb(sr1 | 1<<5, VGA_SR_DATA);
8734 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8735 udelay(300);
8736
8737 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8738 POSTING_READ(vga_reg);
8739 }
8740
8741 void intel_modeset_init_hw(struct drm_device *dev)
8742 {
8743 /* We attempt to init the necessary power wells early in the initialization
8744 * time, so the subsystems that expect power to be enabled can work.
8745 */
8746 intel_init_power_wells(dev);
8747
8748 intel_prepare_ddi(dev);
8749
8750 intel_init_clock_gating(dev);
8751
8752 mutex_lock(&dev->struct_mutex);
8753 intel_enable_gt_powersave(dev);
8754 mutex_unlock(&dev->struct_mutex);
8755 }
8756
8757 void intel_modeset_init(struct drm_device *dev)
8758 {
8759 struct drm_i915_private *dev_priv = dev->dev_private;
8760 int i, ret;
8761
8762 drm_mode_config_init(dev);
8763
8764 dev->mode_config.min_width = 0;
8765 dev->mode_config.min_height = 0;
8766
8767 dev->mode_config.preferred_depth = 24;
8768 dev->mode_config.prefer_shadow = 1;
8769
8770 dev->mode_config.funcs = &intel_mode_funcs;
8771
8772 intel_init_quirks(dev);
8773
8774 intel_init_pm(dev);
8775
8776 intel_init_display(dev);
8777
8778 if (IS_GEN2(dev)) {
8779 dev->mode_config.max_width = 2048;
8780 dev->mode_config.max_height = 2048;
8781 } else if (IS_GEN3(dev)) {
8782 dev->mode_config.max_width = 4096;
8783 dev->mode_config.max_height = 4096;
8784 } else {
8785 dev->mode_config.max_width = 8192;
8786 dev->mode_config.max_height = 8192;
8787 }
8788 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8789
8790 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8791 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8792
8793 for (i = 0; i < dev_priv->num_pipe; i++) {
8794 intel_crtc_init(dev, i);
8795 ret = intel_plane_init(dev, i);
8796 if (ret)
8797 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8798 }
8799
8800 intel_cpu_pll_init(dev);
8801 intel_pch_pll_init(dev);
8802
8803 /* Just disable it once at startup */
8804 i915_disable_vga(dev);
8805 intel_setup_outputs(dev);
8806 }
8807
8808 static void
8809 intel_connector_break_all_links(struct intel_connector *connector)
8810 {
8811 connector->base.dpms = DRM_MODE_DPMS_OFF;
8812 connector->base.encoder = NULL;
8813 connector->encoder->connectors_active = false;
8814 connector->encoder->base.crtc = NULL;
8815 }
8816
8817 static void intel_enable_pipe_a(struct drm_device *dev)
8818 {
8819 struct intel_connector *connector;
8820 struct drm_connector *crt = NULL;
8821 struct intel_load_detect_pipe load_detect_temp;
8822
8823 /* We can't just switch on the pipe A, we need to set things up with a
8824 * proper mode and output configuration. As a gross hack, enable pipe A
8825 * by enabling the load detect pipe once. */
8826 list_for_each_entry(connector,
8827 &dev->mode_config.connector_list,
8828 base.head) {
8829 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8830 crt = &connector->base;
8831 break;
8832 }
8833 }
8834
8835 if (!crt)
8836 return;
8837
8838 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8839 intel_release_load_detect_pipe(crt, &load_detect_temp);
8840
8841
8842 }
8843
8844 static bool
8845 intel_check_plane_mapping(struct intel_crtc *crtc)
8846 {
8847 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8848 u32 reg, val;
8849
8850 if (dev_priv->num_pipe == 1)
8851 return true;
8852
8853 reg = DSPCNTR(!crtc->plane);
8854 val = I915_READ(reg);
8855
8856 if ((val & DISPLAY_PLANE_ENABLE) &&
8857 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8858 return false;
8859
8860 return true;
8861 }
8862
8863 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8864 {
8865 struct drm_device *dev = crtc->base.dev;
8866 struct drm_i915_private *dev_priv = dev->dev_private;
8867 u32 reg;
8868
8869 /* Clear any frame start delays used for debugging left by the BIOS */
8870 reg = PIPECONF(crtc->cpu_transcoder);
8871 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8872
8873 /* We need to sanitize the plane -> pipe mapping first because this will
8874 * disable the crtc (and hence change the state) if it is wrong. Note
8875 * that gen4+ has a fixed plane -> pipe mapping. */
8876 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8877 struct intel_connector *connector;
8878 bool plane;
8879
8880 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8881 crtc->base.base.id);
8882
8883 /* Pipe has the wrong plane attached and the plane is active.
8884 * Temporarily change the plane mapping and disable everything
8885 * ... */
8886 plane = crtc->plane;
8887 crtc->plane = !plane;
8888 dev_priv->display.crtc_disable(&crtc->base);
8889 crtc->plane = plane;
8890
8891 /* ... and break all links. */
8892 list_for_each_entry(connector, &dev->mode_config.connector_list,
8893 base.head) {
8894 if (connector->encoder->base.crtc != &crtc->base)
8895 continue;
8896
8897 intel_connector_break_all_links(connector);
8898 }
8899
8900 WARN_ON(crtc->active);
8901 crtc->base.enabled = false;
8902 }
8903
8904 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8905 crtc->pipe == PIPE_A && !crtc->active) {
8906 /* BIOS forgot to enable pipe A, this mostly happens after
8907 * resume. Force-enable the pipe to fix this, the update_dpms
8908 * call below we restore the pipe to the right state, but leave
8909 * the required bits on. */
8910 intel_enable_pipe_a(dev);
8911 }
8912
8913 /* Adjust the state of the output pipe according to whether we
8914 * have active connectors/encoders. */
8915 intel_crtc_update_dpms(&crtc->base);
8916
8917 if (crtc->active != crtc->base.enabled) {
8918 struct intel_encoder *encoder;
8919
8920 /* This can happen either due to bugs in the get_hw_state
8921 * functions or because the pipe is force-enabled due to the
8922 * pipe A quirk. */
8923 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8924 crtc->base.base.id,
8925 crtc->base.enabled ? "enabled" : "disabled",
8926 crtc->active ? "enabled" : "disabled");
8927
8928 crtc->base.enabled = crtc->active;
8929
8930 /* Because we only establish the connector -> encoder ->
8931 * crtc links if something is active, this means the
8932 * crtc is now deactivated. Break the links. connector
8933 * -> encoder links are only establish when things are
8934 * actually up, hence no need to break them. */
8935 WARN_ON(crtc->active);
8936
8937 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8938 WARN_ON(encoder->connectors_active);
8939 encoder->base.crtc = NULL;
8940 }
8941 }
8942 }
8943
8944 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8945 {
8946 struct intel_connector *connector;
8947 struct drm_device *dev = encoder->base.dev;
8948
8949 /* We need to check both for a crtc link (meaning that the
8950 * encoder is active and trying to read from a pipe) and the
8951 * pipe itself being active. */
8952 bool has_active_crtc = encoder->base.crtc &&
8953 to_intel_crtc(encoder->base.crtc)->active;
8954
8955 if (encoder->connectors_active && !has_active_crtc) {
8956 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8957 encoder->base.base.id,
8958 drm_get_encoder_name(&encoder->base));
8959
8960 /* Connector is active, but has no active pipe. This is
8961 * fallout from our resume register restoring. Disable
8962 * the encoder manually again. */
8963 if (encoder->base.crtc) {
8964 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8965 encoder->base.base.id,
8966 drm_get_encoder_name(&encoder->base));
8967 encoder->disable(encoder);
8968 }
8969
8970 /* Inconsistent output/port/pipe state happens presumably due to
8971 * a bug in one of the get_hw_state functions. Or someplace else
8972 * in our code, like the register restore mess on resume. Clamp
8973 * things to off as a safer default. */
8974 list_for_each_entry(connector,
8975 &dev->mode_config.connector_list,
8976 base.head) {
8977 if (connector->encoder != encoder)
8978 continue;
8979
8980 intel_connector_break_all_links(connector);
8981 }
8982 }
8983 /* Enabled encoders without active connectors will be fixed in
8984 * the crtc fixup. */
8985 }
8986
8987 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8988 * and i915 state tracking structures. */
8989 void intel_modeset_setup_hw_state(struct drm_device *dev)
8990 {
8991 struct drm_i915_private *dev_priv = dev->dev_private;
8992 enum pipe pipe;
8993 u32 tmp;
8994 struct intel_crtc *crtc;
8995 struct intel_encoder *encoder;
8996 struct intel_connector *connector;
8997
8998 if (IS_HASWELL(dev)) {
8999 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9000
9001 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9002 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9003 case TRANS_DDI_EDP_INPUT_A_ON:
9004 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9005 pipe = PIPE_A;
9006 break;
9007 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9008 pipe = PIPE_B;
9009 break;
9010 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9011 pipe = PIPE_C;
9012 break;
9013 }
9014
9015 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9016 crtc->cpu_transcoder = TRANSCODER_EDP;
9017
9018 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9019 pipe_name(pipe));
9020 }
9021 }
9022
9023 for_each_pipe(pipe) {
9024 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9025
9026 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9027 if (tmp & PIPECONF_ENABLE)
9028 crtc->active = true;
9029 else
9030 crtc->active = false;
9031
9032 crtc->base.enabled = crtc->active;
9033
9034 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9035 crtc->base.base.id,
9036 crtc->active ? "enabled" : "disabled");
9037 }
9038
9039 if (IS_HASWELL(dev))
9040 intel_ddi_setup_hw_pll_state(dev);
9041
9042 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9043 base.head) {
9044 pipe = 0;
9045
9046 if (encoder->get_hw_state(encoder, &pipe)) {
9047 encoder->base.crtc =
9048 dev_priv->pipe_to_crtc_mapping[pipe];
9049 } else {
9050 encoder->base.crtc = NULL;
9051 }
9052
9053 encoder->connectors_active = false;
9054 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9055 encoder->base.base.id,
9056 drm_get_encoder_name(&encoder->base),
9057 encoder->base.crtc ? "enabled" : "disabled",
9058 pipe);
9059 }
9060
9061 list_for_each_entry(connector, &dev->mode_config.connector_list,
9062 base.head) {
9063 if (connector->get_hw_state(connector)) {
9064 connector->base.dpms = DRM_MODE_DPMS_ON;
9065 connector->encoder->connectors_active = true;
9066 connector->base.encoder = &connector->encoder->base;
9067 } else {
9068 connector->base.dpms = DRM_MODE_DPMS_OFF;
9069 connector->base.encoder = NULL;
9070 }
9071 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9072 connector->base.base.id,
9073 drm_get_connector_name(&connector->base),
9074 connector->base.encoder ? "enabled" : "disabled");
9075 }
9076
9077 /* HW state is read out, now we need to sanitize this mess. */
9078 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9079 base.head) {
9080 intel_sanitize_encoder(encoder);
9081 }
9082
9083 for_each_pipe(pipe) {
9084 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9085 intel_sanitize_crtc(crtc);
9086 }
9087
9088 intel_modeset_update_staged_output_state(dev);
9089
9090 intel_modeset_check_state(dev);
9091
9092 drm_mode_config_reset(dev);
9093 }
9094
9095 void intel_modeset_gem_init(struct drm_device *dev)
9096 {
9097 intel_modeset_init_hw(dev);
9098
9099 intel_setup_overlay(dev);
9100
9101 intel_modeset_setup_hw_state(dev);
9102 }
9103
9104 void intel_modeset_cleanup(struct drm_device *dev)
9105 {
9106 struct drm_i915_private *dev_priv = dev->dev_private;
9107 struct drm_crtc *crtc;
9108 struct intel_crtc *intel_crtc;
9109
9110 drm_kms_helper_poll_fini(dev);
9111 mutex_lock(&dev->struct_mutex);
9112
9113 intel_unregister_dsm_handler();
9114
9115
9116 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9117 /* Skip inactive CRTCs */
9118 if (!crtc->fb)
9119 continue;
9120
9121 intel_crtc = to_intel_crtc(crtc);
9122 intel_increase_pllclock(crtc);
9123 }
9124
9125 intel_disable_fbc(dev);
9126
9127 intel_disable_gt_powersave(dev);
9128
9129 ironlake_teardown_rc6(dev);
9130
9131 if (IS_VALLEYVIEW(dev))
9132 vlv_init_dpio(dev);
9133
9134 mutex_unlock(&dev->struct_mutex);
9135
9136 /* Disable the irq before mode object teardown, for the irq might
9137 * enqueue unpin/hotplug work. */
9138 drm_irq_uninstall(dev);
9139 cancel_work_sync(&dev_priv->hotplug_work);
9140 cancel_work_sync(&dev_priv->rps.work);
9141
9142 /* flush any delayed tasks or pending work */
9143 flush_scheduled_work();
9144
9145 drm_mode_config_cleanup(dev);
9146 }
9147
9148 /*
9149 * Return which encoder is currently attached for connector.
9150 */
9151 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9152 {
9153 return &intel_attached_encoder(connector)->base;
9154 }
9155
9156 void intel_connector_attach_encoder(struct intel_connector *connector,
9157 struct intel_encoder *encoder)
9158 {
9159 connector->encoder = encoder;
9160 drm_mode_connector_attach_encoder(&connector->base,
9161 &encoder->base);
9162 }
9163
9164 /*
9165 * set vga decode state - true == enable VGA decode
9166 */
9167 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9168 {
9169 struct drm_i915_private *dev_priv = dev->dev_private;
9170 u16 gmch_ctrl;
9171
9172 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9173 if (state)
9174 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9175 else
9176 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9177 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9178 return 0;
9179 }
9180
9181 #ifdef CONFIG_DEBUG_FS
9182 #include <linux/seq_file.h>
9183
9184 struct intel_display_error_state {
9185 struct intel_cursor_error_state {
9186 u32 control;
9187 u32 position;
9188 u32 base;
9189 u32 size;
9190 } cursor[I915_MAX_PIPES];
9191
9192 struct intel_pipe_error_state {
9193 u32 conf;
9194 u32 source;
9195
9196 u32 htotal;
9197 u32 hblank;
9198 u32 hsync;
9199 u32 vtotal;
9200 u32 vblank;
9201 u32 vsync;
9202 } pipe[I915_MAX_PIPES];
9203
9204 struct intel_plane_error_state {
9205 u32 control;
9206 u32 stride;
9207 u32 size;
9208 u32 pos;
9209 u32 addr;
9210 u32 surface;
9211 u32 tile_offset;
9212 } plane[I915_MAX_PIPES];
9213 };
9214
9215 struct intel_display_error_state *
9216 intel_display_capture_error_state(struct drm_device *dev)
9217 {
9218 drm_i915_private_t *dev_priv = dev->dev_private;
9219 struct intel_display_error_state *error;
9220 enum transcoder cpu_transcoder;
9221 int i;
9222
9223 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9224 if (error == NULL)
9225 return NULL;
9226
9227 for_each_pipe(i) {
9228 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9229
9230 error->cursor[i].control = I915_READ(CURCNTR(i));
9231 error->cursor[i].position = I915_READ(CURPOS(i));
9232 error->cursor[i].base = I915_READ(CURBASE(i));
9233
9234 error->plane[i].control = I915_READ(DSPCNTR(i));
9235 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9236 error->plane[i].size = I915_READ(DSPSIZE(i));
9237 error->plane[i].pos = I915_READ(DSPPOS(i));
9238 error->plane[i].addr = I915_READ(DSPADDR(i));
9239 if (INTEL_INFO(dev)->gen >= 4) {
9240 error->plane[i].surface = I915_READ(DSPSURF(i));
9241 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9242 }
9243
9244 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9245 error->pipe[i].source = I915_READ(PIPESRC(i));
9246 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9247 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9248 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9249 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9250 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9251 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9252 }
9253
9254 return error;
9255 }
9256
9257 void
9258 intel_display_print_error_state(struct seq_file *m,
9259 struct drm_device *dev,
9260 struct intel_display_error_state *error)
9261 {
9262 drm_i915_private_t *dev_priv = dev->dev_private;
9263 int i;
9264
9265 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9266 for_each_pipe(i) {
9267 seq_printf(m, "Pipe [%d]:\n", i);
9268 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9269 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9270 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9271 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9272 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9273 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9274 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9275 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9276
9277 seq_printf(m, "Plane [%d]:\n", i);
9278 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9279 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9280 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9281 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9282 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9283 if (INTEL_INFO(dev)->gen >= 4) {
9284 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9285 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9286 }
9287
9288 seq_printf(m, "Cursor [%d]:\n", i);
9289 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9290 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9291 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9292 }
9293 }
9294 #endif
Linux kernel - Deliverables
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