projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Use global atomic state for staged pll, config, v3.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
113 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
114
115 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
116 {
117 if (!connector->mst_port)
118 return connector->encoder;
119 else
120 return &connector->mst_port->mst_encoders[pipe]->base;
121 }
122
123 typedef struct {
124 int min, max;
125 } intel_range_t;
126
127 typedef struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130 } intel_p2_t;
131
132 typedef struct intel_limit intel_limit_t;
133 struct intel_limit {
134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
136 };
137
138 int
139 intel_pch_rawclk(struct drm_device *dev)
140 {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142
143 WARN_ON(!HAS_PCH_SPLIT(dev));
144
145 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
146 }
147
148 static inline u32 /* units of 100MHz */
149 intel_fdi_link_freq(struct drm_device *dev)
150 {
151 if (IS_GEN5(dev)) {
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
154 } else
155 return 27;
156 }
157
158 static const intel_limit_t intel_limits_i8xx_dac = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 2 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_dvo = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 2, .max = 33 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 4, .p2_fast = 4 },
182 };
183
184 static const intel_limit_t intel_limits_i8xx_lvds = {
185 .dot = { .min = 25000, .max = 350000 },
186 .vco = { .min = 908000, .max = 1512000 },
187 .n = { .min = 2, .max = 16 },
188 .m = { .min = 96, .max = 140 },
189 .m1 = { .min = 18, .max = 26 },
190 .m2 = { .min = 6, .max = 16 },
191 .p = { .min = 4, .max = 128 },
192 .p1 = { .min = 1, .max = 6 },
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 14, .p2_fast = 7 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_sdvo = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 200000,
207 .p2_slow = 10, .p2_fast = 5 },
208 };
209
210 static const intel_limit_t intel_limits_i9xx_lvds = {
211 .dot = { .min = 20000, .max = 400000 },
212 .vco = { .min = 1400000, .max = 2800000 },
213 .n = { .min = 1, .max = 6 },
214 .m = { .min = 70, .max = 120 },
215 .m1 = { .min = 8, .max = 18 },
216 .m2 = { .min = 3, .max = 7 },
217 .p = { .min = 7, .max = 98 },
218 .p1 = { .min = 1, .max = 8 },
219 .p2 = { .dot_limit = 112000,
220 .p2_slow = 14, .p2_fast = 7 },
221 };
222
223
224 static const intel_limit_t intel_limits_g4x_sdvo = {
225 .dot = { .min = 25000, .max = 270000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 10, .max = 30 },
232 .p1 = { .min = 1, .max = 3},
233 .p2 = { .dot_limit = 270000,
234 .p2_slow = 10,
235 .p2_fast = 10
236 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_hdmi = {
240 .dot = { .min = 22000, .max = 400000 },
241 .vco = { .min = 1750000, .max = 3500000},
242 .n = { .min = 1, .max = 4 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 16, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8},
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 10, .p2_fast = 5 },
250 };
251
252 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
253 .dot = { .min = 20000, .max = 115000 },
254 .vco = { .min = 1750000, .max = 3500000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 104, .max = 138 },
257 .m1 = { .min = 17, .max = 23 },
258 .m2 = { .min = 5, .max = 11 },
259 .p = { .min = 28, .max = 112 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 0,
262 .p2_slow = 14, .p2_fast = 14
263 },
264 };
265
266 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
267 .dot = { .min = 80000, .max = 224000 },
268 .vco = { .min = 1750000, .max = 3500000 },
269 .n = { .min = 1, .max = 3 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 17, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 14, .max = 42 },
274 .p1 = { .min = 2, .max = 6 },
275 .p2 = { .dot_limit = 0,
276 .p2_slow = 7, .p2_fast = 7
277 },
278 };
279
280 static const intel_limit_t intel_limits_pineview_sdvo = {
281 .dot = { .min = 20000, .max = 400000},
282 .vco = { .min = 1700000, .max = 3500000 },
283 /* Pineview's Ncounter is a ring counter */
284 .n = { .min = 3, .max = 6 },
285 .m = { .min = 2, .max = 256 },
286 /* Pineview only has one combined m divider, which we treat as m2. */
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 200000,
292 .p2_slow = 10, .p2_fast = 5 },
293 };
294
295 static const intel_limit_t intel_limits_pineview_lvds = {
296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1700000, .max = 3500000 },
298 .n = { .min = 3, .max = 6 },
299 .m = { .min = 2, .max = 256 },
300 .m1 = { .min = 0, .max = 0 },
301 .m2 = { .min = 0, .max = 254 },
302 .p = { .min = 7, .max = 112 },
303 .p1 = { .min = 1, .max = 8 },
304 .p2 = { .dot_limit = 112000,
305 .p2_slow = 14, .p2_fast = 14 },
306 };
307
308 /* Ironlake / Sandybridge
309 *
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
312 */
313 static const intel_limit_t intel_limits_ironlake_dac = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 5 },
317 .m = { .min = 79, .max = 127 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 5, .max = 80 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 10, .p2_fast = 5 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_single_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 118 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 28, .max = 112 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 14, .p2_fast = 14 },
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 127 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 56 },
347 .p1 = { .min = 2, .max = 8 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 };
351
352 /* LVDS 100mhz refclk limits. */
353 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
364 };
365
366 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 126 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
377 };
378
379 static const intel_limit_t intel_limits_vlv = {
380 /*
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
385 */
386 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
387 .vco = { .min = 4000000, .max = 6000000 },
388 .n = { .min = 1, .max = 7 },
389 .m1 = { .min = 2, .max = 3 },
390 .m2 = { .min = 11, .max = 156 },
391 .p1 = { .min = 2, .max = 3 },
392 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
393 };
394
395 static const intel_limit_t intel_limits_chv = {
396 /*
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
401 */
402 .dot = { .min = 25000 * 5, .max = 540000 * 5},
403 .vco = { .min = 4800000, .max = 6480000 },
404 .n = { .min = 1, .max = 1 },
405 .m1 = { .min = 2, .max = 2 },
406 .m2 = { .min = 24 << 22, .max = 175 << 22 },
407 .p1 = { .min = 2, .max = 4 },
408 .p2 = { .p2_slow = 1, .p2_fast = 14 },
409 };
410
411 static const intel_limit_t intel_limits_bxt = {
412 /* FIXME: find real dot limits */
413 .dot = { .min = 0, .max = INT_MAX },
414 .vco = { .min = 4800000, .max = 6480000 },
415 .n = { .min = 1, .max = 1 },
416 .m1 = { .min = 2, .max = 2 },
417 /* FIXME: find real m2 limits */
418 .m2 = { .min = 2 << 22, .max = 255 << 22 },
419 .p1 = { .min = 2, .max = 4 },
420 .p2 = { .p2_slow = 1, .p2_fast = 20 },
421 };
422
423 static void vlv_clock(int refclk, intel_clock_t *clock)
424 {
425 clock->m = clock->m1 * clock->m2;
426 clock->p = clock->p1 * clock->p2;
427 if (WARN_ON(clock->n == 0 || clock->p == 0))
428 return;
429 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
430 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
431 }
432
433 static bool
434 needs_modeset(struct drm_crtc_state *state)
435 {
436 return state->mode_changed || state->active_changed;
437 }
438
439 /**
440 * Returns whether any output on the specified pipe is of the specified type
441 */
442 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
443 {
444 struct drm_device *dev = crtc->base.dev;
445 struct intel_encoder *encoder;
446
447 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
448 if (encoder->type == type)
449 return true;
450
451 return false;
452 }
453
454 /**
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
458 * encoder->crtc.
459 */
460 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
461 int type)
462 {
463 struct drm_atomic_state *state = crtc_state->base.state;
464 struct drm_connector *connector;
465 struct drm_connector_state *connector_state;
466 struct intel_encoder *encoder;
467 int i, num_connectors = 0;
468
469 for_each_connector_in_state(state, connector, connector_state, i) {
470 if (connector_state->crtc != crtc_state->base.crtc)
471 continue;
472
473 num_connectors++;
474
475 encoder = to_intel_encoder(connector_state->best_encoder);
476 if (encoder->type == type)
477 return true;
478 }
479
480 WARN_ON(num_connectors == 0);
481
482 return false;
483 }
484
485 static const intel_limit_t *
486 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
487 {
488 struct drm_device *dev = crtc_state->base.crtc->dev;
489 const intel_limit_t *limit;
490
491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
492 if (intel_is_dual_link_lvds(dev)) {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_dual_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_dual_lvds;
497 } else {
498 if (refclk == 100000)
499 limit = &intel_limits_ironlake_single_lvds_100m;
500 else
501 limit = &intel_limits_ironlake_single_lvds;
502 }
503 } else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507 }
508
509 static const intel_limit_t *
510 intel_g4x_limit(struct intel_crtc_state *crtc_state)
511 {
512 struct drm_device *dev = crtc_state->base.crtc->dev;
513 const intel_limit_t *limit;
514
515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
516 if (intel_is_dual_link_lvds(dev))
517 limit = &intel_limits_g4x_dual_channel_lvds;
518 else
519 limit = &intel_limits_g4x_single_channel_lvds;
520 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
522 limit = &intel_limits_g4x_hdmi;
523 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
524 limit = &intel_limits_g4x_sdvo;
525 } else /* The option is for other outputs */
526 limit = &intel_limits_i9xx_sdvo;
527
528 return limit;
529 }
530
531 static const intel_limit_t *
532 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
533 {
534 struct drm_device *dev = crtc_state->base.crtc->dev;
535 const intel_limit_t *limit;
536
537 if (IS_BROXTON(dev))
538 limit = &intel_limits_bxt;
539 else if (HAS_PCH_SPLIT(dev))
540 limit = intel_ironlake_limit(crtc_state, refclk);
541 else if (IS_G4X(dev)) {
542 limit = intel_g4x_limit(crtc_state);
543 } else if (IS_PINEVIEW(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_pineview_lvds;
546 else
547 limit = &intel_limits_pineview_sdvo;
548 } else if (IS_CHERRYVIEW(dev)) {
549 limit = &intel_limits_chv;
550 } else if (IS_VALLEYVIEW(dev)) {
551 limit = &intel_limits_vlv;
552 } else if (!IS_GEN2(dev)) {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i9xx_lvds;
555 else
556 limit = &intel_limits_i9xx_sdvo;
557 } else {
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
559 limit = &intel_limits_i8xx_lvds;
560 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
561 limit = &intel_limits_i8xx_dvo;
562 else
563 limit = &intel_limits_i8xx_dac;
564 }
565 return limit;
566 }
567
568 /* m1 is reserved as 0 in Pineview, n is a ring counter */
569 static void pineview_clock(int refclk, intel_clock_t *clock)
570 {
571 clock->m = clock->m2 + 2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
576 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
577 }
578
579 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
580 {
581 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
582 }
583
584 static void i9xx_clock(int refclk, intel_clock_t *clock)
585 {
586 clock->m = i9xx_dpll_compute_m(clock);
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
589 return;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592 }
593
594 static void chv_clock(int refclk, intel_clock_t *clock)
595 {
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
599 return;
600 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
601 clock->n << 22);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603 }
604
605 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
606 /**
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
609 */
610
611 static bool intel_PLL_is_valid(struct drm_device *dev,
612 const intel_limit_t *limit,
613 const intel_clock_t *clock)
614 {
615 if (clock->n < limit->n.min || limit->n.max < clock->n)
616 INTELPllInvalid("n out of range\n");
617 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
618 INTELPllInvalid("p1 out of range\n");
619 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
620 INTELPllInvalid("m2 out of range\n");
621 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
622 INTELPllInvalid("m1 out of range\n");
623
624 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
625 if (clock->m1 <= clock->m2)
626 INTELPllInvalid("m1 <= m2\n");
627
628 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
634
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
642
643 return true;
644 }
645
646 static bool
647 i9xx_find_best_dpll(const intel_limit_t *limit,
648 struct intel_crtc_state *crtc_state,
649 int target, int refclk, intel_clock_t *match_clock,
650 intel_clock_t *best_clock)
651 {
652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
653 struct drm_device *dev = crtc->base.dev;
654 intel_clock_t clock;
655 int err = target;
656
657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
658 /*
659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
662 */
663 if (intel_is_dual_link_lvds(dev))
664 clock.p2 = limit->p2.p2_fast;
665 else
666 clock.p2 = limit->p2.p2_slow;
667 } else {
668 if (target < limit->p2.dot_limit)
669 clock.p2 = limit->p2.p2_slow;
670 else
671 clock.p2 = limit->p2.p2_fast;
672 }
673
674 memset(best_clock, 0, sizeof(*best_clock));
675
676 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
677 clock.m1++) {
678 for (clock.m2 = limit->m2.min;
679 clock.m2 <= limit->m2.max; clock.m2++) {
680 if (clock.m2 >= clock.m1)
681 break;
682 for (clock.n = limit->n.min;
683 clock.n <= limit->n.max; clock.n++) {
684 for (clock.p1 = limit->p1.min;
685 clock.p1 <= limit->p1.max; clock.p1++) {
686 int this_err;
687
688 i9xx_clock(refclk, &clock);
689 if (!intel_PLL_is_valid(dev, limit,
690 &clock))
691 continue;
692 if (match_clock &&
693 clock.p != match_clock->p)
694 continue;
695
696 this_err = abs(clock.dot - target);
697 if (this_err < err) {
698 *best_clock = clock;
699 err = this_err;
700 }
701 }
702 }
703 }
704 }
705
706 return (err != target);
707 }
708
709 static bool
710 pnv_find_best_dpll(const intel_limit_t *limit,
711 struct intel_crtc_state *crtc_state,
712 int target, int refclk, intel_clock_t *match_clock,
713 intel_clock_t *best_clock)
714 {
715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
716 struct drm_device *dev = crtc->base.dev;
717 intel_clock_t clock;
718 int err = target;
719
720 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
721 /*
722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
725 */
726 if (intel_is_dual_link_lvds(dev))
727 clock.p2 = limit->p2.p2_fast;
728 else
729 clock.p2 = limit->p2.p2_slow;
730 } else {
731 if (target < limit->p2.dot_limit)
732 clock.p2 = limit->p2.p2_slow;
733 else
734 clock.p2 = limit->p2.p2_fast;
735 }
736
737 memset(best_clock, 0, sizeof(*best_clock));
738
739 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 clock.m1++) {
741 for (clock.m2 = limit->m2.min;
742 clock.m2 <= limit->m2.max; clock.m2++) {
743 for (clock.n = limit->n.min;
744 clock.n <= limit->n.max; clock.n++) {
745 for (clock.p1 = limit->p1.min;
746 clock.p1 <= limit->p1.max; clock.p1++) {
747 int this_err;
748
749 pineview_clock(refclk, &clock);
750 if (!intel_PLL_is_valid(dev, limit,
751 &clock))
752 continue;
753 if (match_clock &&
754 clock.p != match_clock->p)
755 continue;
756
757 this_err = abs(clock.dot - target);
758 if (this_err < err) {
759 *best_clock = clock;
760 err = this_err;
761 }
762 }
763 }
764 }
765 }
766
767 return (err != target);
768 }
769
770 static bool
771 g4x_find_best_dpll(const intel_limit_t *limit,
772 struct intel_crtc_state *crtc_state,
773 int target, int refclk, intel_clock_t *match_clock,
774 intel_clock_t *best_clock)
775 {
776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
777 struct drm_device *dev = crtc->base.dev;
778 intel_clock_t clock;
779 int max_n;
780 bool found;
781 /* approximately equals target * 0.00585 */
782 int err_most = (target >> 8) + (target >> 9);
783 found = false;
784
785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
786 if (intel_is_dual_link_lvds(dev))
787 clock.p2 = limit->p2.p2_fast;
788 else
789 clock.p2 = limit->p2.p2_slow;
790 } else {
791 if (target < limit->p2.dot_limit)
792 clock.p2 = limit->p2.p2_slow;
793 else
794 clock.p2 = limit->p2.p2_fast;
795 }
796
797 memset(best_clock, 0, sizeof(*best_clock));
798 max_n = limit->n.max;
799 /* based on hardware requirement, prefer smaller n to precision */
800 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
801 /* based on hardware requirement, prefere larger m1,m2 */
802 for (clock.m1 = limit->m1.max;
803 clock.m1 >= limit->m1.min; clock.m1--) {
804 for (clock.m2 = limit->m2.max;
805 clock.m2 >= limit->m2.min; clock.m2--) {
806 for (clock.p1 = limit->p1.max;
807 clock.p1 >= limit->p1.min; clock.p1--) {
808 int this_err;
809
810 i9xx_clock(refclk, &clock);
811 if (!intel_PLL_is_valid(dev, limit,
812 &clock))
813 continue;
814
815 this_err = abs(clock.dot - target);
816 if (this_err < err_most) {
817 *best_clock = clock;
818 err_most = this_err;
819 max_n = clock.n;
820 found = true;
821 }
822 }
823 }
824 }
825 }
826 return found;
827 }
828
829 /*
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
832 */
833 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
834 const intel_clock_t *calculated_clock,
835 const intel_clock_t *best_clock,
836 unsigned int best_error_ppm,
837 unsigned int *error_ppm)
838 {
839 /*
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
842 */
843 if (IS_CHERRYVIEW(dev)) {
844 *error_ppm = 0;
845
846 return calculated_clock->p > best_clock->p;
847 }
848
849 if (WARN_ON_ONCE(!target_freq))
850 return false;
851
852 *error_ppm = div_u64(1000000ULL *
853 abs(target_freq - calculated_clock->dot),
854 target_freq);
855 /*
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
859 */
860 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
861 *error_ppm = 0;
862
863 return true;
864 }
865
866 return *error_ppm + 10 < best_error_ppm;
867 }
868
869 static bool
870 vlv_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
874 {
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
876 struct drm_device *dev = crtc->base.dev;
877 intel_clock_t clock;
878 unsigned int bestppm = 1000000;
879 /* min update 19.2 MHz */
880 int max_n = min(limit->n.max, refclk / 19200);
881 bool found = false;
882
883 target *= 5; /* fast clock */
884
885 memset(best_clock, 0, sizeof(*best_clock));
886
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
889 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
890 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
891 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
892 clock.p = clock.p1 * clock.p2;
893 /* based on hardware requirement, prefer bigger m1,m2 values */
894 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
895 unsigned int ppm;
896
897 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
898 refclk * clock.m1);
899
900 vlv_clock(refclk, &clock);
901
902 if (!intel_PLL_is_valid(dev, limit,
903 &clock))
904 continue;
905
906 if (!vlv_PLL_is_optimal(dev, target,
907 &clock,
908 best_clock,
909 bestppm, &ppm))
910 continue;
911
912 *best_clock = clock;
913 bestppm = ppm;
914 found = true;
915 }
916 }
917 }
918 }
919
920 return found;
921 }
922
923 static bool
924 chv_find_best_dpll(const intel_limit_t *limit,
925 struct intel_crtc_state *crtc_state,
926 int target, int refclk, intel_clock_t *match_clock,
927 intel_clock_t *best_clock)
928 {
929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
930 struct drm_device *dev = crtc->base.dev;
931 unsigned int best_error_ppm;
932 intel_clock_t clock;
933 uint64_t m2;
934 int found = false;
935
936 memset(best_clock, 0, sizeof(*best_clock));
937 best_error_ppm = 1000000;
938
939 /*
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
943 */
944 clock.n = 1, clock.m1 = 2;
945 target *= 5; /* fast clock */
946
947 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
948 for (clock.p2 = limit->p2.p2_fast;
949 clock.p2 >= limit->p2.p2_slow;
950 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
951 unsigned int error_ppm;
952
953 clock.p = clock.p1 * clock.p2;
954
955 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
956 clock.n) << 22, refclk * clock.m1);
957
958 if (m2 > INT_MAX/clock.m1)
959 continue;
960
961 clock.m2 = m2;
962
963 chv_clock(refclk, &clock);
964
965 if (!intel_PLL_is_valid(dev, limit, &clock))
966 continue;
967
968 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
969 best_error_ppm, &error_ppm))
970 continue;
971
972 *best_clock = clock;
973 best_error_ppm = error_ppm;
974 found = true;
975 }
976 }
977
978 return found;
979 }
980
981 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
982 intel_clock_t *best_clock)
983 {
984 int refclk = i9xx_get_refclk(crtc_state, 0);
985
986 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
987 target_clock, refclk, NULL, best_clock);
988 }
989
990 bool intel_crtc_active(struct drm_crtc *crtc)
991 {
992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
996 *
997 * We can ditch the adjusted_mode.crtc_clock check as soon
998 * as Haswell has gained clock readout/fastboot support.
999 *
1000 * We can ditch the crtc->primary->fb check as soon as we can
1001 * properly reconstruct framebuffers.
1002 *
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1005 * for atomic.
1006 */
1007 return intel_crtc->active && crtc->primary->state->fb &&
1008 intel_crtc->config->base.adjusted_mode.crtc_clock;
1009 }
1010
1011 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1012 enum pipe pipe)
1013 {
1014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1016
1017 return intel_crtc->config->cpu_transcoder;
1018 }
1019
1020 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1021 {
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 reg = PIPEDSL(pipe);
1024 u32 line1, line2;
1025 u32 line_mask;
1026
1027 if (IS_GEN2(dev))
1028 line_mask = DSL_LINEMASK_GEN2;
1029 else
1030 line_mask = DSL_LINEMASK_GEN3;
1031
1032 line1 = I915_READ(reg) & line_mask;
1033 mdelay(5);
1034 line2 = I915_READ(reg) & line_mask;
1035
1036 return line1 == line2;
1037 }
1038
1039 /*
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
1041 * @crtc: crtc whose pipe to wait for
1042 *
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1046 *
1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1049 *
1050 * Otherwise:
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
1053 *
1054 */
1055 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1056 {
1057 struct drm_device *dev = crtc->base.dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1060 enum pipe pipe = crtc->pipe;
1061
1062 if (INTEL_INFO(dev)->gen >= 4) {
1063 int reg = PIPECONF(cpu_transcoder);
1064
1065 /* Wait for the Pipe State to go off */
1066 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1067 100))
1068 WARN(1, "pipe_off wait timed out\n");
1069 } else {
1070 /* Wait for the display line to settle */
1071 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1072 WARN(1, "pipe_off wait timed out\n");
1073 }
1074 }
1075
1076 /*
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1080 *
1081 * Returns true if @port is connected, false otherwise.
1082 */
1083 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084 struct intel_digital_port *port)
1085 {
1086 u32 bit;
1087
1088 if (HAS_PCH_IBX(dev_priv->dev)) {
1089 switch (port->port) {
1090 case PORT_B:
1091 bit = SDE_PORTB_HOTPLUG;
1092 break;
1093 case PORT_C:
1094 bit = SDE_PORTC_HOTPLUG;
1095 break;
1096 case PORT_D:
1097 bit = SDE_PORTD_HOTPLUG;
1098 break;
1099 default:
1100 return true;
1101 }
1102 } else {
1103 switch (port->port) {
1104 case PORT_B:
1105 bit = SDE_PORTB_HOTPLUG_CPT;
1106 break;
1107 case PORT_C:
1108 bit = SDE_PORTC_HOTPLUG_CPT;
1109 break;
1110 case PORT_D:
1111 bit = SDE_PORTD_HOTPLUG_CPT;
1112 break;
1113 default:
1114 return true;
1115 }
1116 }
1117
1118 return I915_READ(SDEISR) & bit;
1119 }
1120
1121 static const char *state_string(bool enabled)
1122 {
1123 return enabled ? "on" : "off";
1124 }
1125
1126 /* Only for pre-ILK configs */
1127 void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
1129 {
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133
1134 reg = DPLL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DPLL_VCO_ENABLE);
1137 I915_STATE_WARN(cur_state != state,
1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141
1142 /* XXX: the dsi pll is shared between MIPI DSI ports */
1143 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144 {
1145 u32 val;
1146 bool cur_state;
1147
1148 mutex_lock(&dev_priv->sb_lock);
1149 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1150 mutex_unlock(&dev_priv->sb_lock);
1151
1152 cur_state = val & DSI_PLL_VCO_EN;
1153 I915_STATE_WARN(cur_state != state,
1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156 }
1157 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1159
1160 struct intel_shared_dpll *
1161 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1162 {
1163 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1164
1165 if (crtc->config->shared_dpll < 0)
1166 return NULL;
1167
1168 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1169 }
1170
1171 /* For ILK+ */
1172 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173 struct intel_shared_dpll *pll,
1174 bool state)
1175 {
1176 bool cur_state;
1177 struct intel_dpll_hw_state hw_state;
1178
1179 if (WARN (!pll,
1180 "asserting DPLL %s with no DPLL\n", state_string(state)))
1181 return;
1182
1183 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1184 I915_STATE_WARN(cur_state != state,
1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll->name, state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 int reg;
1193 u32 val;
1194 bool cur_state;
1195 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1196 pipe);
1197
1198 if (HAS_DDI(dev_priv->dev)) {
1199 /* DDI does not have a specific FDI_TX register */
1200 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1203 } else {
1204 reg = FDI_TX_CTL(pipe);
1205 val = I915_READ(reg);
1206 cur_state = !!(val & FDI_TX_ENABLE);
1207 }
1208 I915_STATE_WARN(cur_state != state,
1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211 }
1212 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1214
1215 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1217 {
1218 int reg;
1219 u32 val;
1220 bool cur_state;
1221
1222 reg = FDI_RX_CTL(pipe);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & FDI_RX_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state), state_string(cur_state));
1228 }
1229 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1231
1232 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 int reg;
1236 u32 val;
1237
1238 /* ILK FDI PLL is always enabled */
1239 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1240 return;
1241
1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1243 if (HAS_DDI(dev_priv->dev))
1244 return;
1245
1246 reg = FDI_TX_CTL(pipe);
1247 val = I915_READ(reg);
1248 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1249 }
1250
1251 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = FDI_RX_CTL(pipe);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state), state_string(cur_state));
1264 }
1265
1266 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
1268 {
1269 struct drm_device *dev = dev_priv->dev;
1270 int pp_reg;
1271 u32 val;
1272 enum pipe panel_pipe = PIPE_A;
1273 bool locked = true;
1274
1275 if (WARN_ON(HAS_DDI(dev)))
1276 return;
1277
1278 if (HAS_PCH_SPLIT(dev)) {
1279 u32 port_sel;
1280
1281 pp_reg = PCH_PP_CONTROL;
1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291 panel_pipe = pipe;
1292 } else {
1293 pp_reg = PP_CONTROL;
1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
1296 }
1297
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1301 locked = false;
1302
1303 I915_STATE_WARN(panel_pipe == pipe && locked,
1304 "panel assertion failure, pipe %c regs locked\n",
1305 pipe_name(pipe));
1306 }
1307
1308 static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1310 {
1311 struct drm_device *dev = dev_priv->dev;
1312 bool cur_state;
1313
1314 if (IS_845G(dev) || IS_I865G(dev))
1315 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1316 else
1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1318
1319 I915_STATE_WARN(cur_state != state,
1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), state_string(state), state_string(cur_state));
1322 }
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
1326 void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 int reg;
1330 u32 val;
1331 bool cur_state;
1332 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1333 pipe);
1334
1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338 state = true;
1339
1340 if (!intel_display_power_is_enabled(dev_priv,
1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1342 cur_state = false;
1343 } else {
1344 reg = PIPECONF(cpu_transcoder);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & PIPECONF_ENABLE);
1347 }
1348
1349 I915_STATE_WARN(cur_state != state,
1350 "pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1352 }
1353
1354 static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
1356 {
1357 int reg;
1358 u32 val;
1359 bool cur_state;
1360
1361 reg = DSPCNTR(plane);
1362 val = I915_READ(reg);
1363 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1364 I915_STATE_WARN(cur_state != state,
1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane), state_string(state), state_string(cur_state));
1367 }
1368
1369 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1371
1372 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374 {
1375 struct drm_device *dev = dev_priv->dev;
1376 int reg, i;
1377 u32 val;
1378 int cur_pipe;
1379
1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev)->gen >= 4) {
1382 reg = DSPCNTR(pipe);
1383 val = I915_READ(reg);
1384 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1385 "plane %c assertion failure, should be disabled but not\n",
1386 plane_name(pipe));
1387 return;
1388 }
1389
1390 /* Need to check both planes against the pipe */
1391 for_each_pipe(dev_priv, i) {
1392 reg = DSPCNTR(i);
1393 val = I915_READ(reg);
1394 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395 DISPPLANE_SEL_PIPE_SHIFT;
1396 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i), pipe_name(pipe));
1399 }
1400 }
1401
1402 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404 {
1405 struct drm_device *dev = dev_priv->dev;
1406 int reg, sprite;
1407 u32 val;
1408
1409 if (INTEL_INFO(dev)->gen >= 9) {
1410 for_each_sprite(dev_priv, pipe, sprite) {
1411 val = I915_READ(PLANE_CTL(pipe, sprite));
1412 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite, pipe_name(pipe));
1415 }
1416 } else if (IS_VALLEYVIEW(dev)) {
1417 for_each_sprite(dev_priv, pipe, sprite) {
1418 reg = SPCNTR(pipe, sprite);
1419 val = I915_READ(reg);
1420 I915_STATE_WARN(val & SP_ENABLE,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 sprite_name(pipe, sprite), pipe_name(pipe));
1423 }
1424 } else if (INTEL_INFO(dev)->gen >= 7) {
1425 reg = SPRCTL(pipe);
1426 val = I915_READ(reg);
1427 I915_STATE_WARN(val & SPRITE_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 plane_name(pipe), pipe_name(pipe));
1430 } else if (INTEL_INFO(dev)->gen >= 5) {
1431 reg = DVSCNTR(pipe);
1432 val = I915_READ(reg);
1433 I915_STATE_WARN(val & DVS_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 }
1437 }
1438
1439 static void assert_vblank_disabled(struct drm_crtc *crtc)
1440 {
1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1442 drm_crtc_vblank_put(crtc);
1443 }
1444
1445 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1446 {
1447 u32 val;
1448 bool enabled;
1449
1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1451
1452 val = I915_READ(PCH_DREF_CONTROL);
1453 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454 DREF_SUPERSPREAD_SOURCE_MASK));
1455 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1456 }
1457
1458 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
1460 {
1461 int reg;
1462 u32 val;
1463 bool enabled;
1464
1465 reg = PCH_TRANSCONF(pipe);
1466 val = I915_READ(reg);
1467 enabled = !!(val & TRANS_ENABLE);
1468 I915_STATE_WARN(enabled,
1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1470 pipe_name(pipe));
1471 }
1472
1473 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, u32 port_sel, u32 val)
1475 {
1476 if ((val & DP_PORT_EN) == 0)
1477 return false;
1478
1479 if (HAS_PCH_CPT(dev_priv->dev)) {
1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1483 return false;
1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1486 return false;
1487 } else {
1488 if ((val & DP_PIPE_MASK) != (pipe << 30))
1489 return false;
1490 }
1491 return true;
1492 }
1493
1494 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, u32 val)
1496 {
1497 if ((val & SDVO_ENABLE) == 0)
1498 return false;
1499
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1502 return false;
1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1505 return false;
1506 } else {
1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1508 return false;
1509 }
1510 return true;
1511 }
1512
1513 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe, u32 val)
1515 {
1516 if ((val & LVDS_PORT_EN) == 0)
1517 return false;
1518
1519 if (HAS_PCH_CPT(dev_priv->dev)) {
1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521 return false;
1522 } else {
1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1524 return false;
1525 }
1526 return true;
1527 }
1528
1529 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum pipe pipe, u32 val)
1531 {
1532 if ((val & ADPA_DAC_ENABLE) == 0)
1533 return false;
1534 if (HAS_PCH_CPT(dev_priv->dev)) {
1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1536 return false;
1537 } else {
1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1539 return false;
1540 }
1541 return true;
1542 }
1543
1544 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1545 enum pipe pipe, int reg, u32 port_sel)
1546 {
1547 u32 val = I915_READ(reg);
1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1550 reg, pipe_name(pipe));
1551
1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1553 && (val & DP_PIPEB_SELECT),
1554 "IBX PCH dp port still using transcoder B\n");
1555 }
1556
1557 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe, int reg)
1559 {
1560 u32 val = I915_READ(reg);
1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1563 reg, pipe_name(pipe));
1564
1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1566 && (val & SDVO_PIPE_B_SELECT),
1567 "IBX PCH hdmi port still using transcoder B\n");
1568 }
1569
1570 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1571 enum pipe pipe)
1572 {
1573 int reg;
1574 u32 val;
1575
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1579
1580 reg = PCH_ADPA;
1581 val = I915_READ(reg);
1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
1584 pipe_name(pipe));
1585
1586 reg = PCH_LVDS;
1587 val = I915_READ(reg);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void intel_init_dpio(struct drm_device *dev)
1598 {
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 if (!IS_VALLEYVIEW(dev))
1602 return;
1603
1604 /*
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1608 */
1609 if (IS_CHERRYVIEW(dev)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1612 } else {
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1614 }
1615 }
1616
1617 static void vlv_enable_pll(struct intel_crtc *crtc,
1618 const struct intel_crtc_state *pipe_config)
1619 {
1620 struct drm_device *dev = crtc->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 int reg = DPLL(crtc->pipe);
1623 u32 dpll = pipe_config->dpll_hw_state.dpll;
1624
1625 assert_pipe_disabled(dev_priv, crtc->pipe);
1626
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1629
1630 /* PLL is protected by panel, make sure we can write it */
1631 if (IS_MOBILE(dev_priv->dev))
1632 assert_panel_unlocked(dev_priv, crtc->pipe);
1633
1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150);
1637
1638 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1640
1641 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1642 POSTING_READ(DPLL_MD(crtc->pipe));
1643
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654 }
1655
1656 static void chv_enable_pll(struct intel_crtc *crtc,
1657 const struct intel_crtc_state *pipe_config)
1658 {
1659 struct drm_device *dev = crtc->base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int pipe = crtc->pipe;
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1663 u32 tmp;
1664
1665 assert_pipe_disabled(dev_priv, crtc->pipe);
1666
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1668
1669 mutex_lock(&dev_priv->sb_lock);
1670
1671 /* Enable back the 10bit clock to display controller */
1672 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673 tmp |= DPIO_DCLKP_EN;
1674 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1675
1676 mutex_unlock(&dev_priv->sb_lock);
1677
1678 /*
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 */
1681 udelay(1);
1682
1683 /* Enable PLL */
1684 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1685
1686 /* Check PLL is locked */
1687 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1688 DRM_ERROR("PLL %d failed to lock\n", pipe);
1689
1690 /* not sure when this should be written */
1691 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1692 POSTING_READ(DPLL_MD(pipe));
1693 }
1694
1695 static int intel_num_dvo_pipes(struct drm_device *dev)
1696 {
1697 struct intel_crtc *crtc;
1698 int count = 0;
1699
1700 for_each_intel_crtc(dev, crtc)
1701 count += crtc->active &&
1702 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1703
1704 return count;
1705 }
1706
1707 static void i9xx_enable_pll(struct intel_crtc *crtc)
1708 {
1709 struct drm_device *dev = crtc->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int reg = DPLL(crtc->pipe);
1712 u32 dpll = crtc->config->dpll_hw_state.dpll;
1713
1714 assert_pipe_disabled(dev_priv, crtc->pipe);
1715
1716 /* No really, not for ILK+ */
1717 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1718
1719 /* PLL is protected by panel, make sure we can write it */
1720 if (IS_MOBILE(dev) && !IS_I830(dev))
1721 assert_panel_unlocked(dev_priv, crtc->pipe);
1722
1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1725 /*
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1730 */
1731 dpll |= DPLL_DVO_2X_MODE;
1732 I915_WRITE(DPLL(!crtc->pipe),
1733 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1734 }
1735
1736 /* Wait for the clocks to stabilize. */
1737 POSTING_READ(reg);
1738 udelay(150);
1739
1740 if (INTEL_INFO(dev)->gen >= 4) {
1741 I915_WRITE(DPLL_MD(crtc->pipe),
1742 crtc->config->dpll_hw_state.dpll_md);
1743 } else {
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1746 *
1747 * So write it again.
1748 */
1749 I915_WRITE(reg, dpll);
1750 }
1751
1752 /* We do this three times for luck */
1753 I915_WRITE(reg, dpll);
1754 POSTING_READ(reg);
1755 udelay(150); /* wait for warmup */
1756 I915_WRITE(reg, dpll);
1757 POSTING_READ(reg);
1758 udelay(150); /* wait for warmup */
1759 I915_WRITE(reg, dpll);
1760 POSTING_READ(reg);
1761 udelay(150); /* wait for warmup */
1762 }
1763
1764 /**
1765 * i9xx_disable_pll - disable a PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1768 *
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1770 *
1771 * Note! This is for pre-ILK only.
1772 */
1773 static void i9xx_disable_pll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 enum pipe pipe = crtc->pipe;
1778
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1780 if (IS_I830(dev) &&
1781 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1782 intel_num_dvo_pipes(dev) == 1) {
1783 I915_WRITE(DPLL(PIPE_B),
1784 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785 I915_WRITE(DPLL(PIPE_A),
1786 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787 }
1788
1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1792 return;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 I915_WRITE(DPLL(pipe), 0);
1798 POSTING_READ(DPLL(pipe));
1799 }
1800
1801 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802 {
1803 u32 val = 0;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /*
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1811 */
1812 if (pipe == PIPE_B)
1813 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1814 I915_WRITE(DPLL(pipe), val);
1815 POSTING_READ(DPLL(pipe));
1816
1817 }
1818
1819 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1820 {
1821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1822 u32 val;
1823
1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv, pipe);
1826
1827 /* Set PLL en = 0 */
1828 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1829 if (pipe != PIPE_A)
1830 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831 I915_WRITE(DPLL(pipe), val);
1832 POSTING_READ(DPLL(pipe));
1833
1834 mutex_lock(&dev_priv->sb_lock);
1835
1836 /* Disable 10bit clock to display controller */
1837 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838 val &= ~DPIO_DCLKP_EN;
1839 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1840
1841 /* disable left/right clock distribution */
1842 if (pipe != PIPE_B) {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1846 } else {
1847 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1850 }
1851
1852 mutex_unlock(&dev_priv->sb_lock);
1853 }
1854
1855 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1856 struct intel_digital_port *dport,
1857 unsigned int expected_mask)
1858 {
1859 u32 port_mask;
1860 int dpll_reg;
1861
1862 switch (dport->port) {
1863 case PORT_B:
1864 port_mask = DPLL_PORTB_READY_MASK;
1865 dpll_reg = DPLL(0);
1866 break;
1867 case PORT_C:
1868 port_mask = DPLL_PORTC_READY_MASK;
1869 dpll_reg = DPLL(0);
1870 expected_mask <<= 4;
1871 break;
1872 case PORT_D:
1873 port_mask = DPLL_PORTD_READY_MASK;
1874 dpll_reg = DPIO_PHY_STATUS;
1875 break;
1876 default:
1877 BUG();
1878 }
1879
1880 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1883 }
1884
1885 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1886 {
1887 struct drm_device *dev = crtc->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1890
1891 if (WARN_ON(pll == NULL))
1892 return;
1893
1894 WARN_ON(!pll->config.crtc_mask);
1895 if (pll->active == 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1897 WARN_ON(pll->on);
1898 assert_shared_dpll_disabled(dev_priv, pll);
1899
1900 pll->mode_set(dev_priv, pll);
1901 }
1902 }
1903
1904 /**
1905 * intel_enable_shared_dpll - enable PCH PLL
1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1908 *
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1911 */
1912 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1913 {
1914 struct drm_device *dev = crtc->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
1916 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1917
1918 if (WARN_ON(pll == NULL))
1919 return;
1920
1921 if (WARN_ON(pll->config.crtc_mask == 0))
1922 return;
1923
1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1925 pll->name, pll->active, pll->on,
1926 crtc->base.base.id);
1927
1928 if (pll->active++) {
1929 WARN_ON(!pll->on);
1930 assert_shared_dpll_enabled(dev_priv, pll);
1931 return;
1932 }
1933 WARN_ON(pll->on);
1934
1935 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1936
1937 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1938 pll->enable(dev_priv, pll);
1939 pll->on = true;
1940 }
1941
1942 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1943 {
1944 struct drm_device *dev = crtc->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1947
1948 /* PCH only available on ILK+ */
1949 BUG_ON(INTEL_INFO(dev)->gen < 5);
1950 if (WARN_ON(pll == NULL))
1951 return;
1952
1953 if (WARN_ON(pll->config.crtc_mask == 0))
1954 return;
1955
1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll->name, pll->active, pll->on,
1958 crtc->base.base.id);
1959
1960 if (WARN_ON(pll->active == 0)) {
1961 assert_shared_dpll_disabled(dev_priv, pll);
1962 return;
1963 }
1964
1965 assert_shared_dpll_enabled(dev_priv, pll);
1966 WARN_ON(!pll->on);
1967 if (--pll->active)
1968 return;
1969
1970 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1971 pll->disable(dev_priv, pll);
1972 pll->on = false;
1973
1974 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1975 }
1976
1977 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1978 enum pipe pipe)
1979 {
1980 struct drm_device *dev = dev_priv->dev;
1981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 uint32_t reg, val, pipeconf_val;
1984
1985 /* PCH only available on ILK+ */
1986 BUG_ON(!HAS_PCH_SPLIT(dev));
1987
1988 /* Make sure PCH DPLL is enabled */
1989 assert_shared_dpll_enabled(dev_priv,
1990 intel_crtc_to_shared_dpll(intel_crtc));
1991
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv, pipe);
1994 assert_fdi_rx_enabled(dev_priv, pipe);
1995
1996 if (HAS_PCH_CPT(dev)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg = TRANS_CHICKEN2(pipe);
2000 val = I915_READ(reg);
2001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002 I915_WRITE(reg, val);
2003 }
2004
2005 reg = PCH_TRANSCONF(pipe);
2006 val = I915_READ(reg);
2007 pipeconf_val = I915_READ(PIPECONF(pipe));
2008
2009 if (HAS_PCH_IBX(dev_priv->dev)) {
2010 /*
2011 * make the BPC in transcoder be consistent with
2012 * that in pipeconf reg.
2013 */
2014 val &= ~PIPECONF_BPC_MASK;
2015 val |= pipeconf_val & PIPECONF_BPC_MASK;
2016 }
2017
2018 val &= ~TRANS_INTERLACE_MASK;
2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2020 if (HAS_PCH_IBX(dev_priv->dev) &&
2021 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2022 val |= TRANS_LEGACY_INTERLACED_ILK;
2023 else
2024 val |= TRANS_INTERLACED;
2025 else
2026 val |= TRANS_PROGRESSIVE;
2027
2028 I915_WRITE(reg, val | TRANS_ENABLE);
2029 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2030 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2031 }
2032
2033 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2034 enum transcoder cpu_transcoder)
2035 {
2036 u32 val, pipeconf_val;
2037
2038 /* PCH only available on ILK+ */
2039 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2040
2041 /* FDI must be feeding us bits for PCH ports */
2042 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2043 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2044
2045 /* Workaround: set timing override bit. */
2046 val = I915_READ(_TRANSA_CHICKEN2);
2047 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2048 I915_WRITE(_TRANSA_CHICKEN2, val);
2049
2050 val = TRANS_ENABLE;
2051 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2052
2053 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2054 PIPECONF_INTERLACED_ILK)
2055 val |= TRANS_INTERLACED;
2056 else
2057 val |= TRANS_PROGRESSIVE;
2058
2059 I915_WRITE(LPT_TRANSCONF, val);
2060 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2061 DRM_ERROR("Failed to enable PCH transcoder\n");
2062 }
2063
2064 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2065 enum pipe pipe)
2066 {
2067 struct drm_device *dev = dev_priv->dev;
2068 uint32_t reg, val;
2069
2070 /* FDI relies on the transcoder */
2071 assert_fdi_tx_disabled(dev_priv, pipe);
2072 assert_fdi_rx_disabled(dev_priv, pipe);
2073
2074 /* Ports must be off as well */
2075 assert_pch_ports_disabled(dev_priv, pipe);
2076
2077 reg = PCH_TRANSCONF(pipe);
2078 val = I915_READ(reg);
2079 val &= ~TRANS_ENABLE;
2080 I915_WRITE(reg, val);
2081 /* wait for PCH transcoder off, transcoder state */
2082 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2083 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2084
2085 if (!HAS_PCH_IBX(dev)) {
2086 /* Workaround: Clear the timing override chicken bit again. */
2087 reg = TRANS_CHICKEN2(pipe);
2088 val = I915_READ(reg);
2089 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090 I915_WRITE(reg, val);
2091 }
2092 }
2093
2094 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2095 {
2096 u32 val;
2097
2098 val = I915_READ(LPT_TRANSCONF);
2099 val &= ~TRANS_ENABLE;
2100 I915_WRITE(LPT_TRANSCONF, val);
2101 /* wait for PCH transcoder off, transcoder state */
2102 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2103 DRM_ERROR("Failed to disable PCH transcoder\n");
2104
2105 /* Workaround: clear timing override bit. */
2106 val = I915_READ(_TRANSA_CHICKEN2);
2107 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2108 I915_WRITE(_TRANSA_CHICKEN2, val);
2109 }
2110
2111 /**
2112 * intel_enable_pipe - enable a pipe, asserting requirements
2113 * @crtc: crtc responsible for the pipe
2114 *
2115 * Enable @crtc's pipe, making sure that various hardware specific requirements
2116 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2117 */
2118 static void intel_enable_pipe(struct intel_crtc *crtc)
2119 {
2120 struct drm_device *dev = crtc->base.dev;
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 enum pipe pipe = crtc->pipe;
2123 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2124 pipe);
2125 enum pipe pch_transcoder;
2126 int reg;
2127 u32 val;
2128
2129 assert_planes_disabled(dev_priv, pipe);
2130 assert_cursor_disabled(dev_priv, pipe);
2131 assert_sprites_disabled(dev_priv, pipe);
2132
2133 if (HAS_PCH_LPT(dev_priv->dev))
2134 pch_transcoder = TRANSCODER_A;
2135 else
2136 pch_transcoder = pipe;
2137
2138 /*
2139 * A pipe without a PLL won't actually be able to drive bits from
2140 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2141 * need the check.
2142 */
2143 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2144 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2145 assert_dsi_pll_enabled(dev_priv);
2146 else
2147 assert_pll_enabled(dev_priv, pipe);
2148 else {
2149 if (crtc->config->has_pch_encoder) {
2150 /* if driving the PCH, we need FDI enabled */
2151 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2152 assert_fdi_tx_pll_enabled(dev_priv,
2153 (enum pipe) cpu_transcoder);
2154 }
2155 /* FIXME: assert CPU port conditions for SNB+ */
2156 }
2157
2158 reg = PIPECONF(cpu_transcoder);
2159 val = I915_READ(reg);
2160 if (val & PIPECONF_ENABLE) {
2161 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2162 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2163 return;
2164 }
2165
2166 I915_WRITE(reg, val | PIPECONF_ENABLE);
2167 POSTING_READ(reg);
2168 }
2169
2170 /**
2171 * intel_disable_pipe - disable a pipe, asserting requirements
2172 * @crtc: crtc whose pipes is to be disabled
2173 *
2174 * Disable the pipe of @crtc, making sure that various hardware
2175 * specific requirements are met, if applicable, e.g. plane
2176 * disabled, panel fitter off, etc.
2177 *
2178 * Will wait until the pipe has shut down before returning.
2179 */
2180 static void intel_disable_pipe(struct intel_crtc *crtc)
2181 {
2182 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2183 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2184 enum pipe pipe = crtc->pipe;
2185 int reg;
2186 u32 val;
2187
2188 /*
2189 * Make sure planes won't keep trying to pump pixels to us,
2190 * or we might hang the display.
2191 */
2192 assert_planes_disabled(dev_priv, pipe);
2193 assert_cursor_disabled(dev_priv, pipe);
2194 assert_sprites_disabled(dev_priv, pipe);
2195
2196 reg = PIPECONF(cpu_transcoder);
2197 val = I915_READ(reg);
2198 if ((val & PIPECONF_ENABLE) == 0)
2199 return;
2200
2201 /*
2202 * Double wide has implications for planes
2203 * so best keep it disabled when not needed.
2204 */
2205 if (crtc->config->double_wide)
2206 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208 /* Don't disable pipe or pipe PLLs if needed */
2209 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211 val &= ~PIPECONF_ENABLE;
2212
2213 I915_WRITE(reg, val);
2214 if ((val & PIPECONF_ENABLE) == 0)
2215 intel_wait_for_pipe_off(crtc);
2216 }
2217
2218 /**
2219 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2220 * @plane: plane to be enabled
2221 * @crtc: crtc for the plane
2222 *
2223 * Enable @plane on @crtc, making sure that the pipe is running first.
2224 */
2225 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2226 struct drm_crtc *crtc)
2227 {
2228 struct drm_device *dev = plane->dev;
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2231
2232 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2233 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2234 to_intel_plane_state(plane->state)->visible = true;
2235
2236 dev_priv->display.update_primary_plane(crtc, plane->fb,
2237 crtc->x, crtc->y);
2238 }
2239
2240 static bool need_vtd_wa(struct drm_device *dev)
2241 {
2242 #ifdef CONFIG_INTEL_IOMMU
2243 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2244 return true;
2245 #endif
2246 return false;
2247 }
2248
2249 unsigned int
2250 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2251 uint64_t fb_format_modifier)
2252 {
2253 unsigned int tile_height;
2254 uint32_t pixel_bytes;
2255
2256 switch (fb_format_modifier) {
2257 case DRM_FORMAT_MOD_NONE:
2258 tile_height = 1;
2259 break;
2260 case I915_FORMAT_MOD_X_TILED:
2261 tile_height = IS_GEN2(dev) ? 16 : 8;
2262 break;
2263 case I915_FORMAT_MOD_Y_TILED:
2264 tile_height = 32;
2265 break;
2266 case I915_FORMAT_MOD_Yf_TILED:
2267 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2268 switch (pixel_bytes) {
2269 default:
2270 case 1:
2271 tile_height = 64;
2272 break;
2273 case 2:
2274 case 4:
2275 tile_height = 32;
2276 break;
2277 case 8:
2278 tile_height = 16;
2279 break;
2280 case 16:
2281 WARN_ONCE(1,
2282 "128-bit pixels are not supported for display!");
2283 tile_height = 16;
2284 break;
2285 }
2286 break;
2287 default:
2288 MISSING_CASE(fb_format_modifier);
2289 tile_height = 1;
2290 break;
2291 }
2292
2293 return tile_height;
2294 }
2295
2296 unsigned int
2297 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2298 uint32_t pixel_format, uint64_t fb_format_modifier)
2299 {
2300 return ALIGN(height, intel_tile_height(dev, pixel_format,
2301 fb_format_modifier));
2302 }
2303
2304 static int
2305 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2306 const struct drm_plane_state *plane_state)
2307 {
2308 struct intel_rotation_info *info = &view->rotation_info;
2309
2310 *view = i915_ggtt_view_normal;
2311
2312 if (!plane_state)
2313 return 0;
2314
2315 if (!intel_rotation_90_or_270(plane_state->rotation))
2316 return 0;
2317
2318 *view = i915_ggtt_view_rotated;
2319
2320 info->height = fb->height;
2321 info->pixel_format = fb->pixel_format;
2322 info->pitch = fb->pitches[0];
2323 info->fb_modifier = fb->modifier[0];
2324
2325 return 0;
2326 }
2327
2328 int
2329 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2330 struct drm_framebuffer *fb,
2331 const struct drm_plane_state *plane_state,
2332 struct intel_engine_cs *pipelined)
2333 {
2334 struct drm_device *dev = fb->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337 struct i915_ggtt_view view;
2338 u32 alignment;
2339 int ret;
2340
2341 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
2343 switch (fb->modifier[0]) {
2344 case DRM_FORMAT_MOD_NONE:
2345 if (INTEL_INFO(dev)->gen >= 9)
2346 alignment = 256 * 1024;
2347 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2348 alignment = 128 * 1024;
2349 else if (INTEL_INFO(dev)->gen >= 4)
2350 alignment = 4 * 1024;
2351 else
2352 alignment = 64 * 1024;
2353 break;
2354 case I915_FORMAT_MOD_X_TILED:
2355 if (INTEL_INFO(dev)->gen >= 9)
2356 alignment = 256 * 1024;
2357 else {
2358 /* pin() will align the object as required by fence */
2359 alignment = 0;
2360 }
2361 break;
2362 case I915_FORMAT_MOD_Y_TILED:
2363 case I915_FORMAT_MOD_Yf_TILED:
2364 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2365 "Y tiling bo slipped through, driver bug!\n"))
2366 return -EINVAL;
2367 alignment = 1 * 1024 * 1024;
2368 break;
2369 default:
2370 MISSING_CASE(fb->modifier[0]);
2371 return -EINVAL;
2372 }
2373
2374 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2375 if (ret)
2376 return ret;
2377
2378 /* Note that the w/a also requires 64 PTE of padding following the
2379 * bo. We currently fill all unused PTE with the shadow page and so
2380 * we should always have valid PTE following the scanout preventing
2381 * the VT-d warning.
2382 */
2383 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2384 alignment = 256 * 1024;
2385
2386 /*
2387 * Global gtt pte registers are special registers which actually forward
2388 * writes to a chunk of system memory. Which means that there is no risk
2389 * that the register values disappear as soon as we call
2390 * intel_runtime_pm_put(), so it is correct to wrap only the
2391 * pin/unpin/fence and not more.
2392 */
2393 intel_runtime_pm_get(dev_priv);
2394
2395 dev_priv->mm.interruptible = false;
2396 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2397 &view);
2398 if (ret)
2399 goto err_interruptible;
2400
2401 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2402 * fence, whereas 965+ only requires a fence if using
2403 * framebuffer compression. For simplicity, we always install
2404 * a fence as the cost is not that onerous.
2405 */
2406 ret = i915_gem_object_get_fence(obj);
2407 if (ret)
2408 goto err_unpin;
2409
2410 i915_gem_object_pin_fence(obj);
2411
2412 dev_priv->mm.interruptible = true;
2413 intel_runtime_pm_put(dev_priv);
2414 return 0;
2415
2416 err_unpin:
2417 i915_gem_object_unpin_from_display_plane(obj, &view);
2418 err_interruptible:
2419 dev_priv->mm.interruptible = true;
2420 intel_runtime_pm_put(dev_priv);
2421 return ret;
2422 }
2423
2424 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425 const struct drm_plane_state *plane_state)
2426 {
2427 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2428 struct i915_ggtt_view view;
2429 int ret;
2430
2431 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2432
2433 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2434 WARN_ONCE(ret, "Couldn't get view from plane state!");
2435
2436 i915_gem_object_unpin_fence(obj);
2437 i915_gem_object_unpin_from_display_plane(obj, &view);
2438 }
2439
2440 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441 * is assumed to be a power-of-two. */
2442 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2443 unsigned int tiling_mode,
2444 unsigned int cpp,
2445 unsigned int pitch)
2446 {
2447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
2449
2450 tile_rows = *y / 8;
2451 *y %= 8;
2452
2453 tiles = *x / (512/cpp);
2454 *x %= 512/cpp;
2455
2456 return tile_rows * pitch * 8 + tiles * 4096;
2457 } else {
2458 unsigned int offset;
2459
2460 offset = *y * pitch + *x * cpp;
2461 *y = 0;
2462 *x = (offset & 4095) / cpp;
2463 return offset & -4096;
2464 }
2465 }
2466
2467 static int i9xx_format_to_fourcc(int format)
2468 {
2469 switch (format) {
2470 case DISPPLANE_8BPP:
2471 return DRM_FORMAT_C8;
2472 case DISPPLANE_BGRX555:
2473 return DRM_FORMAT_XRGB1555;
2474 case DISPPLANE_BGRX565:
2475 return DRM_FORMAT_RGB565;
2476 default:
2477 case DISPPLANE_BGRX888:
2478 return DRM_FORMAT_XRGB8888;
2479 case DISPPLANE_RGBX888:
2480 return DRM_FORMAT_XBGR8888;
2481 case DISPPLANE_BGRX101010:
2482 return DRM_FORMAT_XRGB2101010;
2483 case DISPPLANE_RGBX101010:
2484 return DRM_FORMAT_XBGR2101010;
2485 }
2486 }
2487
2488 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2489 {
2490 switch (format) {
2491 case PLANE_CTL_FORMAT_RGB_565:
2492 return DRM_FORMAT_RGB565;
2493 default:
2494 case PLANE_CTL_FORMAT_XRGB_8888:
2495 if (rgb_order) {
2496 if (alpha)
2497 return DRM_FORMAT_ABGR8888;
2498 else
2499 return DRM_FORMAT_XBGR8888;
2500 } else {
2501 if (alpha)
2502 return DRM_FORMAT_ARGB8888;
2503 else
2504 return DRM_FORMAT_XRGB8888;
2505 }
2506 case PLANE_CTL_FORMAT_XRGB_2101010:
2507 if (rgb_order)
2508 return DRM_FORMAT_XBGR2101010;
2509 else
2510 return DRM_FORMAT_XRGB2101010;
2511 }
2512 }
2513
2514 static bool
2515 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2516 struct intel_initial_plane_config *plane_config)
2517 {
2518 struct drm_device *dev = crtc->base.dev;
2519 struct drm_i915_gem_object *obj = NULL;
2520 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2521 struct drm_framebuffer *fb = &plane_config->fb->base;
2522 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2523 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2524 PAGE_SIZE);
2525
2526 size_aligned -= base_aligned;
2527
2528 if (plane_config->size == 0)
2529 return false;
2530
2531 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2532 base_aligned,
2533 base_aligned,
2534 size_aligned);
2535 if (!obj)
2536 return false;
2537
2538 obj->tiling_mode = plane_config->tiling;
2539 if (obj->tiling_mode == I915_TILING_X)
2540 obj->stride = fb->pitches[0];
2541
2542 mode_cmd.pixel_format = fb->pixel_format;
2543 mode_cmd.width = fb->width;
2544 mode_cmd.height = fb->height;
2545 mode_cmd.pitches[0] = fb->pitches[0];
2546 mode_cmd.modifier[0] = fb->modifier[0];
2547 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2548
2549 mutex_lock(&dev->struct_mutex);
2550 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2551 &mode_cmd, obj)) {
2552 DRM_DEBUG_KMS("intel fb init failed\n");
2553 goto out_unref_obj;
2554 }
2555 mutex_unlock(&dev->struct_mutex);
2556
2557 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2558 return true;
2559
2560 out_unref_obj:
2561 drm_gem_object_unreference(&obj->base);
2562 mutex_unlock(&dev->struct_mutex);
2563 return false;
2564 }
2565
2566 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2567 static void
2568 update_state_fb(struct drm_plane *plane)
2569 {
2570 if (plane->fb == plane->state->fb)
2571 return;
2572
2573 if (plane->state->fb)
2574 drm_framebuffer_unreference(plane->state->fb);
2575 plane->state->fb = plane->fb;
2576 if (plane->state->fb)
2577 drm_framebuffer_reference(plane->state->fb);
2578 }
2579
2580 static void
2581 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2582 struct intel_initial_plane_config *plane_config)
2583 {
2584 struct drm_device *dev = intel_crtc->base.dev;
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct drm_crtc *c;
2587 struct intel_crtc *i;
2588 struct drm_i915_gem_object *obj;
2589 struct drm_plane *primary = intel_crtc->base.primary;
2590 struct drm_framebuffer *fb;
2591
2592 if (!plane_config->fb)
2593 return;
2594
2595 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2596 fb = &plane_config->fb->base;
2597 goto valid_fb;
2598 }
2599
2600 kfree(plane_config->fb);
2601
2602 /*
2603 * Failed to alloc the obj, check to see if we should share
2604 * an fb with another CRTC instead
2605 */
2606 for_each_crtc(dev, c) {
2607 i = to_intel_crtc(c);
2608
2609 if (c == &intel_crtc->base)
2610 continue;
2611
2612 if (!i->active)
2613 continue;
2614
2615 fb = c->primary->fb;
2616 if (!fb)
2617 continue;
2618
2619 obj = intel_fb_obj(fb);
2620 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2621 drm_framebuffer_reference(fb);
2622 goto valid_fb;
2623 }
2624 }
2625
2626 return;
2627
2628 valid_fb:
2629 obj = intel_fb_obj(fb);
2630 if (obj->tiling_mode != I915_TILING_NONE)
2631 dev_priv->preserve_bios_swizzle = true;
2632
2633 primary->fb = fb;
2634 primary->crtc = primary->state->crtc = &intel_crtc->base;
2635 update_state_fb(primary);
2636 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2637 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2638 }
2639
2640 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2641 struct drm_framebuffer *fb,
2642 int x, int y)
2643 {
2644 struct drm_device *dev = crtc->dev;
2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2647 struct drm_plane *primary = crtc->primary;
2648 bool visible = to_intel_plane_state(primary->state)->visible;
2649 struct drm_i915_gem_object *obj;
2650 int plane = intel_crtc->plane;
2651 unsigned long linear_offset;
2652 u32 dspcntr;
2653 u32 reg = DSPCNTR(plane);
2654 int pixel_size;
2655
2656 if (!visible || !fb) {
2657 I915_WRITE(reg, 0);
2658 if (INTEL_INFO(dev)->gen >= 4)
2659 I915_WRITE(DSPSURF(plane), 0);
2660 else
2661 I915_WRITE(DSPADDR(plane), 0);
2662 POSTING_READ(reg);
2663 return;
2664 }
2665
2666 obj = intel_fb_obj(fb);
2667 if (WARN_ON(obj == NULL))
2668 return;
2669
2670 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2671
2672 dspcntr = DISPPLANE_GAMMA_ENABLE;
2673
2674 dspcntr |= DISPLAY_PLANE_ENABLE;
2675
2676 if (INTEL_INFO(dev)->gen < 4) {
2677 if (intel_crtc->pipe == PIPE_B)
2678 dspcntr |= DISPPLANE_SEL_PIPE_B;
2679
2680 /* pipesrc and dspsize control the size that is scaled from,
2681 * which should always be the user's requested size.
2682 */
2683 I915_WRITE(DSPSIZE(plane),
2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
2686 I915_WRITE(DSPPOS(plane), 0);
2687 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2688 I915_WRITE(PRIMSIZE(plane),
2689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
2691 I915_WRITE(PRIMPOS(plane), 0);
2692 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2693 }
2694
2695 switch (fb->pixel_format) {
2696 case DRM_FORMAT_C8:
2697 dspcntr |= DISPPLANE_8BPP;
2698 break;
2699 case DRM_FORMAT_XRGB1555:
2700 dspcntr |= DISPPLANE_BGRX555;
2701 break;
2702 case DRM_FORMAT_RGB565:
2703 dspcntr |= DISPPLANE_BGRX565;
2704 break;
2705 case DRM_FORMAT_XRGB8888:
2706 dspcntr |= DISPPLANE_BGRX888;
2707 break;
2708 case DRM_FORMAT_XBGR8888:
2709 dspcntr |= DISPPLANE_RGBX888;
2710 break;
2711 case DRM_FORMAT_XRGB2101010:
2712 dspcntr |= DISPPLANE_BGRX101010;
2713 break;
2714 case DRM_FORMAT_XBGR2101010:
2715 dspcntr |= DISPPLANE_RGBX101010;
2716 break;
2717 default:
2718 BUG();
2719 }
2720
2721 if (INTEL_INFO(dev)->gen >= 4 &&
2722 obj->tiling_mode != I915_TILING_NONE)
2723 dspcntr |= DISPPLANE_TILED;
2724
2725 if (IS_G4X(dev))
2726 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2727
2728 linear_offset = y * fb->pitches[0] + x * pixel_size;
2729
2730 if (INTEL_INFO(dev)->gen >= 4) {
2731 intel_crtc->dspaddr_offset =
2732 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2733 pixel_size,
2734 fb->pitches[0]);
2735 linear_offset -= intel_crtc->dspaddr_offset;
2736 } else {
2737 intel_crtc->dspaddr_offset = linear_offset;
2738 }
2739
2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2741 dspcntr |= DISPPLANE_ROTATE_180;
2742
2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
2745
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2748 linear_offset +=
2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2751 }
2752
2753 I915_WRITE(reg, dspcntr);
2754
2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
2761 } else
2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2763 POSTING_READ(reg);
2764 }
2765
2766 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2768 int x, int y)
2769 {
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 struct drm_plane *primary = crtc->primary;
2774 bool visible = to_intel_plane_state(primary->state)->visible;
2775 struct drm_i915_gem_object *obj;
2776 int plane = intel_crtc->plane;
2777 unsigned long linear_offset;
2778 u32 dspcntr;
2779 u32 reg = DSPCNTR(plane);
2780 int pixel_size;
2781
2782 if (!visible || !fb) {
2783 I915_WRITE(reg, 0);
2784 I915_WRITE(DSPSURF(plane), 0);
2785 POSTING_READ(reg);
2786 return;
2787 }
2788
2789 obj = intel_fb_obj(fb);
2790 if (WARN_ON(obj == NULL))
2791 return;
2792
2793 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2794
2795 dspcntr = DISPPLANE_GAMMA_ENABLE;
2796
2797 dspcntr |= DISPLAY_PLANE_ENABLE;
2798
2799 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2801
2802 switch (fb->pixel_format) {
2803 case DRM_FORMAT_C8:
2804 dspcntr |= DISPPLANE_8BPP;
2805 break;
2806 case DRM_FORMAT_RGB565:
2807 dspcntr |= DISPPLANE_BGRX565;
2808 break;
2809 case DRM_FORMAT_XRGB8888:
2810 dspcntr |= DISPPLANE_BGRX888;
2811 break;
2812 case DRM_FORMAT_XBGR8888:
2813 dspcntr |= DISPPLANE_RGBX888;
2814 break;
2815 case DRM_FORMAT_XRGB2101010:
2816 dspcntr |= DISPPLANE_BGRX101010;
2817 break;
2818 case DRM_FORMAT_XBGR2101010:
2819 dspcntr |= DISPPLANE_RGBX101010;
2820 break;
2821 default:
2822 BUG();
2823 }
2824
2825 if (obj->tiling_mode != I915_TILING_NONE)
2826 dspcntr |= DISPPLANE_TILED;
2827
2828 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2829 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2830
2831 linear_offset = y * fb->pitches[0] + x * pixel_size;
2832 intel_crtc->dspaddr_offset =
2833 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2834 pixel_size,
2835 fb->pitches[0]);
2836 linear_offset -= intel_crtc->dspaddr_offset;
2837 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2838 dspcntr |= DISPPLANE_ROTATE_180;
2839
2840 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2841 x += (intel_crtc->config->pipe_src_w - 1);
2842 y += (intel_crtc->config->pipe_src_h - 1);
2843
2844 /* Finding the last pixel of the last line of the display
2845 data and adding to linear_offset*/
2846 linear_offset +=
2847 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2848 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2849 }
2850 }
2851
2852 I915_WRITE(reg, dspcntr);
2853
2854 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2855 I915_WRITE(DSPSURF(plane),
2856 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2857 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2858 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2859 } else {
2860 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2861 I915_WRITE(DSPLINOFF(plane), linear_offset);
2862 }
2863 POSTING_READ(reg);
2864 }
2865
2866 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2867 uint32_t pixel_format)
2868 {
2869 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2870
2871 /*
2872 * The stride is either expressed as a multiple of 64 bytes
2873 * chunks for linear buffers or in number of tiles for tiled
2874 * buffers.
2875 */
2876 switch (fb_modifier) {
2877 case DRM_FORMAT_MOD_NONE:
2878 return 64;
2879 case I915_FORMAT_MOD_X_TILED:
2880 if (INTEL_INFO(dev)->gen == 2)
2881 return 128;
2882 return 512;
2883 case I915_FORMAT_MOD_Y_TILED:
2884 /* No need to check for old gens and Y tiling since this is
2885 * about the display engine and those will be blocked before
2886 * we get here.
2887 */
2888 return 128;
2889 case I915_FORMAT_MOD_Yf_TILED:
2890 if (bits_per_pixel == 8)
2891 return 64;
2892 else
2893 return 128;
2894 default:
2895 MISSING_CASE(fb_modifier);
2896 return 64;
2897 }
2898 }
2899
2900 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2901 struct drm_i915_gem_object *obj)
2902 {
2903 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2904
2905 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2906 view = &i915_ggtt_view_rotated;
2907
2908 return i915_gem_obj_ggtt_offset_view(obj, view);
2909 }
2910
2911 /*
2912 * This function detaches (aka. unbinds) unused scalers in hardware
2913 */
2914 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2915 {
2916 struct drm_device *dev;
2917 struct drm_i915_private *dev_priv;
2918 struct intel_crtc_scaler_state *scaler_state;
2919 int i;
2920
2921 if (!intel_crtc || !intel_crtc->config)
2922 return;
2923
2924 dev = intel_crtc->base.dev;
2925 dev_priv = dev->dev_private;
2926 scaler_state = &intel_crtc->config->scaler_state;
2927
2928 /* loop through and disable scalers that aren't in use */
2929 for (i = 0; i < intel_crtc->num_scalers; i++) {
2930 if (!scaler_state->scalers[i].in_use) {
2931 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2932 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2933 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2934 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2935 intel_crtc->base.base.id, intel_crtc->pipe, i);
2936 }
2937 }
2938 }
2939
2940 u32 skl_plane_ctl_format(uint32_t pixel_format)
2941 {
2942 switch (pixel_format) {
2943 case DRM_FORMAT_C8:
2944 return PLANE_CTL_FORMAT_INDEXED;
2945 case DRM_FORMAT_RGB565:
2946 return PLANE_CTL_FORMAT_RGB_565;
2947 case DRM_FORMAT_XBGR8888:
2948 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2949 case DRM_FORMAT_XRGB8888:
2950 return PLANE_CTL_FORMAT_XRGB_8888;
2951 /*
2952 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2953 * to be already pre-multiplied. We need to add a knob (or a different
2954 * DRM_FORMAT) for user-space to configure that.
2955 */
2956 case DRM_FORMAT_ABGR8888:
2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2958 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2959 case DRM_FORMAT_ARGB8888:
2960 return PLANE_CTL_FORMAT_XRGB_8888 |
2961 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2962 case DRM_FORMAT_XRGB2101010:
2963 return PLANE_CTL_FORMAT_XRGB_2101010;
2964 case DRM_FORMAT_XBGR2101010:
2965 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2966 case DRM_FORMAT_YUYV:
2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2968 case DRM_FORMAT_YVYU:
2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2970 case DRM_FORMAT_UYVY:
2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2972 case DRM_FORMAT_VYUY:
2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2974 default:
2975 MISSING_CASE(pixel_format);
2976 }
2977
2978 return 0;
2979 }
2980
2981 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2982 {
2983 switch (fb_modifier) {
2984 case DRM_FORMAT_MOD_NONE:
2985 break;
2986 case I915_FORMAT_MOD_X_TILED:
2987 return PLANE_CTL_TILED_X;
2988 case I915_FORMAT_MOD_Y_TILED:
2989 return PLANE_CTL_TILED_Y;
2990 case I915_FORMAT_MOD_Yf_TILED:
2991 return PLANE_CTL_TILED_YF;
2992 default:
2993 MISSING_CASE(fb_modifier);
2994 }
2995
2996 return 0;
2997 }
2998
2999 u32 skl_plane_ctl_rotation(unsigned int rotation)
3000 {
3001 switch (rotation) {
3002 case BIT(DRM_ROTATE_0):
3003 break;
3004 /*
3005 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3006 * while i915 HW rotation is clockwise, thats why this swapping.
3007 */
3008 case BIT(DRM_ROTATE_90):
3009 return PLANE_CTL_ROTATE_270;
3010 case BIT(DRM_ROTATE_180):
3011 return PLANE_CTL_ROTATE_180;
3012 case BIT(DRM_ROTATE_270):
3013 return PLANE_CTL_ROTATE_90;
3014 default:
3015 MISSING_CASE(rotation);
3016 }
3017
3018 return 0;
3019 }
3020
3021 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3022 struct drm_framebuffer *fb,
3023 int x, int y)
3024 {
3025 struct drm_device *dev = crtc->dev;
3026 struct drm_i915_private *dev_priv = dev->dev_private;
3027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3028 struct drm_plane *plane = crtc->primary;
3029 bool visible = to_intel_plane_state(plane->state)->visible;
3030 struct drm_i915_gem_object *obj;
3031 int pipe = intel_crtc->pipe;
3032 u32 plane_ctl, stride_div, stride;
3033 u32 tile_height, plane_offset, plane_size;
3034 unsigned int rotation;
3035 int x_offset, y_offset;
3036 unsigned long surf_addr;
3037 struct intel_crtc_state *crtc_state = intel_crtc->config;
3038 struct intel_plane_state *plane_state;
3039 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3040 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3041 int scaler_id = -1;
3042
3043 plane_state = to_intel_plane_state(plane->state);
3044
3045 if (!visible || !fb) {
3046 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3047 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3048 POSTING_READ(PLANE_CTL(pipe, 0));
3049 return;
3050 }
3051
3052 plane_ctl = PLANE_CTL_ENABLE |
3053 PLANE_CTL_PIPE_GAMMA_ENABLE |
3054 PLANE_CTL_PIPE_CSC_ENABLE;
3055
3056 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3057 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3058 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3059
3060 rotation = plane->state->rotation;
3061 plane_ctl |= skl_plane_ctl_rotation(rotation);
3062
3063 obj = intel_fb_obj(fb);
3064 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3065 fb->pixel_format);
3066 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3067
3068 /*
3069 * FIXME: intel_plane_state->src, dst aren't set when transitional
3070 * update_plane helpers are called from legacy paths.
3071 * Once full atomic crtc is available, below check can be avoided.
3072 */
3073 if (drm_rect_width(&plane_state->src)) {
3074 scaler_id = plane_state->scaler_id;
3075 src_x = plane_state->src.x1 >> 16;
3076 src_y = plane_state->src.y1 >> 16;
3077 src_w = drm_rect_width(&plane_state->src) >> 16;
3078 src_h = drm_rect_height(&plane_state->src) >> 16;
3079 dst_x = plane_state->dst.x1;
3080 dst_y = plane_state->dst.y1;
3081 dst_w = drm_rect_width(&plane_state->dst);
3082 dst_h = drm_rect_height(&plane_state->dst);
3083
3084 WARN_ON(x != src_x || y != src_y);
3085 } else {
3086 src_w = intel_crtc->config->pipe_src_w;
3087 src_h = intel_crtc->config->pipe_src_h;
3088 }
3089
3090 if (intel_rotation_90_or_270(rotation)) {
3091 /* stride = Surface height in tiles */
3092 tile_height = intel_tile_height(dev, fb->pixel_format,
3093 fb->modifier[0]);
3094 stride = DIV_ROUND_UP(fb->height, tile_height);
3095 x_offset = stride * tile_height - y - src_h;
3096 y_offset = x;
3097 plane_size = (src_w - 1) << 16 | (src_h - 1);
3098 } else {
3099 stride = fb->pitches[0] / stride_div;
3100 x_offset = x;
3101 y_offset = y;
3102 plane_size = (src_h - 1) << 16 | (src_w - 1);
3103 }
3104 plane_offset = y_offset << 16 | x_offset;
3105
3106 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3107 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3108 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3109 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3110
3111 if (scaler_id >= 0) {
3112 uint32_t ps_ctrl = 0;
3113
3114 WARN_ON(!dst_w || !dst_h);
3115 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3116 crtc_state->scaler_state.scalers[scaler_id].mode;
3117 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3118 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3119 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3120 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3121 I915_WRITE(PLANE_POS(pipe, 0), 0);
3122 } else {
3123 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3124 }
3125
3126 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3127
3128 POSTING_READ(PLANE_SURF(pipe, 0));
3129 }
3130
3131 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3132 static int
3133 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3134 int x, int y, enum mode_set_atomic state)
3135 {
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138
3139 if (dev_priv->display.disable_fbc)
3140 dev_priv->display.disable_fbc(dev);
3141
3142 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3143
3144 return 0;
3145 }
3146
3147 static void intel_complete_page_flips(struct drm_device *dev)
3148 {
3149 struct drm_crtc *crtc;
3150
3151 for_each_crtc(dev, crtc) {
3152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3153 enum plane plane = intel_crtc->plane;
3154
3155 intel_prepare_page_flip(dev, plane);
3156 intel_finish_page_flip_plane(dev, plane);
3157 }
3158 }
3159
3160 static void intel_update_primary_planes(struct drm_device *dev)
3161 {
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163 struct drm_crtc *crtc;
3164
3165 for_each_crtc(dev, crtc) {
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167
3168 drm_modeset_lock(&crtc->mutex, NULL);
3169 /*
3170 * FIXME: Once we have proper support for primary planes (and
3171 * disabling them without disabling the entire crtc) allow again
3172 * a NULL crtc->primary->fb.
3173 */
3174 if (intel_crtc->active && crtc->primary->fb)
3175 dev_priv->display.update_primary_plane(crtc,
3176 crtc->primary->fb,
3177 crtc->x,
3178 crtc->y);
3179 drm_modeset_unlock(&crtc->mutex);
3180 }
3181 }
3182
3183 void intel_prepare_reset(struct drm_device *dev)
3184 {
3185 /* no reset support for gen2 */
3186 if (IS_GEN2(dev))
3187 return;
3188
3189 /* reset doesn't touch the display */
3190 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3191 return;
3192
3193 drm_modeset_lock_all(dev);
3194 /*
3195 * Disabling the crtcs gracefully seems nicer. Also the
3196 * g33 docs say we should at least disable all the planes.
3197 */
3198 intel_display_suspend(dev);
3199 }
3200
3201 void intel_finish_reset(struct drm_device *dev)
3202 {
3203 struct drm_i915_private *dev_priv = to_i915(dev);
3204
3205 /*
3206 * Flips in the rings will be nuked by the reset,
3207 * so complete all pending flips so that user space
3208 * will get its events and not get stuck.
3209 */
3210 intel_complete_page_flips(dev);
3211
3212 /* no reset support for gen2 */
3213 if (IS_GEN2(dev))
3214 return;
3215
3216 /* reset doesn't touch the display */
3217 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3218 /*
3219 * Flips in the rings have been nuked by the reset,
3220 * so update the base address of all primary
3221 * planes to the the last fb to make sure we're
3222 * showing the correct fb after a reset.
3223 */
3224 intel_update_primary_planes(dev);
3225 return;
3226 }
3227
3228 /*
3229 * The display has been reset as well,
3230 * so need a full re-initialization.
3231 */
3232 intel_runtime_pm_disable_interrupts(dev_priv);
3233 intel_runtime_pm_enable_interrupts(dev_priv);
3234
3235 intel_modeset_init_hw(dev);
3236
3237 spin_lock_irq(&dev_priv->irq_lock);
3238 if (dev_priv->display.hpd_irq_setup)
3239 dev_priv->display.hpd_irq_setup(dev);
3240 spin_unlock_irq(&dev_priv->irq_lock);
3241
3242 intel_modeset_setup_hw_state(dev, true);
3243
3244 intel_hpd_init(dev_priv);
3245
3246 drm_modeset_unlock_all(dev);
3247 }
3248
3249 static void
3250 intel_finish_fb(struct drm_framebuffer *old_fb)
3251 {
3252 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3253 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3254 bool was_interruptible = dev_priv->mm.interruptible;
3255 int ret;
3256
3257 /* Big Hammer, we also need to ensure that any pending
3258 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3259 * current scanout is retired before unpinning the old
3260 * framebuffer. Note that we rely on userspace rendering
3261 * into the buffer attached to the pipe they are waiting
3262 * on. If not, userspace generates a GPU hang with IPEHR
3263 * point to the MI_WAIT_FOR_EVENT.
3264 *
3265 * This should only fail upon a hung GPU, in which case we
3266 * can safely continue.
3267 */
3268 dev_priv->mm.interruptible = false;
3269 ret = i915_gem_object_wait_rendering(obj, true);
3270 dev_priv->mm.interruptible = was_interruptible;
3271
3272 WARN_ON(ret);
3273 }
3274
3275 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3276 {
3277 struct drm_device *dev = crtc->dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3280 bool pending;
3281
3282 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3283 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3284 return false;
3285
3286 spin_lock_irq(&dev->event_lock);
3287 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3288 spin_unlock_irq(&dev->event_lock);
3289
3290 return pending;
3291 }
3292
3293 static void intel_update_pipe_size(struct intel_crtc *crtc)
3294 {
3295 struct drm_device *dev = crtc->base.dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 const struct drm_display_mode *adjusted_mode;
3298
3299 if (!i915.fastboot)
3300 return;
3301
3302 /*
3303 * Update pipe size and adjust fitter if needed: the reason for this is
3304 * that in compute_mode_changes we check the native mode (not the pfit
3305 * mode) to see if we can flip rather than do a full mode set. In the
3306 * fastboot case, we'll flip, but if we don't update the pipesrc and
3307 * pfit state, we'll end up with a big fb scanned out into the wrong
3308 * sized surface.
3309 *
3310 * To fix this properly, we need to hoist the checks up into
3311 * compute_mode_changes (or above), check the actual pfit state and
3312 * whether the platform allows pfit disable with pipe active, and only
3313 * then update the pipesrc and pfit state, even on the flip path.
3314 */
3315
3316 adjusted_mode = &crtc->config->base.adjusted_mode;
3317
3318 I915_WRITE(PIPESRC(crtc->pipe),
3319 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3320 (adjusted_mode->crtc_vdisplay - 1));
3321 if (!crtc->config->pch_pfit.enabled &&
3322 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3323 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3324 I915_WRITE(PF_CTL(crtc->pipe), 0);
3325 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3326 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3327 }
3328 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3329 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3330 }
3331
3332 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3333 {
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 int pipe = intel_crtc->pipe;
3338 u32 reg, temp;
3339
3340 /* enable normal train */
3341 reg = FDI_TX_CTL(pipe);
3342 temp = I915_READ(reg);
3343 if (IS_IVYBRIDGE(dev)) {
3344 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3345 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3346 } else {
3347 temp &= ~FDI_LINK_TRAIN_NONE;
3348 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3349 }
3350 I915_WRITE(reg, temp);
3351
3352 reg = FDI_RX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 if (HAS_PCH_CPT(dev)) {
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3357 } else {
3358 temp &= ~FDI_LINK_TRAIN_NONE;
3359 temp |= FDI_LINK_TRAIN_NONE;
3360 }
3361 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3362
3363 /* wait one idle pattern time */
3364 POSTING_READ(reg);
3365 udelay(1000);
3366
3367 /* IVB wants error correction enabled */
3368 if (IS_IVYBRIDGE(dev))
3369 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3370 FDI_FE_ERRC_ENABLE);
3371 }
3372
3373 /* The FDI link training functions for ILK/Ibexpeak. */
3374 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3375 {
3376 struct drm_device *dev = crtc->dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379 int pipe = intel_crtc->pipe;
3380 u32 reg, temp, tries;
3381
3382 /* FDI needs bits from pipe first */
3383 assert_pipe_enabled(dev_priv, pipe);
3384
3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
3391 I915_WRITE(reg, temp);
3392 I915_READ(reg);
3393 udelay(150);
3394
3395 /* enable CPU FDI TX and PCH FDI RX */
3396 reg = FDI_TX_CTL(pipe);
3397 temp = I915_READ(reg);
3398 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3399 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3400 temp &= ~FDI_LINK_TRAIN_NONE;
3401 temp |= FDI_LINK_TRAIN_PATTERN_1;
3402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3403
3404 reg = FDI_RX_CTL(pipe);
3405 temp = I915_READ(reg);
3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1;
3408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3409
3410 POSTING_READ(reg);
3411 udelay(150);
3412
3413 /* Ironlake workaround, enable clock pointer after FDI enable*/
3414 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3416 FDI_RX_PHASE_SYNC_POINTER_EN);
3417
3418 reg = FDI_RX_IIR(pipe);
3419 for (tries = 0; tries < 5; tries++) {
3420 temp = I915_READ(reg);
3421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3422
3423 if ((temp & FDI_RX_BIT_LOCK)) {
3424 DRM_DEBUG_KMS("FDI train 1 done.\n");
3425 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3426 break;
3427 }
3428 }
3429 if (tries == 5)
3430 DRM_ERROR("FDI train 1 fail!\n");
3431
3432 /* Train 2 */
3433 reg = FDI_TX_CTL(pipe);
3434 temp = I915_READ(reg);
3435 temp &= ~FDI_LINK_TRAIN_NONE;
3436 temp |= FDI_LINK_TRAIN_PATTERN_2;
3437 I915_WRITE(reg, temp);
3438
3439 reg = FDI_RX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2;
3443 I915_WRITE(reg, temp);
3444
3445 POSTING_READ(reg);
3446 udelay(150);
3447
3448 reg = FDI_RX_IIR(pipe);
3449 for (tries = 0; tries < 5; tries++) {
3450 temp = I915_READ(reg);
3451 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3452
3453 if (temp & FDI_RX_SYMBOL_LOCK) {
3454 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3455 DRM_DEBUG_KMS("FDI train 2 done.\n");
3456 break;
3457 }
3458 }
3459 if (tries == 5)
3460 DRM_ERROR("FDI train 2 fail!\n");
3461
3462 DRM_DEBUG_KMS("FDI train done\n");
3463
3464 }
3465
3466 static const int snb_b_fdi_train_param[] = {
3467 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3468 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3469 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3470 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3471 };
3472
3473 /* The FDI link training functions for SNB/Cougarpoint. */
3474 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3475 {
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479 int pipe = intel_crtc->pipe;
3480 u32 reg, temp, i, retry;
3481
3482 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3483 for train result */
3484 reg = FDI_RX_IMR(pipe);
3485 temp = I915_READ(reg);
3486 temp &= ~FDI_RX_SYMBOL_LOCK;
3487 temp &= ~FDI_RX_BIT_LOCK;
3488 I915_WRITE(reg, temp);
3489
3490 POSTING_READ(reg);
3491 udelay(150);
3492
3493 /* enable CPU FDI TX and PCH FDI RX */
3494 reg = FDI_TX_CTL(pipe);
3495 temp = I915_READ(reg);
3496 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3497 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3498 temp &= ~FDI_LINK_TRAIN_NONE;
3499 temp |= FDI_LINK_TRAIN_PATTERN_1;
3500 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3501 /* SNB-B */
3502 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3503 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3504
3505 I915_WRITE(FDI_RX_MISC(pipe),
3506 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3507
3508 reg = FDI_RX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 if (HAS_PCH_CPT(dev)) {
3511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3512 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3513 } else {
3514 temp &= ~FDI_LINK_TRAIN_NONE;
3515 temp |= FDI_LINK_TRAIN_PATTERN_1;
3516 }
3517 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3518
3519 POSTING_READ(reg);
3520 udelay(150);
3521
3522 for (i = 0; i < 4; i++) {
3523 reg = FDI_TX_CTL(pipe);
3524 temp = I915_READ(reg);
3525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526 temp |= snb_b_fdi_train_param[i];
3527 I915_WRITE(reg, temp);
3528
3529 POSTING_READ(reg);
3530 udelay(500);
3531
3532 for (retry = 0; retry < 5; retry++) {
3533 reg = FDI_RX_IIR(pipe);
3534 temp = I915_READ(reg);
3535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3536 if (temp & FDI_RX_BIT_LOCK) {
3537 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3538 DRM_DEBUG_KMS("FDI train 1 done.\n");
3539 break;
3540 }
3541 udelay(50);
3542 }
3543 if (retry < 5)
3544 break;
3545 }
3546 if (i == 4)
3547 DRM_ERROR("FDI train 1 fail!\n");
3548
3549 /* Train 2 */
3550 reg = FDI_TX_CTL(pipe);
3551 temp = I915_READ(reg);
3552 temp &= ~FDI_LINK_TRAIN_NONE;
3553 temp |= FDI_LINK_TRAIN_PATTERN_2;
3554 if (IS_GEN6(dev)) {
3555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3556 /* SNB-B */
3557 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3558 }
3559 I915_WRITE(reg, temp);
3560
3561 reg = FDI_RX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 if (HAS_PCH_CPT(dev)) {
3564 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3565 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3566 } else {
3567 temp &= ~FDI_LINK_TRAIN_NONE;
3568 temp |= FDI_LINK_TRAIN_PATTERN_2;
3569 }
3570 I915_WRITE(reg, temp);
3571
3572 POSTING_READ(reg);
3573 udelay(150);
3574
3575 for (i = 0; i < 4; i++) {
3576 reg = FDI_TX_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3579 temp |= snb_b_fdi_train_param[i];
3580 I915_WRITE(reg, temp);
3581
3582 POSTING_READ(reg);
3583 udelay(500);
3584
3585 for (retry = 0; retry < 5; retry++) {
3586 reg = FDI_RX_IIR(pipe);
3587 temp = I915_READ(reg);
3588 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3589 if (temp & FDI_RX_SYMBOL_LOCK) {
3590 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3591 DRM_DEBUG_KMS("FDI train 2 done.\n");
3592 break;
3593 }
3594 udelay(50);
3595 }
3596 if (retry < 5)
3597 break;
3598 }
3599 if (i == 4)
3600 DRM_ERROR("FDI train 2 fail!\n");
3601
3602 DRM_DEBUG_KMS("FDI train done.\n");
3603 }
3604
3605 /* Manual link training for Ivy Bridge A0 parts */
3606 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3607 {
3608 struct drm_device *dev = crtc->dev;
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3611 int pipe = intel_crtc->pipe;
3612 u32 reg, temp, i, j;
3613
3614 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3615 for train result */
3616 reg = FDI_RX_IMR(pipe);
3617 temp = I915_READ(reg);
3618 temp &= ~FDI_RX_SYMBOL_LOCK;
3619 temp &= ~FDI_RX_BIT_LOCK;
3620 I915_WRITE(reg, temp);
3621
3622 POSTING_READ(reg);
3623 udelay(150);
3624
3625 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3626 I915_READ(FDI_RX_IIR(pipe)));
3627
3628 /* Try each vswing and preemphasis setting twice before moving on */
3629 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3630 /* disable first in case we need to retry */
3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3634 temp &= ~FDI_TX_ENABLE;
3635 I915_WRITE(reg, temp);
3636
3637 reg = FDI_RX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~FDI_LINK_TRAIN_AUTO;
3640 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3641 temp &= ~FDI_RX_ENABLE;
3642 I915_WRITE(reg, temp);
3643
3644 /* enable CPU FDI TX and PCH FDI RX */
3645 reg = FDI_TX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3649 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3651 temp |= snb_b_fdi_train_param[j/2];
3652 temp |= FDI_COMPOSITE_SYNC;
3653 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3654
3655 I915_WRITE(FDI_RX_MISC(pipe),
3656 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3657
3658 reg = FDI_RX_CTL(pipe);
3659 temp = I915_READ(reg);
3660 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3661 temp |= FDI_COMPOSITE_SYNC;
3662 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3663
3664 POSTING_READ(reg);
3665 udelay(1); /* should be 0.5us */
3666
3667 for (i = 0; i < 4; i++) {
3668 reg = FDI_RX_IIR(pipe);
3669 temp = I915_READ(reg);
3670 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3671
3672 if (temp & FDI_RX_BIT_LOCK ||
3673 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3674 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3675 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3676 i);
3677 break;
3678 }
3679 udelay(1); /* should be 0.5us */
3680 }
3681 if (i == 4) {
3682 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3683 continue;
3684 }
3685
3686 /* Train 2 */
3687 reg = FDI_TX_CTL(pipe);
3688 temp = I915_READ(reg);
3689 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3690 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3691 I915_WRITE(reg, temp);
3692
3693 reg = FDI_RX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3696 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3697 I915_WRITE(reg, temp);
3698
3699 POSTING_READ(reg);
3700 udelay(2); /* should be 1.5us */
3701
3702 for (i = 0; i < 4; i++) {
3703 reg = FDI_RX_IIR(pipe);
3704 temp = I915_READ(reg);
3705 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3706
3707 if (temp & FDI_RX_SYMBOL_LOCK ||
3708 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3709 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3710 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3711 i);
3712 goto train_done;
3713 }
3714 udelay(2); /* should be 1.5us */
3715 }
3716 if (i == 4)
3717 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3718 }
3719
3720 train_done:
3721 DRM_DEBUG_KMS("FDI train done.\n");
3722 }
3723
3724 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3725 {
3726 struct drm_device *dev = intel_crtc->base.dev;
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3728 int pipe = intel_crtc->pipe;
3729 u32 reg, temp;
3730
3731
3732 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3733 reg = FDI_RX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3736 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3738 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3739
3740 POSTING_READ(reg);
3741 udelay(200);
3742
3743 /* Switch from Rawclk to PCDclk */
3744 temp = I915_READ(reg);
3745 I915_WRITE(reg, temp | FDI_PCDCLK);
3746
3747 POSTING_READ(reg);
3748 udelay(200);
3749
3750 /* Enable CPU FDI TX PLL, always on for Ironlake */
3751 reg = FDI_TX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3754 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758 }
3759 }
3760
3761 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3762 {
3763 struct drm_device *dev = intel_crtc->base.dev;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 int pipe = intel_crtc->pipe;
3766 u32 reg, temp;
3767
3768 /* Switch from PCDclk to Rawclk */
3769 reg = FDI_RX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3772
3773 /* Disable CPU FDI TX PLL */
3774 reg = FDI_TX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3777
3778 POSTING_READ(reg);
3779 udelay(100);
3780
3781 reg = FDI_RX_CTL(pipe);
3782 temp = I915_READ(reg);
3783 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3784
3785 /* Wait for the clocks to turn off. */
3786 POSTING_READ(reg);
3787 udelay(100);
3788 }
3789
3790 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3791 {
3792 struct drm_device *dev = crtc->dev;
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795 int pipe = intel_crtc->pipe;
3796 u32 reg, temp;
3797
3798 /* disable CPU FDI tx and PCH FDI rx */
3799 reg = FDI_TX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3802 POSTING_READ(reg);
3803
3804 reg = FDI_RX_CTL(pipe);
3805 temp = I915_READ(reg);
3806 temp &= ~(0x7 << 16);
3807 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3808 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 /* Ironlake workaround, disable clock pointer after downing FDI */
3814 if (HAS_PCH_IBX(dev))
3815 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3816
3817 /* still set train pattern 1 */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~FDI_LINK_TRAIN_NONE;
3821 temp |= FDI_LINK_TRAIN_PATTERN_1;
3822 I915_WRITE(reg, temp);
3823
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 if (HAS_PCH_CPT(dev)) {
3827 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3828 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3829 } else {
3830 temp &= ~FDI_LINK_TRAIN_NONE;
3831 temp |= FDI_LINK_TRAIN_PATTERN_1;
3832 }
3833 /* BPC in FDI rx is consistent with that in PIPECONF */
3834 temp &= ~(0x07 << 16);
3835 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3836 I915_WRITE(reg, temp);
3837
3838 POSTING_READ(reg);
3839 udelay(100);
3840 }
3841
3842 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3843 {
3844 struct intel_crtc *crtc;
3845
3846 /* Note that we don't need to be called with mode_config.lock here
3847 * as our list of CRTC objects is static for the lifetime of the
3848 * device and so cannot disappear as we iterate. Similarly, we can
3849 * happily treat the predicates as racy, atomic checks as userspace
3850 * cannot claim and pin a new fb without at least acquring the
3851 * struct_mutex and so serialising with us.
3852 */
3853 for_each_intel_crtc(dev, crtc) {
3854 if (atomic_read(&crtc->unpin_work_count) == 0)
3855 continue;
3856
3857 if (crtc->unpin_work)
3858 intel_wait_for_vblank(dev, crtc->pipe);
3859
3860 return true;
3861 }
3862
3863 return false;
3864 }
3865
3866 static void page_flip_completed(struct intel_crtc *intel_crtc)
3867 {
3868 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3869 struct intel_unpin_work *work = intel_crtc->unpin_work;
3870
3871 /* ensure that the unpin work is consistent wrt ->pending. */
3872 smp_rmb();
3873 intel_crtc->unpin_work = NULL;
3874
3875 if (work->event)
3876 drm_send_vblank_event(intel_crtc->base.dev,
3877 intel_crtc->pipe,
3878 work->event);
3879
3880 drm_crtc_vblank_put(&intel_crtc->base);
3881
3882 wake_up_all(&dev_priv->pending_flip_queue);
3883 queue_work(dev_priv->wq, &work->work);
3884
3885 trace_i915_flip_complete(intel_crtc->plane,
3886 work->pending_flip_obj);
3887 }
3888
3889 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3890 {
3891 struct drm_device *dev = crtc->dev;
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893
3894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3895 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3896 !intel_crtc_has_pending_flip(crtc),
3897 60*HZ) == 0)) {
3898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3899
3900 spin_lock_irq(&dev->event_lock);
3901 if (intel_crtc->unpin_work) {
3902 WARN_ONCE(1, "Removing stuck page flip\n");
3903 page_flip_completed(intel_crtc);
3904 }
3905 spin_unlock_irq(&dev->event_lock);
3906 }
3907
3908 if (crtc->primary->fb) {
3909 mutex_lock(&dev->struct_mutex);
3910 intel_finish_fb(crtc->primary->fb);
3911 mutex_unlock(&dev->struct_mutex);
3912 }
3913 }
3914
3915 /* Program iCLKIP clock to the desired frequency */
3916 static void lpt_program_iclkip(struct drm_crtc *crtc)
3917 {
3918 struct drm_device *dev = crtc->dev;
3919 struct drm_i915_private *dev_priv = dev->dev_private;
3920 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3921 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3922 u32 temp;
3923
3924 mutex_lock(&dev_priv->sb_lock);
3925
3926 /* It is necessary to ungate the pixclk gate prior to programming
3927 * the divisors, and gate it back when it is done.
3928 */
3929 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3930
3931 /* Disable SSCCTL */
3932 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3933 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3934 SBI_SSCCTL_DISABLE,
3935 SBI_ICLK);
3936
3937 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3938 if (clock == 20000) {
3939 auxdiv = 1;
3940 divsel = 0x41;
3941 phaseinc = 0x20;
3942 } else {
3943 /* The iCLK virtual clock root frequency is in MHz,
3944 * but the adjusted_mode->crtc_clock in in KHz. To get the
3945 * divisors, it is necessary to divide one by another, so we
3946 * convert the virtual clock precision to KHz here for higher
3947 * precision.
3948 */
3949 u32 iclk_virtual_root_freq = 172800 * 1000;
3950 u32 iclk_pi_range = 64;
3951 u32 desired_divisor, msb_divisor_value, pi_value;
3952
3953 desired_divisor = (iclk_virtual_root_freq / clock);
3954 msb_divisor_value = desired_divisor / iclk_pi_range;
3955 pi_value = desired_divisor % iclk_pi_range;
3956
3957 auxdiv = 0;
3958 divsel = msb_divisor_value - 2;
3959 phaseinc = pi_value;
3960 }
3961
3962 /* This should not happen with any sane values */
3963 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3964 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3965 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3966 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3967
3968 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3969 clock,
3970 auxdiv,
3971 divsel,
3972 phasedir,
3973 phaseinc);
3974
3975 /* Program SSCDIVINTPHASE6 */
3976 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3977 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3978 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3979 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3980 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3981 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3982 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3983 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3984
3985 /* Program SSCAUXDIV */
3986 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3987 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3988 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3989 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3990
3991 /* Enable modulator and associated divider */
3992 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3993 temp &= ~SBI_SSCCTL_DISABLE;
3994 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3995
3996 /* Wait for initialization time */
3997 udelay(24);
3998
3999 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4000
4001 mutex_unlock(&dev_priv->sb_lock);
4002 }
4003
4004 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4005 enum pipe pch_transcoder)
4006 {
4007 struct drm_device *dev = crtc->base.dev;
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4010
4011 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4012 I915_READ(HTOTAL(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4014 I915_READ(HBLANK(cpu_transcoder)));
4015 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4016 I915_READ(HSYNC(cpu_transcoder)));
4017
4018 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4019 I915_READ(VTOTAL(cpu_transcoder)));
4020 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4021 I915_READ(VBLANK(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4023 I915_READ(VSYNC(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4025 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4026 }
4027
4028 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4029 {
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 uint32_t temp;
4032
4033 temp = I915_READ(SOUTH_CHICKEN1);
4034 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4035 return;
4036
4037 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4038 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4039
4040 temp &= ~FDI_BC_BIFURCATION_SELECT;
4041 if (enable)
4042 temp |= FDI_BC_BIFURCATION_SELECT;
4043
4044 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4045 I915_WRITE(SOUTH_CHICKEN1, temp);
4046 POSTING_READ(SOUTH_CHICKEN1);
4047 }
4048
4049 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4050 {
4051 struct drm_device *dev = intel_crtc->base.dev;
4052
4053 switch (intel_crtc->pipe) {
4054 case PIPE_A:
4055 break;
4056 case PIPE_B:
4057 if (intel_crtc->config->fdi_lanes > 2)
4058 cpt_set_fdi_bc_bifurcation(dev, false);
4059 else
4060 cpt_set_fdi_bc_bifurcation(dev, true);
4061
4062 break;
4063 case PIPE_C:
4064 cpt_set_fdi_bc_bifurcation(dev, true);
4065
4066 break;
4067 default:
4068 BUG();
4069 }
4070 }
4071
4072 /*
4073 * Enable PCH resources required for PCH ports:
4074 * - PCH PLLs
4075 * - FDI training & RX/TX
4076 * - update transcoder timings
4077 * - DP transcoding bits
4078 * - transcoder
4079 */
4080 static void ironlake_pch_enable(struct drm_crtc *crtc)
4081 {
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4085 int pipe = intel_crtc->pipe;
4086 u32 reg, temp;
4087
4088 assert_pch_transcoder_disabled(dev_priv, pipe);
4089
4090 if (IS_IVYBRIDGE(dev))
4091 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4092
4093 /* Write the TU size bits before fdi link training, so that error
4094 * detection works. */
4095 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4096 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4097
4098 /* For PCH output, training FDI link */
4099 dev_priv->display.fdi_link_train(crtc);
4100
4101 /* We need to program the right clock selection before writing the pixel
4102 * mutliplier into the DPLL. */
4103 if (HAS_PCH_CPT(dev)) {
4104 u32 sel;
4105
4106 temp = I915_READ(PCH_DPLL_SEL);
4107 temp |= TRANS_DPLL_ENABLE(pipe);
4108 sel = TRANS_DPLLB_SEL(pipe);
4109 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4110 temp |= sel;
4111 else
4112 temp &= ~sel;
4113 I915_WRITE(PCH_DPLL_SEL, temp);
4114 }
4115
4116 /* XXX: pch pll's can be enabled any time before we enable the PCH
4117 * transcoder, and we actually should do this to not upset any PCH
4118 * transcoder that already use the clock when we share it.
4119 *
4120 * Note that enable_shared_dpll tries to do the right thing, but
4121 * get_shared_dpll unconditionally resets the pll - we need that to have
4122 * the right LVDS enable sequence. */
4123 intel_enable_shared_dpll(intel_crtc);
4124
4125 /* set transcoder timing, panel must allow it */
4126 assert_panel_unlocked(dev_priv, pipe);
4127 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4128
4129 intel_fdi_normal_train(crtc);
4130
4131 /* For PCH DP, enable TRANS_DP_CTL */
4132 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4133 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4134 reg = TRANS_DP_CTL(pipe);
4135 temp = I915_READ(reg);
4136 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4137 TRANS_DP_SYNC_MASK |
4138 TRANS_DP_BPC_MASK);
4139 temp |= TRANS_DP_OUTPUT_ENABLE;
4140 temp |= bpc << 9; /* same format but at 11:9 */
4141
4142 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4143 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4144 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4145 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4146
4147 switch (intel_trans_dp_port_sel(crtc)) {
4148 case PCH_DP_B:
4149 temp |= TRANS_DP_PORT_SEL_B;
4150 break;
4151 case PCH_DP_C:
4152 temp |= TRANS_DP_PORT_SEL_C;
4153 break;
4154 case PCH_DP_D:
4155 temp |= TRANS_DP_PORT_SEL_D;
4156 break;
4157 default:
4158 BUG();
4159 }
4160
4161 I915_WRITE(reg, temp);
4162 }
4163
4164 ironlake_enable_pch_transcoder(dev_priv, pipe);
4165 }
4166
4167 static void lpt_pch_enable(struct drm_crtc *crtc)
4168 {
4169 struct drm_device *dev = crtc->dev;
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4173
4174 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4175
4176 lpt_program_iclkip(crtc);
4177
4178 /* Set transcoder timing. */
4179 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4180
4181 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4182 }
4183
4184 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4185 struct intel_crtc_state *crtc_state)
4186 {
4187 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4188 struct intel_shared_dpll *pll;
4189 struct intel_shared_dpll_config *shared_dpll;
4190 enum intel_dpll_id i;
4191
4192 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4193
4194 if (HAS_PCH_IBX(dev_priv->dev)) {
4195 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4196 i = (enum intel_dpll_id) crtc->pipe;
4197 pll = &dev_priv->shared_dplls[i];
4198
4199 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4200 crtc->base.base.id, pll->name);
4201
4202 WARN_ON(shared_dpll[i].crtc_mask);
4203
4204 goto found;
4205 }
4206
4207 if (IS_BROXTON(dev_priv->dev)) {
4208 /* PLL is attached to port in bxt */
4209 struct intel_encoder *encoder;
4210 struct intel_digital_port *intel_dig_port;
4211
4212 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4213 if (WARN_ON(!encoder))
4214 return NULL;
4215
4216 intel_dig_port = enc_to_dig_port(&encoder->base);
4217 /* 1:1 mapping between ports and PLLs */
4218 i = (enum intel_dpll_id)intel_dig_port->port;
4219 pll = &dev_priv->shared_dplls[i];
4220 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4221 crtc->base.base.id, pll->name);
4222 WARN_ON(shared_dpll[i].crtc_mask);
4223
4224 goto found;
4225 }
4226
4227 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4228 pll = &dev_priv->shared_dplls[i];
4229
4230 /* Only want to check enabled timings first */
4231 if (shared_dpll[i].crtc_mask == 0)
4232 continue;
4233
4234 if (memcmp(&crtc_state->dpll_hw_state,
4235 &shared_dpll[i].hw_state,
4236 sizeof(crtc_state->dpll_hw_state)) == 0) {
4237 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4238 crtc->base.base.id, pll->name,
4239 shared_dpll[i].crtc_mask,
4240 pll->active);
4241 goto found;
4242 }
4243 }
4244
4245 /* Ok no matching timings, maybe there's a free one? */
4246 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4247 pll = &dev_priv->shared_dplls[i];
4248 if (shared_dpll[i].crtc_mask == 0) {
4249 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4250 crtc->base.base.id, pll->name);
4251 goto found;
4252 }
4253 }
4254
4255 return NULL;
4256
4257 found:
4258 if (shared_dpll[i].crtc_mask == 0)
4259 shared_dpll[i].hw_state =
4260 crtc_state->dpll_hw_state;
4261
4262 crtc_state->shared_dpll = i;
4263 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4264 pipe_name(crtc->pipe));
4265
4266 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4267
4268 return pll;
4269 }
4270
4271 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4272 {
4273 struct drm_i915_private *dev_priv = to_i915(state->dev);
4274 struct intel_shared_dpll_config *shared_dpll;
4275 struct intel_shared_dpll *pll;
4276 enum intel_dpll_id i;
4277
4278 if (!to_intel_atomic_state(state)->dpll_set)
4279 return;
4280
4281 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
4284 pll->config = shared_dpll[i];
4285 }
4286 }
4287
4288 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4289 {
4290 struct drm_i915_private *dev_priv = dev->dev_private;
4291 int dslreg = PIPEDSL(pipe);
4292 u32 temp;
4293
4294 temp = I915_READ(dslreg);
4295 udelay(500);
4296 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4297 if (wait_for(I915_READ(dslreg) != temp, 5))
4298 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4299 }
4300 }
4301
4302 /**
4303 * skl_update_scaler_users - Stages update to crtc's scaler state
4304 * @intel_crtc: crtc
4305 * @crtc_state: crtc_state
4306 * @plane: plane (NULL indicates crtc is requesting update)
4307 * @plane_state: plane's state
4308 * @force_detach: request unconditional detachment of scaler
4309 *
4310 * This function updates scaler state for requested plane or crtc.
4311 * To request scaler usage update for a plane, caller shall pass plane pointer.
4312 * To request scaler usage update for crtc, caller shall pass plane pointer
4313 * as NULL.
4314 *
4315 * Return
4316 * 0 - scaler_usage updated successfully
4317 * error - requested scaling cannot be supported or other error condition
4318 */
4319 int
4320 skl_update_scaler_users(
4321 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4322 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4323 int force_detach)
4324 {
4325 int need_scaling;
4326 int idx;
4327 int src_w, src_h, dst_w, dst_h;
4328 int *scaler_id;
4329 struct drm_framebuffer *fb;
4330 struct intel_crtc_scaler_state *scaler_state;
4331 unsigned int rotation;
4332
4333 if (!intel_crtc || !crtc_state)
4334 return 0;
4335
4336 scaler_state = &crtc_state->scaler_state;
4337
4338 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4339 fb = intel_plane ? plane_state->base.fb : NULL;
4340
4341 if (intel_plane) {
4342 src_w = drm_rect_width(&plane_state->src) >> 16;
4343 src_h = drm_rect_height(&plane_state->src) >> 16;
4344 dst_w = drm_rect_width(&plane_state->dst);
4345 dst_h = drm_rect_height(&plane_state->dst);
4346 scaler_id = &plane_state->scaler_id;
4347 rotation = plane_state->base.rotation;
4348 } else {
4349 struct drm_display_mode *adjusted_mode =
4350 &crtc_state->base.adjusted_mode;
4351 src_w = crtc_state->pipe_src_w;
4352 src_h = crtc_state->pipe_src_h;
4353 dst_w = adjusted_mode->hdisplay;
4354 dst_h = adjusted_mode->vdisplay;
4355 scaler_id = &scaler_state->scaler_id;
4356 rotation = DRM_ROTATE_0;
4357 }
4358
4359 need_scaling = intel_rotation_90_or_270(rotation) ?
4360 (src_h != dst_w || src_w != dst_h):
4361 (src_w != dst_w || src_h != dst_h);
4362
4363 /*
4364 * if plane is being disabled or scaler is no more required or force detach
4365 * - free scaler binded to this plane/crtc
4366 * - in order to do this, update crtc->scaler_usage
4367 *
4368 * Here scaler state in crtc_state is set free so that
4369 * scaler can be assigned to other user. Actual register
4370 * update to free the scaler is done in plane/panel-fit programming.
4371 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4372 */
4373 if (force_detach || !need_scaling || (intel_plane &&
4374 (!fb || !plane_state->visible))) {
4375 if (*scaler_id >= 0) {
4376 scaler_state->scaler_users &= ~(1 << idx);
4377 scaler_state->scalers[*scaler_id].in_use = 0;
4378
4379 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4380 "crtc_state = %p scaler_users = 0x%x\n",
4381 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4382 intel_plane ? intel_plane->base.base.id :
4383 intel_crtc->base.base.id, crtc_state,
4384 scaler_state->scaler_users);
4385 *scaler_id = -1;
4386 }
4387 return 0;
4388 }
4389
4390 /* range checks */
4391 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4392 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4393
4394 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4395 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4396 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4397 "size is out of scaler range\n",
4398 intel_plane ? "PLANE" : "CRTC",
4399 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4400 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4401 return -EINVAL;
4402 }
4403
4404 /* check colorkey */
4405 if (WARN_ON(intel_plane &&
4406 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4407 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4408 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4409 return -EINVAL;
4410 }
4411
4412 /* Check src format */
4413 if (intel_plane) {
4414 switch (fb->pixel_format) {
4415 case DRM_FORMAT_RGB565:
4416 case DRM_FORMAT_XBGR8888:
4417 case DRM_FORMAT_XRGB8888:
4418 case DRM_FORMAT_ABGR8888:
4419 case DRM_FORMAT_ARGB8888:
4420 case DRM_FORMAT_XRGB2101010:
4421 case DRM_FORMAT_XBGR2101010:
4422 case DRM_FORMAT_YUYV:
4423 case DRM_FORMAT_YVYU:
4424 case DRM_FORMAT_UYVY:
4425 case DRM_FORMAT_VYUY:
4426 break;
4427 default:
4428 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4429 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4430 return -EINVAL;
4431 }
4432 }
4433
4434 /* mark this plane as a scaler user in crtc_state */
4435 scaler_state->scaler_users |= (1 << idx);
4436 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4437 "crtc_state = %p scaler_users = 0x%x\n",
4438 intel_plane ? "PLANE" : "CRTC",
4439 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4440 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4441 return 0;
4442 }
4443
4444 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4445 {
4446 struct drm_device *dev = crtc->base.dev;
4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448 int pipe = crtc->pipe;
4449 struct intel_crtc_scaler_state *scaler_state =
4450 &crtc->config->scaler_state;
4451
4452 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4453
4454 /* To update pfit, first update scaler state */
4455 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4456 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4457 skl_detach_scalers(crtc);
4458 if (!enable)
4459 return;
4460
4461 if (crtc->config->pch_pfit.enabled) {
4462 int id;
4463
4464 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4465 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4466 return;
4467 }
4468
4469 id = scaler_state->scaler_id;
4470 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4471 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4472 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4473 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4474
4475 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4476 }
4477 }
4478
4479 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4480 {
4481 struct drm_device *dev = crtc->base.dev;
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 int pipe = crtc->pipe;
4484
4485 if (crtc->config->pch_pfit.enabled) {
4486 /* Force use of hard-coded filter coefficients
4487 * as some pre-programmed values are broken,
4488 * e.g. x201.
4489 */
4490 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4491 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4492 PF_PIPE_SEL_IVB(pipe));
4493 else
4494 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4495 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4496 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4497 }
4498 }
4499
4500 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4501 {
4502 struct drm_device *dev = crtc->dev;
4503 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4504 struct drm_plane *plane;
4505 struct intel_plane *intel_plane;
4506
4507 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4508 intel_plane = to_intel_plane(plane);
4509 if (intel_plane->pipe == pipe)
4510 intel_plane_restore(&intel_plane->base);
4511 }
4512 }
4513
4514 void hsw_enable_ips(struct intel_crtc *crtc)
4515 {
4516 struct drm_device *dev = crtc->base.dev;
4517 struct drm_i915_private *dev_priv = dev->dev_private;
4518
4519 if (!crtc->config->ips_enabled)
4520 return;
4521
4522 /* We can only enable IPS after we enable a plane and wait for a vblank */
4523 intel_wait_for_vblank(dev, crtc->pipe);
4524
4525 assert_plane_enabled(dev_priv, crtc->plane);
4526 if (IS_BROADWELL(dev)) {
4527 mutex_lock(&dev_priv->rps.hw_lock);
4528 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4529 mutex_unlock(&dev_priv->rps.hw_lock);
4530 /* Quoting Art Runyan: "its not safe to expect any particular
4531 * value in IPS_CTL bit 31 after enabling IPS through the
4532 * mailbox." Moreover, the mailbox may return a bogus state,
4533 * so we need to just enable it and continue on.
4534 */
4535 } else {
4536 I915_WRITE(IPS_CTL, IPS_ENABLE);
4537 /* The bit only becomes 1 in the next vblank, so this wait here
4538 * is essentially intel_wait_for_vblank. If we don't have this
4539 * and don't wait for vblanks until the end of crtc_enable, then
4540 * the HW state readout code will complain that the expected
4541 * IPS_CTL value is not the one we read. */
4542 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4543 DRM_ERROR("Timed out waiting for IPS enable\n");
4544 }
4545 }
4546
4547 void hsw_disable_ips(struct intel_crtc *crtc)
4548 {
4549 struct drm_device *dev = crtc->base.dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551
4552 if (!crtc->config->ips_enabled)
4553 return;
4554
4555 assert_plane_enabled(dev_priv, crtc->plane);
4556 if (IS_BROADWELL(dev)) {
4557 mutex_lock(&dev_priv->rps.hw_lock);
4558 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4559 mutex_unlock(&dev_priv->rps.hw_lock);
4560 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4561 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4562 DRM_ERROR("Timed out waiting for IPS disable\n");
4563 } else {
4564 I915_WRITE(IPS_CTL, 0);
4565 POSTING_READ(IPS_CTL);
4566 }
4567
4568 /* We need to wait for a vblank before we can disable the plane. */
4569 intel_wait_for_vblank(dev, crtc->pipe);
4570 }
4571
4572 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4573 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4574 {
4575 struct drm_device *dev = crtc->dev;
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4578 enum pipe pipe = intel_crtc->pipe;
4579 int palreg = PALETTE(pipe);
4580 int i;
4581 bool reenable_ips = false;
4582
4583 /* The clocks have to be on to load the palette. */
4584 if (!crtc->state->active)
4585 return;
4586
4587 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4588 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4589 assert_dsi_pll_enabled(dev_priv);
4590 else
4591 assert_pll_enabled(dev_priv, pipe);
4592 }
4593
4594 /* use legacy palette for Ironlake */
4595 if (!HAS_GMCH_DISPLAY(dev))
4596 palreg = LGC_PALETTE(pipe);
4597
4598 /* Workaround : Do not read or write the pipe palette/gamma data while
4599 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4600 */
4601 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4602 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4603 GAMMA_MODE_MODE_SPLIT)) {
4604 hsw_disable_ips(intel_crtc);
4605 reenable_ips = true;
4606 }
4607
4608 for (i = 0; i < 256; i++) {
4609 I915_WRITE(palreg + 4 * i,
4610 (intel_crtc->lut_r[i] << 16) |
4611 (intel_crtc->lut_g[i] << 8) |
4612 intel_crtc->lut_b[i]);
4613 }
4614
4615 if (reenable_ips)
4616 hsw_enable_ips(intel_crtc);
4617 }
4618
4619 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4620 {
4621 if (intel_crtc->overlay) {
4622 struct drm_device *dev = intel_crtc->base.dev;
4623 struct drm_i915_private *dev_priv = dev->dev_private;
4624
4625 mutex_lock(&dev->struct_mutex);
4626 dev_priv->mm.interruptible = false;
4627 (void) intel_overlay_switch_off(intel_crtc->overlay);
4628 dev_priv->mm.interruptible = true;
4629 mutex_unlock(&dev->struct_mutex);
4630 }
4631
4632 /* Let userspace switch the overlay on again. In most cases userspace
4633 * has to recompute where to put it anyway.
4634 */
4635 }
4636
4637 /**
4638 * intel_post_enable_primary - Perform operations after enabling primary plane
4639 * @crtc: the CRTC whose primary plane was just enabled
4640 *
4641 * Performs potentially sleeping operations that must be done after the primary
4642 * plane is enabled, such as updating FBC and IPS. Note that this may be
4643 * called due to an explicit primary plane update, or due to an implicit
4644 * re-enable that is caused when a sprite plane is updated to no longer
4645 * completely hide the primary plane.
4646 */
4647 static void
4648 intel_post_enable_primary(struct drm_crtc *crtc)
4649 {
4650 struct drm_device *dev = crtc->dev;
4651 struct drm_i915_private *dev_priv = dev->dev_private;
4652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4653 int pipe = intel_crtc->pipe;
4654
4655 /*
4656 * BDW signals flip done immediately if the plane
4657 * is disabled, even if the plane enable is already
4658 * armed to occur at the next vblank :(
4659 */
4660 if (IS_BROADWELL(dev))
4661 intel_wait_for_vblank(dev, pipe);
4662
4663 /*
4664 * FIXME IPS should be fine as long as one plane is
4665 * enabled, but in practice it seems to have problems
4666 * when going from primary only to sprite only and vice
4667 * versa.
4668 */
4669 hsw_enable_ips(intel_crtc);
4670
4671 mutex_lock(&dev->struct_mutex);
4672 intel_fbc_update(dev);
4673 mutex_unlock(&dev->struct_mutex);
4674
4675 /*
4676 * Gen2 reports pipe underruns whenever all planes are disabled.
4677 * So don't enable underrun reporting before at least some planes
4678 * are enabled.
4679 * FIXME: Need to fix the logic to work when we turn off all planes
4680 * but leave the pipe running.
4681 */
4682 if (IS_GEN2(dev))
4683 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4684
4685 /* Underruns don't raise interrupts, so check manually. */
4686 if (HAS_GMCH_DISPLAY(dev))
4687 i9xx_check_fifo_underruns(dev_priv);
4688 }
4689
4690 /**
4691 * intel_pre_disable_primary - Perform operations before disabling primary plane
4692 * @crtc: the CRTC whose primary plane is to be disabled
4693 *
4694 * Performs potentially sleeping operations that must be done before the
4695 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4696 * be called due to an explicit primary plane update, or due to an implicit
4697 * disable that is caused when a sprite plane completely hides the primary
4698 * plane.
4699 */
4700 static void
4701 intel_pre_disable_primary(struct drm_crtc *crtc)
4702 {
4703 struct drm_device *dev = crtc->dev;
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706 int pipe = intel_crtc->pipe;
4707
4708 /*
4709 * Gen2 reports pipe underruns whenever all planes are disabled.
4710 * So diasble underrun reporting before all the planes get disabled.
4711 * FIXME: Need to fix the logic to work when we turn off all planes
4712 * but leave the pipe running.
4713 */
4714 if (IS_GEN2(dev))
4715 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4716
4717 /*
4718 * Vblank time updates from the shadow to live plane control register
4719 * are blocked if the memory self-refresh mode is active at that
4720 * moment. So to make sure the plane gets truly disabled, disable
4721 * first the self-refresh mode. The self-refresh enable bit in turn
4722 * will be checked/applied by the HW only at the next frame start
4723 * event which is after the vblank start event, so we need to have a
4724 * wait-for-vblank between disabling the plane and the pipe.
4725 */
4726 if (HAS_GMCH_DISPLAY(dev))
4727 intel_set_memory_cxsr(dev_priv, false);
4728
4729 mutex_lock(&dev->struct_mutex);
4730 if (dev_priv->fbc.crtc == intel_crtc)
4731 intel_fbc_disable(dev);
4732 mutex_unlock(&dev->struct_mutex);
4733
4734 /*
4735 * FIXME IPS should be fine as long as one plane is
4736 * enabled, but in practice it seems to have problems
4737 * when going from primary only to sprite only and vice
4738 * versa.
4739 */
4740 hsw_disable_ips(intel_crtc);
4741 }
4742
4743 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4744 {
4745 struct drm_device *dev = crtc->dev;
4746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4747 int pipe = intel_crtc->pipe;
4748
4749 intel_enable_primary_hw_plane(crtc->primary, crtc);
4750 intel_enable_sprite_planes(crtc);
4751 intel_crtc_update_cursor(crtc, true);
4752
4753 intel_post_enable_primary(crtc);
4754
4755 /*
4756 * FIXME: Once we grow proper nuclear flip support out of this we need
4757 * to compute the mask of flip planes precisely. For the time being
4758 * consider this a flip to a NULL plane.
4759 */
4760 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4761 }
4762
4763 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4764 {
4765 struct drm_device *dev = crtc->dev;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 struct intel_plane *intel_plane;
4768 int pipe = intel_crtc->pipe;
4769
4770 intel_crtc_wait_for_pending_flips(crtc);
4771
4772 intel_pre_disable_primary(crtc);
4773
4774 intel_crtc_dpms_overlay_disable(intel_crtc);
4775 for_each_intel_plane(dev, intel_plane) {
4776 if (intel_plane->pipe == pipe) {
4777 struct drm_crtc *from = intel_plane->base.crtc;
4778
4779 intel_plane->disable_plane(&intel_plane->base,
4780 from ?: crtc, true);
4781 }
4782 }
4783
4784 /*
4785 * FIXME: Once we grow proper nuclear flip support out of this we need
4786 * to compute the mask of flip planes precisely. For the time being
4787 * consider this a flip to a NULL plane.
4788 */
4789 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4790 }
4791
4792 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4793 {
4794 struct drm_device *dev = crtc->dev;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4797 struct intel_encoder *encoder;
4798 int pipe = intel_crtc->pipe;
4799
4800 if (WARN_ON(intel_crtc->active))
4801 return;
4802
4803 if (intel_crtc->config->has_pch_encoder)
4804 intel_prepare_shared_dpll(intel_crtc);
4805
4806 if (intel_crtc->config->has_dp_encoder)
4807 intel_dp_set_m_n(intel_crtc, M1_N1);
4808
4809 intel_set_pipe_timings(intel_crtc);
4810
4811 if (intel_crtc->config->has_pch_encoder) {
4812 intel_cpu_transcoder_set_m_n(intel_crtc,
4813 &intel_crtc->config->fdi_m_n, NULL);
4814 }
4815
4816 ironlake_set_pipeconf(crtc);
4817
4818 intel_crtc->active = true;
4819
4820 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4821 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4822
4823 for_each_encoder_on_crtc(dev, crtc, encoder)
4824 if (encoder->pre_enable)
4825 encoder->pre_enable(encoder);
4826
4827 if (intel_crtc->config->has_pch_encoder) {
4828 /* Note: FDI PLL enabling _must_ be done before we enable the
4829 * cpu pipes, hence this is separate from all the other fdi/pch
4830 * enabling. */
4831 ironlake_fdi_pll_enable(intel_crtc);
4832 } else {
4833 assert_fdi_tx_disabled(dev_priv, pipe);
4834 assert_fdi_rx_disabled(dev_priv, pipe);
4835 }
4836
4837 ironlake_pfit_enable(intel_crtc);
4838
4839 /*
4840 * On ILK+ LUT must be loaded before the pipe is running but with
4841 * clocks enabled
4842 */
4843 intel_crtc_load_lut(crtc);
4844
4845 intel_update_watermarks(crtc);
4846 intel_enable_pipe(intel_crtc);
4847
4848 if (intel_crtc->config->has_pch_encoder)
4849 ironlake_pch_enable(crtc);
4850
4851 assert_vblank_disabled(crtc);
4852 drm_crtc_vblank_on(crtc);
4853
4854 for_each_encoder_on_crtc(dev, crtc, encoder)
4855 encoder->enable(encoder);
4856
4857 if (HAS_PCH_CPT(dev))
4858 cpt_verify_modeset(dev, intel_crtc->pipe);
4859 }
4860
4861 /* IPS only exists on ULT machines and is tied to pipe A. */
4862 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4863 {
4864 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4865 }
4866
4867 /*
4868 * This implements the workaround described in the "notes" section of the mode
4869 * set sequence documentation. When going from no pipes or single pipe to
4870 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4871 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4872 */
4873 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4874 {
4875 struct drm_device *dev = crtc->base.dev;
4876 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4877
4878 /* We want to get the other_active_crtc only if there's only 1 other
4879 * active crtc. */
4880 for_each_intel_crtc(dev, crtc_it) {
4881 if (!crtc_it->active || crtc_it == crtc)
4882 continue;
4883
4884 if (other_active_crtc)
4885 return;
4886
4887 other_active_crtc = crtc_it;
4888 }
4889 if (!other_active_crtc)
4890 return;
4891
4892 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4893 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4894 }
4895
4896 static void haswell_crtc_enable(struct drm_crtc *crtc)
4897 {
4898 struct drm_device *dev = crtc->dev;
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4901 struct intel_encoder *encoder;
4902 int pipe = intel_crtc->pipe;
4903
4904 if (WARN_ON(intel_crtc->active))
4905 return;
4906
4907 if (intel_crtc_to_shared_dpll(intel_crtc))
4908 intel_enable_shared_dpll(intel_crtc);
4909
4910 if (intel_crtc->config->has_dp_encoder)
4911 intel_dp_set_m_n(intel_crtc, M1_N1);
4912
4913 intel_set_pipe_timings(intel_crtc);
4914
4915 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4916 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4917 intel_crtc->config->pixel_multiplier - 1);
4918 }
4919
4920 if (intel_crtc->config->has_pch_encoder) {
4921 intel_cpu_transcoder_set_m_n(intel_crtc,
4922 &intel_crtc->config->fdi_m_n, NULL);
4923 }
4924
4925 haswell_set_pipeconf(crtc);
4926
4927 intel_set_pipe_csc(crtc);
4928
4929 intel_crtc->active = true;
4930
4931 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4932 for_each_encoder_on_crtc(dev, crtc, encoder)
4933 if (encoder->pre_enable)
4934 encoder->pre_enable(encoder);
4935
4936 if (intel_crtc->config->has_pch_encoder) {
4937 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4938 true);
4939 dev_priv->display.fdi_link_train(crtc);
4940 }
4941
4942 intel_ddi_enable_pipe_clock(intel_crtc);
4943
4944 if (INTEL_INFO(dev)->gen == 9)
4945 skylake_pfit_update(intel_crtc, 1);
4946 else if (INTEL_INFO(dev)->gen < 9)
4947 ironlake_pfit_enable(intel_crtc);
4948 else
4949 MISSING_CASE(INTEL_INFO(dev)->gen);
4950
4951 /*
4952 * On ILK+ LUT must be loaded before the pipe is running but with
4953 * clocks enabled
4954 */
4955 intel_crtc_load_lut(crtc);
4956
4957 intel_ddi_set_pipe_settings(crtc);
4958 intel_ddi_enable_transcoder_func(crtc);
4959
4960 intel_update_watermarks(crtc);
4961 intel_enable_pipe(intel_crtc);
4962
4963 if (intel_crtc->config->has_pch_encoder)
4964 lpt_pch_enable(crtc);
4965
4966 if (intel_crtc->config->dp_encoder_is_mst)
4967 intel_ddi_set_vc_payload_alloc(crtc, true);
4968
4969 assert_vblank_disabled(crtc);
4970 drm_crtc_vblank_on(crtc);
4971
4972 for_each_encoder_on_crtc(dev, crtc, encoder) {
4973 encoder->enable(encoder);
4974 intel_opregion_notify_encoder(encoder, true);
4975 }
4976
4977 /* If we change the relative order between pipe/planes enabling, we need
4978 * to change the workaround. */
4979 haswell_mode_set_planes_workaround(intel_crtc);
4980 }
4981
4982 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4983 {
4984 struct drm_device *dev = crtc->base.dev;
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 int pipe = crtc->pipe;
4987
4988 /* To avoid upsetting the power well on haswell only disable the pfit if
4989 * it's in use. The hw state code will make sure we get this right. */
4990 if (crtc->config->pch_pfit.enabled) {
4991 I915_WRITE(PF_CTL(pipe), 0);
4992 I915_WRITE(PF_WIN_POS(pipe), 0);
4993 I915_WRITE(PF_WIN_SZ(pipe), 0);
4994 }
4995 }
4996
4997 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4998 {
4999 struct drm_device *dev = crtc->dev;
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5002 struct intel_encoder *encoder;
5003 int pipe = intel_crtc->pipe;
5004 u32 reg, temp;
5005
5006 if (WARN_ON(!intel_crtc->active))
5007 return;
5008
5009 for_each_encoder_on_crtc(dev, crtc, encoder)
5010 encoder->disable(encoder);
5011
5012 drm_crtc_vblank_off(crtc);
5013 assert_vblank_disabled(crtc);
5014
5015 if (intel_crtc->config->has_pch_encoder)
5016 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5017
5018 intel_disable_pipe(intel_crtc);
5019
5020 ironlake_pfit_disable(intel_crtc);
5021
5022 if (intel_crtc->config->has_pch_encoder)
5023 ironlake_fdi_disable(crtc);
5024
5025 for_each_encoder_on_crtc(dev, crtc, encoder)
5026 if (encoder->post_disable)
5027 encoder->post_disable(encoder);
5028
5029 if (intel_crtc->config->has_pch_encoder) {
5030 ironlake_disable_pch_transcoder(dev_priv, pipe);
5031
5032 if (HAS_PCH_CPT(dev)) {
5033 /* disable TRANS_DP_CTL */
5034 reg = TRANS_DP_CTL(pipe);
5035 temp = I915_READ(reg);
5036 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5037 TRANS_DP_PORT_SEL_MASK);
5038 temp |= TRANS_DP_PORT_SEL_NONE;
5039 I915_WRITE(reg, temp);
5040
5041 /* disable DPLL_SEL */
5042 temp = I915_READ(PCH_DPLL_SEL);
5043 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5044 I915_WRITE(PCH_DPLL_SEL, temp);
5045 }
5046
5047 /* disable PCH DPLL */
5048 intel_disable_shared_dpll(intel_crtc);
5049
5050 ironlake_fdi_pll_disable(intel_crtc);
5051 }
5052
5053 intel_crtc->active = false;
5054 intel_update_watermarks(crtc);
5055
5056 mutex_lock(&dev->struct_mutex);
5057 intel_fbc_update(dev);
5058 mutex_unlock(&dev->struct_mutex);
5059 }
5060
5061 static void haswell_crtc_disable(struct drm_crtc *crtc)
5062 {
5063 struct drm_device *dev = crtc->dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066 struct intel_encoder *encoder;
5067 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5068
5069 if (WARN_ON(!intel_crtc->active))
5070 return;
5071
5072 for_each_encoder_on_crtc(dev, crtc, encoder) {
5073 intel_opregion_notify_encoder(encoder, false);
5074 encoder->disable(encoder);
5075 }
5076
5077 drm_crtc_vblank_off(crtc);
5078 assert_vblank_disabled(crtc);
5079
5080 if (intel_crtc->config->has_pch_encoder)
5081 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5082 false);
5083 intel_disable_pipe(intel_crtc);
5084
5085 if (intel_crtc->config->dp_encoder_is_mst)
5086 intel_ddi_set_vc_payload_alloc(crtc, false);
5087
5088 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5089
5090 if (INTEL_INFO(dev)->gen == 9)
5091 skylake_pfit_update(intel_crtc, 0);
5092 else if (INTEL_INFO(dev)->gen < 9)
5093 ironlake_pfit_disable(intel_crtc);
5094 else
5095 MISSING_CASE(INTEL_INFO(dev)->gen);
5096
5097 intel_ddi_disable_pipe_clock(intel_crtc);
5098
5099 if (intel_crtc->config->has_pch_encoder) {
5100 lpt_disable_pch_transcoder(dev_priv);
5101 intel_ddi_fdi_disable(crtc);
5102 }
5103
5104 for_each_encoder_on_crtc(dev, crtc, encoder)
5105 if (encoder->post_disable)
5106 encoder->post_disable(encoder);
5107
5108 intel_crtc->active = false;
5109 intel_update_watermarks(crtc);
5110
5111 mutex_lock(&dev->struct_mutex);
5112 intel_fbc_update(dev);
5113 mutex_unlock(&dev->struct_mutex);
5114
5115 if (intel_crtc_to_shared_dpll(intel_crtc))
5116 intel_disable_shared_dpll(intel_crtc);
5117 }
5118
5119 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5120 {
5121 struct drm_device *dev = crtc->base.dev;
5122 struct drm_i915_private *dev_priv = dev->dev_private;
5123 struct intel_crtc_state *pipe_config = crtc->config;
5124
5125 if (!pipe_config->gmch_pfit.control)
5126 return;
5127
5128 /*
5129 * The panel fitter should only be adjusted whilst the pipe is disabled,
5130 * according to register description and PRM.
5131 */
5132 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5133 assert_pipe_disabled(dev_priv, crtc->pipe);
5134
5135 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5136 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5137
5138 /* Border color in case we don't scale up to the full screen. Black by
5139 * default, change to something else for debugging. */
5140 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5141 }
5142
5143 static enum intel_display_power_domain port_to_power_domain(enum port port)
5144 {
5145 switch (port) {
5146 case PORT_A:
5147 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5148 case PORT_B:
5149 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5150 case PORT_C:
5151 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5152 case PORT_D:
5153 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5154 default:
5155 WARN_ON_ONCE(1);
5156 return POWER_DOMAIN_PORT_OTHER;
5157 }
5158 }
5159
5160 #define for_each_power_domain(domain, mask) \
5161 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5162 if ((1 << (domain)) & (mask))
5163
5164 enum intel_display_power_domain
5165 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5166 {
5167 struct drm_device *dev = intel_encoder->base.dev;
5168 struct intel_digital_port *intel_dig_port;
5169
5170 switch (intel_encoder->type) {
5171 case INTEL_OUTPUT_UNKNOWN:
5172 /* Only DDI platforms should ever use this output type */
5173 WARN_ON_ONCE(!HAS_DDI(dev));
5174 case INTEL_OUTPUT_DISPLAYPORT:
5175 case INTEL_OUTPUT_HDMI:
5176 case INTEL_OUTPUT_EDP:
5177 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5178 return port_to_power_domain(intel_dig_port->port);
5179 case INTEL_OUTPUT_DP_MST:
5180 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5181 return port_to_power_domain(intel_dig_port->port);
5182 case INTEL_OUTPUT_ANALOG:
5183 return POWER_DOMAIN_PORT_CRT;
5184 case INTEL_OUTPUT_DSI:
5185 return POWER_DOMAIN_PORT_DSI;
5186 default:
5187 return POWER_DOMAIN_PORT_OTHER;
5188 }
5189 }
5190
5191 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5192 {
5193 struct drm_device *dev = crtc->dev;
5194 struct intel_encoder *intel_encoder;
5195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5196 enum pipe pipe = intel_crtc->pipe;
5197 unsigned long mask;
5198 enum transcoder transcoder;
5199
5200 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5201
5202 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5203 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5204 if (intel_crtc->config->pch_pfit.enabled ||
5205 intel_crtc->config->pch_pfit.force_thru)
5206 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5207
5208 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5209 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5210
5211 return mask;
5212 }
5213
5214 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5215 {
5216 struct drm_device *dev = state->dev;
5217 struct drm_i915_private *dev_priv = dev->dev_private;
5218 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5219 struct intel_crtc *crtc;
5220
5221 /*
5222 * First get all needed power domains, then put all unneeded, to avoid
5223 * any unnecessary toggling of the power wells.
5224 */
5225 for_each_intel_crtc(dev, crtc) {
5226 enum intel_display_power_domain domain;
5227
5228 if (!crtc->base.state->enable)
5229 continue;
5230
5231 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5232
5233 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5234 intel_display_power_get(dev_priv, domain);
5235 }
5236
5237 if (dev_priv->display.modeset_global_resources)
5238 dev_priv->display.modeset_global_resources(state);
5239
5240 for_each_intel_crtc(dev, crtc) {
5241 enum intel_display_power_domain domain;
5242
5243 for_each_power_domain(domain, crtc->enabled_power_domains)
5244 intel_display_power_put(dev_priv, domain);
5245
5246 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5247 }
5248
5249 intel_display_set_init_power(dev_priv, false);
5250 }
5251
5252 static void intel_update_max_cdclk(struct drm_device *dev)
5253 {
5254 struct drm_i915_private *dev_priv = dev->dev_private;
5255
5256 if (IS_SKYLAKE(dev)) {
5257 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5258
5259 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5260 dev_priv->max_cdclk_freq = 675000;
5261 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5262 dev_priv->max_cdclk_freq = 540000;
5263 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5264 dev_priv->max_cdclk_freq = 450000;
5265 else
5266 dev_priv->max_cdclk_freq = 337500;
5267 } else if (IS_BROADWELL(dev)) {
5268 /*
5269 * FIXME with extra cooling we can allow
5270 * 540 MHz for ULX and 675 Mhz for ULT.
5271 * How can we know if extra cooling is
5272 * available? PCI ID, VTB, something else?
5273 */
5274 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5275 dev_priv->max_cdclk_freq = 450000;
5276 else if (IS_BDW_ULX(dev))
5277 dev_priv->max_cdclk_freq = 450000;
5278 else if (IS_BDW_ULT(dev))
5279 dev_priv->max_cdclk_freq = 540000;
5280 else
5281 dev_priv->max_cdclk_freq = 675000;
5282 } else if (IS_VALLEYVIEW(dev)) {
5283 dev_priv->max_cdclk_freq = 400000;
5284 } else {
5285 /* otherwise assume cdclk is fixed */
5286 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5287 }
5288
5289 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5290 dev_priv->max_cdclk_freq);
5291 }
5292
5293 static void intel_update_cdclk(struct drm_device *dev)
5294 {
5295 struct drm_i915_private *dev_priv = dev->dev_private;
5296
5297 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5298 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5299 dev_priv->cdclk_freq);
5300
5301 /*
5302 * Program the gmbus_freq based on the cdclk frequency.
5303 * BSpec erroneously claims we should aim for 4MHz, but
5304 * in fact 1MHz is the correct frequency.
5305 */
5306 if (IS_VALLEYVIEW(dev)) {
5307 /*
5308 * Program the gmbus_freq based on the cdclk frequency.
5309 * BSpec erroneously claims we should aim for 4MHz, but
5310 * in fact 1MHz is the correct frequency.
5311 */
5312 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5313 }
5314
5315 if (dev_priv->max_cdclk_freq == 0)
5316 intel_update_max_cdclk(dev);
5317 }
5318
5319 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5320 {
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322 uint32_t divider;
5323 uint32_t ratio;
5324 uint32_t current_freq;
5325 int ret;
5326
5327 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5328 switch (frequency) {
5329 case 144000:
5330 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5331 ratio = BXT_DE_PLL_RATIO(60);
5332 break;
5333 case 288000:
5334 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5335 ratio = BXT_DE_PLL_RATIO(60);
5336 break;
5337 case 384000:
5338 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5339 ratio = BXT_DE_PLL_RATIO(60);
5340 break;
5341 case 576000:
5342 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5343 ratio = BXT_DE_PLL_RATIO(60);
5344 break;
5345 case 624000:
5346 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5347 ratio = BXT_DE_PLL_RATIO(65);
5348 break;
5349 case 19200:
5350 /*
5351 * Bypass frequency with DE PLL disabled. Init ratio, divider
5352 * to suppress GCC warning.
5353 */
5354 ratio = 0;
5355 divider = 0;
5356 break;
5357 default:
5358 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5359
5360 return;
5361 }
5362
5363 mutex_lock(&dev_priv->rps.hw_lock);
5364 /* Inform power controller of upcoming frequency change */
5365 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5366 0x80000000);
5367 mutex_unlock(&dev_priv->rps.hw_lock);
5368
5369 if (ret) {
5370 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5371 ret, frequency);
5372 return;
5373 }
5374
5375 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5376 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5377 current_freq = current_freq * 500 + 1000;
5378
5379 /*
5380 * DE PLL has to be disabled when
5381 * - setting to 19.2MHz (bypass, PLL isn't used)
5382 * - before setting to 624MHz (PLL needs toggling)
5383 * - before setting to any frequency from 624MHz (PLL needs toggling)
5384 */
5385 if (frequency == 19200 || frequency == 624000 ||
5386 current_freq == 624000) {
5387 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5388 /* Timeout 200us */
5389 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5390 1))
5391 DRM_ERROR("timout waiting for DE PLL unlock\n");
5392 }
5393
5394 if (frequency != 19200) {
5395 uint32_t val;
5396
5397 val = I915_READ(BXT_DE_PLL_CTL);
5398 val &= ~BXT_DE_PLL_RATIO_MASK;
5399 val |= ratio;
5400 I915_WRITE(BXT_DE_PLL_CTL, val);
5401
5402 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5403 /* Timeout 200us */
5404 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5405 DRM_ERROR("timeout waiting for DE PLL lock\n");
5406
5407 val = I915_READ(CDCLK_CTL);
5408 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5409 val |= divider;
5410 /*
5411 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5412 * enable otherwise.
5413 */
5414 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5415 if (frequency >= 500000)
5416 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5417
5418 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5419 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5420 val |= (frequency - 1000) / 500;
5421 I915_WRITE(CDCLK_CTL, val);
5422 }
5423
5424 mutex_lock(&dev_priv->rps.hw_lock);
5425 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5426 DIV_ROUND_UP(frequency, 25000));
5427 mutex_unlock(&dev_priv->rps.hw_lock);
5428
5429 if (ret) {
5430 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5431 ret, frequency);
5432 return;
5433 }
5434
5435 intel_update_cdclk(dev);
5436 }
5437
5438 void broxton_init_cdclk(struct drm_device *dev)
5439 {
5440 struct drm_i915_private *dev_priv = dev->dev_private;
5441 uint32_t val;
5442
5443 /*
5444 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5445 * or else the reset will hang because there is no PCH to respond.
5446 * Move the handshake programming to initialization sequence.
5447 * Previously was left up to BIOS.
5448 */
5449 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5450 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5451 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5452
5453 /* Enable PG1 for cdclk */
5454 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5455
5456 /* check if cd clock is enabled */
5457 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5458 DRM_DEBUG_KMS("Display already initialized\n");
5459 return;
5460 }
5461
5462 /*
5463 * FIXME:
5464 * - The initial CDCLK needs to be read from VBT.
5465 * Need to make this change after VBT has changes for BXT.
5466 * - check if setting the max (or any) cdclk freq is really necessary
5467 * here, it belongs to modeset time
5468 */
5469 broxton_set_cdclk(dev, 624000);
5470
5471 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5472 POSTING_READ(DBUF_CTL);
5473
5474 udelay(10);
5475
5476 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5477 DRM_ERROR("DBuf power enable timeout!\n");
5478 }
5479
5480 void broxton_uninit_cdclk(struct drm_device *dev)
5481 {
5482 struct drm_i915_private *dev_priv = dev->dev_private;
5483
5484 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5485 POSTING_READ(DBUF_CTL);
5486
5487 udelay(10);
5488
5489 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5490 DRM_ERROR("DBuf power disable timeout!\n");
5491
5492 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5493 broxton_set_cdclk(dev, 19200);
5494
5495 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5496 }
5497
5498 static const struct skl_cdclk_entry {
5499 unsigned int freq;
5500 unsigned int vco;
5501 } skl_cdclk_frequencies[] = {
5502 { .freq = 308570, .vco = 8640 },
5503 { .freq = 337500, .vco = 8100 },
5504 { .freq = 432000, .vco = 8640 },
5505 { .freq = 450000, .vco = 8100 },
5506 { .freq = 540000, .vco = 8100 },
5507 { .freq = 617140, .vco = 8640 },
5508 { .freq = 675000, .vco = 8100 },
5509 };
5510
5511 static unsigned int skl_cdclk_decimal(unsigned int freq)
5512 {
5513 return (freq - 1000) / 500;
5514 }
5515
5516 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5517 {
5518 unsigned int i;
5519
5520 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5521 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5522
5523 if (e->freq == freq)
5524 return e->vco;
5525 }
5526
5527 return 8100;
5528 }
5529
5530 static void
5531 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5532 {
5533 unsigned int min_freq;
5534 u32 val;
5535
5536 /* select the minimum CDCLK before enabling DPLL 0 */
5537 val = I915_READ(CDCLK_CTL);
5538 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5539 val |= CDCLK_FREQ_337_308;
5540
5541 if (required_vco == 8640)
5542 min_freq = 308570;
5543 else
5544 min_freq = 337500;
5545
5546 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5547
5548 I915_WRITE(CDCLK_CTL, val);
5549 POSTING_READ(CDCLK_CTL);
5550
5551 /*
5552 * We always enable DPLL0 with the lowest link rate possible, but still
5553 * taking into account the VCO required to operate the eDP panel at the
5554 * desired frequency. The usual DP link rates operate with a VCO of
5555 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5556 * The modeset code is responsible for the selection of the exact link
5557 * rate later on, with the constraint of choosing a frequency that
5558 * works with required_vco.
5559 */
5560 val = I915_READ(DPLL_CTRL1);
5561
5562 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5563 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5564 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5565 if (required_vco == 8640)
5566 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5567 SKL_DPLL0);
5568 else
5569 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5570 SKL_DPLL0);
5571
5572 I915_WRITE(DPLL_CTRL1, val);
5573 POSTING_READ(DPLL_CTRL1);
5574
5575 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5576
5577 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5578 DRM_ERROR("DPLL0 not locked\n");
5579 }
5580
5581 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5582 {
5583 int ret;
5584 u32 val;
5585
5586 /* inform PCU we want to change CDCLK */
5587 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5588 mutex_lock(&dev_priv->rps.hw_lock);
5589 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5590 mutex_unlock(&dev_priv->rps.hw_lock);
5591
5592 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5593 }
5594
5595 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5596 {
5597 unsigned int i;
5598
5599 for (i = 0; i < 15; i++) {
5600 if (skl_cdclk_pcu_ready(dev_priv))
5601 return true;
5602 udelay(10);
5603 }
5604
5605 return false;
5606 }
5607
5608 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5609 {
5610 struct drm_device *dev = dev_priv->dev;
5611 u32 freq_select, pcu_ack;
5612
5613 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5614
5615 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5616 DRM_ERROR("failed to inform PCU about cdclk change\n");
5617 return;
5618 }
5619
5620 /* set CDCLK_CTL */
5621 switch(freq) {
5622 case 450000:
5623 case 432000:
5624 freq_select = CDCLK_FREQ_450_432;
5625 pcu_ack = 1;
5626 break;
5627 case 540000:
5628 freq_select = CDCLK_FREQ_540;
5629 pcu_ack = 2;
5630 break;
5631 case 308570:
5632 case 337500:
5633 default:
5634 freq_select = CDCLK_FREQ_337_308;
5635 pcu_ack = 0;
5636 break;
5637 case 617140:
5638 case 675000:
5639 freq_select = CDCLK_FREQ_675_617;
5640 pcu_ack = 3;
5641 break;
5642 }
5643
5644 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5645 POSTING_READ(CDCLK_CTL);
5646
5647 /* inform PCU of the change */
5648 mutex_lock(&dev_priv->rps.hw_lock);
5649 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5650 mutex_unlock(&dev_priv->rps.hw_lock);
5651
5652 intel_update_cdclk(dev);
5653 }
5654
5655 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5656 {
5657 /* disable DBUF power */
5658 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5659 POSTING_READ(DBUF_CTL);
5660
5661 udelay(10);
5662
5663 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5664 DRM_ERROR("DBuf power disable timeout\n");
5665
5666 /* disable DPLL0 */
5667 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5668 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5669 DRM_ERROR("Couldn't disable DPLL0\n");
5670
5671 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5672 }
5673
5674 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5675 {
5676 u32 val;
5677 unsigned int required_vco;
5678
5679 /* enable PCH reset handshake */
5680 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5681 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5682
5683 /* enable PG1 and Misc I/O */
5684 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5685
5686 /* DPLL0 already enabed !? */
5687 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5688 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5689 return;
5690 }
5691
5692 /* enable DPLL0 */
5693 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5694 skl_dpll0_enable(dev_priv, required_vco);
5695
5696 /* set CDCLK to the frequency the BIOS chose */
5697 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5698
5699 /* enable DBUF power */
5700 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5701 POSTING_READ(DBUF_CTL);
5702
5703 udelay(10);
5704
5705 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5706 DRM_ERROR("DBuf power enable timeout\n");
5707 }
5708
5709 /* returns HPLL frequency in kHz */
5710 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5711 {
5712 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5713
5714 /* Obtain SKU information */
5715 mutex_lock(&dev_priv->sb_lock);
5716 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5717 CCK_FUSE_HPLL_FREQ_MASK;
5718 mutex_unlock(&dev_priv->sb_lock);
5719
5720 return vco_freq[hpll_freq] * 1000;
5721 }
5722
5723 /* Adjust CDclk dividers to allow high res or save power if possible */
5724 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5725 {
5726 struct drm_i915_private *dev_priv = dev->dev_private;
5727 u32 val, cmd;
5728
5729 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5730 != dev_priv->cdclk_freq);
5731
5732 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5733 cmd = 2;
5734 else if (cdclk == 266667)
5735 cmd = 1;
5736 else
5737 cmd = 0;
5738
5739 mutex_lock(&dev_priv->rps.hw_lock);
5740 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5741 val &= ~DSPFREQGUAR_MASK;
5742 val |= (cmd << DSPFREQGUAR_SHIFT);
5743 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5744 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5745 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5746 50)) {
5747 DRM_ERROR("timed out waiting for CDclk change\n");
5748 }
5749 mutex_unlock(&dev_priv->rps.hw_lock);
5750
5751 mutex_lock(&dev_priv->sb_lock);
5752
5753 if (cdclk == 400000) {
5754 u32 divider;
5755
5756 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5757
5758 /* adjust cdclk divider */
5759 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5760 val &= ~DISPLAY_FREQUENCY_VALUES;
5761 val |= divider;
5762 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5763
5764 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5765 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5766 50))
5767 DRM_ERROR("timed out waiting for CDclk change\n");
5768 }
5769
5770 /* adjust self-refresh exit latency value */
5771 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5772 val &= ~0x7f;
5773
5774 /*
5775 * For high bandwidth configs, we set a higher latency in the bunit
5776 * so that the core display fetch happens in time to avoid underruns.
5777 */
5778 if (cdclk == 400000)
5779 val |= 4500 / 250; /* 4.5 usec */
5780 else
5781 val |= 3000 / 250; /* 3.0 usec */
5782 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5783
5784 mutex_unlock(&dev_priv->sb_lock);
5785
5786 intel_update_cdclk(dev);
5787 }
5788
5789 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5790 {
5791 struct drm_i915_private *dev_priv = dev->dev_private;
5792 u32 val, cmd;
5793
5794 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5795 != dev_priv->cdclk_freq);
5796
5797 switch (cdclk) {
5798 case 333333:
5799 case 320000:
5800 case 266667:
5801 case 200000:
5802 break;
5803 default:
5804 MISSING_CASE(cdclk);
5805 return;
5806 }
5807
5808 /*
5809 * Specs are full of misinformation, but testing on actual
5810 * hardware has shown that we just need to write the desired
5811 * CCK divider into the Punit register.
5812 */
5813 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5814
5815 mutex_lock(&dev_priv->rps.hw_lock);
5816 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5817 val &= ~DSPFREQGUAR_MASK_CHV;
5818 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5819 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5820 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5821 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5822 50)) {
5823 DRM_ERROR("timed out waiting for CDclk change\n");
5824 }
5825 mutex_unlock(&dev_priv->rps.hw_lock);
5826
5827 intel_update_cdclk(dev);
5828 }
5829
5830 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5831 int max_pixclk)
5832 {
5833 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5834 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5835
5836 /*
5837 * Really only a few cases to deal with, as only 4 CDclks are supported:
5838 * 200MHz
5839 * 267MHz
5840 * 320/333MHz (depends on HPLL freq)
5841 * 400MHz (VLV only)
5842 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5843 * of the lower bin and adjust if needed.
5844 *
5845 * We seem to get an unstable or solid color picture at 200MHz.
5846 * Not sure what's wrong. For now use 200MHz only when all pipes
5847 * are off.
5848 */
5849 if (!IS_CHERRYVIEW(dev_priv) &&
5850 max_pixclk > freq_320*limit/100)
5851 return 400000;
5852 else if (max_pixclk > 266667*limit/100)
5853 return freq_320;
5854 else if (max_pixclk > 0)
5855 return 266667;
5856 else
5857 return 200000;
5858 }
5859
5860 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5861 int max_pixclk)
5862 {
5863 /*
5864 * FIXME:
5865 * - remove the guardband, it's not needed on BXT
5866 * - set 19.2MHz bypass frequency if there are no active pipes
5867 */
5868 if (max_pixclk > 576000*9/10)
5869 return 624000;
5870 else if (max_pixclk > 384000*9/10)
5871 return 576000;
5872 else if (max_pixclk > 288000*9/10)
5873 return 384000;
5874 else if (max_pixclk > 144000*9/10)
5875 return 288000;
5876 else
5877 return 144000;
5878 }
5879
5880 /* Compute the max pixel clock for new configuration. Uses atomic state if
5881 * that's non-NULL, look at current state otherwise. */
5882 static int intel_mode_max_pixclk(struct drm_device *dev,
5883 struct drm_atomic_state *state)
5884 {
5885 struct intel_crtc *intel_crtc;
5886 struct intel_crtc_state *crtc_state;
5887 int max_pixclk = 0;
5888
5889 for_each_intel_crtc(dev, intel_crtc) {
5890 if (state)
5891 crtc_state =
5892 intel_atomic_get_crtc_state(state, intel_crtc);
5893 else
5894 crtc_state = intel_crtc->config;
5895 if (IS_ERR(crtc_state))
5896 return PTR_ERR(crtc_state);
5897
5898 if (!crtc_state->base.enable)
5899 continue;
5900
5901 max_pixclk = max(max_pixclk,
5902 crtc_state->base.adjusted_mode.crtc_clock);
5903 }
5904
5905 return max_pixclk;
5906 }
5907
5908 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5909 {
5910 struct drm_i915_private *dev_priv = to_i915(state->dev);
5911 struct drm_crtc *crtc;
5912 struct drm_crtc_state *crtc_state;
5913 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5914 int cdclk, ret = 0;
5915
5916 if (max_pixclk < 0)
5917 return max_pixclk;
5918
5919 if (IS_VALLEYVIEW(dev_priv))
5920 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5921 else
5922 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5923
5924 if (cdclk == dev_priv->cdclk_freq)
5925 return 0;
5926
5927 /* add all active pipes to the state */
5928 for_each_crtc(state->dev, crtc) {
5929 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5930 if (IS_ERR(crtc_state))
5931 return PTR_ERR(crtc_state);
5932
5933 if (!crtc_state->active || needs_modeset(crtc_state))
5934 continue;
5935
5936 crtc_state->mode_changed = true;
5937
5938 ret = drm_atomic_add_affected_connectors(state, crtc);
5939 if (ret)
5940 break;
5941
5942 ret = drm_atomic_add_affected_planes(state, crtc);
5943 if (ret)
5944 break;
5945 }
5946
5947 return ret;
5948 }
5949
5950 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5951 {
5952 unsigned int credits, default_credits;
5953
5954 if (IS_CHERRYVIEW(dev_priv))
5955 default_credits = PFI_CREDIT(12);
5956 else
5957 default_credits = PFI_CREDIT(8);
5958
5959 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5960 /* CHV suggested value is 31 or 63 */
5961 if (IS_CHERRYVIEW(dev_priv))
5962 credits = PFI_CREDIT_31;
5963 else
5964 credits = PFI_CREDIT(15);
5965 } else {
5966 credits = default_credits;
5967 }
5968
5969 /*
5970 * WA - write default credits before re-programming
5971 * FIXME: should we also set the resend bit here?
5972 */
5973 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5974 default_credits);
5975
5976 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5977 credits | PFI_CREDIT_RESEND);
5978
5979 /*
5980 * FIXME is this guaranteed to clear
5981 * immediately or should we poll for it?
5982 */
5983 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5984 }
5985
5986 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5987 {
5988 struct drm_device *dev = old_state->dev;
5989 struct drm_i915_private *dev_priv = dev->dev_private;
5990 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5991 int req_cdclk;
5992
5993 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5994 * never fail. */
5995 if (WARN_ON(max_pixclk < 0))
5996 return;
5997
5998 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5999
6000 if (req_cdclk != dev_priv->cdclk_freq) {
6001 /*
6002 * FIXME: We can end up here with all power domains off, yet
6003 * with a CDCLK frequency other than the minimum. To account
6004 * for this take the PIPE-A power domain, which covers the HW
6005 * blocks needed for the following programming. This can be
6006 * removed once it's guaranteed that we get here either with
6007 * the minimum CDCLK set, or the required power domains
6008 * enabled.
6009 */
6010 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6011
6012 if (IS_CHERRYVIEW(dev))
6013 cherryview_set_cdclk(dev, req_cdclk);
6014 else
6015 valleyview_set_cdclk(dev, req_cdclk);
6016
6017 vlv_program_pfi_credits(dev_priv);
6018
6019 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6020 }
6021 }
6022
6023 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6024 {
6025 struct drm_device *dev = crtc->dev;
6026 struct drm_i915_private *dev_priv = to_i915(dev);
6027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6028 struct intel_encoder *encoder;
6029 int pipe = intel_crtc->pipe;
6030 bool is_dsi;
6031
6032 if (WARN_ON(intel_crtc->active))
6033 return;
6034
6035 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6036
6037 if (!is_dsi) {
6038 if (IS_CHERRYVIEW(dev))
6039 chv_prepare_pll(intel_crtc, intel_crtc->config);
6040 else
6041 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6042 }
6043
6044 if (intel_crtc->config->has_dp_encoder)
6045 intel_dp_set_m_n(intel_crtc, M1_N1);
6046
6047 intel_set_pipe_timings(intel_crtc);
6048
6049 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051
6052 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6053 I915_WRITE(CHV_CANVAS(pipe), 0);
6054 }
6055
6056 i9xx_set_pipeconf(intel_crtc);
6057
6058 intel_crtc->active = true;
6059
6060 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6061
6062 for_each_encoder_on_crtc(dev, crtc, encoder)
6063 if (encoder->pre_pll_enable)
6064 encoder->pre_pll_enable(encoder);
6065
6066 if (!is_dsi) {
6067 if (IS_CHERRYVIEW(dev))
6068 chv_enable_pll(intel_crtc, intel_crtc->config);
6069 else
6070 vlv_enable_pll(intel_crtc, intel_crtc->config);
6071 }
6072
6073 for_each_encoder_on_crtc(dev, crtc, encoder)
6074 if (encoder->pre_enable)
6075 encoder->pre_enable(encoder);
6076
6077 i9xx_pfit_enable(intel_crtc);
6078
6079 intel_crtc_load_lut(crtc);
6080
6081 intel_update_watermarks(crtc);
6082 intel_enable_pipe(intel_crtc);
6083
6084 assert_vblank_disabled(crtc);
6085 drm_crtc_vblank_on(crtc);
6086
6087 for_each_encoder_on_crtc(dev, crtc, encoder)
6088 encoder->enable(encoder);
6089 }
6090
6091 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6092 {
6093 struct drm_device *dev = crtc->base.dev;
6094 struct drm_i915_private *dev_priv = dev->dev_private;
6095
6096 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6097 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6098 }
6099
6100 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6101 {
6102 struct drm_device *dev = crtc->dev;
6103 struct drm_i915_private *dev_priv = to_i915(dev);
6104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6105 struct intel_encoder *encoder;
6106 int pipe = intel_crtc->pipe;
6107
6108 if (WARN_ON(intel_crtc->active))
6109 return;
6110
6111 i9xx_set_pll_dividers(intel_crtc);
6112
6113 if (intel_crtc->config->has_dp_encoder)
6114 intel_dp_set_m_n(intel_crtc, M1_N1);
6115
6116 intel_set_pipe_timings(intel_crtc);
6117
6118 i9xx_set_pipeconf(intel_crtc);
6119
6120 intel_crtc->active = true;
6121
6122 if (!IS_GEN2(dev))
6123 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6124
6125 for_each_encoder_on_crtc(dev, crtc, encoder)
6126 if (encoder->pre_enable)
6127 encoder->pre_enable(encoder);
6128
6129 i9xx_enable_pll(intel_crtc);
6130
6131 i9xx_pfit_enable(intel_crtc);
6132
6133 intel_crtc_load_lut(crtc);
6134
6135 intel_update_watermarks(crtc);
6136 intel_enable_pipe(intel_crtc);
6137
6138 assert_vblank_disabled(crtc);
6139 drm_crtc_vblank_on(crtc);
6140
6141 for_each_encoder_on_crtc(dev, crtc, encoder)
6142 encoder->enable(encoder);
6143 }
6144
6145 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6146 {
6147 struct drm_device *dev = crtc->base.dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149
6150 if (!crtc->config->gmch_pfit.control)
6151 return;
6152
6153 assert_pipe_disabled(dev_priv, crtc->pipe);
6154
6155 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6156 I915_READ(PFIT_CONTROL));
6157 I915_WRITE(PFIT_CONTROL, 0);
6158 }
6159
6160 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6161 {
6162 struct drm_device *dev = crtc->dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6165 struct intel_encoder *encoder;
6166 int pipe = intel_crtc->pipe;
6167
6168 if (WARN_ON(!intel_crtc->active))
6169 return;
6170
6171 /*
6172 * On gen2 planes are double buffered but the pipe isn't, so we must
6173 * wait for planes to fully turn off before disabling the pipe.
6174 * We also need to wait on all gmch platforms because of the
6175 * self-refresh mode constraint explained above.
6176 */
6177 intel_wait_for_vblank(dev, pipe);
6178
6179 for_each_encoder_on_crtc(dev, crtc, encoder)
6180 encoder->disable(encoder);
6181
6182 drm_crtc_vblank_off(crtc);
6183 assert_vblank_disabled(crtc);
6184
6185 intel_disable_pipe(intel_crtc);
6186
6187 i9xx_pfit_disable(intel_crtc);
6188
6189 for_each_encoder_on_crtc(dev, crtc, encoder)
6190 if (encoder->post_disable)
6191 encoder->post_disable(encoder);
6192
6193 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6194 if (IS_CHERRYVIEW(dev))
6195 chv_disable_pll(dev_priv, pipe);
6196 else if (IS_VALLEYVIEW(dev))
6197 vlv_disable_pll(dev_priv, pipe);
6198 else
6199 i9xx_disable_pll(intel_crtc);
6200 }
6201
6202 if (!IS_GEN2(dev))
6203 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6204
6205 intel_crtc->active = false;
6206 intel_update_watermarks(crtc);
6207
6208 mutex_lock(&dev->struct_mutex);
6209 intel_fbc_update(dev);
6210 mutex_unlock(&dev->struct_mutex);
6211 }
6212
6213 /*
6214 * turn all crtc's off, but do not adjust state
6215 * This has to be paired with a call to intel_modeset_setup_hw_state.
6216 */
6217 void intel_display_suspend(struct drm_device *dev)
6218 {
6219 struct drm_i915_private *dev_priv = to_i915(dev);
6220 struct drm_crtc *crtc;
6221
6222 for_each_crtc(dev, crtc) {
6223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6224 enum intel_display_power_domain domain;
6225 unsigned long domains;
6226
6227 if (!intel_crtc->active)
6228 continue;
6229
6230 intel_crtc_disable_planes(crtc);
6231 dev_priv->display.crtc_disable(crtc);
6232
6233 domains = intel_crtc->enabled_power_domains;
6234 for_each_power_domain(domain, domains)
6235 intel_display_power_put(dev_priv, domain);
6236 intel_crtc->enabled_power_domains = 0;
6237 }
6238 }
6239
6240 /* Master function to enable/disable CRTC and corresponding power wells */
6241 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6242 {
6243 struct drm_device *dev = crtc->dev;
6244 struct drm_i915_private *dev_priv = dev->dev_private;
6245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6246 enum intel_display_power_domain domain;
6247 unsigned long domains;
6248
6249 if (enable == intel_crtc->active)
6250 return;
6251
6252 if (enable && !crtc->state->enable)
6253 return;
6254
6255 crtc->state->active = enable;
6256 if (enable) {
6257 domains = get_crtc_power_domains(crtc);
6258 for_each_power_domain(domain, domains)
6259 intel_display_power_get(dev_priv, domain);
6260 intel_crtc->enabled_power_domains = domains;
6261
6262 dev_priv->display.crtc_enable(crtc);
6263 intel_crtc_enable_planes(crtc);
6264 } else {
6265 intel_crtc_disable_planes(crtc);
6266 dev_priv->display.crtc_disable(crtc);
6267
6268 domains = intel_crtc->enabled_power_domains;
6269 for_each_power_domain(domain, domains)
6270 intel_display_power_put(dev_priv, domain);
6271 intel_crtc->enabled_power_domains = 0;
6272 }
6273 }
6274
6275 /**
6276 * Sets the power management mode of the pipe and plane.
6277 */
6278 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6279 {
6280 struct drm_device *dev = crtc->dev;
6281 struct intel_encoder *intel_encoder;
6282 bool enable = false;
6283
6284 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6285 enable |= intel_encoder->connectors_active;
6286
6287 intel_crtc_control(crtc, enable);
6288 }
6289
6290 void intel_encoder_destroy(struct drm_encoder *encoder)
6291 {
6292 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6293
6294 drm_encoder_cleanup(encoder);
6295 kfree(intel_encoder);
6296 }
6297
6298 /* Simple dpms helper for encoders with just one connector, no cloning and only
6299 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6300 * state of the entire output pipe. */
6301 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6302 {
6303 if (mode == DRM_MODE_DPMS_ON) {
6304 encoder->connectors_active = true;
6305
6306 intel_crtc_update_dpms(encoder->base.crtc);
6307 } else {
6308 encoder->connectors_active = false;
6309
6310 intel_crtc_update_dpms(encoder->base.crtc);
6311 }
6312 }
6313
6314 /* Cross check the actual hw state with our own modeset state tracking (and it's
6315 * internal consistency). */
6316 static void intel_connector_check_state(struct intel_connector *connector)
6317 {
6318 if (connector->get_hw_state(connector)) {
6319 struct intel_encoder *encoder = connector->encoder;
6320 struct drm_crtc *crtc;
6321 bool encoder_enabled;
6322 enum pipe pipe;
6323
6324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6325 connector->base.base.id,
6326 connector->base.name);
6327
6328 /* there is no real hw state for MST connectors */
6329 if (connector->mst_port)
6330 return;
6331
6332 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6333 "wrong connector dpms state\n");
6334 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6335 "active connector not linked to encoder\n");
6336
6337 if (encoder) {
6338 I915_STATE_WARN(!encoder->connectors_active,
6339 "encoder->connectors_active not set\n");
6340
6341 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6342 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6343 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6344 return;
6345
6346 crtc = encoder->base.crtc;
6347
6348 I915_STATE_WARN(!crtc->state->enable,
6349 "crtc not enabled\n");
6350 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6351 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6352 "encoder active on the wrong pipe\n");
6353 }
6354 }
6355 }
6356
6357 int intel_connector_init(struct intel_connector *connector)
6358 {
6359 struct drm_connector_state *connector_state;
6360
6361 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6362 if (!connector_state)
6363 return -ENOMEM;
6364
6365 connector->base.state = connector_state;
6366 return 0;
6367 }
6368
6369 struct intel_connector *intel_connector_alloc(void)
6370 {
6371 struct intel_connector *connector;
6372
6373 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6374 if (!connector)
6375 return NULL;
6376
6377 if (intel_connector_init(connector) < 0) {
6378 kfree(connector);
6379 return NULL;
6380 }
6381
6382 return connector;
6383 }
6384
6385 /* Even simpler default implementation, if there's really no special case to
6386 * consider. */
6387 void intel_connector_dpms(struct drm_connector *connector, int mode)
6388 {
6389 /* All the simple cases only support two dpms states. */
6390 if (mode != DRM_MODE_DPMS_ON)
6391 mode = DRM_MODE_DPMS_OFF;
6392
6393 if (mode == connector->dpms)
6394 return;
6395
6396 connector->dpms = mode;
6397
6398 /* Only need to change hw state when actually enabled */
6399 if (connector->encoder)
6400 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6401
6402 intel_modeset_check_state(connector->dev);
6403 }
6404
6405 /* Simple connector->get_hw_state implementation for encoders that support only
6406 * one connector and no cloning and hence the encoder state determines the state
6407 * of the connector. */
6408 bool intel_connector_get_hw_state(struct intel_connector *connector)
6409 {
6410 enum pipe pipe = 0;
6411 struct intel_encoder *encoder = connector->encoder;
6412
6413 return encoder->get_hw_state(encoder, &pipe);
6414 }
6415
6416 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6417 {
6418 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6419 return crtc_state->fdi_lanes;
6420
6421 return 0;
6422 }
6423
6424 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6425 struct intel_crtc_state *pipe_config)
6426 {
6427 struct drm_atomic_state *state = pipe_config->base.state;
6428 struct intel_crtc *other_crtc;
6429 struct intel_crtc_state *other_crtc_state;
6430
6431 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6432 pipe_name(pipe), pipe_config->fdi_lanes);
6433 if (pipe_config->fdi_lanes > 4) {
6434 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6435 pipe_name(pipe), pipe_config->fdi_lanes);
6436 return -EINVAL;
6437 }
6438
6439 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6440 if (pipe_config->fdi_lanes > 2) {
6441 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6442 pipe_config->fdi_lanes);
6443 return -EINVAL;
6444 } else {
6445 return 0;
6446 }
6447 }
6448
6449 if (INTEL_INFO(dev)->num_pipes == 2)
6450 return 0;
6451
6452 /* Ivybridge 3 pipe is really complicated */
6453 switch (pipe) {
6454 case PIPE_A:
6455 return 0;
6456 case PIPE_B:
6457 if (pipe_config->fdi_lanes <= 2)
6458 return 0;
6459
6460 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6461 other_crtc_state =
6462 intel_atomic_get_crtc_state(state, other_crtc);
6463 if (IS_ERR(other_crtc_state))
6464 return PTR_ERR(other_crtc_state);
6465
6466 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6467 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6468 pipe_name(pipe), pipe_config->fdi_lanes);
6469 return -EINVAL;
6470 }
6471 return 0;
6472 case PIPE_C:
6473 if (pipe_config->fdi_lanes > 2) {
6474 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6475 pipe_name(pipe), pipe_config->fdi_lanes);
6476 return -EINVAL;
6477 }
6478
6479 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6480 other_crtc_state =
6481 intel_atomic_get_crtc_state(state, other_crtc);
6482 if (IS_ERR(other_crtc_state))
6483 return PTR_ERR(other_crtc_state);
6484
6485 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6486 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6487 return -EINVAL;
6488 }
6489 return 0;
6490 default:
6491 BUG();
6492 }
6493 }
6494
6495 #define RETRY 1
6496 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6497 struct intel_crtc_state *pipe_config)
6498 {
6499 struct drm_device *dev = intel_crtc->base.dev;
6500 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6501 int lane, link_bw, fdi_dotclock, ret;
6502 bool needs_recompute = false;
6503
6504 retry:
6505 /* FDI is a binary signal running at ~2.7GHz, encoding
6506 * each output octet as 10 bits. The actual frequency
6507 * is stored as a divider into a 100MHz clock, and the
6508 * mode pixel clock is stored in units of 1KHz.
6509 * Hence the bw of each lane in terms of the mode signal
6510 * is:
6511 */
6512 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6513
6514 fdi_dotclock = adjusted_mode->crtc_clock;
6515
6516 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6517 pipe_config->pipe_bpp);
6518
6519 pipe_config->fdi_lanes = lane;
6520
6521 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6522 link_bw, &pipe_config->fdi_m_n);
6523
6524 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6525 intel_crtc->pipe, pipe_config);
6526 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6527 pipe_config->pipe_bpp -= 2*3;
6528 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6529 pipe_config->pipe_bpp);
6530 needs_recompute = true;
6531 pipe_config->bw_constrained = true;
6532
6533 goto retry;
6534 }
6535
6536 if (needs_recompute)
6537 return RETRY;
6538
6539 return ret;
6540 }
6541
6542 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6543 struct intel_crtc_state *pipe_config)
6544 {
6545 if (pipe_config->pipe_bpp > 24)
6546 return false;
6547
6548 /* HSW can handle pixel rate up to cdclk? */
6549 if (IS_HASWELL(dev_priv->dev))
6550 return true;
6551
6552 /*
6553 * We compare against max which means we must take
6554 * the increased cdclk requirement into account when
6555 * calculating the new cdclk.
6556 *
6557 * Should measure whether using a lower cdclk w/o IPS
6558 */
6559 return ilk_pipe_pixel_rate(pipe_config) <=
6560 dev_priv->max_cdclk_freq * 95 / 100;
6561 }
6562
6563 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6564 struct intel_crtc_state *pipe_config)
6565 {
6566 struct drm_device *dev = crtc->base.dev;
6567 struct drm_i915_private *dev_priv = dev->dev_private;
6568
6569 pipe_config->ips_enabled = i915.enable_ips &&
6570 hsw_crtc_supports_ips(crtc) &&
6571 pipe_config_supports_ips(dev_priv, pipe_config);
6572 }
6573
6574 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6575 struct intel_crtc_state *pipe_config)
6576 {
6577 struct drm_device *dev = crtc->base.dev;
6578 struct drm_i915_private *dev_priv = dev->dev_private;
6579 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6580 int ret;
6581
6582 /* FIXME should check pixel clock limits on all platforms */
6583 if (INTEL_INFO(dev)->gen < 4) {
6584 int clock_limit = dev_priv->max_cdclk_freq;
6585
6586 /*
6587 * Enable pixel doubling when the dot clock
6588 * is > 90% of the (display) core speed.
6589 *
6590 * GDG double wide on either pipe,
6591 * otherwise pipe A only.
6592 */
6593 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6594 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6595 clock_limit *= 2;
6596 pipe_config->double_wide = true;
6597 }
6598
6599 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6600 return -EINVAL;
6601 }
6602
6603 /*
6604 * Pipe horizontal size must be even in:
6605 * - DVO ganged mode
6606 * - LVDS dual channel mode
6607 * - Double wide pipe
6608 */
6609 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6610 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6611 pipe_config->pipe_src_w &= ~1;
6612
6613 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6614 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6615 */
6616 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6617 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6618 return -EINVAL;
6619
6620 if (HAS_IPS(dev))
6621 hsw_compute_ips_config(crtc, pipe_config);
6622
6623 if (pipe_config->has_pch_encoder)
6624 return ironlake_fdi_compute_config(crtc, pipe_config);
6625
6626 /* FIXME: remove below call once atomic mode set is place and all crtc
6627 * related checks called from atomic_crtc_check function */
6628 ret = 0;
6629 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6630 crtc, pipe_config->base.state);
6631 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6632
6633 return ret;
6634 }
6635
6636 static int skylake_get_display_clock_speed(struct drm_device *dev)
6637 {
6638 struct drm_i915_private *dev_priv = to_i915(dev);
6639 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6640 uint32_t cdctl = I915_READ(CDCLK_CTL);
6641 uint32_t linkrate;
6642
6643 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6644 return 24000; /* 24MHz is the cd freq with NSSC ref */
6645
6646 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6647 return 540000;
6648
6649 linkrate = (I915_READ(DPLL_CTRL1) &
6650 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6651
6652 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6653 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6654 /* vco 8640 */
6655 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6656 case CDCLK_FREQ_450_432:
6657 return 432000;
6658 case CDCLK_FREQ_337_308:
6659 return 308570;
6660 case CDCLK_FREQ_675_617:
6661 return 617140;
6662 default:
6663 WARN(1, "Unknown cd freq selection\n");
6664 }
6665 } else {
6666 /* vco 8100 */
6667 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6668 case CDCLK_FREQ_450_432:
6669 return 450000;
6670 case CDCLK_FREQ_337_308:
6671 return 337500;
6672 case CDCLK_FREQ_675_617:
6673 return 675000;
6674 default:
6675 WARN(1, "Unknown cd freq selection\n");
6676 }
6677 }
6678
6679 /* error case, do as if DPLL0 isn't enabled */
6680 return 24000;
6681 }
6682
6683 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6684 {
6685 struct drm_i915_private *dev_priv = dev->dev_private;
6686 uint32_t lcpll = I915_READ(LCPLL_CTL);
6687 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6688
6689 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6690 return 800000;
6691 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6692 return 450000;
6693 else if (freq == LCPLL_CLK_FREQ_450)
6694 return 450000;
6695 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6696 return 540000;
6697 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6698 return 337500;
6699 else
6700 return 675000;
6701 }
6702
6703 static int haswell_get_display_clock_speed(struct drm_device *dev)
6704 {
6705 struct drm_i915_private *dev_priv = dev->dev_private;
6706 uint32_t lcpll = I915_READ(LCPLL_CTL);
6707 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6708
6709 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6710 return 800000;
6711 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6712 return 450000;
6713 else if (freq == LCPLL_CLK_FREQ_450)
6714 return 450000;
6715 else if (IS_HSW_ULT(dev))
6716 return 337500;
6717 else
6718 return 540000;
6719 }
6720
6721 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6722 {
6723 struct drm_i915_private *dev_priv = dev->dev_private;
6724 u32 val;
6725 int divider;
6726
6727 if (dev_priv->hpll_freq == 0)
6728 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6729
6730 mutex_lock(&dev_priv->sb_lock);
6731 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6732 mutex_unlock(&dev_priv->sb_lock);
6733
6734 divider = val & DISPLAY_FREQUENCY_VALUES;
6735
6736 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6737 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6738 "cdclk change in progress\n");
6739
6740 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6741 }
6742
6743 static int ilk_get_display_clock_speed(struct drm_device *dev)
6744 {
6745 return 450000;
6746 }
6747
6748 static int i945_get_display_clock_speed(struct drm_device *dev)
6749 {
6750 return 400000;
6751 }
6752
6753 static int i915_get_display_clock_speed(struct drm_device *dev)
6754 {
6755 return 333333;
6756 }
6757
6758 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6759 {
6760 return 200000;
6761 }
6762
6763 static int pnv_get_display_clock_speed(struct drm_device *dev)
6764 {
6765 u16 gcfgc = 0;
6766
6767 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6768
6769 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6770 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6771 return 266667;
6772 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6773 return 333333;
6774 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6775 return 444444;
6776 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6777 return 200000;
6778 default:
6779 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6780 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6781 return 133333;
6782 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6783 return 166667;
6784 }
6785 }
6786
6787 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6788 {
6789 u16 gcfgc = 0;
6790
6791 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6792
6793 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6794 return 133333;
6795 else {
6796 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6797 case GC_DISPLAY_CLOCK_333_MHZ:
6798 return 333333;
6799 default:
6800 case GC_DISPLAY_CLOCK_190_200_MHZ:
6801 return 190000;
6802 }
6803 }
6804 }
6805
6806 static int i865_get_display_clock_speed(struct drm_device *dev)
6807 {
6808 return 266667;
6809 }
6810
6811 static int i85x_get_display_clock_speed(struct drm_device *dev)
6812 {
6813 u16 hpllcc = 0;
6814
6815 /*
6816 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6817 * encoding is different :(
6818 * FIXME is this the right way to detect 852GM/852GMV?
6819 */
6820 if (dev->pdev->revision == 0x1)
6821 return 133333;
6822
6823 pci_bus_read_config_word(dev->pdev->bus,
6824 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6825
6826 /* Assume that the hardware is in the high speed state. This
6827 * should be the default.
6828 */
6829 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6830 case GC_CLOCK_133_200:
6831 case GC_CLOCK_133_200_2:
6832 case GC_CLOCK_100_200:
6833 return 200000;
6834 case GC_CLOCK_166_250:
6835 return 250000;
6836 case GC_CLOCK_100_133:
6837 return 133333;
6838 case GC_CLOCK_133_266:
6839 case GC_CLOCK_133_266_2:
6840 case GC_CLOCK_166_266:
6841 return 266667;
6842 }
6843
6844 /* Shouldn't happen */
6845 return 0;
6846 }
6847
6848 static int i830_get_display_clock_speed(struct drm_device *dev)
6849 {
6850 return 133333;
6851 }
6852
6853 static unsigned int intel_hpll_vco(struct drm_device *dev)
6854 {
6855 struct drm_i915_private *dev_priv = dev->dev_private;
6856 static const unsigned int blb_vco[8] = {
6857 [0] = 3200000,
6858 [1] = 4000000,
6859 [2] = 5333333,
6860 [3] = 4800000,
6861 [4] = 6400000,
6862 };
6863 static const unsigned int pnv_vco[8] = {
6864 [0] = 3200000,
6865 [1] = 4000000,
6866 [2] = 5333333,
6867 [3] = 4800000,
6868 [4] = 2666667,
6869 };
6870 static const unsigned int cl_vco[8] = {
6871 [0] = 3200000,
6872 [1] = 4000000,
6873 [2] = 5333333,
6874 [3] = 6400000,
6875 [4] = 3333333,
6876 [5] = 3566667,
6877 [6] = 4266667,
6878 };
6879 static const unsigned int elk_vco[8] = {
6880 [0] = 3200000,
6881 [1] = 4000000,
6882 [2] = 5333333,
6883 [3] = 4800000,
6884 };
6885 static const unsigned int ctg_vco[8] = {
6886 [0] = 3200000,
6887 [1] = 4000000,
6888 [2] = 5333333,
6889 [3] = 6400000,
6890 [4] = 2666667,
6891 [5] = 4266667,
6892 };
6893 const unsigned int *vco_table;
6894 unsigned int vco;
6895 uint8_t tmp = 0;
6896
6897 /* FIXME other chipsets? */
6898 if (IS_GM45(dev))
6899 vco_table = ctg_vco;
6900 else if (IS_G4X(dev))
6901 vco_table = elk_vco;
6902 else if (IS_CRESTLINE(dev))
6903 vco_table = cl_vco;
6904 else if (IS_PINEVIEW(dev))
6905 vco_table = pnv_vco;
6906 else if (IS_G33(dev))
6907 vco_table = blb_vco;
6908 else
6909 return 0;
6910
6911 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6912
6913 vco = vco_table[tmp & 0x7];
6914 if (vco == 0)
6915 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6916 else
6917 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6918
6919 return vco;
6920 }
6921
6922 static int gm45_get_display_clock_speed(struct drm_device *dev)
6923 {
6924 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6925 uint16_t tmp = 0;
6926
6927 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6928
6929 cdclk_sel = (tmp >> 12) & 0x1;
6930
6931 switch (vco) {
6932 case 2666667:
6933 case 4000000:
6934 case 5333333:
6935 return cdclk_sel ? 333333 : 222222;
6936 case 3200000:
6937 return cdclk_sel ? 320000 : 228571;
6938 default:
6939 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6940 return 222222;
6941 }
6942 }
6943
6944 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6945 {
6946 static const uint8_t div_3200[] = { 16, 10, 8 };
6947 static const uint8_t div_4000[] = { 20, 12, 10 };
6948 static const uint8_t div_5333[] = { 24, 16, 14 };
6949 const uint8_t *div_table;
6950 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6951 uint16_t tmp = 0;
6952
6953 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6954
6955 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6956
6957 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6958 goto fail;
6959
6960 switch (vco) {
6961 case 3200000:
6962 div_table = div_3200;
6963 break;
6964 case 4000000:
6965 div_table = div_4000;
6966 break;
6967 case 5333333:
6968 div_table = div_5333;
6969 break;
6970 default:
6971 goto fail;
6972 }
6973
6974 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6975
6976 fail:
6977 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6978 return 200000;
6979 }
6980
6981 static int g33_get_display_clock_speed(struct drm_device *dev)
6982 {
6983 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6984 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6985 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6986 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6987 const uint8_t *div_table;
6988 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6989 uint16_t tmp = 0;
6990
6991 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6992
6993 cdclk_sel = (tmp >> 4) & 0x7;
6994
6995 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6996 goto fail;
6997
6998 switch (vco) {
6999 case 3200000:
7000 div_table = div_3200;
7001 break;
7002 case 4000000:
7003 div_table = div_4000;
7004 break;
7005 case 4800000:
7006 div_table = div_4800;
7007 break;
7008 case 5333333:
7009 div_table = div_5333;
7010 break;
7011 default:
7012 goto fail;
7013 }
7014
7015 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7016
7017 fail:
7018 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7019 return 190476;
7020 }
7021
7022 static void
7023 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7024 {
7025 while (*num > DATA_LINK_M_N_MASK ||
7026 *den > DATA_LINK_M_N_MASK) {
7027 *num >>= 1;
7028 *den >>= 1;
7029 }
7030 }
7031
7032 static void compute_m_n(unsigned int m, unsigned int n,
7033 uint32_t *ret_m, uint32_t *ret_n)
7034 {
7035 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7036 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7037 intel_reduce_m_n_ratio(ret_m, ret_n);
7038 }
7039
7040 void
7041 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7042 int pixel_clock, int link_clock,
7043 struct intel_link_m_n *m_n)
7044 {
7045 m_n->tu = 64;
7046
7047 compute_m_n(bits_per_pixel * pixel_clock,
7048 link_clock * nlanes * 8,
7049 &m_n->gmch_m, &m_n->gmch_n);
7050
7051 compute_m_n(pixel_clock, link_clock,
7052 &m_n->link_m, &m_n->link_n);
7053 }
7054
7055 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7056 {
7057 if (i915.panel_use_ssc >= 0)
7058 return i915.panel_use_ssc != 0;
7059 return dev_priv->vbt.lvds_use_ssc
7060 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7061 }
7062
7063 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7064 int num_connectors)
7065 {
7066 struct drm_device *dev = crtc_state->base.crtc->dev;
7067 struct drm_i915_private *dev_priv = dev->dev_private;
7068 int refclk;
7069
7070 WARN_ON(!crtc_state->base.state);
7071
7072 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7073 refclk = 100000;
7074 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7075 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7076 refclk = dev_priv->vbt.lvds_ssc_freq;
7077 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7078 } else if (!IS_GEN2(dev)) {
7079 refclk = 96000;
7080 } else {
7081 refclk = 48000;
7082 }
7083
7084 return refclk;
7085 }
7086
7087 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7088 {
7089 return (1 << dpll->n) << 16 | dpll->m2;
7090 }
7091
7092 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7093 {
7094 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7095 }
7096
7097 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7098 struct intel_crtc_state *crtc_state,
7099 intel_clock_t *reduced_clock)
7100 {
7101 struct drm_device *dev = crtc->base.dev;
7102 u32 fp, fp2 = 0;
7103
7104 if (IS_PINEVIEW(dev)) {
7105 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7106 if (reduced_clock)
7107 fp2 = pnv_dpll_compute_fp(reduced_clock);
7108 } else {
7109 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7110 if (reduced_clock)
7111 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7112 }
7113
7114 crtc_state->dpll_hw_state.fp0 = fp;
7115
7116 crtc->lowfreq_avail = false;
7117 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7118 reduced_clock) {
7119 crtc_state->dpll_hw_state.fp1 = fp2;
7120 crtc->lowfreq_avail = true;
7121 } else {
7122 crtc_state->dpll_hw_state.fp1 = fp;
7123 }
7124 }
7125
7126 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7127 pipe)
7128 {
7129 u32 reg_val;
7130
7131 /*
7132 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7133 * and set it to a reasonable value instead.
7134 */
7135 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7136 reg_val &= 0xffffff00;
7137 reg_val |= 0x00000030;
7138 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7139
7140 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7141 reg_val &= 0x8cffffff;
7142 reg_val = 0x8c000000;
7143 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7144
7145 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7146 reg_val &= 0xffffff00;
7147 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7148
7149 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7150 reg_val &= 0x00ffffff;
7151 reg_val |= 0xb0000000;
7152 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7153 }
7154
7155 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7156 struct intel_link_m_n *m_n)
7157 {
7158 struct drm_device *dev = crtc->base.dev;
7159 struct drm_i915_private *dev_priv = dev->dev_private;
7160 int pipe = crtc->pipe;
7161
7162 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7163 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7164 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7165 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7166 }
7167
7168 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7169 struct intel_link_m_n *m_n,
7170 struct intel_link_m_n *m2_n2)
7171 {
7172 struct drm_device *dev = crtc->base.dev;
7173 struct drm_i915_private *dev_priv = dev->dev_private;
7174 int pipe = crtc->pipe;
7175 enum transcoder transcoder = crtc->config->cpu_transcoder;
7176
7177 if (INTEL_INFO(dev)->gen >= 5) {
7178 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7179 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7180 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7181 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7182 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7183 * for gen < 8) and if DRRS is supported (to make sure the
7184 * registers are not unnecessarily accessed).
7185 */
7186 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7187 crtc->config->has_drrs) {
7188 I915_WRITE(PIPE_DATA_M2(transcoder),
7189 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7190 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7191 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7192 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7193 }
7194 } else {
7195 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7196 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7197 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7198 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7199 }
7200 }
7201
7202 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7203 {
7204 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7205
7206 if (m_n == M1_N1) {
7207 dp_m_n = &crtc->config->dp_m_n;
7208 dp_m2_n2 = &crtc->config->dp_m2_n2;
7209 } else if (m_n == M2_N2) {
7210
7211 /*
7212 * M2_N2 registers are not supported. Hence m2_n2 divider value
7213 * needs to be programmed into M1_N1.
7214 */
7215 dp_m_n = &crtc->config->dp_m2_n2;
7216 } else {
7217 DRM_ERROR("Unsupported divider value\n");
7218 return;
7219 }
7220
7221 if (crtc->config->has_pch_encoder)
7222 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7223 else
7224 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7225 }
7226
7227 static void vlv_update_pll(struct intel_crtc *crtc,
7228 struct intel_crtc_state *pipe_config)
7229 {
7230 u32 dpll, dpll_md;
7231
7232 /*
7233 * Enable DPIO clock input. We should never disable the reference
7234 * clock for pipe B, since VGA hotplug / manual detection depends
7235 * on it.
7236 */
7237 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7238 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7239 /* We should never disable this, set it here for state tracking */
7240 if (crtc->pipe == PIPE_B)
7241 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7242 dpll |= DPLL_VCO_ENABLE;
7243 pipe_config->dpll_hw_state.dpll = dpll;
7244
7245 dpll_md = (pipe_config->pixel_multiplier - 1)
7246 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7247 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7248 }
7249
7250 static void vlv_prepare_pll(struct intel_crtc *crtc,
7251 const struct intel_crtc_state *pipe_config)
7252 {
7253 struct drm_device *dev = crtc->base.dev;
7254 struct drm_i915_private *dev_priv = dev->dev_private;
7255 int pipe = crtc->pipe;
7256 u32 mdiv;
7257 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7258 u32 coreclk, reg_val;
7259
7260 mutex_lock(&dev_priv->sb_lock);
7261
7262 bestn = pipe_config->dpll.n;
7263 bestm1 = pipe_config->dpll.m1;
7264 bestm2 = pipe_config->dpll.m2;
7265 bestp1 = pipe_config->dpll.p1;
7266 bestp2 = pipe_config->dpll.p2;
7267
7268 /* See eDP HDMI DPIO driver vbios notes doc */
7269
7270 /* PLL B needs special handling */
7271 if (pipe == PIPE_B)
7272 vlv_pllb_recal_opamp(dev_priv, pipe);
7273
7274 /* Set up Tx target for periodic Rcomp update */
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7276
7277 /* Disable target IRef on PLL */
7278 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7279 reg_val &= 0x00ffffff;
7280 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7281
7282 /* Disable fast lock */
7283 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7284
7285 /* Set idtafcrecal before PLL is enabled */
7286 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7287 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7288 mdiv |= ((bestn << DPIO_N_SHIFT));
7289 mdiv |= (1 << DPIO_K_SHIFT);
7290
7291 /*
7292 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7293 * but we don't support that).
7294 * Note: don't use the DAC post divider as it seems unstable.
7295 */
7296 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7297 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7298
7299 mdiv |= DPIO_ENABLE_CALIBRATION;
7300 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7301
7302 /* Set HBR and RBR LPF coefficients */
7303 if (pipe_config->port_clock == 162000 ||
7304 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7305 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7306 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7307 0x009f0003);
7308 else
7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7310 0x00d0000f);
7311
7312 if (pipe_config->has_dp_encoder) {
7313 /* Use SSC source */
7314 if (pipe == PIPE_A)
7315 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7316 0x0df40000);
7317 else
7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7319 0x0df70000);
7320 } else { /* HDMI or VGA */
7321 /* Use bend source */
7322 if (pipe == PIPE_A)
7323 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7324 0x0df70000);
7325 else
7326 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7327 0x0df40000);
7328 }
7329
7330 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7331 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7332 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7333 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7334 coreclk |= 0x01000000;
7335 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7336
7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7338 mutex_unlock(&dev_priv->sb_lock);
7339 }
7340
7341 static void chv_update_pll(struct intel_crtc *crtc,
7342 struct intel_crtc_state *pipe_config)
7343 {
7344 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7345 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7346 DPLL_VCO_ENABLE;
7347 if (crtc->pipe != PIPE_A)
7348 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7349
7350 pipe_config->dpll_hw_state.dpll_md =
7351 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7352 }
7353
7354 static void chv_prepare_pll(struct intel_crtc *crtc,
7355 const struct intel_crtc_state *pipe_config)
7356 {
7357 struct drm_device *dev = crtc->base.dev;
7358 struct drm_i915_private *dev_priv = dev->dev_private;
7359 int pipe = crtc->pipe;
7360 int dpll_reg = DPLL(crtc->pipe);
7361 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7362 u32 loopfilter, tribuf_calcntr;
7363 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7364 u32 dpio_val;
7365 int vco;
7366
7367 bestn = pipe_config->dpll.n;
7368 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7369 bestm1 = pipe_config->dpll.m1;
7370 bestm2 = pipe_config->dpll.m2 >> 22;
7371 bestp1 = pipe_config->dpll.p1;
7372 bestp2 = pipe_config->dpll.p2;
7373 vco = pipe_config->dpll.vco;
7374 dpio_val = 0;
7375 loopfilter = 0;
7376
7377 /*
7378 * Enable Refclk and SSC
7379 */
7380 I915_WRITE(dpll_reg,
7381 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7382
7383 mutex_lock(&dev_priv->sb_lock);
7384
7385 /* p1 and p2 divider */
7386 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7387 5 << DPIO_CHV_S1_DIV_SHIFT |
7388 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7389 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7390 1 << DPIO_CHV_K_DIV_SHIFT);
7391
7392 /* Feedback post-divider - m2 */
7393 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7394
7395 /* Feedback refclk divider - n and m1 */
7396 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7397 DPIO_CHV_M1_DIV_BY_2 |
7398 1 << DPIO_CHV_N_DIV_SHIFT);
7399
7400 /* M2 fraction division */
7401 if (bestm2_frac)
7402 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7403
7404 /* M2 fraction division enable */
7405 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7406 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7407 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7408 if (bestm2_frac)
7409 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7410 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7411
7412 /* Program digital lock detect threshold */
7413 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7414 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7415 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7416 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7417 if (!bestm2_frac)
7418 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7419 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7420
7421 /* Loop filter */
7422 if (vco == 5400000) {
7423 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7424 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7425 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7426 tribuf_calcntr = 0x9;
7427 } else if (vco <= 6200000) {
7428 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7429 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7430 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7431 tribuf_calcntr = 0x9;
7432 } else if (vco <= 6480000) {
7433 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7434 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7435 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7436 tribuf_calcntr = 0x8;
7437 } else {
7438 /* Not supported. Apply the same limits as in the max case */
7439 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7440 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7441 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7442 tribuf_calcntr = 0;
7443 }
7444 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7445
7446 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7447 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7448 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7449 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7450
7451 /* AFC Recal */
7452 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7453 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7454 DPIO_AFC_RECAL);
7455
7456 mutex_unlock(&dev_priv->sb_lock);
7457 }
7458
7459 /**
7460 * vlv_force_pll_on - forcibly enable just the PLL
7461 * @dev_priv: i915 private structure
7462 * @pipe: pipe PLL to enable
7463 * @dpll: PLL configuration
7464 *
7465 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7466 * in cases where we need the PLL enabled even when @pipe is not going to
7467 * be enabled.
7468 */
7469 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7470 const struct dpll *dpll)
7471 {
7472 struct intel_crtc *crtc =
7473 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7474 struct intel_crtc_state pipe_config = {
7475 .base.crtc = &crtc->base,
7476 .pixel_multiplier = 1,
7477 .dpll = *dpll,
7478 };
7479
7480 if (IS_CHERRYVIEW(dev)) {
7481 chv_update_pll(crtc, &pipe_config);
7482 chv_prepare_pll(crtc, &pipe_config);
7483 chv_enable_pll(crtc, &pipe_config);
7484 } else {
7485 vlv_update_pll(crtc, &pipe_config);
7486 vlv_prepare_pll(crtc, &pipe_config);
7487 vlv_enable_pll(crtc, &pipe_config);
7488 }
7489 }
7490
7491 /**
7492 * vlv_force_pll_off - forcibly disable just the PLL
7493 * @dev_priv: i915 private structure
7494 * @pipe: pipe PLL to disable
7495 *
7496 * Disable the PLL for @pipe. To be used in cases where we need
7497 * the PLL enabled even when @pipe is not going to be enabled.
7498 */
7499 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7500 {
7501 if (IS_CHERRYVIEW(dev))
7502 chv_disable_pll(to_i915(dev), pipe);
7503 else
7504 vlv_disable_pll(to_i915(dev), pipe);
7505 }
7506
7507 static void i9xx_update_pll(struct intel_crtc *crtc,
7508 struct intel_crtc_state *crtc_state,
7509 intel_clock_t *reduced_clock,
7510 int num_connectors)
7511 {
7512 struct drm_device *dev = crtc->base.dev;
7513 struct drm_i915_private *dev_priv = dev->dev_private;
7514 u32 dpll;
7515 bool is_sdvo;
7516 struct dpll *clock = &crtc_state->dpll;
7517
7518 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7519
7520 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7522
7523 dpll = DPLL_VGA_MODE_DIS;
7524
7525 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7526 dpll |= DPLLB_MODE_LVDS;
7527 else
7528 dpll |= DPLLB_MODE_DAC_SERIAL;
7529
7530 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7531 dpll |= (crtc_state->pixel_multiplier - 1)
7532 << SDVO_MULTIPLIER_SHIFT_HIRES;
7533 }
7534
7535 if (is_sdvo)
7536 dpll |= DPLL_SDVO_HIGH_SPEED;
7537
7538 if (crtc_state->has_dp_encoder)
7539 dpll |= DPLL_SDVO_HIGH_SPEED;
7540
7541 /* compute bitmask from p1 value */
7542 if (IS_PINEVIEW(dev))
7543 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7544 else {
7545 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7546 if (IS_G4X(dev) && reduced_clock)
7547 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7548 }
7549 switch (clock->p2) {
7550 case 5:
7551 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7552 break;
7553 case 7:
7554 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7555 break;
7556 case 10:
7557 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7558 break;
7559 case 14:
7560 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7561 break;
7562 }
7563 if (INTEL_INFO(dev)->gen >= 4)
7564 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7565
7566 if (crtc_state->sdvo_tv_clock)
7567 dpll |= PLL_REF_INPUT_TVCLKINBC;
7568 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7569 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7570 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7571 else
7572 dpll |= PLL_REF_INPUT_DREFCLK;
7573
7574 dpll |= DPLL_VCO_ENABLE;
7575 crtc_state->dpll_hw_state.dpll = dpll;
7576
7577 if (INTEL_INFO(dev)->gen >= 4) {
7578 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7579 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7580 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7581 }
7582 }
7583
7584 static void i8xx_update_pll(struct intel_crtc *crtc,
7585 struct intel_crtc_state *crtc_state,
7586 intel_clock_t *reduced_clock,
7587 int num_connectors)
7588 {
7589 struct drm_device *dev = crtc->base.dev;
7590 struct drm_i915_private *dev_priv = dev->dev_private;
7591 u32 dpll;
7592 struct dpll *clock = &crtc_state->dpll;
7593
7594 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7595
7596 dpll = DPLL_VGA_MODE_DIS;
7597
7598 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7599 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7600 } else {
7601 if (clock->p1 == 2)
7602 dpll |= PLL_P1_DIVIDE_BY_TWO;
7603 else
7604 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7605 if (clock->p2 == 4)
7606 dpll |= PLL_P2_DIVIDE_BY_4;
7607 }
7608
7609 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7610 dpll |= DPLL_DVO_2X_MODE;
7611
7612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7613 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7614 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7615 else
7616 dpll |= PLL_REF_INPUT_DREFCLK;
7617
7618 dpll |= DPLL_VCO_ENABLE;
7619 crtc_state->dpll_hw_state.dpll = dpll;
7620 }
7621
7622 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7623 {
7624 struct drm_device *dev = intel_crtc->base.dev;
7625 struct drm_i915_private *dev_priv = dev->dev_private;
7626 enum pipe pipe = intel_crtc->pipe;
7627 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7628 struct drm_display_mode *adjusted_mode =
7629 &intel_crtc->config->base.adjusted_mode;
7630 uint32_t crtc_vtotal, crtc_vblank_end;
7631 int vsyncshift = 0;
7632
7633 /* We need to be careful not to changed the adjusted mode, for otherwise
7634 * the hw state checker will get angry at the mismatch. */
7635 crtc_vtotal = adjusted_mode->crtc_vtotal;
7636 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7637
7638 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7639 /* the chip adds 2 halflines automatically */
7640 crtc_vtotal -= 1;
7641 crtc_vblank_end -= 1;
7642
7643 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7644 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7645 else
7646 vsyncshift = adjusted_mode->crtc_hsync_start -
7647 adjusted_mode->crtc_htotal / 2;
7648 if (vsyncshift < 0)
7649 vsyncshift += adjusted_mode->crtc_htotal;
7650 }
7651
7652 if (INTEL_INFO(dev)->gen > 3)
7653 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7654
7655 I915_WRITE(HTOTAL(cpu_transcoder),
7656 (adjusted_mode->crtc_hdisplay - 1) |
7657 ((adjusted_mode->crtc_htotal - 1) << 16));
7658 I915_WRITE(HBLANK(cpu_transcoder),
7659 (adjusted_mode->crtc_hblank_start - 1) |
7660 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7661 I915_WRITE(HSYNC(cpu_transcoder),
7662 (adjusted_mode->crtc_hsync_start - 1) |
7663 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7664
7665 I915_WRITE(VTOTAL(cpu_transcoder),
7666 (adjusted_mode->crtc_vdisplay - 1) |
7667 ((crtc_vtotal - 1) << 16));
7668 I915_WRITE(VBLANK(cpu_transcoder),
7669 (adjusted_mode->crtc_vblank_start - 1) |
7670 ((crtc_vblank_end - 1) << 16));
7671 I915_WRITE(VSYNC(cpu_transcoder),
7672 (adjusted_mode->crtc_vsync_start - 1) |
7673 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7674
7675 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7676 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7677 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7678 * bits. */
7679 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7680 (pipe == PIPE_B || pipe == PIPE_C))
7681 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7682
7683 /* pipesrc controls the size that is scaled from, which should
7684 * always be the user's requested size.
7685 */
7686 I915_WRITE(PIPESRC(pipe),
7687 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7688 (intel_crtc->config->pipe_src_h - 1));
7689 }
7690
7691 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7692 struct intel_crtc_state *pipe_config)
7693 {
7694 struct drm_device *dev = crtc->base.dev;
7695 struct drm_i915_private *dev_priv = dev->dev_private;
7696 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7697 uint32_t tmp;
7698
7699 tmp = I915_READ(HTOTAL(cpu_transcoder));
7700 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7701 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7702 tmp = I915_READ(HBLANK(cpu_transcoder));
7703 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7704 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7705 tmp = I915_READ(HSYNC(cpu_transcoder));
7706 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7707 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7708
7709 tmp = I915_READ(VTOTAL(cpu_transcoder));
7710 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7711 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7712 tmp = I915_READ(VBLANK(cpu_transcoder));
7713 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7714 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7715 tmp = I915_READ(VSYNC(cpu_transcoder));
7716 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7717 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7718
7719 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7720 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7721 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7722 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7723 }
7724
7725 tmp = I915_READ(PIPESRC(crtc->pipe));
7726 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7727 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7728
7729 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7730 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7731 }
7732
7733 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7734 struct intel_crtc_state *pipe_config)
7735 {
7736 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7737 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7738 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7739 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7740
7741 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7742 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7743 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7744 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7745
7746 mode->flags = pipe_config->base.adjusted_mode.flags;
7747
7748 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7749 mode->flags |= pipe_config->base.adjusted_mode.flags;
7750 }
7751
7752 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7753 {
7754 struct drm_device *dev = intel_crtc->base.dev;
7755 struct drm_i915_private *dev_priv = dev->dev_private;
7756 uint32_t pipeconf;
7757
7758 pipeconf = 0;
7759
7760 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7761 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7762 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7763
7764 if (intel_crtc->config->double_wide)
7765 pipeconf |= PIPECONF_DOUBLE_WIDE;
7766
7767 /* only g4x and later have fancy bpc/dither controls */
7768 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7769 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7770 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7771 pipeconf |= PIPECONF_DITHER_EN |
7772 PIPECONF_DITHER_TYPE_SP;
7773
7774 switch (intel_crtc->config->pipe_bpp) {
7775 case 18:
7776 pipeconf |= PIPECONF_6BPC;
7777 break;
7778 case 24:
7779 pipeconf |= PIPECONF_8BPC;
7780 break;
7781 case 30:
7782 pipeconf |= PIPECONF_10BPC;
7783 break;
7784 default:
7785 /* Case prevented by intel_choose_pipe_bpp_dither. */
7786 BUG();
7787 }
7788 }
7789
7790 if (HAS_PIPE_CXSR(dev)) {
7791 if (intel_crtc->lowfreq_avail) {
7792 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7793 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7794 } else {
7795 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7796 }
7797 }
7798
7799 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7800 if (INTEL_INFO(dev)->gen < 4 ||
7801 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7802 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7803 else
7804 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7805 } else
7806 pipeconf |= PIPECONF_PROGRESSIVE;
7807
7808 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7809 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7810
7811 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7812 POSTING_READ(PIPECONF(intel_crtc->pipe));
7813 }
7814
7815 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7816 struct intel_crtc_state *crtc_state)
7817 {
7818 struct drm_device *dev = crtc->base.dev;
7819 struct drm_i915_private *dev_priv = dev->dev_private;
7820 int refclk, num_connectors = 0;
7821 intel_clock_t clock, reduced_clock;
7822 bool ok, has_reduced_clock = false;
7823 bool is_lvds = false, is_dsi = false;
7824 struct intel_encoder *encoder;
7825 const intel_limit_t *limit;
7826 struct drm_atomic_state *state = crtc_state->base.state;
7827 struct drm_connector *connector;
7828 struct drm_connector_state *connector_state;
7829 int i;
7830
7831 memset(&crtc_state->dpll_hw_state, 0,
7832 sizeof(crtc_state->dpll_hw_state));
7833
7834 for_each_connector_in_state(state, connector, connector_state, i) {
7835 if (connector_state->crtc != &crtc->base)
7836 continue;
7837
7838 encoder = to_intel_encoder(connector_state->best_encoder);
7839
7840 switch (encoder->type) {
7841 case INTEL_OUTPUT_LVDS:
7842 is_lvds = true;
7843 break;
7844 case INTEL_OUTPUT_DSI:
7845 is_dsi = true;
7846 break;
7847 default:
7848 break;
7849 }
7850
7851 num_connectors++;
7852 }
7853
7854 if (is_dsi)
7855 return 0;
7856
7857 if (!crtc_state->clock_set) {
7858 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7859
7860 /*
7861 * Returns a set of divisors for the desired target clock with
7862 * the given refclk, or FALSE. The returned values represent
7863 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7864 * 2) / p1 / p2.
7865 */
7866 limit = intel_limit(crtc_state, refclk);
7867 ok = dev_priv->display.find_dpll(limit, crtc_state,
7868 crtc_state->port_clock,
7869 refclk, NULL, &clock);
7870 if (!ok) {
7871 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7872 return -EINVAL;
7873 }
7874
7875 if (is_lvds && dev_priv->lvds_downclock_avail) {
7876 /*
7877 * Ensure we match the reduced clock's P to the target
7878 * clock. If the clocks don't match, we can't switch
7879 * the display clock by using the FP0/FP1. In such case
7880 * we will disable the LVDS downclock feature.
7881 */
7882 has_reduced_clock =
7883 dev_priv->display.find_dpll(limit, crtc_state,
7884 dev_priv->lvds_downclock,
7885 refclk, &clock,
7886 &reduced_clock);
7887 }
7888 /* Compat-code for transition, will disappear. */
7889 crtc_state->dpll.n = clock.n;
7890 crtc_state->dpll.m1 = clock.m1;
7891 crtc_state->dpll.m2 = clock.m2;
7892 crtc_state->dpll.p1 = clock.p1;
7893 crtc_state->dpll.p2 = clock.p2;
7894 }
7895
7896 if (IS_GEN2(dev)) {
7897 i8xx_update_pll(crtc, crtc_state,
7898 has_reduced_clock ? &reduced_clock : NULL,
7899 num_connectors);
7900 } else if (IS_CHERRYVIEW(dev)) {
7901 chv_update_pll(crtc, crtc_state);
7902 } else if (IS_VALLEYVIEW(dev)) {
7903 vlv_update_pll(crtc, crtc_state);
7904 } else {
7905 i9xx_update_pll(crtc, crtc_state,
7906 has_reduced_clock ? &reduced_clock : NULL,
7907 num_connectors);
7908 }
7909
7910 return 0;
7911 }
7912
7913 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7914 struct intel_crtc_state *pipe_config)
7915 {
7916 struct drm_device *dev = crtc->base.dev;
7917 struct drm_i915_private *dev_priv = dev->dev_private;
7918 uint32_t tmp;
7919
7920 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7921 return;
7922
7923 tmp = I915_READ(PFIT_CONTROL);
7924 if (!(tmp & PFIT_ENABLE))
7925 return;
7926
7927 /* Check whether the pfit is attached to our pipe. */
7928 if (INTEL_INFO(dev)->gen < 4) {
7929 if (crtc->pipe != PIPE_B)
7930 return;
7931 } else {
7932 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7933 return;
7934 }
7935
7936 pipe_config->gmch_pfit.control = tmp;
7937 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7938 if (INTEL_INFO(dev)->gen < 5)
7939 pipe_config->gmch_pfit.lvds_border_bits =
7940 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7941 }
7942
7943 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7944 struct intel_crtc_state *pipe_config)
7945 {
7946 struct drm_device *dev = crtc->base.dev;
7947 struct drm_i915_private *dev_priv = dev->dev_private;
7948 int pipe = pipe_config->cpu_transcoder;
7949 intel_clock_t clock;
7950 u32 mdiv;
7951 int refclk = 100000;
7952
7953 /* In case of MIPI DPLL will not even be used */
7954 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7955 return;
7956
7957 mutex_lock(&dev_priv->sb_lock);
7958 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7959 mutex_unlock(&dev_priv->sb_lock);
7960
7961 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7962 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7963 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7964 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7965 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7966
7967 vlv_clock(refclk, &clock);
7968
7969 /* clock.dot is the fast clock */
7970 pipe_config->port_clock = clock.dot / 5;
7971 }
7972
7973 static void
7974 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7975 struct intel_initial_plane_config *plane_config)
7976 {
7977 struct drm_device *dev = crtc->base.dev;
7978 struct drm_i915_private *dev_priv = dev->dev_private;
7979 u32 val, base, offset;
7980 int pipe = crtc->pipe, plane = crtc->plane;
7981 int fourcc, pixel_format;
7982 unsigned int aligned_height;
7983 struct drm_framebuffer *fb;
7984 struct intel_framebuffer *intel_fb;
7985
7986 val = I915_READ(DSPCNTR(plane));
7987 if (!(val & DISPLAY_PLANE_ENABLE))
7988 return;
7989
7990 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7991 if (!intel_fb) {
7992 DRM_DEBUG_KMS("failed to alloc fb\n");
7993 return;
7994 }
7995
7996 fb = &intel_fb->base;
7997
7998 if (INTEL_INFO(dev)->gen >= 4) {
7999 if (val & DISPPLANE_TILED) {
8000 plane_config->tiling = I915_TILING_X;
8001 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8002 }
8003 }
8004
8005 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8006 fourcc = i9xx_format_to_fourcc(pixel_format);
8007 fb->pixel_format = fourcc;
8008 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8009
8010 if (INTEL_INFO(dev)->gen >= 4) {
8011 if (plane_config->tiling)
8012 offset = I915_READ(DSPTILEOFF(plane));
8013 else
8014 offset = I915_READ(DSPLINOFF(plane));
8015 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8016 } else {
8017 base = I915_READ(DSPADDR(plane));
8018 }
8019 plane_config->base = base;
8020
8021 val = I915_READ(PIPESRC(pipe));
8022 fb->width = ((val >> 16) & 0xfff) + 1;
8023 fb->height = ((val >> 0) & 0xfff) + 1;
8024
8025 val = I915_READ(DSPSTRIDE(pipe));
8026 fb->pitches[0] = val & 0xffffffc0;
8027
8028 aligned_height = intel_fb_align_height(dev, fb->height,
8029 fb->pixel_format,
8030 fb->modifier[0]);
8031
8032 plane_config->size = fb->pitches[0] * aligned_height;
8033
8034 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8035 pipe_name(pipe), plane, fb->width, fb->height,
8036 fb->bits_per_pixel, base, fb->pitches[0],
8037 plane_config->size);
8038
8039 plane_config->fb = intel_fb;
8040 }
8041
8042 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8043 struct intel_crtc_state *pipe_config)
8044 {
8045 struct drm_device *dev = crtc->base.dev;
8046 struct drm_i915_private *dev_priv = dev->dev_private;
8047 int pipe = pipe_config->cpu_transcoder;
8048 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8049 intel_clock_t clock;
8050 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8051 int refclk = 100000;
8052
8053 mutex_lock(&dev_priv->sb_lock);
8054 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8055 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8056 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8057 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8058 mutex_unlock(&dev_priv->sb_lock);
8059
8060 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8061 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8062 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8063 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8064 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8065
8066 chv_clock(refclk, &clock);
8067
8068 /* clock.dot is the fast clock */
8069 pipe_config->port_clock = clock.dot / 5;
8070 }
8071
8072 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8073 struct intel_crtc_state *pipe_config)
8074 {
8075 struct drm_device *dev = crtc->base.dev;
8076 struct drm_i915_private *dev_priv = dev->dev_private;
8077 uint32_t tmp;
8078
8079 if (!intel_display_power_is_enabled(dev_priv,
8080 POWER_DOMAIN_PIPE(crtc->pipe)))
8081 return false;
8082
8083 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8084 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8085
8086 tmp = I915_READ(PIPECONF(crtc->pipe));
8087 if (!(tmp & PIPECONF_ENABLE))
8088 return false;
8089
8090 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8091 switch (tmp & PIPECONF_BPC_MASK) {
8092 case PIPECONF_6BPC:
8093 pipe_config->pipe_bpp = 18;
8094 break;
8095 case PIPECONF_8BPC:
8096 pipe_config->pipe_bpp = 24;
8097 break;
8098 case PIPECONF_10BPC:
8099 pipe_config->pipe_bpp = 30;
8100 break;
8101 default:
8102 break;
8103 }
8104 }
8105
8106 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8107 pipe_config->limited_color_range = true;
8108
8109 if (INTEL_INFO(dev)->gen < 4)
8110 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8111
8112 intel_get_pipe_timings(crtc, pipe_config);
8113
8114 i9xx_get_pfit_config(crtc, pipe_config);
8115
8116 if (INTEL_INFO(dev)->gen >= 4) {
8117 tmp = I915_READ(DPLL_MD(crtc->pipe));
8118 pipe_config->pixel_multiplier =
8119 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8120 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8121 pipe_config->dpll_hw_state.dpll_md = tmp;
8122 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8123 tmp = I915_READ(DPLL(crtc->pipe));
8124 pipe_config->pixel_multiplier =
8125 ((tmp & SDVO_MULTIPLIER_MASK)
8126 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8127 } else {
8128 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8129 * port and will be fixed up in the encoder->get_config
8130 * function. */
8131 pipe_config->pixel_multiplier = 1;
8132 }
8133 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8134 if (!IS_VALLEYVIEW(dev)) {
8135 /*
8136 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8137 * on 830. Filter it out here so that we don't
8138 * report errors due to that.
8139 */
8140 if (IS_I830(dev))
8141 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8142
8143 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8144 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8145 } else {
8146 /* Mask out read-only status bits. */
8147 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8148 DPLL_PORTC_READY_MASK |
8149 DPLL_PORTB_READY_MASK);
8150 }
8151
8152 if (IS_CHERRYVIEW(dev))
8153 chv_crtc_clock_get(crtc, pipe_config);
8154 else if (IS_VALLEYVIEW(dev))
8155 vlv_crtc_clock_get(crtc, pipe_config);
8156 else
8157 i9xx_crtc_clock_get(crtc, pipe_config);
8158
8159 return true;
8160 }
8161
8162 static void ironlake_init_pch_refclk(struct drm_device *dev)
8163 {
8164 struct drm_i915_private *dev_priv = dev->dev_private;
8165 struct intel_encoder *encoder;
8166 u32 val, final;
8167 bool has_lvds = false;
8168 bool has_cpu_edp = false;
8169 bool has_panel = false;
8170 bool has_ck505 = false;
8171 bool can_ssc = false;
8172
8173 /* We need to take the global config into account */
8174 for_each_intel_encoder(dev, encoder) {
8175 switch (encoder->type) {
8176 case INTEL_OUTPUT_LVDS:
8177 has_panel = true;
8178 has_lvds = true;
8179 break;
8180 case INTEL_OUTPUT_EDP:
8181 has_panel = true;
8182 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8183 has_cpu_edp = true;
8184 break;
8185 default:
8186 break;
8187 }
8188 }
8189
8190 if (HAS_PCH_IBX(dev)) {
8191 has_ck505 = dev_priv->vbt.display_clock_mode;
8192 can_ssc = has_ck505;
8193 } else {
8194 has_ck505 = false;
8195 can_ssc = true;
8196 }
8197
8198 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8199 has_panel, has_lvds, has_ck505);
8200
8201 /* Ironlake: try to setup display ref clock before DPLL
8202 * enabling. This is only under driver's control after
8203 * PCH B stepping, previous chipset stepping should be
8204 * ignoring this setting.
8205 */
8206 val = I915_READ(PCH_DREF_CONTROL);
8207
8208 /* As we must carefully and slowly disable/enable each source in turn,
8209 * compute the final state we want first and check if we need to
8210 * make any changes at all.
8211 */
8212 final = val;
8213 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8214 if (has_ck505)
8215 final |= DREF_NONSPREAD_CK505_ENABLE;
8216 else
8217 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8218
8219 final &= ~DREF_SSC_SOURCE_MASK;
8220 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8221 final &= ~DREF_SSC1_ENABLE;
8222
8223 if (has_panel) {
8224 final |= DREF_SSC_SOURCE_ENABLE;
8225
8226 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8227 final |= DREF_SSC1_ENABLE;
8228
8229 if (has_cpu_edp) {
8230 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8231 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8232 else
8233 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8234 } else
8235 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8236 } else {
8237 final |= DREF_SSC_SOURCE_DISABLE;
8238 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8239 }
8240
8241 if (final == val)
8242 return;
8243
8244 /* Always enable nonspread source */
8245 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8246
8247 if (has_ck505)
8248 val |= DREF_NONSPREAD_CK505_ENABLE;
8249 else
8250 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8251
8252 if (has_panel) {
8253 val &= ~DREF_SSC_SOURCE_MASK;
8254 val |= DREF_SSC_SOURCE_ENABLE;
8255
8256 /* SSC must be turned on before enabling the CPU output */
8257 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8258 DRM_DEBUG_KMS("Using SSC on panel\n");
8259 val |= DREF_SSC1_ENABLE;
8260 } else
8261 val &= ~DREF_SSC1_ENABLE;
8262
8263 /* Get SSC going before enabling the outputs */
8264 I915_WRITE(PCH_DREF_CONTROL, val);
8265 POSTING_READ(PCH_DREF_CONTROL);
8266 udelay(200);
8267
8268 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8269
8270 /* Enable CPU source on CPU attached eDP */
8271 if (has_cpu_edp) {
8272 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8273 DRM_DEBUG_KMS("Using SSC on eDP\n");
8274 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8275 } else
8276 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8277 } else
8278 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8279
8280 I915_WRITE(PCH_DREF_CONTROL, val);
8281 POSTING_READ(PCH_DREF_CONTROL);
8282 udelay(200);
8283 } else {
8284 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8285
8286 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8287
8288 /* Turn off CPU output */
8289 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8290
8291 I915_WRITE(PCH_DREF_CONTROL, val);
8292 POSTING_READ(PCH_DREF_CONTROL);
8293 udelay(200);
8294
8295 /* Turn off the SSC source */
8296 val &= ~DREF_SSC_SOURCE_MASK;
8297 val |= DREF_SSC_SOURCE_DISABLE;
8298
8299 /* Turn off SSC1 */
8300 val &= ~DREF_SSC1_ENABLE;
8301
8302 I915_WRITE(PCH_DREF_CONTROL, val);
8303 POSTING_READ(PCH_DREF_CONTROL);
8304 udelay(200);
8305 }
8306
8307 BUG_ON(val != final);
8308 }
8309
8310 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8311 {
8312 uint32_t tmp;
8313
8314 tmp = I915_READ(SOUTH_CHICKEN2);
8315 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8316 I915_WRITE(SOUTH_CHICKEN2, tmp);
8317
8318 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8319 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8320 DRM_ERROR("FDI mPHY reset assert timeout\n");
8321
8322 tmp = I915_READ(SOUTH_CHICKEN2);
8323 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8324 I915_WRITE(SOUTH_CHICKEN2, tmp);
8325
8326 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8327 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8328 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8329 }
8330
8331 /* WaMPhyProgramming:hsw */
8332 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8333 {
8334 uint32_t tmp;
8335
8336 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8337 tmp &= ~(0xFF << 24);
8338 tmp |= (0x12 << 24);
8339 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8340
8341 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8342 tmp |= (1 << 11);
8343 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8344
8345 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8346 tmp |= (1 << 11);
8347 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8348
8349 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8350 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8351 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8352
8353 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8354 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8355 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8356
8357 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8358 tmp &= ~(7 << 13);
8359 tmp |= (5 << 13);
8360 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8361
8362 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8363 tmp &= ~(7 << 13);
8364 tmp |= (5 << 13);
8365 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8366
8367 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8368 tmp &= ~0xFF;
8369 tmp |= 0x1C;
8370 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8371
8372 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8373 tmp &= ~0xFF;
8374 tmp |= 0x1C;
8375 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8376
8377 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8378 tmp &= ~(0xFF << 16);
8379 tmp |= (0x1C << 16);
8380 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8381
8382 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8383 tmp &= ~(0xFF << 16);
8384 tmp |= (0x1C << 16);
8385 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8386
8387 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8388 tmp |= (1 << 27);
8389 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8390
8391 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8392 tmp |= (1 << 27);
8393 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8394
8395 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8396 tmp &= ~(0xF << 28);
8397 tmp |= (4 << 28);
8398 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8399
8400 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8401 tmp &= ~(0xF << 28);
8402 tmp |= (4 << 28);
8403 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8404 }
8405
8406 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8407 * Programming" based on the parameters passed:
8408 * - Sequence to enable CLKOUT_DP
8409 * - Sequence to enable CLKOUT_DP without spread
8410 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8411 */
8412 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8413 bool with_fdi)
8414 {
8415 struct drm_i915_private *dev_priv = dev->dev_private;
8416 uint32_t reg, tmp;
8417
8418 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8419 with_spread = true;
8420 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8421 with_fdi, "LP PCH doesn't have FDI\n"))
8422 with_fdi = false;
8423
8424 mutex_lock(&dev_priv->sb_lock);
8425
8426 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8427 tmp &= ~SBI_SSCCTL_DISABLE;
8428 tmp |= SBI_SSCCTL_PATHALT;
8429 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8430
8431 udelay(24);
8432
8433 if (with_spread) {
8434 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8435 tmp &= ~SBI_SSCCTL_PATHALT;
8436 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8437
8438 if (with_fdi) {
8439 lpt_reset_fdi_mphy(dev_priv);
8440 lpt_program_fdi_mphy(dev_priv);
8441 }
8442 }
8443
8444 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8445 SBI_GEN0 : SBI_DBUFF0;
8446 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8447 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8448 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8449
8450 mutex_unlock(&dev_priv->sb_lock);
8451 }
8452
8453 /* Sequence to disable CLKOUT_DP */
8454 static void lpt_disable_clkout_dp(struct drm_device *dev)
8455 {
8456 struct drm_i915_private *dev_priv = dev->dev_private;
8457 uint32_t reg, tmp;
8458
8459 mutex_lock(&dev_priv->sb_lock);
8460
8461 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8462 SBI_GEN0 : SBI_DBUFF0;
8463 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8464 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8465 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8466
8467 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8468 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8469 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8470 tmp |= SBI_SSCCTL_PATHALT;
8471 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8472 udelay(32);
8473 }
8474 tmp |= SBI_SSCCTL_DISABLE;
8475 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8476 }
8477
8478 mutex_unlock(&dev_priv->sb_lock);
8479 }
8480
8481 static void lpt_init_pch_refclk(struct drm_device *dev)
8482 {
8483 struct intel_encoder *encoder;
8484 bool has_vga = false;
8485
8486 for_each_intel_encoder(dev, encoder) {
8487 switch (encoder->type) {
8488 case INTEL_OUTPUT_ANALOG:
8489 has_vga = true;
8490 break;
8491 default:
8492 break;
8493 }
8494 }
8495
8496 if (has_vga)
8497 lpt_enable_clkout_dp(dev, true, true);
8498 else
8499 lpt_disable_clkout_dp(dev);
8500 }
8501
8502 /*
8503 * Initialize reference clocks when the driver loads
8504 */
8505 void intel_init_pch_refclk(struct drm_device *dev)
8506 {
8507 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8508 ironlake_init_pch_refclk(dev);
8509 else if (HAS_PCH_LPT(dev))
8510 lpt_init_pch_refclk(dev);
8511 }
8512
8513 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8514 {
8515 struct drm_device *dev = crtc_state->base.crtc->dev;
8516 struct drm_i915_private *dev_priv = dev->dev_private;
8517 struct drm_atomic_state *state = crtc_state->base.state;
8518 struct drm_connector *connector;
8519 struct drm_connector_state *connector_state;
8520 struct intel_encoder *encoder;
8521 int num_connectors = 0, i;
8522 bool is_lvds = false;
8523
8524 for_each_connector_in_state(state, connector, connector_state, i) {
8525 if (connector_state->crtc != crtc_state->base.crtc)
8526 continue;
8527
8528 encoder = to_intel_encoder(connector_state->best_encoder);
8529
8530 switch (encoder->type) {
8531 case INTEL_OUTPUT_LVDS:
8532 is_lvds = true;
8533 break;
8534 default:
8535 break;
8536 }
8537 num_connectors++;
8538 }
8539
8540 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8541 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8542 dev_priv->vbt.lvds_ssc_freq);
8543 return dev_priv->vbt.lvds_ssc_freq;
8544 }
8545
8546 return 120000;
8547 }
8548
8549 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8550 {
8551 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8553 int pipe = intel_crtc->pipe;
8554 uint32_t val;
8555
8556 val = 0;
8557
8558 switch (intel_crtc->config->pipe_bpp) {
8559 case 18:
8560 val |= PIPECONF_6BPC;
8561 break;
8562 case 24:
8563 val |= PIPECONF_8BPC;
8564 break;
8565 case 30:
8566 val |= PIPECONF_10BPC;
8567 break;
8568 case 36:
8569 val |= PIPECONF_12BPC;
8570 break;
8571 default:
8572 /* Case prevented by intel_choose_pipe_bpp_dither. */
8573 BUG();
8574 }
8575
8576 if (intel_crtc->config->dither)
8577 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8578
8579 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8580 val |= PIPECONF_INTERLACED_ILK;
8581 else
8582 val |= PIPECONF_PROGRESSIVE;
8583
8584 if (intel_crtc->config->limited_color_range)
8585 val |= PIPECONF_COLOR_RANGE_SELECT;
8586
8587 I915_WRITE(PIPECONF(pipe), val);
8588 POSTING_READ(PIPECONF(pipe));
8589 }
8590
8591 /*
8592 * Set up the pipe CSC unit.
8593 *
8594 * Currently only full range RGB to limited range RGB conversion
8595 * is supported, but eventually this should handle various
8596 * RGB<->YCbCr scenarios as well.
8597 */
8598 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8599 {
8600 struct drm_device *dev = crtc->dev;
8601 struct drm_i915_private *dev_priv = dev->dev_private;
8602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8603 int pipe = intel_crtc->pipe;
8604 uint16_t coeff = 0x7800; /* 1.0 */
8605
8606 /*
8607 * TODO: Check what kind of values actually come out of the pipe
8608 * with these coeff/postoff values and adjust to get the best
8609 * accuracy. Perhaps we even need to take the bpc value into
8610 * consideration.
8611 */
8612
8613 if (intel_crtc->config->limited_color_range)
8614 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8615
8616 /*
8617 * GY/GU and RY/RU should be the other way around according
8618 * to BSpec, but reality doesn't agree. Just set them up in
8619 * a way that results in the correct picture.
8620 */
8621 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8622 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8623
8624 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8625 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8626
8627 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8628 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8629
8630 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8631 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8632 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8633
8634 if (INTEL_INFO(dev)->gen > 6) {
8635 uint16_t postoff = 0;
8636
8637 if (intel_crtc->config->limited_color_range)
8638 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8639
8640 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8641 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8642 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8643
8644 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8645 } else {
8646 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8647
8648 if (intel_crtc->config->limited_color_range)
8649 mode |= CSC_BLACK_SCREEN_OFFSET;
8650
8651 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8652 }
8653 }
8654
8655 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8656 {
8657 struct drm_device *dev = crtc->dev;
8658 struct drm_i915_private *dev_priv = dev->dev_private;
8659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8660 enum pipe pipe = intel_crtc->pipe;
8661 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8662 uint32_t val;
8663
8664 val = 0;
8665
8666 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8667 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8668
8669 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8670 val |= PIPECONF_INTERLACED_ILK;
8671 else
8672 val |= PIPECONF_PROGRESSIVE;
8673
8674 I915_WRITE(PIPECONF(cpu_transcoder), val);
8675 POSTING_READ(PIPECONF(cpu_transcoder));
8676
8677 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8678 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8679
8680 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8681 val = 0;
8682
8683 switch (intel_crtc->config->pipe_bpp) {
8684 case 18:
8685 val |= PIPEMISC_DITHER_6_BPC;
8686 break;
8687 case 24:
8688 val |= PIPEMISC_DITHER_8_BPC;
8689 break;
8690 case 30:
8691 val |= PIPEMISC_DITHER_10_BPC;
8692 break;
8693 case 36:
8694 val |= PIPEMISC_DITHER_12_BPC;
8695 break;
8696 default:
8697 /* Case prevented by pipe_config_set_bpp. */
8698 BUG();
8699 }
8700
8701 if (intel_crtc->config->dither)
8702 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8703
8704 I915_WRITE(PIPEMISC(pipe), val);
8705 }
8706 }
8707
8708 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8709 struct intel_crtc_state *crtc_state,
8710 intel_clock_t *clock,
8711 bool *has_reduced_clock,
8712 intel_clock_t *reduced_clock)
8713 {
8714 struct drm_device *dev = crtc->dev;
8715 struct drm_i915_private *dev_priv = dev->dev_private;
8716 int refclk;
8717 const intel_limit_t *limit;
8718 bool ret, is_lvds = false;
8719
8720 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8721
8722 refclk = ironlake_get_refclk(crtc_state);
8723
8724 /*
8725 * Returns a set of divisors for the desired target clock with the given
8726 * refclk, or FALSE. The returned values represent the clock equation:
8727 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8728 */
8729 limit = intel_limit(crtc_state, refclk);
8730 ret = dev_priv->display.find_dpll(limit, crtc_state,
8731 crtc_state->port_clock,
8732 refclk, NULL, clock);
8733 if (!ret)
8734 return false;
8735
8736 if (is_lvds && dev_priv->lvds_downclock_avail) {
8737 /*
8738 * Ensure we match the reduced clock's P to the target clock.
8739 * If the clocks don't match, we can't switch the display clock
8740 * by using the FP0/FP1. In such case we will disable the LVDS
8741 * downclock feature.
8742 */
8743 *has_reduced_clock =
8744 dev_priv->display.find_dpll(limit, crtc_state,
8745 dev_priv->lvds_downclock,
8746 refclk, clock,
8747 reduced_clock);
8748 }
8749
8750 return true;
8751 }
8752
8753 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8754 {
8755 /*
8756 * Account for spread spectrum to avoid
8757 * oversubscribing the link. Max center spread
8758 * is 2.5%; use 5% for safety's sake.
8759 */
8760 u32 bps = target_clock * bpp * 21 / 20;
8761 return DIV_ROUND_UP(bps, link_bw * 8);
8762 }
8763
8764 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8765 {
8766 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8767 }
8768
8769 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8770 struct intel_crtc_state *crtc_state,
8771 u32 *fp,
8772 intel_clock_t *reduced_clock, u32 *fp2)
8773 {
8774 struct drm_crtc *crtc = &intel_crtc->base;
8775 struct drm_device *dev = crtc->dev;
8776 struct drm_i915_private *dev_priv = dev->dev_private;
8777 struct drm_atomic_state *state = crtc_state->base.state;
8778 struct drm_connector *connector;
8779 struct drm_connector_state *connector_state;
8780 struct intel_encoder *encoder;
8781 uint32_t dpll;
8782 int factor, num_connectors = 0, i;
8783 bool is_lvds = false, is_sdvo = false;
8784
8785 for_each_connector_in_state(state, connector, connector_state, i) {
8786 if (connector_state->crtc != crtc_state->base.crtc)
8787 continue;
8788
8789 encoder = to_intel_encoder(connector_state->best_encoder);
8790
8791 switch (encoder->type) {
8792 case INTEL_OUTPUT_LVDS:
8793 is_lvds = true;
8794 break;
8795 case INTEL_OUTPUT_SDVO:
8796 case INTEL_OUTPUT_HDMI:
8797 is_sdvo = true;
8798 break;
8799 default:
8800 break;
8801 }
8802
8803 num_connectors++;
8804 }
8805
8806 /* Enable autotuning of the PLL clock (if permissible) */
8807 factor = 21;
8808 if (is_lvds) {
8809 if ((intel_panel_use_ssc(dev_priv) &&
8810 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8811 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8812 factor = 25;
8813 } else if (crtc_state->sdvo_tv_clock)
8814 factor = 20;
8815
8816 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8817 *fp |= FP_CB_TUNE;
8818
8819 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8820 *fp2 |= FP_CB_TUNE;
8821
8822 dpll = 0;
8823
8824 if (is_lvds)
8825 dpll |= DPLLB_MODE_LVDS;
8826 else
8827 dpll |= DPLLB_MODE_DAC_SERIAL;
8828
8829 dpll |= (crtc_state->pixel_multiplier - 1)
8830 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8831
8832 if (is_sdvo)
8833 dpll |= DPLL_SDVO_HIGH_SPEED;
8834 if (crtc_state->has_dp_encoder)
8835 dpll |= DPLL_SDVO_HIGH_SPEED;
8836
8837 /* compute bitmask from p1 value */
8838 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8839 /* also FPA1 */
8840 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8841
8842 switch (crtc_state->dpll.p2) {
8843 case 5:
8844 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8845 break;
8846 case 7:
8847 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8848 break;
8849 case 10:
8850 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8851 break;
8852 case 14:
8853 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8854 break;
8855 }
8856
8857 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8858 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8859 else
8860 dpll |= PLL_REF_INPUT_DREFCLK;
8861
8862 return dpll | DPLL_VCO_ENABLE;
8863 }
8864
8865 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8866 struct intel_crtc_state *crtc_state)
8867 {
8868 struct drm_device *dev = crtc->base.dev;
8869 intel_clock_t clock, reduced_clock;
8870 u32 dpll = 0, fp = 0, fp2 = 0;
8871 bool ok, has_reduced_clock = false;
8872 bool is_lvds = false;
8873 struct intel_shared_dpll *pll;
8874
8875 memset(&crtc_state->dpll_hw_state, 0,
8876 sizeof(crtc_state->dpll_hw_state));
8877
8878 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8879
8880 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8881 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8882
8883 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8884 &has_reduced_clock, &reduced_clock);
8885 if (!ok && !crtc_state->clock_set) {
8886 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8887 return -EINVAL;
8888 }
8889 /* Compat-code for transition, will disappear. */
8890 if (!crtc_state->clock_set) {
8891 crtc_state->dpll.n = clock.n;
8892 crtc_state->dpll.m1 = clock.m1;
8893 crtc_state->dpll.m2 = clock.m2;
8894 crtc_state->dpll.p1 = clock.p1;
8895 crtc_state->dpll.p2 = clock.p2;
8896 }
8897
8898 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8899 if (crtc_state->has_pch_encoder) {
8900 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8901 if (has_reduced_clock)
8902 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8903
8904 dpll = ironlake_compute_dpll(crtc, crtc_state,
8905 &fp, &reduced_clock,
8906 has_reduced_clock ? &fp2 : NULL);
8907
8908 crtc_state->dpll_hw_state.dpll = dpll;
8909 crtc_state->dpll_hw_state.fp0 = fp;
8910 if (has_reduced_clock)
8911 crtc_state->dpll_hw_state.fp1 = fp2;
8912 else
8913 crtc_state->dpll_hw_state.fp1 = fp;
8914
8915 pll = intel_get_shared_dpll(crtc, crtc_state);
8916 if (pll == NULL) {
8917 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8918 pipe_name(crtc->pipe));
8919 return -EINVAL;
8920 }
8921 }
8922
8923 if (is_lvds && has_reduced_clock)
8924 crtc->lowfreq_avail = true;
8925 else
8926 crtc->lowfreq_avail = false;
8927
8928 return 0;
8929 }
8930
8931 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8932 struct intel_link_m_n *m_n)
8933 {
8934 struct drm_device *dev = crtc->base.dev;
8935 struct drm_i915_private *dev_priv = dev->dev_private;
8936 enum pipe pipe = crtc->pipe;
8937
8938 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8939 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8940 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8941 & ~TU_SIZE_MASK;
8942 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8943 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8944 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8945 }
8946
8947 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8948 enum transcoder transcoder,
8949 struct intel_link_m_n *m_n,
8950 struct intel_link_m_n *m2_n2)
8951 {
8952 struct drm_device *dev = crtc->base.dev;
8953 struct drm_i915_private *dev_priv = dev->dev_private;
8954 enum pipe pipe = crtc->pipe;
8955
8956 if (INTEL_INFO(dev)->gen >= 5) {
8957 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8958 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8959 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8960 & ~TU_SIZE_MASK;
8961 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8962 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8963 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8964 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8965 * gen < 8) and if DRRS is supported (to make sure the
8966 * registers are not unnecessarily read).
8967 */
8968 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8969 crtc->config->has_drrs) {
8970 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8971 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8972 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8973 & ~TU_SIZE_MASK;
8974 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8975 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8976 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8977 }
8978 } else {
8979 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8980 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8981 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8982 & ~TU_SIZE_MASK;
8983 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8984 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8985 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8986 }
8987 }
8988
8989 void intel_dp_get_m_n(struct intel_crtc *crtc,
8990 struct intel_crtc_state *pipe_config)
8991 {
8992 if (pipe_config->has_pch_encoder)
8993 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8994 else
8995 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8996 &pipe_config->dp_m_n,
8997 &pipe_config->dp_m2_n2);
8998 }
8999
9000 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9001 struct intel_crtc_state *pipe_config)
9002 {
9003 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9004 &pipe_config->fdi_m_n, NULL);
9005 }
9006
9007 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9008 struct intel_crtc_state *pipe_config)
9009 {
9010 struct drm_device *dev = crtc->base.dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9013 uint32_t ps_ctrl = 0;
9014 int id = -1;
9015 int i;
9016
9017 /* find scaler attached to this pipe */
9018 for (i = 0; i < crtc->num_scalers; i++) {
9019 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9020 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9021 id = i;
9022 pipe_config->pch_pfit.enabled = true;
9023 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9024 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9025 break;
9026 }
9027 }
9028
9029 scaler_state->scaler_id = id;
9030 if (id >= 0) {
9031 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9032 } else {
9033 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9034 }
9035 }
9036
9037 static void
9038 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9039 struct intel_initial_plane_config *plane_config)
9040 {
9041 struct drm_device *dev = crtc->base.dev;
9042 struct drm_i915_private *dev_priv = dev->dev_private;
9043 u32 val, base, offset, stride_mult, tiling;
9044 int pipe = crtc->pipe;
9045 int fourcc, pixel_format;
9046 unsigned int aligned_height;
9047 struct drm_framebuffer *fb;
9048 struct intel_framebuffer *intel_fb;
9049
9050 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9051 if (!intel_fb) {
9052 DRM_DEBUG_KMS("failed to alloc fb\n");
9053 return;
9054 }
9055
9056 fb = &intel_fb->base;
9057
9058 val = I915_READ(PLANE_CTL(pipe, 0));
9059 if (!(val & PLANE_CTL_ENABLE))
9060 goto error;
9061
9062 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9063 fourcc = skl_format_to_fourcc(pixel_format,
9064 val & PLANE_CTL_ORDER_RGBX,
9065 val & PLANE_CTL_ALPHA_MASK);
9066 fb->pixel_format = fourcc;
9067 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9068
9069 tiling = val & PLANE_CTL_TILED_MASK;
9070 switch (tiling) {
9071 case PLANE_CTL_TILED_LINEAR:
9072 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9073 break;
9074 case PLANE_CTL_TILED_X:
9075 plane_config->tiling = I915_TILING_X;
9076 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9077 break;
9078 case PLANE_CTL_TILED_Y:
9079 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9080 break;
9081 case PLANE_CTL_TILED_YF:
9082 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9083 break;
9084 default:
9085 MISSING_CASE(tiling);
9086 goto error;
9087 }
9088
9089 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9090 plane_config->base = base;
9091
9092 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9093
9094 val = I915_READ(PLANE_SIZE(pipe, 0));
9095 fb->height = ((val >> 16) & 0xfff) + 1;
9096 fb->width = ((val >> 0) & 0x1fff) + 1;
9097
9098 val = I915_READ(PLANE_STRIDE(pipe, 0));
9099 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9100 fb->pixel_format);
9101 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9102
9103 aligned_height = intel_fb_align_height(dev, fb->height,
9104 fb->pixel_format,
9105 fb->modifier[0]);
9106
9107 plane_config->size = fb->pitches[0] * aligned_height;
9108
9109 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9110 pipe_name(pipe), fb->width, fb->height,
9111 fb->bits_per_pixel, base, fb->pitches[0],
9112 plane_config->size);
9113
9114 plane_config->fb = intel_fb;
9115 return;
9116
9117 error:
9118 kfree(fb);
9119 }
9120
9121 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9122 struct intel_crtc_state *pipe_config)
9123 {
9124 struct drm_device *dev = crtc->base.dev;
9125 struct drm_i915_private *dev_priv = dev->dev_private;
9126 uint32_t tmp;
9127
9128 tmp = I915_READ(PF_CTL(crtc->pipe));
9129
9130 if (tmp & PF_ENABLE) {
9131 pipe_config->pch_pfit.enabled = true;
9132 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9133 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9134
9135 /* We currently do not free assignements of panel fitters on
9136 * ivb/hsw (since we don't use the higher upscaling modes which
9137 * differentiates them) so just WARN about this case for now. */
9138 if (IS_GEN7(dev)) {
9139 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9140 PF_PIPE_SEL_IVB(crtc->pipe));
9141 }
9142 }
9143 }
9144
9145 static void
9146 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9147 struct intel_initial_plane_config *plane_config)
9148 {
9149 struct drm_device *dev = crtc->base.dev;
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9151 u32 val, base, offset;
9152 int pipe = crtc->pipe;
9153 int fourcc, pixel_format;
9154 unsigned int aligned_height;
9155 struct drm_framebuffer *fb;
9156 struct intel_framebuffer *intel_fb;
9157
9158 val = I915_READ(DSPCNTR(pipe));
9159 if (!(val & DISPLAY_PLANE_ENABLE))
9160 return;
9161
9162 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9163 if (!intel_fb) {
9164 DRM_DEBUG_KMS("failed to alloc fb\n");
9165 return;
9166 }
9167
9168 fb = &intel_fb->base;
9169
9170 if (INTEL_INFO(dev)->gen >= 4) {
9171 if (val & DISPPLANE_TILED) {
9172 plane_config->tiling = I915_TILING_X;
9173 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9174 }
9175 }
9176
9177 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9178 fourcc = i9xx_format_to_fourcc(pixel_format);
9179 fb->pixel_format = fourcc;
9180 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9181
9182 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9183 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9184 offset = I915_READ(DSPOFFSET(pipe));
9185 } else {
9186 if (plane_config->tiling)
9187 offset = I915_READ(DSPTILEOFF(pipe));
9188 else
9189 offset = I915_READ(DSPLINOFF(pipe));
9190 }
9191 plane_config->base = base;
9192
9193 val = I915_READ(PIPESRC(pipe));
9194 fb->width = ((val >> 16) & 0xfff) + 1;
9195 fb->height = ((val >> 0) & 0xfff) + 1;
9196
9197 val = I915_READ(DSPSTRIDE(pipe));
9198 fb->pitches[0] = val & 0xffffffc0;
9199
9200 aligned_height = intel_fb_align_height(dev, fb->height,
9201 fb->pixel_format,
9202 fb->modifier[0]);
9203
9204 plane_config->size = fb->pitches[0] * aligned_height;
9205
9206 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9207 pipe_name(pipe), fb->width, fb->height,
9208 fb->bits_per_pixel, base, fb->pitches[0],
9209 plane_config->size);
9210
9211 plane_config->fb = intel_fb;
9212 }
9213
9214 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9215 struct intel_crtc_state *pipe_config)
9216 {
9217 struct drm_device *dev = crtc->base.dev;
9218 struct drm_i915_private *dev_priv = dev->dev_private;
9219 uint32_t tmp;
9220
9221 if (!intel_display_power_is_enabled(dev_priv,
9222 POWER_DOMAIN_PIPE(crtc->pipe)))
9223 return false;
9224
9225 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9226 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9227
9228 tmp = I915_READ(PIPECONF(crtc->pipe));
9229 if (!(tmp & PIPECONF_ENABLE))
9230 return false;
9231
9232 switch (tmp & PIPECONF_BPC_MASK) {
9233 case PIPECONF_6BPC:
9234 pipe_config->pipe_bpp = 18;
9235 break;
9236 case PIPECONF_8BPC:
9237 pipe_config->pipe_bpp = 24;
9238 break;
9239 case PIPECONF_10BPC:
9240 pipe_config->pipe_bpp = 30;
9241 break;
9242 case PIPECONF_12BPC:
9243 pipe_config->pipe_bpp = 36;
9244 break;
9245 default:
9246 break;
9247 }
9248
9249 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9250 pipe_config->limited_color_range = true;
9251
9252 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9253 struct intel_shared_dpll *pll;
9254
9255 pipe_config->has_pch_encoder = true;
9256
9257 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9258 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9259 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9260
9261 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9262
9263 if (HAS_PCH_IBX(dev_priv->dev)) {
9264 pipe_config->shared_dpll =
9265 (enum intel_dpll_id) crtc->pipe;
9266 } else {
9267 tmp = I915_READ(PCH_DPLL_SEL);
9268 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9269 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9270 else
9271 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9272 }
9273
9274 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9275
9276 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9277 &pipe_config->dpll_hw_state));
9278
9279 tmp = pipe_config->dpll_hw_state.dpll;
9280 pipe_config->pixel_multiplier =
9281 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9282 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9283
9284 ironlake_pch_clock_get(crtc, pipe_config);
9285 } else {
9286 pipe_config->pixel_multiplier = 1;
9287 }
9288
9289 intel_get_pipe_timings(crtc, pipe_config);
9290
9291 ironlake_get_pfit_config(crtc, pipe_config);
9292
9293 return true;
9294 }
9295
9296 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9297 {
9298 struct drm_device *dev = dev_priv->dev;
9299 struct intel_crtc *crtc;
9300
9301 for_each_intel_crtc(dev, crtc)
9302 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9303 pipe_name(crtc->pipe));
9304
9305 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9306 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9307 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9308 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9309 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9310 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9311 "CPU PWM1 enabled\n");
9312 if (IS_HASWELL(dev))
9313 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9314 "CPU PWM2 enabled\n");
9315 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9316 "PCH PWM1 enabled\n");
9317 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9318 "Utility pin enabled\n");
9319 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9320
9321 /*
9322 * In theory we can still leave IRQs enabled, as long as only the HPD
9323 * interrupts remain enabled. We used to check for that, but since it's
9324 * gen-specific and since we only disable LCPLL after we fully disable
9325 * the interrupts, the check below should be enough.
9326 */
9327 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9328 }
9329
9330 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9331 {
9332 struct drm_device *dev = dev_priv->dev;
9333
9334 if (IS_HASWELL(dev))
9335 return I915_READ(D_COMP_HSW);
9336 else
9337 return I915_READ(D_COMP_BDW);
9338 }
9339
9340 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9341 {
9342 struct drm_device *dev = dev_priv->dev;
9343
9344 if (IS_HASWELL(dev)) {
9345 mutex_lock(&dev_priv->rps.hw_lock);
9346 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9347 val))
9348 DRM_ERROR("Failed to write to D_COMP\n");
9349 mutex_unlock(&dev_priv->rps.hw_lock);
9350 } else {
9351 I915_WRITE(D_COMP_BDW, val);
9352 POSTING_READ(D_COMP_BDW);
9353 }
9354 }
9355
9356 /*
9357 * This function implements pieces of two sequences from BSpec:
9358 * - Sequence for display software to disable LCPLL
9359 * - Sequence for display software to allow package C8+
9360 * The steps implemented here are just the steps that actually touch the LCPLL
9361 * register. Callers should take care of disabling all the display engine
9362 * functions, doing the mode unset, fixing interrupts, etc.
9363 */
9364 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9365 bool switch_to_fclk, bool allow_power_down)
9366 {
9367 uint32_t val;
9368
9369 assert_can_disable_lcpll(dev_priv);
9370
9371 val = I915_READ(LCPLL_CTL);
9372
9373 if (switch_to_fclk) {
9374 val |= LCPLL_CD_SOURCE_FCLK;
9375 I915_WRITE(LCPLL_CTL, val);
9376
9377 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9378 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9379 DRM_ERROR("Switching to FCLK failed\n");
9380
9381 val = I915_READ(LCPLL_CTL);
9382 }
9383
9384 val |= LCPLL_PLL_DISABLE;
9385 I915_WRITE(LCPLL_CTL, val);
9386 POSTING_READ(LCPLL_CTL);
9387
9388 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9389 DRM_ERROR("LCPLL still locked\n");
9390
9391 val = hsw_read_dcomp(dev_priv);
9392 val |= D_COMP_COMP_DISABLE;
9393 hsw_write_dcomp(dev_priv, val);
9394 ndelay(100);
9395
9396 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9397 1))
9398 DRM_ERROR("D_COMP RCOMP still in progress\n");
9399
9400 if (allow_power_down) {
9401 val = I915_READ(LCPLL_CTL);
9402 val |= LCPLL_POWER_DOWN_ALLOW;
9403 I915_WRITE(LCPLL_CTL, val);
9404 POSTING_READ(LCPLL_CTL);
9405 }
9406 }
9407
9408 /*
9409 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9410 * source.
9411 */
9412 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9413 {
9414 uint32_t val;
9415
9416 val = I915_READ(LCPLL_CTL);
9417
9418 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9419 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9420 return;
9421
9422 /*
9423 * Make sure we're not on PC8 state before disabling PC8, otherwise
9424 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9425 */
9426 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9427
9428 if (val & LCPLL_POWER_DOWN_ALLOW) {
9429 val &= ~LCPLL_POWER_DOWN_ALLOW;
9430 I915_WRITE(LCPLL_CTL, val);
9431 POSTING_READ(LCPLL_CTL);
9432 }
9433
9434 val = hsw_read_dcomp(dev_priv);
9435 val |= D_COMP_COMP_FORCE;
9436 val &= ~D_COMP_COMP_DISABLE;
9437 hsw_write_dcomp(dev_priv, val);
9438
9439 val = I915_READ(LCPLL_CTL);
9440 val &= ~LCPLL_PLL_DISABLE;
9441 I915_WRITE(LCPLL_CTL, val);
9442
9443 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9444 DRM_ERROR("LCPLL not locked yet\n");
9445
9446 if (val & LCPLL_CD_SOURCE_FCLK) {
9447 val = I915_READ(LCPLL_CTL);
9448 val &= ~LCPLL_CD_SOURCE_FCLK;
9449 I915_WRITE(LCPLL_CTL, val);
9450
9451 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9452 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9453 DRM_ERROR("Switching back to LCPLL failed\n");
9454 }
9455
9456 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9457 intel_update_cdclk(dev_priv->dev);
9458 }
9459
9460 /*
9461 * Package states C8 and deeper are really deep PC states that can only be
9462 * reached when all the devices on the system allow it, so even if the graphics
9463 * device allows PC8+, it doesn't mean the system will actually get to these
9464 * states. Our driver only allows PC8+ when going into runtime PM.
9465 *
9466 * The requirements for PC8+ are that all the outputs are disabled, the power
9467 * well is disabled and most interrupts are disabled, and these are also
9468 * requirements for runtime PM. When these conditions are met, we manually do
9469 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9470 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9471 * hang the machine.
9472 *
9473 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9474 * the state of some registers, so when we come back from PC8+ we need to
9475 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9476 * need to take care of the registers kept by RC6. Notice that this happens even
9477 * if we don't put the device in PCI D3 state (which is what currently happens
9478 * because of the runtime PM support).
9479 *
9480 * For more, read "Display Sequences for Package C8" on the hardware
9481 * documentation.
9482 */
9483 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9484 {
9485 struct drm_device *dev = dev_priv->dev;
9486 uint32_t val;
9487
9488 DRM_DEBUG_KMS("Enabling package C8+\n");
9489
9490 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9491 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9492 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9493 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9494 }
9495
9496 lpt_disable_clkout_dp(dev);
9497 hsw_disable_lcpll(dev_priv, true, true);
9498 }
9499
9500 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9501 {
9502 struct drm_device *dev = dev_priv->dev;
9503 uint32_t val;
9504
9505 DRM_DEBUG_KMS("Disabling package C8+\n");
9506
9507 hsw_restore_lcpll(dev_priv);
9508 lpt_init_pch_refclk(dev);
9509
9510 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9511 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9512 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9513 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9514 }
9515
9516 intel_prepare_ddi(dev);
9517 }
9518
9519 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9520 {
9521 struct drm_device *dev = old_state->dev;
9522 struct drm_i915_private *dev_priv = dev->dev_private;
9523 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9524 int req_cdclk;
9525
9526 /* see the comment in valleyview_modeset_global_resources */
9527 if (WARN_ON(max_pixclk < 0))
9528 return;
9529
9530 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9531
9532 if (req_cdclk != dev_priv->cdclk_freq)
9533 broxton_set_cdclk(dev, req_cdclk);
9534 }
9535
9536 /* compute the max rate for new configuration */
9537 static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9538 {
9539 struct drm_device *dev = dev_priv->dev;
9540 struct intel_crtc *intel_crtc;
9541 struct drm_crtc *crtc;
9542 int max_pixel_rate = 0;
9543 int pixel_rate;
9544
9545 for_each_crtc(dev, crtc) {
9546 if (!crtc->state->enable)
9547 continue;
9548
9549 intel_crtc = to_intel_crtc(crtc);
9550 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9551
9552 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9553 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9554 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9555
9556 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9557 }
9558
9559 return max_pixel_rate;
9560 }
9561
9562 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9563 {
9564 struct drm_i915_private *dev_priv = dev->dev_private;
9565 uint32_t val, data;
9566 int ret;
9567
9568 if (WARN((I915_READ(LCPLL_CTL) &
9569 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9570 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9571 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9572 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9573 "trying to change cdclk frequency with cdclk not enabled\n"))
9574 return;
9575
9576 mutex_lock(&dev_priv->rps.hw_lock);
9577 ret = sandybridge_pcode_write(dev_priv,
9578 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9579 mutex_unlock(&dev_priv->rps.hw_lock);
9580 if (ret) {
9581 DRM_ERROR("failed to inform pcode about cdclk change\n");
9582 return;
9583 }
9584
9585 val = I915_READ(LCPLL_CTL);
9586 val |= LCPLL_CD_SOURCE_FCLK;
9587 I915_WRITE(LCPLL_CTL, val);
9588
9589 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9590 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9591 DRM_ERROR("Switching to FCLK failed\n");
9592
9593 val = I915_READ(LCPLL_CTL);
9594 val &= ~LCPLL_CLK_FREQ_MASK;
9595
9596 switch (cdclk) {
9597 case 450000:
9598 val |= LCPLL_CLK_FREQ_450;
9599 data = 0;
9600 break;
9601 case 540000:
9602 val |= LCPLL_CLK_FREQ_54O_BDW;
9603 data = 1;
9604 break;
9605 case 337500:
9606 val |= LCPLL_CLK_FREQ_337_5_BDW;
9607 data = 2;
9608 break;
9609 case 675000:
9610 val |= LCPLL_CLK_FREQ_675_BDW;
9611 data = 3;
9612 break;
9613 default:
9614 WARN(1, "invalid cdclk frequency\n");
9615 return;
9616 }
9617
9618 I915_WRITE(LCPLL_CTL, val);
9619
9620 val = I915_READ(LCPLL_CTL);
9621 val &= ~LCPLL_CD_SOURCE_FCLK;
9622 I915_WRITE(LCPLL_CTL, val);
9623
9624 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9625 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9626 DRM_ERROR("Switching back to LCPLL failed\n");
9627
9628 mutex_lock(&dev_priv->rps.hw_lock);
9629 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9630 mutex_unlock(&dev_priv->rps.hw_lock);
9631
9632 intel_update_cdclk(dev);
9633
9634 WARN(cdclk != dev_priv->cdclk_freq,
9635 "cdclk requested %d kHz but got %d kHz\n",
9636 cdclk, dev_priv->cdclk_freq);
9637 }
9638
9639 static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9640 int max_pixel_rate)
9641 {
9642 int cdclk;
9643
9644 /*
9645 * FIXME should also account for plane ratio
9646 * once 64bpp pixel formats are supported.
9647 */
9648 if (max_pixel_rate > 540000)
9649 cdclk = 675000;
9650 else if (max_pixel_rate > 450000)
9651 cdclk = 540000;
9652 else if (max_pixel_rate > 337500)
9653 cdclk = 450000;
9654 else
9655 cdclk = 337500;
9656
9657 /*
9658 * FIXME move the cdclk caclulation to
9659 * compute_config() so we can fail gracegully.
9660 */
9661 if (cdclk > dev_priv->max_cdclk_freq) {
9662 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9663 cdclk, dev_priv->max_cdclk_freq);
9664 cdclk = dev_priv->max_cdclk_freq;
9665 }
9666
9667 return cdclk;
9668 }
9669
9670 static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9671 {
9672 struct drm_i915_private *dev_priv = to_i915(state->dev);
9673 struct drm_crtc *crtc;
9674 struct drm_crtc_state *crtc_state;
9675 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9676 int cdclk, i;
9677
9678 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9679
9680 if (cdclk == dev_priv->cdclk_freq)
9681 return 0;
9682
9683 /* add all active pipes to the state */
9684 for_each_crtc(state->dev, crtc) {
9685 if (!crtc->state->enable)
9686 continue;
9687
9688 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9689 if (IS_ERR(crtc_state))
9690 return PTR_ERR(crtc_state);
9691 }
9692
9693 /* disable/enable all currently active pipes while we change cdclk */
9694 for_each_crtc_in_state(state, crtc, crtc_state, i)
9695 if (crtc_state->enable)
9696 crtc_state->mode_changed = true;
9697
9698 return 0;
9699 }
9700
9701 static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9702 {
9703 struct drm_device *dev = state->dev;
9704 struct drm_i915_private *dev_priv = dev->dev_private;
9705 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9706 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9707
9708 if (req_cdclk != dev_priv->cdclk_freq)
9709 broadwell_set_cdclk(dev, req_cdclk);
9710 }
9711
9712 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9713 struct intel_crtc_state *crtc_state)
9714 {
9715 if (!intel_ddi_pll_select(crtc, crtc_state))
9716 return -EINVAL;
9717
9718 crtc->lowfreq_avail = false;
9719
9720 return 0;
9721 }
9722
9723 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9724 enum port port,
9725 struct intel_crtc_state *pipe_config)
9726 {
9727 switch (port) {
9728 case PORT_A:
9729 pipe_config->ddi_pll_sel = SKL_DPLL0;
9730 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9731 break;
9732 case PORT_B:
9733 pipe_config->ddi_pll_sel = SKL_DPLL1;
9734 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9735 break;
9736 case PORT_C:
9737 pipe_config->ddi_pll_sel = SKL_DPLL2;
9738 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9739 break;
9740 default:
9741 DRM_ERROR("Incorrect port type\n");
9742 }
9743 }
9744
9745 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9746 enum port port,
9747 struct intel_crtc_state *pipe_config)
9748 {
9749 u32 temp, dpll_ctl1;
9750
9751 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9752 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9753
9754 switch (pipe_config->ddi_pll_sel) {
9755 case SKL_DPLL0:
9756 /*
9757 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9758 * of the shared DPLL framework and thus needs to be read out
9759 * separately
9760 */
9761 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9762 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9763 break;
9764 case SKL_DPLL1:
9765 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9766 break;
9767 case SKL_DPLL2:
9768 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9769 break;
9770 case SKL_DPLL3:
9771 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9772 break;
9773 }
9774 }
9775
9776 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9777 enum port port,
9778 struct intel_crtc_state *pipe_config)
9779 {
9780 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9781
9782 switch (pipe_config->ddi_pll_sel) {
9783 case PORT_CLK_SEL_WRPLL1:
9784 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9785 break;
9786 case PORT_CLK_SEL_WRPLL2:
9787 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9788 break;
9789 }
9790 }
9791
9792 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9793 struct intel_crtc_state *pipe_config)
9794 {
9795 struct drm_device *dev = crtc->base.dev;
9796 struct drm_i915_private *dev_priv = dev->dev_private;
9797 struct intel_shared_dpll *pll;
9798 enum port port;
9799 uint32_t tmp;
9800
9801 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9802
9803 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9804
9805 if (IS_SKYLAKE(dev))
9806 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9807 else if (IS_BROXTON(dev))
9808 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9809 else
9810 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9811
9812 if (pipe_config->shared_dpll >= 0) {
9813 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9814
9815 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9816 &pipe_config->dpll_hw_state));
9817 }
9818
9819 /*
9820 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9821 * DDI E. So just check whether this pipe is wired to DDI E and whether
9822 * the PCH transcoder is on.
9823 */
9824 if (INTEL_INFO(dev)->gen < 9 &&
9825 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9826 pipe_config->has_pch_encoder = true;
9827
9828 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9829 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9830 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9831
9832 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9833 }
9834 }
9835
9836 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9837 struct intel_crtc_state *pipe_config)
9838 {
9839 struct drm_device *dev = crtc->base.dev;
9840 struct drm_i915_private *dev_priv = dev->dev_private;
9841 enum intel_display_power_domain pfit_domain;
9842 uint32_t tmp;
9843
9844 if (!intel_display_power_is_enabled(dev_priv,
9845 POWER_DOMAIN_PIPE(crtc->pipe)))
9846 return false;
9847
9848 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9849 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9850
9851 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9852 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9853 enum pipe trans_edp_pipe;
9854 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9855 default:
9856 WARN(1, "unknown pipe linked to edp transcoder\n");
9857 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9858 case TRANS_DDI_EDP_INPUT_A_ON:
9859 trans_edp_pipe = PIPE_A;
9860 break;
9861 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9862 trans_edp_pipe = PIPE_B;
9863 break;
9864 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9865 trans_edp_pipe = PIPE_C;
9866 break;
9867 }
9868
9869 if (trans_edp_pipe == crtc->pipe)
9870 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9871 }
9872
9873 if (!intel_display_power_is_enabled(dev_priv,
9874 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9875 return false;
9876
9877 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9878 if (!(tmp & PIPECONF_ENABLE))
9879 return false;
9880
9881 haswell_get_ddi_port_state(crtc, pipe_config);
9882
9883 intel_get_pipe_timings(crtc, pipe_config);
9884
9885 if (INTEL_INFO(dev)->gen >= 9) {
9886 skl_init_scalers(dev, crtc, pipe_config);
9887 }
9888
9889 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9890
9891 if (INTEL_INFO(dev)->gen >= 9) {
9892 pipe_config->scaler_state.scaler_id = -1;
9893 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9894 }
9895
9896 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9897 if (INTEL_INFO(dev)->gen == 9)
9898 skylake_get_pfit_config(crtc, pipe_config);
9899 else if (INTEL_INFO(dev)->gen < 9)
9900 ironlake_get_pfit_config(crtc, pipe_config);
9901 else
9902 MISSING_CASE(INTEL_INFO(dev)->gen);
9903 }
9904
9905 if (IS_HASWELL(dev))
9906 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9907 (I915_READ(IPS_CTL) & IPS_ENABLE);
9908
9909 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9910 pipe_config->pixel_multiplier =
9911 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9912 } else {
9913 pipe_config->pixel_multiplier = 1;
9914 }
9915
9916 return true;
9917 }
9918
9919 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9920 {
9921 struct drm_device *dev = crtc->dev;
9922 struct drm_i915_private *dev_priv = dev->dev_private;
9923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9924 uint32_t cntl = 0, size = 0;
9925
9926 if (base) {
9927 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9928 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9929 unsigned int stride = roundup_pow_of_two(width) * 4;
9930
9931 switch (stride) {
9932 default:
9933 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9934 width, stride);
9935 stride = 256;
9936 /* fallthrough */
9937 case 256:
9938 case 512:
9939 case 1024:
9940 case 2048:
9941 break;
9942 }
9943
9944 cntl |= CURSOR_ENABLE |
9945 CURSOR_GAMMA_ENABLE |
9946 CURSOR_FORMAT_ARGB |
9947 CURSOR_STRIDE(stride);
9948
9949 size = (height << 12) | width;
9950 }
9951
9952 if (intel_crtc->cursor_cntl != 0 &&
9953 (intel_crtc->cursor_base != base ||
9954 intel_crtc->cursor_size != size ||
9955 intel_crtc->cursor_cntl != cntl)) {
9956 /* On these chipsets we can only modify the base/size/stride
9957 * whilst the cursor is disabled.
9958 */
9959 I915_WRITE(_CURACNTR, 0);
9960 POSTING_READ(_CURACNTR);
9961 intel_crtc->cursor_cntl = 0;
9962 }
9963
9964 if (intel_crtc->cursor_base != base) {
9965 I915_WRITE(_CURABASE, base);
9966 intel_crtc->cursor_base = base;
9967 }
9968
9969 if (intel_crtc->cursor_size != size) {
9970 I915_WRITE(CURSIZE, size);
9971 intel_crtc->cursor_size = size;
9972 }
9973
9974 if (intel_crtc->cursor_cntl != cntl) {
9975 I915_WRITE(_CURACNTR, cntl);
9976 POSTING_READ(_CURACNTR);
9977 intel_crtc->cursor_cntl = cntl;
9978 }
9979 }
9980
9981 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9982 {
9983 struct drm_device *dev = crtc->dev;
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9986 int pipe = intel_crtc->pipe;
9987 uint32_t cntl;
9988
9989 cntl = 0;
9990 if (base) {
9991 cntl = MCURSOR_GAMMA_ENABLE;
9992 switch (intel_crtc->base.cursor->state->crtc_w) {
9993 case 64:
9994 cntl |= CURSOR_MODE_64_ARGB_AX;
9995 break;
9996 case 128:
9997 cntl |= CURSOR_MODE_128_ARGB_AX;
9998 break;
9999 case 256:
10000 cntl |= CURSOR_MODE_256_ARGB_AX;
10001 break;
10002 default:
10003 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10004 return;
10005 }
10006 cntl |= pipe << 28; /* Connect to correct pipe */
10007
10008 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10009 cntl |= CURSOR_PIPE_CSC_ENABLE;
10010 }
10011
10012 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10013 cntl |= CURSOR_ROTATE_180;
10014
10015 if (intel_crtc->cursor_cntl != cntl) {
10016 I915_WRITE(CURCNTR(pipe), cntl);
10017 POSTING_READ(CURCNTR(pipe));
10018 intel_crtc->cursor_cntl = cntl;
10019 }
10020
10021 /* and commit changes on next vblank */
10022 I915_WRITE(CURBASE(pipe), base);
10023 POSTING_READ(CURBASE(pipe));
10024
10025 intel_crtc->cursor_base = base;
10026 }
10027
10028 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10029 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10030 bool on)
10031 {
10032 struct drm_device *dev = crtc->dev;
10033 struct drm_i915_private *dev_priv = dev->dev_private;
10034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10035 int pipe = intel_crtc->pipe;
10036 int x = crtc->cursor_x;
10037 int y = crtc->cursor_y;
10038 u32 base = 0, pos = 0;
10039
10040 if (on)
10041 base = intel_crtc->cursor_addr;
10042
10043 if (x >= intel_crtc->config->pipe_src_w)
10044 base = 0;
10045
10046 if (y >= intel_crtc->config->pipe_src_h)
10047 base = 0;
10048
10049 if (x < 0) {
10050 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10051 base = 0;
10052
10053 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10054 x = -x;
10055 }
10056 pos |= x << CURSOR_X_SHIFT;
10057
10058 if (y < 0) {
10059 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10060 base = 0;
10061
10062 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10063 y = -y;
10064 }
10065 pos |= y << CURSOR_Y_SHIFT;
10066
10067 if (base == 0 && intel_crtc->cursor_base == 0)
10068 return;
10069
10070 I915_WRITE(CURPOS(pipe), pos);
10071
10072 /* ILK+ do this automagically */
10073 if (HAS_GMCH_DISPLAY(dev) &&
10074 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10075 base += (intel_crtc->base.cursor->state->crtc_h *
10076 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10077 }
10078
10079 if (IS_845G(dev) || IS_I865G(dev))
10080 i845_update_cursor(crtc, base);
10081 else
10082 i9xx_update_cursor(crtc, base);
10083 }
10084
10085 static bool cursor_size_ok(struct drm_device *dev,
10086 uint32_t width, uint32_t height)
10087 {
10088 if (width == 0 || height == 0)
10089 return false;
10090
10091 /*
10092 * 845g/865g are special in that they are only limited by
10093 * the width of their cursors, the height is arbitrary up to
10094 * the precision of the register. Everything else requires
10095 * square cursors, limited to a few power-of-two sizes.
10096 */
10097 if (IS_845G(dev) || IS_I865G(dev)) {
10098 if ((width & 63) != 0)
10099 return false;
10100
10101 if (width > (IS_845G(dev) ? 64 : 512))
10102 return false;
10103
10104 if (height > 1023)
10105 return false;
10106 } else {
10107 switch (width | height) {
10108 case 256:
10109 case 128:
10110 if (IS_GEN2(dev))
10111 return false;
10112 case 64:
10113 break;
10114 default:
10115 return false;
10116 }
10117 }
10118
10119 return true;
10120 }
10121
10122 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10123 u16 *blue, uint32_t start, uint32_t size)
10124 {
10125 int end = (start + size > 256) ? 256 : start + size, i;
10126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10127
10128 for (i = start; i < end; i++) {
10129 intel_crtc->lut_r[i] = red[i] >> 8;
10130 intel_crtc->lut_g[i] = green[i] >> 8;
10131 intel_crtc->lut_b[i] = blue[i] >> 8;
10132 }
10133
10134 intel_crtc_load_lut(crtc);
10135 }
10136
10137 /* VESA 640x480x72Hz mode to set on the pipe */
10138 static struct drm_display_mode load_detect_mode = {
10139 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10140 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10141 };
10142
10143 struct drm_framebuffer *
10144 __intel_framebuffer_create(struct drm_device *dev,
10145 struct drm_mode_fb_cmd2 *mode_cmd,
10146 struct drm_i915_gem_object *obj)
10147 {
10148 struct intel_framebuffer *intel_fb;
10149 int ret;
10150
10151 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10152 if (!intel_fb) {
10153 drm_gem_object_unreference(&obj->base);
10154 return ERR_PTR(-ENOMEM);
10155 }
10156
10157 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10158 if (ret)
10159 goto err;
10160
10161 return &intel_fb->base;
10162 err:
10163 drm_gem_object_unreference(&obj->base);
10164 kfree(intel_fb);
10165
10166 return ERR_PTR(ret);
10167 }
10168
10169 static struct drm_framebuffer *
10170 intel_framebuffer_create(struct drm_device *dev,
10171 struct drm_mode_fb_cmd2 *mode_cmd,
10172 struct drm_i915_gem_object *obj)
10173 {
10174 struct drm_framebuffer *fb;
10175 int ret;
10176
10177 ret = i915_mutex_lock_interruptible(dev);
10178 if (ret)
10179 return ERR_PTR(ret);
10180 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10181 mutex_unlock(&dev->struct_mutex);
10182
10183 return fb;
10184 }
10185
10186 static u32
10187 intel_framebuffer_pitch_for_width(int width, int bpp)
10188 {
10189 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10190 return ALIGN(pitch, 64);
10191 }
10192
10193 static u32
10194 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10195 {
10196 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10197 return PAGE_ALIGN(pitch * mode->vdisplay);
10198 }
10199
10200 static struct drm_framebuffer *
10201 intel_framebuffer_create_for_mode(struct drm_device *dev,
10202 struct drm_display_mode *mode,
10203 int depth, int bpp)
10204 {
10205 struct drm_i915_gem_object *obj;
10206 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10207
10208 obj = i915_gem_alloc_object(dev,
10209 intel_framebuffer_size_for_mode(mode, bpp));
10210 if (obj == NULL)
10211 return ERR_PTR(-ENOMEM);
10212
10213 mode_cmd.width = mode->hdisplay;
10214 mode_cmd.height = mode->vdisplay;
10215 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10216 bpp);
10217 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10218
10219 return intel_framebuffer_create(dev, &mode_cmd, obj);
10220 }
10221
10222 static struct drm_framebuffer *
10223 mode_fits_in_fbdev(struct drm_device *dev,
10224 struct drm_display_mode *mode)
10225 {
10226 #ifdef CONFIG_DRM_I915_FBDEV
10227 struct drm_i915_private *dev_priv = dev->dev_private;
10228 struct drm_i915_gem_object *obj;
10229 struct drm_framebuffer *fb;
10230
10231 if (!dev_priv->fbdev)
10232 return NULL;
10233
10234 if (!dev_priv->fbdev->fb)
10235 return NULL;
10236
10237 obj = dev_priv->fbdev->fb->obj;
10238 BUG_ON(!obj);
10239
10240 fb = &dev_priv->fbdev->fb->base;
10241 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10242 fb->bits_per_pixel))
10243 return NULL;
10244
10245 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10246 return NULL;
10247
10248 return fb;
10249 #else
10250 return NULL;
10251 #endif
10252 }
10253
10254 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10255 struct drm_crtc *crtc,
10256 struct drm_display_mode *mode,
10257 struct drm_framebuffer *fb,
10258 int x, int y)
10259 {
10260 struct drm_plane_state *plane_state;
10261 int hdisplay, vdisplay;
10262 int ret;
10263
10264 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10265 if (IS_ERR(plane_state))
10266 return PTR_ERR(plane_state);
10267
10268 if (mode)
10269 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10270 else
10271 hdisplay = vdisplay = 0;
10272
10273 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10274 if (ret)
10275 return ret;
10276 drm_atomic_set_fb_for_plane(plane_state, fb);
10277 plane_state->crtc_x = 0;
10278 plane_state->crtc_y = 0;
10279 plane_state->crtc_w = hdisplay;
10280 plane_state->crtc_h = vdisplay;
10281 plane_state->src_x = x << 16;
10282 plane_state->src_y = y << 16;
10283 plane_state->src_w = hdisplay << 16;
10284 plane_state->src_h = vdisplay << 16;
10285
10286 return 0;
10287 }
10288
10289 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10290 struct drm_display_mode *mode,
10291 struct intel_load_detect_pipe *old,
10292 struct drm_modeset_acquire_ctx *ctx)
10293 {
10294 struct intel_crtc *intel_crtc;
10295 struct intel_encoder *intel_encoder =
10296 intel_attached_encoder(connector);
10297 struct drm_crtc *possible_crtc;
10298 struct drm_encoder *encoder = &intel_encoder->base;
10299 struct drm_crtc *crtc = NULL;
10300 struct drm_device *dev = encoder->dev;
10301 struct drm_framebuffer *fb;
10302 struct drm_mode_config *config = &dev->mode_config;
10303 struct drm_atomic_state *state = NULL;
10304 struct drm_connector_state *connector_state;
10305 struct intel_crtc_state *crtc_state;
10306 int ret, i = -1;
10307
10308 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10309 connector->base.id, connector->name,
10310 encoder->base.id, encoder->name);
10311
10312 retry:
10313 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10314 if (ret)
10315 goto fail_unlock;
10316
10317 /*
10318 * Algorithm gets a little messy:
10319 *
10320 * - if the connector already has an assigned crtc, use it (but make
10321 * sure it's on first)
10322 *
10323 * - try to find the first unused crtc that can drive this connector,
10324 * and use that if we find one
10325 */
10326
10327 /* See if we already have a CRTC for this connector */
10328 if (encoder->crtc) {
10329 crtc = encoder->crtc;
10330
10331 ret = drm_modeset_lock(&crtc->mutex, ctx);
10332 if (ret)
10333 goto fail_unlock;
10334 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10335 if (ret)
10336 goto fail_unlock;
10337
10338 old->dpms_mode = connector->dpms;
10339 old->load_detect_temp = false;
10340
10341 /* Make sure the crtc and connector are running */
10342 if (connector->dpms != DRM_MODE_DPMS_ON)
10343 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10344
10345 return true;
10346 }
10347
10348 /* Find an unused one (if possible) */
10349 for_each_crtc(dev, possible_crtc) {
10350 i++;
10351 if (!(encoder->possible_crtcs & (1 << i)))
10352 continue;
10353 if (possible_crtc->state->enable)
10354 continue;
10355 /* This can occur when applying the pipe A quirk on resume. */
10356 if (to_intel_crtc(possible_crtc)->new_enabled)
10357 continue;
10358
10359 crtc = possible_crtc;
10360 break;
10361 }
10362
10363 /*
10364 * If we didn't find an unused CRTC, don't use any.
10365 */
10366 if (!crtc) {
10367 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10368 goto fail_unlock;
10369 }
10370
10371 ret = drm_modeset_lock(&crtc->mutex, ctx);
10372 if (ret)
10373 goto fail_unlock;
10374 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10375 if (ret)
10376 goto fail_unlock;
10377 intel_encoder->new_crtc = to_intel_crtc(crtc);
10378 to_intel_connector(connector)->new_encoder = intel_encoder;
10379
10380 intel_crtc = to_intel_crtc(crtc);
10381 intel_crtc->new_enabled = true;
10382 old->dpms_mode = connector->dpms;
10383 old->load_detect_temp = true;
10384 old->release_fb = NULL;
10385
10386 state = drm_atomic_state_alloc(dev);
10387 if (!state)
10388 return false;
10389
10390 state->acquire_ctx = ctx;
10391
10392 connector_state = drm_atomic_get_connector_state(state, connector);
10393 if (IS_ERR(connector_state)) {
10394 ret = PTR_ERR(connector_state);
10395 goto fail;
10396 }
10397
10398 connector_state->crtc = crtc;
10399 connector_state->best_encoder = &intel_encoder->base;
10400
10401 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10402 if (IS_ERR(crtc_state)) {
10403 ret = PTR_ERR(crtc_state);
10404 goto fail;
10405 }
10406
10407 crtc_state->base.active = crtc_state->base.enable = true;
10408
10409 if (!mode)
10410 mode = &load_detect_mode;
10411
10412 /* We need a framebuffer large enough to accommodate all accesses
10413 * that the plane may generate whilst we perform load detection.
10414 * We can not rely on the fbcon either being present (we get called
10415 * during its initialisation to detect all boot displays, or it may
10416 * not even exist) or that it is large enough to satisfy the
10417 * requested mode.
10418 */
10419 fb = mode_fits_in_fbdev(dev, mode);
10420 if (fb == NULL) {
10421 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10422 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10423 old->release_fb = fb;
10424 } else
10425 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10426 if (IS_ERR(fb)) {
10427 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10428 goto fail;
10429 }
10430
10431 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10432 if (ret)
10433 goto fail;
10434
10435 drm_mode_copy(&crtc_state->base.mode, mode);
10436
10437 if (intel_set_mode(state)) {
10438 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10439 if (old->release_fb)
10440 old->release_fb->funcs->destroy(old->release_fb);
10441 goto fail;
10442 }
10443 crtc->primary->crtc = crtc;
10444
10445 /* let the connector get through one full cycle before testing */
10446 intel_wait_for_vblank(dev, intel_crtc->pipe);
10447 return true;
10448
10449 fail:
10450 intel_crtc->new_enabled = crtc->state->enable;
10451 fail_unlock:
10452 drm_atomic_state_free(state);
10453 state = NULL;
10454
10455 if (ret == -EDEADLK) {
10456 drm_modeset_backoff(ctx);
10457 goto retry;
10458 }
10459
10460 return false;
10461 }
10462
10463 void intel_release_load_detect_pipe(struct drm_connector *connector,
10464 struct intel_load_detect_pipe *old,
10465 struct drm_modeset_acquire_ctx *ctx)
10466 {
10467 struct drm_device *dev = connector->dev;
10468 struct intel_encoder *intel_encoder =
10469 intel_attached_encoder(connector);
10470 struct drm_encoder *encoder = &intel_encoder->base;
10471 struct drm_crtc *crtc = encoder->crtc;
10472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10473 struct drm_atomic_state *state;
10474 struct drm_connector_state *connector_state;
10475 struct intel_crtc_state *crtc_state;
10476 int ret;
10477
10478 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10479 connector->base.id, connector->name,
10480 encoder->base.id, encoder->name);
10481
10482 if (old->load_detect_temp) {
10483 state = drm_atomic_state_alloc(dev);
10484 if (!state)
10485 goto fail;
10486
10487 state->acquire_ctx = ctx;
10488
10489 connector_state = drm_atomic_get_connector_state(state, connector);
10490 if (IS_ERR(connector_state))
10491 goto fail;
10492
10493 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10494 if (IS_ERR(crtc_state))
10495 goto fail;
10496
10497 to_intel_connector(connector)->new_encoder = NULL;
10498 intel_encoder->new_crtc = NULL;
10499 intel_crtc->new_enabled = false;
10500
10501 connector_state->best_encoder = NULL;
10502 connector_state->crtc = NULL;
10503
10504 crtc_state->base.enable = crtc_state->base.active = false;
10505
10506 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10507 0, 0);
10508 if (ret)
10509 goto fail;
10510
10511 ret = intel_set_mode(state);
10512 if (ret)
10513 goto fail;
10514
10515 if (old->release_fb) {
10516 drm_framebuffer_unregister_private(old->release_fb);
10517 drm_framebuffer_unreference(old->release_fb);
10518 }
10519
10520 return;
10521 }
10522
10523 /* Switch crtc and encoder back off if necessary */
10524 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10525 connector->funcs->dpms(connector, old->dpms_mode);
10526
10527 return;
10528 fail:
10529 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10530 drm_atomic_state_free(state);
10531 }
10532
10533 static int i9xx_pll_refclk(struct drm_device *dev,
10534 const struct intel_crtc_state *pipe_config)
10535 {
10536 struct drm_i915_private *dev_priv = dev->dev_private;
10537 u32 dpll = pipe_config->dpll_hw_state.dpll;
10538
10539 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10540 return dev_priv->vbt.lvds_ssc_freq;
10541 else if (HAS_PCH_SPLIT(dev))
10542 return 120000;
10543 else if (!IS_GEN2(dev))
10544 return 96000;
10545 else
10546 return 48000;
10547 }
10548
10549 /* Returns the clock of the currently programmed mode of the given pipe. */
10550 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10551 struct intel_crtc_state *pipe_config)
10552 {
10553 struct drm_device *dev = crtc->base.dev;
10554 struct drm_i915_private *dev_priv = dev->dev_private;
10555 int pipe = pipe_config->cpu_transcoder;
10556 u32 dpll = pipe_config->dpll_hw_state.dpll;
10557 u32 fp;
10558 intel_clock_t clock;
10559 int refclk = i9xx_pll_refclk(dev, pipe_config);
10560
10561 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10562 fp = pipe_config->dpll_hw_state.fp0;
10563 else
10564 fp = pipe_config->dpll_hw_state.fp1;
10565
10566 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10567 if (IS_PINEVIEW(dev)) {
10568 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10569 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10570 } else {
10571 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10572 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10573 }
10574
10575 if (!IS_GEN2(dev)) {
10576 if (IS_PINEVIEW(dev))
10577 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10578 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10579 else
10580 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10581 DPLL_FPA01_P1_POST_DIV_SHIFT);
10582
10583 switch (dpll & DPLL_MODE_MASK) {
10584 case DPLLB_MODE_DAC_SERIAL:
10585 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10586 5 : 10;
10587 break;
10588 case DPLLB_MODE_LVDS:
10589 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10590 7 : 14;
10591 break;
10592 default:
10593 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10594 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10595 return;
10596 }
10597
10598 if (IS_PINEVIEW(dev))
10599 pineview_clock(refclk, &clock);
10600 else
10601 i9xx_clock(refclk, &clock);
10602 } else {
10603 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10604 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10605
10606 if (is_lvds) {
10607 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10608 DPLL_FPA01_P1_POST_DIV_SHIFT);
10609
10610 if (lvds & LVDS_CLKB_POWER_UP)
10611 clock.p2 = 7;
10612 else
10613 clock.p2 = 14;
10614 } else {
10615 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10616 clock.p1 = 2;
10617 else {
10618 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10619 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10620 }
10621 if (dpll & PLL_P2_DIVIDE_BY_4)
10622 clock.p2 = 4;
10623 else
10624 clock.p2 = 2;
10625 }
10626
10627 i9xx_clock(refclk, &clock);
10628 }
10629
10630 /*
10631 * This value includes pixel_multiplier. We will use
10632 * port_clock to compute adjusted_mode.crtc_clock in the
10633 * encoder's get_config() function.
10634 */
10635 pipe_config->port_clock = clock.dot;
10636 }
10637
10638 int intel_dotclock_calculate(int link_freq,
10639 const struct intel_link_m_n *m_n)
10640 {
10641 /*
10642 * The calculation for the data clock is:
10643 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10644 * But we want to avoid losing precison if possible, so:
10645 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10646 *
10647 * and the link clock is simpler:
10648 * link_clock = (m * link_clock) / n
10649 */
10650
10651 if (!m_n->link_n)
10652 return 0;
10653
10654 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10655 }
10656
10657 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10658 struct intel_crtc_state *pipe_config)
10659 {
10660 struct drm_device *dev = crtc->base.dev;
10661
10662 /* read out port_clock from the DPLL */
10663 i9xx_crtc_clock_get(crtc, pipe_config);
10664
10665 /*
10666 * This value does not include pixel_multiplier.
10667 * We will check that port_clock and adjusted_mode.crtc_clock
10668 * agree once we know their relationship in the encoder's
10669 * get_config() function.
10670 */
10671 pipe_config->base.adjusted_mode.crtc_clock =
10672 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10673 &pipe_config->fdi_m_n);
10674 }
10675
10676 /** Returns the currently programmed mode of the given pipe. */
10677 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10678 struct drm_crtc *crtc)
10679 {
10680 struct drm_i915_private *dev_priv = dev->dev_private;
10681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10682 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10683 struct drm_display_mode *mode;
10684 struct intel_crtc_state pipe_config;
10685 int htot = I915_READ(HTOTAL(cpu_transcoder));
10686 int hsync = I915_READ(HSYNC(cpu_transcoder));
10687 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10688 int vsync = I915_READ(VSYNC(cpu_transcoder));
10689 enum pipe pipe = intel_crtc->pipe;
10690
10691 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10692 if (!mode)
10693 return NULL;
10694
10695 /*
10696 * Construct a pipe_config sufficient for getting the clock info
10697 * back out of crtc_clock_get.
10698 *
10699 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10700 * to use a real value here instead.
10701 */
10702 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10703 pipe_config.pixel_multiplier = 1;
10704 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10705 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10706 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10707 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10708
10709 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10710 mode->hdisplay = (htot & 0xffff) + 1;
10711 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10712 mode->hsync_start = (hsync & 0xffff) + 1;
10713 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10714 mode->vdisplay = (vtot & 0xffff) + 1;
10715 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10716 mode->vsync_start = (vsync & 0xffff) + 1;
10717 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10718
10719 drm_mode_set_name(mode);
10720
10721 return mode;
10722 }
10723
10724 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10725 {
10726 struct drm_device *dev = crtc->dev;
10727 struct drm_i915_private *dev_priv = dev->dev_private;
10728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10729
10730 if (!HAS_GMCH_DISPLAY(dev))
10731 return;
10732
10733 if (!dev_priv->lvds_downclock_avail)
10734 return;
10735
10736 /*
10737 * Since this is called by a timer, we should never get here in
10738 * the manual case.
10739 */
10740 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10741 int pipe = intel_crtc->pipe;
10742 int dpll_reg = DPLL(pipe);
10743 int dpll;
10744
10745 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10746
10747 assert_panel_unlocked(dev_priv, pipe);
10748
10749 dpll = I915_READ(dpll_reg);
10750 dpll |= DISPLAY_RATE_SELECT_FPA1;
10751 I915_WRITE(dpll_reg, dpll);
10752 intel_wait_for_vblank(dev, pipe);
10753 dpll = I915_READ(dpll_reg);
10754 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10755 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10756 }
10757
10758 }
10759
10760 void intel_mark_busy(struct drm_device *dev)
10761 {
10762 struct drm_i915_private *dev_priv = dev->dev_private;
10763
10764 if (dev_priv->mm.busy)
10765 return;
10766
10767 intel_runtime_pm_get(dev_priv);
10768 i915_update_gfx_val(dev_priv);
10769 if (INTEL_INFO(dev)->gen >= 6)
10770 gen6_rps_busy(dev_priv);
10771 dev_priv->mm.busy = true;
10772 }
10773
10774 void intel_mark_idle(struct drm_device *dev)
10775 {
10776 struct drm_i915_private *dev_priv = dev->dev_private;
10777 struct drm_crtc *crtc;
10778
10779 if (!dev_priv->mm.busy)
10780 return;
10781
10782 dev_priv->mm.busy = false;
10783
10784 for_each_crtc(dev, crtc) {
10785 if (!crtc->primary->fb)
10786 continue;
10787
10788 intel_decrease_pllclock(crtc);
10789 }
10790
10791 if (INTEL_INFO(dev)->gen >= 6)
10792 gen6_rps_idle(dev->dev_private);
10793
10794 intel_runtime_pm_put(dev_priv);
10795 }
10796
10797 static void intel_crtc_destroy(struct drm_crtc *crtc)
10798 {
10799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10800 struct drm_device *dev = crtc->dev;
10801 struct intel_unpin_work *work;
10802
10803 spin_lock_irq(&dev->event_lock);
10804 work = intel_crtc->unpin_work;
10805 intel_crtc->unpin_work = NULL;
10806 spin_unlock_irq(&dev->event_lock);
10807
10808 if (work) {
10809 cancel_work_sync(&work->work);
10810 kfree(work);
10811 }
10812
10813 drm_crtc_cleanup(crtc);
10814
10815 kfree(intel_crtc);
10816 }
10817
10818 static void intel_unpin_work_fn(struct work_struct *__work)
10819 {
10820 struct intel_unpin_work *work =
10821 container_of(__work, struct intel_unpin_work, work);
10822 struct drm_device *dev = work->crtc->dev;
10823 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10824
10825 mutex_lock(&dev->struct_mutex);
10826 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10827 drm_gem_object_unreference(&work->pending_flip_obj->base);
10828
10829 intel_fbc_update(dev);
10830
10831 if (work->flip_queued_req)
10832 i915_gem_request_assign(&work->flip_queued_req, NULL);
10833 mutex_unlock(&dev->struct_mutex);
10834
10835 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10836 drm_framebuffer_unreference(work->old_fb);
10837
10838 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10839 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10840
10841 kfree(work);
10842 }
10843
10844 static void do_intel_finish_page_flip(struct drm_device *dev,
10845 struct drm_crtc *crtc)
10846 {
10847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10848 struct intel_unpin_work *work;
10849 unsigned long flags;
10850
10851 /* Ignore early vblank irqs */
10852 if (intel_crtc == NULL)
10853 return;
10854
10855 /*
10856 * This is called both by irq handlers and the reset code (to complete
10857 * lost pageflips) so needs the full irqsave spinlocks.
10858 */
10859 spin_lock_irqsave(&dev->event_lock, flags);
10860 work = intel_crtc->unpin_work;
10861
10862 /* Ensure we don't miss a work->pending update ... */
10863 smp_rmb();
10864
10865 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10866 spin_unlock_irqrestore(&dev->event_lock, flags);
10867 return;
10868 }
10869
10870 page_flip_completed(intel_crtc);
10871
10872 spin_unlock_irqrestore(&dev->event_lock, flags);
10873 }
10874
10875 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10876 {
10877 struct drm_i915_private *dev_priv = dev->dev_private;
10878 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10879
10880 do_intel_finish_page_flip(dev, crtc);
10881 }
10882
10883 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10884 {
10885 struct drm_i915_private *dev_priv = dev->dev_private;
10886 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10887
10888 do_intel_finish_page_flip(dev, crtc);
10889 }
10890
10891 /* Is 'a' after or equal to 'b'? */
10892 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10893 {
10894 return !((a - b) & 0x80000000);
10895 }
10896
10897 static bool page_flip_finished(struct intel_crtc *crtc)
10898 {
10899 struct drm_device *dev = crtc->base.dev;
10900 struct drm_i915_private *dev_priv = dev->dev_private;
10901
10902 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10903 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10904 return true;
10905
10906 /*
10907 * The relevant registers doen't exist on pre-ctg.
10908 * As the flip done interrupt doesn't trigger for mmio
10909 * flips on gmch platforms, a flip count check isn't
10910 * really needed there. But since ctg has the registers,
10911 * include it in the check anyway.
10912 */
10913 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10914 return true;
10915
10916 /*
10917 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10918 * used the same base address. In that case the mmio flip might
10919 * have completed, but the CS hasn't even executed the flip yet.
10920 *
10921 * A flip count check isn't enough as the CS might have updated
10922 * the base address just after start of vblank, but before we
10923 * managed to process the interrupt. This means we'd complete the
10924 * CS flip too soon.
10925 *
10926 * Combining both checks should get us a good enough result. It may
10927 * still happen that the CS flip has been executed, but has not
10928 * yet actually completed. But in case the base address is the same
10929 * anyway, we don't really care.
10930 */
10931 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10932 crtc->unpin_work->gtt_offset &&
10933 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10934 crtc->unpin_work->flip_count);
10935 }
10936
10937 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10938 {
10939 struct drm_i915_private *dev_priv = dev->dev_private;
10940 struct intel_crtc *intel_crtc =
10941 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10942 unsigned long flags;
10943
10944
10945 /*
10946 * This is called both by irq handlers and the reset code (to complete
10947 * lost pageflips) so needs the full irqsave spinlocks.
10948 *
10949 * NB: An MMIO update of the plane base pointer will also
10950 * generate a page-flip completion irq, i.e. every modeset
10951 * is also accompanied by a spurious intel_prepare_page_flip().
10952 */
10953 spin_lock_irqsave(&dev->event_lock, flags);
10954 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10955 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10956 spin_unlock_irqrestore(&dev->event_lock, flags);
10957 }
10958
10959 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10960 {
10961 /* Ensure that the work item is consistent when activating it ... */
10962 smp_wmb();
10963 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10964 /* and that it is marked active as soon as the irq could fire. */
10965 smp_wmb();
10966 }
10967
10968 static int intel_gen2_queue_flip(struct drm_device *dev,
10969 struct drm_crtc *crtc,
10970 struct drm_framebuffer *fb,
10971 struct drm_i915_gem_object *obj,
10972 struct intel_engine_cs *ring,
10973 uint32_t flags)
10974 {
10975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10976 u32 flip_mask;
10977 int ret;
10978
10979 ret = intel_ring_begin(ring, 6);
10980 if (ret)
10981 return ret;
10982
10983 /* Can't queue multiple flips, so wait for the previous
10984 * one to finish before executing the next.
10985 */
10986 if (intel_crtc->plane)
10987 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10988 else
10989 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10990 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10991 intel_ring_emit(ring, MI_NOOP);
10992 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10993 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10994 intel_ring_emit(ring, fb->pitches[0]);
10995 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10996 intel_ring_emit(ring, 0); /* aux display base address, unused */
10997
10998 intel_mark_page_flip_active(intel_crtc);
10999 __intel_ring_advance(ring);
11000 return 0;
11001 }
11002
11003 static int intel_gen3_queue_flip(struct drm_device *dev,
11004 struct drm_crtc *crtc,
11005 struct drm_framebuffer *fb,
11006 struct drm_i915_gem_object *obj,
11007 struct intel_engine_cs *ring,
11008 uint32_t flags)
11009 {
11010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11011 u32 flip_mask;
11012 int ret;
11013
11014 ret = intel_ring_begin(ring, 6);
11015 if (ret)
11016 return ret;
11017
11018 if (intel_crtc->plane)
11019 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11020 else
11021 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11022 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11023 intel_ring_emit(ring, MI_NOOP);
11024 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11025 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11026 intel_ring_emit(ring, fb->pitches[0]);
11027 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11028 intel_ring_emit(ring, MI_NOOP);
11029
11030 intel_mark_page_flip_active(intel_crtc);
11031 __intel_ring_advance(ring);
11032 return 0;
11033 }
11034
11035 static int intel_gen4_queue_flip(struct drm_device *dev,
11036 struct drm_crtc *crtc,
11037 struct drm_framebuffer *fb,
11038 struct drm_i915_gem_object *obj,
11039 struct intel_engine_cs *ring,
11040 uint32_t flags)
11041 {
11042 struct drm_i915_private *dev_priv = dev->dev_private;
11043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11044 uint32_t pf, pipesrc;
11045 int ret;
11046
11047 ret = intel_ring_begin(ring, 4);
11048 if (ret)
11049 return ret;
11050
11051 /* i965+ uses the linear or tiled offsets from the
11052 * Display Registers (which do not change across a page-flip)
11053 * so we need only reprogram the base address.
11054 */
11055 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11056 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11057 intel_ring_emit(ring, fb->pitches[0]);
11058 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11059 obj->tiling_mode);
11060
11061 /* XXX Enabling the panel-fitter across page-flip is so far
11062 * untested on non-native modes, so ignore it for now.
11063 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11064 */
11065 pf = 0;
11066 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11067 intel_ring_emit(ring, pf | pipesrc);
11068
11069 intel_mark_page_flip_active(intel_crtc);
11070 __intel_ring_advance(ring);
11071 return 0;
11072 }
11073
11074 static int intel_gen6_queue_flip(struct drm_device *dev,
11075 struct drm_crtc *crtc,
11076 struct drm_framebuffer *fb,
11077 struct drm_i915_gem_object *obj,
11078 struct intel_engine_cs *ring,
11079 uint32_t flags)
11080 {
11081 struct drm_i915_private *dev_priv = dev->dev_private;
11082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11083 uint32_t pf, pipesrc;
11084 int ret;
11085
11086 ret = intel_ring_begin(ring, 4);
11087 if (ret)
11088 return ret;
11089
11090 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11091 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11092 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11093 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11094
11095 /* Contrary to the suggestions in the documentation,
11096 * "Enable Panel Fitter" does not seem to be required when page
11097 * flipping with a non-native mode, and worse causes a normal
11098 * modeset to fail.
11099 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11100 */
11101 pf = 0;
11102 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11103 intel_ring_emit(ring, pf | pipesrc);
11104
11105 intel_mark_page_flip_active(intel_crtc);
11106 __intel_ring_advance(ring);
11107 return 0;
11108 }
11109
11110 static int intel_gen7_queue_flip(struct drm_device *dev,
11111 struct drm_crtc *crtc,
11112 struct drm_framebuffer *fb,
11113 struct drm_i915_gem_object *obj,
11114 struct intel_engine_cs *ring,
11115 uint32_t flags)
11116 {
11117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11118 uint32_t plane_bit = 0;
11119 int len, ret;
11120
11121 switch (intel_crtc->plane) {
11122 case PLANE_A:
11123 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11124 break;
11125 case PLANE_B:
11126 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11127 break;
11128 case PLANE_C:
11129 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11130 break;
11131 default:
11132 WARN_ONCE(1, "unknown plane in flip command\n");
11133 return -ENODEV;
11134 }
11135
11136 len = 4;
11137 if (ring->id == RCS) {
11138 len += 6;
11139 /*
11140 * On Gen 8, SRM is now taking an extra dword to accommodate
11141 * 48bits addresses, and we need a NOOP for the batch size to
11142 * stay even.
11143 */
11144 if (IS_GEN8(dev))
11145 len += 2;
11146 }
11147
11148 /*
11149 * BSpec MI_DISPLAY_FLIP for IVB:
11150 * "The full packet must be contained within the same cache line."
11151 *
11152 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11153 * cacheline, if we ever start emitting more commands before
11154 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11155 * then do the cacheline alignment, and finally emit the
11156 * MI_DISPLAY_FLIP.
11157 */
11158 ret = intel_ring_cacheline_align(ring);
11159 if (ret)
11160 return ret;
11161
11162 ret = intel_ring_begin(ring, len);
11163 if (ret)
11164 return ret;
11165
11166 /* Unmask the flip-done completion message. Note that the bspec says that
11167 * we should do this for both the BCS and RCS, and that we must not unmask
11168 * more than one flip event at any time (or ensure that one flip message
11169 * can be sent by waiting for flip-done prior to queueing new flips).
11170 * Experimentation says that BCS works despite DERRMR masking all
11171 * flip-done completion events and that unmasking all planes at once
11172 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11173 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11174 */
11175 if (ring->id == RCS) {
11176 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11177 intel_ring_emit(ring, DERRMR);
11178 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11179 DERRMR_PIPEB_PRI_FLIP_DONE |
11180 DERRMR_PIPEC_PRI_FLIP_DONE));
11181 if (IS_GEN8(dev))
11182 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11183 MI_SRM_LRM_GLOBAL_GTT);
11184 else
11185 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11186 MI_SRM_LRM_GLOBAL_GTT);
11187 intel_ring_emit(ring, DERRMR);
11188 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11189 if (IS_GEN8(dev)) {
11190 intel_ring_emit(ring, 0);
11191 intel_ring_emit(ring, MI_NOOP);
11192 }
11193 }
11194
11195 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11196 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11197 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11198 intel_ring_emit(ring, (MI_NOOP));
11199
11200 intel_mark_page_flip_active(intel_crtc);
11201 __intel_ring_advance(ring);
11202 return 0;
11203 }
11204
11205 static bool use_mmio_flip(struct intel_engine_cs *ring,
11206 struct drm_i915_gem_object *obj)
11207 {
11208 /*
11209 * This is not being used for older platforms, because
11210 * non-availability of flip done interrupt forces us to use
11211 * CS flips. Older platforms derive flip done using some clever
11212 * tricks involving the flip_pending status bits and vblank irqs.
11213 * So using MMIO flips there would disrupt this mechanism.
11214 */
11215
11216 if (ring == NULL)
11217 return true;
11218
11219 if (INTEL_INFO(ring->dev)->gen < 5)
11220 return false;
11221
11222 if (i915.use_mmio_flip < 0)
11223 return false;
11224 else if (i915.use_mmio_flip > 0)
11225 return true;
11226 else if (i915.enable_execlists)
11227 return true;
11228 else
11229 return ring != i915_gem_request_get_ring(obj->last_write_req);
11230 }
11231
11232 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11233 {
11234 struct drm_device *dev = intel_crtc->base.dev;
11235 struct drm_i915_private *dev_priv = dev->dev_private;
11236 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11237 const enum pipe pipe = intel_crtc->pipe;
11238 u32 ctl, stride;
11239
11240 ctl = I915_READ(PLANE_CTL(pipe, 0));
11241 ctl &= ~PLANE_CTL_TILED_MASK;
11242 switch (fb->modifier[0]) {
11243 case DRM_FORMAT_MOD_NONE:
11244 break;
11245 case I915_FORMAT_MOD_X_TILED:
11246 ctl |= PLANE_CTL_TILED_X;
11247 break;
11248 case I915_FORMAT_MOD_Y_TILED:
11249 ctl |= PLANE_CTL_TILED_Y;
11250 break;
11251 case I915_FORMAT_MOD_Yf_TILED:
11252 ctl |= PLANE_CTL_TILED_YF;
11253 break;
11254 default:
11255 MISSING_CASE(fb->modifier[0]);
11256 }
11257
11258 /*
11259 * The stride is either expressed as a multiple of 64 bytes chunks for
11260 * linear buffers or in number of tiles for tiled buffers.
11261 */
11262 stride = fb->pitches[0] /
11263 intel_fb_stride_alignment(dev, fb->modifier[0],
11264 fb->pixel_format);
11265
11266 /*
11267 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11268 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11269 */
11270 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11271 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11272
11273 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11274 POSTING_READ(PLANE_SURF(pipe, 0));
11275 }
11276
11277 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11278 {
11279 struct drm_device *dev = intel_crtc->base.dev;
11280 struct drm_i915_private *dev_priv = dev->dev_private;
11281 struct intel_framebuffer *intel_fb =
11282 to_intel_framebuffer(intel_crtc->base.primary->fb);
11283 struct drm_i915_gem_object *obj = intel_fb->obj;
11284 u32 dspcntr;
11285 u32 reg;
11286
11287 reg = DSPCNTR(intel_crtc->plane);
11288 dspcntr = I915_READ(reg);
11289
11290 if (obj->tiling_mode != I915_TILING_NONE)
11291 dspcntr |= DISPPLANE_TILED;
11292 else
11293 dspcntr &= ~DISPPLANE_TILED;
11294
11295 I915_WRITE(reg, dspcntr);
11296
11297 I915_WRITE(DSPSURF(intel_crtc->plane),
11298 intel_crtc->unpin_work->gtt_offset);
11299 POSTING_READ(DSPSURF(intel_crtc->plane));
11300
11301 }
11302
11303 /*
11304 * XXX: This is the temporary way to update the plane registers until we get
11305 * around to using the usual plane update functions for MMIO flips
11306 */
11307 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11308 {
11309 struct drm_device *dev = intel_crtc->base.dev;
11310 bool atomic_update;
11311 u32 start_vbl_count;
11312
11313 intel_mark_page_flip_active(intel_crtc);
11314
11315 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11316
11317 if (INTEL_INFO(dev)->gen >= 9)
11318 skl_do_mmio_flip(intel_crtc);
11319 else
11320 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11321 ilk_do_mmio_flip(intel_crtc);
11322
11323 if (atomic_update)
11324 intel_pipe_update_end(intel_crtc, start_vbl_count);
11325 }
11326
11327 static void intel_mmio_flip_work_func(struct work_struct *work)
11328 {
11329 struct intel_mmio_flip *mmio_flip =
11330 container_of(work, struct intel_mmio_flip, work);
11331
11332 if (mmio_flip->req)
11333 WARN_ON(__i915_wait_request(mmio_flip->req,
11334 mmio_flip->crtc->reset_counter,
11335 false, NULL,
11336 &mmio_flip->i915->rps.mmioflips));
11337
11338 intel_do_mmio_flip(mmio_flip->crtc);
11339
11340 i915_gem_request_unreference__unlocked(mmio_flip->req);
11341 kfree(mmio_flip);
11342 }
11343
11344 static int intel_queue_mmio_flip(struct drm_device *dev,
11345 struct drm_crtc *crtc,
11346 struct drm_framebuffer *fb,
11347 struct drm_i915_gem_object *obj,
11348 struct intel_engine_cs *ring,
11349 uint32_t flags)
11350 {
11351 struct intel_mmio_flip *mmio_flip;
11352
11353 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11354 if (mmio_flip == NULL)
11355 return -ENOMEM;
11356
11357 mmio_flip->i915 = to_i915(dev);
11358 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11359 mmio_flip->crtc = to_intel_crtc(crtc);
11360
11361 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11362 schedule_work(&mmio_flip->work);
11363
11364 return 0;
11365 }
11366
11367 static int intel_default_queue_flip(struct drm_device *dev,
11368 struct drm_crtc *crtc,
11369 struct drm_framebuffer *fb,
11370 struct drm_i915_gem_object *obj,
11371 struct intel_engine_cs *ring,
11372 uint32_t flags)
11373 {
11374 return -ENODEV;
11375 }
11376
11377 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11378 struct drm_crtc *crtc)
11379 {
11380 struct drm_i915_private *dev_priv = dev->dev_private;
11381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11382 struct intel_unpin_work *work = intel_crtc->unpin_work;
11383 u32 addr;
11384
11385 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11386 return true;
11387
11388 if (!work->enable_stall_check)
11389 return false;
11390
11391 if (work->flip_ready_vblank == 0) {
11392 if (work->flip_queued_req &&
11393 !i915_gem_request_completed(work->flip_queued_req, true))
11394 return false;
11395
11396 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11397 }
11398
11399 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11400 return false;
11401
11402 /* Potential stall - if we see that the flip has happened,
11403 * assume a missed interrupt. */
11404 if (INTEL_INFO(dev)->gen >= 4)
11405 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11406 else
11407 addr = I915_READ(DSPADDR(intel_crtc->plane));
11408
11409 /* There is a potential issue here with a false positive after a flip
11410 * to the same address. We could address this by checking for a
11411 * non-incrementing frame counter.
11412 */
11413 return addr == work->gtt_offset;
11414 }
11415
11416 void intel_check_page_flip(struct drm_device *dev, int pipe)
11417 {
11418 struct drm_i915_private *dev_priv = dev->dev_private;
11419 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11421 struct intel_unpin_work *work;
11422
11423 WARN_ON(!in_interrupt());
11424
11425 if (crtc == NULL)
11426 return;
11427
11428 spin_lock(&dev->event_lock);
11429 work = intel_crtc->unpin_work;
11430 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11431 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11432 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11433 page_flip_completed(intel_crtc);
11434 work = NULL;
11435 }
11436 if (work != NULL &&
11437 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11438 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11439 spin_unlock(&dev->event_lock);
11440 }
11441
11442 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11443 struct drm_framebuffer *fb,
11444 struct drm_pending_vblank_event *event,
11445 uint32_t page_flip_flags)
11446 {
11447 struct drm_device *dev = crtc->dev;
11448 struct drm_i915_private *dev_priv = dev->dev_private;
11449 struct drm_framebuffer *old_fb = crtc->primary->fb;
11450 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11452 struct drm_plane *primary = crtc->primary;
11453 enum pipe pipe = intel_crtc->pipe;
11454 struct intel_unpin_work *work;
11455 struct intel_engine_cs *ring;
11456 bool mmio_flip;
11457 int ret;
11458
11459 /*
11460 * drm_mode_page_flip_ioctl() should already catch this, but double
11461 * check to be safe. In the future we may enable pageflipping from
11462 * a disabled primary plane.
11463 */
11464 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11465 return -EBUSY;
11466
11467 /* Can't change pixel format via MI display flips. */
11468 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11469 return -EINVAL;
11470
11471 /*
11472 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11473 * Note that pitch changes could also affect these register.
11474 */
11475 if (INTEL_INFO(dev)->gen > 3 &&
11476 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11477 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11478 return -EINVAL;
11479
11480 if (i915_terminally_wedged(&dev_priv->gpu_error))
11481 goto out_hang;
11482
11483 work = kzalloc(sizeof(*work), GFP_KERNEL);
11484 if (work == NULL)
11485 return -ENOMEM;
11486
11487 work->event = event;
11488 work->crtc = crtc;
11489 work->old_fb = old_fb;
11490 INIT_WORK(&work->work, intel_unpin_work_fn);
11491
11492 ret = drm_crtc_vblank_get(crtc);
11493 if (ret)
11494 goto free_work;
11495
11496 /* We borrow the event spin lock for protecting unpin_work */
11497 spin_lock_irq(&dev->event_lock);
11498 if (intel_crtc->unpin_work) {
11499 /* Before declaring the flip queue wedged, check if
11500 * the hardware completed the operation behind our backs.
11501 */
11502 if (__intel_pageflip_stall_check(dev, crtc)) {
11503 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11504 page_flip_completed(intel_crtc);
11505 } else {
11506 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11507 spin_unlock_irq(&dev->event_lock);
11508
11509 drm_crtc_vblank_put(crtc);
11510 kfree(work);
11511 return -EBUSY;
11512 }
11513 }
11514 intel_crtc->unpin_work = work;
11515 spin_unlock_irq(&dev->event_lock);
11516
11517 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11518 flush_workqueue(dev_priv->wq);
11519
11520 /* Reference the objects for the scheduled work. */
11521 drm_framebuffer_reference(work->old_fb);
11522 drm_gem_object_reference(&obj->base);
11523
11524 crtc->primary->fb = fb;
11525 update_state_fb(crtc->primary);
11526
11527 work->pending_flip_obj = obj;
11528
11529 ret = i915_mutex_lock_interruptible(dev);
11530 if (ret)
11531 goto cleanup;
11532
11533 atomic_inc(&intel_crtc->unpin_work_count);
11534 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11535
11536 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11537 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11538
11539 if (IS_VALLEYVIEW(dev)) {
11540 ring = &dev_priv->ring[BCS];
11541 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11542 /* vlv: DISPLAY_FLIP fails to change tiling */
11543 ring = NULL;
11544 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11545 ring = &dev_priv->ring[BCS];
11546 } else if (INTEL_INFO(dev)->gen >= 7) {
11547 ring = i915_gem_request_get_ring(obj->last_write_req);
11548 if (ring == NULL || ring->id != RCS)
11549 ring = &dev_priv->ring[BCS];
11550 } else {
11551 ring = &dev_priv->ring[RCS];
11552 }
11553
11554 mmio_flip = use_mmio_flip(ring, obj);
11555
11556 /* When using CS flips, we want to emit semaphores between rings.
11557 * However, when using mmio flips we will create a task to do the
11558 * synchronisation, so all we want here is to pin the framebuffer
11559 * into the display plane and skip any waits.
11560 */
11561 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11562 crtc->primary->state,
11563 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11564 if (ret)
11565 goto cleanup_pending;
11566
11567 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11568 + intel_crtc->dspaddr_offset;
11569
11570 if (mmio_flip) {
11571 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11572 page_flip_flags);
11573 if (ret)
11574 goto cleanup_unpin;
11575
11576 i915_gem_request_assign(&work->flip_queued_req,
11577 obj->last_write_req);
11578 } else {
11579 if (obj->last_write_req) {
11580 ret = i915_gem_check_olr(obj->last_write_req);
11581 if (ret)
11582 goto cleanup_unpin;
11583 }
11584
11585 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11586 page_flip_flags);
11587 if (ret)
11588 goto cleanup_unpin;
11589
11590 i915_gem_request_assign(&work->flip_queued_req,
11591 intel_ring_get_request(ring));
11592 }
11593
11594 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11595 work->enable_stall_check = true;
11596
11597 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11598 INTEL_FRONTBUFFER_PRIMARY(pipe));
11599
11600 intel_fbc_disable(dev);
11601 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11602 mutex_unlock(&dev->struct_mutex);
11603
11604 trace_i915_flip_request(intel_crtc->plane, obj);
11605
11606 return 0;
11607
11608 cleanup_unpin:
11609 intel_unpin_fb_obj(fb, crtc->primary->state);
11610 cleanup_pending:
11611 atomic_dec(&intel_crtc->unpin_work_count);
11612 mutex_unlock(&dev->struct_mutex);
11613 cleanup:
11614 crtc->primary->fb = old_fb;
11615 update_state_fb(crtc->primary);
11616
11617 drm_gem_object_unreference_unlocked(&obj->base);
11618 drm_framebuffer_unreference(work->old_fb);
11619
11620 spin_lock_irq(&dev->event_lock);
11621 intel_crtc->unpin_work = NULL;
11622 spin_unlock_irq(&dev->event_lock);
11623
11624 drm_crtc_vblank_put(crtc);
11625 free_work:
11626 kfree(work);
11627
11628 if (ret == -EIO) {
11629 out_hang:
11630 ret = intel_plane_restore(primary);
11631 if (ret == 0 && event) {
11632 spin_lock_irq(&dev->event_lock);
11633 drm_send_vblank_event(dev, pipe, event);
11634 spin_unlock_irq(&dev->event_lock);
11635 }
11636 }
11637 return ret;
11638 }
11639
11640 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11641 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11642 .load_lut = intel_crtc_load_lut,
11643 .atomic_begin = intel_begin_crtc_commit,
11644 .atomic_flush = intel_finish_crtc_commit,
11645 };
11646
11647 /**
11648 * intel_modeset_update_staged_output_state
11649 *
11650 * Updates the staged output configuration state, e.g. after we've read out the
11651 * current hw state.
11652 */
11653 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11654 {
11655 struct intel_crtc *crtc;
11656 struct intel_encoder *encoder;
11657 struct intel_connector *connector;
11658
11659 for_each_intel_connector(dev, connector) {
11660 connector->new_encoder =
11661 to_intel_encoder(connector->base.encoder);
11662 }
11663
11664 for_each_intel_encoder(dev, encoder) {
11665 encoder->new_crtc =
11666 to_intel_crtc(encoder->base.crtc);
11667 }
11668
11669 for_each_intel_crtc(dev, crtc) {
11670 crtc->new_enabled = crtc->base.state->enable;
11671 }
11672 }
11673
11674 /* Transitional helper to copy current connector/encoder state to
11675 * connector->state. This is needed so that code that is partially
11676 * converted to atomic does the right thing.
11677 */
11678 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11679 {
11680 struct intel_connector *connector;
11681
11682 for_each_intel_connector(dev, connector) {
11683 if (connector->base.encoder) {
11684 connector->base.state->best_encoder =
11685 connector->base.encoder;
11686 connector->base.state->crtc =
11687 connector->base.encoder->crtc;
11688 } else {
11689 connector->base.state->best_encoder = NULL;
11690 connector->base.state->crtc = NULL;
11691 }
11692 }
11693 }
11694
11695 static void
11696 connected_sink_compute_bpp(struct intel_connector *connector,
11697 struct intel_crtc_state *pipe_config)
11698 {
11699 int bpp = pipe_config->pipe_bpp;
11700
11701 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11702 connector->base.base.id,
11703 connector->base.name);
11704
11705 /* Don't use an invalid EDID bpc value */
11706 if (connector->base.display_info.bpc &&
11707 connector->base.display_info.bpc * 3 < bpp) {
11708 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11709 bpp, connector->base.display_info.bpc*3);
11710 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11711 }
11712
11713 /* Clamp bpp to 8 on screens without EDID 1.4 */
11714 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11715 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11716 bpp);
11717 pipe_config->pipe_bpp = 24;
11718 }
11719 }
11720
11721 static int
11722 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11723 struct intel_crtc_state *pipe_config)
11724 {
11725 struct drm_device *dev = crtc->base.dev;
11726 struct drm_atomic_state *state;
11727 struct drm_connector *connector;
11728 struct drm_connector_state *connector_state;
11729 int bpp, i;
11730
11731 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11732 bpp = 10*3;
11733 else if (INTEL_INFO(dev)->gen >= 5)
11734 bpp = 12*3;
11735 else
11736 bpp = 8*3;
11737
11738
11739 pipe_config->pipe_bpp = bpp;
11740
11741 state = pipe_config->base.state;
11742
11743 /* Clamp display bpp to EDID value */
11744 for_each_connector_in_state(state, connector, connector_state, i) {
11745 if (connector_state->crtc != &crtc->base)
11746 continue;
11747
11748 connected_sink_compute_bpp(to_intel_connector(connector),
11749 pipe_config);
11750 }
11751
11752 return bpp;
11753 }
11754
11755 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11756 {
11757 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11758 "type: 0x%x flags: 0x%x\n",
11759 mode->crtc_clock,
11760 mode->crtc_hdisplay, mode->crtc_hsync_start,
11761 mode->crtc_hsync_end, mode->crtc_htotal,
11762 mode->crtc_vdisplay, mode->crtc_vsync_start,
11763 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11764 }
11765
11766 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11767 struct intel_crtc_state *pipe_config,
11768 const char *context)
11769 {
11770 struct drm_device *dev = crtc->base.dev;
11771 struct drm_plane *plane;
11772 struct intel_plane *intel_plane;
11773 struct intel_plane_state *state;
11774 struct drm_framebuffer *fb;
11775
11776 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11777 context, pipe_config, pipe_name(crtc->pipe));
11778
11779 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11780 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11781 pipe_config->pipe_bpp, pipe_config->dither);
11782 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11783 pipe_config->has_pch_encoder,
11784 pipe_config->fdi_lanes,
11785 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11786 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11787 pipe_config->fdi_m_n.tu);
11788 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11789 pipe_config->has_dp_encoder,
11790 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11791 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11792 pipe_config->dp_m_n.tu);
11793
11794 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11795 pipe_config->has_dp_encoder,
11796 pipe_config->dp_m2_n2.gmch_m,
11797 pipe_config->dp_m2_n2.gmch_n,
11798 pipe_config->dp_m2_n2.link_m,
11799 pipe_config->dp_m2_n2.link_n,
11800 pipe_config->dp_m2_n2.tu);
11801
11802 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11803 pipe_config->has_audio,
11804 pipe_config->has_infoframe);
11805
11806 DRM_DEBUG_KMS("requested mode:\n");
11807 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11808 DRM_DEBUG_KMS("adjusted mode:\n");
11809 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11810 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11811 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11812 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11813 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11814 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11815 crtc->num_scalers,
11816 pipe_config->scaler_state.scaler_users,
11817 pipe_config->scaler_state.scaler_id);
11818 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11819 pipe_config->gmch_pfit.control,
11820 pipe_config->gmch_pfit.pgm_ratios,
11821 pipe_config->gmch_pfit.lvds_border_bits);
11822 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11823 pipe_config->pch_pfit.pos,
11824 pipe_config->pch_pfit.size,
11825 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11826 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11827 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11828
11829 if (IS_BROXTON(dev)) {
11830 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11831 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11832 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11833 pipe_config->ddi_pll_sel,
11834 pipe_config->dpll_hw_state.ebb0,
11835 pipe_config->dpll_hw_state.pll0,
11836 pipe_config->dpll_hw_state.pll1,
11837 pipe_config->dpll_hw_state.pll2,
11838 pipe_config->dpll_hw_state.pll3,
11839 pipe_config->dpll_hw_state.pll6,
11840 pipe_config->dpll_hw_state.pll8,
11841 pipe_config->dpll_hw_state.pcsdw12);
11842 } else if (IS_SKYLAKE(dev)) {
11843 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11844 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11845 pipe_config->ddi_pll_sel,
11846 pipe_config->dpll_hw_state.ctrl1,
11847 pipe_config->dpll_hw_state.cfgcr1,
11848 pipe_config->dpll_hw_state.cfgcr2);
11849 } else if (HAS_DDI(dev)) {
11850 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11851 pipe_config->ddi_pll_sel,
11852 pipe_config->dpll_hw_state.wrpll);
11853 } else {
11854 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11855 "fp0: 0x%x, fp1: 0x%x\n",
11856 pipe_config->dpll_hw_state.dpll,
11857 pipe_config->dpll_hw_state.dpll_md,
11858 pipe_config->dpll_hw_state.fp0,
11859 pipe_config->dpll_hw_state.fp1);
11860 }
11861
11862 DRM_DEBUG_KMS("planes on this crtc\n");
11863 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11864 intel_plane = to_intel_plane(plane);
11865 if (intel_plane->pipe != crtc->pipe)
11866 continue;
11867
11868 state = to_intel_plane_state(plane->state);
11869 fb = state->base.fb;
11870 if (!fb) {
11871 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11872 "disabled, scaler_id = %d\n",
11873 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11874 plane->base.id, intel_plane->pipe,
11875 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11876 drm_plane_index(plane), state->scaler_id);
11877 continue;
11878 }
11879
11880 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11881 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11882 plane->base.id, intel_plane->pipe,
11883 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11884 drm_plane_index(plane));
11885 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11886 fb->base.id, fb->width, fb->height, fb->pixel_format);
11887 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11888 state->scaler_id,
11889 state->src.x1 >> 16, state->src.y1 >> 16,
11890 drm_rect_width(&state->src) >> 16,
11891 drm_rect_height(&state->src) >> 16,
11892 state->dst.x1, state->dst.y1,
11893 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11894 }
11895 }
11896
11897 static bool encoders_cloneable(const struct intel_encoder *a,
11898 const struct intel_encoder *b)
11899 {
11900 /* masks could be asymmetric, so check both ways */
11901 return a == b || (a->cloneable & (1 << b->type) &&
11902 b->cloneable & (1 << a->type));
11903 }
11904
11905 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11906 struct intel_crtc *crtc,
11907 struct intel_encoder *encoder)
11908 {
11909 struct intel_encoder *source_encoder;
11910 struct drm_connector *connector;
11911 struct drm_connector_state *connector_state;
11912 int i;
11913
11914 for_each_connector_in_state(state, connector, connector_state, i) {
11915 if (connector_state->crtc != &crtc->base)
11916 continue;
11917
11918 source_encoder =
11919 to_intel_encoder(connector_state->best_encoder);
11920 if (!encoders_cloneable(encoder, source_encoder))
11921 return false;
11922 }
11923
11924 return true;
11925 }
11926
11927 static bool check_encoder_cloning(struct drm_atomic_state *state,
11928 struct intel_crtc *crtc)
11929 {
11930 struct intel_encoder *encoder;
11931 struct drm_connector *connector;
11932 struct drm_connector_state *connector_state;
11933 int i;
11934
11935 for_each_connector_in_state(state, connector, connector_state, i) {
11936 if (connector_state->crtc != &crtc->base)
11937 continue;
11938
11939 encoder = to_intel_encoder(connector_state->best_encoder);
11940 if (!check_single_encoder_cloning(state, crtc, encoder))
11941 return false;
11942 }
11943
11944 return true;
11945 }
11946
11947 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11948 {
11949 struct drm_device *dev = state->dev;
11950 struct intel_encoder *encoder;
11951 struct drm_connector *connector;
11952 struct drm_connector_state *connector_state;
11953 unsigned int used_ports = 0;
11954 int i;
11955
11956 /*
11957 * Walk the connector list instead of the encoder
11958 * list to detect the problem on ddi platforms
11959 * where there's just one encoder per digital port.
11960 */
11961 for_each_connector_in_state(state, connector, connector_state, i) {
11962 if (!connector_state->best_encoder)
11963 continue;
11964
11965 encoder = to_intel_encoder(connector_state->best_encoder);
11966
11967 WARN_ON(!connector_state->crtc);
11968
11969 switch (encoder->type) {
11970 unsigned int port_mask;
11971 case INTEL_OUTPUT_UNKNOWN:
11972 if (WARN_ON(!HAS_DDI(dev)))
11973 break;
11974 case INTEL_OUTPUT_DISPLAYPORT:
11975 case INTEL_OUTPUT_HDMI:
11976 case INTEL_OUTPUT_EDP:
11977 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11978
11979 /* the same port mustn't appear more than once */
11980 if (used_ports & port_mask)
11981 return false;
11982
11983 used_ports |= port_mask;
11984 default:
11985 break;
11986 }
11987 }
11988
11989 return true;
11990 }
11991
11992 static void
11993 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11994 {
11995 struct drm_crtc_state tmp_state;
11996 struct intel_crtc_scaler_state scaler_state;
11997 struct intel_dpll_hw_state dpll_hw_state;
11998 enum intel_dpll_id shared_dpll;
11999 uint32_t ddi_pll_sel;
12000
12001 /* FIXME: before the switch to atomic started, a new pipe_config was
12002 * kzalloc'd. Code that depends on any field being zero should be
12003 * fixed, so that the crtc_state can be safely duplicated. For now,
12004 * only fields that are know to not cause problems are preserved. */
12005
12006 tmp_state = crtc_state->base;
12007 scaler_state = crtc_state->scaler_state;
12008 shared_dpll = crtc_state->shared_dpll;
12009 dpll_hw_state = crtc_state->dpll_hw_state;
12010 ddi_pll_sel = crtc_state->ddi_pll_sel;
12011
12012 memset(crtc_state, 0, sizeof *crtc_state);
12013
12014 crtc_state->base = tmp_state;
12015 crtc_state->scaler_state = scaler_state;
12016 crtc_state->shared_dpll = shared_dpll;
12017 crtc_state->dpll_hw_state = dpll_hw_state;
12018 crtc_state->ddi_pll_sel = ddi_pll_sel;
12019 }
12020
12021 static int
12022 intel_modeset_pipe_config(struct drm_crtc *crtc,
12023 struct drm_atomic_state *state)
12024 {
12025 struct drm_crtc_state *crtc_state;
12026 struct intel_crtc_state *pipe_config;
12027 struct intel_encoder *encoder;
12028 struct drm_connector *connector;
12029 struct drm_connector_state *connector_state;
12030 int base_bpp, ret = -EINVAL;
12031 int i;
12032 bool retry = true;
12033
12034 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
12035 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12036 return -EINVAL;
12037 }
12038
12039 if (!check_digital_port_conflicts(state)) {
12040 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12041 return -EINVAL;
12042 }
12043
12044 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12045 if (WARN_ON(!crtc_state))
12046 return -EINVAL;
12047
12048 pipe_config = to_intel_crtc_state(crtc_state);
12049
12050 /*
12051 * XXX: Add all connectors to make the crtc state match the encoders.
12052 */
12053 if (!needs_modeset(&pipe_config->base)) {
12054 ret = drm_atomic_add_affected_connectors(state, crtc);
12055 if (ret)
12056 return ret;
12057 }
12058
12059 clear_intel_crtc_state(pipe_config);
12060
12061 pipe_config->cpu_transcoder =
12062 (enum transcoder) to_intel_crtc(crtc)->pipe;
12063
12064 /*
12065 * Sanitize sync polarity flags based on requested ones. If neither
12066 * positive or negative polarity is requested, treat this as meaning
12067 * negative polarity.
12068 */
12069 if (!(pipe_config->base.adjusted_mode.flags &
12070 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12071 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12072
12073 if (!(pipe_config->base.adjusted_mode.flags &
12074 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12075 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12076
12077 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12078 * plane pixel format and any sink constraints into account. Returns the
12079 * source plane bpp so that dithering can be selected on mismatches
12080 * after encoders and crtc also have had their say. */
12081 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12082 pipe_config);
12083 if (base_bpp < 0)
12084 goto fail;
12085
12086 /*
12087 * Determine the real pipe dimensions. Note that stereo modes can
12088 * increase the actual pipe size due to the frame doubling and
12089 * insertion of additional space for blanks between the frame. This
12090 * is stored in the crtc timings. We use the requested mode to do this
12091 * computation to clearly distinguish it from the adjusted mode, which
12092 * can be changed by the connectors in the below retry loop.
12093 */
12094 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12095 &pipe_config->pipe_src_w,
12096 &pipe_config->pipe_src_h);
12097
12098 encoder_retry:
12099 /* Ensure the port clock defaults are reset when retrying. */
12100 pipe_config->port_clock = 0;
12101 pipe_config->pixel_multiplier = 1;
12102
12103 /* Fill in default crtc timings, allow encoders to overwrite them. */
12104 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12105 CRTC_STEREO_DOUBLE);
12106
12107 /* Pass our mode to the connectors and the CRTC to give them a chance to
12108 * adjust it according to limitations or connector properties, and also
12109 * a chance to reject the mode entirely.
12110 */
12111 for_each_connector_in_state(state, connector, connector_state, i) {
12112 if (connector_state->crtc != crtc)
12113 continue;
12114
12115 encoder = to_intel_encoder(connector_state->best_encoder);
12116
12117 if (!(encoder->compute_config(encoder, pipe_config))) {
12118 DRM_DEBUG_KMS("Encoder config failure\n");
12119 goto fail;
12120 }
12121 }
12122
12123 /* Set default port clock if not overwritten by the encoder. Needs to be
12124 * done afterwards in case the encoder adjusts the mode. */
12125 if (!pipe_config->port_clock)
12126 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12127 * pipe_config->pixel_multiplier;
12128
12129 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12130 if (ret < 0) {
12131 DRM_DEBUG_KMS("CRTC fixup failed\n");
12132 goto fail;
12133 }
12134
12135 if (ret == RETRY) {
12136 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12137 ret = -EINVAL;
12138 goto fail;
12139 }
12140
12141 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12142 retry = false;
12143 goto encoder_retry;
12144 }
12145
12146 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12147 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12148 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12149
12150 /* Check if we need to force a modeset */
12151 if (pipe_config->has_audio !=
12152 to_intel_crtc_state(crtc->state)->has_audio) {
12153 pipe_config->base.mode_changed = true;
12154 ret = drm_atomic_add_affected_planes(state, crtc);
12155 }
12156
12157 /*
12158 * Note we have an issue here with infoframes: current code
12159 * only updates them on the full mode set path per hw
12160 * requirements. So here we should be checking for any
12161 * required changes and forcing a mode set.
12162 */
12163 fail:
12164 return ret;
12165 }
12166
12167 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12168 {
12169 struct drm_encoder *encoder;
12170 struct drm_device *dev = crtc->dev;
12171
12172 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12173 if (encoder->crtc == crtc)
12174 return true;
12175
12176 return false;
12177 }
12178
12179 static void
12180 intel_modeset_update_state(struct drm_atomic_state *state)
12181 {
12182 struct drm_device *dev = state->dev;
12183 struct intel_encoder *intel_encoder;
12184 struct drm_crtc *crtc;
12185 struct drm_crtc_state *crtc_state;
12186 struct drm_connector *connector;
12187
12188 intel_shared_dpll_commit(state);
12189 drm_atomic_helper_swap_state(state->dev, state);
12190
12191 for_each_intel_encoder(dev, intel_encoder) {
12192 if (!intel_encoder->base.crtc)
12193 continue;
12194
12195 crtc = intel_encoder->base.crtc;
12196 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12197 if (!crtc_state || !needs_modeset(crtc->state))
12198 continue;
12199
12200 intel_encoder->connectors_active = false;
12201 }
12202
12203 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12204 intel_modeset_update_staged_output_state(state->dev);
12205
12206 /* Double check state. */
12207 for_each_crtc(dev, crtc) {
12208 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12209
12210 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12211 }
12212
12213 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12214 if (!connector->encoder || !connector->encoder->crtc)
12215 continue;
12216
12217 crtc = connector->encoder->crtc;
12218 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12219 if (!crtc_state || !needs_modeset(crtc->state))
12220 continue;
12221
12222 if (crtc->state->active) {
12223 struct drm_property *dpms_property =
12224 dev->mode_config.dpms_property;
12225
12226 connector->dpms = DRM_MODE_DPMS_ON;
12227 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12228
12229 intel_encoder = to_intel_encoder(connector->encoder);
12230 intel_encoder->connectors_active = true;
12231 } else
12232 connector->dpms = DRM_MODE_DPMS_OFF;
12233 }
12234 }
12235
12236 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12237 {
12238 int diff;
12239
12240 if (clock1 == clock2)
12241 return true;
12242
12243 if (!clock1 || !clock2)
12244 return false;
12245
12246 diff = abs(clock1 - clock2);
12247
12248 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12249 return true;
12250
12251 return false;
12252 }
12253
12254 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12255 list_for_each_entry((intel_crtc), \
12256 &(dev)->mode_config.crtc_list, \
12257 base.head) \
12258 if (mask & (1 <<(intel_crtc)->pipe))
12259
12260 static bool
12261 intel_pipe_config_compare(struct drm_device *dev,
12262 struct intel_crtc_state *current_config,
12263 struct intel_crtc_state *pipe_config)
12264 {
12265 #define PIPE_CONF_CHECK_X(name) \
12266 if (current_config->name != pipe_config->name) { \
12267 DRM_ERROR("mismatch in " #name " " \
12268 "(expected 0x%08x, found 0x%08x)\n", \
12269 current_config->name, \
12270 pipe_config->name); \
12271 return false; \
12272 }
12273
12274 #define PIPE_CONF_CHECK_I(name) \
12275 if (current_config->name != pipe_config->name) { \
12276 DRM_ERROR("mismatch in " #name " " \
12277 "(expected %i, found %i)\n", \
12278 current_config->name, \
12279 pipe_config->name); \
12280 return false; \
12281 }
12282
12283 /* This is required for BDW+ where there is only one set of registers for
12284 * switching between high and low RR.
12285 * This macro can be used whenever a comparison has to be made between one
12286 * hw state and multiple sw state variables.
12287 */
12288 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12289 if ((current_config->name != pipe_config->name) && \
12290 (current_config->alt_name != pipe_config->name)) { \
12291 DRM_ERROR("mismatch in " #name " " \
12292 "(expected %i or %i, found %i)\n", \
12293 current_config->name, \
12294 current_config->alt_name, \
12295 pipe_config->name); \
12296 return false; \
12297 }
12298
12299 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12300 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12301 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12302 "(expected %i, found %i)\n", \
12303 current_config->name & (mask), \
12304 pipe_config->name & (mask)); \
12305 return false; \
12306 }
12307
12308 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12309 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12310 DRM_ERROR("mismatch in " #name " " \
12311 "(expected %i, found %i)\n", \
12312 current_config->name, \
12313 pipe_config->name); \
12314 return false; \
12315 }
12316
12317 #define PIPE_CONF_QUIRK(quirk) \
12318 ((current_config->quirks | pipe_config->quirks) & (quirk))
12319
12320 PIPE_CONF_CHECK_I(cpu_transcoder);
12321
12322 PIPE_CONF_CHECK_I(has_pch_encoder);
12323 PIPE_CONF_CHECK_I(fdi_lanes);
12324 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12325 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12326 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12327 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12328 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12329
12330 PIPE_CONF_CHECK_I(has_dp_encoder);
12331
12332 if (INTEL_INFO(dev)->gen < 8) {
12333 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12334 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12335 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12336 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12337 PIPE_CONF_CHECK_I(dp_m_n.tu);
12338
12339 if (current_config->has_drrs) {
12340 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12341 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12342 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12343 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12344 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12345 }
12346 } else {
12347 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12348 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12349 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12350 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12351 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12352 }
12353
12354 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12355 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12356 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12357 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12358 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12359 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12360
12361 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12362 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12363 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12364 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12365 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12366 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12367
12368 PIPE_CONF_CHECK_I(pixel_multiplier);
12369 PIPE_CONF_CHECK_I(has_hdmi_sink);
12370 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12371 IS_VALLEYVIEW(dev))
12372 PIPE_CONF_CHECK_I(limited_color_range);
12373 PIPE_CONF_CHECK_I(has_infoframe);
12374
12375 PIPE_CONF_CHECK_I(has_audio);
12376
12377 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12378 DRM_MODE_FLAG_INTERLACE);
12379
12380 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12381 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12382 DRM_MODE_FLAG_PHSYNC);
12383 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12384 DRM_MODE_FLAG_NHSYNC);
12385 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12386 DRM_MODE_FLAG_PVSYNC);
12387 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12388 DRM_MODE_FLAG_NVSYNC);
12389 }
12390
12391 PIPE_CONF_CHECK_I(pipe_src_w);
12392 PIPE_CONF_CHECK_I(pipe_src_h);
12393
12394 /*
12395 * FIXME: BIOS likes to set up a cloned config with lvds+external
12396 * screen. Since we don't yet re-compute the pipe config when moving
12397 * just the lvds port away to another pipe the sw tracking won't match.
12398 *
12399 * Proper atomic modesets with recomputed global state will fix this.
12400 * Until then just don't check gmch state for inherited modes.
12401 */
12402 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12403 PIPE_CONF_CHECK_I(gmch_pfit.control);
12404 /* pfit ratios are autocomputed by the hw on gen4+ */
12405 if (INTEL_INFO(dev)->gen < 4)
12406 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12407 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12408 }
12409
12410 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12411 if (current_config->pch_pfit.enabled) {
12412 PIPE_CONF_CHECK_I(pch_pfit.pos);
12413 PIPE_CONF_CHECK_I(pch_pfit.size);
12414 }
12415
12416 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12417
12418 /* BDW+ don't expose a synchronous way to read the state */
12419 if (IS_HASWELL(dev))
12420 PIPE_CONF_CHECK_I(ips_enabled);
12421
12422 PIPE_CONF_CHECK_I(double_wide);
12423
12424 PIPE_CONF_CHECK_X(ddi_pll_sel);
12425
12426 PIPE_CONF_CHECK_I(shared_dpll);
12427 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12428 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12429 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12430 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12431 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12432 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12433 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12434 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12435
12436 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12437 PIPE_CONF_CHECK_I(pipe_bpp);
12438
12439 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12440 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12441
12442 #undef PIPE_CONF_CHECK_X
12443 #undef PIPE_CONF_CHECK_I
12444 #undef PIPE_CONF_CHECK_I_ALT
12445 #undef PIPE_CONF_CHECK_FLAGS
12446 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12447 #undef PIPE_CONF_QUIRK
12448
12449 return true;
12450 }
12451
12452 static void check_wm_state(struct drm_device *dev)
12453 {
12454 struct drm_i915_private *dev_priv = dev->dev_private;
12455 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12456 struct intel_crtc *intel_crtc;
12457 int plane;
12458
12459 if (INTEL_INFO(dev)->gen < 9)
12460 return;
12461
12462 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12463 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12464
12465 for_each_intel_crtc(dev, intel_crtc) {
12466 struct skl_ddb_entry *hw_entry, *sw_entry;
12467 const enum pipe pipe = intel_crtc->pipe;
12468
12469 if (!intel_crtc->active)
12470 continue;
12471
12472 /* planes */
12473 for_each_plane(dev_priv, pipe, plane) {
12474 hw_entry = &hw_ddb.plane[pipe][plane];
12475 sw_entry = &sw_ddb->plane[pipe][plane];
12476
12477 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12478 continue;
12479
12480 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12481 "(expected (%u,%u), found (%u,%u))\n",
12482 pipe_name(pipe), plane + 1,
12483 sw_entry->start, sw_entry->end,
12484 hw_entry->start, hw_entry->end);
12485 }
12486
12487 /* cursor */
12488 hw_entry = &hw_ddb.cursor[pipe];
12489 sw_entry = &sw_ddb->cursor[pipe];
12490
12491 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12492 continue;
12493
12494 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12495 "(expected (%u,%u), found (%u,%u))\n",
12496 pipe_name(pipe),
12497 sw_entry->start, sw_entry->end,
12498 hw_entry->start, hw_entry->end);
12499 }
12500 }
12501
12502 static void
12503 check_connector_state(struct drm_device *dev)
12504 {
12505 struct intel_connector *connector;
12506
12507 for_each_intel_connector(dev, connector) {
12508 /* This also checks the encoder/connector hw state with the
12509 * ->get_hw_state callbacks. */
12510 intel_connector_check_state(connector);
12511
12512 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12513 "connector's staged encoder doesn't match current encoder\n");
12514 }
12515 }
12516
12517 static void
12518 check_encoder_state(struct drm_device *dev)
12519 {
12520 struct intel_encoder *encoder;
12521 struct intel_connector *connector;
12522
12523 for_each_intel_encoder(dev, encoder) {
12524 bool enabled = false;
12525 bool active = false;
12526 enum pipe pipe, tracked_pipe;
12527
12528 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12529 encoder->base.base.id,
12530 encoder->base.name);
12531
12532 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12533 "encoder's stage crtc doesn't match current crtc\n");
12534 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12535 "encoder's active_connectors set, but no crtc\n");
12536
12537 for_each_intel_connector(dev, connector) {
12538 if (connector->base.encoder != &encoder->base)
12539 continue;
12540 enabled = true;
12541 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12542 active = true;
12543 }
12544 /*
12545 * for MST connectors if we unplug the connector is gone
12546 * away but the encoder is still connected to a crtc
12547 * until a modeset happens in response to the hotplug.
12548 */
12549 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12550 continue;
12551
12552 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12553 "encoder's enabled state mismatch "
12554 "(expected %i, found %i)\n",
12555 !!encoder->base.crtc, enabled);
12556 I915_STATE_WARN(active && !encoder->base.crtc,
12557 "active encoder with no crtc\n");
12558
12559 I915_STATE_WARN(encoder->connectors_active != active,
12560 "encoder's computed active state doesn't match tracked active state "
12561 "(expected %i, found %i)\n", active, encoder->connectors_active);
12562
12563 active = encoder->get_hw_state(encoder, &pipe);
12564 I915_STATE_WARN(active != encoder->connectors_active,
12565 "encoder's hw state doesn't match sw tracking "
12566 "(expected %i, found %i)\n",
12567 encoder->connectors_active, active);
12568
12569 if (!encoder->base.crtc)
12570 continue;
12571
12572 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12573 I915_STATE_WARN(active && pipe != tracked_pipe,
12574 "active encoder's pipe doesn't match"
12575 "(expected %i, found %i)\n",
12576 tracked_pipe, pipe);
12577
12578 }
12579 }
12580
12581 static void
12582 check_crtc_state(struct drm_device *dev)
12583 {
12584 struct drm_i915_private *dev_priv = dev->dev_private;
12585 struct intel_crtc *crtc;
12586 struct intel_encoder *encoder;
12587 struct intel_crtc_state pipe_config;
12588
12589 for_each_intel_crtc(dev, crtc) {
12590 bool enabled = false;
12591 bool active = false;
12592
12593 memset(&pipe_config, 0, sizeof(pipe_config));
12594
12595 DRM_DEBUG_KMS("[CRTC:%d]\n",
12596 crtc->base.base.id);
12597
12598 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12599 "active crtc, but not enabled in sw tracking\n");
12600
12601 for_each_intel_encoder(dev, encoder) {
12602 if (encoder->base.crtc != &crtc->base)
12603 continue;
12604 enabled = true;
12605 if (encoder->connectors_active)
12606 active = true;
12607 }
12608
12609 I915_STATE_WARN(active != crtc->active,
12610 "crtc's computed active state doesn't match tracked active state "
12611 "(expected %i, found %i)\n", active, crtc->active);
12612 I915_STATE_WARN(enabled != crtc->base.state->enable,
12613 "crtc's computed enabled state doesn't match tracked enabled state "
12614 "(expected %i, found %i)\n", enabled,
12615 crtc->base.state->enable);
12616
12617 active = dev_priv->display.get_pipe_config(crtc,
12618 &pipe_config);
12619
12620 /* hw state is inconsistent with the pipe quirk */
12621 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12622 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12623 active = crtc->active;
12624
12625 for_each_intel_encoder(dev, encoder) {
12626 enum pipe pipe;
12627 if (encoder->base.crtc != &crtc->base)
12628 continue;
12629 if (encoder->get_hw_state(encoder, &pipe))
12630 encoder->get_config(encoder, &pipe_config);
12631 }
12632
12633 I915_STATE_WARN(crtc->active != active,
12634 "crtc active state doesn't match with hw state "
12635 "(expected %i, found %i)\n", crtc->active, active);
12636
12637 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12638 "transitional active state does not match atomic hw state "
12639 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12640
12641 if (active &&
12642 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12643 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12644 intel_dump_pipe_config(crtc, &pipe_config,
12645 "[hw state]");
12646 intel_dump_pipe_config(crtc, crtc->config,
12647 "[sw state]");
12648 }
12649 }
12650 }
12651
12652 static void
12653 check_shared_dpll_state(struct drm_device *dev)
12654 {
12655 struct drm_i915_private *dev_priv = dev->dev_private;
12656 struct intel_crtc *crtc;
12657 struct intel_dpll_hw_state dpll_hw_state;
12658 int i;
12659
12660 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12661 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12662 int enabled_crtcs = 0, active_crtcs = 0;
12663 bool active;
12664
12665 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12666
12667 DRM_DEBUG_KMS("%s\n", pll->name);
12668
12669 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12670
12671 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12672 "more active pll users than references: %i vs %i\n",
12673 pll->active, hweight32(pll->config.crtc_mask));
12674 I915_STATE_WARN(pll->active && !pll->on,
12675 "pll in active use but not on in sw tracking\n");
12676 I915_STATE_WARN(pll->on && !pll->active,
12677 "pll in on but not on in use in sw tracking\n");
12678 I915_STATE_WARN(pll->on != active,
12679 "pll on state mismatch (expected %i, found %i)\n",
12680 pll->on, active);
12681
12682 for_each_intel_crtc(dev, crtc) {
12683 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12684 enabled_crtcs++;
12685 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12686 active_crtcs++;
12687 }
12688 I915_STATE_WARN(pll->active != active_crtcs,
12689 "pll active crtcs mismatch (expected %i, found %i)\n",
12690 pll->active, active_crtcs);
12691 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12692 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12693 hweight32(pll->config.crtc_mask), enabled_crtcs);
12694
12695 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12696 sizeof(dpll_hw_state)),
12697 "pll hw state mismatch\n");
12698 }
12699 }
12700
12701 void
12702 intel_modeset_check_state(struct drm_device *dev)
12703 {
12704 check_wm_state(dev);
12705 check_connector_state(dev);
12706 check_encoder_state(dev);
12707 check_crtc_state(dev);
12708 check_shared_dpll_state(dev);
12709 }
12710
12711 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12712 int dotclock)
12713 {
12714 /*
12715 * FDI already provided one idea for the dotclock.
12716 * Yell if the encoder disagrees.
12717 */
12718 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12719 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12720 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12721 }
12722
12723 static void update_scanline_offset(struct intel_crtc *crtc)
12724 {
12725 struct drm_device *dev = crtc->base.dev;
12726
12727 /*
12728 * The scanline counter increments at the leading edge of hsync.
12729 *
12730 * On most platforms it starts counting from vtotal-1 on the
12731 * first active line. That means the scanline counter value is
12732 * always one less than what we would expect. Ie. just after
12733 * start of vblank, which also occurs at start of hsync (on the
12734 * last active line), the scanline counter will read vblank_start-1.
12735 *
12736 * On gen2 the scanline counter starts counting from 1 instead
12737 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12738 * to keep the value positive), instead of adding one.
12739 *
12740 * On HSW+ the behaviour of the scanline counter depends on the output
12741 * type. For DP ports it behaves like most other platforms, but on HDMI
12742 * there's an extra 1 line difference. So we need to add two instead of
12743 * one to the value.
12744 */
12745 if (IS_GEN2(dev)) {
12746 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12747 int vtotal;
12748
12749 vtotal = mode->crtc_vtotal;
12750 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12751 vtotal /= 2;
12752
12753 crtc->scanline_offset = vtotal - 1;
12754 } else if (HAS_DDI(dev) &&
12755 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12756 crtc->scanline_offset = 2;
12757 } else
12758 crtc->scanline_offset = 1;
12759 }
12760
12761 static int
12762 intel_modeset_compute_config(struct drm_atomic_state *state)
12763 {
12764 struct drm_crtc *crtc;
12765 struct drm_crtc_state *crtc_state;
12766 int ret, i;
12767
12768 ret = drm_atomic_helper_check_modeset(state->dev, state);
12769 if (ret)
12770 return ret;
12771
12772 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12773 if (!crtc_state->enable &&
12774 WARN_ON(crtc_state->active))
12775 crtc_state->active = false;
12776
12777 if (!crtc_state->enable)
12778 continue;
12779
12780 ret = intel_modeset_pipe_config(crtc, state);
12781 if (ret)
12782 return ret;
12783
12784 intel_dump_pipe_config(to_intel_crtc(crtc),
12785 to_intel_crtc_state(crtc_state),
12786 "[modeset]");
12787 }
12788
12789 return drm_atomic_helper_check_planes(state->dev, state);
12790 }
12791
12792 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12793 {
12794 struct drm_device *dev = state->dev;
12795 struct drm_i915_private *dev_priv = to_i915(dev);
12796 unsigned clear_pipes = 0;
12797 struct intel_crtc *intel_crtc;
12798 struct intel_crtc_state *intel_crtc_state;
12799 struct drm_crtc *crtc;
12800 struct drm_crtc_state *crtc_state;
12801 int ret = 0;
12802 int i;
12803
12804 if (!dev_priv->display.crtc_compute_clock)
12805 return 0;
12806
12807 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12808 intel_crtc = to_intel_crtc(crtc);
12809 intel_crtc_state = to_intel_crtc_state(crtc_state);
12810
12811 if (needs_modeset(crtc_state)) {
12812 clear_pipes |= 1 << intel_crtc->pipe;
12813 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12814 }
12815 }
12816
12817 if (clear_pipes) {
12818 struct intel_shared_dpll_config *shared_dpll =
12819 intel_atomic_get_shared_dpll_state(state);
12820
12821 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12822 shared_dpll[i].crtc_mask &= ~clear_pipes;
12823 }
12824
12825 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12826 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12827 continue;
12828
12829 intel_crtc = to_intel_crtc(crtc);
12830 intel_crtc_state = to_intel_crtc_state(crtc_state);
12831
12832 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12833 intel_crtc_state);
12834 if (ret)
12835 return ret;
12836 }
12837
12838 return ret;
12839 }
12840
12841 /* Code that should eventually be part of atomic_check() */
12842 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12843 {
12844 struct drm_device *dev = state->dev;
12845 int ret;
12846
12847 /*
12848 * See if the config requires any additional preparation, e.g.
12849 * to adjust global state with pipes off. We need to do this
12850 * here so we can get the modeset_pipe updated config for the new
12851 * mode set on this crtc. For other crtcs we need to use the
12852 * adjusted_mode bits in the crtc directly.
12853 */
12854 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12855 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12856 ret = valleyview_modeset_global_pipes(state);
12857 else
12858 ret = broadwell_modeset_global_pipes(state);
12859
12860 if (ret)
12861 return ret;
12862 }
12863
12864 ret = __intel_set_mode_setup_plls(state);
12865 if (ret)
12866 return ret;
12867
12868 return 0;
12869 }
12870
12871 static int __intel_set_mode(struct drm_atomic_state *state)
12872 {
12873 struct drm_device *dev = state->dev;
12874 struct drm_i915_private *dev_priv = dev->dev_private;
12875 struct drm_crtc *crtc;
12876 struct drm_crtc_state *crtc_state;
12877 int ret = 0;
12878 int i;
12879
12880 ret = __intel_set_mode_checks(state);
12881 if (ret < 0)
12882 return ret;
12883
12884 ret = drm_atomic_helper_prepare_planes(dev, state);
12885 if (ret)
12886 return ret;
12887
12888 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12889 if (!needs_modeset(crtc_state) || !crtc->state->active)
12890 continue;
12891
12892 intel_crtc_disable_planes(crtc);
12893 dev_priv->display.crtc_disable(crtc);
12894 }
12895
12896 /* Only after disabling all output pipelines that will be changed can we
12897 * update the the output configuration. */
12898 intel_modeset_update_state(state);
12899
12900 /* The state has been swaped above, so state actually contains the
12901 * old state now. */
12902
12903 modeset_update_crtc_power_domains(state);
12904
12905 drm_atomic_helper_commit_planes(dev, state);
12906
12907 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12908 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12909 if (!needs_modeset(crtc->state) || !crtc->state->active)
12910 continue;
12911
12912 update_scanline_offset(to_intel_crtc(crtc));
12913
12914 dev_priv->display.crtc_enable(crtc);
12915 intel_crtc_enable_planes(crtc);
12916 }
12917
12918 /* FIXME: add subpixel order */
12919
12920 drm_atomic_helper_cleanup_planes(dev, state);
12921
12922 drm_atomic_state_free(state);
12923
12924 return 0;
12925 }
12926
12927 static int intel_set_mode_checked(struct drm_atomic_state *state)
12928 {
12929 struct drm_device *dev = state->dev;
12930 int ret;
12931
12932 ret = __intel_set_mode(state);
12933 if (ret == 0)
12934 intel_modeset_check_state(dev);
12935
12936 return ret;
12937 }
12938
12939 static int intel_set_mode(struct drm_atomic_state *state)
12940 {
12941 int ret;
12942
12943 ret = intel_modeset_compute_config(state);
12944 if (ret)
12945 return ret;
12946
12947 return intel_set_mode_checked(state);
12948 }
12949
12950 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12951 {
12952 struct drm_device *dev = crtc->dev;
12953 struct drm_atomic_state *state;
12954 struct intel_crtc *intel_crtc;
12955 struct intel_encoder *encoder;
12956 struct intel_connector *connector;
12957 struct drm_connector_state *connector_state;
12958 struct intel_crtc_state *crtc_state;
12959 int ret;
12960
12961 state = drm_atomic_state_alloc(dev);
12962 if (!state) {
12963 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12964 crtc->base.id);
12965 return;
12966 }
12967
12968 state->acquire_ctx = dev->mode_config.acquire_ctx;
12969
12970 /* The force restore path in the HW readout code relies on the staged
12971 * config still keeping the user requested config while the actual
12972 * state has been overwritten by the configuration read from HW. We
12973 * need to copy the staged config to the atomic state, otherwise the
12974 * mode set will just reapply the state the HW is already in. */
12975 for_each_intel_encoder(dev, encoder) {
12976 if (&encoder->new_crtc->base != crtc)
12977 continue;
12978
12979 for_each_intel_connector(dev, connector) {
12980 if (connector->new_encoder != encoder)
12981 continue;
12982
12983 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12984 if (IS_ERR(connector_state)) {
12985 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12986 connector->base.base.id,
12987 connector->base.name,
12988 PTR_ERR(connector_state));
12989 continue;
12990 }
12991
12992 connector_state->crtc = crtc;
12993 connector_state->best_encoder = &encoder->base;
12994 }
12995 }
12996
12997 for_each_intel_crtc(dev, intel_crtc) {
12998 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12999 continue;
13000
13001 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13002 if (IS_ERR(crtc_state)) {
13003 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13004 intel_crtc->base.base.id,
13005 PTR_ERR(crtc_state));
13006 continue;
13007 }
13008
13009 crtc_state->base.active = crtc_state->base.enable =
13010 intel_crtc->new_enabled;
13011
13012 if (&intel_crtc->base == crtc)
13013 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13014 }
13015
13016 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13017 crtc->primary->fb, crtc->x, crtc->y);
13018
13019 ret = intel_set_mode(state);
13020 if (ret)
13021 drm_atomic_state_free(state);
13022 }
13023
13024 #undef for_each_intel_crtc_masked
13025
13026 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13027 struct drm_mode_set *set)
13028 {
13029 int ro;
13030
13031 for (ro = 0; ro < set->num_connectors; ro++)
13032 if (set->connectors[ro] == &connector->base)
13033 return true;
13034
13035 return false;
13036 }
13037
13038 static int
13039 intel_modeset_stage_output_state(struct drm_device *dev,
13040 struct drm_mode_set *set,
13041 struct drm_atomic_state *state)
13042 {
13043 struct intel_connector *connector;
13044 struct drm_connector *drm_connector;
13045 struct drm_connector_state *connector_state;
13046 struct drm_crtc *crtc;
13047 struct drm_crtc_state *crtc_state;
13048 int i, ret;
13049
13050 /* The upper layers ensure that we either disable a crtc or have a list
13051 * of connectors. For paranoia, double-check this. */
13052 WARN_ON(!set->fb && (set->num_connectors != 0));
13053 WARN_ON(set->fb && (set->num_connectors == 0));
13054
13055 for_each_intel_connector(dev, connector) {
13056 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13057
13058 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13059 continue;
13060
13061 connector_state =
13062 drm_atomic_get_connector_state(state, &connector->base);
13063 if (IS_ERR(connector_state))
13064 return PTR_ERR(connector_state);
13065
13066 if (in_mode_set) {
13067 int pipe = to_intel_crtc(set->crtc)->pipe;
13068 connector_state->best_encoder =
13069 &intel_find_encoder(connector, pipe)->base;
13070 }
13071
13072 if (connector->base.state->crtc != set->crtc)
13073 continue;
13074
13075 /* If we disable the crtc, disable all its connectors. Also, if
13076 * the connector is on the changing crtc but not on the new
13077 * connector list, disable it. */
13078 if (!set->fb || !in_mode_set) {
13079 connector_state->best_encoder = NULL;
13080
13081 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13082 connector->base.base.id,
13083 connector->base.name);
13084 }
13085 }
13086 /* connector->new_encoder is now updated for all connectors. */
13087
13088 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13089 connector = to_intel_connector(drm_connector);
13090
13091 if (!connector_state->best_encoder) {
13092 ret = drm_atomic_set_crtc_for_connector(connector_state,
13093 NULL);
13094 if (ret)
13095 return ret;
13096
13097 continue;
13098 }
13099
13100 if (intel_connector_in_mode_set(connector, set)) {
13101 struct drm_crtc *crtc = connector->base.state->crtc;
13102
13103 /* If this connector was in a previous crtc, add it
13104 * to the state. We might need to disable it. */
13105 if (crtc) {
13106 crtc_state =
13107 drm_atomic_get_crtc_state(state, crtc);
13108 if (IS_ERR(crtc_state))
13109 return PTR_ERR(crtc_state);
13110 }
13111
13112 ret = drm_atomic_set_crtc_for_connector(connector_state,
13113 set->crtc);
13114 if (ret)
13115 return ret;
13116 }
13117
13118 /* Make sure the new CRTC will work with the encoder */
13119 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13120 connector_state->crtc)) {
13121 return -EINVAL;
13122 }
13123
13124 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13125 connector->base.base.id,
13126 connector->base.name,
13127 connector_state->crtc->base.id);
13128
13129 if (connector_state->best_encoder != &connector->encoder->base)
13130 connector->encoder =
13131 to_intel_encoder(connector_state->best_encoder);
13132 }
13133
13134 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13135 bool has_connectors;
13136
13137 ret = drm_atomic_add_affected_connectors(state, crtc);
13138 if (ret)
13139 return ret;
13140
13141 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13142 if (has_connectors != crtc_state->enable)
13143 crtc_state->enable =
13144 crtc_state->active = has_connectors;
13145 }
13146
13147 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13148 set->fb, set->x, set->y);
13149 if (ret)
13150 return ret;
13151
13152 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13153 if (IS_ERR(crtc_state))
13154 return PTR_ERR(crtc_state);
13155
13156 if (set->mode)
13157 drm_mode_copy(&crtc_state->mode, set->mode);
13158
13159 if (set->num_connectors)
13160 crtc_state->active = true;
13161
13162 return 0;
13163 }
13164
13165 static int intel_crtc_set_config(struct drm_mode_set *set)
13166 {
13167 struct drm_device *dev;
13168 struct drm_atomic_state *state = NULL;
13169 int ret;
13170
13171 BUG_ON(!set);
13172 BUG_ON(!set->crtc);
13173 BUG_ON(!set->crtc->helper_private);
13174
13175 /* Enforce sane interface api - has been abused by the fb helper. */
13176 BUG_ON(!set->mode && set->fb);
13177 BUG_ON(set->fb && set->num_connectors == 0);
13178
13179 if (set->fb) {
13180 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13181 set->crtc->base.id, set->fb->base.id,
13182 (int)set->num_connectors, set->x, set->y);
13183 } else {
13184 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13185 }
13186
13187 dev = set->crtc->dev;
13188
13189 state = drm_atomic_state_alloc(dev);
13190 if (!state)
13191 return -ENOMEM;
13192
13193 state->acquire_ctx = dev->mode_config.acquire_ctx;
13194
13195 ret = intel_modeset_stage_output_state(dev, set, state);
13196 if (ret)
13197 goto out;
13198
13199 ret = intel_modeset_compute_config(state);
13200 if (ret)
13201 goto out;
13202
13203 intel_update_pipe_size(to_intel_crtc(set->crtc));
13204
13205 ret = intel_set_mode_checked(state);
13206 if (ret) {
13207 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13208 set->crtc->base.id, ret);
13209 }
13210
13211 out:
13212 if (ret)
13213 drm_atomic_state_free(state);
13214 return ret;
13215 }
13216
13217 static const struct drm_crtc_funcs intel_crtc_funcs = {
13218 .gamma_set = intel_crtc_gamma_set,
13219 .set_config = intel_crtc_set_config,
13220 .destroy = intel_crtc_destroy,
13221 .page_flip = intel_crtc_page_flip,
13222 .atomic_duplicate_state = intel_crtc_duplicate_state,
13223 .atomic_destroy_state = intel_crtc_destroy_state,
13224 };
13225
13226 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13227 struct intel_shared_dpll *pll,
13228 struct intel_dpll_hw_state *hw_state)
13229 {
13230 uint32_t val;
13231
13232 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13233 return false;
13234
13235 val = I915_READ(PCH_DPLL(pll->id));
13236 hw_state->dpll = val;
13237 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13238 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13239
13240 return val & DPLL_VCO_ENABLE;
13241 }
13242
13243 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13244 struct intel_shared_dpll *pll)
13245 {
13246 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13247 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13248 }
13249
13250 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13251 struct intel_shared_dpll *pll)
13252 {
13253 /* PCH refclock must be enabled first */
13254 ibx_assert_pch_refclk_enabled(dev_priv);
13255
13256 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13257
13258 /* Wait for the clocks to stabilize. */
13259 POSTING_READ(PCH_DPLL(pll->id));
13260 udelay(150);
13261
13262 /* The pixel multiplier can only be updated once the
13263 * DPLL is enabled and the clocks are stable.
13264 *
13265 * So write it again.
13266 */
13267 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13268 POSTING_READ(PCH_DPLL(pll->id));
13269 udelay(200);
13270 }
13271
13272 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13273 struct intel_shared_dpll *pll)
13274 {
13275 struct drm_device *dev = dev_priv->dev;
13276 struct intel_crtc *crtc;
13277
13278 /* Make sure no transcoder isn't still depending on us. */
13279 for_each_intel_crtc(dev, crtc) {
13280 if (intel_crtc_to_shared_dpll(crtc) == pll)
13281 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13282 }
13283
13284 I915_WRITE(PCH_DPLL(pll->id), 0);
13285 POSTING_READ(PCH_DPLL(pll->id));
13286 udelay(200);
13287 }
13288
13289 static char *ibx_pch_dpll_names[] = {
13290 "PCH DPLL A",
13291 "PCH DPLL B",
13292 };
13293
13294 static void ibx_pch_dpll_init(struct drm_device *dev)
13295 {
13296 struct drm_i915_private *dev_priv = dev->dev_private;
13297 int i;
13298
13299 dev_priv->num_shared_dpll = 2;
13300
13301 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13302 dev_priv->shared_dplls[i].id = i;
13303 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13304 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13305 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13306 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13307 dev_priv->shared_dplls[i].get_hw_state =
13308 ibx_pch_dpll_get_hw_state;
13309 }
13310 }
13311
13312 static void intel_shared_dpll_init(struct drm_device *dev)
13313 {
13314 struct drm_i915_private *dev_priv = dev->dev_private;
13315
13316 intel_update_cdclk(dev);
13317
13318 if (HAS_DDI(dev))
13319 intel_ddi_pll_init(dev);
13320 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13321 ibx_pch_dpll_init(dev);
13322 else
13323 dev_priv->num_shared_dpll = 0;
13324
13325 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13326 }
13327
13328 /**
13329 * intel_wm_need_update - Check whether watermarks need updating
13330 * @plane: drm plane
13331 * @state: new plane state
13332 *
13333 * Check current plane state versus the new one to determine whether
13334 * watermarks need to be recalculated.
13335 *
13336 * Returns true or false.
13337 */
13338 bool intel_wm_need_update(struct drm_plane *plane,
13339 struct drm_plane_state *state)
13340 {
13341 /* Update watermarks on tiling changes. */
13342 if (!plane->state->fb || !state->fb ||
13343 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13344 plane->state->rotation != state->rotation)
13345 return true;
13346
13347 return false;
13348 }
13349
13350 /**
13351 * intel_prepare_plane_fb - Prepare fb for usage on plane
13352 * @plane: drm plane to prepare for
13353 * @fb: framebuffer to prepare for presentation
13354 *
13355 * Prepares a framebuffer for usage on a display plane. Generally this
13356 * involves pinning the underlying object and updating the frontbuffer tracking
13357 * bits. Some older platforms need special physical address handling for
13358 * cursor planes.
13359 *
13360 * Returns 0 on success, negative error code on failure.
13361 */
13362 int
13363 intel_prepare_plane_fb(struct drm_plane *plane,
13364 struct drm_framebuffer *fb,
13365 const struct drm_plane_state *new_state)
13366 {
13367 struct drm_device *dev = plane->dev;
13368 struct intel_plane *intel_plane = to_intel_plane(plane);
13369 enum pipe pipe = intel_plane->pipe;
13370 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13371 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13372 unsigned frontbuffer_bits = 0;
13373 int ret = 0;
13374
13375 if (!obj)
13376 return 0;
13377
13378 switch (plane->type) {
13379 case DRM_PLANE_TYPE_PRIMARY:
13380 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13381 break;
13382 case DRM_PLANE_TYPE_CURSOR:
13383 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13384 break;
13385 case DRM_PLANE_TYPE_OVERLAY:
13386 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13387 break;
13388 }
13389
13390 mutex_lock(&dev->struct_mutex);
13391
13392 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13393 INTEL_INFO(dev)->cursor_needs_physical) {
13394 int align = IS_I830(dev) ? 16 * 1024 : 256;
13395 ret = i915_gem_object_attach_phys(obj, align);
13396 if (ret)
13397 DRM_DEBUG_KMS("failed to attach phys object\n");
13398 } else {
13399 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13400 }
13401
13402 if (ret == 0)
13403 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13404
13405 mutex_unlock(&dev->struct_mutex);
13406
13407 return ret;
13408 }
13409
13410 /**
13411 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13412 * @plane: drm plane to clean up for
13413 * @fb: old framebuffer that was on plane
13414 *
13415 * Cleans up a framebuffer that has just been removed from a plane.
13416 */
13417 void
13418 intel_cleanup_plane_fb(struct drm_plane *plane,
13419 struct drm_framebuffer *fb,
13420 const struct drm_plane_state *old_state)
13421 {
13422 struct drm_device *dev = plane->dev;
13423 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13424
13425 if (WARN_ON(!obj))
13426 return;
13427
13428 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13429 !INTEL_INFO(dev)->cursor_needs_physical) {
13430 mutex_lock(&dev->struct_mutex);
13431 intel_unpin_fb_obj(fb, old_state);
13432 mutex_unlock(&dev->struct_mutex);
13433 }
13434 }
13435
13436 int
13437 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13438 {
13439 int max_scale;
13440 struct drm_device *dev;
13441 struct drm_i915_private *dev_priv;
13442 int crtc_clock, cdclk;
13443
13444 if (!intel_crtc || !crtc_state)
13445 return DRM_PLANE_HELPER_NO_SCALING;
13446
13447 dev = intel_crtc->base.dev;
13448 dev_priv = dev->dev_private;
13449 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13450 cdclk = dev_priv->display.get_display_clock_speed(dev);
13451
13452 if (!crtc_clock || !cdclk)
13453 return DRM_PLANE_HELPER_NO_SCALING;
13454
13455 /*
13456 * skl max scale is lower of:
13457 * close to 3 but not 3, -1 is for that purpose
13458 * or
13459 * cdclk/crtc_clock
13460 */
13461 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13462
13463 return max_scale;
13464 }
13465
13466 static int
13467 intel_check_primary_plane(struct drm_plane *plane,
13468 struct intel_plane_state *state)
13469 {
13470 struct drm_device *dev = plane->dev;
13471 struct drm_i915_private *dev_priv = dev->dev_private;
13472 struct drm_crtc *crtc = state->base.crtc;
13473 struct intel_crtc *intel_crtc;
13474 struct intel_crtc_state *crtc_state;
13475 struct drm_framebuffer *fb = state->base.fb;
13476 struct drm_rect *dest = &state->dst;
13477 struct drm_rect *src = &state->src;
13478 const struct drm_rect *clip = &state->clip;
13479 bool can_position = false;
13480 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13481 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13482 int ret;
13483
13484 crtc = crtc ? crtc : plane->crtc;
13485 intel_crtc = to_intel_crtc(crtc);
13486 crtc_state = state->base.state ?
13487 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13488
13489 if (INTEL_INFO(dev)->gen >= 9) {
13490 /* use scaler when colorkey is not required */
13491 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13492 min_scale = 1;
13493 max_scale = skl_max_scale(intel_crtc, crtc_state);
13494 }
13495 can_position = true;
13496 }
13497
13498 ret = drm_plane_helper_check_update(plane, crtc, fb,
13499 src, dest, clip,
13500 min_scale,
13501 max_scale,
13502 can_position, true,
13503 &state->visible);
13504 if (ret)
13505 return ret;
13506
13507 if (intel_crtc->active) {
13508 struct intel_plane_state *old_state =
13509 to_intel_plane_state(plane->state);
13510
13511 intel_crtc->atomic.wait_for_flips = true;
13512
13513 /*
13514 * FBC does not work on some platforms for rotated
13515 * planes, so disable it when rotation is not 0 and
13516 * update it when rotation is set back to 0.
13517 *
13518 * FIXME: This is redundant with the fbc update done in
13519 * the primary plane enable function except that that
13520 * one is done too late. We eventually need to unify
13521 * this.
13522 */
13523 if (state->visible &&
13524 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13525 dev_priv->fbc.crtc == intel_crtc &&
13526 state->base.rotation != BIT(DRM_ROTATE_0)) {
13527 intel_crtc->atomic.disable_fbc = true;
13528 }
13529
13530 if (state->visible && !old_state->visible) {
13531 /*
13532 * BDW signals flip done immediately if the plane
13533 * is disabled, even if the plane enable is already
13534 * armed to occur at the next vblank :(
13535 */
13536 if (IS_BROADWELL(dev))
13537 intel_crtc->atomic.wait_vblank = true;
13538
13539 if (crtc_state && !needs_modeset(&crtc_state->base))
13540 intel_crtc->atomic.post_enable_primary = true;
13541 }
13542
13543 if (!state->visible && old_state->visible &&
13544 crtc_state && !needs_modeset(&crtc_state->base))
13545 intel_crtc->atomic.pre_disable_primary = true;
13546
13547 intel_crtc->atomic.fb_bits |=
13548 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13549
13550 intel_crtc->atomic.update_fbc = true;
13551
13552 if (intel_wm_need_update(plane, &state->base))
13553 intel_crtc->atomic.update_wm = true;
13554 }
13555
13556 if (INTEL_INFO(dev)->gen >= 9) {
13557 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13558 to_intel_plane(plane), state, 0);
13559 if (ret)
13560 return ret;
13561 }
13562
13563 return 0;
13564 }
13565
13566 static void
13567 intel_commit_primary_plane(struct drm_plane *plane,
13568 struct intel_plane_state *state)
13569 {
13570 struct drm_crtc *crtc = state->base.crtc;
13571 struct drm_framebuffer *fb = state->base.fb;
13572 struct drm_device *dev = plane->dev;
13573 struct drm_i915_private *dev_priv = dev->dev_private;
13574 struct intel_crtc *intel_crtc;
13575 struct drm_rect *src = &state->src;
13576
13577 crtc = crtc ? crtc : plane->crtc;
13578 intel_crtc = to_intel_crtc(crtc);
13579
13580 plane->fb = fb;
13581 crtc->x = src->x1 >> 16;
13582 crtc->y = src->y1 >> 16;
13583
13584 if (intel_crtc->active) {
13585 if (state->visible)
13586 /* FIXME: kill this fastboot hack */
13587 intel_update_pipe_size(intel_crtc);
13588
13589 dev_priv->display.update_primary_plane(crtc, plane->fb,
13590 crtc->x, crtc->y);
13591 }
13592 }
13593
13594 static void
13595 intel_disable_primary_plane(struct drm_plane *plane,
13596 struct drm_crtc *crtc,
13597 bool force)
13598 {
13599 struct drm_device *dev = plane->dev;
13600 struct drm_i915_private *dev_priv = dev->dev_private;
13601
13602 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13603 }
13604
13605 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13606 {
13607 struct drm_device *dev = crtc->dev;
13608 struct drm_i915_private *dev_priv = dev->dev_private;
13609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13610 struct intel_plane *intel_plane;
13611 struct drm_plane *p;
13612 unsigned fb_bits = 0;
13613
13614 /* Track fb's for any planes being disabled */
13615 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13616 intel_plane = to_intel_plane(p);
13617
13618 if (intel_crtc->atomic.disabled_planes &
13619 (1 << drm_plane_index(p))) {
13620 switch (p->type) {
13621 case DRM_PLANE_TYPE_PRIMARY:
13622 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13623 break;
13624 case DRM_PLANE_TYPE_CURSOR:
13625 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13626 break;
13627 case DRM_PLANE_TYPE_OVERLAY:
13628 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13629 break;
13630 }
13631
13632 mutex_lock(&dev->struct_mutex);
13633 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13634 mutex_unlock(&dev->struct_mutex);
13635 }
13636 }
13637
13638 if (intel_crtc->atomic.wait_for_flips)
13639 intel_crtc_wait_for_pending_flips(crtc);
13640
13641 if (intel_crtc->atomic.disable_fbc)
13642 intel_fbc_disable(dev);
13643
13644 if (intel_crtc->atomic.pre_disable_primary)
13645 intel_pre_disable_primary(crtc);
13646
13647 if (intel_crtc->atomic.update_wm)
13648 intel_update_watermarks(crtc);
13649
13650 intel_runtime_pm_get(dev_priv);
13651
13652 /* Perform vblank evasion around commit operation */
13653 if (intel_crtc->active)
13654 intel_crtc->atomic.evade =
13655 intel_pipe_update_start(intel_crtc,
13656 &intel_crtc->atomic.start_vbl_count);
13657 }
13658
13659 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13660 {
13661 struct drm_device *dev = crtc->dev;
13662 struct drm_i915_private *dev_priv = dev->dev_private;
13663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13664 struct drm_plane *p;
13665
13666 if (intel_crtc->atomic.evade)
13667 intel_pipe_update_end(intel_crtc,
13668 intel_crtc->atomic.start_vbl_count);
13669
13670 intel_runtime_pm_put(dev_priv);
13671
13672 if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
13673 intel_wait_for_vblank(dev, intel_crtc->pipe);
13674
13675 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13676
13677 if (intel_crtc->atomic.update_fbc) {
13678 mutex_lock(&dev->struct_mutex);
13679 intel_fbc_update(dev);
13680 mutex_unlock(&dev->struct_mutex);
13681 }
13682
13683 if (intel_crtc->atomic.post_enable_primary)
13684 intel_post_enable_primary(crtc);
13685
13686 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13687 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13688 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13689 false, false);
13690
13691 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13692 }
13693
13694 /**
13695 * intel_plane_destroy - destroy a plane
13696 * @plane: plane to destroy
13697 *
13698 * Common destruction function for all types of planes (primary, cursor,
13699 * sprite).
13700 */
13701 void intel_plane_destroy(struct drm_plane *plane)
13702 {
13703 struct intel_plane *intel_plane = to_intel_plane(plane);
13704 drm_plane_cleanup(plane);
13705 kfree(intel_plane);
13706 }
13707
13708 const struct drm_plane_funcs intel_plane_funcs = {
13709 .update_plane = drm_atomic_helper_update_plane,
13710 .disable_plane = drm_atomic_helper_disable_plane,
13711 .destroy = intel_plane_destroy,
13712 .set_property = drm_atomic_helper_plane_set_property,
13713 .atomic_get_property = intel_plane_atomic_get_property,
13714 .atomic_set_property = intel_plane_atomic_set_property,
13715 .atomic_duplicate_state = intel_plane_duplicate_state,
13716 .atomic_destroy_state = intel_plane_destroy_state,
13717
13718 };
13719
13720 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13721 int pipe)
13722 {
13723 struct intel_plane *primary;
13724 struct intel_plane_state *state;
13725 const uint32_t *intel_primary_formats;
13726 int num_formats;
13727
13728 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13729 if (primary == NULL)
13730 return NULL;
13731
13732 state = intel_create_plane_state(&primary->base);
13733 if (!state) {
13734 kfree(primary);
13735 return NULL;
13736 }
13737 primary->base.state = &state->base;
13738
13739 primary->can_scale = false;
13740 primary->max_downscale = 1;
13741 if (INTEL_INFO(dev)->gen >= 9) {
13742 primary->can_scale = true;
13743 state->scaler_id = -1;
13744 }
13745 primary->pipe = pipe;
13746 primary->plane = pipe;
13747 primary->check_plane = intel_check_primary_plane;
13748 primary->commit_plane = intel_commit_primary_plane;
13749 primary->disable_plane = intel_disable_primary_plane;
13750 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13751 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13752 primary->plane = !pipe;
13753
13754 if (INTEL_INFO(dev)->gen >= 9) {
13755 intel_primary_formats = skl_primary_formats;
13756 num_formats = ARRAY_SIZE(skl_primary_formats);
13757 } else if (INTEL_INFO(dev)->gen >= 4) {
13758 intel_primary_formats = i965_primary_formats;
13759 num_formats = ARRAY_SIZE(i965_primary_formats);
13760 } else {
13761 intel_primary_formats = i8xx_primary_formats;
13762 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13763 }
13764
13765 drm_universal_plane_init(dev, &primary->base, 0,
13766 &intel_plane_funcs,
13767 intel_primary_formats, num_formats,
13768 DRM_PLANE_TYPE_PRIMARY);
13769
13770 if (INTEL_INFO(dev)->gen >= 4)
13771 intel_create_rotation_property(dev, primary);
13772
13773 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13774
13775 return &primary->base;
13776 }
13777
13778 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13779 {
13780 if (!dev->mode_config.rotation_property) {
13781 unsigned long flags = BIT(DRM_ROTATE_0) |
13782 BIT(DRM_ROTATE_180);
13783
13784 if (INTEL_INFO(dev)->gen >= 9)
13785 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13786
13787 dev->mode_config.rotation_property =
13788 drm_mode_create_rotation_property(dev, flags);
13789 }
13790 if (dev->mode_config.rotation_property)
13791 drm_object_attach_property(&plane->base.base,
13792 dev->mode_config.rotation_property,
13793 plane->base.state->rotation);
13794 }
13795
13796 static int
13797 intel_check_cursor_plane(struct drm_plane *plane,
13798 struct intel_plane_state *state)
13799 {
13800 struct drm_crtc *crtc = state->base.crtc;
13801 struct drm_device *dev = plane->dev;
13802 struct drm_framebuffer *fb = state->base.fb;
13803 struct drm_rect *dest = &state->dst;
13804 struct drm_rect *src = &state->src;
13805 const struct drm_rect *clip = &state->clip;
13806 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13807 struct intel_crtc *intel_crtc;
13808 unsigned stride;
13809 int ret;
13810
13811 crtc = crtc ? crtc : plane->crtc;
13812 intel_crtc = to_intel_crtc(crtc);
13813
13814 ret = drm_plane_helper_check_update(plane, crtc, fb,
13815 src, dest, clip,
13816 DRM_PLANE_HELPER_NO_SCALING,
13817 DRM_PLANE_HELPER_NO_SCALING,
13818 true, true, &state->visible);
13819 if (ret)
13820 return ret;
13821
13822
13823 /* if we want to turn off the cursor ignore width and height */
13824 if (!obj)
13825 goto finish;
13826
13827 /* Check for which cursor types we support */
13828 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13829 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13830 state->base.crtc_w, state->base.crtc_h);
13831 return -EINVAL;
13832 }
13833
13834 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13835 if (obj->base.size < stride * state->base.crtc_h) {
13836 DRM_DEBUG_KMS("buffer is too small\n");
13837 return -ENOMEM;
13838 }
13839
13840 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13841 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13842 ret = -EINVAL;
13843 }
13844
13845 finish:
13846 if (intel_crtc->active) {
13847 if (plane->state->crtc_w != state->base.crtc_w)
13848 intel_crtc->atomic.update_wm = true;
13849
13850 intel_crtc->atomic.fb_bits |=
13851 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13852 }
13853
13854 return ret;
13855 }
13856
13857 static void
13858 intel_disable_cursor_plane(struct drm_plane *plane,
13859 struct drm_crtc *crtc,
13860 bool force)
13861 {
13862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13863
13864 if (!force) {
13865 plane->fb = NULL;
13866 intel_crtc->cursor_bo = NULL;
13867 intel_crtc->cursor_addr = 0;
13868 }
13869
13870 intel_crtc_update_cursor(crtc, false);
13871 }
13872
13873 static void
13874 intel_commit_cursor_plane(struct drm_plane *plane,
13875 struct intel_plane_state *state)
13876 {
13877 struct drm_crtc *crtc = state->base.crtc;
13878 struct drm_device *dev = plane->dev;
13879 struct intel_crtc *intel_crtc;
13880 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13881 uint32_t addr;
13882
13883 crtc = crtc ? crtc : plane->crtc;
13884 intel_crtc = to_intel_crtc(crtc);
13885
13886 plane->fb = state->base.fb;
13887 crtc->cursor_x = state->base.crtc_x;
13888 crtc->cursor_y = state->base.crtc_y;
13889
13890 if (intel_crtc->cursor_bo == obj)
13891 goto update;
13892
13893 if (!obj)
13894 addr = 0;
13895 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13896 addr = i915_gem_obj_ggtt_offset(obj);
13897 else
13898 addr = obj->phys_handle->busaddr;
13899
13900 intel_crtc->cursor_addr = addr;
13901 intel_crtc->cursor_bo = obj;
13902 update:
13903
13904 if (intel_crtc->active)
13905 intel_crtc_update_cursor(crtc, state->visible);
13906 }
13907
13908 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13909 int pipe)
13910 {
13911 struct intel_plane *cursor;
13912 struct intel_plane_state *state;
13913
13914 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13915 if (cursor == NULL)
13916 return NULL;
13917
13918 state = intel_create_plane_state(&cursor->base);
13919 if (!state) {
13920 kfree(cursor);
13921 return NULL;
13922 }
13923 cursor->base.state = &state->base;
13924
13925 cursor->can_scale = false;
13926 cursor->max_downscale = 1;
13927 cursor->pipe = pipe;
13928 cursor->plane = pipe;
13929 cursor->check_plane = intel_check_cursor_plane;
13930 cursor->commit_plane = intel_commit_cursor_plane;
13931 cursor->disable_plane = intel_disable_cursor_plane;
13932
13933 drm_universal_plane_init(dev, &cursor->base, 0,
13934 &intel_plane_funcs,
13935 intel_cursor_formats,
13936 ARRAY_SIZE(intel_cursor_formats),
13937 DRM_PLANE_TYPE_CURSOR);
13938
13939 if (INTEL_INFO(dev)->gen >= 4) {
13940 if (!dev->mode_config.rotation_property)
13941 dev->mode_config.rotation_property =
13942 drm_mode_create_rotation_property(dev,
13943 BIT(DRM_ROTATE_0) |
13944 BIT(DRM_ROTATE_180));
13945 if (dev->mode_config.rotation_property)
13946 drm_object_attach_property(&cursor->base.base,
13947 dev->mode_config.rotation_property,
13948 state->base.rotation);
13949 }
13950
13951 if (INTEL_INFO(dev)->gen >=9)
13952 state->scaler_id = -1;
13953
13954 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13955
13956 return &cursor->base;
13957 }
13958
13959 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13960 struct intel_crtc_state *crtc_state)
13961 {
13962 int i;
13963 struct intel_scaler *intel_scaler;
13964 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13965
13966 for (i = 0; i < intel_crtc->num_scalers; i++) {
13967 intel_scaler = &scaler_state->scalers[i];
13968 intel_scaler->in_use = 0;
13969 intel_scaler->id = i;
13970
13971 intel_scaler->mode = PS_SCALER_MODE_DYN;
13972 }
13973
13974 scaler_state->scaler_id = -1;
13975 }
13976
13977 static void intel_crtc_init(struct drm_device *dev, int pipe)
13978 {
13979 struct drm_i915_private *dev_priv = dev->dev_private;
13980 struct intel_crtc *intel_crtc;
13981 struct intel_crtc_state *crtc_state = NULL;
13982 struct drm_plane *primary = NULL;
13983 struct drm_plane *cursor = NULL;
13984 int i, ret;
13985
13986 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13987 if (intel_crtc == NULL)
13988 return;
13989
13990 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13991 if (!crtc_state)
13992 goto fail;
13993 intel_crtc->config = crtc_state;
13994 intel_crtc->base.state = &crtc_state->base;
13995 crtc_state->base.crtc = &intel_crtc->base;
13996
13997 /* initialize shared scalers */
13998 if (INTEL_INFO(dev)->gen >= 9) {
13999 if (pipe == PIPE_C)
14000 intel_crtc->num_scalers = 1;
14001 else
14002 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14003
14004 skl_init_scalers(dev, intel_crtc, crtc_state);
14005 }
14006
14007 primary = intel_primary_plane_create(dev, pipe);
14008 if (!primary)
14009 goto fail;
14010
14011 cursor = intel_cursor_plane_create(dev, pipe);
14012 if (!cursor)
14013 goto fail;
14014
14015 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14016 cursor, &intel_crtc_funcs);
14017 if (ret)
14018 goto fail;
14019
14020 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14021 for (i = 0; i < 256; i++) {
14022 intel_crtc->lut_r[i] = i;
14023 intel_crtc->lut_g[i] = i;
14024 intel_crtc->lut_b[i] = i;
14025 }
14026
14027 /*
14028 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14029 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14030 */
14031 intel_crtc->pipe = pipe;
14032 intel_crtc->plane = pipe;
14033 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14034 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14035 intel_crtc->plane = !pipe;
14036 }
14037
14038 intel_crtc->cursor_base = ~0;
14039 intel_crtc->cursor_cntl = ~0;
14040 intel_crtc->cursor_size = ~0;
14041
14042 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14043 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14044 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14045 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14046
14047 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14048
14049 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14050 return;
14051
14052 fail:
14053 if (primary)
14054 drm_plane_cleanup(primary);
14055 if (cursor)
14056 drm_plane_cleanup(cursor);
14057 kfree(crtc_state);
14058 kfree(intel_crtc);
14059 }
14060
14061 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14062 {
14063 struct drm_encoder *encoder = connector->base.encoder;
14064 struct drm_device *dev = connector->base.dev;
14065
14066 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14067
14068 if (!encoder || WARN_ON(!encoder->crtc))
14069 return INVALID_PIPE;
14070
14071 return to_intel_crtc(encoder->crtc)->pipe;
14072 }
14073
14074 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14075 struct drm_file *file)
14076 {
14077 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14078 struct drm_crtc *drmmode_crtc;
14079 struct intel_crtc *crtc;
14080
14081 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14082
14083 if (!drmmode_crtc) {
14084 DRM_ERROR("no such CRTC id\n");
14085 return -ENOENT;
14086 }
14087
14088 crtc = to_intel_crtc(drmmode_crtc);
14089 pipe_from_crtc_id->pipe = crtc->pipe;
14090
14091 return 0;
14092 }
14093
14094 static int intel_encoder_clones(struct intel_encoder *encoder)
14095 {
14096 struct drm_device *dev = encoder->base.dev;
14097 struct intel_encoder *source_encoder;
14098 int index_mask = 0;
14099 int entry = 0;
14100
14101 for_each_intel_encoder(dev, source_encoder) {
14102 if (encoders_cloneable(encoder, source_encoder))
14103 index_mask |= (1 << entry);
14104
14105 entry++;
14106 }
14107
14108 return index_mask;
14109 }
14110
14111 static bool has_edp_a(struct drm_device *dev)
14112 {
14113 struct drm_i915_private *dev_priv = dev->dev_private;
14114
14115 if (!IS_MOBILE(dev))
14116 return false;
14117
14118 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14119 return false;
14120
14121 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14122 return false;
14123
14124 return true;
14125 }
14126
14127 static bool intel_crt_present(struct drm_device *dev)
14128 {
14129 struct drm_i915_private *dev_priv = dev->dev_private;
14130
14131 if (INTEL_INFO(dev)->gen >= 9)
14132 return false;
14133
14134 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14135 return false;
14136
14137 if (IS_CHERRYVIEW(dev))
14138 return false;
14139
14140 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14141 return false;
14142
14143 return true;
14144 }
14145
14146 static void intel_setup_outputs(struct drm_device *dev)
14147 {
14148 struct drm_i915_private *dev_priv = dev->dev_private;
14149 struct intel_encoder *encoder;
14150 bool dpd_is_edp = false;
14151
14152 intel_lvds_init(dev);
14153
14154 if (intel_crt_present(dev))
14155 intel_crt_init(dev);
14156
14157 if (IS_BROXTON(dev)) {
14158 /*
14159 * FIXME: Broxton doesn't support port detection via the
14160 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14161 * detect the ports.
14162 */
14163 intel_ddi_init(dev, PORT_A);
14164 intel_ddi_init(dev, PORT_B);
14165 intel_ddi_init(dev, PORT_C);
14166 } else if (HAS_DDI(dev)) {
14167 int found;
14168
14169 /*
14170 * Haswell uses DDI functions to detect digital outputs.
14171 * On SKL pre-D0 the strap isn't connected, so we assume
14172 * it's there.
14173 */
14174 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14175 /* WaIgnoreDDIAStrap: skl */
14176 if (found ||
14177 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14178 intel_ddi_init(dev, PORT_A);
14179
14180 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14181 * register */
14182 found = I915_READ(SFUSE_STRAP);
14183
14184 if (found & SFUSE_STRAP_DDIB_DETECTED)
14185 intel_ddi_init(dev, PORT_B);
14186 if (found & SFUSE_STRAP_DDIC_DETECTED)
14187 intel_ddi_init(dev, PORT_C);
14188 if (found & SFUSE_STRAP_DDID_DETECTED)
14189 intel_ddi_init(dev, PORT_D);
14190 } else if (HAS_PCH_SPLIT(dev)) {
14191 int found;
14192 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14193
14194 if (has_edp_a(dev))
14195 intel_dp_init(dev, DP_A, PORT_A);
14196
14197 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14198 /* PCH SDVOB multiplex with HDMIB */
14199 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14200 if (!found)
14201 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14202 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14203 intel_dp_init(dev, PCH_DP_B, PORT_B);
14204 }
14205
14206 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14207 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14208
14209 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14210 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14211
14212 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14213 intel_dp_init(dev, PCH_DP_C, PORT_C);
14214
14215 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14216 intel_dp_init(dev, PCH_DP_D, PORT_D);
14217 } else if (IS_VALLEYVIEW(dev)) {
14218 /*
14219 * The DP_DETECTED bit is the latched state of the DDC
14220 * SDA pin at boot. However since eDP doesn't require DDC
14221 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14222 * eDP ports may have been muxed to an alternate function.
14223 * Thus we can't rely on the DP_DETECTED bit alone to detect
14224 * eDP ports. Consult the VBT as well as DP_DETECTED to
14225 * detect eDP ports.
14226 */
14227 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14228 !intel_dp_is_edp(dev, PORT_B))
14229 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14230 PORT_B);
14231 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14232 intel_dp_is_edp(dev, PORT_B))
14233 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14234
14235 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14236 !intel_dp_is_edp(dev, PORT_C))
14237 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14238 PORT_C);
14239 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14240 intel_dp_is_edp(dev, PORT_C))
14241 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14242
14243 if (IS_CHERRYVIEW(dev)) {
14244 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14245 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14246 PORT_D);
14247 /* eDP not supported on port D, so don't check VBT */
14248 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14249 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14250 }
14251
14252 intel_dsi_init(dev);
14253 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14254 bool found = false;
14255
14256 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14257 DRM_DEBUG_KMS("probing SDVOB\n");
14258 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14259 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14260 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14261 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14262 }
14263
14264 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14265 intel_dp_init(dev, DP_B, PORT_B);
14266 }
14267
14268 /* Before G4X SDVOC doesn't have its own detect register */
14269
14270 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14271 DRM_DEBUG_KMS("probing SDVOC\n");
14272 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14273 }
14274
14275 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14276
14277 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14278 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14279 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14280 }
14281 if (SUPPORTS_INTEGRATED_DP(dev))
14282 intel_dp_init(dev, DP_C, PORT_C);
14283 }
14284
14285 if (SUPPORTS_INTEGRATED_DP(dev) &&
14286 (I915_READ(DP_D) & DP_DETECTED))
14287 intel_dp_init(dev, DP_D, PORT_D);
14288 } else if (IS_GEN2(dev))
14289 intel_dvo_init(dev);
14290
14291 if (SUPPORTS_TV(dev))
14292 intel_tv_init(dev);
14293
14294 intel_psr_init(dev);
14295
14296 for_each_intel_encoder(dev, encoder) {
14297 encoder->base.possible_crtcs = encoder->crtc_mask;
14298 encoder->base.possible_clones =
14299 intel_encoder_clones(encoder);
14300 }
14301
14302 intel_init_pch_refclk(dev);
14303
14304 drm_helper_move_panel_connectors_to_head(dev);
14305 }
14306
14307 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14308 {
14309 struct drm_device *dev = fb->dev;
14310 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14311
14312 drm_framebuffer_cleanup(fb);
14313 mutex_lock(&dev->struct_mutex);
14314 WARN_ON(!intel_fb->obj->framebuffer_references--);
14315 drm_gem_object_unreference(&intel_fb->obj->base);
14316 mutex_unlock(&dev->struct_mutex);
14317 kfree(intel_fb);
14318 }
14319
14320 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14321 struct drm_file *file,
14322 unsigned int *handle)
14323 {
14324 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14325 struct drm_i915_gem_object *obj = intel_fb->obj;
14326
14327 return drm_gem_handle_create(file, &obj->base, handle);
14328 }
14329
14330 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14331 .destroy = intel_user_framebuffer_destroy,
14332 .create_handle = intel_user_framebuffer_create_handle,
14333 };
14334
14335 static
14336 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14337 uint32_t pixel_format)
14338 {
14339 u32 gen = INTEL_INFO(dev)->gen;
14340
14341 if (gen >= 9) {
14342 /* "The stride in bytes must not exceed the of the size of 8K
14343 * pixels and 32K bytes."
14344 */
14345 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14346 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14347 return 32*1024;
14348 } else if (gen >= 4) {
14349 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14350 return 16*1024;
14351 else
14352 return 32*1024;
14353 } else if (gen >= 3) {
14354 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14355 return 8*1024;
14356 else
14357 return 16*1024;
14358 } else {
14359 /* XXX DSPC is limited to 4k tiled */
14360 return 8*1024;
14361 }
14362 }
14363
14364 static int intel_framebuffer_init(struct drm_device *dev,
14365 struct intel_framebuffer *intel_fb,
14366 struct drm_mode_fb_cmd2 *mode_cmd,
14367 struct drm_i915_gem_object *obj)
14368 {
14369 unsigned int aligned_height;
14370 int ret;
14371 u32 pitch_limit, stride_alignment;
14372
14373 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14374
14375 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14376 /* Enforce that fb modifier and tiling mode match, but only for
14377 * X-tiled. This is needed for FBC. */
14378 if (!!(obj->tiling_mode == I915_TILING_X) !=
14379 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14380 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14381 return -EINVAL;
14382 }
14383 } else {
14384 if (obj->tiling_mode == I915_TILING_X)
14385 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14386 else if (obj->tiling_mode == I915_TILING_Y) {
14387 DRM_DEBUG("No Y tiling for legacy addfb\n");
14388 return -EINVAL;
14389 }
14390 }
14391
14392 /* Passed in modifier sanity checking. */
14393 switch (mode_cmd->modifier[0]) {
14394 case I915_FORMAT_MOD_Y_TILED:
14395 case I915_FORMAT_MOD_Yf_TILED:
14396 if (INTEL_INFO(dev)->gen < 9) {
14397 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14398 mode_cmd->modifier[0]);
14399 return -EINVAL;
14400 }
14401 case DRM_FORMAT_MOD_NONE:
14402 case I915_FORMAT_MOD_X_TILED:
14403 break;
14404 default:
14405 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14406 mode_cmd->modifier[0]);
14407 return -EINVAL;
14408 }
14409
14410 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14411 mode_cmd->pixel_format);
14412 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14413 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14414 mode_cmd->pitches[0], stride_alignment);
14415 return -EINVAL;
14416 }
14417
14418 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14419 mode_cmd->pixel_format);
14420 if (mode_cmd->pitches[0] > pitch_limit) {
14421 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14422 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14423 "tiled" : "linear",
14424 mode_cmd->pitches[0], pitch_limit);
14425 return -EINVAL;
14426 }
14427
14428 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14429 mode_cmd->pitches[0] != obj->stride) {
14430 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14431 mode_cmd->pitches[0], obj->stride);
14432 return -EINVAL;
14433 }
14434
14435 /* Reject formats not supported by any plane early. */
14436 switch (mode_cmd->pixel_format) {
14437 case DRM_FORMAT_C8:
14438 case DRM_FORMAT_RGB565:
14439 case DRM_FORMAT_XRGB8888:
14440 case DRM_FORMAT_ARGB8888:
14441 break;
14442 case DRM_FORMAT_XRGB1555:
14443 if (INTEL_INFO(dev)->gen > 3) {
14444 DRM_DEBUG("unsupported pixel format: %s\n",
14445 drm_get_format_name(mode_cmd->pixel_format));
14446 return -EINVAL;
14447 }
14448 break;
14449 case DRM_FORMAT_ABGR8888:
14450 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14451 DRM_DEBUG("unsupported pixel format: %s\n",
14452 drm_get_format_name(mode_cmd->pixel_format));
14453 return -EINVAL;
14454 }
14455 break;
14456 case DRM_FORMAT_XBGR8888:
14457 case DRM_FORMAT_XRGB2101010:
14458 case DRM_FORMAT_XBGR2101010:
14459 if (INTEL_INFO(dev)->gen < 4) {
14460 DRM_DEBUG("unsupported pixel format: %s\n",
14461 drm_get_format_name(mode_cmd->pixel_format));
14462 return -EINVAL;
14463 }
14464 break;
14465 case DRM_FORMAT_ABGR2101010:
14466 if (!IS_VALLEYVIEW(dev)) {
14467 DRM_DEBUG("unsupported pixel format: %s\n",
14468 drm_get_format_name(mode_cmd->pixel_format));
14469 return -EINVAL;
14470 }
14471 break;
14472 case DRM_FORMAT_YUYV:
14473 case DRM_FORMAT_UYVY:
14474 case DRM_FORMAT_YVYU:
14475 case DRM_FORMAT_VYUY:
14476 if (INTEL_INFO(dev)->gen < 5) {
14477 DRM_DEBUG("unsupported pixel format: %s\n",
14478 drm_get_format_name(mode_cmd->pixel_format));
14479 return -EINVAL;
14480 }
14481 break;
14482 default:
14483 DRM_DEBUG("unsupported pixel format: %s\n",
14484 drm_get_format_name(mode_cmd->pixel_format));
14485 return -EINVAL;
14486 }
14487
14488 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14489 if (mode_cmd->offsets[0] != 0)
14490 return -EINVAL;
14491
14492 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14493 mode_cmd->pixel_format,
14494 mode_cmd->modifier[0]);
14495 /* FIXME drm helper for size checks (especially planar formats)? */
14496 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14497 return -EINVAL;
14498
14499 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14500 intel_fb->obj = obj;
14501 intel_fb->obj->framebuffer_references++;
14502
14503 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14504 if (ret) {
14505 DRM_ERROR("framebuffer init failed %d\n", ret);
14506 return ret;
14507 }
14508
14509 return 0;
14510 }
14511
14512 static struct drm_framebuffer *
14513 intel_user_framebuffer_create(struct drm_device *dev,
14514 struct drm_file *filp,
14515 struct drm_mode_fb_cmd2 *mode_cmd)
14516 {
14517 struct drm_i915_gem_object *obj;
14518
14519 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14520 mode_cmd->handles[0]));
14521 if (&obj->base == NULL)
14522 return ERR_PTR(-ENOENT);
14523
14524 return intel_framebuffer_create(dev, mode_cmd, obj);
14525 }
14526
14527 #ifndef CONFIG_DRM_I915_FBDEV
14528 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14529 {
14530 }
14531 #endif
14532
14533 static const struct drm_mode_config_funcs intel_mode_funcs = {
14534 .fb_create = intel_user_framebuffer_create,
14535 .output_poll_changed = intel_fbdev_output_poll_changed,
14536 .atomic_check = intel_atomic_check,
14537 .atomic_commit = intel_atomic_commit,
14538 .atomic_state_alloc = intel_atomic_state_alloc,
14539 .atomic_state_clear = intel_atomic_state_clear,
14540 };
14541
14542 /* Set up chip specific display functions */
14543 static void intel_init_display(struct drm_device *dev)
14544 {
14545 struct drm_i915_private *dev_priv = dev->dev_private;
14546
14547 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14548 dev_priv->display.find_dpll = g4x_find_best_dpll;
14549 else if (IS_CHERRYVIEW(dev))
14550 dev_priv->display.find_dpll = chv_find_best_dpll;
14551 else if (IS_VALLEYVIEW(dev))
14552 dev_priv->display.find_dpll = vlv_find_best_dpll;
14553 else if (IS_PINEVIEW(dev))
14554 dev_priv->display.find_dpll = pnv_find_best_dpll;
14555 else
14556 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14557
14558 if (INTEL_INFO(dev)->gen >= 9) {
14559 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14560 dev_priv->display.get_initial_plane_config =
14561 skylake_get_initial_plane_config;
14562 dev_priv->display.crtc_compute_clock =
14563 haswell_crtc_compute_clock;
14564 dev_priv->display.crtc_enable = haswell_crtc_enable;
14565 dev_priv->display.crtc_disable = haswell_crtc_disable;
14566 dev_priv->display.update_primary_plane =
14567 skylake_update_primary_plane;
14568 } else if (HAS_DDI(dev)) {
14569 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14570 dev_priv->display.get_initial_plane_config =
14571 ironlake_get_initial_plane_config;
14572 dev_priv->display.crtc_compute_clock =
14573 haswell_crtc_compute_clock;
14574 dev_priv->display.crtc_enable = haswell_crtc_enable;
14575 dev_priv->display.crtc_disable = haswell_crtc_disable;
14576 dev_priv->display.update_primary_plane =
14577 ironlake_update_primary_plane;
14578 } else if (HAS_PCH_SPLIT(dev)) {
14579 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14580 dev_priv->display.get_initial_plane_config =
14581 ironlake_get_initial_plane_config;
14582 dev_priv->display.crtc_compute_clock =
14583 ironlake_crtc_compute_clock;
14584 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14585 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14586 dev_priv->display.update_primary_plane =
14587 ironlake_update_primary_plane;
14588 } else if (IS_VALLEYVIEW(dev)) {
14589 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14590 dev_priv->display.get_initial_plane_config =
14591 i9xx_get_initial_plane_config;
14592 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14593 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14594 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14595 dev_priv->display.update_primary_plane =
14596 i9xx_update_primary_plane;
14597 } else {
14598 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14599 dev_priv->display.get_initial_plane_config =
14600 i9xx_get_initial_plane_config;
14601 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14602 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14603 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14604 dev_priv->display.update_primary_plane =
14605 i9xx_update_primary_plane;
14606 }
14607
14608 /* Returns the core display clock speed */
14609 if (IS_SKYLAKE(dev))
14610 dev_priv->display.get_display_clock_speed =
14611 skylake_get_display_clock_speed;
14612 else if (IS_BROADWELL(dev))
14613 dev_priv->display.get_display_clock_speed =
14614 broadwell_get_display_clock_speed;
14615 else if (IS_HASWELL(dev))
14616 dev_priv->display.get_display_clock_speed =
14617 haswell_get_display_clock_speed;
14618 else if (IS_VALLEYVIEW(dev))
14619 dev_priv->display.get_display_clock_speed =
14620 valleyview_get_display_clock_speed;
14621 else if (IS_GEN5(dev))
14622 dev_priv->display.get_display_clock_speed =
14623 ilk_get_display_clock_speed;
14624 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14625 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14626 dev_priv->display.get_display_clock_speed =
14627 i945_get_display_clock_speed;
14628 else if (IS_GM45(dev))
14629 dev_priv->display.get_display_clock_speed =
14630 gm45_get_display_clock_speed;
14631 else if (IS_CRESTLINE(dev))
14632 dev_priv->display.get_display_clock_speed =
14633 i965gm_get_display_clock_speed;
14634 else if (IS_PINEVIEW(dev))
14635 dev_priv->display.get_display_clock_speed =
14636 pnv_get_display_clock_speed;
14637 else if (IS_G33(dev) || IS_G4X(dev))
14638 dev_priv->display.get_display_clock_speed =
14639 g33_get_display_clock_speed;
14640 else if (IS_I915G(dev))
14641 dev_priv->display.get_display_clock_speed =
14642 i915_get_display_clock_speed;
14643 else if (IS_I945GM(dev) || IS_845G(dev))
14644 dev_priv->display.get_display_clock_speed =
14645 i9xx_misc_get_display_clock_speed;
14646 else if (IS_PINEVIEW(dev))
14647 dev_priv->display.get_display_clock_speed =
14648 pnv_get_display_clock_speed;
14649 else if (IS_I915GM(dev))
14650 dev_priv->display.get_display_clock_speed =
14651 i915gm_get_display_clock_speed;
14652 else if (IS_I865G(dev))
14653 dev_priv->display.get_display_clock_speed =
14654 i865_get_display_clock_speed;
14655 else if (IS_I85X(dev))
14656 dev_priv->display.get_display_clock_speed =
14657 i85x_get_display_clock_speed;
14658 else { /* 830 */
14659 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14660 dev_priv->display.get_display_clock_speed =
14661 i830_get_display_clock_speed;
14662 }
14663
14664 if (IS_GEN5(dev)) {
14665 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14666 } else if (IS_GEN6(dev)) {
14667 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14668 } else if (IS_IVYBRIDGE(dev)) {
14669 /* FIXME: detect B0+ stepping and use auto training */
14670 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14671 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14672 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14673 if (IS_BROADWELL(dev))
14674 dev_priv->display.modeset_global_resources =
14675 broadwell_modeset_global_resources;
14676 } else if (IS_VALLEYVIEW(dev)) {
14677 dev_priv->display.modeset_global_resources =
14678 valleyview_modeset_global_resources;
14679 } else if (IS_BROXTON(dev)) {
14680 dev_priv->display.modeset_global_resources =
14681 broxton_modeset_global_resources;
14682 }
14683
14684 switch (INTEL_INFO(dev)->gen) {
14685 case 2:
14686 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14687 break;
14688
14689 case 3:
14690 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14691 break;
14692
14693 case 4:
14694 case 5:
14695 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14696 break;
14697
14698 case 6:
14699 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14700 break;
14701 case 7:
14702 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14703 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14704 break;
14705 case 9:
14706 /* Drop through - unsupported since execlist only. */
14707 default:
14708 /* Default just returns -ENODEV to indicate unsupported */
14709 dev_priv->display.queue_flip = intel_default_queue_flip;
14710 }
14711
14712 intel_panel_init_backlight_funcs(dev);
14713
14714 mutex_init(&dev_priv->pps_mutex);
14715 }
14716
14717 /*
14718 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14719 * resume, or other times. This quirk makes sure that's the case for
14720 * affected systems.
14721 */
14722 static void quirk_pipea_force(struct drm_device *dev)
14723 {
14724 struct drm_i915_private *dev_priv = dev->dev_private;
14725
14726 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14727 DRM_INFO("applying pipe a force quirk\n");
14728 }
14729
14730 static void quirk_pipeb_force(struct drm_device *dev)
14731 {
14732 struct drm_i915_private *dev_priv = dev->dev_private;
14733
14734 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14735 DRM_INFO("applying pipe b force quirk\n");
14736 }
14737
14738 /*
14739 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14740 */
14741 static void quirk_ssc_force_disable(struct drm_device *dev)
14742 {
14743 struct drm_i915_private *dev_priv = dev->dev_private;
14744 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14745 DRM_INFO("applying lvds SSC disable quirk\n");
14746 }
14747
14748 /*
14749 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14750 * brightness value
14751 */
14752 static void quirk_invert_brightness(struct drm_device *dev)
14753 {
14754 struct drm_i915_private *dev_priv = dev->dev_private;
14755 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14756 DRM_INFO("applying inverted panel brightness quirk\n");
14757 }
14758
14759 /* Some VBT's incorrectly indicate no backlight is present */
14760 static void quirk_backlight_present(struct drm_device *dev)
14761 {
14762 struct drm_i915_private *dev_priv = dev->dev_private;
14763 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14764 DRM_INFO("applying backlight present quirk\n");
14765 }
14766
14767 struct intel_quirk {
14768 int device;
14769 int subsystem_vendor;
14770 int subsystem_device;
14771 void (*hook)(struct drm_device *dev);
14772 };
14773
14774 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14775 struct intel_dmi_quirk {
14776 void (*hook)(struct drm_device *dev);
14777 const struct dmi_system_id (*dmi_id_list)[];
14778 };
14779
14780 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14781 {
14782 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14783 return 1;
14784 }
14785
14786 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14787 {
14788 .dmi_id_list = &(const struct dmi_system_id[]) {
14789 {
14790 .callback = intel_dmi_reverse_brightness,
14791 .ident = "NCR Corporation",
14792 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14793 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14794 },
14795 },
14796 { } /* terminating entry */
14797 },
14798 .hook = quirk_invert_brightness,
14799 },
14800 };
14801
14802 static struct intel_quirk intel_quirks[] = {
14803 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14804 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14805
14806 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14807 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14808
14809 /* 830 needs to leave pipe A & dpll A up */
14810 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14811
14812 /* 830 needs to leave pipe B & dpll B up */
14813 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14814
14815 /* Lenovo U160 cannot use SSC on LVDS */
14816 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14817
14818 /* Sony Vaio Y cannot use SSC on LVDS */
14819 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14820
14821 /* Acer Aspire 5734Z must invert backlight brightness */
14822 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14823
14824 /* Acer/eMachines G725 */
14825 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14826
14827 /* Acer/eMachines e725 */
14828 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14829
14830 /* Acer/Packard Bell NCL20 */
14831 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14832
14833 /* Acer Aspire 4736Z */
14834 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14835
14836 /* Acer Aspire 5336 */
14837 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14838
14839 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14840 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14841
14842 /* Acer C720 Chromebook (Core i3 4005U) */
14843 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14844
14845 /* Apple Macbook 2,1 (Core 2 T7400) */
14846 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14847
14848 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14849 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14850
14851 /* HP Chromebook 14 (Celeron 2955U) */
14852 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14853
14854 /* Dell Chromebook 11 */
14855 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14856 };
14857
14858 static void intel_init_quirks(struct drm_device *dev)
14859 {
14860 struct pci_dev *d = dev->pdev;
14861 int i;
14862
14863 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14864 struct intel_quirk *q = &intel_quirks[i];
14865
14866 if (d->device == q->device &&
14867 (d->subsystem_vendor == q->subsystem_vendor ||
14868 q->subsystem_vendor == PCI_ANY_ID) &&
14869 (d->subsystem_device == q->subsystem_device ||
14870 q->subsystem_device == PCI_ANY_ID))
14871 q->hook(dev);
14872 }
14873 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14874 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14875 intel_dmi_quirks[i].hook(dev);
14876 }
14877 }
14878
14879 /* Disable the VGA plane that we never use */
14880 static void i915_disable_vga(struct drm_device *dev)
14881 {
14882 struct drm_i915_private *dev_priv = dev->dev_private;
14883 u8 sr1;
14884 u32 vga_reg = i915_vgacntrl_reg(dev);
14885
14886 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14887 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14888 outb(SR01, VGA_SR_INDEX);
14889 sr1 = inb(VGA_SR_DATA);
14890 outb(sr1 | 1<<5, VGA_SR_DATA);
14891 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14892 udelay(300);
14893
14894 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14895 POSTING_READ(vga_reg);
14896 }
14897
14898 void intel_modeset_init_hw(struct drm_device *dev)
14899 {
14900 intel_update_cdclk(dev);
14901 intel_prepare_ddi(dev);
14902 intel_init_clock_gating(dev);
14903 intel_enable_gt_powersave(dev);
14904 }
14905
14906 void intel_modeset_init(struct drm_device *dev)
14907 {
14908 struct drm_i915_private *dev_priv = dev->dev_private;
14909 int sprite, ret;
14910 enum pipe pipe;
14911 struct intel_crtc *crtc;
14912
14913 drm_mode_config_init(dev);
14914
14915 dev->mode_config.min_width = 0;
14916 dev->mode_config.min_height = 0;
14917
14918 dev->mode_config.preferred_depth = 24;
14919 dev->mode_config.prefer_shadow = 1;
14920
14921 dev->mode_config.allow_fb_modifiers = true;
14922
14923 dev->mode_config.funcs = &intel_mode_funcs;
14924
14925 intel_init_quirks(dev);
14926
14927 intel_init_pm(dev);
14928
14929 if (INTEL_INFO(dev)->num_pipes == 0)
14930 return;
14931
14932 intel_init_display(dev);
14933 intel_init_audio(dev);
14934
14935 if (IS_GEN2(dev)) {
14936 dev->mode_config.max_width = 2048;
14937 dev->mode_config.max_height = 2048;
14938 } else if (IS_GEN3(dev)) {
14939 dev->mode_config.max_width = 4096;
14940 dev->mode_config.max_height = 4096;
14941 } else {
14942 dev->mode_config.max_width = 8192;
14943 dev->mode_config.max_height = 8192;
14944 }
14945
14946 if (IS_845G(dev) || IS_I865G(dev)) {
14947 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14948 dev->mode_config.cursor_height = 1023;
14949 } else if (IS_GEN2(dev)) {
14950 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14951 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14952 } else {
14953 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14954 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14955 }
14956
14957 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14958
14959 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14960 INTEL_INFO(dev)->num_pipes,
14961 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14962
14963 for_each_pipe(dev_priv, pipe) {
14964 intel_crtc_init(dev, pipe);
14965 for_each_sprite(dev_priv, pipe, sprite) {
14966 ret = intel_plane_init(dev, pipe, sprite);
14967 if (ret)
14968 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14969 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14970 }
14971 }
14972
14973 intel_init_dpio(dev);
14974
14975 intel_shared_dpll_init(dev);
14976
14977 /* Just disable it once at startup */
14978 i915_disable_vga(dev);
14979 intel_setup_outputs(dev);
14980
14981 /* Just in case the BIOS is doing something questionable. */
14982 intel_fbc_disable(dev);
14983
14984 drm_modeset_lock_all(dev);
14985 intel_modeset_setup_hw_state(dev, false);
14986 drm_modeset_unlock_all(dev);
14987
14988 for_each_intel_crtc(dev, crtc) {
14989 if (!crtc->active)
14990 continue;
14991
14992 /*
14993 * Note that reserving the BIOS fb up front prevents us
14994 * from stuffing other stolen allocations like the ring
14995 * on top. This prevents some ugliness at boot time, and
14996 * can even allow for smooth boot transitions if the BIOS
14997 * fb is large enough for the active pipe configuration.
14998 */
14999 if (dev_priv->display.get_initial_plane_config) {
15000 dev_priv->display.get_initial_plane_config(crtc,
15001 &crtc->plane_config);
15002 /*
15003 * If the fb is shared between multiple heads, we'll
15004 * just get the first one.
15005 */
15006 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15007 }
15008 }
15009 }
15010
15011 static void intel_enable_pipe_a(struct drm_device *dev)
15012 {
15013 struct intel_connector *connector;
15014 struct drm_connector *crt = NULL;
15015 struct intel_load_detect_pipe load_detect_temp;
15016 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15017
15018 /* We can't just switch on the pipe A, we need to set things up with a
15019 * proper mode and output configuration. As a gross hack, enable pipe A
15020 * by enabling the load detect pipe once. */
15021 for_each_intel_connector(dev, connector) {
15022 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15023 crt = &connector->base;
15024 break;
15025 }
15026 }
15027
15028 if (!crt)
15029 return;
15030
15031 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15032 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15033 }
15034
15035 static bool
15036 intel_check_plane_mapping(struct intel_crtc *crtc)
15037 {
15038 struct drm_device *dev = crtc->base.dev;
15039 struct drm_i915_private *dev_priv = dev->dev_private;
15040 u32 reg, val;
15041
15042 if (INTEL_INFO(dev)->num_pipes == 1)
15043 return true;
15044
15045 reg = DSPCNTR(!crtc->plane);
15046 val = I915_READ(reg);
15047
15048 if ((val & DISPLAY_PLANE_ENABLE) &&
15049 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15050 return false;
15051
15052 return true;
15053 }
15054
15055 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15056 {
15057 struct drm_device *dev = crtc->base.dev;
15058 struct drm_i915_private *dev_priv = dev->dev_private;
15059 u32 reg;
15060
15061 /* Clear any frame start delays used for debugging left by the BIOS */
15062 reg = PIPECONF(crtc->config->cpu_transcoder);
15063 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15064
15065 /* restore vblank interrupts to correct state */
15066 drm_crtc_vblank_reset(&crtc->base);
15067 if (crtc->active) {
15068 update_scanline_offset(crtc);
15069 drm_crtc_vblank_on(&crtc->base);
15070 }
15071
15072 /* We need to sanitize the plane -> pipe mapping first because this will
15073 * disable the crtc (and hence change the state) if it is wrong. Note
15074 * that gen4+ has a fixed plane -> pipe mapping. */
15075 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15076 struct intel_connector *connector;
15077 bool plane;
15078
15079 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15080 crtc->base.base.id);
15081
15082 /* Pipe has the wrong plane attached and the plane is active.
15083 * Temporarily change the plane mapping and disable everything
15084 * ... */
15085 plane = crtc->plane;
15086 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15087 crtc->plane = !plane;
15088 intel_crtc_control(&crtc->base, false);
15089 crtc->plane = plane;
15090
15091 /* ... and break all links. */
15092 for_each_intel_connector(dev, connector) {
15093 if (connector->encoder->base.crtc != &crtc->base)
15094 continue;
15095
15096 connector->base.dpms = DRM_MODE_DPMS_OFF;
15097 connector->base.encoder = NULL;
15098 }
15099 /* multiple connectors may have the same encoder:
15100 * handle them and break crtc link separately */
15101 for_each_intel_connector(dev, connector)
15102 if (connector->encoder->base.crtc == &crtc->base) {
15103 connector->encoder->base.crtc = NULL;
15104 connector->encoder->connectors_active = false;
15105 }
15106
15107 WARN_ON(crtc->active);
15108 crtc->base.state->enable = false;
15109 crtc->base.state->active = false;
15110 crtc->base.enabled = false;
15111 }
15112
15113 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15114 crtc->pipe == PIPE_A && !crtc->active) {
15115 /* BIOS forgot to enable pipe A, this mostly happens after
15116 * resume. Force-enable the pipe to fix this, the update_dpms
15117 * call below we restore the pipe to the right state, but leave
15118 * the required bits on. */
15119 intel_enable_pipe_a(dev);
15120 }
15121
15122 /* Adjust the state of the output pipe according to whether we
15123 * have active connectors/encoders. */
15124 intel_crtc_update_dpms(&crtc->base);
15125
15126 if (crtc->active != crtc->base.state->active) {
15127 struct intel_encoder *encoder;
15128
15129 /* This can happen either due to bugs in the get_hw_state
15130 * functions or because the pipe is force-enabled due to the
15131 * pipe A quirk. */
15132 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15133 crtc->base.base.id,
15134 crtc->base.state->enable ? "enabled" : "disabled",
15135 crtc->active ? "enabled" : "disabled");
15136
15137 crtc->base.state->enable = crtc->active;
15138 crtc->base.state->active = crtc->active;
15139 crtc->base.enabled = crtc->active;
15140
15141 /* Because we only establish the connector -> encoder ->
15142 * crtc links if something is active, this means the
15143 * crtc is now deactivated. Break the links. connector
15144 * -> encoder links are only establish when things are
15145 * actually up, hence no need to break them. */
15146 WARN_ON(crtc->active);
15147
15148 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15149 WARN_ON(encoder->connectors_active);
15150 encoder->base.crtc = NULL;
15151 }
15152 }
15153
15154 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15155 /*
15156 * We start out with underrun reporting disabled to avoid races.
15157 * For correct bookkeeping mark this on active crtcs.
15158 *
15159 * Also on gmch platforms we dont have any hardware bits to
15160 * disable the underrun reporting. Which means we need to start
15161 * out with underrun reporting disabled also on inactive pipes,
15162 * since otherwise we'll complain about the garbage we read when
15163 * e.g. coming up after runtime pm.
15164 *
15165 * No protection against concurrent access is required - at
15166 * worst a fifo underrun happens which also sets this to false.
15167 */
15168 crtc->cpu_fifo_underrun_disabled = true;
15169 crtc->pch_fifo_underrun_disabled = true;
15170 }
15171 }
15172
15173 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15174 {
15175 struct intel_connector *connector;
15176 struct drm_device *dev = encoder->base.dev;
15177
15178 /* We need to check both for a crtc link (meaning that the
15179 * encoder is active and trying to read from a pipe) and the
15180 * pipe itself being active. */
15181 bool has_active_crtc = encoder->base.crtc &&
15182 to_intel_crtc(encoder->base.crtc)->active;
15183
15184 if (encoder->connectors_active && !has_active_crtc) {
15185 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15186 encoder->base.base.id,
15187 encoder->base.name);
15188
15189 /* Connector is active, but has no active pipe. This is
15190 * fallout from our resume register restoring. Disable
15191 * the encoder manually again. */
15192 if (encoder->base.crtc) {
15193 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15194 encoder->base.base.id,
15195 encoder->base.name);
15196 encoder->disable(encoder);
15197 if (encoder->post_disable)
15198 encoder->post_disable(encoder);
15199 }
15200 encoder->base.crtc = NULL;
15201 encoder->connectors_active = false;
15202
15203 /* Inconsistent output/port/pipe state happens presumably due to
15204 * a bug in one of the get_hw_state functions. Or someplace else
15205 * in our code, like the register restore mess on resume. Clamp
15206 * things to off as a safer default. */
15207 for_each_intel_connector(dev, connector) {
15208 if (connector->encoder != encoder)
15209 continue;
15210 connector->base.dpms = DRM_MODE_DPMS_OFF;
15211 connector->base.encoder = NULL;
15212 }
15213 }
15214 /* Enabled encoders without active connectors will be fixed in
15215 * the crtc fixup. */
15216 }
15217
15218 void i915_redisable_vga_power_on(struct drm_device *dev)
15219 {
15220 struct drm_i915_private *dev_priv = dev->dev_private;
15221 u32 vga_reg = i915_vgacntrl_reg(dev);
15222
15223 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15224 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15225 i915_disable_vga(dev);
15226 }
15227 }
15228
15229 void i915_redisable_vga(struct drm_device *dev)
15230 {
15231 struct drm_i915_private *dev_priv = dev->dev_private;
15232
15233 /* This function can be called both from intel_modeset_setup_hw_state or
15234 * at a very early point in our resume sequence, where the power well
15235 * structures are not yet restored. Since this function is at a very
15236 * paranoid "someone might have enabled VGA while we were not looking"
15237 * level, just check if the power well is enabled instead of trying to
15238 * follow the "don't touch the power well if we don't need it" policy
15239 * the rest of the driver uses. */
15240 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15241 return;
15242
15243 i915_redisable_vga_power_on(dev);
15244 }
15245
15246 static bool primary_get_hw_state(struct intel_crtc *crtc)
15247 {
15248 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15249
15250 if (!crtc->active)
15251 return false;
15252
15253 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15254 }
15255
15256 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15257 {
15258 struct drm_i915_private *dev_priv = dev->dev_private;
15259 enum pipe pipe;
15260 struct intel_crtc *crtc;
15261 struct intel_encoder *encoder;
15262 struct intel_connector *connector;
15263 int i;
15264
15265 for_each_intel_crtc(dev, crtc) {
15266 struct drm_plane *primary = crtc->base.primary;
15267 struct intel_plane_state *plane_state;
15268
15269 memset(crtc->config, 0, sizeof(*crtc->config));
15270
15271 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15272
15273 crtc->active = dev_priv->display.get_pipe_config(crtc,
15274 crtc->config);
15275
15276 crtc->base.state->enable = crtc->active;
15277 crtc->base.state->active = crtc->active;
15278 crtc->base.enabled = crtc->active;
15279
15280 plane_state = to_intel_plane_state(primary->state);
15281 plane_state->visible = primary_get_hw_state(crtc);
15282
15283 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15284 crtc->base.base.id,
15285 crtc->active ? "enabled" : "disabled");
15286 }
15287
15288 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15289 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15290
15291 pll->on = pll->get_hw_state(dev_priv, pll,
15292 &pll->config.hw_state);
15293 pll->active = 0;
15294 pll->config.crtc_mask = 0;
15295 for_each_intel_crtc(dev, crtc) {
15296 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15297 pll->active++;
15298 pll->config.crtc_mask |= 1 << crtc->pipe;
15299 }
15300 }
15301
15302 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15303 pll->name, pll->config.crtc_mask, pll->on);
15304
15305 if (pll->config.crtc_mask)
15306 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15307 }
15308
15309 for_each_intel_encoder(dev, encoder) {
15310 pipe = 0;
15311
15312 if (encoder->get_hw_state(encoder, &pipe)) {
15313 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15314 encoder->base.crtc = &crtc->base;
15315 encoder->get_config(encoder, crtc->config);
15316 } else {
15317 encoder->base.crtc = NULL;
15318 }
15319
15320 encoder->connectors_active = false;
15321 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15322 encoder->base.base.id,
15323 encoder->base.name,
15324 encoder->base.crtc ? "enabled" : "disabled",
15325 pipe_name(pipe));
15326 }
15327
15328 for_each_intel_connector(dev, connector) {
15329 if (connector->get_hw_state(connector)) {
15330 connector->base.dpms = DRM_MODE_DPMS_ON;
15331 connector->encoder->connectors_active = true;
15332 connector->base.encoder = &connector->encoder->base;
15333 } else {
15334 connector->base.dpms = DRM_MODE_DPMS_OFF;
15335 connector->base.encoder = NULL;
15336 }
15337 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15338 connector->base.base.id,
15339 connector->base.name,
15340 connector->base.encoder ? "enabled" : "disabled");
15341 }
15342 }
15343
15344 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15345 * and i915 state tracking structures. */
15346 void intel_modeset_setup_hw_state(struct drm_device *dev,
15347 bool force_restore)
15348 {
15349 struct drm_i915_private *dev_priv = dev->dev_private;
15350 enum pipe pipe;
15351 struct intel_crtc *crtc;
15352 struct intel_encoder *encoder;
15353 int i;
15354
15355 intel_modeset_readout_hw_state(dev);
15356
15357 /*
15358 * Now that we have the config, copy it to each CRTC struct
15359 * Note that this could go away if we move to using crtc_config
15360 * checking everywhere.
15361 */
15362 for_each_intel_crtc(dev, crtc) {
15363 if (crtc->active && i915.fastboot) {
15364 intel_mode_from_pipe_config(&crtc->base.mode,
15365 crtc->config);
15366 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15367 crtc->base.base.id);
15368 drm_mode_debug_printmodeline(&crtc->base.mode);
15369 }
15370 }
15371
15372 /* HW state is read out, now we need to sanitize this mess. */
15373 for_each_intel_encoder(dev, encoder) {
15374 intel_sanitize_encoder(encoder);
15375 }
15376
15377 for_each_pipe(dev_priv, pipe) {
15378 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15379 intel_sanitize_crtc(crtc);
15380 intel_dump_pipe_config(crtc, crtc->config,
15381 "[setup_hw_state]");
15382 }
15383
15384 intel_modeset_update_connector_atomic_state(dev);
15385
15386 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15387 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15388
15389 if (!pll->on || pll->active)
15390 continue;
15391
15392 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15393
15394 pll->disable(dev_priv, pll);
15395 pll->on = false;
15396 }
15397
15398 if (IS_GEN9(dev))
15399 skl_wm_get_hw_state(dev);
15400 else if (HAS_PCH_SPLIT(dev))
15401 ilk_wm_get_hw_state(dev);
15402
15403 if (force_restore) {
15404 i915_redisable_vga(dev);
15405
15406 /*
15407 * We need to use raw interfaces for restoring state to avoid
15408 * checking (bogus) intermediate states.
15409 */
15410 for_each_pipe(dev_priv, pipe) {
15411 struct drm_crtc *crtc =
15412 dev_priv->pipe_to_crtc_mapping[pipe];
15413
15414 intel_crtc_restore_mode(crtc);
15415 }
15416 } else {
15417 intel_modeset_update_staged_output_state(dev);
15418 }
15419
15420 intel_modeset_check_state(dev);
15421 }
15422
15423 void intel_modeset_gem_init(struct drm_device *dev)
15424 {
15425 struct drm_i915_private *dev_priv = dev->dev_private;
15426 struct drm_crtc *c;
15427 struct drm_i915_gem_object *obj;
15428 int ret;
15429
15430 mutex_lock(&dev->struct_mutex);
15431 intel_init_gt_powersave(dev);
15432 mutex_unlock(&dev->struct_mutex);
15433
15434 /*
15435 * There may be no VBT; and if the BIOS enabled SSC we can
15436 * just keep using it to avoid unnecessary flicker. Whereas if the
15437 * BIOS isn't using it, don't assume it will work even if the VBT
15438 * indicates as much.
15439 */
15440 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15441 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15442 DREF_SSC1_ENABLE);
15443
15444 intel_modeset_init_hw(dev);
15445
15446 intel_setup_overlay(dev);
15447
15448 /*
15449 * Make sure any fbs we allocated at startup are properly
15450 * pinned & fenced. When we do the allocation it's too early
15451 * for this.
15452 */
15453 for_each_crtc(dev, c) {
15454 obj = intel_fb_obj(c->primary->fb);
15455 if (obj == NULL)
15456 continue;
15457
15458 mutex_lock(&dev->struct_mutex);
15459 ret = intel_pin_and_fence_fb_obj(c->primary,
15460 c->primary->fb,
15461 c->primary->state,
15462 NULL);
15463 mutex_unlock(&dev->struct_mutex);
15464 if (ret) {
15465 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15466 to_intel_crtc(c)->pipe);
15467 drm_framebuffer_unreference(c->primary->fb);
15468 c->primary->fb = NULL;
15469 c->primary->crtc = c->primary->state->crtc = NULL;
15470 update_state_fb(c->primary);
15471 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15472 }
15473 }
15474
15475 intel_backlight_register(dev);
15476 }
15477
15478 void intel_connector_unregister(struct intel_connector *intel_connector)
15479 {
15480 struct drm_connector *connector = &intel_connector->base;
15481
15482 intel_panel_destroy_backlight(connector);
15483 drm_connector_unregister(connector);
15484 }
15485
15486 void intel_modeset_cleanup(struct drm_device *dev)
15487 {
15488 struct drm_i915_private *dev_priv = dev->dev_private;
15489 struct drm_connector *connector;
15490
15491 intel_disable_gt_powersave(dev);
15492
15493 intel_backlight_unregister(dev);
15494
15495 /*
15496 * Interrupts and polling as the first thing to avoid creating havoc.
15497 * Too much stuff here (turning of connectors, ...) would
15498 * experience fancy races otherwise.
15499 */
15500 intel_irq_uninstall(dev_priv);
15501
15502 /*
15503 * Due to the hpd irq storm handling the hotplug work can re-arm the
15504 * poll handlers. Hence disable polling after hpd handling is shut down.
15505 */
15506 drm_kms_helper_poll_fini(dev);
15507
15508 mutex_lock(&dev->struct_mutex);
15509
15510 intel_unregister_dsm_handler();
15511
15512 intel_fbc_disable(dev);
15513
15514 mutex_unlock(&dev->struct_mutex);
15515
15516 /* flush any delayed tasks or pending work */
15517 flush_scheduled_work();
15518
15519 /* destroy the backlight and sysfs files before encoders/connectors */
15520 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15521 struct intel_connector *intel_connector;
15522
15523 intel_connector = to_intel_connector(connector);
15524 intel_connector->unregister(intel_connector);
15525 }
15526
15527 drm_mode_config_cleanup(dev);
15528
15529 intel_cleanup_overlay(dev);
15530
15531 mutex_lock(&dev->struct_mutex);
15532 intel_cleanup_gt_powersave(dev);
15533 mutex_unlock(&dev->struct_mutex);
15534 }
15535
15536 /*
15537 * Return which encoder is currently attached for connector.
15538 */
15539 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15540 {
15541 return &intel_attached_encoder(connector)->base;
15542 }
15543
15544 void intel_connector_attach_encoder(struct intel_connector *connector,
15545 struct intel_encoder *encoder)
15546 {
15547 connector->encoder = encoder;
15548 drm_mode_connector_attach_encoder(&connector->base,
15549 &encoder->base);
15550 }
15551
15552 /*
15553 * set vga decode state - true == enable VGA decode
15554 */
15555 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15556 {
15557 struct drm_i915_private *dev_priv = dev->dev_private;
15558 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15559 u16 gmch_ctrl;
15560
15561 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15562 DRM_ERROR("failed to read control word\n");
15563 return -EIO;
15564 }
15565
15566 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15567 return 0;
15568
15569 if (state)
15570 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15571 else
15572 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15573
15574 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15575 DRM_ERROR("failed to write control word\n");
15576 return -EIO;
15577 }
15578
15579 return 0;
15580 }
15581
15582 struct intel_display_error_state {
15583
15584 u32 power_well_driver;
15585
15586 int num_transcoders;
15587
15588 struct intel_cursor_error_state {
15589 u32 control;
15590 u32 position;
15591 u32 base;
15592 u32 size;
15593 } cursor[I915_MAX_PIPES];
15594
15595 struct intel_pipe_error_state {
15596 bool power_domain_on;
15597 u32 source;
15598 u32 stat;
15599 } pipe[I915_MAX_PIPES];
15600
15601 struct intel_plane_error_state {
15602 u32 control;
15603 u32 stride;
15604 u32 size;
15605 u32 pos;
15606 u32 addr;
15607 u32 surface;
15608 u32 tile_offset;
15609 } plane[I915_MAX_PIPES];
15610
15611 struct intel_transcoder_error_state {
15612 bool power_domain_on;
15613 enum transcoder cpu_transcoder;
15614
15615 u32 conf;
15616
15617 u32 htotal;
15618 u32 hblank;
15619 u32 hsync;
15620 u32 vtotal;
15621 u32 vblank;
15622 u32 vsync;
15623 } transcoder[4];
15624 };
15625
15626 struct intel_display_error_state *
15627 intel_display_capture_error_state(struct drm_device *dev)
15628 {
15629 struct drm_i915_private *dev_priv = dev->dev_private;
15630 struct intel_display_error_state *error;
15631 int transcoders[] = {
15632 TRANSCODER_A,
15633 TRANSCODER_B,
15634 TRANSCODER_C,
15635 TRANSCODER_EDP,
15636 };
15637 int i;
15638
15639 if (INTEL_INFO(dev)->num_pipes == 0)
15640 return NULL;
15641
15642 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15643 if (error == NULL)
15644 return NULL;
15645
15646 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15647 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15648
15649 for_each_pipe(dev_priv, i) {
15650 error->pipe[i].power_domain_on =
15651 __intel_display_power_is_enabled(dev_priv,
15652 POWER_DOMAIN_PIPE(i));
15653 if (!error->pipe[i].power_domain_on)
15654 continue;
15655
15656 error->cursor[i].control = I915_READ(CURCNTR(i));
15657 error->cursor[i].position = I915_READ(CURPOS(i));
15658 error->cursor[i].base = I915_READ(CURBASE(i));
15659
15660 error->plane[i].control = I915_READ(DSPCNTR(i));
15661 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15662 if (INTEL_INFO(dev)->gen <= 3) {
15663 error->plane[i].size = I915_READ(DSPSIZE(i));
15664 error->plane[i].pos = I915_READ(DSPPOS(i));
15665 }
15666 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15667 error->plane[i].addr = I915_READ(DSPADDR(i));
15668 if (INTEL_INFO(dev)->gen >= 4) {
15669 error->plane[i].surface = I915_READ(DSPSURF(i));
15670 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15671 }
15672
15673 error->pipe[i].source = I915_READ(PIPESRC(i));
15674
15675 if (HAS_GMCH_DISPLAY(dev))
15676 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15677 }
15678
15679 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15680 if (HAS_DDI(dev_priv->dev))
15681 error->num_transcoders++; /* Account for eDP. */
15682
15683 for (i = 0; i < error->num_transcoders; i++) {
15684 enum transcoder cpu_transcoder = transcoders[i];
15685
15686 error->transcoder[i].power_domain_on =
15687 __intel_display_power_is_enabled(dev_priv,
15688 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15689 if (!error->transcoder[i].power_domain_on)
15690 continue;
15691
15692 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15693
15694 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15695 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15696 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15697 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15698 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15699 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15700 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15701 }
15702
15703 return error;
15704 }
15705
15706 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15707
15708 void
15709 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15710 struct drm_device *dev,
15711 struct intel_display_error_state *error)
15712 {
15713 struct drm_i915_private *dev_priv = dev->dev_private;
15714 int i;
15715
15716 if (!error)
15717 return;
15718
15719 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15720 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15721 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15722 error->power_well_driver);
15723 for_each_pipe(dev_priv, i) {
15724 err_printf(m, "Pipe [%d]:\n", i);
15725 err_printf(m, " Power: %s\n",
15726 error->pipe[i].power_domain_on ? "on" : "off");
15727 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15728 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15729
15730 err_printf(m, "Plane [%d]:\n", i);
15731 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15732 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15733 if (INTEL_INFO(dev)->gen <= 3) {
15734 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15735 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15736 }
15737 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15738 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15739 if (INTEL_INFO(dev)->gen >= 4) {
15740 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15741 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15742 }
15743
15744 err_printf(m, "Cursor [%d]:\n", i);
15745 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15746 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15747 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15748 }
15749
15750 for (i = 0; i < error->num_transcoders; i++) {
15751 err_printf(m, "CPU transcoder: %c\n",
15752 transcoder_name(error->transcoder[i].cpu_transcoder));
15753 err_printf(m, " Power: %s\n",
15754 error->transcoder[i].power_domain_on ? "on" : "off");
15755 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15756 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15757 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15758 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15759 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15760 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15761 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15762 }
15763 }
15764
15765 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15766 {
15767 struct intel_crtc *crtc;
15768
15769 for_each_intel_crtc(dev, crtc) {
15770 struct intel_unpin_work *work;
15771
15772 spin_lock_irq(&dev->event_lock);
15773
15774 work = crtc->unpin_work;
15775
15776 if (work && work->event &&
15777 work->event->base.file_priv == file) {
15778 kfree(work->event);
15779 work->event = NULL;
15780 }
15781
15782 spin_unlock_irq(&dev->event_lock);
15783 }
15784 }
Linux kernel - Deliverables
This page took 0.349396 seconds and 6 git commands to generate.