2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
29 #include "intel_drv.h"
33 #include "drm_crtc_helper.h"
35 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
58 #define INTEL_P2_NUM 2
61 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
65 #define I8XX_DOT_MIN 25000
66 #define I8XX_DOT_MAX 350000
67 #define I8XX_VCO_MIN 930000
68 #define I8XX_VCO_MAX 1400000
72 #define I8XX_M_MAX 140
73 #define I8XX_M1_MIN 18
74 #define I8XX_M1_MAX 26
76 #define I8XX_M2_MAX 16
78 #define I8XX_P_MAX 128
80 #define I8XX_P1_MAX 33
81 #define I8XX_P1_LVDS_MIN 1
82 #define I8XX_P1_LVDS_MAX 6
83 #define I8XX_P2_SLOW 4
84 #define I8XX_P2_FAST 2
85 #define I8XX_P2_LVDS_SLOW 14
86 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
87 #define I8XX_P2_SLOW_LIMIT 165000
89 #define I9XX_DOT_MIN 20000
90 #define I9XX_DOT_MAX 400000
91 #define I9XX_VCO_MIN 1400000
92 #define I9XX_VCO_MAX 2800000
96 #define I9XX_M_MAX 120
97 #define I9XX_M1_MIN 10
98 #define I9XX_M1_MAX 22
100 #define I9XX_M2_MAX 9
101 #define I9XX_P_SDVO_DAC_MIN 5
102 #define I9XX_P_SDVO_DAC_MAX 80
103 #define I9XX_P_LVDS_MIN 7
104 #define I9XX_P_LVDS_MAX 98
105 #define I9XX_P1_MIN 1
106 #define I9XX_P1_MAX 8
107 #define I9XX_P2_SDVO_DAC_SLOW 10
108 #define I9XX_P2_SDVO_DAC_FAST 5
109 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
110 #define I9XX_P2_LVDS_SLOW 14
111 #define I9XX_P2_LVDS_FAST 7
112 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
114 #define INTEL_LIMIT_I8XX_DVO_DAC 0
115 #define INTEL_LIMIT_I8XX_LVDS 1
116 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
117 #define INTEL_LIMIT_I9XX_LVDS 3
119 static const intel_limit_t intel_limits
[] = {
120 { /* INTEL_LIMIT_I8XX_DVO_DAC */
121 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
122 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
123 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
124 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
125 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
126 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
127 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
128 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
129 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
130 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
132 { /* INTEL_LIMIT_I8XX_LVDS */
133 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
134 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
135 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
136 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
137 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
138 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
139 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
140 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
141 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
142 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
144 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
145 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
146 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
147 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
148 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
149 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
150 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
151 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
152 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
153 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
154 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
156 { /* INTEL_LIMIT_I9XX_LVDS */
157 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
158 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
159 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
160 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
161 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
162 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
163 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
164 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
165 /* The single-channel range is 25-112Mhz, and dual-channel
166 * is 80-224Mhz. Prefer single channel as much as possible.
168 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
169 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
173 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
175 struct drm_device
*dev
= crtc
->dev
;
176 const intel_limit_t
*limit
;
179 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
180 limit
= &intel_limits
[INTEL_LIMIT_I9XX_LVDS
];
182 limit
= &intel_limits
[INTEL_LIMIT_I9XX_SDVO_DAC
];
184 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
185 limit
= &intel_limits
[INTEL_LIMIT_I8XX_LVDS
];
187 limit
= &intel_limits
[INTEL_LIMIT_I8XX_DVO_DAC
];
192 static void intel_clock(int refclk
, intel_clock_t
*clock
)
194 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
195 clock
->p
= clock
->p1
* clock
->p2
;
196 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
197 clock
->dot
= clock
->vco
/ clock
->p
;
201 * Returns whether any output on the specified pipe is of the specified type
203 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
205 struct drm_device
*dev
= crtc
->dev
;
206 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
207 struct drm_connector
*l_entry
;
209 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
210 if (l_entry
->encoder
&&
211 l_entry
->encoder
->crtc
== crtc
) {
212 struct intel_output
*intel_output
= to_intel_output(l_entry
);
213 if (intel_output
->type
== type
)
220 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
222 * Returns whether the given set of divisors are valid for a given refclk with
223 * the given connectors.
226 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
228 const intel_limit_t
*limit
= intel_limit (crtc
);
230 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
231 INTELPllInvalid ("p1 out of range\n");
232 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
233 INTELPllInvalid ("p out of range\n");
234 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
235 INTELPllInvalid ("m2 out of range\n");
236 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
237 INTELPllInvalid ("m1 out of range\n");
238 if (clock
->m1
<= clock
->m2
)
239 INTELPllInvalid ("m1 <= m2\n");
240 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
241 INTELPllInvalid ("m out of range\n");
242 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
243 INTELPllInvalid ("n out of range\n");
244 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
245 INTELPllInvalid ("vco out of range\n");
246 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
247 * connector, etc., rather than just a single range.
249 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
250 INTELPllInvalid ("dot out of range\n");
256 * Returns a set of divisors for the desired target clock with the given
257 * refclk, or FALSE. The returned values represent the clock equation:
258 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
260 static bool intel_find_best_PLL(struct drm_crtc
*crtc
, int target
,
261 int refclk
, intel_clock_t
*best_clock
)
263 struct drm_device
*dev
= crtc
->dev
;
264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 const intel_limit_t
*limit
= intel_limit(crtc
);
269 if (IS_I9XX(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
270 (I915_READ(LVDS
) & LVDS_PORT_EN
) != 0) {
272 * For LVDS, if the panel is on, just rely on its current
273 * settings for dual-channel. We haven't figured out how to
274 * reliably set up different single/dual channel state, if we
277 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
279 clock
.p2
= limit
->p2
.p2_fast
;
281 clock
.p2
= limit
->p2
.p2_slow
;
283 if (target
< limit
->p2
.dot_limit
)
284 clock
.p2
= limit
->p2
.p2_slow
;
286 clock
.p2
= limit
->p2
.p2_fast
;
289 memset (best_clock
, 0, sizeof (*best_clock
));
291 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
292 for (clock
.m2
= limit
->m2
.min
; clock
.m2
< clock
.m1
&&
293 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
294 for (clock
.n
= limit
->n
.min
; clock
.n
<= limit
->n
.max
;
296 for (clock
.p1
= limit
->p1
.min
;
297 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
300 intel_clock(refclk
, &clock
);
302 if (!intel_PLL_is_valid(crtc
, &clock
))
305 this_err
= abs(clock
.dot
- target
);
306 if (this_err
< err
) {
315 return (err
!= target
);
319 intel_wait_for_vblank(struct drm_device
*dev
)
321 /* Wait for 20ms, i.e. one cycle at 50hz. */
326 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
327 struct drm_framebuffer
*old_fb
)
329 struct drm_device
*dev
= crtc
->dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
331 struct drm_i915_master_private
*master_priv
;
332 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
333 struct intel_framebuffer
*intel_fb
;
334 struct drm_i915_gem_object
*obj_priv
;
335 struct drm_gem_object
*obj
;
336 int pipe
= intel_crtc
->pipe
;
337 unsigned long Start
, Offset
;
338 int dspbase
= (pipe
== 0 ? DSPAADDR
: DSPBADDR
);
339 int dspsurf
= (pipe
== 0 ? DSPASURF
: DSPBSURF
);
340 int dspstride
= (pipe
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
341 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
342 u32 dspcntr
, alignment
;
347 DRM_DEBUG("No FB bound\n");
356 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
360 intel_fb
= to_intel_framebuffer(crtc
->fb
);
362 obj_priv
= obj
->driver_private
;
364 switch (obj_priv
->tiling_mode
) {
365 case I915_TILING_NONE
:
366 alignment
= 64 * 1024;
369 /* pin() will align the object as required by fence */
373 /* FIXME: Is this true? */
374 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
380 mutex_lock(&dev
->struct_mutex
);
381 ret
= i915_gem_object_pin(intel_fb
->obj
, alignment
);
383 mutex_unlock(&dev
->struct_mutex
);
387 ret
= i915_gem_object_set_to_gtt_domain(intel_fb
->obj
, 1);
389 i915_gem_object_unpin(intel_fb
->obj
);
390 mutex_unlock(&dev
->struct_mutex
);
394 dspcntr
= I915_READ(dspcntr_reg
);
395 /* Mask out pixel format bits in case we change it */
396 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
397 switch (crtc
->fb
->bits_per_pixel
) {
399 dspcntr
|= DISPPLANE_8BPP
;
402 if (crtc
->fb
->depth
== 15)
403 dspcntr
|= DISPPLANE_15_16BPP
;
405 dspcntr
|= DISPPLANE_16BPP
;
409 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
412 DRM_ERROR("Unknown color depth\n");
413 i915_gem_object_unpin(intel_fb
->obj
);
414 mutex_unlock(&dev
->struct_mutex
);
417 I915_WRITE(dspcntr_reg
, dspcntr
);
419 Start
= obj_priv
->gtt_offset
;
420 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
422 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
423 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
425 I915_WRITE(dspbase
, Offset
);
427 I915_WRITE(dspsurf
, Start
);
430 I915_WRITE(dspbase
, Start
+ Offset
);
434 intel_wait_for_vblank(dev
);
437 intel_fb
= to_intel_framebuffer(old_fb
);
438 i915_gem_object_unpin(intel_fb
->obj
);
440 mutex_unlock(&dev
->struct_mutex
);
442 if (!dev
->primary
->master
)
445 master_priv
= dev
->primary
->master
->driver_priv
;
446 if (!master_priv
->sarea_priv
)
450 master_priv
->sarea_priv
->pipeB_x
= x
;
451 master_priv
->sarea_priv
->pipeB_y
= y
;
453 master_priv
->sarea_priv
->pipeA_x
= x
;
454 master_priv
->sarea_priv
->pipeA_y
= y
;
463 * Sets the power management mode of the pipe and plane.
465 * This code should probably grow support for turning the cursor off and back
466 * on appropriately at the same time as we're turning the pipe off/on.
468 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
470 struct drm_device
*dev
= crtc
->dev
;
471 struct drm_i915_master_private
*master_priv
;
472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
473 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
474 int pipe
= intel_crtc
->pipe
;
475 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
476 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
477 int dspbase_reg
= (pipe
== 0) ? DSPAADDR
: DSPBADDR
;
478 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
482 /* XXX: When our outputs are all unaware of DPMS modes other than off
483 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
486 case DRM_MODE_DPMS_ON
:
487 case DRM_MODE_DPMS_STANDBY
:
488 case DRM_MODE_DPMS_SUSPEND
:
489 /* Enable the DPLL */
490 temp
= I915_READ(dpll_reg
);
491 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
492 I915_WRITE(dpll_reg
, temp
);
494 /* Wait for the clocks to stabilize. */
496 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
498 /* Wait for the clocks to stabilize. */
500 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
502 /* Wait for the clocks to stabilize. */
506 /* Enable the pipe */
507 temp
= I915_READ(pipeconf_reg
);
508 if ((temp
& PIPEACONF_ENABLE
) == 0)
509 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
511 /* Enable the plane */
512 temp
= I915_READ(dspcntr_reg
);
513 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
514 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
515 /* Flush the plane changes */
516 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
519 intel_crtc_load_lut(crtc
);
521 /* Give the overlay scaler a chance to enable if it's on this pipe */
522 //intel_crtc_dpms_video(crtc, true); TODO
524 case DRM_MODE_DPMS_OFF
:
525 /* Give the overlay scaler a chance to disable if it's on this pipe */
526 //intel_crtc_dpms_video(crtc, FALSE); TODO
528 /* Disable the VGA plane that we never use */
529 I915_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
531 /* Disable display plane */
532 temp
= I915_READ(dspcntr_reg
);
533 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
534 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
535 /* Flush the plane changes */
536 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
537 I915_READ(dspbase_reg
);
541 /* Wait for vblank for the disable to take effect */
542 intel_wait_for_vblank(dev
);
545 /* Next, disable display pipes */
546 temp
= I915_READ(pipeconf_reg
);
547 if ((temp
& PIPEACONF_ENABLE
) != 0) {
548 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
549 I915_READ(pipeconf_reg
);
552 /* Wait for vblank for the disable to take effect. */
553 intel_wait_for_vblank(dev
);
555 temp
= I915_READ(dpll_reg
);
556 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
557 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
561 /* Wait for the clocks to turn off. */
566 if (!dev
->primary
->master
)
569 master_priv
= dev
->primary
->master
->driver_priv
;
570 if (!master_priv
->sarea_priv
)
573 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
577 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
578 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
581 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
582 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
585 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
589 intel_crtc
->dpms_mode
= mode
;
592 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
594 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
595 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
598 static void intel_crtc_commit (struct drm_crtc
*crtc
)
600 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
601 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
604 void intel_encoder_prepare (struct drm_encoder
*encoder
)
606 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
607 /* lvds has its own version of prepare see intel_lvds_prepare */
608 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
611 void intel_encoder_commit (struct drm_encoder
*encoder
)
613 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
614 /* lvds has its own version of commit see intel_lvds_commit */
615 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
618 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
619 struct drm_display_mode
*mode
,
620 struct drm_display_mode
*adjusted_mode
)
626 /** Returns the core display clock speed for i830 - i945 */
627 static int intel_get_core_clock_speed(struct drm_device
*dev
)
630 /* Core clock values taken from the published datasheets.
631 * The 830 may go up to 166 Mhz, which we should check.
635 else if (IS_I915G(dev
))
637 else if (IS_I945GM(dev
) || IS_845G(dev
))
639 else if (IS_I915GM(dev
)) {
642 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
644 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
647 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
648 case GC_DISPLAY_CLOCK_333_MHZ
:
651 case GC_DISPLAY_CLOCK_190_200_MHZ
:
655 } else if (IS_I865G(dev
))
657 else if (IS_I855(dev
)) {
659 /* Assume that the hardware is in the high speed state. This
660 * should be the default.
662 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
663 case GC_CLOCK_133_200
:
664 case GC_CLOCK_100_200
:
666 case GC_CLOCK_166_250
:
668 case GC_CLOCK_100_133
:
671 } else /* 852, 830 */
674 return 0; /* Silence gcc warning */
679 * Return the pipe currently connected to the panel fitter,
680 * or -1 if the panel fitter is not present or not in use
682 static int intel_panel_fitter_pipe (struct drm_device
*dev
)
684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
687 /* i830 doesn't have a panel fitter */
691 pfit_control
= I915_READ(PFIT_CONTROL
);
693 /* See if the panel fitter is in use */
694 if ((pfit_control
& PFIT_ENABLE
) == 0)
697 /* 965 can place panel fitter on either pipe */
699 return (pfit_control
>> 29) & 0x3;
701 /* older chips can only use pipe 1 */
705 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
706 struct drm_display_mode
*mode
,
707 struct drm_display_mode
*adjusted_mode
,
709 struct drm_framebuffer
*old_fb
)
711 struct drm_device
*dev
= crtc
->dev
;
712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
714 int pipe
= intel_crtc
->pipe
;
715 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
716 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
717 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
718 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
719 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
720 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
721 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
722 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
723 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
724 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
725 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
726 int dspsize_reg
= (pipe
== 0) ? DSPASIZE
: DSPBSIZE
;
727 int dsppos_reg
= (pipe
== 0) ? DSPAPOS
: DSPBPOS
;
728 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
729 int refclk
, num_outputs
= 0;
731 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
732 bool ok
, is_sdvo
= false, is_dvo
= false;
733 bool is_crt
= false, is_lvds
= false, is_tv
= false;
734 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
735 struct drm_connector
*connector
;
738 drm_vblank_pre_modeset(dev
, pipe
);
740 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
741 struct intel_output
*intel_output
= to_intel_output(connector
);
743 if (!connector
->encoder
|| connector
->encoder
->crtc
!= crtc
)
746 switch (intel_output
->type
) {
747 case INTEL_OUTPUT_LVDS
:
750 case INTEL_OUTPUT_SDVO
:
751 case INTEL_OUTPUT_HDMI
:
753 if (intel_output
->needs_tv_clock
)
756 case INTEL_OUTPUT_DVO
:
759 case INTEL_OUTPUT_TVOUT
:
762 case INTEL_OUTPUT_ANALOG
:
770 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2) {
771 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
772 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk
/ 1000);
773 } else if (IS_I9XX(dev
)) {
779 ok
= intel_find_best_PLL(crtc
, adjusted_mode
->clock
, refclk
, &clock
);
781 DRM_ERROR("Couldn't find PLL settings for mode!\n");
785 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
787 dpll
= DPLL_VGA_MODE_DIS
;
790 dpll
|= DPLLB_MODE_LVDS
;
792 dpll
|= DPLLB_MODE_DAC_SERIAL
;
794 dpll
|= DPLL_DVO_HIGH_SPEED
;
795 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
796 int sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
797 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
801 /* compute bitmask from p1 value */
802 dpll
|= (1 << (clock
.p1
- 1)) << 16;
805 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
808 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
811 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
814 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
818 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
821 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
824 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
826 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
828 dpll
|= PLL_P2_DIVIDE_BY_4
;
832 if (is_sdvo
&& is_tv
)
833 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
835 /* XXX: just matching BIOS for now */
836 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
838 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2)
839 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
841 dpll
|= PLL_REF_INPUT_DREFCLK
;
844 pipeconf
= I915_READ(pipeconf_reg
);
846 /* Set up the display plane register */
847 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
850 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
852 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
854 if (pipe
== 0 && !IS_I965G(dev
)) {
855 /* Enable pixel doubling when the dot clock is > 90% of the (display)
858 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
861 if (mode
->clock
> intel_get_core_clock_speed(dev
) * 9 / 10)
862 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
864 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
867 dspcntr
|= DISPLAY_PLANE_ENABLE
;
868 pipeconf
|= PIPEACONF_ENABLE
;
869 dpll
|= DPLL_VCO_ENABLE
;
872 /* Disable the panel fitter if it was on our pipe */
873 if (intel_panel_fitter_pipe(dev
) == pipe
)
874 I915_WRITE(PFIT_CONTROL
, 0);
876 DRM_DEBUG("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
877 drm_mode_debug_printmodeline(mode
);
880 if (dpll
& DPLL_VCO_ENABLE
) {
881 I915_WRITE(fp_reg
, fp
);
882 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
887 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
888 * This is an exception to the general rule that mode_set doesn't turn
892 u32 lvds
= I915_READ(LVDS
);
894 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
| LVDS_PIPEB_SELECT
;
895 /* Set the B0-B3 data pairs corresponding to whether we're going to
896 * set the DPLLs for dual-channel mode or not.
899 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
901 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
903 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
904 * appropriately here, but we need to look more thoroughly into how
905 * panels behave in the two modes.
908 I915_WRITE(LVDS
, lvds
);
912 I915_WRITE(fp_reg
, fp
);
913 I915_WRITE(dpll_reg
, dpll
);
915 /* Wait for the clocks to stabilize. */
919 int sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
920 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
921 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
923 /* write it again -- the BIOS does, after all */
924 I915_WRITE(dpll_reg
, dpll
);
927 /* Wait for the clocks to stabilize. */
930 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
931 ((adjusted_mode
->crtc_htotal
- 1) << 16));
932 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
933 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
934 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
935 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
936 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
937 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
938 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
939 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
940 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
941 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
942 /* pipesrc and dspsize control the size that is scaled from, which should
943 * always be the user's requested size.
945 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) | (mode
->hdisplay
- 1));
946 I915_WRITE(dsppos_reg
, 0);
947 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
948 I915_WRITE(pipeconf_reg
, pipeconf
);
949 I915_READ(pipeconf_reg
);
951 intel_wait_for_vblank(dev
);
953 I915_WRITE(dspcntr_reg
, dspcntr
);
955 /* Flush the plane changes */
956 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
960 drm_vblank_post_modeset(dev
, pipe
);
965 /** Loads the palette/gamma unit for the CRTC with the prepared values */
966 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
968 struct drm_device
*dev
= crtc
->dev
;
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
971 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
974 /* The clocks have to be on to load the palette. */
978 for (i
= 0; i
< 256; i
++) {
979 I915_WRITE(palreg
+ 4 * i
,
980 (intel_crtc
->lut_r
[i
] << 16) |
981 (intel_crtc
->lut_g
[i
] << 8) |
982 intel_crtc
->lut_b
[i
]);
986 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
987 struct drm_file
*file_priv
,
989 uint32_t width
, uint32_t height
)
991 struct drm_device
*dev
= crtc
->dev
;
992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
993 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
994 struct drm_gem_object
*bo
;
995 struct drm_i915_gem_object
*obj_priv
;
996 int pipe
= intel_crtc
->pipe
;
997 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
998 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
1005 /* if we want to turn off the cursor ignore width and height */
1007 DRM_DEBUG("cursor off\n");
1008 temp
= CURSOR_MODE_DISABLE
;
1011 mutex_lock(&dev
->struct_mutex
);
1015 /* Currently we only support 64x64 cursors */
1016 if (width
!= 64 || height
!= 64) {
1017 DRM_ERROR("we currently only support 64x64 cursors\n");
1021 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
1025 obj_priv
= bo
->driver_private
;
1027 if (bo
->size
< width
* height
* 4) {
1028 DRM_ERROR("buffer is to small\n");
1033 /* we only need to pin inside GTT if cursor is non-phy */
1034 mutex_lock(&dev
->struct_mutex
);
1035 if (!dev_priv
->cursor_needs_physical
) {
1036 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
1038 DRM_ERROR("failed to pin cursor bo\n");
1041 addr
= obj_priv
->gtt_offset
;
1043 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
1045 DRM_ERROR("failed to attach phys object\n");
1048 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
1052 /* set the pipe for the cursor */
1053 temp
|= (pipe
<< 28);
1054 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
1057 I915_WRITE(control
, temp
);
1058 I915_WRITE(base
, addr
);
1060 if (intel_crtc
->cursor_bo
) {
1061 if (dev_priv
->cursor_needs_physical
) {
1062 if (intel_crtc
->cursor_bo
!= bo
)
1063 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
1065 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
1066 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
1068 mutex_unlock(&dev
->struct_mutex
);
1070 intel_crtc
->cursor_addr
= addr
;
1071 intel_crtc
->cursor_bo
= bo
;
1075 mutex_lock(&dev
->struct_mutex
);
1077 drm_gem_object_unreference(bo
);
1078 mutex_unlock(&dev
->struct_mutex
);
1082 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
1084 struct drm_device
*dev
= crtc
->dev
;
1085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1087 int pipe
= intel_crtc
->pipe
;
1092 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
1096 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
1100 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
1101 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
1103 adder
= intel_crtc
->cursor_addr
;
1104 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
1105 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
1110 /** Sets the color ramps on behalf of RandR */
1111 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
1112 u16 blue
, int regno
)
1114 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1116 intel_crtc
->lut_r
[regno
] = red
>> 8;
1117 intel_crtc
->lut_g
[regno
] = green
>> 8;
1118 intel_crtc
->lut_b
[regno
] = blue
>> 8;
1121 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
1122 u16
*blue
, uint32_t size
)
1124 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1130 for (i
= 0; i
< 256; i
++) {
1131 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
1132 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
1133 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
1136 intel_crtc_load_lut(crtc
);
1140 * Get a pipe with a simple mode set on it for doing load-based monitor
1143 * It will be up to the load-detect code to adjust the pipe as appropriate for
1144 * its requirements. The pipe will be connected to no other outputs.
1146 * Currently this code will only succeed if there is a pipe with no outputs
1147 * configured for it. In the future, it could choose to temporarily disable
1148 * some outputs to free up a pipe for its use.
1150 * \return crtc, or NULL if no pipes are available.
1153 /* VESA 640x480x72Hz mode to set on the pipe */
1154 static struct drm_display_mode load_detect_mode
= {
1155 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
1156 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
1159 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_output
*intel_output
,
1160 struct drm_display_mode
*mode
,
1163 struct intel_crtc
*intel_crtc
;
1164 struct drm_crtc
*possible_crtc
;
1165 struct drm_crtc
*supported_crtc
=NULL
;
1166 struct drm_encoder
*encoder
= &intel_output
->enc
;
1167 struct drm_crtc
*crtc
= NULL
;
1168 struct drm_device
*dev
= encoder
->dev
;
1169 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1170 struct drm_crtc_helper_funcs
*crtc_funcs
;
1174 * Algorithm gets a little messy:
1175 * - if the connector already has an assigned crtc, use it (but make
1176 * sure it's on first)
1177 * - try to find the first unused crtc that can drive this connector,
1178 * and use that if we find one
1179 * - if there are no unused crtcs available, try to use the first
1180 * one we found that supports the connector
1183 /* See if we already have a CRTC for this connector */
1184 if (encoder
->crtc
) {
1185 crtc
= encoder
->crtc
;
1186 /* Make sure the crtc and connector are running */
1187 intel_crtc
= to_intel_crtc(crtc
);
1188 *dpms_mode
= intel_crtc
->dpms_mode
;
1189 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
1190 crtc_funcs
= crtc
->helper_private
;
1191 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1192 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
1197 /* Find an unused one (if possible) */
1198 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1200 if (!(encoder
->possible_crtcs
& (1 << i
)))
1202 if (!possible_crtc
->enabled
) {
1203 crtc
= possible_crtc
;
1206 if (!supported_crtc
)
1207 supported_crtc
= possible_crtc
;
1211 * If we didn't find an unused CRTC, don't use any.
1217 encoder
->crtc
= crtc
;
1218 intel_output
->load_detect_temp
= true;
1220 intel_crtc
= to_intel_crtc(crtc
);
1221 *dpms_mode
= intel_crtc
->dpms_mode
;
1223 if (!crtc
->enabled
) {
1225 mode
= &load_detect_mode
;
1226 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
1228 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
1229 crtc_funcs
= crtc
->helper_private
;
1230 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1233 /* Add this connector to the crtc */
1234 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
1235 encoder_funcs
->commit(encoder
);
1237 /* let the connector get through one full cycle before testing */
1238 intel_wait_for_vblank(dev
);
1243 void intel_release_load_detect_pipe(struct intel_output
*intel_output
, int dpms_mode
)
1245 struct drm_encoder
*encoder
= &intel_output
->enc
;
1246 struct drm_device
*dev
= encoder
->dev
;
1247 struct drm_crtc
*crtc
= encoder
->crtc
;
1248 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1249 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1251 if (intel_output
->load_detect_temp
) {
1252 encoder
->crtc
= NULL
;
1253 intel_output
->load_detect_temp
= false;
1254 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
1255 drm_helper_disable_unused_functions(dev
);
1258 /* Switch crtc and output back off if necessary */
1259 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
1260 if (encoder
->crtc
== crtc
)
1261 encoder_funcs
->dpms(encoder
, dpms_mode
);
1262 crtc_funcs
->dpms(crtc
, dpms_mode
);
1266 /* Returns the clock of the currently programmed mode of the given pipe. */
1267 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
1269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1271 int pipe
= intel_crtc
->pipe
;
1272 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
1274 intel_clock_t clock
;
1276 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1277 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
1279 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
1281 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
1282 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
1283 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
1285 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
1286 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1288 switch (dpll
& DPLL_MODE_MASK
) {
1289 case DPLLB_MODE_DAC_SERIAL
:
1290 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
1293 case DPLLB_MODE_LVDS
:
1294 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
1298 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1299 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
1303 /* XXX: Handle the 100Mhz refclk */
1304 intel_clock(96000, &clock
);
1306 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
1309 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
1310 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1313 if ((dpll
& PLL_REF_INPUT_MASK
) ==
1314 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
1315 /* XXX: might not be 66MHz */
1316 intel_clock(66000, &clock
);
1318 intel_clock(48000, &clock
);
1320 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
1323 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
1324 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
1326 if (dpll
& PLL_P2_DIVIDE_BY_4
)
1331 intel_clock(48000, &clock
);
1335 /* XXX: It would be nice to validate the clocks, but we can't reuse
1336 * i830PllIsValid() because it relies on the xf86_config connector
1337 * configuration being accurate, which it isn't necessarily.
1343 /** Returns the currently programmed mode of the given pipe. */
1344 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1345 struct drm_crtc
*crtc
)
1347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1349 int pipe
= intel_crtc
->pipe
;
1350 struct drm_display_mode
*mode
;
1351 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
1352 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
1353 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
1354 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
1356 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
1360 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
1361 mode
->hdisplay
= (htot
& 0xffff) + 1;
1362 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
1363 mode
->hsync_start
= (hsync
& 0xffff) + 1;
1364 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
1365 mode
->vdisplay
= (vtot
& 0xffff) + 1;
1366 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
1367 mode
->vsync_start
= (vsync
& 0xffff) + 1;
1368 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
1370 drm_mode_set_name(mode
);
1371 drm_mode_set_crtcinfo(mode
, 0);
1376 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
1378 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1380 drm_crtc_cleanup(crtc
);
1384 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
1385 .dpms
= intel_crtc_dpms
,
1386 .mode_fixup
= intel_crtc_mode_fixup
,
1387 .mode_set
= intel_crtc_mode_set
,
1388 .mode_set_base
= intel_pipe_set_base
,
1389 .prepare
= intel_crtc_prepare
,
1390 .commit
= intel_crtc_commit
,
1393 static const struct drm_crtc_funcs intel_crtc_funcs
= {
1394 .cursor_set
= intel_crtc_cursor_set
,
1395 .cursor_move
= intel_crtc_cursor_move
,
1396 .gamma_set
= intel_crtc_gamma_set
,
1397 .set_config
= drm_crtc_helper_set_config
,
1398 .destroy
= intel_crtc_destroy
,
1402 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
1404 struct intel_crtc
*intel_crtc
;
1407 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
1408 if (intel_crtc
== NULL
)
1411 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
1413 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
1414 intel_crtc
->pipe
= pipe
;
1415 for (i
= 0; i
< 256; i
++) {
1416 intel_crtc
->lut_r
[i
] = i
;
1417 intel_crtc
->lut_g
[i
] = i
;
1418 intel_crtc
->lut_b
[i
] = i
;
1421 intel_crtc
->cursor_addr
= 0;
1422 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
1423 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
1425 intel_crtc
->mode_set
.crtc
= &intel_crtc
->base
;
1426 intel_crtc
->mode_set
.connectors
= (struct drm_connector
**)(intel_crtc
+ 1);
1427 intel_crtc
->mode_set
.num_connectors
= 0;
1429 if (i915_fbpercrtc
) {
1436 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
1438 struct drm_crtc
*crtc
= NULL
;
1440 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1441 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1442 if (intel_crtc
->pipe
== pipe
)
1448 static int intel_connector_clones(struct drm_device
*dev
, int type_mask
)
1451 struct drm_connector
*connector
;
1454 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1455 struct intel_output
*intel_output
= to_intel_output(connector
);
1456 if (type_mask
& (1 << intel_output
->type
))
1457 index_mask
|= (1 << entry
);
1464 static void intel_setup_outputs(struct drm_device
*dev
)
1466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1467 struct drm_connector
*connector
;
1469 intel_crt_init(dev
);
1471 /* Set up integrated LVDS */
1472 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1473 intel_lvds_init(dev
);
1478 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
1479 found
= intel_sdvo_init(dev
, SDVOB
);
1480 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
))
1481 intel_hdmi_init(dev
, SDVOB
);
1483 if (!IS_G4X(dev
) || (I915_READ(SDVOB
) & SDVO_DETECTED
)) {
1484 found
= intel_sdvo_init(dev
, SDVOC
);
1485 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
))
1486 intel_hdmi_init(dev
, SDVOC
);
1489 intel_dvo_init(dev
);
1491 if (IS_I9XX(dev
) && IS_MOBILE(dev
))
1494 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1495 struct intel_output
*intel_output
= to_intel_output(connector
);
1496 struct drm_encoder
*encoder
= &intel_output
->enc
;
1497 int crtc_mask
= 0, clone_mask
= 0;
1500 switch(intel_output
->type
) {
1501 case INTEL_OUTPUT_HDMI
:
1502 crtc_mask
= ((1 << 0)|
1504 clone_mask
= ((1 << INTEL_OUTPUT_HDMI
));
1506 case INTEL_OUTPUT_DVO
:
1507 case INTEL_OUTPUT_SDVO
:
1508 crtc_mask
= ((1 << 0)|
1510 clone_mask
= ((1 << INTEL_OUTPUT_ANALOG
) |
1511 (1 << INTEL_OUTPUT_DVO
) |
1512 (1 << INTEL_OUTPUT_SDVO
));
1514 case INTEL_OUTPUT_ANALOG
:
1515 crtc_mask
= ((1 << 0)|
1517 clone_mask
= ((1 << INTEL_OUTPUT_ANALOG
) |
1518 (1 << INTEL_OUTPUT_DVO
) |
1519 (1 << INTEL_OUTPUT_SDVO
));
1521 case INTEL_OUTPUT_LVDS
:
1522 crtc_mask
= (1 << 1);
1523 clone_mask
= (1 << INTEL_OUTPUT_LVDS
);
1525 case INTEL_OUTPUT_TVOUT
:
1526 crtc_mask
= ((1 << 0) |
1528 clone_mask
= (1 << INTEL_OUTPUT_TVOUT
);
1531 encoder
->possible_crtcs
= crtc_mask
;
1532 encoder
->possible_clones
= intel_connector_clones(dev
, clone_mask
);
1536 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
1538 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1539 struct drm_device
*dev
= fb
->dev
;
1542 intelfb_remove(dev
, fb
);
1544 drm_framebuffer_cleanup(fb
);
1545 mutex_lock(&dev
->struct_mutex
);
1546 drm_gem_object_unreference(intel_fb
->obj
);
1547 mutex_unlock(&dev
->struct_mutex
);
1552 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
1553 struct drm_file
*file_priv
,
1554 unsigned int *handle
)
1556 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1557 struct drm_gem_object
*object
= intel_fb
->obj
;
1559 return drm_gem_handle_create(file_priv
, object
, handle
);
1562 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
1563 .destroy
= intel_user_framebuffer_destroy
,
1564 .create_handle
= intel_user_framebuffer_create_handle
,
1567 int intel_framebuffer_create(struct drm_device
*dev
,
1568 struct drm_mode_fb_cmd
*mode_cmd
,
1569 struct drm_framebuffer
**fb
,
1570 struct drm_gem_object
*obj
)
1572 struct intel_framebuffer
*intel_fb
;
1575 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
1579 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
1581 DRM_ERROR("framebuffer init failed %d\n", ret
);
1585 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
1587 intel_fb
->obj
= obj
;
1589 *fb
= &intel_fb
->base
;
1595 static struct drm_framebuffer
*
1596 intel_user_framebuffer_create(struct drm_device
*dev
,
1597 struct drm_file
*filp
,
1598 struct drm_mode_fb_cmd
*mode_cmd
)
1600 struct drm_gem_object
*obj
;
1601 struct drm_framebuffer
*fb
;
1604 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
1608 ret
= intel_framebuffer_create(dev
, mode_cmd
, &fb
, obj
);
1610 mutex_lock(&dev
->struct_mutex
);
1611 drm_gem_object_unreference(obj
);
1612 mutex_unlock(&dev
->struct_mutex
);
1619 static const struct drm_mode_config_funcs intel_mode_funcs
= {
1620 .fb_create
= intel_user_framebuffer_create
,
1621 .fb_changed
= intelfb_probe
,
1624 void intel_modeset_init(struct drm_device
*dev
)
1629 drm_mode_config_init(dev
);
1631 dev
->mode_config
.min_width
= 0;
1632 dev
->mode_config
.min_height
= 0;
1634 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
1636 if (IS_I965G(dev
)) {
1637 dev
->mode_config
.max_width
= 8192;
1638 dev
->mode_config
.max_height
= 8192;
1640 dev
->mode_config
.max_width
= 2048;
1641 dev
->mode_config
.max_height
= 2048;
1644 /* set memory base */
1646 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
1648 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
1650 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
1654 DRM_DEBUG("%d display pipe%s available.\n",
1655 num_pipe
, num_pipe
> 1 ? "s" : "");
1657 for (i
= 0; i
< num_pipe
; i
++) {
1658 intel_crtc_init(dev
, i
);
1661 intel_setup_outputs(dev
);
1664 void intel_modeset_cleanup(struct drm_device
*dev
)
1666 drm_mode_config_cleanup(dev
);
1670 /* current intel driver doesn't take advantage of encoders
1671 always give back the encoder for the connector
1673 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
1675 struct intel_output
*intel_output
= to_intel_output(connector
);
1677 return &intel_output
->enc
;