2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
95 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
97 struct intel_link_m_n
*m_n
,
98 struct intel_link_m_n
*m2_n2
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
103 static void chv_prepare_pll(struct intel_crtc
*crtc
);
105 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
107 if (!connector
->mst_port
)
108 return connector
->encoder
;
110 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
119 int p2_slow
, p2_fast
;
122 typedef struct intel_limit intel_limit_t
;
124 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
129 intel_pch_rawclk(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 WARN_ON(!HAS_PCH_SPLIT(dev
));
135 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
138 static inline u32
/* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac
= {
149 .dot
= { .min
= 25000, .max
= 350000 },
150 .vco
= { .min
= 908000, .max
= 1512000 },
151 .n
= { .min
= 2, .max
= 16 },
152 .m
= { .min
= 96, .max
= 140 },
153 .m1
= { .min
= 18, .max
= 26 },
154 .m2
= { .min
= 6, .max
= 16 },
155 .p
= { .min
= 4, .max
= 128 },
156 .p1
= { .min
= 2, .max
= 33 },
157 .p2
= { .dot_limit
= 165000,
158 .p2_slow
= 4, .p2_fast
= 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo
= {
162 .dot
= { .min
= 25000, .max
= 350000 },
163 .vco
= { .min
= 908000, .max
= 1512000 },
164 .n
= { .min
= 2, .max
= 16 },
165 .m
= { .min
= 96, .max
= 140 },
166 .m1
= { .min
= 18, .max
= 26 },
167 .m2
= { .min
= 6, .max
= 16 },
168 .p
= { .min
= 4, .max
= 128 },
169 .p1
= { .min
= 2, .max
= 33 },
170 .p2
= { .dot_limit
= 165000,
171 .p2_slow
= 4, .p2_fast
= 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds
= {
175 .dot
= { .min
= 25000, .max
= 350000 },
176 .vco
= { .min
= 908000, .max
= 1512000 },
177 .n
= { .min
= 2, .max
= 16 },
178 .m
= { .min
= 96, .max
= 140 },
179 .m1
= { .min
= 18, .max
= 26 },
180 .m2
= { .min
= 6, .max
= 16 },
181 .p
= { .min
= 4, .max
= 128 },
182 .p1
= { .min
= 1, .max
= 6 },
183 .p2
= { .dot_limit
= 165000,
184 .p2_slow
= 14, .p2_fast
= 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo
= {
188 .dot
= { .min
= 20000, .max
= 400000 },
189 .vco
= { .min
= 1400000, .max
= 2800000 },
190 .n
= { .min
= 1, .max
= 6 },
191 .m
= { .min
= 70, .max
= 120 },
192 .m1
= { .min
= 8, .max
= 18 },
193 .m2
= { .min
= 3, .max
= 7 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8 },
196 .p2
= { .dot_limit
= 200000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds
= {
201 .dot
= { .min
= 20000, .max
= 400000 },
202 .vco
= { .min
= 1400000, .max
= 2800000 },
203 .n
= { .min
= 1, .max
= 6 },
204 .m
= { .min
= 70, .max
= 120 },
205 .m1
= { .min
= 8, .max
= 18 },
206 .m2
= { .min
= 3, .max
= 7 },
207 .p
= { .min
= 7, .max
= 98 },
208 .p1
= { .min
= 1, .max
= 8 },
209 .p2
= { .dot_limit
= 112000,
210 .p2_slow
= 14, .p2_fast
= 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo
= {
215 .dot
= { .min
= 25000, .max
= 270000 },
216 .vco
= { .min
= 1750000, .max
= 3500000},
217 .n
= { .min
= 1, .max
= 4 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 10, .max
= 30 },
222 .p1
= { .min
= 1, .max
= 3},
223 .p2
= { .dot_limit
= 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi
= {
230 .dot
= { .min
= 22000, .max
= 400000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 4 },
233 .m
= { .min
= 104, .max
= 138 },
234 .m1
= { .min
= 16, .max
= 23 },
235 .m2
= { .min
= 5, .max
= 11 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8},
238 .p2
= { .dot_limit
= 165000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
243 .dot
= { .min
= 20000, .max
= 115000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 14, .p2_fast
= 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
257 .dot
= { .min
= 80000, .max
= 224000 },
258 .vco
= { .min
= 1750000, .max
= 3500000 },
259 .n
= { .min
= 1, .max
= 3 },
260 .m
= { .min
= 104, .max
= 138 },
261 .m1
= { .min
= 17, .max
= 23 },
262 .m2
= { .min
= 5, .max
= 11 },
263 .p
= { .min
= 14, .max
= 42 },
264 .p1
= { .min
= 2, .max
= 6 },
265 .p2
= { .dot_limit
= 0,
266 .p2_slow
= 7, .p2_fast
= 7
270 static const intel_limit_t intel_limits_pineview_sdvo
= {
271 .dot
= { .min
= 20000, .max
= 400000},
272 .vco
= { .min
= 1700000, .max
= 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1
= { .min
= 0, .max
= 0 },
278 .m2
= { .min
= 0, .max
= 254 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 200000,
282 .p2_slow
= 10, .p2_fast
= 5 },
285 static const intel_limit_t intel_limits_pineview_lvds
= {
286 .dot
= { .min
= 20000, .max
= 400000 },
287 .vco
= { .min
= 1700000, .max
= 3500000 },
288 .n
= { .min
= 3, .max
= 6 },
289 .m
= { .min
= 2, .max
= 256 },
290 .m1
= { .min
= 0, .max
= 0 },
291 .m2
= { .min
= 0, .max
= 254 },
292 .p
= { .min
= 7, .max
= 112 },
293 .p1
= { .min
= 1, .max
= 8 },
294 .p2
= { .dot_limit
= 112000,
295 .p2_slow
= 14, .p2_fast
= 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac
= {
304 .dot
= { .min
= 25000, .max
= 350000 },
305 .vco
= { .min
= 1760000, .max
= 3510000 },
306 .n
= { .min
= 1, .max
= 5 },
307 .m
= { .min
= 79, .max
= 127 },
308 .m1
= { .min
= 12, .max
= 22 },
309 .m2
= { .min
= 5, .max
= 9 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 225000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
317 .dot
= { .min
= 25000, .max
= 350000 },
318 .vco
= { .min
= 1760000, .max
= 3510000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 79, .max
= 118 },
321 .m1
= { .min
= 12, .max
= 22 },
322 .m2
= { .min
= 5, .max
= 9 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 225000,
326 .p2_slow
= 14, .p2_fast
= 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 127 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 56 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 79, .max
= 126 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 28, .max
= 112 },
351 .p1
= { .min
= 2, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 14, .p2_fast
= 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 126 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 14, .max
= 42 },
364 .p1
= { .min
= 2, .max
= 6 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 7, .p2_fast
= 7 },
369 static const intel_limit_t intel_limits_vlv
= {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m1
= { .min
= 2, .max
= 3 },
380 .m2
= { .min
= 11, .max
= 156 },
381 .p1
= { .min
= 2, .max
= 3 },
382 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv
= {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
393 .vco
= { .min
= 4860000, .max
= 6700000 },
394 .n
= { .min
= 1, .max
= 1 },
395 .m1
= { .min
= 2, .max
= 2 },
396 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
397 .p1
= { .min
= 2, .max
= 4 },
398 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
401 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
403 clock
->m
= clock
->m1
* clock
->m2
;
404 clock
->p
= clock
->p1
* clock
->p2
;
405 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
407 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
408 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
412 * Returns whether any output on the specified pipe is of the specified type
414 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
416 struct drm_device
*dev
= crtc
->dev
;
417 struct intel_encoder
*encoder
;
419 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
420 if (encoder
->type
== type
)
426 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
429 struct drm_device
*dev
= crtc
->dev
;
430 const intel_limit_t
*limit
;
432 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
433 if (intel_is_dual_link_lvds(dev
)) {
434 if (refclk
== 100000)
435 limit
= &intel_limits_ironlake_dual_lvds_100m
;
437 limit
= &intel_limits_ironlake_dual_lvds
;
439 if (refclk
== 100000)
440 limit
= &intel_limits_ironlake_single_lvds_100m
;
442 limit
= &intel_limits_ironlake_single_lvds
;
445 limit
= &intel_limits_ironlake_dac
;
450 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
452 struct drm_device
*dev
= crtc
->dev
;
453 const intel_limit_t
*limit
;
455 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
456 if (intel_is_dual_link_lvds(dev
))
457 limit
= &intel_limits_g4x_dual_channel_lvds
;
459 limit
= &intel_limits_g4x_single_channel_lvds
;
460 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
461 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
462 limit
= &intel_limits_g4x_hdmi
;
463 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
464 limit
= &intel_limits_g4x_sdvo
;
465 } else /* The option is for other outputs */
466 limit
= &intel_limits_i9xx_sdvo
;
471 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
473 struct drm_device
*dev
= crtc
->dev
;
474 const intel_limit_t
*limit
;
476 if (HAS_PCH_SPLIT(dev
))
477 limit
= intel_ironlake_limit(crtc
, refclk
);
478 else if (IS_G4X(dev
)) {
479 limit
= intel_g4x_limit(crtc
);
480 } else if (IS_PINEVIEW(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
482 limit
= &intel_limits_pineview_lvds
;
484 limit
= &intel_limits_pineview_sdvo
;
485 } else if (IS_CHERRYVIEW(dev
)) {
486 limit
= &intel_limits_chv
;
487 } else if (IS_VALLEYVIEW(dev
)) {
488 limit
= &intel_limits_vlv
;
489 } else if (!IS_GEN2(dev
)) {
490 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
491 limit
= &intel_limits_i9xx_lvds
;
493 limit
= &intel_limits_i9xx_sdvo
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
496 limit
= &intel_limits_i8xx_lvds
;
497 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
498 limit
= &intel_limits_i8xx_dvo
;
500 limit
= &intel_limits_i8xx_dac
;
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
508 clock
->m
= clock
->m2
+ 2;
509 clock
->p
= clock
->p1
* clock
->p2
;
510 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
512 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
513 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
516 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
518 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
521 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= i9xx_dpll_compute_m(clock
);
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static void chv_clock(int refclk
, intel_clock_t
*clock
)
533 clock
->m
= clock
->m1
* clock
->m2
;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
539 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device
*dev
,
549 const intel_limit_t
*limit
,
550 const intel_clock_t
*clock
)
552 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
553 INTELPllInvalid("n out of range\n");
554 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
559 INTELPllInvalid("m1 out of range\n");
561 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
562 if (clock
->m1
<= clock
->m2
)
563 INTELPllInvalid("m1 <= m2\n");
565 if (!IS_VALLEYVIEW(dev
)) {
566 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
567 INTELPllInvalid("p out of range\n");
568 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
569 INTELPllInvalid("m out of range\n");
572 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
577 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
578 INTELPllInvalid("dot out of range\n");
584 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
585 int target
, int refclk
, intel_clock_t
*match_clock
,
586 intel_clock_t
*best_clock
)
588 struct drm_device
*dev
= crtc
->dev
;
592 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
598 if (intel_is_dual_link_lvds(dev
))
599 clock
.p2
= limit
->p2
.p2_fast
;
601 clock
.p2
= limit
->p2
.p2_slow
;
603 if (target
< limit
->p2
.dot_limit
)
604 clock
.p2
= limit
->p2
.p2_slow
;
606 clock
.p2
= limit
->p2
.p2_fast
;
609 memset(best_clock
, 0, sizeof(*best_clock
));
611 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
613 for (clock
.m2
= limit
->m2
.min
;
614 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
615 if (clock
.m2
>= clock
.m1
)
617 for (clock
.n
= limit
->n
.min
;
618 clock
.n
<= limit
->n
.max
; clock
.n
++) {
619 for (clock
.p1
= limit
->p1
.min
;
620 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
623 i9xx_clock(refclk
, &clock
);
624 if (!intel_PLL_is_valid(dev
, limit
,
628 clock
.p
!= match_clock
->p
)
631 this_err
= abs(clock
.dot
- target
);
632 if (this_err
< err
) {
641 return (err
!= target
);
645 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
646 int target
, int refclk
, intel_clock_t
*match_clock
,
647 intel_clock_t
*best_clock
)
649 struct drm_device
*dev
= crtc
->dev
;
653 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev
))
660 clock
.p2
= limit
->p2
.p2_fast
;
662 clock
.p2
= limit
->p2
.p2_slow
;
664 if (target
< limit
->p2
.dot_limit
)
665 clock
.p2
= limit
->p2
.p2_slow
;
667 clock
.p2
= limit
->p2
.p2_fast
;
670 memset(best_clock
, 0, sizeof(*best_clock
));
672 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
674 for (clock
.m2
= limit
->m2
.min
;
675 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
676 for (clock
.n
= limit
->n
.min
;
677 clock
.n
<= limit
->n
.max
; clock
.n
++) {
678 for (clock
.p1
= limit
->p1
.min
;
679 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
682 pineview_clock(refclk
, &clock
);
683 if (!intel_PLL_is_valid(dev
, limit
,
687 clock
.p
!= match_clock
->p
)
690 this_err
= abs(clock
.dot
- target
);
691 if (this_err
< err
) {
700 return (err
!= target
);
704 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 struct drm_device
*dev
= crtc
->dev
;
712 /* approximately equals target * 0.00585 */
713 int err_most
= (target
>> 8) + (target
>> 9);
716 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (intel_is_dual_link_lvds(dev
))
718 clock
.p2
= limit
->p2
.p2_fast
;
720 clock
.p2
= limit
->p2
.p2_slow
;
722 if (target
< limit
->p2
.dot_limit
)
723 clock
.p2
= limit
->p2
.p2_slow
;
725 clock
.p2
= limit
->p2
.p2_fast
;
728 memset(best_clock
, 0, sizeof(*best_clock
));
729 max_n
= limit
->n
.max
;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock
.m1
= limit
->m1
.max
;
734 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
735 for (clock
.m2
= limit
->m2
.max
;
736 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
737 for (clock
.p1
= limit
->p1
.max
;
738 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
741 i9xx_clock(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 this_err
= abs(clock
.dot
- target
);
747 if (this_err
< err_most
) {
761 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
762 int target
, int refclk
, intel_clock_t
*match_clock
,
763 intel_clock_t
*best_clock
)
765 struct drm_device
*dev
= crtc
->dev
;
767 unsigned int bestppm
= 1000000;
768 /* min update 19.2 MHz */
769 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
772 target
*= 5; /* fast clock */
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
778 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
779 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
780 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
781 clock
.p
= clock
.p1
* clock
.p2
;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
784 unsigned int ppm
, diff
;
786 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
789 vlv_clock(refclk
, &clock
);
791 if (!intel_PLL_is_valid(dev
, limit
,
795 diff
= abs(clock
.dot
- target
);
796 ppm
= div_u64(1000000ULL * diff
, target
);
798 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
804 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
818 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
819 int target
, int refclk
, intel_clock_t
*match_clock
,
820 intel_clock_t
*best_clock
)
822 struct drm_device
*dev
= crtc
->dev
;
827 memset(best_clock
, 0, sizeof(*best_clock
));
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
834 clock
.n
= 1, clock
.m1
= 2;
835 target
*= 5; /* fast clock */
837 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
838 for (clock
.p2
= limit
->p2
.p2_fast
;
839 clock
.p2
>= limit
->p2
.p2_slow
;
840 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
842 clock
.p
= clock
.p1
* clock
.p2
;
844 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
845 clock
.n
) << 22, refclk
* clock
.m1
);
847 if (m2
> INT_MAX
/clock
.m1
)
852 chv_clock(refclk
, &clock
);
854 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
857 /* based on hardware requirement, prefer bigger p
859 if (clock
.p
> best_clock
->p
) {
869 bool intel_crtc_active(struct drm_crtc
*crtc
)
871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
882 return intel_crtc
->active
&& crtc
->primary
->fb
&&
883 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
886 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
889 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
892 return intel_crtc
->config
.cpu_transcoder
;
895 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
898 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
900 frame
= I915_READ(frame_reg
);
902 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
908 * intel_wait_for_vblank - wait for vblank on a given pipe
910 * @pipe: pipe to wait for
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
918 int pipestat_reg
= PIPESTAT(pipe
);
920 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
921 g4x_wait_for_vblank(dev
, pipe
);
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
938 I915_WRITE(pipestat_reg
,
939 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg
) &
943 PIPE_VBLANK_INTERRUPT_STATUS
,
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
949 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 u32 reg
= PIPEDSL(pipe
);
957 line_mask
= DSL_LINEMASK_GEN2
;
959 line_mask
= DSL_LINEMASK_GEN3
;
961 line1
= I915_READ(reg
) & line_mask
;
963 line2
= I915_READ(reg
) & line_mask
;
965 return line1
== line2
;
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
977 * wait for the pipe register state bit to turn off
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
984 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
986 struct drm_device
*dev
= crtc
->base
.dev
;
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
989 enum pipe pipe
= crtc
->pipe
;
991 if (INTEL_INFO(dev
)->gen
>= 4) {
992 int reg
= PIPECONF(cpu_transcoder
);
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
997 WARN(1, "pipe_off wait timed out\n");
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1010 * Returns true if @port is connected, false otherwise.
1012 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1013 struct intel_digital_port
*port
)
1017 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1018 switch (port
->port
) {
1020 bit
= SDE_PORTB_HOTPLUG
;
1023 bit
= SDE_PORTC_HOTPLUG
;
1026 bit
= SDE_PORTD_HOTPLUG
;
1032 switch (port
->port
) {
1034 bit
= SDE_PORTB_HOTPLUG_CPT
;
1037 bit
= SDE_PORTC_HOTPLUG_CPT
;
1040 bit
= SDE_PORTD_HOTPLUG_CPT
;
1047 return I915_READ(SDEISR
) & bit
;
1050 static const char *state_string(bool enabled
)
1052 return enabled
? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private
*dev_priv
,
1057 enum pipe pipe
, bool state
)
1064 val
= I915_READ(reg
);
1065 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1066 WARN(cur_state
!= state
,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state
), state_string(cur_state
));
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1077 mutex_lock(&dev_priv
->dpio_lock
);
1078 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1079 mutex_unlock(&dev_priv
->dpio_lock
);
1081 cur_state
= val
& DSI_PLL_VCO_EN
;
1082 WARN(cur_state
!= state
,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state
), state_string(cur_state
));
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1089 struct intel_shared_dpll
*
1090 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1092 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1094 if (crtc
->config
.shared_dpll
< 0)
1097 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1101 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1102 struct intel_shared_dpll
*pll
,
1106 struct intel_dpll_hw_state hw_state
;
1109 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1112 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1113 WARN(cur_state
!= state
,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll
->name
, state_string(state
), state_string(cur_state
));
1118 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1119 enum pipe pipe
, bool state
)
1124 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1127 if (HAS_DDI(dev_priv
->dev
)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1130 val
= I915_READ(reg
);
1131 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1133 reg
= FDI_TX_CTL(pipe
);
1134 val
= I915_READ(reg
);
1135 cur_state
= !!(val
& FDI_TX_ENABLE
);
1137 WARN(cur_state
!= state
,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state
), state_string(cur_state
));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1151 reg
= FDI_RX_CTL(pipe
);
1152 val
= I915_READ(reg
);
1153 cur_state
= !!(val
& FDI_RX_ENABLE
);
1154 WARN(cur_state
!= state
,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state
), state_string(cur_state
));
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv
->dev
))
1175 reg
= FDI_TX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1181 enum pipe pipe
, bool state
)
1187 reg
= FDI_RX_CTL(pipe
);
1188 val
= I915_READ(reg
);
1189 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1190 WARN(cur_state
!= state
,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state
), state_string(cur_state
));
1195 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1198 struct drm_device
*dev
= dev_priv
->dev
;
1201 enum pipe panel_pipe
= PIPE_A
;
1204 if (WARN_ON(HAS_DDI(dev
)))
1207 if (HAS_PCH_SPLIT(dev
)) {
1210 pp_reg
= PCH_PP_CONTROL
;
1211 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1213 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1214 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1215 panel_pipe
= PIPE_B
;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev
)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1222 pp_reg
= PP_CONTROL
;
1223 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1224 panel_pipe
= PIPE_B
;
1227 val
= I915_READ(pp_reg
);
1228 if (!(val
& PANEL_POWER_ON
) ||
1229 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1232 WARN(panel_pipe
== pipe
&& locked
,
1233 "panel assertion failure, pipe %c regs locked\n",
1237 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1238 enum pipe pipe
, bool state
)
1240 struct drm_device
*dev
= dev_priv
->dev
;
1243 if (IS_845G(dev
) || IS_I865G(dev
))
1244 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1246 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1248 WARN(cur_state
!= state
,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1255 void assert_pipe(struct drm_i915_private
*dev_priv
,
1256 enum pipe pipe
, bool state
)
1261 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1266 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1269 if (!intel_display_power_enabled(dev_priv
,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1273 reg
= PIPECONF(cpu_transcoder
);
1274 val
= I915_READ(reg
);
1275 cur_state
= !!(val
& PIPECONF_ENABLE
);
1278 WARN(cur_state
!= state
,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1283 static void assert_plane(struct drm_i915_private
*dev_priv
,
1284 enum plane plane
, bool state
)
1290 reg
= DSPCNTR(plane
);
1291 val
= I915_READ(reg
);
1292 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1293 WARN(cur_state
!= state
,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane
), state_string(state
), state_string(cur_state
));
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1301 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1304 struct drm_device
*dev
= dev_priv
->dev
;
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev
)->gen
>= 4) {
1311 reg
= DSPCNTR(pipe
);
1312 val
= I915_READ(reg
);
1313 WARN(val
& DISPLAY_PLANE_ENABLE
,
1314 "plane %c assertion failure, should be disabled but not\n",
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv
, i
) {
1322 val
= I915_READ(reg
);
1323 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1324 DISPPLANE_SEL_PIPE_SHIFT
;
1325 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i
), pipe_name(pipe
));
1331 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1334 struct drm_device
*dev
= dev_priv
->dev
;
1338 if (IS_VALLEYVIEW(dev
)) {
1339 for_each_sprite(pipe
, sprite
) {
1340 reg
= SPCNTR(pipe
, sprite
);
1341 val
= I915_READ(reg
);
1342 WARN(val
& SP_ENABLE
,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1346 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1348 val
= I915_READ(reg
);
1349 WARN(val
& SPRITE_ENABLE
,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe
), pipe_name(pipe
));
1352 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1353 reg
= DVSCNTR(pipe
);
1354 val
= I915_READ(reg
);
1355 WARN(val
& DVS_ENABLE
,
1356 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(pipe
), pipe_name(pipe
));
1361 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1363 if (WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1364 drm_crtc_vblank_put(crtc
);
1367 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1372 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1374 val
= I915_READ(PCH_DREF_CONTROL
);
1375 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1376 DREF_SUPERSPREAD_SOURCE_MASK
));
1377 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1380 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1387 reg
= PCH_TRANSCONF(pipe
);
1388 val
= I915_READ(reg
);
1389 enabled
= !!(val
& TRANS_ENABLE
);
1391 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1395 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1396 enum pipe pipe
, u32 port_sel
, u32 val
)
1398 if ((val
& DP_PORT_EN
) == 0)
1401 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1402 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1403 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1404 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1406 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1407 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1410 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1416 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1417 enum pipe pipe
, u32 val
)
1419 if ((val
& SDVO_ENABLE
) == 0)
1422 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1423 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1425 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1426 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1429 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1435 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1436 enum pipe pipe
, u32 val
)
1438 if ((val
& LVDS_PORT_EN
) == 0)
1441 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1442 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1445 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1451 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1452 enum pipe pipe
, u32 val
)
1454 if ((val
& ADPA_DAC_ENABLE
) == 0)
1456 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1457 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1460 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1466 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1467 enum pipe pipe
, int reg
, u32 port_sel
)
1469 u32 val
= I915_READ(reg
);
1470 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1471 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1472 reg
, pipe_name(pipe
));
1474 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1475 && (val
& DP_PIPEB_SELECT
),
1476 "IBX PCH dp port still using transcoder B\n");
1479 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1480 enum pipe pipe
, int reg
)
1482 u32 val
= I915_READ(reg
);
1483 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1484 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1485 reg
, pipe_name(pipe
));
1487 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1488 && (val
& SDVO_PIPE_B_SELECT
),
1489 "IBX PCH hdmi port still using transcoder B\n");
1492 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1498 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1499 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1500 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1503 val
= I915_READ(reg
);
1504 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1505 "PCH VGA enabled on transcoder %c, should be disabled\n",
1509 val
= I915_READ(reg
);
1510 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1511 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1514 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1515 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1516 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1519 static void intel_init_dpio(struct drm_device
*dev
)
1521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 if (!IS_VALLEYVIEW(dev
))
1527 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1528 * CHV x1 PHY (DP/HDMI D)
1529 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1531 if (IS_CHERRYVIEW(dev
)) {
1532 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1533 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1535 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1539 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1541 struct drm_device
*dev
= crtc
->base
.dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 int reg
= DPLL(crtc
->pipe
);
1544 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1546 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1548 /* No really, not for ILK+ */
1549 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1551 /* PLL is protected by panel, make sure we can write it */
1552 if (IS_MOBILE(dev_priv
->dev
))
1553 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1555 I915_WRITE(reg
, dpll
);
1559 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1560 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1562 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1563 POSTING_READ(DPLL_MD(crtc
->pipe
));
1565 /* We do this three times for luck */
1566 I915_WRITE(reg
, dpll
);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg
, dpll
);
1571 udelay(150); /* wait for warmup */
1572 I915_WRITE(reg
, dpll
);
1574 udelay(150); /* wait for warmup */
1577 static void chv_enable_pll(struct intel_crtc
*crtc
)
1579 struct drm_device
*dev
= crtc
->base
.dev
;
1580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1581 int pipe
= crtc
->pipe
;
1582 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1585 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1587 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1589 mutex_lock(&dev_priv
->dpio_lock
);
1591 /* Enable back the 10bit clock to display controller */
1592 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1593 tmp
|= DPIO_DCLKP_EN
;
1594 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1597 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1602 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1604 /* Check PLL is locked */
1605 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1606 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1608 /* not sure when this should be written */
1609 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1610 POSTING_READ(DPLL_MD(pipe
));
1612 mutex_unlock(&dev_priv
->dpio_lock
);
1615 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1617 struct intel_crtc
*crtc
;
1620 for_each_intel_crtc(dev
, crtc
)
1621 count
+= crtc
->active
&&
1622 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
);
1627 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1629 struct drm_device
*dev
= crtc
->base
.dev
;
1630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1631 int reg
= DPLL(crtc
->pipe
);
1632 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1634 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1636 /* No really, not for ILK+ */
1637 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1639 /* PLL is protected by panel, make sure we can write it */
1640 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1641 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1643 /* Enable DVO 2x clock on both PLLs if necessary */
1644 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1646 * It appears to be important that we don't enable this
1647 * for the current pipe before otherwise configuring the
1648 * PLL. No idea how this should be handled if multiple
1649 * DVO outputs are enabled simultaneosly.
1651 dpll
|= DPLL_DVO_2X_MODE
;
1652 I915_WRITE(DPLL(!crtc
->pipe
),
1653 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1656 /* Wait for the clocks to stabilize. */
1660 if (INTEL_INFO(dev
)->gen
>= 4) {
1661 I915_WRITE(DPLL_MD(crtc
->pipe
),
1662 crtc
->config
.dpll_hw_state
.dpll_md
);
1664 /* The pixel multiplier can only be updated once the
1665 * DPLL is enabled and the clocks are stable.
1667 * So write it again.
1669 I915_WRITE(reg
, dpll
);
1672 /* We do this three times for luck */
1673 I915_WRITE(reg
, dpll
);
1675 udelay(150); /* wait for warmup */
1676 I915_WRITE(reg
, dpll
);
1678 udelay(150); /* wait for warmup */
1679 I915_WRITE(reg
, dpll
);
1681 udelay(150); /* wait for warmup */
1685 * i9xx_disable_pll - disable a PLL
1686 * @dev_priv: i915 private structure
1687 * @pipe: pipe PLL to disable
1689 * Disable the PLL for @pipe, making sure the pipe is off first.
1691 * Note! This is for pre-ILK only.
1693 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1695 struct drm_device
*dev
= crtc
->base
.dev
;
1696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1697 enum pipe pipe
= crtc
->pipe
;
1699 /* Disable DVO 2x clock on both PLLs if necessary */
1701 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
) &&
1702 intel_num_dvo_pipes(dev
) == 1) {
1703 I915_WRITE(DPLL(PIPE_B
),
1704 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1705 I915_WRITE(DPLL(PIPE_A
),
1706 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1709 /* Don't disable pipe or pipe PLLs if needed */
1710 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1711 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv
, pipe
);
1717 I915_WRITE(DPLL(pipe
), 0);
1718 POSTING_READ(DPLL(pipe
));
1721 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1725 /* Make sure the pipe isn't still relying on us */
1726 assert_pipe_disabled(dev_priv
, pipe
);
1729 * Leave integrated clock source and reference clock enabled for pipe B.
1730 * The latter is needed for VGA hotplug / manual detection.
1733 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1734 I915_WRITE(DPLL(pipe
), val
);
1735 POSTING_READ(DPLL(pipe
));
1739 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1741 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1744 /* Make sure the pipe isn't still relying on us */
1745 assert_pipe_disabled(dev_priv
, pipe
);
1747 /* Set PLL en = 0 */
1748 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1750 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1751 I915_WRITE(DPLL(pipe
), val
);
1752 POSTING_READ(DPLL(pipe
));
1754 mutex_lock(&dev_priv
->dpio_lock
);
1756 /* Disable 10bit clock to display controller */
1757 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1758 val
&= ~DPIO_DCLKP_EN
;
1759 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1761 /* disable left/right clock distribution */
1762 if (pipe
!= PIPE_B
) {
1763 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1764 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1765 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1767 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1768 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1769 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1772 mutex_unlock(&dev_priv
->dpio_lock
);
1775 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1776 struct intel_digital_port
*dport
)
1781 switch (dport
->port
) {
1783 port_mask
= DPLL_PORTB_READY_MASK
;
1787 port_mask
= DPLL_PORTC_READY_MASK
;
1791 port_mask
= DPLL_PORTD_READY_MASK
;
1792 dpll_reg
= DPIO_PHY_STATUS
;
1798 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1799 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1800 port_name(dport
->port
), I915_READ(dpll_reg
));
1803 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1805 struct drm_device
*dev
= crtc
->base
.dev
;
1806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1807 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1809 if (WARN_ON(pll
== NULL
))
1812 WARN_ON(!pll
->refcount
);
1813 if (pll
->active
== 0) {
1814 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1816 assert_shared_dpll_disabled(dev_priv
, pll
);
1818 pll
->mode_set(dev_priv
, pll
);
1823 * intel_enable_shared_dpll - enable PCH PLL
1824 * @dev_priv: i915 private structure
1825 * @pipe: pipe PLL to enable
1827 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1828 * drives the transcoder clock.
1830 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1832 struct drm_device
*dev
= crtc
->base
.dev
;
1833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1834 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1836 if (WARN_ON(pll
== NULL
))
1839 if (WARN_ON(pll
->refcount
== 0))
1842 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1843 pll
->name
, pll
->active
, pll
->on
,
1844 crtc
->base
.base
.id
);
1846 if (pll
->active
++) {
1848 assert_shared_dpll_enabled(dev_priv
, pll
);
1853 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1855 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1856 pll
->enable(dev_priv
, pll
);
1860 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1862 struct drm_device
*dev
= crtc
->base
.dev
;
1863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1866 /* PCH only available on ILK+ */
1867 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1868 if (WARN_ON(pll
== NULL
))
1871 if (WARN_ON(pll
->refcount
== 0))
1874 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1875 pll
->name
, pll
->active
, pll
->on
,
1876 crtc
->base
.base
.id
);
1878 if (WARN_ON(pll
->active
== 0)) {
1879 assert_shared_dpll_disabled(dev_priv
, pll
);
1883 assert_shared_dpll_enabled(dev_priv
, pll
);
1888 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1889 pll
->disable(dev_priv
, pll
);
1892 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1895 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1898 struct drm_device
*dev
= dev_priv
->dev
;
1899 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1900 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1901 uint32_t reg
, val
, pipeconf_val
;
1903 /* PCH only available on ILK+ */
1904 BUG_ON(!HAS_PCH_SPLIT(dev
));
1906 /* Make sure PCH DPLL is enabled */
1907 assert_shared_dpll_enabled(dev_priv
,
1908 intel_crtc_to_shared_dpll(intel_crtc
));
1910 /* FDI must be feeding us bits for PCH ports */
1911 assert_fdi_tx_enabled(dev_priv
, pipe
);
1912 assert_fdi_rx_enabled(dev_priv
, pipe
);
1914 if (HAS_PCH_CPT(dev
)) {
1915 /* Workaround: Set the timing override bit before enabling the
1916 * pch transcoder. */
1917 reg
= TRANS_CHICKEN2(pipe
);
1918 val
= I915_READ(reg
);
1919 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1920 I915_WRITE(reg
, val
);
1923 reg
= PCH_TRANSCONF(pipe
);
1924 val
= I915_READ(reg
);
1925 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1927 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1929 * make the BPC in transcoder be consistent with
1930 * that in pipeconf reg.
1932 val
&= ~PIPECONF_BPC_MASK
;
1933 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1936 val
&= ~TRANS_INTERLACE_MASK
;
1937 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1938 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1939 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1940 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1942 val
|= TRANS_INTERLACED
;
1944 val
|= TRANS_PROGRESSIVE
;
1946 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1947 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1948 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1951 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1952 enum transcoder cpu_transcoder
)
1954 u32 val
, pipeconf_val
;
1956 /* PCH only available on ILK+ */
1957 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1959 /* FDI must be feeding us bits for PCH ports */
1960 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1961 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1963 /* Workaround: set timing override bit. */
1964 val
= I915_READ(_TRANSA_CHICKEN2
);
1965 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1966 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1969 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1971 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1972 PIPECONF_INTERLACED_ILK
)
1973 val
|= TRANS_INTERLACED
;
1975 val
|= TRANS_PROGRESSIVE
;
1977 I915_WRITE(LPT_TRANSCONF
, val
);
1978 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1979 DRM_ERROR("Failed to enable PCH transcoder\n");
1982 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1985 struct drm_device
*dev
= dev_priv
->dev
;
1988 /* FDI relies on the transcoder */
1989 assert_fdi_tx_disabled(dev_priv
, pipe
);
1990 assert_fdi_rx_disabled(dev_priv
, pipe
);
1992 /* Ports must be off as well */
1993 assert_pch_ports_disabled(dev_priv
, pipe
);
1995 reg
= PCH_TRANSCONF(pipe
);
1996 val
= I915_READ(reg
);
1997 val
&= ~TRANS_ENABLE
;
1998 I915_WRITE(reg
, val
);
1999 /* wait for PCH transcoder off, transcoder state */
2000 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2001 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2003 if (!HAS_PCH_IBX(dev
)) {
2004 /* Workaround: Clear the timing override chicken bit again. */
2005 reg
= TRANS_CHICKEN2(pipe
);
2006 val
= I915_READ(reg
);
2007 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2008 I915_WRITE(reg
, val
);
2012 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2016 val
= I915_READ(LPT_TRANSCONF
);
2017 val
&= ~TRANS_ENABLE
;
2018 I915_WRITE(LPT_TRANSCONF
, val
);
2019 /* wait for PCH transcoder off, transcoder state */
2020 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2021 DRM_ERROR("Failed to disable PCH transcoder\n");
2023 /* Workaround: clear timing override bit. */
2024 val
= I915_READ(_TRANSA_CHICKEN2
);
2025 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2026 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2030 * intel_enable_pipe - enable a pipe, asserting requirements
2031 * @crtc: crtc responsible for the pipe
2033 * Enable @crtc's pipe, making sure that various hardware specific requirements
2034 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2036 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2038 struct drm_device
*dev
= crtc
->base
.dev
;
2039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2040 enum pipe pipe
= crtc
->pipe
;
2041 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2043 enum pipe pch_transcoder
;
2047 assert_planes_disabled(dev_priv
, pipe
);
2048 assert_cursor_disabled(dev_priv
, pipe
);
2049 assert_sprites_disabled(dev_priv
, pipe
);
2051 if (HAS_PCH_LPT(dev_priv
->dev
))
2052 pch_transcoder
= TRANSCODER_A
;
2054 pch_transcoder
= pipe
;
2057 * A pipe without a PLL won't actually be able to drive bits from
2058 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2061 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2062 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2063 assert_dsi_pll_enabled(dev_priv
);
2065 assert_pll_enabled(dev_priv
, pipe
);
2067 if (crtc
->config
.has_pch_encoder
) {
2068 /* if driving the PCH, we need FDI enabled */
2069 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2070 assert_fdi_tx_pll_enabled(dev_priv
,
2071 (enum pipe
) cpu_transcoder
);
2073 /* FIXME: assert CPU port conditions for SNB+ */
2076 reg
= PIPECONF(cpu_transcoder
);
2077 val
= I915_READ(reg
);
2078 if (val
& PIPECONF_ENABLE
) {
2079 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2080 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2084 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2089 * intel_disable_pipe - disable a pipe, asserting requirements
2090 * @crtc: crtc whose pipes is to be disabled
2092 * Disable the pipe of @crtc, making sure that various hardware
2093 * specific requirements are met, if applicable, e.g. plane
2094 * disabled, panel fitter off, etc.
2096 * Will wait until the pipe has shut down before returning.
2098 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2100 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2101 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2102 enum pipe pipe
= crtc
->pipe
;
2107 * Make sure planes won't keep trying to pump pixels to us,
2108 * or we might hang the display.
2110 assert_planes_disabled(dev_priv
, pipe
);
2111 assert_cursor_disabled(dev_priv
, pipe
);
2112 assert_sprites_disabled(dev_priv
, pipe
);
2114 reg
= PIPECONF(cpu_transcoder
);
2115 val
= I915_READ(reg
);
2116 if ((val
& PIPECONF_ENABLE
) == 0)
2120 * Double wide has implications for planes
2121 * so best keep it disabled when not needed.
2123 if (crtc
->config
.double_wide
)
2124 val
&= ~PIPECONF_DOUBLE_WIDE
;
2126 /* Don't disable pipe or pipe PLLs if needed */
2127 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2128 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2129 val
&= ~PIPECONF_ENABLE
;
2131 I915_WRITE(reg
, val
);
2132 if ((val
& PIPECONF_ENABLE
) == 0)
2133 intel_wait_for_pipe_off(crtc
);
2137 * Plane regs are double buffered, going from enabled->disabled needs a
2138 * trigger in order to latch. The display address reg provides this.
2140 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2143 struct drm_device
*dev
= dev_priv
->dev
;
2144 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2146 I915_WRITE(reg
, I915_READ(reg
));
2151 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2152 * @plane: plane to be enabled
2153 * @crtc: crtc for the plane
2155 * Enable @plane on @crtc, making sure that the pipe is running first.
2157 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2158 struct drm_crtc
*crtc
)
2160 struct drm_device
*dev
= plane
->dev
;
2161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2162 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2164 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2165 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2167 if (intel_crtc
->primary_enabled
)
2170 intel_crtc
->primary_enabled
= true;
2172 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2176 * BDW signals flip done immediately if the plane
2177 * is disabled, even if the plane enable is already
2178 * armed to occur at the next vblank :(
2180 if (IS_BROADWELL(dev
))
2181 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2185 * intel_disable_primary_hw_plane - disable the primary hardware plane
2186 * @plane: plane to be disabled
2187 * @crtc: crtc for the plane
2189 * Disable @plane on @crtc, making sure that the pipe is running first.
2191 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2192 struct drm_crtc
*crtc
)
2194 struct drm_device
*dev
= plane
->dev
;
2195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2198 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2200 if (!intel_crtc
->primary_enabled
)
2203 intel_crtc
->primary_enabled
= false;
2205 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2209 static bool need_vtd_wa(struct drm_device
*dev
)
2211 #ifdef CONFIG_INTEL_IOMMU
2212 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2218 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2222 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2223 return ALIGN(height
, tile_height
);
2227 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2228 struct drm_i915_gem_object
*obj
,
2229 struct intel_engine_cs
*pipelined
)
2231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2235 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2237 switch (obj
->tiling_mode
) {
2238 case I915_TILING_NONE
:
2239 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2240 alignment
= 128 * 1024;
2241 else if (INTEL_INFO(dev
)->gen
>= 4)
2242 alignment
= 4 * 1024;
2244 alignment
= 64 * 1024;
2247 /* pin() will align the object as required by fence */
2251 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2257 /* Note that the w/a also requires 64 PTE of padding following the
2258 * bo. We currently fill all unused PTE with the shadow page and so
2259 * we should always have valid PTE following the scanout preventing
2262 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2263 alignment
= 256 * 1024;
2266 * Global gtt pte registers are special registers which actually forward
2267 * writes to a chunk of system memory. Which means that there is no risk
2268 * that the register values disappear as soon as we call
2269 * intel_runtime_pm_put(), so it is correct to wrap only the
2270 * pin/unpin/fence and not more.
2272 intel_runtime_pm_get(dev_priv
);
2274 dev_priv
->mm
.interruptible
= false;
2275 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2277 goto err_interruptible
;
2279 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2280 * fence, whereas 965+ only requires a fence if using
2281 * framebuffer compression. For simplicity, we always install
2282 * a fence as the cost is not that onerous.
2284 ret
= i915_gem_object_get_fence(obj
);
2288 i915_gem_object_pin_fence(obj
);
2290 dev_priv
->mm
.interruptible
= true;
2291 intel_runtime_pm_put(dev_priv
);
2295 i915_gem_object_unpin_from_display_plane(obj
);
2297 dev_priv
->mm
.interruptible
= true;
2298 intel_runtime_pm_put(dev_priv
);
2302 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2304 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2306 i915_gem_object_unpin_fence(obj
);
2307 i915_gem_object_unpin_from_display_plane(obj
);
2310 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2311 * is assumed to be a power-of-two. */
2312 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2313 unsigned int tiling_mode
,
2317 if (tiling_mode
!= I915_TILING_NONE
) {
2318 unsigned int tile_rows
, tiles
;
2323 tiles
= *x
/ (512/cpp
);
2326 return tile_rows
* pitch
* 8 + tiles
* 4096;
2328 unsigned int offset
;
2330 offset
= *y
* pitch
+ *x
* cpp
;
2332 *x
= (offset
& 4095) / cpp
;
2333 return offset
& -4096;
2337 int intel_format_to_fourcc(int format
)
2340 case DISPPLANE_8BPP
:
2341 return DRM_FORMAT_C8
;
2342 case DISPPLANE_BGRX555
:
2343 return DRM_FORMAT_XRGB1555
;
2344 case DISPPLANE_BGRX565
:
2345 return DRM_FORMAT_RGB565
;
2347 case DISPPLANE_BGRX888
:
2348 return DRM_FORMAT_XRGB8888
;
2349 case DISPPLANE_RGBX888
:
2350 return DRM_FORMAT_XBGR8888
;
2351 case DISPPLANE_BGRX101010
:
2352 return DRM_FORMAT_XRGB2101010
;
2353 case DISPPLANE_RGBX101010
:
2354 return DRM_FORMAT_XBGR2101010
;
2358 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2359 struct intel_plane_config
*plane_config
)
2361 struct drm_device
*dev
= crtc
->base
.dev
;
2362 struct drm_i915_gem_object
*obj
= NULL
;
2363 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2364 u32 base
= plane_config
->base
;
2366 if (plane_config
->size
== 0)
2369 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2370 plane_config
->size
);
2374 if (plane_config
->tiled
) {
2375 obj
->tiling_mode
= I915_TILING_X
;
2376 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2379 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2380 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2381 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2382 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2384 mutex_lock(&dev
->struct_mutex
);
2386 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2388 DRM_DEBUG_KMS("intel fb init failed\n");
2392 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2393 mutex_unlock(&dev
->struct_mutex
);
2395 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2399 drm_gem_object_unreference(&obj
->base
);
2400 mutex_unlock(&dev
->struct_mutex
);
2404 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2405 struct intel_plane_config
*plane_config
)
2407 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2409 struct intel_crtc
*i
;
2410 struct drm_i915_gem_object
*obj
;
2412 if (!intel_crtc
->base
.primary
->fb
)
2415 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2418 kfree(intel_crtc
->base
.primary
->fb
);
2419 intel_crtc
->base
.primary
->fb
= NULL
;
2422 * Failed to alloc the obj, check to see if we should share
2423 * an fb with another CRTC instead
2425 for_each_crtc(dev
, c
) {
2426 i
= to_intel_crtc(c
);
2428 if (c
== &intel_crtc
->base
)
2434 obj
= intel_fb_obj(c
->primary
->fb
);
2438 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2439 drm_framebuffer_reference(c
->primary
->fb
);
2440 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2441 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2447 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2448 struct drm_framebuffer
*fb
,
2451 struct drm_device
*dev
= crtc
->dev
;
2452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2453 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2454 struct drm_i915_gem_object
*obj
;
2455 int plane
= intel_crtc
->plane
;
2456 unsigned long linear_offset
;
2458 u32 reg
= DSPCNTR(plane
);
2461 if (!intel_crtc
->primary_enabled
) {
2463 if (INTEL_INFO(dev
)->gen
>= 4)
2464 I915_WRITE(DSPSURF(plane
), 0);
2466 I915_WRITE(DSPADDR(plane
), 0);
2471 obj
= intel_fb_obj(fb
);
2472 if (WARN_ON(obj
== NULL
))
2475 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2477 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2479 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2481 if (INTEL_INFO(dev
)->gen
< 4) {
2482 if (intel_crtc
->pipe
== PIPE_B
)
2483 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2485 /* pipesrc and dspsize control the size that is scaled from,
2486 * which should always be the user's requested size.
2488 I915_WRITE(DSPSIZE(plane
),
2489 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2490 (intel_crtc
->config
.pipe_src_w
- 1));
2491 I915_WRITE(DSPPOS(plane
), 0);
2494 switch (fb
->pixel_format
) {
2496 dspcntr
|= DISPPLANE_8BPP
;
2498 case DRM_FORMAT_XRGB1555
:
2499 case DRM_FORMAT_ARGB1555
:
2500 dspcntr
|= DISPPLANE_BGRX555
;
2502 case DRM_FORMAT_RGB565
:
2503 dspcntr
|= DISPPLANE_BGRX565
;
2505 case DRM_FORMAT_XRGB8888
:
2506 case DRM_FORMAT_ARGB8888
:
2507 dspcntr
|= DISPPLANE_BGRX888
;
2509 case DRM_FORMAT_XBGR8888
:
2510 case DRM_FORMAT_ABGR8888
:
2511 dspcntr
|= DISPPLANE_RGBX888
;
2513 case DRM_FORMAT_XRGB2101010
:
2514 case DRM_FORMAT_ARGB2101010
:
2515 dspcntr
|= DISPPLANE_BGRX101010
;
2517 case DRM_FORMAT_XBGR2101010
:
2518 case DRM_FORMAT_ABGR2101010
:
2519 dspcntr
|= DISPPLANE_RGBX101010
;
2525 if (INTEL_INFO(dev
)->gen
>= 4 &&
2526 obj
->tiling_mode
!= I915_TILING_NONE
)
2527 dspcntr
|= DISPPLANE_TILED
;
2530 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2532 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2534 if (INTEL_INFO(dev
)->gen
>= 4) {
2535 intel_crtc
->dspaddr_offset
=
2536 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2539 linear_offset
-= intel_crtc
->dspaddr_offset
;
2541 intel_crtc
->dspaddr_offset
= linear_offset
;
2544 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2545 dspcntr
|= DISPPLANE_ROTATE_180
;
2547 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2548 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2550 /* Finding the last pixel of the last line of the display
2551 data and adding to linear_offset*/
2553 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2554 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2557 I915_WRITE(reg
, dspcntr
);
2559 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2560 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2562 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2563 if (INTEL_INFO(dev
)->gen
>= 4) {
2564 I915_WRITE(DSPSURF(plane
),
2565 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2566 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2567 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2569 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2573 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2574 struct drm_framebuffer
*fb
,
2577 struct drm_device
*dev
= crtc
->dev
;
2578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2579 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2580 struct drm_i915_gem_object
*obj
;
2581 int plane
= intel_crtc
->plane
;
2582 unsigned long linear_offset
;
2584 u32 reg
= DSPCNTR(plane
);
2587 if (!intel_crtc
->primary_enabled
) {
2589 I915_WRITE(DSPSURF(plane
), 0);
2594 obj
= intel_fb_obj(fb
);
2595 if (WARN_ON(obj
== NULL
))
2598 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2600 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2602 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2604 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2605 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2607 switch (fb
->pixel_format
) {
2609 dspcntr
|= DISPPLANE_8BPP
;
2611 case DRM_FORMAT_RGB565
:
2612 dspcntr
|= DISPPLANE_BGRX565
;
2614 case DRM_FORMAT_XRGB8888
:
2615 case DRM_FORMAT_ARGB8888
:
2616 dspcntr
|= DISPPLANE_BGRX888
;
2618 case DRM_FORMAT_XBGR8888
:
2619 case DRM_FORMAT_ABGR8888
:
2620 dspcntr
|= DISPPLANE_RGBX888
;
2622 case DRM_FORMAT_XRGB2101010
:
2623 case DRM_FORMAT_ARGB2101010
:
2624 dspcntr
|= DISPPLANE_BGRX101010
;
2626 case DRM_FORMAT_XBGR2101010
:
2627 case DRM_FORMAT_ABGR2101010
:
2628 dspcntr
|= DISPPLANE_RGBX101010
;
2634 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2635 dspcntr
|= DISPPLANE_TILED
;
2637 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2638 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2640 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2641 intel_crtc
->dspaddr_offset
=
2642 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2645 linear_offset
-= intel_crtc
->dspaddr_offset
;
2646 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2647 dspcntr
|= DISPPLANE_ROTATE_180
;
2649 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2650 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2651 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2653 /* Finding the last pixel of the last line of the display
2654 data and adding to linear_offset*/
2656 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2657 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2661 I915_WRITE(reg
, dspcntr
);
2663 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2664 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2666 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2667 I915_WRITE(DSPSURF(plane
),
2668 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2669 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2670 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2672 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2673 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2678 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2680 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2681 int x
, int y
, enum mode_set_atomic state
)
2683 struct drm_device
*dev
= crtc
->dev
;
2684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2686 if (dev_priv
->display
.disable_fbc
)
2687 dev_priv
->display
.disable_fbc(dev
);
2688 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2690 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2695 void intel_display_handle_reset(struct drm_device
*dev
)
2697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2698 struct drm_crtc
*crtc
;
2701 * Flips in the rings have been nuked by the reset,
2702 * so complete all pending flips so that user space
2703 * will get its events and not get stuck.
2705 * Also update the base address of all primary
2706 * planes to the the last fb to make sure we're
2707 * showing the correct fb after a reset.
2709 * Need to make two loops over the crtcs so that we
2710 * don't try to grab a crtc mutex before the
2711 * pending_flip_queue really got woken up.
2714 for_each_crtc(dev
, crtc
) {
2715 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2716 enum plane plane
= intel_crtc
->plane
;
2718 intel_prepare_page_flip(dev
, plane
);
2719 intel_finish_page_flip_plane(dev
, plane
);
2722 for_each_crtc(dev
, crtc
) {
2723 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2725 drm_modeset_lock(&crtc
->mutex
, NULL
);
2727 * FIXME: Once we have proper support for primary planes (and
2728 * disabling them without disabling the entire crtc) allow again
2729 * a NULL crtc->primary->fb.
2731 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2732 dev_priv
->display
.update_primary_plane(crtc
,
2736 drm_modeset_unlock(&crtc
->mutex
);
2741 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2743 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2744 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2745 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2748 /* Big Hammer, we also need to ensure that any pending
2749 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2750 * current scanout is retired before unpinning the old
2753 * This should only fail upon a hung GPU, in which case we
2754 * can safely continue.
2756 dev_priv
->mm
.interruptible
= false;
2757 ret
= i915_gem_object_finish_gpu(obj
);
2758 dev_priv
->mm
.interruptible
= was_interruptible
;
2763 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2765 struct drm_device
*dev
= crtc
->dev
;
2766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2768 unsigned long flags
;
2771 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2772 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2775 spin_lock_irqsave(&dev
->event_lock
, flags
);
2776 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2777 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2782 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
2784 struct drm_device
*dev
= crtc
->base
.dev
;
2785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2786 const struct drm_display_mode
*adjusted_mode
;
2792 * Update pipe size and adjust fitter if needed: the reason for this is
2793 * that in compute_mode_changes we check the native mode (not the pfit
2794 * mode) to see if we can flip rather than do a full mode set. In the
2795 * fastboot case, we'll flip, but if we don't update the pipesrc and
2796 * pfit state, we'll end up with a big fb scanned out into the wrong
2799 * To fix this properly, we need to hoist the checks up into
2800 * compute_mode_changes (or above), check the actual pfit state and
2801 * whether the platform allows pfit disable with pipe active, and only
2802 * then update the pipesrc and pfit state, even on the flip path.
2805 adjusted_mode
= &crtc
->config
.adjusted_mode
;
2807 I915_WRITE(PIPESRC(crtc
->pipe
),
2808 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2809 (adjusted_mode
->crtc_vdisplay
- 1));
2810 if (!crtc
->config
.pch_pfit
.enabled
&&
2811 (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) ||
2812 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))) {
2813 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
2814 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
2815 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
2817 crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2818 crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2822 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2823 struct drm_framebuffer
*fb
)
2825 struct drm_device
*dev
= crtc
->dev
;
2826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2827 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2828 enum pipe pipe
= intel_crtc
->pipe
;
2829 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2830 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2831 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2834 if (intel_crtc_has_pending_flip(crtc
)) {
2835 DRM_ERROR("pipe is still busy with an old pageflip\n");
2841 DRM_ERROR("No FB bound\n");
2845 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2846 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2847 plane_name(intel_crtc
->plane
),
2848 INTEL_INFO(dev
)->num_pipes
);
2852 mutex_lock(&dev
->struct_mutex
);
2853 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2855 i915_gem_track_fb(old_obj
, obj
,
2856 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2857 mutex_unlock(&dev
->struct_mutex
);
2859 DRM_ERROR("pin & fence failed\n");
2863 intel_update_pipe_size(intel_crtc
);
2865 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2867 if (intel_crtc
->active
)
2868 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2870 crtc
->primary
->fb
= fb
;
2875 if (intel_crtc
->active
&& old_fb
!= fb
)
2876 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2877 mutex_lock(&dev
->struct_mutex
);
2878 intel_unpin_fb_obj(old_obj
);
2879 mutex_unlock(&dev
->struct_mutex
);
2882 mutex_lock(&dev
->struct_mutex
);
2883 intel_update_fbc(dev
);
2884 mutex_unlock(&dev
->struct_mutex
);
2889 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2891 struct drm_device
*dev
= crtc
->dev
;
2892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2893 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2894 int pipe
= intel_crtc
->pipe
;
2897 /* enable normal train */
2898 reg
= FDI_TX_CTL(pipe
);
2899 temp
= I915_READ(reg
);
2900 if (IS_IVYBRIDGE(dev
)) {
2901 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2902 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2904 temp
&= ~FDI_LINK_TRAIN_NONE
;
2905 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2907 I915_WRITE(reg
, temp
);
2909 reg
= FDI_RX_CTL(pipe
);
2910 temp
= I915_READ(reg
);
2911 if (HAS_PCH_CPT(dev
)) {
2912 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2913 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2915 temp
&= ~FDI_LINK_TRAIN_NONE
;
2916 temp
|= FDI_LINK_TRAIN_NONE
;
2918 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2920 /* wait one idle pattern time */
2924 /* IVB wants error correction enabled */
2925 if (IS_IVYBRIDGE(dev
))
2926 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2927 FDI_FE_ERRC_ENABLE
);
2930 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2932 return crtc
->base
.enabled
&& crtc
->active
&&
2933 crtc
->config
.has_pch_encoder
;
2936 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2939 struct intel_crtc
*pipe_B_crtc
=
2940 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2941 struct intel_crtc
*pipe_C_crtc
=
2942 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2946 * When everything is off disable fdi C so that we could enable fdi B
2947 * with all lanes. Note that we don't care about enabled pipes without
2948 * an enabled pch encoder.
2950 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2951 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2952 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2953 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2955 temp
= I915_READ(SOUTH_CHICKEN1
);
2956 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2957 DRM_DEBUG_KMS("disabling fdi C rx\n");
2958 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2962 /* The FDI link training functions for ILK/Ibexpeak. */
2963 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2965 struct drm_device
*dev
= crtc
->dev
;
2966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2968 int pipe
= intel_crtc
->pipe
;
2969 u32 reg
, temp
, tries
;
2971 /* FDI needs bits from pipe first */
2972 assert_pipe_enabled(dev_priv
, pipe
);
2974 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2976 reg
= FDI_RX_IMR(pipe
);
2977 temp
= I915_READ(reg
);
2978 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2979 temp
&= ~FDI_RX_BIT_LOCK
;
2980 I915_WRITE(reg
, temp
);
2984 /* enable CPU FDI TX and PCH FDI RX */
2985 reg
= FDI_TX_CTL(pipe
);
2986 temp
= I915_READ(reg
);
2987 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2988 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2989 temp
&= ~FDI_LINK_TRAIN_NONE
;
2990 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2991 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2993 reg
= FDI_RX_CTL(pipe
);
2994 temp
= I915_READ(reg
);
2995 temp
&= ~FDI_LINK_TRAIN_NONE
;
2996 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2997 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3002 /* Ironlake workaround, enable clock pointer after FDI enable*/
3003 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3004 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3005 FDI_RX_PHASE_SYNC_POINTER_EN
);
3007 reg
= FDI_RX_IIR(pipe
);
3008 for (tries
= 0; tries
< 5; tries
++) {
3009 temp
= I915_READ(reg
);
3010 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3012 if ((temp
& FDI_RX_BIT_LOCK
)) {
3013 DRM_DEBUG_KMS("FDI train 1 done.\n");
3014 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3019 DRM_ERROR("FDI train 1 fail!\n");
3022 reg
= FDI_TX_CTL(pipe
);
3023 temp
= I915_READ(reg
);
3024 temp
&= ~FDI_LINK_TRAIN_NONE
;
3025 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3026 I915_WRITE(reg
, temp
);
3028 reg
= FDI_RX_CTL(pipe
);
3029 temp
= I915_READ(reg
);
3030 temp
&= ~FDI_LINK_TRAIN_NONE
;
3031 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3032 I915_WRITE(reg
, temp
);
3037 reg
= FDI_RX_IIR(pipe
);
3038 for (tries
= 0; tries
< 5; tries
++) {
3039 temp
= I915_READ(reg
);
3040 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3042 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3043 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3044 DRM_DEBUG_KMS("FDI train 2 done.\n");
3049 DRM_ERROR("FDI train 2 fail!\n");
3051 DRM_DEBUG_KMS("FDI train done\n");
3055 static const int snb_b_fdi_train_param
[] = {
3056 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3057 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3058 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3059 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3062 /* The FDI link training functions for SNB/Cougarpoint. */
3063 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3065 struct drm_device
*dev
= crtc
->dev
;
3066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3067 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3068 int pipe
= intel_crtc
->pipe
;
3069 u32 reg
, temp
, i
, retry
;
3071 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3073 reg
= FDI_RX_IMR(pipe
);
3074 temp
= I915_READ(reg
);
3075 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3076 temp
&= ~FDI_RX_BIT_LOCK
;
3077 I915_WRITE(reg
, temp
);
3082 /* enable CPU FDI TX and PCH FDI RX */
3083 reg
= FDI_TX_CTL(pipe
);
3084 temp
= I915_READ(reg
);
3085 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3086 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3087 temp
&= ~FDI_LINK_TRAIN_NONE
;
3088 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3089 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3091 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3092 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3094 I915_WRITE(FDI_RX_MISC(pipe
),
3095 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3097 reg
= FDI_RX_CTL(pipe
);
3098 temp
= I915_READ(reg
);
3099 if (HAS_PCH_CPT(dev
)) {
3100 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3101 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3103 temp
&= ~FDI_LINK_TRAIN_NONE
;
3104 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3106 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3111 for (i
= 0; i
< 4; i
++) {
3112 reg
= FDI_TX_CTL(pipe
);
3113 temp
= I915_READ(reg
);
3114 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3115 temp
|= snb_b_fdi_train_param
[i
];
3116 I915_WRITE(reg
, temp
);
3121 for (retry
= 0; retry
< 5; retry
++) {
3122 reg
= FDI_RX_IIR(pipe
);
3123 temp
= I915_READ(reg
);
3124 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3125 if (temp
& FDI_RX_BIT_LOCK
) {
3126 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3127 DRM_DEBUG_KMS("FDI train 1 done.\n");
3136 DRM_ERROR("FDI train 1 fail!\n");
3139 reg
= FDI_TX_CTL(pipe
);
3140 temp
= I915_READ(reg
);
3141 temp
&= ~FDI_LINK_TRAIN_NONE
;
3142 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3144 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3146 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3148 I915_WRITE(reg
, temp
);
3150 reg
= FDI_RX_CTL(pipe
);
3151 temp
= I915_READ(reg
);
3152 if (HAS_PCH_CPT(dev
)) {
3153 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3154 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3156 temp
&= ~FDI_LINK_TRAIN_NONE
;
3157 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3159 I915_WRITE(reg
, temp
);
3164 for (i
= 0; i
< 4; i
++) {
3165 reg
= FDI_TX_CTL(pipe
);
3166 temp
= I915_READ(reg
);
3167 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3168 temp
|= snb_b_fdi_train_param
[i
];
3169 I915_WRITE(reg
, temp
);
3174 for (retry
= 0; retry
< 5; retry
++) {
3175 reg
= FDI_RX_IIR(pipe
);
3176 temp
= I915_READ(reg
);
3177 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3178 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3179 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3180 DRM_DEBUG_KMS("FDI train 2 done.\n");
3189 DRM_ERROR("FDI train 2 fail!\n");
3191 DRM_DEBUG_KMS("FDI train done.\n");
3194 /* Manual link training for Ivy Bridge A0 parts */
3195 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3197 struct drm_device
*dev
= crtc
->dev
;
3198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3199 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3200 int pipe
= intel_crtc
->pipe
;
3201 u32 reg
, temp
, i
, j
;
3203 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3205 reg
= FDI_RX_IMR(pipe
);
3206 temp
= I915_READ(reg
);
3207 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3208 temp
&= ~FDI_RX_BIT_LOCK
;
3209 I915_WRITE(reg
, temp
);
3214 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3215 I915_READ(FDI_RX_IIR(pipe
)));
3217 /* Try each vswing and preemphasis setting twice before moving on */
3218 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3219 /* disable first in case we need to retry */
3220 reg
= FDI_TX_CTL(pipe
);
3221 temp
= I915_READ(reg
);
3222 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3223 temp
&= ~FDI_TX_ENABLE
;
3224 I915_WRITE(reg
, temp
);
3226 reg
= FDI_RX_CTL(pipe
);
3227 temp
= I915_READ(reg
);
3228 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3229 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3230 temp
&= ~FDI_RX_ENABLE
;
3231 I915_WRITE(reg
, temp
);
3233 /* enable CPU FDI TX and PCH FDI RX */
3234 reg
= FDI_TX_CTL(pipe
);
3235 temp
= I915_READ(reg
);
3236 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3237 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3238 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3239 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3240 temp
|= snb_b_fdi_train_param
[j
/2];
3241 temp
|= FDI_COMPOSITE_SYNC
;
3242 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3244 I915_WRITE(FDI_RX_MISC(pipe
),
3245 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3247 reg
= FDI_RX_CTL(pipe
);
3248 temp
= I915_READ(reg
);
3249 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3250 temp
|= FDI_COMPOSITE_SYNC
;
3251 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3254 udelay(1); /* should be 0.5us */
3256 for (i
= 0; i
< 4; i
++) {
3257 reg
= FDI_RX_IIR(pipe
);
3258 temp
= I915_READ(reg
);
3259 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3261 if (temp
& FDI_RX_BIT_LOCK
||
3262 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3263 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3264 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3268 udelay(1); /* should be 0.5us */
3271 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3276 reg
= FDI_TX_CTL(pipe
);
3277 temp
= I915_READ(reg
);
3278 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3279 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3280 I915_WRITE(reg
, temp
);
3282 reg
= FDI_RX_CTL(pipe
);
3283 temp
= I915_READ(reg
);
3284 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3285 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3286 I915_WRITE(reg
, temp
);
3289 udelay(2); /* should be 1.5us */
3291 for (i
= 0; i
< 4; i
++) {
3292 reg
= FDI_RX_IIR(pipe
);
3293 temp
= I915_READ(reg
);
3294 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3296 if (temp
& FDI_RX_SYMBOL_LOCK
||
3297 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3298 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3299 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3303 udelay(2); /* should be 1.5us */
3306 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3310 DRM_DEBUG_KMS("FDI train done.\n");
3313 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3315 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3317 int pipe
= intel_crtc
->pipe
;
3321 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3322 reg
= FDI_RX_CTL(pipe
);
3323 temp
= I915_READ(reg
);
3324 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3325 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3326 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3327 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3332 /* Switch from Rawclk to PCDclk */
3333 temp
= I915_READ(reg
);
3334 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3339 /* Enable CPU FDI TX PLL, always on for Ironlake */
3340 reg
= FDI_TX_CTL(pipe
);
3341 temp
= I915_READ(reg
);
3342 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3343 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3350 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3352 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3354 int pipe
= intel_crtc
->pipe
;
3357 /* Switch from PCDclk to Rawclk */
3358 reg
= FDI_RX_CTL(pipe
);
3359 temp
= I915_READ(reg
);
3360 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3362 /* Disable CPU FDI TX PLL */
3363 reg
= FDI_TX_CTL(pipe
);
3364 temp
= I915_READ(reg
);
3365 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3370 reg
= FDI_RX_CTL(pipe
);
3371 temp
= I915_READ(reg
);
3372 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3374 /* Wait for the clocks to turn off. */
3379 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3381 struct drm_device
*dev
= crtc
->dev
;
3382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3383 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3384 int pipe
= intel_crtc
->pipe
;
3387 /* disable CPU FDI tx and PCH FDI rx */
3388 reg
= FDI_TX_CTL(pipe
);
3389 temp
= I915_READ(reg
);
3390 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3393 reg
= FDI_RX_CTL(pipe
);
3394 temp
= I915_READ(reg
);
3395 temp
&= ~(0x7 << 16);
3396 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3397 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3402 /* Ironlake workaround, disable clock pointer after downing FDI */
3403 if (HAS_PCH_IBX(dev
))
3404 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3406 /* still set train pattern 1 */
3407 reg
= FDI_TX_CTL(pipe
);
3408 temp
= I915_READ(reg
);
3409 temp
&= ~FDI_LINK_TRAIN_NONE
;
3410 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3411 I915_WRITE(reg
, temp
);
3413 reg
= FDI_RX_CTL(pipe
);
3414 temp
= I915_READ(reg
);
3415 if (HAS_PCH_CPT(dev
)) {
3416 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3417 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3419 temp
&= ~FDI_LINK_TRAIN_NONE
;
3420 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3422 /* BPC in FDI rx is consistent with that in PIPECONF */
3423 temp
&= ~(0x07 << 16);
3424 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3425 I915_WRITE(reg
, temp
);
3431 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3433 struct intel_crtc
*crtc
;
3435 /* Note that we don't need to be called with mode_config.lock here
3436 * as our list of CRTC objects is static for the lifetime of the
3437 * device and so cannot disappear as we iterate. Similarly, we can
3438 * happily treat the predicates as racy, atomic checks as userspace
3439 * cannot claim and pin a new fb without at least acquring the
3440 * struct_mutex and so serialising with us.
3442 for_each_intel_crtc(dev
, crtc
) {
3443 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3446 if (crtc
->unpin_work
)
3447 intel_wait_for_vblank(dev
, crtc
->pipe
);
3455 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3457 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3458 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3460 /* ensure that the unpin work is consistent wrt ->pending. */
3462 intel_crtc
->unpin_work
= NULL
;
3465 drm_send_vblank_event(intel_crtc
->base
.dev
,
3469 drm_crtc_vblank_put(&intel_crtc
->base
);
3471 wake_up_all(&dev_priv
->pending_flip_queue
);
3472 queue_work(dev_priv
->wq
, &work
->work
);
3474 trace_i915_flip_complete(intel_crtc
->plane
,
3475 work
->pending_flip_obj
);
3478 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3480 struct drm_device
*dev
= crtc
->dev
;
3481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3483 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3484 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3485 !intel_crtc_has_pending_flip(crtc
),
3487 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3488 unsigned long flags
;
3490 spin_lock_irqsave(&dev
->event_lock
, flags
);
3491 if (intel_crtc
->unpin_work
) {
3492 WARN_ONCE(1, "Removing stuck page flip\n");
3493 page_flip_completed(intel_crtc
);
3495 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
3498 if (crtc
->primary
->fb
) {
3499 mutex_lock(&dev
->struct_mutex
);
3500 intel_finish_fb(crtc
->primary
->fb
);
3501 mutex_unlock(&dev
->struct_mutex
);
3505 /* Program iCLKIP clock to the desired frequency */
3506 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3508 struct drm_device
*dev
= crtc
->dev
;
3509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3510 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3511 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3514 mutex_lock(&dev_priv
->dpio_lock
);
3516 /* It is necessary to ungate the pixclk gate prior to programming
3517 * the divisors, and gate it back when it is done.
3519 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3521 /* Disable SSCCTL */
3522 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3523 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3527 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3528 if (clock
== 20000) {
3533 /* The iCLK virtual clock root frequency is in MHz,
3534 * but the adjusted_mode->crtc_clock in in KHz. To get the
3535 * divisors, it is necessary to divide one by another, so we
3536 * convert the virtual clock precision to KHz here for higher
3539 u32 iclk_virtual_root_freq
= 172800 * 1000;
3540 u32 iclk_pi_range
= 64;
3541 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3543 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3544 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3545 pi_value
= desired_divisor
% iclk_pi_range
;
3548 divsel
= msb_divisor_value
- 2;
3549 phaseinc
= pi_value
;
3552 /* This should not happen with any sane values */
3553 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3554 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3555 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3556 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3558 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3565 /* Program SSCDIVINTPHASE6 */
3566 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3567 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3568 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3569 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3570 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3571 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3572 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3573 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3575 /* Program SSCAUXDIV */
3576 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3577 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3578 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3579 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3581 /* Enable modulator and associated divider */
3582 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3583 temp
&= ~SBI_SSCCTL_DISABLE
;
3584 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3586 /* Wait for initialization time */
3589 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3591 mutex_unlock(&dev_priv
->dpio_lock
);
3594 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3595 enum pipe pch_transcoder
)
3597 struct drm_device
*dev
= crtc
->base
.dev
;
3598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3599 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3601 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3602 I915_READ(HTOTAL(cpu_transcoder
)));
3603 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3604 I915_READ(HBLANK(cpu_transcoder
)));
3605 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3606 I915_READ(HSYNC(cpu_transcoder
)));
3608 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3609 I915_READ(VTOTAL(cpu_transcoder
)));
3610 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3611 I915_READ(VBLANK(cpu_transcoder
)));
3612 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3613 I915_READ(VSYNC(cpu_transcoder
)));
3614 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3615 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3618 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3623 temp
= I915_READ(SOUTH_CHICKEN1
);
3624 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3627 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3628 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3630 temp
|= FDI_BC_BIFURCATION_SELECT
;
3631 DRM_DEBUG_KMS("enabling fdi C rx\n");
3632 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3633 POSTING_READ(SOUTH_CHICKEN1
);
3636 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3638 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3641 switch (intel_crtc
->pipe
) {
3645 if (intel_crtc
->config
.fdi_lanes
> 2)
3646 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3648 cpt_enable_fdi_bc_bifurcation(dev
);
3652 cpt_enable_fdi_bc_bifurcation(dev
);
3661 * Enable PCH resources required for PCH ports:
3663 * - FDI training & RX/TX
3664 * - update transcoder timings
3665 * - DP transcoding bits
3668 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3670 struct drm_device
*dev
= crtc
->dev
;
3671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3673 int pipe
= intel_crtc
->pipe
;
3676 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3678 if (IS_IVYBRIDGE(dev
))
3679 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3681 /* Write the TU size bits before fdi link training, so that error
3682 * detection works. */
3683 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3684 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3686 /* For PCH output, training FDI link */
3687 dev_priv
->display
.fdi_link_train(crtc
);
3689 /* We need to program the right clock selection before writing the pixel
3690 * mutliplier into the DPLL. */
3691 if (HAS_PCH_CPT(dev
)) {
3694 temp
= I915_READ(PCH_DPLL_SEL
);
3695 temp
|= TRANS_DPLL_ENABLE(pipe
);
3696 sel
= TRANS_DPLLB_SEL(pipe
);
3697 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3701 I915_WRITE(PCH_DPLL_SEL
, temp
);
3704 /* XXX: pch pll's can be enabled any time before we enable the PCH
3705 * transcoder, and we actually should do this to not upset any PCH
3706 * transcoder that already use the clock when we share it.
3708 * Note that enable_shared_dpll tries to do the right thing, but
3709 * get_shared_dpll unconditionally resets the pll - we need that to have
3710 * the right LVDS enable sequence. */
3711 intel_enable_shared_dpll(intel_crtc
);
3713 /* set transcoder timing, panel must allow it */
3714 assert_panel_unlocked(dev_priv
, pipe
);
3715 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3717 intel_fdi_normal_train(crtc
);
3719 /* For PCH DP, enable TRANS_DP_CTL */
3720 if (HAS_PCH_CPT(dev
) &&
3721 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3722 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3723 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3724 reg
= TRANS_DP_CTL(pipe
);
3725 temp
= I915_READ(reg
);
3726 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3727 TRANS_DP_SYNC_MASK
|
3729 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3730 TRANS_DP_ENH_FRAMING
);
3731 temp
|= bpc
<< 9; /* same format but at 11:9 */
3733 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3734 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3735 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3736 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3738 switch (intel_trans_dp_port_sel(crtc
)) {
3740 temp
|= TRANS_DP_PORT_SEL_B
;
3743 temp
|= TRANS_DP_PORT_SEL_C
;
3746 temp
|= TRANS_DP_PORT_SEL_D
;
3752 I915_WRITE(reg
, temp
);
3755 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3758 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3760 struct drm_device
*dev
= crtc
->dev
;
3761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3762 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3763 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3765 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3767 lpt_program_iclkip(crtc
);
3769 /* Set transcoder timing. */
3770 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3772 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3775 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3777 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3782 if (pll
->refcount
== 0) {
3783 WARN(1, "bad %s refcount\n", pll
->name
);
3787 if (--pll
->refcount
== 0) {
3789 WARN_ON(pll
->active
);
3792 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3795 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3797 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3798 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3799 enum intel_dpll_id i
;
3802 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3803 crtc
->base
.base
.id
, pll
->name
);
3804 intel_put_shared_dpll(crtc
);
3807 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3808 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3809 i
= (enum intel_dpll_id
) crtc
->pipe
;
3810 pll
= &dev_priv
->shared_dplls
[i
];
3812 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3813 crtc
->base
.base
.id
, pll
->name
);
3815 WARN_ON(pll
->refcount
);
3820 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3821 pll
= &dev_priv
->shared_dplls
[i
];
3823 /* Only want to check enabled timings first */
3824 if (pll
->refcount
== 0)
3827 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3828 sizeof(pll
->hw_state
)) == 0) {
3829 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3831 pll
->name
, pll
->refcount
, pll
->active
);
3837 /* Ok no matching timings, maybe there's a free one? */
3838 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3839 pll
= &dev_priv
->shared_dplls
[i
];
3840 if (pll
->refcount
== 0) {
3841 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3842 crtc
->base
.base
.id
, pll
->name
);
3850 if (pll
->refcount
== 0)
3851 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3853 crtc
->config
.shared_dpll
= i
;
3854 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3855 pipe_name(crtc
->pipe
));
3862 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3865 int dslreg
= PIPEDSL(pipe
);
3868 temp
= I915_READ(dslreg
);
3870 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3871 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3872 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3876 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3878 struct drm_device
*dev
= crtc
->base
.dev
;
3879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3880 int pipe
= crtc
->pipe
;
3882 if (crtc
->config
.pch_pfit
.enabled
) {
3883 /* Force use of hard-coded filter coefficients
3884 * as some pre-programmed values are broken,
3887 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3888 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3889 PF_PIPE_SEL_IVB(pipe
));
3891 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3892 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3893 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3897 static void intel_enable_planes(struct drm_crtc
*crtc
)
3899 struct drm_device
*dev
= crtc
->dev
;
3900 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3901 struct drm_plane
*plane
;
3902 struct intel_plane
*intel_plane
;
3904 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3905 intel_plane
= to_intel_plane(plane
);
3906 if (intel_plane
->pipe
== pipe
)
3907 intel_plane_restore(&intel_plane
->base
);
3911 static void intel_disable_planes(struct drm_crtc
*crtc
)
3913 struct drm_device
*dev
= crtc
->dev
;
3914 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3915 struct drm_plane
*plane
;
3916 struct intel_plane
*intel_plane
;
3918 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3919 intel_plane
= to_intel_plane(plane
);
3920 if (intel_plane
->pipe
== pipe
)
3921 intel_plane_disable(&intel_plane
->base
);
3925 void hsw_enable_ips(struct intel_crtc
*crtc
)
3927 struct drm_device
*dev
= crtc
->base
.dev
;
3928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3930 if (!crtc
->config
.ips_enabled
)
3933 /* We can only enable IPS after we enable a plane and wait for a vblank */
3934 intel_wait_for_vblank(dev
, crtc
->pipe
);
3936 assert_plane_enabled(dev_priv
, crtc
->plane
);
3937 if (IS_BROADWELL(dev
)) {
3938 mutex_lock(&dev_priv
->rps
.hw_lock
);
3939 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3940 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3941 /* Quoting Art Runyan: "its not safe to expect any particular
3942 * value in IPS_CTL bit 31 after enabling IPS through the
3943 * mailbox." Moreover, the mailbox may return a bogus state,
3944 * so we need to just enable it and continue on.
3947 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3948 /* The bit only becomes 1 in the next vblank, so this wait here
3949 * is essentially intel_wait_for_vblank. If we don't have this
3950 * and don't wait for vblanks until the end of crtc_enable, then
3951 * the HW state readout code will complain that the expected
3952 * IPS_CTL value is not the one we read. */
3953 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3954 DRM_ERROR("Timed out waiting for IPS enable\n");
3958 void hsw_disable_ips(struct intel_crtc
*crtc
)
3960 struct drm_device
*dev
= crtc
->base
.dev
;
3961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3963 if (!crtc
->config
.ips_enabled
)
3966 assert_plane_enabled(dev_priv
, crtc
->plane
);
3967 if (IS_BROADWELL(dev
)) {
3968 mutex_lock(&dev_priv
->rps
.hw_lock
);
3969 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3970 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3971 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3972 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3973 DRM_ERROR("Timed out waiting for IPS disable\n");
3975 I915_WRITE(IPS_CTL
, 0);
3976 POSTING_READ(IPS_CTL
);
3979 /* We need to wait for a vblank before we can disable the plane. */
3980 intel_wait_for_vblank(dev
, crtc
->pipe
);
3983 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3984 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3986 struct drm_device
*dev
= crtc
->dev
;
3987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3989 enum pipe pipe
= intel_crtc
->pipe
;
3990 int palreg
= PALETTE(pipe
);
3992 bool reenable_ips
= false;
3994 /* The clocks have to be on to load the palette. */
3995 if (!crtc
->enabled
|| !intel_crtc
->active
)
3998 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3999 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
4000 assert_dsi_pll_enabled(dev_priv
);
4002 assert_pll_enabled(dev_priv
, pipe
);
4005 /* use legacy palette for Ironlake */
4006 if (!HAS_GMCH_DISPLAY(dev
))
4007 palreg
= LGC_PALETTE(pipe
);
4009 /* Workaround : Do not read or write the pipe palette/gamma data while
4010 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4012 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
4013 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4014 GAMMA_MODE_MODE_SPLIT
)) {
4015 hsw_disable_ips(intel_crtc
);
4016 reenable_ips
= true;
4019 for (i
= 0; i
< 256; i
++) {
4020 I915_WRITE(palreg
+ 4 * i
,
4021 (intel_crtc
->lut_r
[i
] << 16) |
4022 (intel_crtc
->lut_g
[i
] << 8) |
4023 intel_crtc
->lut_b
[i
]);
4027 hsw_enable_ips(intel_crtc
);
4030 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4032 if (!enable
&& intel_crtc
->overlay
) {
4033 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4036 mutex_lock(&dev
->struct_mutex
);
4037 dev_priv
->mm
.interruptible
= false;
4038 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4039 dev_priv
->mm
.interruptible
= true;
4040 mutex_unlock(&dev
->struct_mutex
);
4043 /* Let userspace switch the overlay on again. In most cases userspace
4044 * has to recompute where to put it anyway.
4048 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4050 struct drm_device
*dev
= crtc
->dev
;
4051 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4052 int pipe
= intel_crtc
->pipe
;
4054 assert_vblank_disabled(crtc
);
4056 drm_vblank_on(dev
, pipe
);
4058 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4059 intel_enable_planes(crtc
);
4060 intel_crtc_update_cursor(crtc
, true);
4061 intel_crtc_dpms_overlay(intel_crtc
, true);
4063 hsw_enable_ips(intel_crtc
);
4065 mutex_lock(&dev
->struct_mutex
);
4066 intel_update_fbc(dev
);
4067 mutex_unlock(&dev
->struct_mutex
);
4070 * FIXME: Once we grow proper nuclear flip support out of this we need
4071 * to compute the mask of flip planes precisely. For the time being
4072 * consider this a flip from a NULL plane.
4074 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4077 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4079 struct drm_device
*dev
= crtc
->dev
;
4080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4081 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4082 int pipe
= intel_crtc
->pipe
;
4083 int plane
= intel_crtc
->plane
;
4085 intel_crtc_wait_for_pending_flips(crtc
);
4087 if (dev_priv
->fbc
.plane
== plane
)
4088 intel_disable_fbc(dev
);
4090 hsw_disable_ips(intel_crtc
);
4092 intel_crtc_dpms_overlay(intel_crtc
, false);
4093 intel_crtc_update_cursor(crtc
, false);
4094 intel_disable_planes(crtc
);
4095 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4098 * FIXME: Once we grow proper nuclear flip support out of this we need
4099 * to compute the mask of flip planes precisely. For the time being
4100 * consider this a flip to a NULL plane.
4102 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4104 drm_vblank_off(dev
, pipe
);
4106 assert_vblank_disabled(crtc
);
4109 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4111 struct drm_device
*dev
= crtc
->dev
;
4112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4113 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4114 struct intel_encoder
*encoder
;
4115 int pipe
= intel_crtc
->pipe
;
4117 WARN_ON(!crtc
->enabled
);
4119 if (intel_crtc
->active
)
4122 if (intel_crtc
->config
.has_pch_encoder
)
4123 intel_prepare_shared_dpll(intel_crtc
);
4125 if (intel_crtc
->config
.has_dp_encoder
)
4126 intel_dp_set_m_n(intel_crtc
);
4128 intel_set_pipe_timings(intel_crtc
);
4130 if (intel_crtc
->config
.has_pch_encoder
) {
4131 intel_cpu_transcoder_set_m_n(intel_crtc
,
4132 &intel_crtc
->config
.fdi_m_n
, NULL
);
4135 ironlake_set_pipeconf(crtc
);
4137 intel_crtc
->active
= true;
4139 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4140 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4142 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4143 if (encoder
->pre_enable
)
4144 encoder
->pre_enable(encoder
);
4146 if (intel_crtc
->config
.has_pch_encoder
) {
4147 /* Note: FDI PLL enabling _must_ be done before we enable the
4148 * cpu pipes, hence this is separate from all the other fdi/pch
4150 ironlake_fdi_pll_enable(intel_crtc
);
4152 assert_fdi_tx_disabled(dev_priv
, pipe
);
4153 assert_fdi_rx_disabled(dev_priv
, pipe
);
4156 ironlake_pfit_enable(intel_crtc
);
4159 * On ILK+ LUT must be loaded before the pipe is running but with
4162 intel_crtc_load_lut(crtc
);
4164 intel_update_watermarks(crtc
);
4165 intel_enable_pipe(intel_crtc
);
4167 if (intel_crtc
->config
.has_pch_encoder
)
4168 ironlake_pch_enable(crtc
);
4170 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4171 encoder
->enable(encoder
);
4173 if (HAS_PCH_CPT(dev
))
4174 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4176 intel_crtc_enable_planes(crtc
);
4179 /* IPS only exists on ULT machines and is tied to pipe A. */
4180 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4182 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4186 * This implements the workaround described in the "notes" section of the mode
4187 * set sequence documentation. When going from no pipes or single pipe to
4188 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4189 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4191 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4193 struct drm_device
*dev
= crtc
->base
.dev
;
4194 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4196 /* We want to get the other_active_crtc only if there's only 1 other
4198 for_each_intel_crtc(dev
, crtc_it
) {
4199 if (!crtc_it
->active
|| crtc_it
== crtc
)
4202 if (other_active_crtc
)
4205 other_active_crtc
= crtc_it
;
4207 if (!other_active_crtc
)
4210 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4211 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4214 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4216 struct drm_device
*dev
= crtc
->dev
;
4217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4218 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4219 struct intel_encoder
*encoder
;
4220 int pipe
= intel_crtc
->pipe
;
4222 WARN_ON(!crtc
->enabled
);
4224 if (intel_crtc
->active
)
4227 if (intel_crtc_to_shared_dpll(intel_crtc
))
4228 intel_enable_shared_dpll(intel_crtc
);
4230 if (intel_crtc
->config
.has_dp_encoder
)
4231 intel_dp_set_m_n(intel_crtc
);
4233 intel_set_pipe_timings(intel_crtc
);
4235 if (intel_crtc
->config
.has_pch_encoder
) {
4236 intel_cpu_transcoder_set_m_n(intel_crtc
,
4237 &intel_crtc
->config
.fdi_m_n
, NULL
);
4240 haswell_set_pipeconf(crtc
);
4242 intel_set_pipe_csc(crtc
);
4244 intel_crtc
->active
= true;
4246 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4247 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4248 if (encoder
->pre_enable
)
4249 encoder
->pre_enable(encoder
);
4251 if (intel_crtc
->config
.has_pch_encoder
) {
4252 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4253 dev_priv
->display
.fdi_link_train(crtc
);
4256 intel_ddi_enable_pipe_clock(intel_crtc
);
4258 ironlake_pfit_enable(intel_crtc
);
4261 * On ILK+ LUT must be loaded before the pipe is running but with
4264 intel_crtc_load_lut(crtc
);
4266 intel_ddi_set_pipe_settings(crtc
);
4267 intel_ddi_enable_transcoder_func(crtc
);
4269 intel_update_watermarks(crtc
);
4270 intel_enable_pipe(intel_crtc
);
4272 if (intel_crtc
->config
.has_pch_encoder
)
4273 lpt_pch_enable(crtc
);
4275 if (intel_crtc
->config
.dp_encoder_is_mst
)
4276 intel_ddi_set_vc_payload_alloc(crtc
, true);
4278 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4279 encoder
->enable(encoder
);
4280 intel_opregion_notify_encoder(encoder
, true);
4283 /* If we change the relative order between pipe/planes enabling, we need
4284 * to change the workaround. */
4285 haswell_mode_set_planes_workaround(intel_crtc
);
4286 intel_crtc_enable_planes(crtc
);
4289 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4291 struct drm_device
*dev
= crtc
->base
.dev
;
4292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4293 int pipe
= crtc
->pipe
;
4295 /* To avoid upsetting the power well on haswell only disable the pfit if
4296 * it's in use. The hw state code will make sure we get this right. */
4297 if (crtc
->config
.pch_pfit
.enabled
) {
4298 I915_WRITE(PF_CTL(pipe
), 0);
4299 I915_WRITE(PF_WIN_POS(pipe
), 0);
4300 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4304 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4306 struct drm_device
*dev
= crtc
->dev
;
4307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4309 struct intel_encoder
*encoder
;
4310 int pipe
= intel_crtc
->pipe
;
4313 if (!intel_crtc
->active
)
4316 intel_crtc_disable_planes(crtc
);
4318 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4319 encoder
->disable(encoder
);
4321 if (intel_crtc
->config
.has_pch_encoder
)
4322 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4324 intel_disable_pipe(intel_crtc
);
4326 ironlake_pfit_disable(intel_crtc
);
4328 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4329 if (encoder
->post_disable
)
4330 encoder
->post_disable(encoder
);
4332 if (intel_crtc
->config
.has_pch_encoder
) {
4333 ironlake_fdi_disable(crtc
);
4335 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4336 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4338 if (HAS_PCH_CPT(dev
)) {
4339 /* disable TRANS_DP_CTL */
4340 reg
= TRANS_DP_CTL(pipe
);
4341 temp
= I915_READ(reg
);
4342 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4343 TRANS_DP_PORT_SEL_MASK
);
4344 temp
|= TRANS_DP_PORT_SEL_NONE
;
4345 I915_WRITE(reg
, temp
);
4347 /* disable DPLL_SEL */
4348 temp
= I915_READ(PCH_DPLL_SEL
);
4349 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4350 I915_WRITE(PCH_DPLL_SEL
, temp
);
4353 /* disable PCH DPLL */
4354 intel_disable_shared_dpll(intel_crtc
);
4356 ironlake_fdi_pll_disable(intel_crtc
);
4359 intel_crtc
->active
= false;
4360 intel_update_watermarks(crtc
);
4362 mutex_lock(&dev
->struct_mutex
);
4363 intel_update_fbc(dev
);
4364 mutex_unlock(&dev
->struct_mutex
);
4367 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4369 struct drm_device
*dev
= crtc
->dev
;
4370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4372 struct intel_encoder
*encoder
;
4373 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4375 if (!intel_crtc
->active
)
4378 intel_crtc_disable_planes(crtc
);
4380 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4381 intel_opregion_notify_encoder(encoder
, false);
4382 encoder
->disable(encoder
);
4385 if (intel_crtc
->config
.has_pch_encoder
)
4386 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4387 intel_disable_pipe(intel_crtc
);
4389 if (intel_crtc
->config
.dp_encoder_is_mst
)
4390 intel_ddi_set_vc_payload_alloc(crtc
, false);
4392 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4394 ironlake_pfit_disable(intel_crtc
);
4396 intel_ddi_disable_pipe_clock(intel_crtc
);
4398 if (intel_crtc
->config
.has_pch_encoder
) {
4399 lpt_disable_pch_transcoder(dev_priv
);
4400 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4401 intel_ddi_fdi_disable(crtc
);
4404 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4405 if (encoder
->post_disable
)
4406 encoder
->post_disable(encoder
);
4408 intel_crtc
->active
= false;
4409 intel_update_watermarks(crtc
);
4411 mutex_lock(&dev
->struct_mutex
);
4412 intel_update_fbc(dev
);
4413 mutex_unlock(&dev
->struct_mutex
);
4415 if (intel_crtc_to_shared_dpll(intel_crtc
))
4416 intel_disable_shared_dpll(intel_crtc
);
4419 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4421 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4422 intel_put_shared_dpll(intel_crtc
);
4426 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4428 struct drm_device
*dev
= crtc
->base
.dev
;
4429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4430 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4432 if (!crtc
->config
.gmch_pfit
.control
)
4436 * The panel fitter should only be adjusted whilst the pipe is disabled,
4437 * according to register description and PRM.
4439 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4440 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4442 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4443 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4445 /* Border color in case we don't scale up to the full screen. Black by
4446 * default, change to something else for debugging. */
4447 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4450 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4454 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4456 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4458 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4460 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4463 return POWER_DOMAIN_PORT_OTHER
;
4467 #define for_each_power_domain(domain, mask) \
4468 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4469 if ((1 << (domain)) & (mask))
4471 enum intel_display_power_domain
4472 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4474 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4475 struct intel_digital_port
*intel_dig_port
;
4477 switch (intel_encoder
->type
) {
4478 case INTEL_OUTPUT_UNKNOWN
:
4479 /* Only DDI platforms should ever use this output type */
4480 WARN_ON_ONCE(!HAS_DDI(dev
));
4481 case INTEL_OUTPUT_DISPLAYPORT
:
4482 case INTEL_OUTPUT_HDMI
:
4483 case INTEL_OUTPUT_EDP
:
4484 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4485 return port_to_power_domain(intel_dig_port
->port
);
4486 case INTEL_OUTPUT_DP_MST
:
4487 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4488 return port_to_power_domain(intel_dig_port
->port
);
4489 case INTEL_OUTPUT_ANALOG
:
4490 return POWER_DOMAIN_PORT_CRT
;
4491 case INTEL_OUTPUT_DSI
:
4492 return POWER_DOMAIN_PORT_DSI
;
4494 return POWER_DOMAIN_PORT_OTHER
;
4498 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4500 struct drm_device
*dev
= crtc
->dev
;
4501 struct intel_encoder
*intel_encoder
;
4502 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4503 enum pipe pipe
= intel_crtc
->pipe
;
4505 enum transcoder transcoder
;
4507 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4509 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4510 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4511 if (intel_crtc
->config
.pch_pfit
.enabled
||
4512 intel_crtc
->config
.pch_pfit
.force_thru
)
4513 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4515 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4516 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4521 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4524 if (dev_priv
->power_domains
.init_power_on
== enable
)
4528 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4530 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4532 dev_priv
->power_domains
.init_power_on
= enable
;
4535 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4538 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4539 struct intel_crtc
*crtc
;
4542 * First get all needed power domains, then put all unneeded, to avoid
4543 * any unnecessary toggling of the power wells.
4545 for_each_intel_crtc(dev
, crtc
) {
4546 enum intel_display_power_domain domain
;
4548 if (!crtc
->base
.enabled
)
4551 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4553 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4554 intel_display_power_get(dev_priv
, domain
);
4557 for_each_intel_crtc(dev
, crtc
) {
4558 enum intel_display_power_domain domain
;
4560 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4561 intel_display_power_put(dev_priv
, domain
);
4563 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4566 intel_display_set_init_power(dev_priv
, false);
4569 /* returns HPLL frequency in kHz */
4570 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4572 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4574 /* Obtain SKU information */
4575 mutex_lock(&dev_priv
->dpio_lock
);
4576 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4577 CCK_FUSE_HPLL_FREQ_MASK
;
4578 mutex_unlock(&dev_priv
->dpio_lock
);
4580 return vco_freq
[hpll_freq
] * 1000;
4583 static void vlv_update_cdclk(struct drm_device
*dev
)
4585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4587 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4588 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4589 dev_priv
->vlv_cdclk_freq
);
4592 * Program the gmbus_freq based on the cdclk frequency.
4593 * BSpec erroneously claims we should aim for 4MHz, but
4594 * in fact 1MHz is the correct frequency.
4596 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4599 /* Adjust CDclk dividers to allow high res or save power if possible */
4600 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4605 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4607 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4609 else if (cdclk
== 266667)
4614 mutex_lock(&dev_priv
->rps
.hw_lock
);
4615 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4616 val
&= ~DSPFREQGUAR_MASK
;
4617 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4618 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4619 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4620 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4622 DRM_ERROR("timed out waiting for CDclk change\n");
4624 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4626 if (cdclk
== 400000) {
4629 vco
= valleyview_get_vco(dev_priv
);
4630 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4632 mutex_lock(&dev_priv
->dpio_lock
);
4633 /* adjust cdclk divider */
4634 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4635 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4637 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4639 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4640 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4642 DRM_ERROR("timed out waiting for CDclk change\n");
4643 mutex_unlock(&dev_priv
->dpio_lock
);
4646 mutex_lock(&dev_priv
->dpio_lock
);
4647 /* adjust self-refresh exit latency value */
4648 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4652 * For high bandwidth configs, we set a higher latency in the bunit
4653 * so that the core display fetch happens in time to avoid underruns.
4655 if (cdclk
== 400000)
4656 val
|= 4500 / 250; /* 4.5 usec */
4658 val
|= 3000 / 250; /* 3.0 usec */
4659 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4660 mutex_unlock(&dev_priv
->dpio_lock
);
4662 vlv_update_cdclk(dev
);
4665 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4670 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4691 mutex_lock(&dev_priv
->rps
.hw_lock
);
4692 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4693 val
&= ~DSPFREQGUAR_MASK_CHV
;
4694 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4695 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4696 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4697 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4699 DRM_ERROR("timed out waiting for CDclk change\n");
4701 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4703 vlv_update_cdclk(dev
);
4706 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4709 int vco
= valleyview_get_vco(dev_priv
);
4710 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4712 /* FIXME: Punit isn't quite ready yet */
4713 if (IS_CHERRYVIEW(dev_priv
->dev
))
4717 * Really only a few cases to deal with, as only 4 CDclks are supported:
4720 * 320/333MHz (depends on HPLL freq)
4722 * So we check to see whether we're above 90% of the lower bin and
4725 * We seem to get an unstable or solid color picture at 200MHz.
4726 * Not sure what's wrong. For now use 200MHz only when all pipes
4729 if (max_pixclk
> freq_320
*9/10)
4731 else if (max_pixclk
> 266667*9/10)
4733 else if (max_pixclk
> 0)
4739 /* compute the max pixel clock for new configuration */
4740 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4742 struct drm_device
*dev
= dev_priv
->dev
;
4743 struct intel_crtc
*intel_crtc
;
4746 for_each_intel_crtc(dev
, intel_crtc
) {
4747 if (intel_crtc
->new_enabled
)
4748 max_pixclk
= max(max_pixclk
,
4749 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4755 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4756 unsigned *prepare_pipes
)
4758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4759 struct intel_crtc
*intel_crtc
;
4760 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4762 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4763 dev_priv
->vlv_cdclk_freq
)
4766 /* disable/enable all currently active pipes while we change cdclk */
4767 for_each_intel_crtc(dev
, intel_crtc
)
4768 if (intel_crtc
->base
.enabled
)
4769 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4772 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4775 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4776 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4778 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4779 if (IS_CHERRYVIEW(dev
))
4780 cherryview_set_cdclk(dev
, req_cdclk
);
4782 valleyview_set_cdclk(dev
, req_cdclk
);
4785 modeset_update_crtc_power_domains(dev
);
4788 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4790 struct drm_device
*dev
= crtc
->dev
;
4791 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4792 struct intel_encoder
*encoder
;
4793 int pipe
= intel_crtc
->pipe
;
4796 WARN_ON(!crtc
->enabled
);
4798 if (intel_crtc
->active
)
4801 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4804 if (IS_CHERRYVIEW(dev
))
4805 chv_prepare_pll(intel_crtc
);
4807 vlv_prepare_pll(intel_crtc
);
4810 if (intel_crtc
->config
.has_dp_encoder
)
4811 intel_dp_set_m_n(intel_crtc
);
4813 intel_set_pipe_timings(intel_crtc
);
4815 i9xx_set_pipeconf(intel_crtc
);
4817 intel_crtc
->active
= true;
4819 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4821 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4822 if (encoder
->pre_pll_enable
)
4823 encoder
->pre_pll_enable(encoder
);
4826 if (IS_CHERRYVIEW(dev
))
4827 chv_enable_pll(intel_crtc
);
4829 vlv_enable_pll(intel_crtc
);
4832 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4833 if (encoder
->pre_enable
)
4834 encoder
->pre_enable(encoder
);
4836 i9xx_pfit_enable(intel_crtc
);
4838 intel_crtc_load_lut(crtc
);
4840 intel_update_watermarks(crtc
);
4841 intel_enable_pipe(intel_crtc
);
4843 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4844 encoder
->enable(encoder
);
4846 intel_crtc_enable_planes(crtc
);
4848 /* Underruns don't raise interrupts, so check manually. */
4849 i9xx_check_fifo_underruns(dev
);
4852 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4854 struct drm_device
*dev
= crtc
->base
.dev
;
4855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4857 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4858 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4861 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4863 struct drm_device
*dev
= crtc
->dev
;
4864 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4865 struct intel_encoder
*encoder
;
4866 int pipe
= intel_crtc
->pipe
;
4868 WARN_ON(!crtc
->enabled
);
4870 if (intel_crtc
->active
)
4873 i9xx_set_pll_dividers(intel_crtc
);
4875 if (intel_crtc
->config
.has_dp_encoder
)
4876 intel_dp_set_m_n(intel_crtc
);
4878 intel_set_pipe_timings(intel_crtc
);
4880 i9xx_set_pipeconf(intel_crtc
);
4882 intel_crtc
->active
= true;
4885 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4887 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4888 if (encoder
->pre_enable
)
4889 encoder
->pre_enable(encoder
);
4891 i9xx_enable_pll(intel_crtc
);
4893 i9xx_pfit_enable(intel_crtc
);
4895 intel_crtc_load_lut(crtc
);
4897 intel_update_watermarks(crtc
);
4898 intel_enable_pipe(intel_crtc
);
4900 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4901 encoder
->enable(encoder
);
4903 intel_crtc_enable_planes(crtc
);
4906 * Gen2 reports pipe underruns whenever all planes are disabled.
4907 * So don't enable underrun reporting before at least some planes
4909 * FIXME: Need to fix the logic to work when we turn off all planes
4910 * but leave the pipe running.
4913 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4915 /* Underruns don't raise interrupts, so check manually. */
4916 i9xx_check_fifo_underruns(dev
);
4919 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4921 struct drm_device
*dev
= crtc
->base
.dev
;
4922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4924 if (!crtc
->config
.gmch_pfit
.control
)
4927 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4929 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4930 I915_READ(PFIT_CONTROL
));
4931 I915_WRITE(PFIT_CONTROL
, 0);
4934 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4936 struct drm_device
*dev
= crtc
->dev
;
4937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4938 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4939 struct intel_encoder
*encoder
;
4940 int pipe
= intel_crtc
->pipe
;
4942 if (!intel_crtc
->active
)
4946 * Gen2 reports pipe underruns whenever all planes are disabled.
4947 * So diasble underrun reporting before all the planes get disabled.
4948 * FIXME: Need to fix the logic to work when we turn off all planes
4949 * but leave the pipe running.
4952 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4955 * Vblank time updates from the shadow to live plane control register
4956 * are blocked if the memory self-refresh mode is active at that
4957 * moment. So to make sure the plane gets truly disabled, disable
4958 * first the self-refresh mode. The self-refresh enable bit in turn
4959 * will be checked/applied by the HW only at the next frame start
4960 * event which is after the vblank start event, so we need to have a
4961 * wait-for-vblank between disabling the plane and the pipe.
4963 intel_set_memory_cxsr(dev_priv
, false);
4964 intel_crtc_disable_planes(crtc
);
4966 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4967 encoder
->disable(encoder
);
4970 * On gen2 planes are double buffered but the pipe isn't, so we must
4971 * wait for planes to fully turn off before disabling the pipe.
4972 * We also need to wait on all gmch platforms because of the
4973 * self-refresh mode constraint explained above.
4975 intel_wait_for_vblank(dev
, pipe
);
4977 intel_disable_pipe(intel_crtc
);
4979 i9xx_pfit_disable(intel_crtc
);
4981 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4982 if (encoder
->post_disable
)
4983 encoder
->post_disable(encoder
);
4985 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4986 if (IS_CHERRYVIEW(dev
))
4987 chv_disable_pll(dev_priv
, pipe
);
4988 else if (IS_VALLEYVIEW(dev
))
4989 vlv_disable_pll(dev_priv
, pipe
);
4991 i9xx_disable_pll(intel_crtc
);
4995 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4997 intel_crtc
->active
= false;
4998 intel_update_watermarks(crtc
);
5000 mutex_lock(&dev
->struct_mutex
);
5001 intel_update_fbc(dev
);
5002 mutex_unlock(&dev
->struct_mutex
);
5005 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5009 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
5012 struct drm_device
*dev
= crtc
->dev
;
5013 struct drm_i915_master_private
*master_priv
;
5014 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5015 int pipe
= intel_crtc
->pipe
;
5017 if (!dev
->primary
->master
)
5020 master_priv
= dev
->primary
->master
->driver_priv
;
5021 if (!master_priv
->sarea_priv
)
5026 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
5027 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
5030 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
5031 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
5034 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
5039 /* Master function to enable/disable CRTC and corresponding power wells */
5040 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5042 struct drm_device
*dev
= crtc
->dev
;
5043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5044 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5045 enum intel_display_power_domain domain
;
5046 unsigned long domains
;
5049 if (!intel_crtc
->active
) {
5050 domains
= get_crtc_power_domains(crtc
);
5051 for_each_power_domain(domain
, domains
)
5052 intel_display_power_get(dev_priv
, domain
);
5053 intel_crtc
->enabled_power_domains
= domains
;
5055 dev_priv
->display
.crtc_enable(crtc
);
5058 if (intel_crtc
->active
) {
5059 dev_priv
->display
.crtc_disable(crtc
);
5061 domains
= intel_crtc
->enabled_power_domains
;
5062 for_each_power_domain(domain
, domains
)
5063 intel_display_power_put(dev_priv
, domain
);
5064 intel_crtc
->enabled_power_domains
= 0;
5070 * Sets the power management mode of the pipe and plane.
5072 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5074 struct drm_device
*dev
= crtc
->dev
;
5075 struct intel_encoder
*intel_encoder
;
5076 bool enable
= false;
5078 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5079 enable
|= intel_encoder
->connectors_active
;
5081 intel_crtc_control(crtc
, enable
);
5083 intel_crtc_update_sarea(crtc
, enable
);
5086 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5088 struct drm_device
*dev
= crtc
->dev
;
5089 struct drm_connector
*connector
;
5090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5091 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
5092 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
5094 /* crtc should still be enabled when we disable it. */
5095 WARN_ON(!crtc
->enabled
);
5097 dev_priv
->display
.crtc_disable(crtc
);
5098 intel_crtc_update_sarea(crtc
, false);
5099 dev_priv
->display
.off(crtc
);
5101 if (crtc
->primary
->fb
) {
5102 mutex_lock(&dev
->struct_mutex
);
5103 intel_unpin_fb_obj(old_obj
);
5104 i915_gem_track_fb(old_obj
, NULL
,
5105 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5106 mutex_unlock(&dev
->struct_mutex
);
5107 crtc
->primary
->fb
= NULL
;
5110 /* Update computed state. */
5111 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5112 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5115 if (connector
->encoder
->crtc
!= crtc
)
5118 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5119 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5123 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5125 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5127 drm_encoder_cleanup(encoder
);
5128 kfree(intel_encoder
);
5131 /* Simple dpms helper for encoders with just one connector, no cloning and only
5132 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5133 * state of the entire output pipe. */
5134 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5136 if (mode
== DRM_MODE_DPMS_ON
) {
5137 encoder
->connectors_active
= true;
5139 intel_crtc_update_dpms(encoder
->base
.crtc
);
5141 encoder
->connectors_active
= false;
5143 intel_crtc_update_dpms(encoder
->base
.crtc
);
5147 /* Cross check the actual hw state with our own modeset state tracking (and it's
5148 * internal consistency). */
5149 static void intel_connector_check_state(struct intel_connector
*connector
)
5151 if (connector
->get_hw_state(connector
)) {
5152 struct intel_encoder
*encoder
= connector
->encoder
;
5153 struct drm_crtc
*crtc
;
5154 bool encoder_enabled
;
5157 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5158 connector
->base
.base
.id
,
5159 connector
->base
.name
);
5161 /* there is no real hw state for MST connectors */
5162 if (connector
->mst_port
)
5165 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5166 "wrong connector dpms state\n");
5167 WARN(connector
->base
.encoder
!= &encoder
->base
,
5168 "active connector not linked to encoder\n");
5171 WARN(!encoder
->connectors_active
,
5172 "encoder->connectors_active not set\n");
5174 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5175 WARN(!encoder_enabled
, "encoder not enabled\n");
5176 if (WARN_ON(!encoder
->base
.crtc
))
5179 crtc
= encoder
->base
.crtc
;
5181 WARN(!crtc
->enabled
, "crtc not enabled\n");
5182 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5183 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5184 "encoder active on the wrong pipe\n");
5189 /* Even simpler default implementation, if there's really no special case to
5191 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5193 /* All the simple cases only support two dpms states. */
5194 if (mode
!= DRM_MODE_DPMS_ON
)
5195 mode
= DRM_MODE_DPMS_OFF
;
5197 if (mode
== connector
->dpms
)
5200 connector
->dpms
= mode
;
5202 /* Only need to change hw state when actually enabled */
5203 if (connector
->encoder
)
5204 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5206 intel_modeset_check_state(connector
->dev
);
5209 /* Simple connector->get_hw_state implementation for encoders that support only
5210 * one connector and no cloning and hence the encoder state determines the state
5211 * of the connector. */
5212 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5215 struct intel_encoder
*encoder
= connector
->encoder
;
5217 return encoder
->get_hw_state(encoder
, &pipe
);
5220 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5221 struct intel_crtc_config
*pipe_config
)
5223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5224 struct intel_crtc
*pipe_B_crtc
=
5225 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5227 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5228 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5229 if (pipe_config
->fdi_lanes
> 4) {
5230 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5231 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5235 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5236 if (pipe_config
->fdi_lanes
> 2) {
5237 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5238 pipe_config
->fdi_lanes
);
5245 if (INTEL_INFO(dev
)->num_pipes
== 2)
5248 /* Ivybridge 3 pipe is really complicated */
5253 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5254 pipe_config
->fdi_lanes
> 2) {
5255 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5256 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5261 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5262 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5263 if (pipe_config
->fdi_lanes
> 2) {
5264 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5265 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5269 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5279 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5280 struct intel_crtc_config
*pipe_config
)
5282 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5283 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5284 int lane
, link_bw
, fdi_dotclock
;
5285 bool setup_ok
, needs_recompute
= false;
5288 /* FDI is a binary signal running at ~2.7GHz, encoding
5289 * each output octet as 10 bits. The actual frequency
5290 * is stored as a divider into a 100MHz clock, and the
5291 * mode pixel clock is stored in units of 1KHz.
5292 * Hence the bw of each lane in terms of the mode signal
5295 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5297 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5299 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5300 pipe_config
->pipe_bpp
);
5302 pipe_config
->fdi_lanes
= lane
;
5304 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5305 link_bw
, &pipe_config
->fdi_m_n
);
5307 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5308 intel_crtc
->pipe
, pipe_config
);
5309 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5310 pipe_config
->pipe_bpp
-= 2*3;
5311 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5312 pipe_config
->pipe_bpp
);
5313 needs_recompute
= true;
5314 pipe_config
->bw_constrained
= true;
5319 if (needs_recompute
)
5322 return setup_ok
? 0 : -EINVAL
;
5325 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5326 struct intel_crtc_config
*pipe_config
)
5328 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5329 hsw_crtc_supports_ips(crtc
) &&
5330 pipe_config
->pipe_bpp
<= 24;
5333 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5334 struct intel_crtc_config
*pipe_config
)
5336 struct drm_device
*dev
= crtc
->base
.dev
;
5337 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5339 /* FIXME should check pixel clock limits on all platforms */
5340 if (INTEL_INFO(dev
)->gen
< 4) {
5341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5343 dev_priv
->display
.get_display_clock_speed(dev
);
5346 * Enable pixel doubling when the dot clock
5347 * is > 90% of the (display) core speed.
5349 * GDG double wide on either pipe,
5350 * otherwise pipe A only.
5352 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5353 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5355 pipe_config
->double_wide
= true;
5358 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5363 * Pipe horizontal size must be even in:
5365 * - LVDS dual channel mode
5366 * - Double wide pipe
5368 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5369 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5370 pipe_config
->pipe_src_w
&= ~1;
5372 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5373 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5375 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5376 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5379 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5380 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5381 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5382 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5384 pipe_config
->pipe_bpp
= 8*3;
5388 hsw_compute_ips_config(crtc
, pipe_config
);
5391 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5392 * old clock survives for now.
5394 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5395 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5397 if (pipe_config
->has_pch_encoder
)
5398 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5403 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5406 int vco
= valleyview_get_vco(dev_priv
);
5410 /* FIXME: Punit isn't quite ready yet */
5411 if (IS_CHERRYVIEW(dev
))
5414 mutex_lock(&dev_priv
->dpio_lock
);
5415 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5416 mutex_unlock(&dev_priv
->dpio_lock
);
5418 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5420 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5421 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5422 "cdclk change in progress\n");
5424 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5427 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5432 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5437 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5442 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5446 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5448 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5449 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5451 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5453 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5455 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5458 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5459 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5461 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5466 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5470 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5472 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5475 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5476 case GC_DISPLAY_CLOCK_333_MHZ
:
5479 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5485 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5490 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5493 /* Assume that the hardware is in the high speed state. This
5494 * should be the default.
5496 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5497 case GC_CLOCK_133_200
:
5498 case GC_CLOCK_100_200
:
5500 case GC_CLOCK_166_250
:
5502 case GC_CLOCK_100_133
:
5506 /* Shouldn't happen */
5510 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5516 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5518 while (*num
> DATA_LINK_M_N_MASK
||
5519 *den
> DATA_LINK_M_N_MASK
) {
5525 static void compute_m_n(unsigned int m
, unsigned int n
,
5526 uint32_t *ret_m
, uint32_t *ret_n
)
5528 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5529 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5530 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5534 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5535 int pixel_clock
, int link_clock
,
5536 struct intel_link_m_n
*m_n
)
5540 compute_m_n(bits_per_pixel
* pixel_clock
,
5541 link_clock
* nlanes
* 8,
5542 &m_n
->gmch_m
, &m_n
->gmch_n
);
5544 compute_m_n(pixel_clock
, link_clock
,
5545 &m_n
->link_m
, &m_n
->link_n
);
5548 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5550 if (i915
.panel_use_ssc
>= 0)
5551 return i915
.panel_use_ssc
!= 0;
5552 return dev_priv
->vbt
.lvds_use_ssc
5553 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5556 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5558 struct drm_device
*dev
= crtc
->dev
;
5559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5562 if (IS_VALLEYVIEW(dev
)) {
5564 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5565 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5566 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5567 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5568 } else if (!IS_GEN2(dev
)) {
5577 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5579 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5582 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5584 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5587 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5588 intel_clock_t
*reduced_clock
)
5590 struct drm_device
*dev
= crtc
->base
.dev
;
5593 if (IS_PINEVIEW(dev
)) {
5594 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5596 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5598 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5600 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5603 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5605 crtc
->lowfreq_avail
= false;
5606 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5607 reduced_clock
&& i915
.powersave
) {
5608 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5609 crtc
->lowfreq_avail
= true;
5611 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5615 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5621 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5622 * and set it to a reasonable value instead.
5624 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5625 reg_val
&= 0xffffff00;
5626 reg_val
|= 0x00000030;
5627 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5629 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5630 reg_val
&= 0x8cffffff;
5631 reg_val
= 0x8c000000;
5632 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5634 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5635 reg_val
&= 0xffffff00;
5636 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5638 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5639 reg_val
&= 0x00ffffff;
5640 reg_val
|= 0xb0000000;
5641 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5644 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5645 struct intel_link_m_n
*m_n
)
5647 struct drm_device
*dev
= crtc
->base
.dev
;
5648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5649 int pipe
= crtc
->pipe
;
5651 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5652 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5653 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5654 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5657 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5658 struct intel_link_m_n
*m_n
,
5659 struct intel_link_m_n
*m2_n2
)
5661 struct drm_device
*dev
= crtc
->base
.dev
;
5662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5663 int pipe
= crtc
->pipe
;
5664 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5666 if (INTEL_INFO(dev
)->gen
>= 5) {
5667 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5668 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5669 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5670 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5671 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5672 * for gen < 8) and if DRRS is supported (to make sure the
5673 * registers are not unnecessarily accessed).
5675 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5676 crtc
->config
.has_drrs
) {
5677 I915_WRITE(PIPE_DATA_M2(transcoder
),
5678 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5679 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5680 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5681 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5684 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5685 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5686 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5687 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5691 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5693 if (crtc
->config
.has_pch_encoder
)
5694 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5696 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5697 &crtc
->config
.dp_m2_n2
);
5700 static void vlv_update_pll(struct intel_crtc
*crtc
)
5705 * Enable DPIO clock input. We should never disable the reference
5706 * clock for pipe B, since VGA hotplug / manual detection depends
5709 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5710 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5711 /* We should never disable this, set it here for state tracking */
5712 if (crtc
->pipe
== PIPE_B
)
5713 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5714 dpll
|= DPLL_VCO_ENABLE
;
5715 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5717 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5718 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5719 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5722 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5724 struct drm_device
*dev
= crtc
->base
.dev
;
5725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5726 int pipe
= crtc
->pipe
;
5728 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5729 u32 coreclk
, reg_val
;
5731 mutex_lock(&dev_priv
->dpio_lock
);
5733 bestn
= crtc
->config
.dpll
.n
;
5734 bestm1
= crtc
->config
.dpll
.m1
;
5735 bestm2
= crtc
->config
.dpll
.m2
;
5736 bestp1
= crtc
->config
.dpll
.p1
;
5737 bestp2
= crtc
->config
.dpll
.p2
;
5739 /* See eDP HDMI DPIO driver vbios notes doc */
5741 /* PLL B needs special handling */
5743 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5745 /* Set up Tx target for periodic Rcomp update */
5746 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5748 /* Disable target IRef on PLL */
5749 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5750 reg_val
&= 0x00ffffff;
5751 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5753 /* Disable fast lock */
5754 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5756 /* Set idtafcrecal before PLL is enabled */
5757 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5758 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5759 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5760 mdiv
|= (1 << DPIO_K_SHIFT
);
5763 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5764 * but we don't support that).
5765 * Note: don't use the DAC post divider as it seems unstable.
5767 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5768 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5770 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5771 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5773 /* Set HBR and RBR LPF coefficients */
5774 if (crtc
->config
.port_clock
== 162000 ||
5775 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5776 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5777 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5780 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5783 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5784 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5785 /* Use SSC source */
5787 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5790 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5792 } else { /* HDMI or VGA */
5793 /* Use bend source */
5795 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5798 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5802 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5803 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5804 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5805 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5806 coreclk
|= 0x01000000;
5807 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5809 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5810 mutex_unlock(&dev_priv
->dpio_lock
);
5813 static void chv_update_pll(struct intel_crtc
*crtc
)
5815 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5816 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5818 if (crtc
->pipe
!= PIPE_A
)
5819 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5821 crtc
->config
.dpll_hw_state
.dpll_md
=
5822 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5825 static void chv_prepare_pll(struct intel_crtc
*crtc
)
5827 struct drm_device
*dev
= crtc
->base
.dev
;
5828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5829 int pipe
= crtc
->pipe
;
5830 int dpll_reg
= DPLL(crtc
->pipe
);
5831 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5832 u32 loopfilter
, intcoeff
;
5833 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5836 bestn
= crtc
->config
.dpll
.n
;
5837 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5838 bestm1
= crtc
->config
.dpll
.m1
;
5839 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5840 bestp1
= crtc
->config
.dpll
.p1
;
5841 bestp2
= crtc
->config
.dpll
.p2
;
5844 * Enable Refclk and SSC
5846 I915_WRITE(dpll_reg
,
5847 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5849 mutex_lock(&dev_priv
->dpio_lock
);
5851 /* p1 and p2 divider */
5852 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5853 5 << DPIO_CHV_S1_DIV_SHIFT
|
5854 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5855 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5856 1 << DPIO_CHV_K_DIV_SHIFT
);
5858 /* Feedback post-divider - m2 */
5859 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5861 /* Feedback refclk divider - n and m1 */
5862 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5863 DPIO_CHV_M1_DIV_BY_2
|
5864 1 << DPIO_CHV_N_DIV_SHIFT
);
5866 /* M2 fraction division */
5867 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5869 /* M2 fraction division enable */
5870 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5871 DPIO_CHV_FRAC_DIV_EN
|
5872 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5875 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5876 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5877 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5878 if (refclk
== 100000)
5880 else if (refclk
== 38400)
5884 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5885 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5888 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5889 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5892 mutex_unlock(&dev_priv
->dpio_lock
);
5895 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5896 intel_clock_t
*reduced_clock
,
5899 struct drm_device
*dev
= crtc
->base
.dev
;
5900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5903 struct dpll
*clock
= &crtc
->config
.dpll
;
5905 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5907 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5908 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5910 dpll
= DPLL_VGA_MODE_DIS
;
5912 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5913 dpll
|= DPLLB_MODE_LVDS
;
5915 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5917 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5918 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5919 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5923 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5925 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5926 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5928 /* compute bitmask from p1 value */
5929 if (IS_PINEVIEW(dev
))
5930 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5932 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5933 if (IS_G4X(dev
) && reduced_clock
)
5934 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5936 switch (clock
->p2
) {
5938 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5941 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5944 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5947 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5950 if (INTEL_INFO(dev
)->gen
>= 4)
5951 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5953 if (crtc
->config
.sdvo_tv_clock
)
5954 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5955 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5956 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5957 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5959 dpll
|= PLL_REF_INPUT_DREFCLK
;
5961 dpll
|= DPLL_VCO_ENABLE
;
5962 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5964 if (INTEL_INFO(dev
)->gen
>= 4) {
5965 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5966 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5967 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5971 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5972 intel_clock_t
*reduced_clock
,
5975 struct drm_device
*dev
= crtc
->base
.dev
;
5976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5978 struct dpll
*clock
= &crtc
->config
.dpll
;
5980 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5982 dpll
= DPLL_VGA_MODE_DIS
;
5984 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5985 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5988 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5990 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5992 dpll
|= PLL_P2_DIVIDE_BY_4
;
5995 if (!IS_I830(dev
) && intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5996 dpll
|= DPLL_DVO_2X_MODE
;
5998 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5999 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6000 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6002 dpll
|= PLL_REF_INPUT_DREFCLK
;
6004 dpll
|= DPLL_VCO_ENABLE
;
6005 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6008 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6010 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6012 enum pipe pipe
= intel_crtc
->pipe
;
6013 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6014 struct drm_display_mode
*adjusted_mode
=
6015 &intel_crtc
->config
.adjusted_mode
;
6016 uint32_t crtc_vtotal
, crtc_vblank_end
;
6019 /* We need to be careful not to changed the adjusted mode, for otherwise
6020 * the hw state checker will get angry at the mismatch. */
6021 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6022 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6024 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6025 /* the chip adds 2 halflines automatically */
6027 crtc_vblank_end
-= 1;
6029 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6030 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6032 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6033 adjusted_mode
->crtc_htotal
/ 2;
6035 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6038 if (INTEL_INFO(dev
)->gen
> 3)
6039 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6041 I915_WRITE(HTOTAL(cpu_transcoder
),
6042 (adjusted_mode
->crtc_hdisplay
- 1) |
6043 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6044 I915_WRITE(HBLANK(cpu_transcoder
),
6045 (adjusted_mode
->crtc_hblank_start
- 1) |
6046 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6047 I915_WRITE(HSYNC(cpu_transcoder
),
6048 (adjusted_mode
->crtc_hsync_start
- 1) |
6049 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6051 I915_WRITE(VTOTAL(cpu_transcoder
),
6052 (adjusted_mode
->crtc_vdisplay
- 1) |
6053 ((crtc_vtotal
- 1) << 16));
6054 I915_WRITE(VBLANK(cpu_transcoder
),
6055 (adjusted_mode
->crtc_vblank_start
- 1) |
6056 ((crtc_vblank_end
- 1) << 16));
6057 I915_WRITE(VSYNC(cpu_transcoder
),
6058 (adjusted_mode
->crtc_vsync_start
- 1) |
6059 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6061 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6062 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6063 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6065 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6066 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6067 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6069 /* pipesrc controls the size that is scaled from, which should
6070 * always be the user's requested size.
6072 I915_WRITE(PIPESRC(pipe
),
6073 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
6074 (intel_crtc
->config
.pipe_src_h
- 1));
6077 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6078 struct intel_crtc_config
*pipe_config
)
6080 struct drm_device
*dev
= crtc
->base
.dev
;
6081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6082 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6085 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6086 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6087 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6088 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6089 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6090 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6091 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6092 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6093 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6095 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6096 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6097 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6098 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6099 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6100 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6101 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6102 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6103 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6105 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6106 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6107 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6108 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6111 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6112 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6113 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6115 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6116 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6119 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6120 struct intel_crtc_config
*pipe_config
)
6122 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6123 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6124 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6125 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6127 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6128 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6129 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6130 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6132 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6134 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6135 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6138 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6140 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6146 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6147 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6148 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6150 if (intel_crtc
->config
.double_wide
)
6151 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6153 /* only g4x and later have fancy bpc/dither controls */
6154 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6155 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6156 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6157 pipeconf
|= PIPECONF_DITHER_EN
|
6158 PIPECONF_DITHER_TYPE_SP
;
6160 switch (intel_crtc
->config
.pipe_bpp
) {
6162 pipeconf
|= PIPECONF_6BPC
;
6165 pipeconf
|= PIPECONF_8BPC
;
6168 pipeconf
|= PIPECONF_10BPC
;
6171 /* Case prevented by intel_choose_pipe_bpp_dither. */
6176 if (HAS_PIPE_CXSR(dev
)) {
6177 if (intel_crtc
->lowfreq_avail
) {
6178 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6179 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6181 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6185 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6186 if (INTEL_INFO(dev
)->gen
< 4 ||
6187 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6188 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6190 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6192 pipeconf
|= PIPECONF_PROGRESSIVE
;
6194 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6195 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6197 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6198 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6201 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6203 struct drm_framebuffer
*fb
)
6205 struct drm_device
*dev
= crtc
->dev
;
6206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6207 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6208 int refclk
, num_connectors
= 0;
6209 intel_clock_t clock
, reduced_clock
;
6210 bool ok
, has_reduced_clock
= false;
6211 bool is_lvds
= false, is_dsi
= false;
6212 struct intel_encoder
*encoder
;
6213 const intel_limit_t
*limit
;
6215 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6216 switch (encoder
->type
) {
6217 case INTEL_OUTPUT_LVDS
:
6220 case INTEL_OUTPUT_DSI
:
6231 if (!intel_crtc
->config
.clock_set
) {
6232 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6235 * Returns a set of divisors for the desired target clock with
6236 * the given refclk, or FALSE. The returned values represent
6237 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6240 limit
= intel_limit(crtc
, refclk
);
6241 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6242 intel_crtc
->config
.port_clock
,
6243 refclk
, NULL
, &clock
);
6245 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6249 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6251 * Ensure we match the reduced clock's P to the target
6252 * clock. If the clocks don't match, we can't switch
6253 * the display clock by using the FP0/FP1. In such case
6254 * we will disable the LVDS downclock feature.
6257 dev_priv
->display
.find_dpll(limit
, crtc
,
6258 dev_priv
->lvds_downclock
,
6262 /* Compat-code for transition, will disappear. */
6263 intel_crtc
->config
.dpll
.n
= clock
.n
;
6264 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6265 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6266 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6267 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6271 i8xx_update_pll(intel_crtc
,
6272 has_reduced_clock
? &reduced_clock
: NULL
,
6274 } else if (IS_CHERRYVIEW(dev
)) {
6275 chv_update_pll(intel_crtc
);
6276 } else if (IS_VALLEYVIEW(dev
)) {
6277 vlv_update_pll(intel_crtc
);
6279 i9xx_update_pll(intel_crtc
,
6280 has_reduced_clock
? &reduced_clock
: NULL
,
6287 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6288 struct intel_crtc_config
*pipe_config
)
6290 struct drm_device
*dev
= crtc
->base
.dev
;
6291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6294 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6297 tmp
= I915_READ(PFIT_CONTROL
);
6298 if (!(tmp
& PFIT_ENABLE
))
6301 /* Check whether the pfit is attached to our pipe. */
6302 if (INTEL_INFO(dev
)->gen
< 4) {
6303 if (crtc
->pipe
!= PIPE_B
)
6306 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6310 pipe_config
->gmch_pfit
.control
= tmp
;
6311 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6312 if (INTEL_INFO(dev
)->gen
< 5)
6313 pipe_config
->gmch_pfit
.lvds_border_bits
=
6314 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6317 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6318 struct intel_crtc_config
*pipe_config
)
6320 struct drm_device
*dev
= crtc
->base
.dev
;
6321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6322 int pipe
= pipe_config
->cpu_transcoder
;
6323 intel_clock_t clock
;
6325 int refclk
= 100000;
6327 /* In case of MIPI DPLL will not even be used */
6328 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6331 mutex_lock(&dev_priv
->dpio_lock
);
6332 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6333 mutex_unlock(&dev_priv
->dpio_lock
);
6335 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6336 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6337 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6338 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6339 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6341 vlv_clock(refclk
, &clock
);
6343 /* clock.dot is the fast clock */
6344 pipe_config
->port_clock
= clock
.dot
/ 5;
6347 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6348 struct intel_plane_config
*plane_config
)
6350 struct drm_device
*dev
= crtc
->base
.dev
;
6351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6352 u32 val
, base
, offset
;
6353 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6354 int fourcc
, pixel_format
;
6357 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6358 if (!crtc
->base
.primary
->fb
) {
6359 DRM_DEBUG_KMS("failed to alloc fb\n");
6363 val
= I915_READ(DSPCNTR(plane
));
6365 if (INTEL_INFO(dev
)->gen
>= 4)
6366 if (val
& DISPPLANE_TILED
)
6367 plane_config
->tiled
= true;
6369 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6370 fourcc
= intel_format_to_fourcc(pixel_format
);
6371 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6372 crtc
->base
.primary
->fb
->bits_per_pixel
=
6373 drm_format_plane_cpp(fourcc
, 0) * 8;
6375 if (INTEL_INFO(dev
)->gen
>= 4) {
6376 if (plane_config
->tiled
)
6377 offset
= I915_READ(DSPTILEOFF(plane
));
6379 offset
= I915_READ(DSPLINOFF(plane
));
6380 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6382 base
= I915_READ(DSPADDR(plane
));
6384 plane_config
->base
= base
;
6386 val
= I915_READ(PIPESRC(pipe
));
6387 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6388 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6390 val
= I915_READ(DSPSTRIDE(pipe
));
6391 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6393 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6394 plane_config
->tiled
);
6396 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6399 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6400 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6401 crtc
->base
.primary
->fb
->height
,
6402 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6403 crtc
->base
.primary
->fb
->pitches
[0],
6404 plane_config
->size
);
6408 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6409 struct intel_crtc_config
*pipe_config
)
6411 struct drm_device
*dev
= crtc
->base
.dev
;
6412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6413 int pipe
= pipe_config
->cpu_transcoder
;
6414 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6415 intel_clock_t clock
;
6416 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6417 int refclk
= 100000;
6419 mutex_lock(&dev_priv
->dpio_lock
);
6420 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6421 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6422 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6423 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6424 mutex_unlock(&dev_priv
->dpio_lock
);
6426 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6427 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6428 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6429 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6430 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6432 chv_clock(refclk
, &clock
);
6434 /* clock.dot is the fast clock */
6435 pipe_config
->port_clock
= clock
.dot
/ 5;
6438 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6439 struct intel_crtc_config
*pipe_config
)
6441 struct drm_device
*dev
= crtc
->base
.dev
;
6442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6445 if (!intel_display_power_enabled(dev_priv
,
6446 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6449 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6450 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6452 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6453 if (!(tmp
& PIPECONF_ENABLE
))
6456 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6457 switch (tmp
& PIPECONF_BPC_MASK
) {
6459 pipe_config
->pipe_bpp
= 18;
6462 pipe_config
->pipe_bpp
= 24;
6464 case PIPECONF_10BPC
:
6465 pipe_config
->pipe_bpp
= 30;
6472 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6473 pipe_config
->limited_color_range
= true;
6475 if (INTEL_INFO(dev
)->gen
< 4)
6476 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6478 intel_get_pipe_timings(crtc
, pipe_config
);
6480 i9xx_get_pfit_config(crtc
, pipe_config
);
6482 if (INTEL_INFO(dev
)->gen
>= 4) {
6483 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6484 pipe_config
->pixel_multiplier
=
6485 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6486 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6487 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6488 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6489 tmp
= I915_READ(DPLL(crtc
->pipe
));
6490 pipe_config
->pixel_multiplier
=
6491 ((tmp
& SDVO_MULTIPLIER_MASK
)
6492 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6494 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6495 * port and will be fixed up in the encoder->get_config
6497 pipe_config
->pixel_multiplier
= 1;
6499 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6500 if (!IS_VALLEYVIEW(dev
)) {
6502 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6503 * on 830. Filter it out here so that we don't
6504 * report errors due to that.
6507 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6509 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6510 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6512 /* Mask out read-only status bits. */
6513 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6514 DPLL_PORTC_READY_MASK
|
6515 DPLL_PORTB_READY_MASK
);
6518 if (IS_CHERRYVIEW(dev
))
6519 chv_crtc_clock_get(crtc
, pipe_config
);
6520 else if (IS_VALLEYVIEW(dev
))
6521 vlv_crtc_clock_get(crtc
, pipe_config
);
6523 i9xx_crtc_clock_get(crtc
, pipe_config
);
6528 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6531 struct intel_encoder
*encoder
;
6533 bool has_lvds
= false;
6534 bool has_cpu_edp
= false;
6535 bool has_panel
= false;
6536 bool has_ck505
= false;
6537 bool can_ssc
= false;
6539 /* We need to take the global config into account */
6540 for_each_intel_encoder(dev
, encoder
) {
6541 switch (encoder
->type
) {
6542 case INTEL_OUTPUT_LVDS
:
6546 case INTEL_OUTPUT_EDP
:
6548 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6554 if (HAS_PCH_IBX(dev
)) {
6555 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6556 can_ssc
= has_ck505
;
6562 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6563 has_panel
, has_lvds
, has_ck505
);
6565 /* Ironlake: try to setup display ref clock before DPLL
6566 * enabling. This is only under driver's control after
6567 * PCH B stepping, previous chipset stepping should be
6568 * ignoring this setting.
6570 val
= I915_READ(PCH_DREF_CONTROL
);
6572 /* As we must carefully and slowly disable/enable each source in turn,
6573 * compute the final state we want first and check if we need to
6574 * make any changes at all.
6577 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6579 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6581 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6583 final
&= ~DREF_SSC_SOURCE_MASK
;
6584 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6585 final
&= ~DREF_SSC1_ENABLE
;
6588 final
|= DREF_SSC_SOURCE_ENABLE
;
6590 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6591 final
|= DREF_SSC1_ENABLE
;
6594 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6595 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6597 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6599 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6601 final
|= DREF_SSC_SOURCE_DISABLE
;
6602 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6608 /* Always enable nonspread source */
6609 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6612 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6614 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6617 val
&= ~DREF_SSC_SOURCE_MASK
;
6618 val
|= DREF_SSC_SOURCE_ENABLE
;
6620 /* SSC must be turned on before enabling the CPU output */
6621 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6622 DRM_DEBUG_KMS("Using SSC on panel\n");
6623 val
|= DREF_SSC1_ENABLE
;
6625 val
&= ~DREF_SSC1_ENABLE
;
6627 /* Get SSC going before enabling the outputs */
6628 I915_WRITE(PCH_DREF_CONTROL
, val
);
6629 POSTING_READ(PCH_DREF_CONTROL
);
6632 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6634 /* Enable CPU source on CPU attached eDP */
6636 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6637 DRM_DEBUG_KMS("Using SSC on eDP\n");
6638 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6640 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6642 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6644 I915_WRITE(PCH_DREF_CONTROL
, val
);
6645 POSTING_READ(PCH_DREF_CONTROL
);
6648 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6650 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6652 /* Turn off CPU output */
6653 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6655 I915_WRITE(PCH_DREF_CONTROL
, val
);
6656 POSTING_READ(PCH_DREF_CONTROL
);
6659 /* Turn off the SSC source */
6660 val
&= ~DREF_SSC_SOURCE_MASK
;
6661 val
|= DREF_SSC_SOURCE_DISABLE
;
6664 val
&= ~DREF_SSC1_ENABLE
;
6666 I915_WRITE(PCH_DREF_CONTROL
, val
);
6667 POSTING_READ(PCH_DREF_CONTROL
);
6671 BUG_ON(val
!= final
);
6674 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6678 tmp
= I915_READ(SOUTH_CHICKEN2
);
6679 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6680 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6682 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6683 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6684 DRM_ERROR("FDI mPHY reset assert timeout\n");
6686 tmp
= I915_READ(SOUTH_CHICKEN2
);
6687 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6688 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6690 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6691 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6692 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6695 /* WaMPhyProgramming:hsw */
6696 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6700 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6701 tmp
&= ~(0xFF << 24);
6702 tmp
|= (0x12 << 24);
6703 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6705 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6707 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6709 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6711 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6713 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6714 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6715 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6717 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6718 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6719 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6721 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6724 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6726 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6729 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6731 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6734 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6736 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6739 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6741 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6742 tmp
&= ~(0xFF << 16);
6743 tmp
|= (0x1C << 16);
6744 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6746 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6747 tmp
&= ~(0xFF << 16);
6748 tmp
|= (0x1C << 16);
6749 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6751 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6753 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6755 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6757 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6759 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6760 tmp
&= ~(0xF << 28);
6762 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6764 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6765 tmp
&= ~(0xF << 28);
6767 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6770 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6771 * Programming" based on the parameters passed:
6772 * - Sequence to enable CLKOUT_DP
6773 * - Sequence to enable CLKOUT_DP without spread
6774 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6776 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6782 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6784 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6785 with_fdi
, "LP PCH doesn't have FDI\n"))
6788 mutex_lock(&dev_priv
->dpio_lock
);
6790 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6791 tmp
&= ~SBI_SSCCTL_DISABLE
;
6792 tmp
|= SBI_SSCCTL_PATHALT
;
6793 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6798 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6799 tmp
&= ~SBI_SSCCTL_PATHALT
;
6800 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6803 lpt_reset_fdi_mphy(dev_priv
);
6804 lpt_program_fdi_mphy(dev_priv
);
6808 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6809 SBI_GEN0
: SBI_DBUFF0
;
6810 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6811 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6812 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6814 mutex_unlock(&dev_priv
->dpio_lock
);
6817 /* Sequence to disable CLKOUT_DP */
6818 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6823 mutex_lock(&dev_priv
->dpio_lock
);
6825 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6826 SBI_GEN0
: SBI_DBUFF0
;
6827 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6828 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6829 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6831 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6832 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6833 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6834 tmp
|= SBI_SSCCTL_PATHALT
;
6835 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6838 tmp
|= SBI_SSCCTL_DISABLE
;
6839 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6842 mutex_unlock(&dev_priv
->dpio_lock
);
6845 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6847 struct intel_encoder
*encoder
;
6848 bool has_vga
= false;
6850 for_each_intel_encoder(dev
, encoder
) {
6851 switch (encoder
->type
) {
6852 case INTEL_OUTPUT_ANALOG
:
6859 lpt_enable_clkout_dp(dev
, true, true);
6861 lpt_disable_clkout_dp(dev
);
6865 * Initialize reference clocks when the driver loads
6867 void intel_init_pch_refclk(struct drm_device
*dev
)
6869 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6870 ironlake_init_pch_refclk(dev
);
6871 else if (HAS_PCH_LPT(dev
))
6872 lpt_init_pch_refclk(dev
);
6875 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6877 struct drm_device
*dev
= crtc
->dev
;
6878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6879 struct intel_encoder
*encoder
;
6880 int num_connectors
= 0;
6881 bool is_lvds
= false;
6883 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6884 switch (encoder
->type
) {
6885 case INTEL_OUTPUT_LVDS
:
6892 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6893 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6894 dev_priv
->vbt
.lvds_ssc_freq
);
6895 return dev_priv
->vbt
.lvds_ssc_freq
;
6901 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6903 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6904 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6905 int pipe
= intel_crtc
->pipe
;
6910 switch (intel_crtc
->config
.pipe_bpp
) {
6912 val
|= PIPECONF_6BPC
;
6915 val
|= PIPECONF_8BPC
;
6918 val
|= PIPECONF_10BPC
;
6921 val
|= PIPECONF_12BPC
;
6924 /* Case prevented by intel_choose_pipe_bpp_dither. */
6928 if (intel_crtc
->config
.dither
)
6929 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6931 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6932 val
|= PIPECONF_INTERLACED_ILK
;
6934 val
|= PIPECONF_PROGRESSIVE
;
6936 if (intel_crtc
->config
.limited_color_range
)
6937 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6939 I915_WRITE(PIPECONF(pipe
), val
);
6940 POSTING_READ(PIPECONF(pipe
));
6944 * Set up the pipe CSC unit.
6946 * Currently only full range RGB to limited range RGB conversion
6947 * is supported, but eventually this should handle various
6948 * RGB<->YCbCr scenarios as well.
6950 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6952 struct drm_device
*dev
= crtc
->dev
;
6953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6954 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6955 int pipe
= intel_crtc
->pipe
;
6956 uint16_t coeff
= 0x7800; /* 1.0 */
6959 * TODO: Check what kind of values actually come out of the pipe
6960 * with these coeff/postoff values and adjust to get the best
6961 * accuracy. Perhaps we even need to take the bpc value into
6965 if (intel_crtc
->config
.limited_color_range
)
6966 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6969 * GY/GU and RY/RU should be the other way around according
6970 * to BSpec, but reality doesn't agree. Just set them up in
6971 * a way that results in the correct picture.
6973 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6974 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6976 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6977 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6979 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6980 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6982 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6983 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6984 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6986 if (INTEL_INFO(dev
)->gen
> 6) {
6987 uint16_t postoff
= 0;
6989 if (intel_crtc
->config
.limited_color_range
)
6990 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6992 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6993 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6994 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6996 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6998 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7000 if (intel_crtc
->config
.limited_color_range
)
7001 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7003 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7007 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7009 struct drm_device
*dev
= crtc
->dev
;
7010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7011 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7012 enum pipe pipe
= intel_crtc
->pipe
;
7013 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7018 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
7019 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7021 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7022 val
|= PIPECONF_INTERLACED_ILK
;
7024 val
|= PIPECONF_PROGRESSIVE
;
7026 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7027 POSTING_READ(PIPECONF(cpu_transcoder
));
7029 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7030 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7032 if (IS_BROADWELL(dev
)) {
7035 switch (intel_crtc
->config
.pipe_bpp
) {
7037 val
|= PIPEMISC_DITHER_6_BPC
;
7040 val
|= PIPEMISC_DITHER_8_BPC
;
7043 val
|= PIPEMISC_DITHER_10_BPC
;
7046 val
|= PIPEMISC_DITHER_12_BPC
;
7049 /* Case prevented by pipe_config_set_bpp. */
7053 if (intel_crtc
->config
.dither
)
7054 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7056 I915_WRITE(PIPEMISC(pipe
), val
);
7060 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7061 intel_clock_t
*clock
,
7062 bool *has_reduced_clock
,
7063 intel_clock_t
*reduced_clock
)
7065 struct drm_device
*dev
= crtc
->dev
;
7066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7067 struct intel_encoder
*intel_encoder
;
7069 const intel_limit_t
*limit
;
7070 bool ret
, is_lvds
= false;
7072 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7073 switch (intel_encoder
->type
) {
7074 case INTEL_OUTPUT_LVDS
:
7080 refclk
= ironlake_get_refclk(crtc
);
7083 * Returns a set of divisors for the desired target clock with the given
7084 * refclk, or FALSE. The returned values represent the clock equation:
7085 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7087 limit
= intel_limit(crtc
, refclk
);
7088 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
7089 to_intel_crtc(crtc
)->config
.port_clock
,
7090 refclk
, NULL
, clock
);
7094 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7096 * Ensure we match the reduced clock's P to the target clock.
7097 * If the clocks don't match, we can't switch the display clock
7098 * by using the FP0/FP1. In such case we will disable the LVDS
7099 * downclock feature.
7101 *has_reduced_clock
=
7102 dev_priv
->display
.find_dpll(limit
, crtc
,
7103 dev_priv
->lvds_downclock
,
7111 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7114 * Account for spread spectrum to avoid
7115 * oversubscribing the link. Max center spread
7116 * is 2.5%; use 5% for safety's sake.
7118 u32 bps
= target_clock
* bpp
* 21 / 20;
7119 return DIV_ROUND_UP(bps
, link_bw
* 8);
7122 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7124 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7127 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7129 intel_clock_t
*reduced_clock
, u32
*fp2
)
7131 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7132 struct drm_device
*dev
= crtc
->dev
;
7133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7134 struct intel_encoder
*intel_encoder
;
7136 int factor
, num_connectors
= 0;
7137 bool is_lvds
= false, is_sdvo
= false;
7139 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7140 switch (intel_encoder
->type
) {
7141 case INTEL_OUTPUT_LVDS
:
7144 case INTEL_OUTPUT_SDVO
:
7145 case INTEL_OUTPUT_HDMI
:
7153 /* Enable autotuning of the PLL clock (if permissible) */
7156 if ((intel_panel_use_ssc(dev_priv
) &&
7157 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7158 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7160 } else if (intel_crtc
->config
.sdvo_tv_clock
)
7163 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
7166 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7172 dpll
|= DPLLB_MODE_LVDS
;
7174 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7176 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
7177 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7180 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7181 if (intel_crtc
->config
.has_dp_encoder
)
7182 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7184 /* compute bitmask from p1 value */
7185 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7187 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7189 switch (intel_crtc
->config
.dpll
.p2
) {
7191 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7194 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7197 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7200 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7204 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7205 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7207 dpll
|= PLL_REF_INPUT_DREFCLK
;
7209 return dpll
| DPLL_VCO_ENABLE
;
7212 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7214 struct drm_framebuffer
*fb
)
7216 struct drm_device
*dev
= crtc
->dev
;
7217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7218 int num_connectors
= 0;
7219 intel_clock_t clock
, reduced_clock
;
7220 u32 dpll
= 0, fp
= 0, fp2
= 0;
7221 bool ok
, has_reduced_clock
= false;
7222 bool is_lvds
= false;
7223 struct intel_encoder
*encoder
;
7224 struct intel_shared_dpll
*pll
;
7226 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7227 switch (encoder
->type
) {
7228 case INTEL_OUTPUT_LVDS
:
7236 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7237 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7239 ok
= ironlake_compute_clocks(crtc
, &clock
,
7240 &has_reduced_clock
, &reduced_clock
);
7241 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7242 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7245 /* Compat-code for transition, will disappear. */
7246 if (!intel_crtc
->config
.clock_set
) {
7247 intel_crtc
->config
.dpll
.n
= clock
.n
;
7248 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7249 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7250 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7251 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7254 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7255 if (intel_crtc
->config
.has_pch_encoder
) {
7256 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7257 if (has_reduced_clock
)
7258 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7260 dpll
= ironlake_compute_dpll(intel_crtc
,
7261 &fp
, &reduced_clock
,
7262 has_reduced_clock
? &fp2
: NULL
);
7264 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7265 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7266 if (has_reduced_clock
)
7267 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7269 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7271 pll
= intel_get_shared_dpll(intel_crtc
);
7273 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7274 pipe_name(intel_crtc
->pipe
));
7278 intel_put_shared_dpll(intel_crtc
);
7280 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7281 intel_crtc
->lowfreq_avail
= true;
7283 intel_crtc
->lowfreq_avail
= false;
7288 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7289 struct intel_link_m_n
*m_n
)
7291 struct drm_device
*dev
= crtc
->base
.dev
;
7292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7293 enum pipe pipe
= crtc
->pipe
;
7295 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7296 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7297 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7299 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7300 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7301 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7304 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7305 enum transcoder transcoder
,
7306 struct intel_link_m_n
*m_n
,
7307 struct intel_link_m_n
*m2_n2
)
7309 struct drm_device
*dev
= crtc
->base
.dev
;
7310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7311 enum pipe pipe
= crtc
->pipe
;
7313 if (INTEL_INFO(dev
)->gen
>= 5) {
7314 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7315 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7316 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7318 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7319 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7320 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7321 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7322 * gen < 8) and if DRRS is supported (to make sure the
7323 * registers are not unnecessarily read).
7325 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7326 crtc
->config
.has_drrs
) {
7327 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7328 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7329 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7331 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7332 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7333 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7336 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7337 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7338 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7340 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7341 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7342 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7346 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7347 struct intel_crtc_config
*pipe_config
)
7349 if (crtc
->config
.has_pch_encoder
)
7350 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7352 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7353 &pipe_config
->dp_m_n
,
7354 &pipe_config
->dp_m2_n2
);
7357 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7358 struct intel_crtc_config
*pipe_config
)
7360 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7361 &pipe_config
->fdi_m_n
, NULL
);
7364 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7365 struct intel_crtc_config
*pipe_config
)
7367 struct drm_device
*dev
= crtc
->base
.dev
;
7368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7371 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7373 if (tmp
& PF_ENABLE
) {
7374 pipe_config
->pch_pfit
.enabled
= true;
7375 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7376 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7378 /* We currently do not free assignements of panel fitters on
7379 * ivb/hsw (since we don't use the higher upscaling modes which
7380 * differentiates them) so just WARN about this case for now. */
7382 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7383 PF_PIPE_SEL_IVB(crtc
->pipe
));
7388 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7389 struct intel_plane_config
*plane_config
)
7391 struct drm_device
*dev
= crtc
->base
.dev
;
7392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7393 u32 val
, base
, offset
;
7394 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7395 int fourcc
, pixel_format
;
7398 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7399 if (!crtc
->base
.primary
->fb
) {
7400 DRM_DEBUG_KMS("failed to alloc fb\n");
7404 val
= I915_READ(DSPCNTR(plane
));
7406 if (INTEL_INFO(dev
)->gen
>= 4)
7407 if (val
& DISPPLANE_TILED
)
7408 plane_config
->tiled
= true;
7410 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7411 fourcc
= intel_format_to_fourcc(pixel_format
);
7412 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7413 crtc
->base
.primary
->fb
->bits_per_pixel
=
7414 drm_format_plane_cpp(fourcc
, 0) * 8;
7416 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7417 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7418 offset
= I915_READ(DSPOFFSET(plane
));
7420 if (plane_config
->tiled
)
7421 offset
= I915_READ(DSPTILEOFF(plane
));
7423 offset
= I915_READ(DSPLINOFF(plane
));
7425 plane_config
->base
= base
;
7427 val
= I915_READ(PIPESRC(pipe
));
7428 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7429 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7431 val
= I915_READ(DSPSTRIDE(pipe
));
7432 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7434 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7435 plane_config
->tiled
);
7437 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7440 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7441 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7442 crtc
->base
.primary
->fb
->height
,
7443 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7444 crtc
->base
.primary
->fb
->pitches
[0],
7445 plane_config
->size
);
7448 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7449 struct intel_crtc_config
*pipe_config
)
7451 struct drm_device
*dev
= crtc
->base
.dev
;
7452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7455 if (!intel_display_power_enabled(dev_priv
,
7456 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7459 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7460 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7462 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7463 if (!(tmp
& PIPECONF_ENABLE
))
7466 switch (tmp
& PIPECONF_BPC_MASK
) {
7468 pipe_config
->pipe_bpp
= 18;
7471 pipe_config
->pipe_bpp
= 24;
7473 case PIPECONF_10BPC
:
7474 pipe_config
->pipe_bpp
= 30;
7476 case PIPECONF_12BPC
:
7477 pipe_config
->pipe_bpp
= 36;
7483 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7484 pipe_config
->limited_color_range
= true;
7486 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7487 struct intel_shared_dpll
*pll
;
7489 pipe_config
->has_pch_encoder
= true;
7491 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7492 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7493 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7495 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7497 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7498 pipe_config
->shared_dpll
=
7499 (enum intel_dpll_id
) crtc
->pipe
;
7501 tmp
= I915_READ(PCH_DPLL_SEL
);
7502 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7503 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7505 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7508 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7510 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7511 &pipe_config
->dpll_hw_state
));
7513 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7514 pipe_config
->pixel_multiplier
=
7515 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7516 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7518 ironlake_pch_clock_get(crtc
, pipe_config
);
7520 pipe_config
->pixel_multiplier
= 1;
7523 intel_get_pipe_timings(crtc
, pipe_config
);
7525 ironlake_get_pfit_config(crtc
, pipe_config
);
7530 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7532 struct drm_device
*dev
= dev_priv
->dev
;
7533 struct intel_crtc
*crtc
;
7535 for_each_intel_crtc(dev
, crtc
)
7536 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7537 pipe_name(crtc
->pipe
));
7539 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7540 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7541 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7542 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7543 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7544 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7545 "CPU PWM1 enabled\n");
7546 if (IS_HASWELL(dev
))
7547 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7548 "CPU PWM2 enabled\n");
7549 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7550 "PCH PWM1 enabled\n");
7551 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7552 "Utility pin enabled\n");
7553 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7556 * In theory we can still leave IRQs enabled, as long as only the HPD
7557 * interrupts remain enabled. We used to check for that, but since it's
7558 * gen-specific and since we only disable LCPLL after we fully disable
7559 * the interrupts, the check below should be enough.
7561 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7564 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7566 struct drm_device
*dev
= dev_priv
->dev
;
7568 if (IS_HASWELL(dev
))
7569 return I915_READ(D_COMP_HSW
);
7571 return I915_READ(D_COMP_BDW
);
7574 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7576 struct drm_device
*dev
= dev_priv
->dev
;
7578 if (IS_HASWELL(dev
)) {
7579 mutex_lock(&dev_priv
->rps
.hw_lock
);
7580 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7582 DRM_ERROR("Failed to write to D_COMP\n");
7583 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7585 I915_WRITE(D_COMP_BDW
, val
);
7586 POSTING_READ(D_COMP_BDW
);
7591 * This function implements pieces of two sequences from BSpec:
7592 * - Sequence for display software to disable LCPLL
7593 * - Sequence for display software to allow package C8+
7594 * The steps implemented here are just the steps that actually touch the LCPLL
7595 * register. Callers should take care of disabling all the display engine
7596 * functions, doing the mode unset, fixing interrupts, etc.
7598 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7599 bool switch_to_fclk
, bool allow_power_down
)
7603 assert_can_disable_lcpll(dev_priv
);
7605 val
= I915_READ(LCPLL_CTL
);
7607 if (switch_to_fclk
) {
7608 val
|= LCPLL_CD_SOURCE_FCLK
;
7609 I915_WRITE(LCPLL_CTL
, val
);
7611 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7612 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7613 DRM_ERROR("Switching to FCLK failed\n");
7615 val
= I915_READ(LCPLL_CTL
);
7618 val
|= LCPLL_PLL_DISABLE
;
7619 I915_WRITE(LCPLL_CTL
, val
);
7620 POSTING_READ(LCPLL_CTL
);
7622 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7623 DRM_ERROR("LCPLL still locked\n");
7625 val
= hsw_read_dcomp(dev_priv
);
7626 val
|= D_COMP_COMP_DISABLE
;
7627 hsw_write_dcomp(dev_priv
, val
);
7630 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7632 DRM_ERROR("D_COMP RCOMP still in progress\n");
7634 if (allow_power_down
) {
7635 val
= I915_READ(LCPLL_CTL
);
7636 val
|= LCPLL_POWER_DOWN_ALLOW
;
7637 I915_WRITE(LCPLL_CTL
, val
);
7638 POSTING_READ(LCPLL_CTL
);
7643 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7646 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7649 unsigned long irqflags
;
7651 val
= I915_READ(LCPLL_CTL
);
7653 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7654 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7658 * Make sure we're not on PC8 state before disabling PC8, otherwise
7659 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7661 * The other problem is that hsw_restore_lcpll() is called as part of
7662 * the runtime PM resume sequence, so we can't just call
7663 * gen6_gt_force_wake_get() because that function calls
7664 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7665 * while we are on the resume sequence. So to solve this problem we have
7666 * to call special forcewake code that doesn't touch runtime PM and
7667 * doesn't enable the forcewake delayed work.
7669 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7670 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7671 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7672 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7674 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7675 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7676 I915_WRITE(LCPLL_CTL
, val
);
7677 POSTING_READ(LCPLL_CTL
);
7680 val
= hsw_read_dcomp(dev_priv
);
7681 val
|= D_COMP_COMP_FORCE
;
7682 val
&= ~D_COMP_COMP_DISABLE
;
7683 hsw_write_dcomp(dev_priv
, val
);
7685 val
= I915_READ(LCPLL_CTL
);
7686 val
&= ~LCPLL_PLL_DISABLE
;
7687 I915_WRITE(LCPLL_CTL
, val
);
7689 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7690 DRM_ERROR("LCPLL not locked yet\n");
7692 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7693 val
= I915_READ(LCPLL_CTL
);
7694 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7695 I915_WRITE(LCPLL_CTL
, val
);
7697 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7698 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7699 DRM_ERROR("Switching back to LCPLL failed\n");
7702 /* See the big comment above. */
7703 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7704 if (--dev_priv
->uncore
.forcewake_count
== 0)
7705 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7706 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7710 * Package states C8 and deeper are really deep PC states that can only be
7711 * reached when all the devices on the system allow it, so even if the graphics
7712 * device allows PC8+, it doesn't mean the system will actually get to these
7713 * states. Our driver only allows PC8+ when going into runtime PM.
7715 * The requirements for PC8+ are that all the outputs are disabled, the power
7716 * well is disabled and most interrupts are disabled, and these are also
7717 * requirements for runtime PM. When these conditions are met, we manually do
7718 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7719 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7722 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7723 * the state of some registers, so when we come back from PC8+ we need to
7724 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7725 * need to take care of the registers kept by RC6. Notice that this happens even
7726 * if we don't put the device in PCI D3 state (which is what currently happens
7727 * because of the runtime PM support).
7729 * For more, read "Display Sequences for Package C8" on the hardware
7732 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7734 struct drm_device
*dev
= dev_priv
->dev
;
7737 DRM_DEBUG_KMS("Enabling package C8+\n");
7739 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7740 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7741 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7742 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7745 lpt_disable_clkout_dp(dev
);
7746 hsw_disable_lcpll(dev_priv
, true, true);
7749 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7751 struct drm_device
*dev
= dev_priv
->dev
;
7754 DRM_DEBUG_KMS("Disabling package C8+\n");
7756 hsw_restore_lcpll(dev_priv
);
7757 lpt_init_pch_refclk(dev
);
7759 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7760 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7761 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7762 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7765 intel_prepare_ddi(dev
);
7768 static void snb_modeset_global_resources(struct drm_device
*dev
)
7770 modeset_update_crtc_power_domains(dev
);
7773 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7775 modeset_update_crtc_power_domains(dev
);
7778 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7780 struct drm_framebuffer
*fb
)
7782 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7784 if (!intel_ddi_pll_select(intel_crtc
))
7787 intel_crtc
->lowfreq_avail
= false;
7792 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7794 struct intel_crtc_config
*pipe_config
)
7796 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7798 switch (pipe_config
->ddi_pll_sel
) {
7799 case PORT_CLK_SEL_WRPLL1
:
7800 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7802 case PORT_CLK_SEL_WRPLL2
:
7803 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7808 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7809 struct intel_crtc_config
*pipe_config
)
7811 struct drm_device
*dev
= crtc
->base
.dev
;
7812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7813 struct intel_shared_dpll
*pll
;
7817 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7819 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7821 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
7823 if (pipe_config
->shared_dpll
>= 0) {
7824 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7826 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7827 &pipe_config
->dpll_hw_state
));
7831 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7832 * DDI E. So just check whether this pipe is wired to DDI E and whether
7833 * the PCH transcoder is on.
7835 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7836 pipe_config
->has_pch_encoder
= true;
7838 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7839 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7840 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7842 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7846 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7847 struct intel_crtc_config
*pipe_config
)
7849 struct drm_device
*dev
= crtc
->base
.dev
;
7850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7851 enum intel_display_power_domain pfit_domain
;
7854 if (!intel_display_power_enabled(dev_priv
,
7855 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7858 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7859 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7861 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7862 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7863 enum pipe trans_edp_pipe
;
7864 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7866 WARN(1, "unknown pipe linked to edp transcoder\n");
7867 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7868 case TRANS_DDI_EDP_INPUT_A_ON
:
7869 trans_edp_pipe
= PIPE_A
;
7871 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7872 trans_edp_pipe
= PIPE_B
;
7874 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7875 trans_edp_pipe
= PIPE_C
;
7879 if (trans_edp_pipe
== crtc
->pipe
)
7880 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7883 if (!intel_display_power_enabled(dev_priv
,
7884 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7887 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7888 if (!(tmp
& PIPECONF_ENABLE
))
7891 haswell_get_ddi_port_state(crtc
, pipe_config
);
7893 intel_get_pipe_timings(crtc
, pipe_config
);
7895 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7896 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7897 ironlake_get_pfit_config(crtc
, pipe_config
);
7899 if (IS_HASWELL(dev
))
7900 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7901 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7903 pipe_config
->pixel_multiplier
= 1;
7911 } hdmi_audio_clock
[] = {
7912 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7913 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7914 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7915 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7916 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7917 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7918 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7919 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7920 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7921 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7924 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7925 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7929 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7930 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7934 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7935 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7939 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7940 hdmi_audio_clock
[i
].clock
,
7941 hdmi_audio_clock
[i
].config
);
7943 return hdmi_audio_clock
[i
].config
;
7946 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7947 int reg_eldv
, uint32_t bits_eldv
,
7948 int reg_elda
, uint32_t bits_elda
,
7951 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7952 uint8_t *eld
= connector
->eld
;
7955 i
= I915_READ(reg_eldv
);
7964 i
= I915_READ(reg_elda
);
7966 I915_WRITE(reg_elda
, i
);
7968 for (i
= 0; i
< eld
[2]; i
++)
7969 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7975 static void g4x_write_eld(struct drm_connector
*connector
,
7976 struct drm_crtc
*crtc
,
7977 struct drm_display_mode
*mode
)
7979 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7980 uint8_t *eld
= connector
->eld
;
7985 i
= I915_READ(G4X_AUD_VID_DID
);
7987 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7988 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7990 eldv
= G4X_ELDV_DEVCTG
;
7992 if (intel_eld_uptodate(connector
,
7993 G4X_AUD_CNTL_ST
, eldv
,
7994 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7995 G4X_HDMIW_HDMIEDID
))
7998 i
= I915_READ(G4X_AUD_CNTL_ST
);
7999 i
&= ~(eldv
| G4X_ELD_ADDR
);
8000 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
8001 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
8006 len
= min_t(uint8_t, eld
[2], len
);
8007 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8008 for (i
= 0; i
< len
; i
++)
8009 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
8011 i
= I915_READ(G4X_AUD_CNTL_ST
);
8013 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
8016 static void haswell_write_eld(struct drm_connector
*connector
,
8017 struct drm_crtc
*crtc
,
8018 struct drm_display_mode
*mode
)
8020 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
8021 uint8_t *eld
= connector
->eld
;
8025 int pipe
= to_intel_crtc(crtc
)->pipe
;
8028 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
8029 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
8030 int aud_config
= HSW_AUD_CFG(pipe
);
8031 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
8033 /* Audio output enable */
8034 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8035 tmp
= I915_READ(aud_cntrl_st2
);
8036 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
8037 I915_WRITE(aud_cntrl_st2
, tmp
);
8038 POSTING_READ(aud_cntrl_st2
);
8040 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
8042 /* Set ELD valid state */
8043 tmp
= I915_READ(aud_cntrl_st2
);
8044 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
8045 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
8046 I915_WRITE(aud_cntrl_st2
, tmp
);
8047 tmp
= I915_READ(aud_cntrl_st2
);
8048 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
8050 /* Enable HDMI mode */
8051 tmp
= I915_READ(aud_config
);
8052 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
8053 /* clear N_programing_enable and N_value_index */
8054 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
8055 I915_WRITE(aud_config
, tmp
);
8057 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8059 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
8061 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8062 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8063 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8064 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8066 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8069 if (intel_eld_uptodate(connector
,
8070 aud_cntrl_st2
, eldv
,
8071 aud_cntl_st
, IBX_ELD_ADDRESS
,
8075 i
= I915_READ(aud_cntrl_st2
);
8077 I915_WRITE(aud_cntrl_st2
, i
);
8082 i
= I915_READ(aud_cntl_st
);
8083 i
&= ~IBX_ELD_ADDRESS
;
8084 I915_WRITE(aud_cntl_st
, i
);
8085 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
8086 DRM_DEBUG_DRIVER("port num:%d\n", i
);
8088 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8089 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8090 for (i
= 0; i
< len
; i
++)
8091 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8093 i
= I915_READ(aud_cntrl_st2
);
8095 I915_WRITE(aud_cntrl_st2
, i
);
8099 static void ironlake_write_eld(struct drm_connector
*connector
,
8100 struct drm_crtc
*crtc
,
8101 struct drm_display_mode
*mode
)
8103 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
8104 uint8_t *eld
= connector
->eld
;
8112 int pipe
= to_intel_crtc(crtc
)->pipe
;
8114 if (HAS_PCH_IBX(connector
->dev
)) {
8115 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
8116 aud_config
= IBX_AUD_CFG(pipe
);
8117 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
8118 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
8119 } else if (IS_VALLEYVIEW(connector
->dev
)) {
8120 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
8121 aud_config
= VLV_AUD_CFG(pipe
);
8122 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
8123 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
8125 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
8126 aud_config
= CPT_AUD_CFG(pipe
);
8127 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
8128 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
8131 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8133 if (IS_VALLEYVIEW(connector
->dev
)) {
8134 struct intel_encoder
*intel_encoder
;
8135 struct intel_digital_port
*intel_dig_port
;
8137 intel_encoder
= intel_attached_encoder(connector
);
8138 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
8139 i
= intel_dig_port
->port
;
8141 i
= I915_READ(aud_cntl_st
);
8142 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
8143 /* DIP_Port_Select, 0x1 = PortB */
8147 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8148 /* operate blindly on all ports */
8149 eldv
= IBX_ELD_VALIDB
;
8150 eldv
|= IBX_ELD_VALIDB
<< 4;
8151 eldv
|= IBX_ELD_VALIDB
<< 8;
8153 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
8154 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
8157 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8158 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8159 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8160 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8162 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8165 if (intel_eld_uptodate(connector
,
8166 aud_cntrl_st2
, eldv
,
8167 aud_cntl_st
, IBX_ELD_ADDRESS
,
8171 i
= I915_READ(aud_cntrl_st2
);
8173 I915_WRITE(aud_cntrl_st2
, i
);
8178 i
= I915_READ(aud_cntl_st
);
8179 i
&= ~IBX_ELD_ADDRESS
;
8180 I915_WRITE(aud_cntl_st
, i
);
8182 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8183 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8184 for (i
= 0; i
< len
; i
++)
8185 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8187 i
= I915_READ(aud_cntrl_st2
);
8189 I915_WRITE(aud_cntrl_st2
, i
);
8192 void intel_write_eld(struct drm_encoder
*encoder
,
8193 struct drm_display_mode
*mode
)
8195 struct drm_crtc
*crtc
= encoder
->crtc
;
8196 struct drm_connector
*connector
;
8197 struct drm_device
*dev
= encoder
->dev
;
8198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8200 connector
= drm_select_eld(encoder
, mode
);
8204 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8207 connector
->encoder
->base
.id
,
8208 connector
->encoder
->name
);
8210 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
8212 if (dev_priv
->display
.write_eld
)
8213 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
8216 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8218 struct drm_device
*dev
= crtc
->dev
;
8219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8220 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8221 uint32_t cntl
= 0, size
= 0;
8224 unsigned int width
= intel_crtc
->cursor_width
;
8225 unsigned int height
= intel_crtc
->cursor_height
;
8226 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8230 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8241 cntl
|= CURSOR_ENABLE
|
8242 CURSOR_GAMMA_ENABLE
|
8243 CURSOR_FORMAT_ARGB
|
8244 CURSOR_STRIDE(stride
);
8246 size
= (height
<< 12) | width
;
8249 if (intel_crtc
->cursor_cntl
!= 0 &&
8250 (intel_crtc
->cursor_base
!= base
||
8251 intel_crtc
->cursor_size
!= size
||
8252 intel_crtc
->cursor_cntl
!= cntl
)) {
8253 /* On these chipsets we can only modify the base/size/stride
8254 * whilst the cursor is disabled.
8256 I915_WRITE(_CURACNTR
, 0);
8257 POSTING_READ(_CURACNTR
);
8258 intel_crtc
->cursor_cntl
= 0;
8261 if (intel_crtc
->cursor_base
!= base
)
8262 I915_WRITE(_CURABASE
, base
);
8264 if (intel_crtc
->cursor_size
!= size
) {
8265 I915_WRITE(CURSIZE
, size
);
8266 intel_crtc
->cursor_size
= size
;
8269 if (intel_crtc
->cursor_cntl
!= cntl
) {
8270 I915_WRITE(_CURACNTR
, cntl
);
8271 POSTING_READ(_CURACNTR
);
8272 intel_crtc
->cursor_cntl
= cntl
;
8276 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8278 struct drm_device
*dev
= crtc
->dev
;
8279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8280 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8281 int pipe
= intel_crtc
->pipe
;
8286 cntl
= MCURSOR_GAMMA_ENABLE
;
8287 switch (intel_crtc
->cursor_width
) {
8289 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8292 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8295 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8301 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8303 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8304 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8306 if (intel_crtc
->cursor_cntl
!= cntl
) {
8307 I915_WRITE(CURCNTR(pipe
), cntl
);
8308 POSTING_READ(CURCNTR(pipe
));
8309 intel_crtc
->cursor_cntl
= cntl
;
8312 /* and commit changes on next vblank */
8313 I915_WRITE(CURBASE(pipe
), base
);
8314 POSTING_READ(CURBASE(pipe
));
8317 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8318 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8321 struct drm_device
*dev
= crtc
->dev
;
8322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8323 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8324 int pipe
= intel_crtc
->pipe
;
8325 int x
= crtc
->cursor_x
;
8326 int y
= crtc
->cursor_y
;
8327 u32 base
= 0, pos
= 0;
8330 base
= intel_crtc
->cursor_addr
;
8332 if (x
>= intel_crtc
->config
.pipe_src_w
)
8335 if (y
>= intel_crtc
->config
.pipe_src_h
)
8339 if (x
+ intel_crtc
->cursor_width
<= 0)
8342 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8345 pos
|= x
<< CURSOR_X_SHIFT
;
8348 if (y
+ intel_crtc
->cursor_height
<= 0)
8351 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8354 pos
|= y
<< CURSOR_Y_SHIFT
;
8356 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8359 I915_WRITE(CURPOS(pipe
), pos
);
8361 if (IS_845G(dev
) || IS_I865G(dev
))
8362 i845_update_cursor(crtc
, base
);
8364 i9xx_update_cursor(crtc
, base
);
8365 intel_crtc
->cursor_base
= base
;
8368 static bool cursor_size_ok(struct drm_device
*dev
,
8369 uint32_t width
, uint32_t height
)
8371 if (width
== 0 || height
== 0)
8375 * 845g/865g are special in that they are only limited by
8376 * the width of their cursors, the height is arbitrary up to
8377 * the precision of the register. Everything else requires
8378 * square cursors, limited to a few power-of-two sizes.
8380 if (IS_845G(dev
) || IS_I865G(dev
)) {
8381 if ((width
& 63) != 0)
8384 if (width
> (IS_845G(dev
) ? 64 : 512))
8390 switch (width
| height
) {
8406 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8408 * Note that the object's reference will be consumed if the update fails. If
8409 * the update succeeds, the reference of the old object (if any) will be
8412 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8413 struct drm_i915_gem_object
*obj
,
8414 uint32_t width
, uint32_t height
)
8416 struct drm_device
*dev
= crtc
->dev
;
8417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8418 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8419 enum pipe pipe
= intel_crtc
->pipe
;
8420 unsigned old_width
, stride
;
8424 /* if we want to turn off the cursor ignore width and height */
8426 DRM_DEBUG_KMS("cursor off\n");
8428 mutex_lock(&dev
->struct_mutex
);
8432 /* Check for which cursor types we support */
8433 if (!cursor_size_ok(dev
, width
, height
)) {
8434 DRM_DEBUG("Cursor dimension not supported\n");
8438 stride
= roundup_pow_of_two(width
) * 4;
8439 if (obj
->base
.size
< stride
* height
) {
8440 DRM_DEBUG_KMS("buffer is too small\n");
8445 /* we only need to pin inside GTT if cursor is non-phy */
8446 mutex_lock(&dev
->struct_mutex
);
8447 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8450 if (obj
->tiling_mode
) {
8451 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8457 * Global gtt pte registers are special registers which actually
8458 * forward writes to a chunk of system memory. Which means that
8459 * there is no risk that the register values disappear as soon
8460 * as we call intel_runtime_pm_put(), so it is correct to wrap
8461 * only the pin/unpin/fence and not more.
8463 intel_runtime_pm_get(dev_priv
);
8465 /* Note that the w/a also requires 2 PTE of padding following
8466 * the bo. We currently fill all unused PTE with the shadow
8467 * page and so we should always have valid PTE following the
8468 * cursor preventing the VT-d warning.
8471 if (need_vtd_wa(dev
))
8472 alignment
= 64*1024;
8474 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8476 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8477 intel_runtime_pm_put(dev_priv
);
8481 ret
= i915_gem_object_put_fence(obj
);
8483 DRM_DEBUG_KMS("failed to release fence for cursor");
8484 intel_runtime_pm_put(dev_priv
);
8488 addr
= i915_gem_obj_ggtt_offset(obj
);
8490 intel_runtime_pm_put(dev_priv
);
8492 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8493 ret
= i915_gem_object_attach_phys(obj
, align
);
8495 DRM_DEBUG_KMS("failed to attach phys object\n");
8498 addr
= obj
->phys_handle
->busaddr
;
8502 if (intel_crtc
->cursor_bo
) {
8503 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8504 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8507 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8508 INTEL_FRONTBUFFER_CURSOR(pipe
));
8509 mutex_unlock(&dev
->struct_mutex
);
8511 old_width
= intel_crtc
->cursor_width
;
8513 intel_crtc
->cursor_addr
= addr
;
8514 intel_crtc
->cursor_bo
= obj
;
8515 intel_crtc
->cursor_width
= width
;
8516 intel_crtc
->cursor_height
= height
;
8518 if (intel_crtc
->active
) {
8519 if (old_width
!= width
)
8520 intel_update_watermarks(crtc
);
8521 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8524 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8528 i915_gem_object_unpin_from_display_plane(obj
);
8530 mutex_unlock(&dev
->struct_mutex
);
8532 drm_gem_object_unreference_unlocked(&obj
->base
);
8536 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8537 u16
*blue
, uint32_t start
, uint32_t size
)
8539 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8540 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8542 for (i
= start
; i
< end
; i
++) {
8543 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8544 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8545 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8548 intel_crtc_load_lut(crtc
);
8551 /* VESA 640x480x72Hz mode to set on the pipe */
8552 static struct drm_display_mode load_detect_mode
= {
8553 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8554 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8557 struct drm_framebuffer
*
8558 __intel_framebuffer_create(struct drm_device
*dev
,
8559 struct drm_mode_fb_cmd2
*mode_cmd
,
8560 struct drm_i915_gem_object
*obj
)
8562 struct intel_framebuffer
*intel_fb
;
8565 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8567 drm_gem_object_unreference_unlocked(&obj
->base
);
8568 return ERR_PTR(-ENOMEM
);
8571 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8575 return &intel_fb
->base
;
8577 drm_gem_object_unreference_unlocked(&obj
->base
);
8580 return ERR_PTR(ret
);
8583 static struct drm_framebuffer
*
8584 intel_framebuffer_create(struct drm_device
*dev
,
8585 struct drm_mode_fb_cmd2
*mode_cmd
,
8586 struct drm_i915_gem_object
*obj
)
8588 struct drm_framebuffer
*fb
;
8591 ret
= i915_mutex_lock_interruptible(dev
);
8593 return ERR_PTR(ret
);
8594 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8595 mutex_unlock(&dev
->struct_mutex
);
8601 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8603 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8604 return ALIGN(pitch
, 64);
8608 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8610 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8611 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8614 static struct drm_framebuffer
*
8615 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8616 struct drm_display_mode
*mode
,
8619 struct drm_i915_gem_object
*obj
;
8620 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8622 obj
= i915_gem_alloc_object(dev
,
8623 intel_framebuffer_size_for_mode(mode
, bpp
));
8625 return ERR_PTR(-ENOMEM
);
8627 mode_cmd
.width
= mode
->hdisplay
;
8628 mode_cmd
.height
= mode
->vdisplay
;
8629 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8631 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8633 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8636 static struct drm_framebuffer
*
8637 mode_fits_in_fbdev(struct drm_device
*dev
,
8638 struct drm_display_mode
*mode
)
8640 #ifdef CONFIG_DRM_I915_FBDEV
8641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8642 struct drm_i915_gem_object
*obj
;
8643 struct drm_framebuffer
*fb
;
8645 if (!dev_priv
->fbdev
)
8648 if (!dev_priv
->fbdev
->fb
)
8651 obj
= dev_priv
->fbdev
->fb
->obj
;
8654 fb
= &dev_priv
->fbdev
->fb
->base
;
8655 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8656 fb
->bits_per_pixel
))
8659 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8668 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8669 struct drm_display_mode
*mode
,
8670 struct intel_load_detect_pipe
*old
,
8671 struct drm_modeset_acquire_ctx
*ctx
)
8673 struct intel_crtc
*intel_crtc
;
8674 struct intel_encoder
*intel_encoder
=
8675 intel_attached_encoder(connector
);
8676 struct drm_crtc
*possible_crtc
;
8677 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8678 struct drm_crtc
*crtc
= NULL
;
8679 struct drm_device
*dev
= encoder
->dev
;
8680 struct drm_framebuffer
*fb
;
8681 struct drm_mode_config
*config
= &dev
->mode_config
;
8684 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8685 connector
->base
.id
, connector
->name
,
8686 encoder
->base
.id
, encoder
->name
);
8689 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8694 * Algorithm gets a little messy:
8696 * - if the connector already has an assigned crtc, use it (but make
8697 * sure it's on first)
8699 * - try to find the first unused crtc that can drive this connector,
8700 * and use that if we find one
8703 /* See if we already have a CRTC for this connector */
8704 if (encoder
->crtc
) {
8705 crtc
= encoder
->crtc
;
8707 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8711 old
->dpms_mode
= connector
->dpms
;
8712 old
->load_detect_temp
= false;
8714 /* Make sure the crtc and connector are running */
8715 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8716 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8721 /* Find an unused one (if possible) */
8722 for_each_crtc(dev
, possible_crtc
) {
8724 if (!(encoder
->possible_crtcs
& (1 << i
)))
8726 if (possible_crtc
->enabled
)
8728 /* This can occur when applying the pipe A quirk on resume. */
8729 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8732 crtc
= possible_crtc
;
8737 * If we didn't find an unused CRTC, don't use any.
8740 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8744 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8747 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8748 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8750 intel_crtc
= to_intel_crtc(crtc
);
8751 intel_crtc
->new_enabled
= true;
8752 intel_crtc
->new_config
= &intel_crtc
->config
;
8753 old
->dpms_mode
= connector
->dpms
;
8754 old
->load_detect_temp
= true;
8755 old
->release_fb
= NULL
;
8758 mode
= &load_detect_mode
;
8760 /* We need a framebuffer large enough to accommodate all accesses
8761 * that the plane may generate whilst we perform load detection.
8762 * We can not rely on the fbcon either being present (we get called
8763 * during its initialisation to detect all boot displays, or it may
8764 * not even exist) or that it is large enough to satisfy the
8767 fb
= mode_fits_in_fbdev(dev
, mode
);
8769 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8770 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8771 old
->release_fb
= fb
;
8773 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8775 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8779 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8780 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8781 if (old
->release_fb
)
8782 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8786 /* let the connector get through one full cycle before testing */
8787 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8791 intel_crtc
->new_enabled
= crtc
->enabled
;
8792 if (intel_crtc
->new_enabled
)
8793 intel_crtc
->new_config
= &intel_crtc
->config
;
8795 intel_crtc
->new_config
= NULL
;
8797 if (ret
== -EDEADLK
) {
8798 drm_modeset_backoff(ctx
);
8805 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8806 struct intel_load_detect_pipe
*old
)
8808 struct intel_encoder
*intel_encoder
=
8809 intel_attached_encoder(connector
);
8810 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8811 struct drm_crtc
*crtc
= encoder
->crtc
;
8812 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8814 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8815 connector
->base
.id
, connector
->name
,
8816 encoder
->base
.id
, encoder
->name
);
8818 if (old
->load_detect_temp
) {
8819 to_intel_connector(connector
)->new_encoder
= NULL
;
8820 intel_encoder
->new_crtc
= NULL
;
8821 intel_crtc
->new_enabled
= false;
8822 intel_crtc
->new_config
= NULL
;
8823 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8825 if (old
->release_fb
) {
8826 drm_framebuffer_unregister_private(old
->release_fb
);
8827 drm_framebuffer_unreference(old
->release_fb
);
8833 /* Switch crtc and encoder back off if necessary */
8834 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8835 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8838 static int i9xx_pll_refclk(struct drm_device
*dev
,
8839 const struct intel_crtc_config
*pipe_config
)
8841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8842 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8844 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8845 return dev_priv
->vbt
.lvds_ssc_freq
;
8846 else if (HAS_PCH_SPLIT(dev
))
8848 else if (!IS_GEN2(dev
))
8854 /* Returns the clock of the currently programmed mode of the given pipe. */
8855 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8856 struct intel_crtc_config
*pipe_config
)
8858 struct drm_device
*dev
= crtc
->base
.dev
;
8859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8860 int pipe
= pipe_config
->cpu_transcoder
;
8861 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8863 intel_clock_t clock
;
8864 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8866 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8867 fp
= pipe_config
->dpll_hw_state
.fp0
;
8869 fp
= pipe_config
->dpll_hw_state
.fp1
;
8871 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8872 if (IS_PINEVIEW(dev
)) {
8873 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8874 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8876 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8877 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8880 if (!IS_GEN2(dev
)) {
8881 if (IS_PINEVIEW(dev
))
8882 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8883 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8885 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8886 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8888 switch (dpll
& DPLL_MODE_MASK
) {
8889 case DPLLB_MODE_DAC_SERIAL
:
8890 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8893 case DPLLB_MODE_LVDS
:
8894 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8898 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8899 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8903 if (IS_PINEVIEW(dev
))
8904 pineview_clock(refclk
, &clock
);
8906 i9xx_clock(refclk
, &clock
);
8908 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8909 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8912 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8913 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8915 if (lvds
& LVDS_CLKB_POWER_UP
)
8920 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8923 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8924 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8926 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8932 i9xx_clock(refclk
, &clock
);
8936 * This value includes pixel_multiplier. We will use
8937 * port_clock to compute adjusted_mode.crtc_clock in the
8938 * encoder's get_config() function.
8940 pipe_config
->port_clock
= clock
.dot
;
8943 int intel_dotclock_calculate(int link_freq
,
8944 const struct intel_link_m_n
*m_n
)
8947 * The calculation for the data clock is:
8948 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8949 * But we want to avoid losing precison if possible, so:
8950 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8952 * and the link clock is simpler:
8953 * link_clock = (m * link_clock) / n
8959 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8962 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8963 struct intel_crtc_config
*pipe_config
)
8965 struct drm_device
*dev
= crtc
->base
.dev
;
8967 /* read out port_clock from the DPLL */
8968 i9xx_crtc_clock_get(crtc
, pipe_config
);
8971 * This value does not include pixel_multiplier.
8972 * We will check that port_clock and adjusted_mode.crtc_clock
8973 * agree once we know their relationship in the encoder's
8974 * get_config() function.
8976 pipe_config
->adjusted_mode
.crtc_clock
=
8977 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8978 &pipe_config
->fdi_m_n
);
8981 /** Returns the currently programmed mode of the given pipe. */
8982 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8983 struct drm_crtc
*crtc
)
8985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8986 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8987 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8988 struct drm_display_mode
*mode
;
8989 struct intel_crtc_config pipe_config
;
8990 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8991 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8992 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8993 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8994 enum pipe pipe
= intel_crtc
->pipe
;
8996 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
9001 * Construct a pipe_config sufficient for getting the clock info
9002 * back out of crtc_clock_get.
9004 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9005 * to use a real value here instead.
9007 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
9008 pipe_config
.pixel_multiplier
= 1;
9009 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
9010 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
9011 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
9012 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
9014 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
9015 mode
->hdisplay
= (htot
& 0xffff) + 1;
9016 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
9017 mode
->hsync_start
= (hsync
& 0xffff) + 1;
9018 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
9019 mode
->vdisplay
= (vtot
& 0xffff) + 1;
9020 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
9021 mode
->vsync_start
= (vsync
& 0xffff) + 1;
9022 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
9024 drm_mode_set_name(mode
);
9029 static void intel_increase_pllclock(struct drm_device
*dev
,
9032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9033 int dpll_reg
= DPLL(pipe
);
9036 if (!HAS_GMCH_DISPLAY(dev
))
9039 if (!dev_priv
->lvds_downclock_avail
)
9042 dpll
= I915_READ(dpll_reg
);
9043 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
9044 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9046 assert_panel_unlocked(dev_priv
, pipe
);
9048 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
9049 I915_WRITE(dpll_reg
, dpll
);
9050 intel_wait_for_vblank(dev
, pipe
);
9052 dpll
= I915_READ(dpll_reg
);
9053 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
9054 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9058 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
9060 struct drm_device
*dev
= crtc
->dev
;
9061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9062 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9064 if (!HAS_GMCH_DISPLAY(dev
))
9067 if (!dev_priv
->lvds_downclock_avail
)
9071 * Since this is called by a timer, we should never get here in
9074 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9075 int pipe
= intel_crtc
->pipe
;
9076 int dpll_reg
= DPLL(pipe
);
9079 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9081 assert_panel_unlocked(dev_priv
, pipe
);
9083 dpll
= I915_READ(dpll_reg
);
9084 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9085 I915_WRITE(dpll_reg
, dpll
);
9086 intel_wait_for_vblank(dev
, pipe
);
9087 dpll
= I915_READ(dpll_reg
);
9088 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9089 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9094 void intel_mark_busy(struct drm_device
*dev
)
9096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9098 if (dev_priv
->mm
.busy
)
9101 intel_runtime_pm_get(dev_priv
);
9102 i915_update_gfx_val(dev_priv
);
9103 dev_priv
->mm
.busy
= true;
9106 void intel_mark_idle(struct drm_device
*dev
)
9108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9109 struct drm_crtc
*crtc
;
9111 if (!dev_priv
->mm
.busy
)
9114 dev_priv
->mm
.busy
= false;
9116 if (!i915
.powersave
)
9119 for_each_crtc(dev
, crtc
) {
9120 if (!crtc
->primary
->fb
)
9123 intel_decrease_pllclock(crtc
);
9126 if (INTEL_INFO(dev
)->gen
>= 6)
9127 gen6_rps_idle(dev
->dev_private
);
9130 intel_runtime_pm_put(dev_priv
);
9135 * intel_mark_fb_busy - mark given planes as busy
9137 * @frontbuffer_bits: bits for the affected planes
9138 * @ring: optional ring for asynchronous commands
9140 * This function gets called every time the screen contents change. It can be
9141 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9143 static void intel_mark_fb_busy(struct drm_device
*dev
,
9144 unsigned frontbuffer_bits
,
9145 struct intel_engine_cs
*ring
)
9147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9150 if (!i915
.powersave
)
9153 for_each_pipe(dev_priv
, pipe
) {
9154 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
9157 intel_increase_pllclock(dev
, pipe
);
9158 if (ring
&& intel_fbc_enabled(dev
))
9159 ring
->fbc_dirty
= true;
9164 * intel_fb_obj_invalidate - invalidate frontbuffer object
9165 * @obj: GEM object to invalidate
9166 * @ring: set for asynchronous rendering
9168 * This function gets called every time rendering on the given object starts and
9169 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9170 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9171 * until the rendering completes or a flip on this frontbuffer plane is
9174 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
9175 struct intel_engine_cs
*ring
)
9177 struct drm_device
*dev
= obj
->base
.dev
;
9178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9180 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9182 if (!obj
->frontbuffer_bits
)
9186 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9187 dev_priv
->fb_tracking
.busy_bits
9188 |= obj
->frontbuffer_bits
;
9189 dev_priv
->fb_tracking
.flip_bits
9190 &= ~obj
->frontbuffer_bits
;
9191 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9194 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
9196 intel_edp_psr_invalidate(dev
, obj
->frontbuffer_bits
);
9200 * intel_frontbuffer_flush - flush frontbuffer
9202 * @frontbuffer_bits: frontbuffer plane tracking bits
9204 * This function gets called every time rendering on the given planes has
9205 * completed and frontbuffer caching can be started again. Flushes will get
9206 * delayed if they're blocked by some oustanding asynchronous rendering.
9208 * Can be called without any locks held.
9210 void intel_frontbuffer_flush(struct drm_device
*dev
,
9211 unsigned frontbuffer_bits
)
9213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9215 /* Delay flushing when rings are still busy.*/
9216 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9217 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
9218 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9220 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
9222 intel_edp_psr_flush(dev
, frontbuffer_bits
);
9225 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9226 * needs to be reworked into a proper frontbuffer tracking scheme like
9229 if (IS_BROADWELL(dev
))
9230 gen8_fbc_sw_flush(dev
, FBC_REND_CACHE_CLEAN
);
9234 * intel_fb_obj_flush - flush frontbuffer object
9235 * @obj: GEM object to flush
9236 * @retire: set when retiring asynchronous rendering
9238 * This function gets called every time rendering on the given object has
9239 * completed and frontbuffer caching can be started again. If @retire is true
9240 * then any delayed flushes will be unblocked.
9242 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
9245 struct drm_device
*dev
= obj
->base
.dev
;
9246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9247 unsigned frontbuffer_bits
;
9249 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9251 if (!obj
->frontbuffer_bits
)
9254 frontbuffer_bits
= obj
->frontbuffer_bits
;
9257 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9258 /* Filter out new bits since rendering started. */
9259 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9261 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9262 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9265 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9269 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9271 * @frontbuffer_bits: frontbuffer plane tracking bits
9273 * This function gets called after scheduling a flip on @obj. The actual
9274 * frontbuffer flushing will be delayed until completion is signalled with
9275 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9276 * flush will be cancelled.
9278 * Can be called without any locks held.
9280 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9281 unsigned frontbuffer_bits
)
9283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9285 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9286 dev_priv
->fb_tracking
.flip_bits
9287 |= frontbuffer_bits
;
9288 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9292 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9294 * @frontbuffer_bits: frontbuffer plane tracking bits
9296 * This function gets called after the flip has been latched and will complete
9297 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9299 * Can be called without any locks held.
9301 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9302 unsigned frontbuffer_bits
)
9304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9306 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9307 /* Mask any cancelled flips. */
9308 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9309 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9310 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9312 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9315 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9318 struct drm_device
*dev
= crtc
->dev
;
9319 struct intel_unpin_work
*work
;
9320 unsigned long flags
;
9322 spin_lock_irqsave(&dev
->event_lock
, flags
);
9323 work
= intel_crtc
->unpin_work
;
9324 intel_crtc
->unpin_work
= NULL
;
9325 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9328 cancel_work_sync(&work
->work
);
9332 drm_crtc_cleanup(crtc
);
9337 static void intel_unpin_work_fn(struct work_struct
*__work
)
9339 struct intel_unpin_work
*work
=
9340 container_of(__work
, struct intel_unpin_work
, work
);
9341 struct drm_device
*dev
= work
->crtc
->dev
;
9342 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9344 mutex_lock(&dev
->struct_mutex
);
9345 intel_unpin_fb_obj(work
->old_fb_obj
);
9346 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9347 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9349 intel_update_fbc(dev
);
9350 mutex_unlock(&dev
->struct_mutex
);
9352 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9354 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9355 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9360 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9361 struct drm_crtc
*crtc
)
9363 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9364 struct intel_unpin_work
*work
;
9365 unsigned long flags
;
9367 /* Ignore early vblank irqs */
9368 if (intel_crtc
== NULL
)
9371 spin_lock_irqsave(&dev
->event_lock
, flags
);
9372 work
= intel_crtc
->unpin_work
;
9374 /* Ensure we don't miss a work->pending update ... */
9377 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9378 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9382 page_flip_completed(intel_crtc
);
9384 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9387 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9390 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9392 do_intel_finish_page_flip(dev
, crtc
);
9395 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9398 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9400 do_intel_finish_page_flip(dev
, crtc
);
9403 /* Is 'a' after or equal to 'b'? */
9404 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9406 return !((a
- b
) & 0x80000000);
9409 static bool page_flip_finished(struct intel_crtc
*crtc
)
9411 struct drm_device
*dev
= crtc
->base
.dev
;
9412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9415 * The relevant registers doen't exist on pre-ctg.
9416 * As the flip done interrupt doesn't trigger for mmio
9417 * flips on gmch platforms, a flip count check isn't
9418 * really needed there. But since ctg has the registers,
9419 * include it in the check anyway.
9421 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9425 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9426 * used the same base address. In that case the mmio flip might
9427 * have completed, but the CS hasn't even executed the flip yet.
9429 * A flip count check isn't enough as the CS might have updated
9430 * the base address just after start of vblank, but before we
9431 * managed to process the interrupt. This means we'd complete the
9434 * Combining both checks should get us a good enough result. It may
9435 * still happen that the CS flip has been executed, but has not
9436 * yet actually completed. But in case the base address is the same
9437 * anyway, we don't really care.
9439 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9440 crtc
->unpin_work
->gtt_offset
&&
9441 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9442 crtc
->unpin_work
->flip_count
);
9445 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9448 struct intel_crtc
*intel_crtc
=
9449 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9450 unsigned long flags
;
9452 /* NB: An MMIO update of the plane base pointer will also
9453 * generate a page-flip completion irq, i.e. every modeset
9454 * is also accompanied by a spurious intel_prepare_page_flip().
9456 spin_lock_irqsave(&dev
->event_lock
, flags
);
9457 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9458 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9459 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9462 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9464 /* Ensure that the work item is consistent when activating it ... */
9466 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9467 /* and that it is marked active as soon as the irq could fire. */
9471 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9472 struct drm_crtc
*crtc
,
9473 struct drm_framebuffer
*fb
,
9474 struct drm_i915_gem_object
*obj
,
9475 struct intel_engine_cs
*ring
,
9478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9482 ret
= intel_ring_begin(ring
, 6);
9486 /* Can't queue multiple flips, so wait for the previous
9487 * one to finish before executing the next.
9489 if (intel_crtc
->plane
)
9490 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9492 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9493 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9494 intel_ring_emit(ring
, MI_NOOP
);
9495 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9496 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9497 intel_ring_emit(ring
, fb
->pitches
[0]);
9498 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9499 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9501 intel_mark_page_flip_active(intel_crtc
);
9502 __intel_ring_advance(ring
);
9506 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9507 struct drm_crtc
*crtc
,
9508 struct drm_framebuffer
*fb
,
9509 struct drm_i915_gem_object
*obj
,
9510 struct intel_engine_cs
*ring
,
9513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9517 ret
= intel_ring_begin(ring
, 6);
9521 if (intel_crtc
->plane
)
9522 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9524 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9525 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9526 intel_ring_emit(ring
, MI_NOOP
);
9527 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9528 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9529 intel_ring_emit(ring
, fb
->pitches
[0]);
9530 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9531 intel_ring_emit(ring
, MI_NOOP
);
9533 intel_mark_page_flip_active(intel_crtc
);
9534 __intel_ring_advance(ring
);
9538 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9539 struct drm_crtc
*crtc
,
9540 struct drm_framebuffer
*fb
,
9541 struct drm_i915_gem_object
*obj
,
9542 struct intel_engine_cs
*ring
,
9545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9546 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9547 uint32_t pf
, pipesrc
;
9550 ret
= intel_ring_begin(ring
, 4);
9554 /* i965+ uses the linear or tiled offsets from the
9555 * Display Registers (which do not change across a page-flip)
9556 * so we need only reprogram the base address.
9558 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9559 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9560 intel_ring_emit(ring
, fb
->pitches
[0]);
9561 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9564 /* XXX Enabling the panel-fitter across page-flip is so far
9565 * untested on non-native modes, so ignore it for now.
9566 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9569 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9570 intel_ring_emit(ring
, pf
| pipesrc
);
9572 intel_mark_page_flip_active(intel_crtc
);
9573 __intel_ring_advance(ring
);
9577 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9578 struct drm_crtc
*crtc
,
9579 struct drm_framebuffer
*fb
,
9580 struct drm_i915_gem_object
*obj
,
9581 struct intel_engine_cs
*ring
,
9584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9585 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9586 uint32_t pf
, pipesrc
;
9589 ret
= intel_ring_begin(ring
, 4);
9593 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9594 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9595 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9596 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9598 /* Contrary to the suggestions in the documentation,
9599 * "Enable Panel Fitter" does not seem to be required when page
9600 * flipping with a non-native mode, and worse causes a normal
9602 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9605 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9606 intel_ring_emit(ring
, pf
| pipesrc
);
9608 intel_mark_page_flip_active(intel_crtc
);
9609 __intel_ring_advance(ring
);
9613 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9614 struct drm_crtc
*crtc
,
9615 struct drm_framebuffer
*fb
,
9616 struct drm_i915_gem_object
*obj
,
9617 struct intel_engine_cs
*ring
,
9620 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9621 uint32_t plane_bit
= 0;
9624 switch (intel_crtc
->plane
) {
9626 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9629 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9632 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9635 WARN_ONCE(1, "unknown plane in flip command\n");
9640 if (ring
->id
== RCS
) {
9643 * On Gen 8, SRM is now taking an extra dword to accommodate
9644 * 48bits addresses, and we need a NOOP for the batch size to
9652 * BSpec MI_DISPLAY_FLIP for IVB:
9653 * "The full packet must be contained within the same cache line."
9655 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9656 * cacheline, if we ever start emitting more commands before
9657 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9658 * then do the cacheline alignment, and finally emit the
9661 ret
= intel_ring_cacheline_align(ring
);
9665 ret
= intel_ring_begin(ring
, len
);
9669 /* Unmask the flip-done completion message. Note that the bspec says that
9670 * we should do this for both the BCS and RCS, and that we must not unmask
9671 * more than one flip event at any time (or ensure that one flip message
9672 * can be sent by waiting for flip-done prior to queueing new flips).
9673 * Experimentation says that BCS works despite DERRMR masking all
9674 * flip-done completion events and that unmasking all planes at once
9675 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9676 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9678 if (ring
->id
== RCS
) {
9679 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9680 intel_ring_emit(ring
, DERRMR
);
9681 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9682 DERRMR_PIPEB_PRI_FLIP_DONE
|
9683 DERRMR_PIPEC_PRI_FLIP_DONE
));
9685 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9686 MI_SRM_LRM_GLOBAL_GTT
);
9688 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9689 MI_SRM_LRM_GLOBAL_GTT
);
9690 intel_ring_emit(ring
, DERRMR
);
9691 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9693 intel_ring_emit(ring
, 0);
9694 intel_ring_emit(ring
, MI_NOOP
);
9698 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9699 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9700 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9701 intel_ring_emit(ring
, (MI_NOOP
));
9703 intel_mark_page_flip_active(intel_crtc
);
9704 __intel_ring_advance(ring
);
9708 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9709 struct drm_i915_gem_object
*obj
)
9712 * This is not being used for older platforms, because
9713 * non-availability of flip done interrupt forces us to use
9714 * CS flips. Older platforms derive flip done using some clever
9715 * tricks involving the flip_pending status bits and vblank irqs.
9716 * So using MMIO flips there would disrupt this mechanism.
9722 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9725 if (i915
.use_mmio_flip
< 0)
9727 else if (i915
.use_mmio_flip
> 0)
9729 else if (i915
.enable_execlists
)
9732 return ring
!= obj
->ring
;
9735 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9737 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9739 struct intel_framebuffer
*intel_fb
=
9740 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9741 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9745 intel_mark_page_flip_active(intel_crtc
);
9747 reg
= DSPCNTR(intel_crtc
->plane
);
9748 dspcntr
= I915_READ(reg
);
9750 if (INTEL_INFO(dev
)->gen
>= 4) {
9751 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9752 dspcntr
|= DISPPLANE_TILED
;
9754 dspcntr
&= ~DISPPLANE_TILED
;
9756 I915_WRITE(reg
, dspcntr
);
9758 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9759 intel_crtc
->unpin_work
->gtt_offset
);
9760 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9763 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9765 struct intel_engine_cs
*ring
;
9768 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9770 if (!obj
->last_write_seqno
)
9775 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9776 obj
->last_write_seqno
))
9779 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9783 if (WARN_ON(!ring
->irq_get(ring
)))
9789 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9791 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9792 struct intel_crtc
*intel_crtc
;
9793 unsigned long irq_flags
;
9796 seqno
= ring
->get_seqno(ring
, false);
9798 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9799 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9800 struct intel_mmio_flip
*mmio_flip
;
9802 mmio_flip
= &intel_crtc
->mmio_flip
;
9803 if (mmio_flip
->seqno
== 0)
9806 if (ring
->id
!= mmio_flip
->ring_id
)
9809 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9810 intel_do_mmio_flip(intel_crtc
);
9811 mmio_flip
->seqno
= 0;
9812 ring
->irq_put(ring
);
9815 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9818 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9819 struct drm_crtc
*crtc
,
9820 struct drm_framebuffer
*fb
,
9821 struct drm_i915_gem_object
*obj
,
9822 struct intel_engine_cs
*ring
,
9825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9827 unsigned long irq_flags
;
9830 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9833 ret
= intel_postpone_flip(obj
);
9837 intel_do_mmio_flip(intel_crtc
);
9841 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9842 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9843 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9844 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9847 * Double check to catch cases where irq fired before
9848 * mmio flip data was ready
9850 intel_notify_mmio_flip(obj
->ring
);
9854 static int intel_default_queue_flip(struct drm_device
*dev
,
9855 struct drm_crtc
*crtc
,
9856 struct drm_framebuffer
*fb
,
9857 struct drm_i915_gem_object
*obj
,
9858 struct intel_engine_cs
*ring
,
9864 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9865 struct drm_crtc
*crtc
)
9867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9868 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9869 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9872 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9875 if (!work
->enable_stall_check
)
9878 if (work
->flip_ready_vblank
== 0) {
9879 if (work
->flip_queued_ring
&&
9880 !i915_seqno_passed(work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
9881 work
->flip_queued_seqno
))
9884 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9887 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9890 /* Potential stall - if we see that the flip has happened,
9891 * assume a missed interrupt. */
9892 if (INTEL_INFO(dev
)->gen
>= 4)
9893 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9895 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9897 /* There is a potential issue here with a false positive after a flip
9898 * to the same address. We could address this by checking for a
9899 * non-incrementing frame counter.
9901 return addr
== work
->gtt_offset
;
9904 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9907 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9908 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9909 unsigned long flags
;
9914 spin_lock_irqsave(&dev
->event_lock
, flags
);
9915 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9916 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9917 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9918 page_flip_completed(intel_crtc
);
9920 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9923 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9924 struct drm_framebuffer
*fb
,
9925 struct drm_pending_vblank_event
*event
,
9926 uint32_t page_flip_flags
)
9928 struct drm_device
*dev
= crtc
->dev
;
9929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9930 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9931 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9932 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9933 enum pipe pipe
= intel_crtc
->pipe
;
9934 struct intel_unpin_work
*work
;
9935 struct intel_engine_cs
*ring
;
9936 unsigned long flags
;
9939 //trigger software GT busyness calculation
9940 gen8_flip_interrupt(dev
);
9943 * drm_mode_page_flip_ioctl() should already catch this, but double
9944 * check to be safe. In the future we may enable pageflipping from
9945 * a disabled primary plane.
9947 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9950 /* Can't change pixel format via MI display flips. */
9951 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9955 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9956 * Note that pitch changes could also affect these register.
9958 if (INTEL_INFO(dev
)->gen
> 3 &&
9959 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9960 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9963 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9966 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9970 work
->event
= event
;
9972 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9973 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9975 ret
= drm_crtc_vblank_get(crtc
);
9979 /* We borrow the event spin lock for protecting unpin_work */
9980 spin_lock_irqsave(&dev
->event_lock
, flags
);
9981 if (intel_crtc
->unpin_work
) {
9982 /* Before declaring the flip queue wedged, check if
9983 * the hardware completed the operation behind our backs.
9985 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9986 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9987 page_flip_completed(intel_crtc
);
9989 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9990 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9992 drm_crtc_vblank_put(crtc
);
9997 intel_crtc
->unpin_work
= work
;
9998 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10000 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
10001 flush_workqueue(dev_priv
->wq
);
10003 ret
= i915_mutex_lock_interruptible(dev
);
10007 /* Reference the objects for the scheduled work. */
10008 drm_gem_object_reference(&work
->old_fb_obj
->base
);
10009 drm_gem_object_reference(&obj
->base
);
10011 crtc
->primary
->fb
= fb
;
10013 work
->pending_flip_obj
= obj
;
10015 atomic_inc(&intel_crtc
->unpin_work_count
);
10016 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
10018 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
10019 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
10021 if (IS_VALLEYVIEW(dev
)) {
10022 ring
= &dev_priv
->ring
[BCS
];
10023 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
10024 /* vlv: DISPLAY_FLIP fails to change tiling */
10026 } else if (IS_IVYBRIDGE(dev
)) {
10027 ring
= &dev_priv
->ring
[BCS
];
10028 } else if (INTEL_INFO(dev
)->gen
>= 7) {
10030 if (ring
== NULL
|| ring
->id
!= RCS
)
10031 ring
= &dev_priv
->ring
[BCS
];
10033 ring
= &dev_priv
->ring
[RCS
];
10036 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
10038 goto cleanup_pending
;
10041 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
10043 if (use_mmio_flip(ring
, obj
)) {
10044 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
10047 goto cleanup_unpin
;
10049 work
->flip_queued_seqno
= obj
->last_write_seqno
;
10050 work
->flip_queued_ring
= obj
->ring
;
10052 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
10055 goto cleanup_unpin
;
10057 work
->flip_queued_seqno
= intel_ring_get_seqno(ring
);
10058 work
->flip_queued_ring
= ring
;
10061 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
10062 work
->enable_stall_check
= true;
10064 i915_gem_track_fb(work
->old_fb_obj
, obj
,
10065 INTEL_FRONTBUFFER_PRIMARY(pipe
));
10067 intel_disable_fbc(dev
);
10068 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10069 mutex_unlock(&dev
->struct_mutex
);
10071 trace_i915_flip_request(intel_crtc
->plane
, obj
);
10076 intel_unpin_fb_obj(obj
);
10078 atomic_dec(&intel_crtc
->unpin_work_count
);
10079 crtc
->primary
->fb
= old_fb
;
10080 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
10081 drm_gem_object_unreference(&obj
->base
);
10082 mutex_unlock(&dev
->struct_mutex
);
10085 spin_lock_irqsave(&dev
->event_lock
, flags
);
10086 intel_crtc
->unpin_work
= NULL
;
10087 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10089 drm_crtc_vblank_put(crtc
);
10095 intel_crtc_wait_for_pending_flips(crtc
);
10096 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
10097 if (ret
== 0 && event
) {
10098 spin_lock_irqsave(&dev
->event_lock
, flags
);
10099 drm_send_vblank_event(dev
, pipe
, event
);
10100 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10106 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
10107 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
10108 .load_lut
= intel_crtc_load_lut
,
10112 * intel_modeset_update_staged_output_state
10114 * Updates the staged output configuration state, e.g. after we've read out the
10115 * current hw state.
10117 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
10119 struct intel_crtc
*crtc
;
10120 struct intel_encoder
*encoder
;
10121 struct intel_connector
*connector
;
10123 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10125 connector
->new_encoder
=
10126 to_intel_encoder(connector
->base
.encoder
);
10129 for_each_intel_encoder(dev
, encoder
) {
10130 encoder
->new_crtc
=
10131 to_intel_crtc(encoder
->base
.crtc
);
10134 for_each_intel_crtc(dev
, crtc
) {
10135 crtc
->new_enabled
= crtc
->base
.enabled
;
10137 if (crtc
->new_enabled
)
10138 crtc
->new_config
= &crtc
->config
;
10140 crtc
->new_config
= NULL
;
10145 * intel_modeset_commit_output_state
10147 * This function copies the stage display pipe configuration to the real one.
10149 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
10151 struct intel_crtc
*crtc
;
10152 struct intel_encoder
*encoder
;
10153 struct intel_connector
*connector
;
10155 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10157 connector
->base
.encoder
= &connector
->new_encoder
->base
;
10160 for_each_intel_encoder(dev
, encoder
) {
10161 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
10164 for_each_intel_crtc(dev
, crtc
) {
10165 crtc
->base
.enabled
= crtc
->new_enabled
;
10170 connected_sink_compute_bpp(struct intel_connector
*connector
,
10171 struct intel_crtc_config
*pipe_config
)
10173 int bpp
= pipe_config
->pipe_bpp
;
10175 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10176 connector
->base
.base
.id
,
10177 connector
->base
.name
);
10179 /* Don't use an invalid EDID bpc value */
10180 if (connector
->base
.display_info
.bpc
&&
10181 connector
->base
.display_info
.bpc
* 3 < bpp
) {
10182 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10183 bpp
, connector
->base
.display_info
.bpc
*3);
10184 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
10187 /* Clamp bpp to 8 on screens without EDID 1.4 */
10188 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
10189 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10191 pipe_config
->pipe_bpp
= 24;
10196 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10197 struct drm_framebuffer
*fb
,
10198 struct intel_crtc_config
*pipe_config
)
10200 struct drm_device
*dev
= crtc
->base
.dev
;
10201 struct intel_connector
*connector
;
10204 switch (fb
->pixel_format
) {
10205 case DRM_FORMAT_C8
:
10206 bpp
= 8*3; /* since we go through a colormap */
10208 case DRM_FORMAT_XRGB1555
:
10209 case DRM_FORMAT_ARGB1555
:
10210 /* checked in intel_framebuffer_init already */
10211 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10213 case DRM_FORMAT_RGB565
:
10214 bpp
= 6*3; /* min is 18bpp */
10216 case DRM_FORMAT_XBGR8888
:
10217 case DRM_FORMAT_ABGR8888
:
10218 /* checked in intel_framebuffer_init already */
10219 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10221 case DRM_FORMAT_XRGB8888
:
10222 case DRM_FORMAT_ARGB8888
:
10225 case DRM_FORMAT_XRGB2101010
:
10226 case DRM_FORMAT_ARGB2101010
:
10227 case DRM_FORMAT_XBGR2101010
:
10228 case DRM_FORMAT_ABGR2101010
:
10229 /* checked in intel_framebuffer_init already */
10230 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10234 /* TODO: gen4+ supports 16 bpc floating point, too. */
10236 DRM_DEBUG_KMS("unsupported depth\n");
10240 pipe_config
->pipe_bpp
= bpp
;
10242 /* Clamp display bpp to EDID value */
10243 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10245 if (!connector
->new_encoder
||
10246 connector
->new_encoder
->new_crtc
!= crtc
)
10249 connected_sink_compute_bpp(connector
, pipe_config
);
10255 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10257 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10258 "type: 0x%x flags: 0x%x\n",
10260 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10261 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10262 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10263 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10266 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10267 struct intel_crtc_config
*pipe_config
,
10268 const char *context
)
10270 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10271 context
, pipe_name(crtc
->pipe
));
10273 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10274 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10275 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10276 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10277 pipe_config
->has_pch_encoder
,
10278 pipe_config
->fdi_lanes
,
10279 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10280 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10281 pipe_config
->fdi_m_n
.tu
);
10282 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10283 pipe_config
->has_dp_encoder
,
10284 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10285 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10286 pipe_config
->dp_m_n
.tu
);
10288 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10289 pipe_config
->has_dp_encoder
,
10290 pipe_config
->dp_m2_n2
.gmch_m
,
10291 pipe_config
->dp_m2_n2
.gmch_n
,
10292 pipe_config
->dp_m2_n2
.link_m
,
10293 pipe_config
->dp_m2_n2
.link_n
,
10294 pipe_config
->dp_m2_n2
.tu
);
10296 DRM_DEBUG_KMS("requested mode:\n");
10297 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10298 DRM_DEBUG_KMS("adjusted mode:\n");
10299 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10300 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10301 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10302 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10303 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10304 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10305 pipe_config
->gmch_pfit
.control
,
10306 pipe_config
->gmch_pfit
.pgm_ratios
,
10307 pipe_config
->gmch_pfit
.lvds_border_bits
);
10308 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10309 pipe_config
->pch_pfit
.pos
,
10310 pipe_config
->pch_pfit
.size
,
10311 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10312 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10313 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10316 static bool encoders_cloneable(const struct intel_encoder
*a
,
10317 const struct intel_encoder
*b
)
10319 /* masks could be asymmetric, so check both ways */
10320 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10321 b
->cloneable
& (1 << a
->type
));
10324 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10325 struct intel_encoder
*encoder
)
10327 struct drm_device
*dev
= crtc
->base
.dev
;
10328 struct intel_encoder
*source_encoder
;
10330 for_each_intel_encoder(dev
, source_encoder
) {
10331 if (source_encoder
->new_crtc
!= crtc
)
10334 if (!encoders_cloneable(encoder
, source_encoder
))
10341 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10343 struct drm_device
*dev
= crtc
->base
.dev
;
10344 struct intel_encoder
*encoder
;
10346 for_each_intel_encoder(dev
, encoder
) {
10347 if (encoder
->new_crtc
!= crtc
)
10350 if (!check_single_encoder_cloning(crtc
, encoder
))
10357 static struct intel_crtc_config
*
10358 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10359 struct drm_framebuffer
*fb
,
10360 struct drm_display_mode
*mode
)
10362 struct drm_device
*dev
= crtc
->dev
;
10363 struct intel_encoder
*encoder
;
10364 struct intel_crtc_config
*pipe_config
;
10365 int plane_bpp
, ret
= -EINVAL
;
10368 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10369 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10370 return ERR_PTR(-EINVAL
);
10373 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10375 return ERR_PTR(-ENOMEM
);
10377 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10378 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10380 pipe_config
->cpu_transcoder
=
10381 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10382 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10385 * Sanitize sync polarity flags based on requested ones. If neither
10386 * positive or negative polarity is requested, treat this as meaning
10387 * negative polarity.
10389 if (!(pipe_config
->adjusted_mode
.flags
&
10390 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10391 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10393 if (!(pipe_config
->adjusted_mode
.flags
&
10394 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10395 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10397 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10398 * plane pixel format and any sink constraints into account. Returns the
10399 * source plane bpp so that dithering can be selected on mismatches
10400 * after encoders and crtc also have had their say. */
10401 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10407 * Determine the real pipe dimensions. Note that stereo modes can
10408 * increase the actual pipe size due to the frame doubling and
10409 * insertion of additional space for blanks between the frame. This
10410 * is stored in the crtc timings. We use the requested mode to do this
10411 * computation to clearly distinguish it from the adjusted mode, which
10412 * can be changed by the connectors in the below retry loop.
10414 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10415 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10416 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10419 /* Ensure the port clock defaults are reset when retrying. */
10420 pipe_config
->port_clock
= 0;
10421 pipe_config
->pixel_multiplier
= 1;
10423 /* Fill in default crtc timings, allow encoders to overwrite them. */
10424 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10426 /* Pass our mode to the connectors and the CRTC to give them a chance to
10427 * adjust it according to limitations or connector properties, and also
10428 * a chance to reject the mode entirely.
10430 for_each_intel_encoder(dev
, encoder
) {
10432 if (&encoder
->new_crtc
->base
!= crtc
)
10435 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10436 DRM_DEBUG_KMS("Encoder config failure\n");
10441 /* Set default port clock if not overwritten by the encoder. Needs to be
10442 * done afterwards in case the encoder adjusts the mode. */
10443 if (!pipe_config
->port_clock
)
10444 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10445 * pipe_config
->pixel_multiplier
;
10447 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10449 DRM_DEBUG_KMS("CRTC fixup failed\n");
10453 if (ret
== RETRY
) {
10454 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10459 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10461 goto encoder_retry
;
10464 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10465 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10466 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10468 return pipe_config
;
10470 kfree(pipe_config
);
10471 return ERR_PTR(ret
);
10474 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10475 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10477 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10478 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10480 struct intel_crtc
*intel_crtc
;
10481 struct drm_device
*dev
= crtc
->dev
;
10482 struct intel_encoder
*encoder
;
10483 struct intel_connector
*connector
;
10484 struct drm_crtc
*tmp_crtc
;
10486 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10488 /* Check which crtcs have changed outputs connected to them, these need
10489 * to be part of the prepare_pipes mask. We don't (yet) support global
10490 * modeset across multiple crtcs, so modeset_pipes will only have one
10491 * bit set at most. */
10492 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10494 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10497 if (connector
->base
.encoder
) {
10498 tmp_crtc
= connector
->base
.encoder
->crtc
;
10500 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10503 if (connector
->new_encoder
)
10505 1 << connector
->new_encoder
->new_crtc
->pipe
;
10508 for_each_intel_encoder(dev
, encoder
) {
10509 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10512 if (encoder
->base
.crtc
) {
10513 tmp_crtc
= encoder
->base
.crtc
;
10515 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10518 if (encoder
->new_crtc
)
10519 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10522 /* Check for pipes that will be enabled/disabled ... */
10523 for_each_intel_crtc(dev
, intel_crtc
) {
10524 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10527 if (!intel_crtc
->new_enabled
)
10528 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10530 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10534 /* set_mode is also used to update properties on life display pipes. */
10535 intel_crtc
= to_intel_crtc(crtc
);
10536 if (intel_crtc
->new_enabled
)
10537 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10540 * For simplicity do a full modeset on any pipe where the output routing
10541 * changed. We could be more clever, but that would require us to be
10542 * more careful with calling the relevant encoder->mode_set functions.
10544 if (*prepare_pipes
)
10545 *modeset_pipes
= *prepare_pipes
;
10547 /* ... and mask these out. */
10548 *modeset_pipes
&= ~(*disable_pipes
);
10549 *prepare_pipes
&= ~(*disable_pipes
);
10552 * HACK: We don't (yet) fully support global modesets. intel_set_config
10553 * obies this rule, but the modeset restore mode of
10554 * intel_modeset_setup_hw_state does not.
10556 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10557 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10559 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10560 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10563 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10565 struct drm_encoder
*encoder
;
10566 struct drm_device
*dev
= crtc
->dev
;
10568 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10569 if (encoder
->crtc
== crtc
)
10576 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10578 struct intel_encoder
*intel_encoder
;
10579 struct intel_crtc
*intel_crtc
;
10580 struct drm_connector
*connector
;
10582 for_each_intel_encoder(dev
, intel_encoder
) {
10583 if (!intel_encoder
->base
.crtc
)
10586 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10588 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10589 intel_encoder
->connectors_active
= false;
10592 intel_modeset_commit_output_state(dev
);
10594 /* Double check state. */
10595 for_each_intel_crtc(dev
, intel_crtc
) {
10596 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10597 WARN_ON(intel_crtc
->new_config
&&
10598 intel_crtc
->new_config
!= &intel_crtc
->config
);
10599 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10602 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10603 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10606 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10608 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10609 struct drm_property
*dpms_property
=
10610 dev
->mode_config
.dpms_property
;
10612 connector
->dpms
= DRM_MODE_DPMS_ON
;
10613 drm_object_property_set_value(&connector
->base
,
10617 intel_encoder
= to_intel_encoder(connector
->encoder
);
10618 intel_encoder
->connectors_active
= true;
10624 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10628 if (clock1
== clock2
)
10631 if (!clock1
|| !clock2
)
10634 diff
= abs(clock1
- clock2
);
10636 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10642 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10643 list_for_each_entry((intel_crtc), \
10644 &(dev)->mode_config.crtc_list, \
10646 if (mask & (1 <<(intel_crtc)->pipe))
10649 intel_pipe_config_compare(struct drm_device
*dev
,
10650 struct intel_crtc_config
*current_config
,
10651 struct intel_crtc_config
*pipe_config
)
10653 #define PIPE_CONF_CHECK_X(name) \
10654 if (current_config->name != pipe_config->name) { \
10655 DRM_ERROR("mismatch in " #name " " \
10656 "(expected 0x%08x, found 0x%08x)\n", \
10657 current_config->name, \
10658 pipe_config->name); \
10662 #define PIPE_CONF_CHECK_I(name) \
10663 if (current_config->name != pipe_config->name) { \
10664 DRM_ERROR("mismatch in " #name " " \
10665 "(expected %i, found %i)\n", \
10666 current_config->name, \
10667 pipe_config->name); \
10671 /* This is required for BDW+ where there is only one set of registers for
10672 * switching between high and low RR.
10673 * This macro can be used whenever a comparison has to be made between one
10674 * hw state and multiple sw state variables.
10676 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10677 if ((current_config->name != pipe_config->name) && \
10678 (current_config->alt_name != pipe_config->name)) { \
10679 DRM_ERROR("mismatch in " #name " " \
10680 "(expected %i or %i, found %i)\n", \
10681 current_config->name, \
10682 current_config->alt_name, \
10683 pipe_config->name); \
10687 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10688 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10689 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10690 "(expected %i, found %i)\n", \
10691 current_config->name & (mask), \
10692 pipe_config->name & (mask)); \
10696 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10697 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10698 DRM_ERROR("mismatch in " #name " " \
10699 "(expected %i, found %i)\n", \
10700 current_config->name, \
10701 pipe_config->name); \
10705 #define PIPE_CONF_QUIRK(quirk) \
10706 ((current_config->quirks | pipe_config->quirks) & (quirk))
10708 PIPE_CONF_CHECK_I(cpu_transcoder
);
10710 PIPE_CONF_CHECK_I(has_pch_encoder
);
10711 PIPE_CONF_CHECK_I(fdi_lanes
);
10712 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10713 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10714 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10715 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10716 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10718 PIPE_CONF_CHECK_I(has_dp_encoder
);
10720 if (INTEL_INFO(dev
)->gen
< 8) {
10721 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10722 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10723 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10724 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10725 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10727 if (current_config
->has_drrs
) {
10728 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10729 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10730 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10731 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10732 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10735 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10736 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10737 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10738 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10739 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10742 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10743 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10744 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10745 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10746 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10747 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10749 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10750 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10751 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10752 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10753 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10754 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10756 PIPE_CONF_CHECK_I(pixel_multiplier
);
10757 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10758 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10759 IS_VALLEYVIEW(dev
))
10760 PIPE_CONF_CHECK_I(limited_color_range
);
10762 PIPE_CONF_CHECK_I(has_audio
);
10764 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10765 DRM_MODE_FLAG_INTERLACE
);
10767 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10768 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10769 DRM_MODE_FLAG_PHSYNC
);
10770 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10771 DRM_MODE_FLAG_NHSYNC
);
10772 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10773 DRM_MODE_FLAG_PVSYNC
);
10774 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10775 DRM_MODE_FLAG_NVSYNC
);
10778 PIPE_CONF_CHECK_I(pipe_src_w
);
10779 PIPE_CONF_CHECK_I(pipe_src_h
);
10782 * FIXME: BIOS likes to set up a cloned config with lvds+external
10783 * screen. Since we don't yet re-compute the pipe config when moving
10784 * just the lvds port away to another pipe the sw tracking won't match.
10786 * Proper atomic modesets with recomputed global state will fix this.
10787 * Until then just don't check gmch state for inherited modes.
10789 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10790 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10791 /* pfit ratios are autocomputed by the hw on gen4+ */
10792 if (INTEL_INFO(dev
)->gen
< 4)
10793 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10794 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10797 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10798 if (current_config
->pch_pfit
.enabled
) {
10799 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10800 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10803 /* BDW+ don't expose a synchronous way to read the state */
10804 if (IS_HASWELL(dev
))
10805 PIPE_CONF_CHECK_I(ips_enabled
);
10807 PIPE_CONF_CHECK_I(double_wide
);
10809 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10811 PIPE_CONF_CHECK_I(shared_dpll
);
10812 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10813 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10814 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10815 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10816 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10818 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10819 PIPE_CONF_CHECK_I(pipe_bpp
);
10821 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10822 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10824 #undef PIPE_CONF_CHECK_X
10825 #undef PIPE_CONF_CHECK_I
10826 #undef PIPE_CONF_CHECK_I_ALT
10827 #undef PIPE_CONF_CHECK_FLAGS
10828 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10829 #undef PIPE_CONF_QUIRK
10835 check_connector_state(struct drm_device
*dev
)
10837 struct intel_connector
*connector
;
10839 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10841 /* This also checks the encoder/connector hw state with the
10842 * ->get_hw_state callbacks. */
10843 intel_connector_check_state(connector
);
10845 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10846 "connector's staged encoder doesn't match current encoder\n");
10851 check_encoder_state(struct drm_device
*dev
)
10853 struct intel_encoder
*encoder
;
10854 struct intel_connector
*connector
;
10856 for_each_intel_encoder(dev
, encoder
) {
10857 bool enabled
= false;
10858 bool active
= false;
10859 enum pipe pipe
, tracked_pipe
;
10861 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10862 encoder
->base
.base
.id
,
10863 encoder
->base
.name
);
10865 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10866 "encoder's stage crtc doesn't match current crtc\n");
10867 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10868 "encoder's active_connectors set, but no crtc\n");
10870 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10872 if (connector
->base
.encoder
!= &encoder
->base
)
10875 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10879 * for MST connectors if we unplug the connector is gone
10880 * away but the encoder is still connected to a crtc
10881 * until a modeset happens in response to the hotplug.
10883 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10886 WARN(!!encoder
->base
.crtc
!= enabled
,
10887 "encoder's enabled state mismatch "
10888 "(expected %i, found %i)\n",
10889 !!encoder
->base
.crtc
, enabled
);
10890 WARN(active
&& !encoder
->base
.crtc
,
10891 "active encoder with no crtc\n");
10893 WARN(encoder
->connectors_active
!= active
,
10894 "encoder's computed active state doesn't match tracked active state "
10895 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10897 active
= encoder
->get_hw_state(encoder
, &pipe
);
10898 WARN(active
!= encoder
->connectors_active
,
10899 "encoder's hw state doesn't match sw tracking "
10900 "(expected %i, found %i)\n",
10901 encoder
->connectors_active
, active
);
10903 if (!encoder
->base
.crtc
)
10906 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10907 WARN(active
&& pipe
!= tracked_pipe
,
10908 "active encoder's pipe doesn't match"
10909 "(expected %i, found %i)\n",
10910 tracked_pipe
, pipe
);
10916 check_crtc_state(struct drm_device
*dev
)
10918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10919 struct intel_crtc
*crtc
;
10920 struct intel_encoder
*encoder
;
10921 struct intel_crtc_config pipe_config
;
10923 for_each_intel_crtc(dev
, crtc
) {
10924 bool enabled
= false;
10925 bool active
= false;
10927 memset(&pipe_config
, 0, sizeof(pipe_config
));
10929 DRM_DEBUG_KMS("[CRTC:%d]\n",
10930 crtc
->base
.base
.id
);
10932 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10933 "active crtc, but not enabled in sw tracking\n");
10935 for_each_intel_encoder(dev
, encoder
) {
10936 if (encoder
->base
.crtc
!= &crtc
->base
)
10939 if (encoder
->connectors_active
)
10943 WARN(active
!= crtc
->active
,
10944 "crtc's computed active state doesn't match tracked active state "
10945 "(expected %i, found %i)\n", active
, crtc
->active
);
10946 WARN(enabled
!= crtc
->base
.enabled
,
10947 "crtc's computed enabled state doesn't match tracked enabled state "
10948 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10950 active
= dev_priv
->display
.get_pipe_config(crtc
,
10953 /* hw state is inconsistent with the pipe quirk */
10954 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10955 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10956 active
= crtc
->active
;
10958 for_each_intel_encoder(dev
, encoder
) {
10960 if (encoder
->base
.crtc
!= &crtc
->base
)
10962 if (encoder
->get_hw_state(encoder
, &pipe
))
10963 encoder
->get_config(encoder
, &pipe_config
);
10966 WARN(crtc
->active
!= active
,
10967 "crtc active state doesn't match with hw state "
10968 "(expected %i, found %i)\n", crtc
->active
, active
);
10971 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10972 WARN(1, "pipe state doesn't match!\n");
10973 intel_dump_pipe_config(crtc
, &pipe_config
,
10975 intel_dump_pipe_config(crtc
, &crtc
->config
,
10982 check_shared_dpll_state(struct drm_device
*dev
)
10984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10985 struct intel_crtc
*crtc
;
10986 struct intel_dpll_hw_state dpll_hw_state
;
10989 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10990 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10991 int enabled_crtcs
= 0, active_crtcs
= 0;
10994 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10996 DRM_DEBUG_KMS("%s\n", pll
->name
);
10998 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
11000 WARN(pll
->active
> pll
->refcount
,
11001 "more active pll users than references: %i vs %i\n",
11002 pll
->active
, pll
->refcount
);
11003 WARN(pll
->active
&& !pll
->on
,
11004 "pll in active use but not on in sw tracking\n");
11005 WARN(pll
->on
&& !pll
->active
,
11006 "pll in on but not on in use in sw tracking\n");
11007 WARN(pll
->on
!= active
,
11008 "pll on state mismatch (expected %i, found %i)\n",
11011 for_each_intel_crtc(dev
, crtc
) {
11012 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11014 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11017 WARN(pll
->active
!= active_crtcs
,
11018 "pll active crtcs mismatch (expected %i, found %i)\n",
11019 pll
->active
, active_crtcs
);
11020 WARN(pll
->refcount
!= enabled_crtcs
,
11021 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11022 pll
->refcount
, enabled_crtcs
);
11024 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
11025 sizeof(dpll_hw_state
)),
11026 "pll hw state mismatch\n");
11031 intel_modeset_check_state(struct drm_device
*dev
)
11033 check_connector_state(dev
);
11034 check_encoder_state(dev
);
11035 check_crtc_state(dev
);
11036 check_shared_dpll_state(dev
);
11039 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
11043 * FDI already provided one idea for the dotclock.
11044 * Yell if the encoder disagrees.
11046 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
11047 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11048 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
11051 static void update_scanline_offset(struct intel_crtc
*crtc
)
11053 struct drm_device
*dev
= crtc
->base
.dev
;
11056 * The scanline counter increments at the leading edge of hsync.
11058 * On most platforms it starts counting from vtotal-1 on the
11059 * first active line. That means the scanline counter value is
11060 * always one less than what we would expect. Ie. just after
11061 * start of vblank, which also occurs at start of hsync (on the
11062 * last active line), the scanline counter will read vblank_start-1.
11064 * On gen2 the scanline counter starts counting from 1 instead
11065 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11066 * to keep the value positive), instead of adding one.
11068 * On HSW+ the behaviour of the scanline counter depends on the output
11069 * type. For DP ports it behaves like most other platforms, but on HDMI
11070 * there's an extra 1 line difference. So we need to add two instead of
11071 * one to the value.
11073 if (IS_GEN2(dev
)) {
11074 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
11077 vtotal
= mode
->crtc_vtotal
;
11078 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11081 crtc
->scanline_offset
= vtotal
- 1;
11082 } else if (HAS_DDI(dev
) &&
11083 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
11084 crtc
->scanline_offset
= 2;
11086 crtc
->scanline_offset
= 1;
11089 static int __intel_set_mode(struct drm_crtc
*crtc
,
11090 struct drm_display_mode
*mode
,
11091 int x
, int y
, struct drm_framebuffer
*fb
)
11093 struct drm_device
*dev
= crtc
->dev
;
11094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11095 struct drm_display_mode
*saved_mode
;
11096 struct intel_crtc_config
*pipe_config
= NULL
;
11097 struct intel_crtc
*intel_crtc
;
11098 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
11101 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11105 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
11106 &prepare_pipes
, &disable_pipes
);
11108 *saved_mode
= crtc
->mode
;
11110 /* Hack: Because we don't (yet) support global modeset on multiple
11111 * crtcs, we don't keep track of the new mode for more than one crtc.
11112 * Hence simply check whether any bit is set in modeset_pipes in all the
11113 * pieces of code that are not yet converted to deal with mutliple crtcs
11114 * changing their mode at the same time. */
11115 if (modeset_pipes
) {
11116 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
11117 if (IS_ERR(pipe_config
)) {
11118 ret
= PTR_ERR(pipe_config
);
11119 pipe_config
= NULL
;
11123 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11125 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11129 * See if the config requires any additional preparation, e.g.
11130 * to adjust global state with pipes off. We need to do this
11131 * here so we can get the modeset_pipe updated config for the new
11132 * mode set on this crtc. For other crtcs we need to use the
11133 * adjusted_mode bits in the crtc directly.
11135 if (IS_VALLEYVIEW(dev
)) {
11136 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11138 /* may have added more to prepare_pipes than we should */
11139 prepare_pipes
&= ~disable_pipes
;
11142 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11143 intel_crtc_disable(&intel_crtc
->base
);
11145 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11146 if (intel_crtc
->base
.enabled
)
11147 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11150 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11151 * to set it here already despite that we pass it down the callchain.
11153 if (modeset_pipes
) {
11154 crtc
->mode
= *mode
;
11155 /* mode_set/enable/disable functions rely on a correct pipe
11157 to_intel_crtc(crtc
)->config
= *pipe_config
;
11158 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
11161 * Calculate and store various constants which
11162 * are later needed by vblank and swap-completion
11163 * timestamping. They are derived from true hwmode.
11165 drm_calc_timestamping_constants(crtc
,
11166 &pipe_config
->adjusted_mode
);
11169 /* Only after disabling all output pipelines that will be changed can we
11170 * update the the output configuration. */
11171 intel_modeset_update_state(dev
, prepare_pipes
);
11173 if (dev_priv
->display
.modeset_global_resources
)
11174 dev_priv
->display
.modeset_global_resources(dev
);
11176 /* Set up the DPLL and any encoders state that needs to adjust or depend
11179 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11180 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11181 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
11182 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11184 mutex_lock(&dev
->struct_mutex
);
11185 ret
= intel_pin_and_fence_fb_obj(dev
,
11189 DRM_ERROR("pin & fence failed\n");
11190 mutex_unlock(&dev
->struct_mutex
);
11194 intel_unpin_fb_obj(old_obj
);
11195 i915_gem_track_fb(old_obj
, obj
,
11196 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11197 mutex_unlock(&dev
->struct_mutex
);
11199 crtc
->primary
->fb
= fb
;
11203 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
11209 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11210 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11211 update_scanline_offset(intel_crtc
);
11213 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11216 /* FIXME: add subpixel order */
11218 if (ret
&& crtc
->enabled
)
11219 crtc
->mode
= *saved_mode
;
11222 kfree(pipe_config
);
11227 static int intel_set_mode(struct drm_crtc
*crtc
,
11228 struct drm_display_mode
*mode
,
11229 int x
, int y
, struct drm_framebuffer
*fb
)
11233 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
11236 intel_modeset_check_state(crtc
->dev
);
11241 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11243 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11246 #undef for_each_intel_crtc_masked
11248 static void intel_set_config_free(struct intel_set_config
*config
)
11253 kfree(config
->save_connector_encoders
);
11254 kfree(config
->save_encoder_crtcs
);
11255 kfree(config
->save_crtc_enabled
);
11259 static int intel_set_config_save_state(struct drm_device
*dev
,
11260 struct intel_set_config
*config
)
11262 struct drm_crtc
*crtc
;
11263 struct drm_encoder
*encoder
;
11264 struct drm_connector
*connector
;
11267 config
->save_crtc_enabled
=
11268 kcalloc(dev
->mode_config
.num_crtc
,
11269 sizeof(bool), GFP_KERNEL
);
11270 if (!config
->save_crtc_enabled
)
11273 config
->save_encoder_crtcs
=
11274 kcalloc(dev
->mode_config
.num_encoder
,
11275 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11276 if (!config
->save_encoder_crtcs
)
11279 config
->save_connector_encoders
=
11280 kcalloc(dev
->mode_config
.num_connector
,
11281 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11282 if (!config
->save_connector_encoders
)
11285 /* Copy data. Note that driver private data is not affected.
11286 * Should anything bad happen only the expected state is
11287 * restored, not the drivers personal bookkeeping.
11290 for_each_crtc(dev
, crtc
) {
11291 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11295 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11296 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11300 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11301 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11307 static void intel_set_config_restore_state(struct drm_device
*dev
,
11308 struct intel_set_config
*config
)
11310 struct intel_crtc
*crtc
;
11311 struct intel_encoder
*encoder
;
11312 struct intel_connector
*connector
;
11316 for_each_intel_crtc(dev
, crtc
) {
11317 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11319 if (crtc
->new_enabled
)
11320 crtc
->new_config
= &crtc
->config
;
11322 crtc
->new_config
= NULL
;
11326 for_each_intel_encoder(dev
, encoder
) {
11327 encoder
->new_crtc
=
11328 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11332 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11333 connector
->new_encoder
=
11334 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11339 is_crtc_connector_off(struct drm_mode_set
*set
)
11343 if (set
->num_connectors
== 0)
11346 if (WARN_ON(set
->connectors
== NULL
))
11349 for (i
= 0; i
< set
->num_connectors
; i
++)
11350 if (set
->connectors
[i
]->encoder
&&
11351 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11352 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11359 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11360 struct intel_set_config
*config
)
11363 /* We should be able to check here if the fb has the same properties
11364 * and then just flip_or_move it */
11365 if (is_crtc_connector_off(set
)) {
11366 config
->mode_changed
= true;
11367 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11369 * If we have no fb, we can only flip as long as the crtc is
11370 * active, otherwise we need a full mode set. The crtc may
11371 * be active if we've only disabled the primary plane, or
11372 * in fastboot situations.
11374 if (set
->crtc
->primary
->fb
== NULL
) {
11375 struct intel_crtc
*intel_crtc
=
11376 to_intel_crtc(set
->crtc
);
11378 if (intel_crtc
->active
) {
11379 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11380 config
->fb_changed
= true;
11382 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11383 config
->mode_changed
= true;
11385 } else if (set
->fb
== NULL
) {
11386 config
->mode_changed
= true;
11387 } else if (set
->fb
->pixel_format
!=
11388 set
->crtc
->primary
->fb
->pixel_format
) {
11389 config
->mode_changed
= true;
11391 config
->fb_changed
= true;
11395 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11396 config
->fb_changed
= true;
11398 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11399 DRM_DEBUG_KMS("modes are different, full mode set\n");
11400 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11401 drm_mode_debug_printmodeline(set
->mode
);
11402 config
->mode_changed
= true;
11405 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11406 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11410 intel_modeset_stage_output_state(struct drm_device
*dev
,
11411 struct drm_mode_set
*set
,
11412 struct intel_set_config
*config
)
11414 struct intel_connector
*connector
;
11415 struct intel_encoder
*encoder
;
11416 struct intel_crtc
*crtc
;
11419 /* The upper layers ensure that we either disable a crtc or have a list
11420 * of connectors. For paranoia, double-check this. */
11421 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11422 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11424 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11426 /* Otherwise traverse passed in connector list and get encoders
11428 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11429 if (set
->connectors
[ro
] == &connector
->base
) {
11430 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11435 /* If we disable the crtc, disable all its connectors. Also, if
11436 * the connector is on the changing crtc but not on the new
11437 * connector list, disable it. */
11438 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11439 connector
->base
.encoder
&&
11440 connector
->base
.encoder
->crtc
== set
->crtc
) {
11441 connector
->new_encoder
= NULL
;
11443 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11444 connector
->base
.base
.id
,
11445 connector
->base
.name
);
11449 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11450 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11451 config
->mode_changed
= true;
11454 /* connector->new_encoder is now updated for all connectors. */
11456 /* Update crtc of enabled connectors. */
11457 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11459 struct drm_crtc
*new_crtc
;
11461 if (!connector
->new_encoder
)
11464 new_crtc
= connector
->new_encoder
->base
.crtc
;
11466 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11467 if (set
->connectors
[ro
] == &connector
->base
)
11468 new_crtc
= set
->crtc
;
11471 /* Make sure the new CRTC will work with the encoder */
11472 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11476 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11478 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11479 connector
->base
.base
.id
,
11480 connector
->base
.name
,
11481 new_crtc
->base
.id
);
11484 /* Check for any encoders that needs to be disabled. */
11485 for_each_intel_encoder(dev
, encoder
) {
11486 int num_connectors
= 0;
11487 list_for_each_entry(connector
,
11488 &dev
->mode_config
.connector_list
,
11490 if (connector
->new_encoder
== encoder
) {
11491 WARN_ON(!connector
->new_encoder
->new_crtc
);
11496 if (num_connectors
== 0)
11497 encoder
->new_crtc
= NULL
;
11498 else if (num_connectors
> 1)
11501 /* Only now check for crtc changes so we don't miss encoders
11502 * that will be disabled. */
11503 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11504 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11505 config
->mode_changed
= true;
11508 /* Now we've also updated encoder->new_crtc for all encoders. */
11509 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11511 if (connector
->new_encoder
)
11512 if (connector
->new_encoder
!= connector
->encoder
)
11513 connector
->encoder
= connector
->new_encoder
;
11515 for_each_intel_crtc(dev
, crtc
) {
11516 crtc
->new_enabled
= false;
11518 for_each_intel_encoder(dev
, encoder
) {
11519 if (encoder
->new_crtc
== crtc
) {
11520 crtc
->new_enabled
= true;
11525 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11526 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11527 crtc
->new_enabled
? "en" : "dis");
11528 config
->mode_changed
= true;
11531 if (crtc
->new_enabled
)
11532 crtc
->new_config
= &crtc
->config
;
11534 crtc
->new_config
= NULL
;
11540 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11542 struct drm_device
*dev
= crtc
->base
.dev
;
11543 struct intel_encoder
*encoder
;
11544 struct intel_connector
*connector
;
11546 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11547 pipe_name(crtc
->pipe
));
11549 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11550 if (connector
->new_encoder
&&
11551 connector
->new_encoder
->new_crtc
== crtc
)
11552 connector
->new_encoder
= NULL
;
11555 for_each_intel_encoder(dev
, encoder
) {
11556 if (encoder
->new_crtc
== crtc
)
11557 encoder
->new_crtc
= NULL
;
11560 crtc
->new_enabled
= false;
11561 crtc
->new_config
= NULL
;
11564 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11566 struct drm_device
*dev
;
11567 struct drm_mode_set save_set
;
11568 struct intel_set_config
*config
;
11572 BUG_ON(!set
->crtc
);
11573 BUG_ON(!set
->crtc
->helper_private
);
11575 /* Enforce sane interface api - has been abused by the fb helper. */
11576 BUG_ON(!set
->mode
&& set
->fb
);
11577 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11580 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11581 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11582 (int)set
->num_connectors
, set
->x
, set
->y
);
11584 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11587 dev
= set
->crtc
->dev
;
11590 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11594 ret
= intel_set_config_save_state(dev
, config
);
11598 save_set
.crtc
= set
->crtc
;
11599 save_set
.mode
= &set
->crtc
->mode
;
11600 save_set
.x
= set
->crtc
->x
;
11601 save_set
.y
= set
->crtc
->y
;
11602 save_set
.fb
= set
->crtc
->primary
->fb
;
11604 /* Compute whether we need a full modeset, only an fb base update or no
11605 * change at all. In the future we might also check whether only the
11606 * mode changed, e.g. for LVDS where we only change the panel fitter in
11608 intel_set_config_compute_mode_changes(set
, config
);
11610 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11614 if (config
->mode_changed
) {
11615 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11616 set
->x
, set
->y
, set
->fb
);
11617 } else if (config
->fb_changed
) {
11618 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11620 intel_crtc_wait_for_pending_flips(set
->crtc
);
11622 ret
= intel_pipe_set_base(set
->crtc
,
11623 set
->x
, set
->y
, set
->fb
);
11626 * We need to make sure the primary plane is re-enabled if it
11627 * has previously been turned off.
11629 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11630 WARN_ON(!intel_crtc
->active
);
11631 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11635 * In the fastboot case this may be our only check of the
11636 * state after boot. It would be better to only do it on
11637 * the first update, but we don't have a nice way of doing that
11638 * (and really, set_config isn't used much for high freq page
11639 * flipping, so increasing its cost here shouldn't be a big
11642 if (i915
.fastboot
&& ret
== 0)
11643 intel_modeset_check_state(set
->crtc
->dev
);
11647 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11648 set
->crtc
->base
.id
, ret
);
11650 intel_set_config_restore_state(dev
, config
);
11653 * HACK: if the pipe was on, but we didn't have a framebuffer,
11654 * force the pipe off to avoid oopsing in the modeset code
11655 * due to fb==NULL. This should only happen during boot since
11656 * we don't yet reconstruct the FB from the hardware state.
11658 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11659 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11661 /* Try to restore the config */
11662 if (config
->mode_changed
&&
11663 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11664 save_set
.x
, save_set
.y
, save_set
.fb
))
11665 DRM_ERROR("failed to restore config after modeset failure\n");
11669 intel_set_config_free(config
);
11673 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11674 .gamma_set
= intel_crtc_gamma_set
,
11675 .set_config
= intel_crtc_set_config
,
11676 .destroy
= intel_crtc_destroy
,
11677 .page_flip
= intel_crtc_page_flip
,
11680 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11681 struct intel_shared_dpll
*pll
,
11682 struct intel_dpll_hw_state
*hw_state
)
11686 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11689 val
= I915_READ(PCH_DPLL(pll
->id
));
11690 hw_state
->dpll
= val
;
11691 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11692 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11694 return val
& DPLL_VCO_ENABLE
;
11697 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11698 struct intel_shared_dpll
*pll
)
11700 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11701 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11704 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11705 struct intel_shared_dpll
*pll
)
11707 /* PCH refclock must be enabled first */
11708 ibx_assert_pch_refclk_enabled(dev_priv
);
11710 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11712 /* Wait for the clocks to stabilize. */
11713 POSTING_READ(PCH_DPLL(pll
->id
));
11716 /* The pixel multiplier can only be updated once the
11717 * DPLL is enabled and the clocks are stable.
11719 * So write it again.
11721 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11722 POSTING_READ(PCH_DPLL(pll
->id
));
11726 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11727 struct intel_shared_dpll
*pll
)
11729 struct drm_device
*dev
= dev_priv
->dev
;
11730 struct intel_crtc
*crtc
;
11732 /* Make sure no transcoder isn't still depending on us. */
11733 for_each_intel_crtc(dev
, crtc
) {
11734 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11735 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11738 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11739 POSTING_READ(PCH_DPLL(pll
->id
));
11743 static char *ibx_pch_dpll_names
[] = {
11748 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11753 dev_priv
->num_shared_dpll
= 2;
11755 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11756 dev_priv
->shared_dplls
[i
].id
= i
;
11757 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11758 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11759 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11760 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11761 dev_priv
->shared_dplls
[i
].get_hw_state
=
11762 ibx_pch_dpll_get_hw_state
;
11766 static void intel_shared_dpll_init(struct drm_device
*dev
)
11768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11771 intel_ddi_pll_init(dev
);
11772 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11773 ibx_pch_dpll_init(dev
);
11775 dev_priv
->num_shared_dpll
= 0;
11777 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11781 intel_primary_plane_disable(struct drm_plane
*plane
)
11783 struct drm_device
*dev
= plane
->dev
;
11784 struct intel_crtc
*intel_crtc
;
11789 BUG_ON(!plane
->crtc
);
11791 intel_crtc
= to_intel_crtc(plane
->crtc
);
11794 * Even though we checked plane->fb above, it's still possible that
11795 * the primary plane has been implicitly disabled because the crtc
11796 * coordinates given weren't visible, or because we detected
11797 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11798 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11799 * In either case, we need to unpin the FB and let the fb pointer get
11800 * updated, but otherwise we don't need to touch the hardware.
11802 if (!intel_crtc
->primary_enabled
)
11803 goto disable_unpin
;
11805 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11806 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11809 mutex_lock(&dev
->struct_mutex
);
11810 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11811 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11812 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11813 mutex_unlock(&dev
->struct_mutex
);
11820 intel_check_primary_plane(struct drm_plane
*plane
,
11821 struct intel_plane_state
*state
)
11823 struct drm_crtc
*crtc
= state
->crtc
;
11824 struct drm_framebuffer
*fb
= state
->fb
;
11825 struct drm_rect
*dest
= &state
->dst
;
11826 struct drm_rect
*src
= &state
->src
;
11827 const struct drm_rect
*clip
= &state
->clip
;
11829 return drm_plane_helper_check_update(plane
, crtc
, fb
,
11831 DRM_PLANE_HELPER_NO_SCALING
,
11832 DRM_PLANE_HELPER_NO_SCALING
,
11833 false, true, &state
->visible
);
11837 intel_commit_primary_plane(struct drm_plane
*plane
,
11838 struct intel_plane_state
*state
)
11840 struct drm_crtc
*crtc
= state
->crtc
;
11841 struct drm_framebuffer
*fb
= state
->fb
;
11842 struct drm_device
*dev
= crtc
->dev
;
11843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11844 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11845 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11846 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11847 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11848 struct drm_rect
*src
= &state
->src
;
11851 intel_crtc_wait_for_pending_flips(crtc
);
11854 * If clipping results in a non-visible primary plane, we'll disable
11855 * the primary plane. Note that this is a bit different than what
11856 * happens if userspace explicitly disables the plane by passing fb=0
11857 * because plane->fb still gets set and pinned.
11859 if (!state
->visible
) {
11860 mutex_lock(&dev
->struct_mutex
);
11863 * Try to pin the new fb first so that we can bail out if we
11866 if (plane
->fb
!= fb
) {
11867 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11869 mutex_unlock(&dev
->struct_mutex
);
11874 i915_gem_track_fb(old_obj
, obj
,
11875 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11877 if (intel_crtc
->primary_enabled
)
11878 intel_disable_primary_hw_plane(plane
, crtc
);
11881 if (plane
->fb
!= fb
)
11883 intel_unpin_fb_obj(old_obj
);
11885 mutex_unlock(&dev
->struct_mutex
);
11888 if (intel_crtc
&& intel_crtc
->active
&&
11889 intel_crtc
->primary_enabled
) {
11891 * FBC does not work on some platforms for rotated
11892 * planes, so disable it when rotation is not 0 and
11893 * update it when rotation is set back to 0.
11895 * FIXME: This is redundant with the fbc update done in
11896 * the primary plane enable function except that that
11897 * one is done too late. We eventually need to unify
11900 if (INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11901 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11902 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11903 intel_disable_fbc(dev
);
11906 ret
= intel_pipe_set_base(crtc
, src
->x1
, src
->y1
, fb
);
11910 if (!intel_crtc
->primary_enabled
)
11911 intel_enable_primary_hw_plane(plane
, crtc
);
11914 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
11915 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
11916 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
11917 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
11918 intel_plane
->src_x
= state
->orig_src
.x1
;
11919 intel_plane
->src_y
= state
->orig_src
.y1
;
11920 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
11921 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
11922 intel_plane
->obj
= obj
;
11928 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11929 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11930 unsigned int crtc_w
, unsigned int crtc_h
,
11931 uint32_t src_x
, uint32_t src_y
,
11932 uint32_t src_w
, uint32_t src_h
)
11934 struct intel_plane_state state
;
11935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11941 /* sample coordinates in 16.16 fixed point */
11942 state
.src
.x1
= src_x
;
11943 state
.src
.x2
= src_x
+ src_w
;
11944 state
.src
.y1
= src_y
;
11945 state
.src
.y2
= src_y
+ src_h
;
11947 /* integer pixels */
11948 state
.dst
.x1
= crtc_x
;
11949 state
.dst
.x2
= crtc_x
+ crtc_w
;
11950 state
.dst
.y1
= crtc_y
;
11951 state
.dst
.y2
= crtc_y
+ crtc_h
;
11955 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
11956 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
11958 state
.orig_src
= state
.src
;
11959 state
.orig_dst
= state
.dst
;
11961 ret
= intel_check_primary_plane(plane
, &state
);
11965 intel_commit_primary_plane(plane
, &state
);
11970 /* Common destruction function for both primary and cursor planes */
11971 static void intel_plane_destroy(struct drm_plane
*plane
)
11973 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11974 drm_plane_cleanup(plane
);
11975 kfree(intel_plane
);
11978 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11979 .update_plane
= intel_primary_plane_setplane
,
11980 .disable_plane
= intel_primary_plane_disable
,
11981 .destroy
= intel_plane_destroy
,
11982 .set_property
= intel_plane_set_property
11985 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11988 struct intel_plane
*primary
;
11989 const uint32_t *intel_primary_formats
;
11992 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11993 if (primary
== NULL
)
11996 primary
->can_scale
= false;
11997 primary
->max_downscale
= 1;
11998 primary
->pipe
= pipe
;
11999 primary
->plane
= pipe
;
12000 primary
->rotation
= BIT(DRM_ROTATE_0
);
12001 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
12002 primary
->plane
= !pipe
;
12004 if (INTEL_INFO(dev
)->gen
<= 3) {
12005 intel_primary_formats
= intel_primary_formats_gen2
;
12006 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
12008 intel_primary_formats
= intel_primary_formats_gen4
;
12009 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
12012 drm_universal_plane_init(dev
, &primary
->base
, 0,
12013 &intel_primary_plane_funcs
,
12014 intel_primary_formats
, num_formats
,
12015 DRM_PLANE_TYPE_PRIMARY
);
12017 if (INTEL_INFO(dev
)->gen
>= 4) {
12018 if (!dev
->mode_config
.rotation_property
)
12019 dev
->mode_config
.rotation_property
=
12020 drm_mode_create_rotation_property(dev
,
12021 BIT(DRM_ROTATE_0
) |
12022 BIT(DRM_ROTATE_180
));
12023 if (dev
->mode_config
.rotation_property
)
12024 drm_object_attach_property(&primary
->base
.base
,
12025 dev
->mode_config
.rotation_property
,
12026 primary
->rotation
);
12029 return &primary
->base
;
12033 intel_cursor_plane_disable(struct drm_plane
*plane
)
12038 BUG_ON(!plane
->crtc
);
12040 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
12044 intel_check_cursor_plane(struct drm_plane
*plane
,
12045 struct intel_plane_state
*state
)
12047 struct drm_crtc
*crtc
= state
->crtc
;
12048 struct drm_framebuffer
*fb
= state
->fb
;
12049 struct drm_rect
*dest
= &state
->dst
;
12050 struct drm_rect
*src
= &state
->src
;
12051 const struct drm_rect
*clip
= &state
->clip
;
12053 return drm_plane_helper_check_update(plane
, crtc
, fb
,
12055 DRM_PLANE_HELPER_NO_SCALING
,
12056 DRM_PLANE_HELPER_NO_SCALING
,
12057 true, true, &state
->visible
);
12061 intel_commit_cursor_plane(struct drm_plane
*plane
,
12062 struct intel_plane_state
*state
)
12064 struct drm_crtc
*crtc
= state
->crtc
;
12065 struct drm_framebuffer
*fb
= state
->fb
;
12066 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12067 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12068 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12069 int crtc_w
, crtc_h
;
12071 crtc
->cursor_x
= state
->orig_dst
.x1
;
12072 crtc
->cursor_y
= state
->orig_dst
.y1
;
12073 if (fb
!= crtc
->cursor
->fb
) {
12074 crtc_w
= drm_rect_width(&state
->orig_dst
);
12075 crtc_h
= drm_rect_height(&state
->orig_dst
);
12076 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
12078 intel_crtc_update_cursor(crtc
, state
->visible
);
12080 intel_frontbuffer_flip(crtc
->dev
,
12081 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
12088 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
12089 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
12090 unsigned int crtc_w
, unsigned int crtc_h
,
12091 uint32_t src_x
, uint32_t src_y
,
12092 uint32_t src_w
, uint32_t src_h
)
12094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12095 struct intel_plane_state state
;
12101 /* sample coordinates in 16.16 fixed point */
12102 state
.src
.x1
= src_x
;
12103 state
.src
.x2
= src_x
+ src_w
;
12104 state
.src
.y1
= src_y
;
12105 state
.src
.y2
= src_y
+ src_h
;
12107 /* integer pixels */
12108 state
.dst
.x1
= crtc_x
;
12109 state
.dst
.x2
= crtc_x
+ crtc_w
;
12110 state
.dst
.y1
= crtc_y
;
12111 state
.dst
.y2
= crtc_y
+ crtc_h
;
12115 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
12116 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
12118 state
.orig_src
= state
.src
;
12119 state
.orig_dst
= state
.dst
;
12121 ret
= intel_check_cursor_plane(plane
, &state
);
12125 return intel_commit_cursor_plane(plane
, &state
);
12128 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
12129 .update_plane
= intel_cursor_plane_update
,
12130 .disable_plane
= intel_cursor_plane_disable
,
12131 .destroy
= intel_plane_destroy
,
12134 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12137 struct intel_plane
*cursor
;
12139 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12140 if (cursor
== NULL
)
12143 cursor
->can_scale
= false;
12144 cursor
->max_downscale
= 1;
12145 cursor
->pipe
= pipe
;
12146 cursor
->plane
= pipe
;
12148 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12149 &intel_cursor_plane_funcs
,
12150 intel_cursor_formats
,
12151 ARRAY_SIZE(intel_cursor_formats
),
12152 DRM_PLANE_TYPE_CURSOR
);
12153 return &cursor
->base
;
12156 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12159 struct intel_crtc
*intel_crtc
;
12160 struct drm_plane
*primary
= NULL
;
12161 struct drm_plane
*cursor
= NULL
;
12164 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12165 if (intel_crtc
== NULL
)
12168 primary
= intel_primary_plane_create(dev
, pipe
);
12172 cursor
= intel_cursor_plane_create(dev
, pipe
);
12176 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12177 cursor
, &intel_crtc_funcs
);
12181 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12182 for (i
= 0; i
< 256; i
++) {
12183 intel_crtc
->lut_r
[i
] = i
;
12184 intel_crtc
->lut_g
[i
] = i
;
12185 intel_crtc
->lut_b
[i
] = i
;
12189 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12190 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12192 intel_crtc
->pipe
= pipe
;
12193 intel_crtc
->plane
= pipe
;
12194 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12195 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12196 intel_crtc
->plane
= !pipe
;
12199 intel_crtc
->cursor_base
= ~0;
12200 intel_crtc
->cursor_cntl
= ~0;
12201 intel_crtc
->cursor_size
= ~0;
12203 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12204 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12205 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12206 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12208 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12210 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12215 drm_plane_cleanup(primary
);
12217 drm_plane_cleanup(cursor
);
12221 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12223 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12224 struct drm_device
*dev
= connector
->base
.dev
;
12226 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12229 return INVALID_PIPE
;
12231 return to_intel_crtc(encoder
->crtc
)->pipe
;
12234 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12235 struct drm_file
*file
)
12237 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12238 struct drm_crtc
*drmmode_crtc
;
12239 struct intel_crtc
*crtc
;
12241 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12244 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12246 if (!drmmode_crtc
) {
12247 DRM_ERROR("no such CRTC id\n");
12251 crtc
= to_intel_crtc(drmmode_crtc
);
12252 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12257 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12259 struct drm_device
*dev
= encoder
->base
.dev
;
12260 struct intel_encoder
*source_encoder
;
12261 int index_mask
= 0;
12264 for_each_intel_encoder(dev
, source_encoder
) {
12265 if (encoders_cloneable(encoder
, source_encoder
))
12266 index_mask
|= (1 << entry
);
12274 static bool has_edp_a(struct drm_device
*dev
)
12276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12278 if (!IS_MOBILE(dev
))
12281 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12284 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12290 const char *intel_output_name(int output
)
12292 static const char *names
[] = {
12293 [INTEL_OUTPUT_UNUSED
] = "Unused",
12294 [INTEL_OUTPUT_ANALOG
] = "Analog",
12295 [INTEL_OUTPUT_DVO
] = "DVO",
12296 [INTEL_OUTPUT_SDVO
] = "SDVO",
12297 [INTEL_OUTPUT_LVDS
] = "LVDS",
12298 [INTEL_OUTPUT_TVOUT
] = "TV",
12299 [INTEL_OUTPUT_HDMI
] = "HDMI",
12300 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12301 [INTEL_OUTPUT_EDP
] = "eDP",
12302 [INTEL_OUTPUT_DSI
] = "DSI",
12303 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12306 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12309 return names
[output
];
12312 static bool intel_crt_present(struct drm_device
*dev
)
12314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12319 if (IS_CHERRYVIEW(dev
))
12322 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12328 static void intel_setup_outputs(struct drm_device
*dev
)
12330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12331 struct intel_encoder
*encoder
;
12332 bool dpd_is_edp
= false;
12334 intel_lvds_init(dev
);
12336 if (intel_crt_present(dev
))
12337 intel_crt_init(dev
);
12339 if (HAS_DDI(dev
)) {
12342 /* Haswell uses DDI functions to detect digital outputs */
12343 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12344 /* DDI A only supports eDP */
12346 intel_ddi_init(dev
, PORT_A
);
12348 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12350 found
= I915_READ(SFUSE_STRAP
);
12352 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12353 intel_ddi_init(dev
, PORT_B
);
12354 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12355 intel_ddi_init(dev
, PORT_C
);
12356 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12357 intel_ddi_init(dev
, PORT_D
);
12358 } else if (HAS_PCH_SPLIT(dev
)) {
12360 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12362 if (has_edp_a(dev
))
12363 intel_dp_init(dev
, DP_A
, PORT_A
);
12365 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12366 /* PCH SDVOB multiplex with HDMIB */
12367 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12369 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12370 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12371 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12374 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12375 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12377 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12378 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12380 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12381 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12383 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12384 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12385 } else if (IS_VALLEYVIEW(dev
)) {
12386 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
12387 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12389 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
12390 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12393 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
12394 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12396 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
12397 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12400 if (IS_CHERRYVIEW(dev
)) {
12401 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
12402 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12404 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12405 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12409 intel_dsi_init(dev
);
12410 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12411 bool found
= false;
12413 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12414 DRM_DEBUG_KMS("probing SDVOB\n");
12415 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12416 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12417 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12418 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12421 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12422 intel_dp_init(dev
, DP_B
, PORT_B
);
12425 /* Before G4X SDVOC doesn't have its own detect register */
12427 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12428 DRM_DEBUG_KMS("probing SDVOC\n");
12429 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12432 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12434 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12435 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12436 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12438 if (SUPPORTS_INTEGRATED_DP(dev
))
12439 intel_dp_init(dev
, DP_C
, PORT_C
);
12442 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12443 (I915_READ(DP_D
) & DP_DETECTED
))
12444 intel_dp_init(dev
, DP_D
, PORT_D
);
12445 } else if (IS_GEN2(dev
))
12446 intel_dvo_init(dev
);
12448 if (SUPPORTS_TV(dev
))
12449 intel_tv_init(dev
);
12451 intel_edp_psr_init(dev
);
12453 for_each_intel_encoder(dev
, encoder
) {
12454 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12455 encoder
->base
.possible_clones
=
12456 intel_encoder_clones(encoder
);
12459 intel_init_pch_refclk(dev
);
12461 drm_helper_move_panel_connectors_to_head(dev
);
12464 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12466 struct drm_device
*dev
= fb
->dev
;
12467 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12469 drm_framebuffer_cleanup(fb
);
12470 mutex_lock(&dev
->struct_mutex
);
12471 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12472 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12473 mutex_unlock(&dev
->struct_mutex
);
12477 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12478 struct drm_file
*file
,
12479 unsigned int *handle
)
12481 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12482 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12484 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12487 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12488 .destroy
= intel_user_framebuffer_destroy
,
12489 .create_handle
= intel_user_framebuffer_create_handle
,
12492 static int intel_framebuffer_init(struct drm_device
*dev
,
12493 struct intel_framebuffer
*intel_fb
,
12494 struct drm_mode_fb_cmd2
*mode_cmd
,
12495 struct drm_i915_gem_object
*obj
)
12497 int aligned_height
;
12501 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12503 if (obj
->tiling_mode
== I915_TILING_Y
) {
12504 DRM_DEBUG("hardware does not support tiling Y\n");
12508 if (mode_cmd
->pitches
[0] & 63) {
12509 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12510 mode_cmd
->pitches
[0]);
12514 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12515 pitch_limit
= 32*1024;
12516 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12517 if (obj
->tiling_mode
)
12518 pitch_limit
= 16*1024;
12520 pitch_limit
= 32*1024;
12521 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12522 if (obj
->tiling_mode
)
12523 pitch_limit
= 8*1024;
12525 pitch_limit
= 16*1024;
12527 /* XXX DSPC is limited to 4k tiled */
12528 pitch_limit
= 8*1024;
12530 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12531 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12532 obj
->tiling_mode
? "tiled" : "linear",
12533 mode_cmd
->pitches
[0], pitch_limit
);
12537 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12538 mode_cmd
->pitches
[0] != obj
->stride
) {
12539 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12540 mode_cmd
->pitches
[0], obj
->stride
);
12544 /* Reject formats not supported by any plane early. */
12545 switch (mode_cmd
->pixel_format
) {
12546 case DRM_FORMAT_C8
:
12547 case DRM_FORMAT_RGB565
:
12548 case DRM_FORMAT_XRGB8888
:
12549 case DRM_FORMAT_ARGB8888
:
12551 case DRM_FORMAT_XRGB1555
:
12552 case DRM_FORMAT_ARGB1555
:
12553 if (INTEL_INFO(dev
)->gen
> 3) {
12554 DRM_DEBUG("unsupported pixel format: %s\n",
12555 drm_get_format_name(mode_cmd
->pixel_format
));
12559 case DRM_FORMAT_XBGR8888
:
12560 case DRM_FORMAT_ABGR8888
:
12561 case DRM_FORMAT_XRGB2101010
:
12562 case DRM_FORMAT_ARGB2101010
:
12563 case DRM_FORMAT_XBGR2101010
:
12564 case DRM_FORMAT_ABGR2101010
:
12565 if (INTEL_INFO(dev
)->gen
< 4) {
12566 DRM_DEBUG("unsupported pixel format: %s\n",
12567 drm_get_format_name(mode_cmd
->pixel_format
));
12571 case DRM_FORMAT_YUYV
:
12572 case DRM_FORMAT_UYVY
:
12573 case DRM_FORMAT_YVYU
:
12574 case DRM_FORMAT_VYUY
:
12575 if (INTEL_INFO(dev
)->gen
< 5) {
12576 DRM_DEBUG("unsupported pixel format: %s\n",
12577 drm_get_format_name(mode_cmd
->pixel_format
));
12582 DRM_DEBUG("unsupported pixel format: %s\n",
12583 drm_get_format_name(mode_cmd
->pixel_format
));
12587 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12588 if (mode_cmd
->offsets
[0] != 0)
12591 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12593 /* FIXME drm helper for size checks (especially planar formats)? */
12594 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12597 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12598 intel_fb
->obj
= obj
;
12599 intel_fb
->obj
->framebuffer_references
++;
12601 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12603 DRM_ERROR("framebuffer init failed %d\n", ret
);
12610 static struct drm_framebuffer
*
12611 intel_user_framebuffer_create(struct drm_device
*dev
,
12612 struct drm_file
*filp
,
12613 struct drm_mode_fb_cmd2
*mode_cmd
)
12615 struct drm_i915_gem_object
*obj
;
12617 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12618 mode_cmd
->handles
[0]));
12619 if (&obj
->base
== NULL
)
12620 return ERR_PTR(-ENOENT
);
12622 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12625 #ifndef CONFIG_DRM_I915_FBDEV
12626 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12631 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12632 .fb_create
= intel_user_framebuffer_create
,
12633 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12636 /* Set up chip specific display functions */
12637 static void intel_init_display(struct drm_device
*dev
)
12639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12641 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12642 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12643 else if (IS_CHERRYVIEW(dev
))
12644 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12645 else if (IS_VALLEYVIEW(dev
))
12646 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12647 else if (IS_PINEVIEW(dev
))
12648 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12650 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12652 if (HAS_DDI(dev
)) {
12653 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12654 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12655 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12656 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12657 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12658 dev_priv
->display
.off
= ironlake_crtc_off
;
12659 dev_priv
->display
.update_primary_plane
=
12660 ironlake_update_primary_plane
;
12661 } else if (HAS_PCH_SPLIT(dev
)) {
12662 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12663 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12664 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12665 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12666 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12667 dev_priv
->display
.off
= ironlake_crtc_off
;
12668 dev_priv
->display
.update_primary_plane
=
12669 ironlake_update_primary_plane
;
12670 } else if (IS_VALLEYVIEW(dev
)) {
12671 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12672 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12673 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12674 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12675 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12676 dev_priv
->display
.off
= i9xx_crtc_off
;
12677 dev_priv
->display
.update_primary_plane
=
12678 i9xx_update_primary_plane
;
12680 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12681 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12682 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12683 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12684 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12685 dev_priv
->display
.off
= i9xx_crtc_off
;
12686 dev_priv
->display
.update_primary_plane
=
12687 i9xx_update_primary_plane
;
12690 /* Returns the core display clock speed */
12691 if (IS_VALLEYVIEW(dev
))
12692 dev_priv
->display
.get_display_clock_speed
=
12693 valleyview_get_display_clock_speed
;
12694 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12695 dev_priv
->display
.get_display_clock_speed
=
12696 i945_get_display_clock_speed
;
12697 else if (IS_I915G(dev
))
12698 dev_priv
->display
.get_display_clock_speed
=
12699 i915_get_display_clock_speed
;
12700 else if (IS_I945GM(dev
) || IS_845G(dev
))
12701 dev_priv
->display
.get_display_clock_speed
=
12702 i9xx_misc_get_display_clock_speed
;
12703 else if (IS_PINEVIEW(dev
))
12704 dev_priv
->display
.get_display_clock_speed
=
12705 pnv_get_display_clock_speed
;
12706 else if (IS_I915GM(dev
))
12707 dev_priv
->display
.get_display_clock_speed
=
12708 i915gm_get_display_clock_speed
;
12709 else if (IS_I865G(dev
))
12710 dev_priv
->display
.get_display_clock_speed
=
12711 i865_get_display_clock_speed
;
12712 else if (IS_I85X(dev
))
12713 dev_priv
->display
.get_display_clock_speed
=
12714 i855_get_display_clock_speed
;
12715 else /* 852, 830 */
12716 dev_priv
->display
.get_display_clock_speed
=
12717 i830_get_display_clock_speed
;
12720 dev_priv
->display
.write_eld
= g4x_write_eld
;
12721 } else if (IS_GEN5(dev
)) {
12722 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12723 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12724 } else if (IS_GEN6(dev
)) {
12725 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12726 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12727 dev_priv
->display
.modeset_global_resources
=
12728 snb_modeset_global_resources
;
12729 } else if (IS_IVYBRIDGE(dev
)) {
12730 /* FIXME: detect B0+ stepping and use auto training */
12731 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12732 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12733 dev_priv
->display
.modeset_global_resources
=
12734 ivb_modeset_global_resources
;
12735 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12736 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12737 dev_priv
->display
.write_eld
= haswell_write_eld
;
12738 dev_priv
->display
.modeset_global_resources
=
12739 haswell_modeset_global_resources
;
12740 } else if (IS_VALLEYVIEW(dev
)) {
12741 dev_priv
->display
.modeset_global_resources
=
12742 valleyview_modeset_global_resources
;
12743 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12746 /* Default just returns -ENODEV to indicate unsupported */
12747 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12749 switch (INTEL_INFO(dev
)->gen
) {
12751 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12755 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12760 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12764 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12767 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12768 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12772 intel_panel_init_backlight_funcs(dev
);
12774 mutex_init(&dev_priv
->pps_mutex
);
12778 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12779 * resume, or other times. This quirk makes sure that's the case for
12780 * affected systems.
12782 static void quirk_pipea_force(struct drm_device
*dev
)
12784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12786 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12787 DRM_INFO("applying pipe a force quirk\n");
12790 static void quirk_pipeb_force(struct drm_device
*dev
)
12792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12794 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12795 DRM_INFO("applying pipe b force quirk\n");
12799 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12801 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12804 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12805 DRM_INFO("applying lvds SSC disable quirk\n");
12809 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12812 static void quirk_invert_brightness(struct drm_device
*dev
)
12814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12815 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12816 DRM_INFO("applying inverted panel brightness quirk\n");
12819 /* Some VBT's incorrectly indicate no backlight is present */
12820 static void quirk_backlight_present(struct drm_device
*dev
)
12822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12823 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12824 DRM_INFO("applying backlight present quirk\n");
12827 struct intel_quirk
{
12829 int subsystem_vendor
;
12830 int subsystem_device
;
12831 void (*hook
)(struct drm_device
*dev
);
12834 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12835 struct intel_dmi_quirk
{
12836 void (*hook
)(struct drm_device
*dev
);
12837 const struct dmi_system_id (*dmi_id_list
)[];
12840 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12842 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12846 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12848 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12850 .callback
= intel_dmi_reverse_brightness
,
12851 .ident
= "NCR Corporation",
12852 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12853 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12856 { } /* terminating entry */
12858 .hook
= quirk_invert_brightness
,
12862 static struct intel_quirk intel_quirks
[] = {
12863 /* HP Mini needs pipe A force quirk (LP: #322104) */
12864 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12866 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12867 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12869 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12870 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12872 /* 830 needs to leave pipe A & dpll A up */
12873 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12875 /* 830 needs to leave pipe B & dpll B up */
12876 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12878 /* Lenovo U160 cannot use SSC on LVDS */
12879 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12881 /* Sony Vaio Y cannot use SSC on LVDS */
12882 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12884 /* Acer Aspire 5734Z must invert backlight brightness */
12885 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12887 /* Acer/eMachines G725 */
12888 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12890 /* Acer/eMachines e725 */
12891 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12893 /* Acer/Packard Bell NCL20 */
12894 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12896 /* Acer Aspire 4736Z */
12897 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12899 /* Acer Aspire 5336 */
12900 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12902 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12903 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12905 /* Acer C720 Chromebook (Core i3 4005U) */
12906 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
12908 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12909 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12911 /* HP Chromebook 14 (Celeron 2955U) */
12912 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12915 static void intel_init_quirks(struct drm_device
*dev
)
12917 struct pci_dev
*d
= dev
->pdev
;
12920 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12921 struct intel_quirk
*q
= &intel_quirks
[i
];
12923 if (d
->device
== q
->device
&&
12924 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12925 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12926 (d
->subsystem_device
== q
->subsystem_device
||
12927 q
->subsystem_device
== PCI_ANY_ID
))
12930 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12931 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12932 intel_dmi_quirks
[i
].hook(dev
);
12936 /* Disable the VGA plane that we never use */
12937 static void i915_disable_vga(struct drm_device
*dev
)
12939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12941 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12943 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12944 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12945 outb(SR01
, VGA_SR_INDEX
);
12946 sr1
= inb(VGA_SR_DATA
);
12947 outb(sr1
| 1<<5, VGA_SR_DATA
);
12948 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12952 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12953 * from S3 without preserving (some of?) the other bits.
12955 I915_WRITE(vga_reg
, dev_priv
->bios_vgacntr
| VGA_DISP_DISABLE
);
12956 POSTING_READ(vga_reg
);
12959 void intel_modeset_init_hw(struct drm_device
*dev
)
12961 intel_prepare_ddi(dev
);
12963 if (IS_VALLEYVIEW(dev
))
12964 vlv_update_cdclk(dev
);
12966 intel_init_clock_gating(dev
);
12968 intel_enable_gt_powersave(dev
);
12971 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12973 intel_suspend_hw(dev
);
12976 void intel_modeset_init(struct drm_device
*dev
)
12978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12981 struct intel_crtc
*crtc
;
12983 drm_mode_config_init(dev
);
12985 dev
->mode_config
.min_width
= 0;
12986 dev
->mode_config
.min_height
= 0;
12988 dev
->mode_config
.preferred_depth
= 24;
12989 dev
->mode_config
.prefer_shadow
= 1;
12991 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12993 intel_init_quirks(dev
);
12995 intel_init_pm(dev
);
12997 if (INTEL_INFO(dev
)->num_pipes
== 0)
13000 intel_init_display(dev
);
13002 if (IS_GEN2(dev
)) {
13003 dev
->mode_config
.max_width
= 2048;
13004 dev
->mode_config
.max_height
= 2048;
13005 } else if (IS_GEN3(dev
)) {
13006 dev
->mode_config
.max_width
= 4096;
13007 dev
->mode_config
.max_height
= 4096;
13009 dev
->mode_config
.max_width
= 8192;
13010 dev
->mode_config
.max_height
= 8192;
13013 if (IS_845G(dev
) || IS_I865G(dev
)) {
13014 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13015 dev
->mode_config
.cursor_height
= 1023;
13016 } else if (IS_GEN2(dev
)) {
13017 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13018 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13020 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13021 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13024 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13026 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13027 INTEL_INFO(dev
)->num_pipes
,
13028 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
13030 for_each_pipe(dev_priv
, pipe
) {
13031 intel_crtc_init(dev
, pipe
);
13032 for_each_sprite(pipe
, sprite
) {
13033 ret
= intel_plane_init(dev
, pipe
, sprite
);
13035 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13036 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
13040 intel_init_dpio(dev
);
13042 intel_shared_dpll_init(dev
);
13044 /* save the BIOS value before clobbering it */
13045 dev_priv
->bios_vgacntr
= I915_READ(i915_vgacntrl_reg(dev
));
13046 /* Just disable it once at startup */
13047 i915_disable_vga(dev
);
13048 intel_setup_outputs(dev
);
13050 /* Just in case the BIOS is doing something questionable. */
13051 intel_disable_fbc(dev
);
13053 drm_modeset_lock_all(dev
);
13054 intel_modeset_setup_hw_state(dev
, false);
13055 drm_modeset_unlock_all(dev
);
13057 for_each_intel_crtc(dev
, crtc
) {
13062 * Note that reserving the BIOS fb up front prevents us
13063 * from stuffing other stolen allocations like the ring
13064 * on top. This prevents some ugliness at boot time, and
13065 * can even allow for smooth boot transitions if the BIOS
13066 * fb is large enough for the active pipe configuration.
13068 if (dev_priv
->display
.get_plane_config
) {
13069 dev_priv
->display
.get_plane_config(crtc
,
13070 &crtc
->plane_config
);
13072 * If the fb is shared between multiple heads, we'll
13073 * just get the first one.
13075 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13080 static void intel_enable_pipe_a(struct drm_device
*dev
)
13082 struct intel_connector
*connector
;
13083 struct drm_connector
*crt
= NULL
;
13084 struct intel_load_detect_pipe load_detect_temp
;
13085 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13087 /* We can't just switch on the pipe A, we need to set things up with a
13088 * proper mode and output configuration. As a gross hack, enable pipe A
13089 * by enabling the load detect pipe once. */
13090 list_for_each_entry(connector
,
13091 &dev
->mode_config
.connector_list
,
13093 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13094 crt
= &connector
->base
;
13102 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13103 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13107 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13109 struct drm_device
*dev
= crtc
->base
.dev
;
13110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13113 if (INTEL_INFO(dev
)->num_pipes
== 1)
13116 reg
= DSPCNTR(!crtc
->plane
);
13117 val
= I915_READ(reg
);
13119 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13120 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13126 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13128 struct drm_device
*dev
= crtc
->base
.dev
;
13129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13132 /* Clear any frame start delays used for debugging left by the BIOS */
13133 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
13134 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13136 /* restore vblank interrupts to correct state */
13137 if (crtc
->active
) {
13138 update_scanline_offset(crtc
);
13139 drm_vblank_on(dev
, crtc
->pipe
);
13141 drm_vblank_off(dev
, crtc
->pipe
);
13143 /* We need to sanitize the plane -> pipe mapping first because this will
13144 * disable the crtc (and hence change the state) if it is wrong. Note
13145 * that gen4+ has a fixed plane -> pipe mapping. */
13146 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13147 struct intel_connector
*connector
;
13150 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13151 crtc
->base
.base
.id
);
13153 /* Pipe has the wrong plane attached and the plane is active.
13154 * Temporarily change the plane mapping and disable everything
13156 plane
= crtc
->plane
;
13157 crtc
->plane
= !plane
;
13158 crtc
->primary_enabled
= true;
13159 dev_priv
->display
.crtc_disable(&crtc
->base
);
13160 crtc
->plane
= plane
;
13162 /* ... and break all links. */
13163 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13165 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13168 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13169 connector
->base
.encoder
= NULL
;
13171 /* multiple connectors may have the same encoder:
13172 * handle them and break crtc link separately */
13173 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13175 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13176 connector
->encoder
->base
.crtc
= NULL
;
13177 connector
->encoder
->connectors_active
= false;
13180 WARN_ON(crtc
->active
);
13181 crtc
->base
.enabled
= false;
13184 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13185 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13186 /* BIOS forgot to enable pipe A, this mostly happens after
13187 * resume. Force-enable the pipe to fix this, the update_dpms
13188 * call below we restore the pipe to the right state, but leave
13189 * the required bits on. */
13190 intel_enable_pipe_a(dev
);
13193 /* Adjust the state of the output pipe according to whether we
13194 * have active connectors/encoders. */
13195 intel_crtc_update_dpms(&crtc
->base
);
13197 if (crtc
->active
!= crtc
->base
.enabled
) {
13198 struct intel_encoder
*encoder
;
13200 /* This can happen either due to bugs in the get_hw_state
13201 * functions or because the pipe is force-enabled due to the
13203 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13204 crtc
->base
.base
.id
,
13205 crtc
->base
.enabled
? "enabled" : "disabled",
13206 crtc
->active
? "enabled" : "disabled");
13208 crtc
->base
.enabled
= crtc
->active
;
13210 /* Because we only establish the connector -> encoder ->
13211 * crtc links if something is active, this means the
13212 * crtc is now deactivated. Break the links. connector
13213 * -> encoder links are only establish when things are
13214 * actually up, hence no need to break them. */
13215 WARN_ON(crtc
->active
);
13217 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13218 WARN_ON(encoder
->connectors_active
);
13219 encoder
->base
.crtc
= NULL
;
13223 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13225 * We start out with underrun reporting disabled to avoid races.
13226 * For correct bookkeeping mark this on active crtcs.
13228 * Also on gmch platforms we dont have any hardware bits to
13229 * disable the underrun reporting. Which means we need to start
13230 * out with underrun reporting disabled also on inactive pipes,
13231 * since otherwise we'll complain about the garbage we read when
13232 * e.g. coming up after runtime pm.
13234 * No protection against concurrent access is required - at
13235 * worst a fifo underrun happens which also sets this to false.
13237 crtc
->cpu_fifo_underrun_disabled
= true;
13238 crtc
->pch_fifo_underrun_disabled
= true;
13242 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13244 struct intel_connector
*connector
;
13245 struct drm_device
*dev
= encoder
->base
.dev
;
13247 /* We need to check both for a crtc link (meaning that the
13248 * encoder is active and trying to read from a pipe) and the
13249 * pipe itself being active. */
13250 bool has_active_crtc
= encoder
->base
.crtc
&&
13251 to_intel_crtc(encoder
->base
.crtc
)->active
;
13253 if (encoder
->connectors_active
&& !has_active_crtc
) {
13254 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13255 encoder
->base
.base
.id
,
13256 encoder
->base
.name
);
13258 /* Connector is active, but has no active pipe. This is
13259 * fallout from our resume register restoring. Disable
13260 * the encoder manually again. */
13261 if (encoder
->base
.crtc
) {
13262 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13263 encoder
->base
.base
.id
,
13264 encoder
->base
.name
);
13265 encoder
->disable(encoder
);
13266 if (encoder
->post_disable
)
13267 encoder
->post_disable(encoder
);
13269 encoder
->base
.crtc
= NULL
;
13270 encoder
->connectors_active
= false;
13272 /* Inconsistent output/port/pipe state happens presumably due to
13273 * a bug in one of the get_hw_state functions. Or someplace else
13274 * in our code, like the register restore mess on resume. Clamp
13275 * things to off as a safer default. */
13276 list_for_each_entry(connector
,
13277 &dev
->mode_config
.connector_list
,
13279 if (connector
->encoder
!= encoder
)
13281 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13282 connector
->base
.encoder
= NULL
;
13285 /* Enabled encoders without active connectors will be fixed in
13286 * the crtc fixup. */
13289 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13292 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13294 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13295 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13296 i915_disable_vga(dev
);
13300 void i915_redisable_vga(struct drm_device
*dev
)
13302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13304 /* This function can be called both from intel_modeset_setup_hw_state or
13305 * at a very early point in our resume sequence, where the power well
13306 * structures are not yet restored. Since this function is at a very
13307 * paranoid "someone might have enabled VGA while we were not looking"
13308 * level, just check if the power well is enabled instead of trying to
13309 * follow the "don't touch the power well if we don't need it" policy
13310 * the rest of the driver uses. */
13311 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13314 i915_redisable_vga_power_on(dev
);
13317 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13319 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13324 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13327 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13331 struct intel_crtc
*crtc
;
13332 struct intel_encoder
*encoder
;
13333 struct intel_connector
*connector
;
13336 for_each_intel_crtc(dev
, crtc
) {
13337 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13339 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13341 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13344 crtc
->base
.enabled
= crtc
->active
;
13345 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13347 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13348 crtc
->base
.base
.id
,
13349 crtc
->active
? "enabled" : "disabled");
13352 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13353 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13355 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
13357 for_each_intel_crtc(dev
, crtc
) {
13358 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
13361 pll
->refcount
= pll
->active
;
13363 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13364 pll
->name
, pll
->refcount
, pll
->on
);
13367 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13370 for_each_intel_encoder(dev
, encoder
) {
13373 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13374 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13375 encoder
->base
.crtc
= &crtc
->base
;
13376 encoder
->get_config(encoder
, &crtc
->config
);
13378 encoder
->base
.crtc
= NULL
;
13381 encoder
->connectors_active
= false;
13382 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13383 encoder
->base
.base
.id
,
13384 encoder
->base
.name
,
13385 encoder
->base
.crtc
? "enabled" : "disabled",
13389 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13391 if (connector
->get_hw_state(connector
)) {
13392 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13393 connector
->encoder
->connectors_active
= true;
13394 connector
->base
.encoder
= &connector
->encoder
->base
;
13396 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13397 connector
->base
.encoder
= NULL
;
13399 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13400 connector
->base
.base
.id
,
13401 connector
->base
.name
,
13402 connector
->base
.encoder
? "enabled" : "disabled");
13406 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13407 * and i915 state tracking structures. */
13408 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13409 bool force_restore
)
13411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13413 struct intel_crtc
*crtc
;
13414 struct intel_encoder
*encoder
;
13417 intel_modeset_readout_hw_state(dev
);
13420 * Now that we have the config, copy it to each CRTC struct
13421 * Note that this could go away if we move to using crtc_config
13422 * checking everywhere.
13424 for_each_intel_crtc(dev
, crtc
) {
13425 if (crtc
->active
&& i915
.fastboot
) {
13426 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13427 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13428 crtc
->base
.base
.id
);
13429 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13433 /* HW state is read out, now we need to sanitize this mess. */
13434 for_each_intel_encoder(dev
, encoder
) {
13435 intel_sanitize_encoder(encoder
);
13438 for_each_pipe(dev_priv
, pipe
) {
13439 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13440 intel_sanitize_crtc(crtc
);
13441 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13444 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13445 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13447 if (!pll
->on
|| pll
->active
)
13450 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13452 pll
->disable(dev_priv
, pll
);
13456 if (HAS_PCH_SPLIT(dev
))
13457 ilk_wm_get_hw_state(dev
);
13459 if (force_restore
) {
13460 i915_redisable_vga(dev
);
13463 * We need to use raw interfaces for restoring state to avoid
13464 * checking (bogus) intermediate states.
13466 for_each_pipe(dev_priv
, pipe
) {
13467 struct drm_crtc
*crtc
=
13468 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13470 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13471 crtc
->primary
->fb
);
13474 intel_modeset_update_staged_output_state(dev
);
13477 intel_modeset_check_state(dev
);
13480 void intel_modeset_gem_init(struct drm_device
*dev
)
13482 struct drm_crtc
*c
;
13483 struct drm_i915_gem_object
*obj
;
13485 mutex_lock(&dev
->struct_mutex
);
13486 intel_init_gt_powersave(dev
);
13487 mutex_unlock(&dev
->struct_mutex
);
13489 intel_modeset_init_hw(dev
);
13491 intel_setup_overlay(dev
);
13494 * Make sure any fbs we allocated at startup are properly
13495 * pinned & fenced. When we do the allocation it's too early
13498 mutex_lock(&dev
->struct_mutex
);
13499 for_each_crtc(dev
, c
) {
13500 obj
= intel_fb_obj(c
->primary
->fb
);
13504 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13505 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13506 to_intel_crtc(c
)->pipe
);
13507 drm_framebuffer_unreference(c
->primary
->fb
);
13508 c
->primary
->fb
= NULL
;
13511 mutex_unlock(&dev
->struct_mutex
);
13514 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13516 struct drm_connector
*connector
= &intel_connector
->base
;
13518 intel_panel_destroy_backlight(connector
);
13519 drm_connector_unregister(connector
);
13522 void intel_modeset_cleanup(struct drm_device
*dev
)
13524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13525 struct drm_connector
*connector
;
13528 * Interrupts and polling as the first thing to avoid creating havoc.
13529 * Too much stuff here (turning of rps, connectors, ...) would
13530 * experience fancy races otherwise.
13532 drm_irq_uninstall(dev
);
13533 intel_hpd_cancel_work(dev_priv
);
13534 dev_priv
->pm
._irqs_disabled
= true;
13537 * Due to the hpd irq storm handling the hotplug work can re-arm the
13538 * poll handlers. Hence disable polling after hpd handling is shut down.
13540 drm_kms_helper_poll_fini(dev
);
13542 mutex_lock(&dev
->struct_mutex
);
13544 intel_unregister_dsm_handler();
13546 intel_disable_fbc(dev
);
13548 intel_disable_gt_powersave(dev
);
13550 ironlake_teardown_rc6(dev
);
13552 mutex_unlock(&dev
->struct_mutex
);
13554 /* flush any delayed tasks or pending work */
13555 flush_scheduled_work();
13557 /* destroy the backlight and sysfs files before encoders/connectors */
13558 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13559 struct intel_connector
*intel_connector
;
13561 intel_connector
= to_intel_connector(connector
);
13562 intel_connector
->unregister(intel_connector
);
13565 drm_mode_config_cleanup(dev
);
13567 intel_cleanup_overlay(dev
);
13569 mutex_lock(&dev
->struct_mutex
);
13570 intel_cleanup_gt_powersave(dev
);
13571 mutex_unlock(&dev
->struct_mutex
);
13575 * Return which encoder is currently attached for connector.
13577 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13579 return &intel_attached_encoder(connector
)->base
;
13582 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13583 struct intel_encoder
*encoder
)
13585 connector
->encoder
= encoder
;
13586 drm_mode_connector_attach_encoder(&connector
->base
,
13591 * set vga decode state - true == enable VGA decode
13593 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13596 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13599 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13600 DRM_ERROR("failed to read control word\n");
13604 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13608 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13610 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13612 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13613 DRM_ERROR("failed to write control word\n");
13620 struct intel_display_error_state
{
13622 u32 power_well_driver
;
13624 int num_transcoders
;
13626 struct intel_cursor_error_state
{
13631 } cursor
[I915_MAX_PIPES
];
13633 struct intel_pipe_error_state
{
13634 bool power_domain_on
;
13637 } pipe
[I915_MAX_PIPES
];
13639 struct intel_plane_error_state
{
13647 } plane
[I915_MAX_PIPES
];
13649 struct intel_transcoder_error_state
{
13650 bool power_domain_on
;
13651 enum transcoder cpu_transcoder
;
13664 struct intel_display_error_state
*
13665 intel_display_capture_error_state(struct drm_device
*dev
)
13667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13668 struct intel_display_error_state
*error
;
13669 int transcoders
[] = {
13677 if (INTEL_INFO(dev
)->num_pipes
== 0)
13680 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13684 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13685 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13687 for_each_pipe(dev_priv
, i
) {
13688 error
->pipe
[i
].power_domain_on
=
13689 intel_display_power_enabled_unlocked(dev_priv
,
13690 POWER_DOMAIN_PIPE(i
));
13691 if (!error
->pipe
[i
].power_domain_on
)
13694 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13695 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13696 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13698 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13699 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13700 if (INTEL_INFO(dev
)->gen
<= 3) {
13701 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13702 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13704 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13705 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13706 if (INTEL_INFO(dev
)->gen
>= 4) {
13707 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13708 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13711 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13713 if (HAS_GMCH_DISPLAY(dev
))
13714 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13717 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13718 if (HAS_DDI(dev_priv
->dev
))
13719 error
->num_transcoders
++; /* Account for eDP. */
13721 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13722 enum transcoder cpu_transcoder
= transcoders
[i
];
13724 error
->transcoder
[i
].power_domain_on
=
13725 intel_display_power_enabled_unlocked(dev_priv
,
13726 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13727 if (!error
->transcoder
[i
].power_domain_on
)
13730 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13732 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13733 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13734 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13735 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13736 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13737 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13738 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13744 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13747 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13748 struct drm_device
*dev
,
13749 struct intel_display_error_state
*error
)
13751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13757 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13758 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13759 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13760 error
->power_well_driver
);
13761 for_each_pipe(dev_priv
, i
) {
13762 err_printf(m
, "Pipe [%d]:\n", i
);
13763 err_printf(m
, " Power: %s\n",
13764 error
->pipe
[i
].power_domain_on
? "on" : "off");
13765 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13766 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13768 err_printf(m
, "Plane [%d]:\n", i
);
13769 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13770 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13771 if (INTEL_INFO(dev
)->gen
<= 3) {
13772 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13773 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13775 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13776 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13777 if (INTEL_INFO(dev
)->gen
>= 4) {
13778 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13779 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13782 err_printf(m
, "Cursor [%d]:\n", i
);
13783 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13784 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13785 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13788 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13789 err_printf(m
, "CPU transcoder: %c\n",
13790 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13791 err_printf(m
, " Power: %s\n",
13792 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13793 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13794 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13795 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13796 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13797 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13798 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13799 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13803 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13805 struct intel_crtc
*crtc
;
13807 for_each_intel_crtc(dev
, crtc
) {
13808 struct intel_unpin_work
*work
;
13809 unsigned long irqflags
;
13811 spin_lock_irqsave(&dev
->event_lock
, irqflags
);
13813 work
= crtc
->unpin_work
;
13815 if (work
&& work
->event
&&
13816 work
->event
->base
.file_priv
== file
) {
13817 kfree(work
->event
);
13818 work
->event
= NULL
;
13821 spin_unlock_irqrestore(&dev
->event_lock
, irqflags
);