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drm/i915: Use GGTT view when (un)pinning objects to planes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105
106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 {
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112 }
113
114 typedef struct {
115 int min, max;
116 } intel_range_t;
117
118 typedef struct {
119 int dot_limit;
120 int p2_slow, p2_fast;
121 } intel_p2_t;
122
123 typedef struct intel_limit intel_limit_t;
124 struct intel_limit {
125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
127 };
128
129 int
130 intel_pch_rawclk(struct drm_device *dev)
131 {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137 }
138
139 static inline u32 /* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device *dev)
141 {
142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
147 }
148
149 static const intel_limit_t intel_limits_i8xx_dac = {
150 .dot = { .min = 25000, .max = 350000 },
151 .vco = { .min = 908000, .max = 1512000 },
152 .n = { .min = 2, .max = 16 },
153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
160 };
161
162 static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
164 .vco = { .min = 908000, .max = 1512000 },
165 .n = { .min = 2, .max = 16 },
166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173 };
174
175 static const intel_limit_t intel_limits_i8xx_lvds = {
176 .dot = { .min = 25000, .max = 350000 },
177 .vco = { .min = 908000, .max = 1512000 },
178 .n = { .min = 2, .max = 16 },
179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
186 };
187
188 static const intel_limit_t intel_limits_i9xx_sdvo = {
189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
199 };
200
201 static const intel_limit_t intel_limits_i9xx_lvds = {
202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
212 };
213
214
215 static const intel_limit_t intel_limits_g4x_sdvo = {
216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
227 },
228 };
229
230 static const intel_limit_t intel_limits_g4x_hdmi = {
231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
254 },
255 };
256
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
268 },
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 };
285
286 static const intel_limit_t intel_limits_pineview_lvds = {
287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 /* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
304 static const intel_limit_t intel_limits_ironlake_dac = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
315 };
316
317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 };
342
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
352 .p1 = { .min = 2, .max = 8 },
353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
355 };
356
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
365 .p1 = { .min = 2, .max = 6 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
368 };
369
370 static const intel_limit_t intel_limits_vlv = {
371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378 .vco = { .min = 4000000, .max = 6000000 },
379 .n = { .min = 1, .max = 7 },
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p1 = { .min = 2, .max = 3 },
383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384 };
385
386 static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
394 .vco = { .min = 4800000, .max = 6480000 },
395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400 };
401
402 static void vlv_clock(int refclk, intel_clock_t *clock)
403 {
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
410 }
411
412 /**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 {
417 struct drm_device *dev = crtc->base.dev;
418 struct intel_encoder *encoder;
419
420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421 if (encoder->type == type)
422 return true;
423
424 return false;
425 }
426
427 /**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
446 int refclk)
447 {
448 struct drm_device *dev = crtc->base.dev;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (intel_is_dual_link_lvds(dev)) {
453 if (refclk == 100000)
454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
458 if (refclk == 100000)
459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
463 } else
464 limit = &intel_limits_ironlake_dac;
465
466 return limit;
467 }
468
469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 {
471 struct drm_device *dev = crtc->base.dev;
472 const intel_limit_t *limit;
473
474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475 if (intel_is_dual_link_lvds(dev))
476 limit = &intel_limits_g4x_dual_channel_lvds;
477 else
478 limit = &intel_limits_g4x_single_channel_lvds;
479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481 limit = &intel_limits_g4x_hdmi;
482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483 limit = &intel_limits_g4x_sdvo;
484 } else /* The option is for other outputs */
485 limit = &intel_limits_i9xx_sdvo;
486
487 return limit;
488 }
489
490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 {
492 struct drm_device *dev = crtc->base.dev;
493 const intel_limit_t *limit;
494
495 if (HAS_PCH_SPLIT(dev))
496 limit = intel_ironlake_limit(crtc, refclk);
497 else if (IS_G4X(dev)) {
498 limit = intel_g4x_limit(crtc);
499 } else if (IS_PINEVIEW(dev)) {
500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501 limit = &intel_limits_pineview_lvds;
502 else
503 limit = &intel_limits_pineview_sdvo;
504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
506 } else if (IS_VALLEYVIEW(dev)) {
507 limit = &intel_limits_vlv;
508 } else if (!IS_GEN2(dev)) {
509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
513 } else {
514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i8xx_lvds;
516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517 limit = &intel_limits_i8xx_dvo;
518 else
519 limit = &intel_limits_i8xx_dac;
520 }
521 return limit;
522 }
523
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk, intel_clock_t *clock)
526 {
527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533 }
534
535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 {
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538 }
539
540 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 {
542 clock->m = i9xx_dpll_compute_m(clock);
543 clock->p = clock->p1 * clock->p2;
544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
548 }
549
550 static void chv_clock(int refclk, intel_clock_t *clock)
551 {
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559 }
560
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 /**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
567 static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
570 {
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597 INTELPllInvalid("dot out of range\n");
598
599 return true;
600 }
601
602 static bool
603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->base.dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 static bool
664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 struct drm_device *dev = crtc->base.dev;
669 intel_clock_t clock;
670 int err = target;
671
672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 /*
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
677 */
678 if (intel_is_dual_link_lvds(dev))
679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
689 memset(best_clock, 0, sizeof(*best_clock));
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 pineview_clock(refclk, &clock);
702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
704 continue;
705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720 }
721
722 static bool
723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
726 {
727 struct drm_device *dev = crtc->base.dev;
728 intel_clock_t clock;
729 int max_n;
730 bool found;
731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
733 found = false;
734
735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736 if (intel_is_dual_link_lvds(dev))
737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
760 i9xx_clock(refclk, &clock);
761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(dev)) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817 }
818
819 static bool
820 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
821 int target, int refclk, intel_clock_t *match_clock,
822 intel_clock_t *best_clock)
823 {
824 struct drm_device *dev = crtc->base.dev;
825 intel_clock_t clock;
826 unsigned int bestppm = 1000000;
827 /* min update 19.2 MHz */
828 int max_n = min(limit->n.max, refclk / 19200);
829 bool found = false;
830
831 target *= 5; /* fast clock */
832
833 memset(best_clock, 0, sizeof(*best_clock));
834
835 /* based on hardware requirement, prefer smaller n to precision */
836 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
840 clock.p = clock.p1 * clock.p2;
841 /* based on hardware requirement, prefer bigger m1,m2 values */
842 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
843 unsigned int ppm;
844
845 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
846 refclk * clock.m1);
847
848 vlv_clock(refclk, &clock);
849
850 if (!intel_PLL_is_valid(dev, limit,
851 &clock))
852 continue;
853
854 if (!vlv_PLL_is_optimal(dev, target,
855 &clock,
856 best_clock,
857 bestppm, &ppm))
858 continue;
859
860 *best_clock = clock;
861 bestppm = ppm;
862 found = true;
863 }
864 }
865 }
866 }
867
868 return found;
869 }
870
871 static bool
872 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875 {
876 struct drm_device *dev = crtc->base.dev;
877 unsigned int best_error_ppm;
878 intel_clock_t clock;
879 uint64_t m2;
880 int found = false;
881
882 memset(best_clock, 0, sizeof(*best_clock));
883 best_error_ppm = 1000000;
884
885 /*
886 * Based on hardware doc, the n always set to 1, and m1 always
887 * set to 2. If requires to support 200Mhz refclk, we need to
888 * revisit this because n may not 1 anymore.
889 */
890 clock.n = 1, clock.m1 = 2;
891 target *= 5; /* fast clock */
892
893 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
894 for (clock.p2 = limit->p2.p2_fast;
895 clock.p2 >= limit->p2.p2_slow;
896 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
897 unsigned int error_ppm;
898
899 clock.p = clock.p1 * clock.p2;
900
901 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
902 clock.n) << 22, refclk * clock.m1);
903
904 if (m2 > INT_MAX/clock.m1)
905 continue;
906
907 clock.m2 = m2;
908
909 chv_clock(refclk, &clock);
910
911 if (!intel_PLL_is_valid(dev, limit, &clock))
912 continue;
913
914 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
915 best_error_ppm, &error_ppm))
916 continue;
917
918 *best_clock = clock;
919 best_error_ppm = error_ppm;
920 found = true;
921 }
922 }
923
924 return found;
925 }
926
927 bool intel_crtc_active(struct drm_crtc *crtc)
928 {
929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
930
931 /* Be paranoid as we can arrive here with only partial
932 * state retrieved from the hardware during setup.
933 *
934 * We can ditch the adjusted_mode.crtc_clock check as soon
935 * as Haswell has gained clock readout/fastboot support.
936 *
937 * We can ditch the crtc->primary->fb check as soon as we can
938 * properly reconstruct framebuffers.
939 *
940 * FIXME: The intel_crtc->active here should be switched to
941 * crtc->state->active once we have proper CRTC states wired up
942 * for atomic.
943 */
944 return intel_crtc->active && crtc->primary->state->fb &&
945 intel_crtc->config->base.adjusted_mode.crtc_clock;
946 }
947
948 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950 {
951 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
953
954 return intel_crtc->config->cpu_transcoder;
955 }
956
957 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
958 {
959 struct drm_i915_private *dev_priv = dev->dev_private;
960 u32 reg = PIPEDSL(pipe);
961 u32 line1, line2;
962 u32 line_mask;
963
964 if (IS_GEN2(dev))
965 line_mask = DSL_LINEMASK_GEN2;
966 else
967 line_mask = DSL_LINEMASK_GEN3;
968
969 line1 = I915_READ(reg) & line_mask;
970 mdelay(5);
971 line2 = I915_READ(reg) & line_mask;
972
973 return line1 == line2;
974 }
975
976 /*
977 * intel_wait_for_pipe_off - wait for pipe to turn off
978 * @crtc: crtc whose pipe to wait for
979 *
980 * After disabling a pipe, we can't wait for vblank in the usual way,
981 * spinning on the vblank interrupt status bit, since we won't actually
982 * see an interrupt when the pipe is disabled.
983 *
984 * On Gen4 and above:
985 * wait for the pipe register state bit to turn off
986 *
987 * Otherwise:
988 * wait for the display line value to settle (it usually
989 * ends up stopping at the start of the next frame).
990 *
991 */
992 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
993 {
994 struct drm_device *dev = crtc->base.dev;
995 struct drm_i915_private *dev_priv = dev->dev_private;
996 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
997 enum pipe pipe = crtc->pipe;
998
999 if (INTEL_INFO(dev)->gen >= 4) {
1000 int reg = PIPECONF(cpu_transcoder);
1001
1002 /* Wait for the Pipe State to go off */
1003 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1004 100))
1005 WARN(1, "pipe_off wait timed out\n");
1006 } else {
1007 /* Wait for the display line to settle */
1008 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1009 WARN(1, "pipe_off wait timed out\n");
1010 }
1011 }
1012
1013 /*
1014 * ibx_digital_port_connected - is the specified port connected?
1015 * @dev_priv: i915 private structure
1016 * @port: the port to test
1017 *
1018 * Returns true if @port is connected, false otherwise.
1019 */
1020 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1021 struct intel_digital_port *port)
1022 {
1023 u32 bit;
1024
1025 if (HAS_PCH_IBX(dev_priv->dev)) {
1026 switch (port->port) {
1027 case PORT_B:
1028 bit = SDE_PORTB_HOTPLUG;
1029 break;
1030 case PORT_C:
1031 bit = SDE_PORTC_HOTPLUG;
1032 break;
1033 case PORT_D:
1034 bit = SDE_PORTD_HOTPLUG;
1035 break;
1036 default:
1037 return true;
1038 }
1039 } else {
1040 switch (port->port) {
1041 case PORT_B:
1042 bit = SDE_PORTB_HOTPLUG_CPT;
1043 break;
1044 case PORT_C:
1045 bit = SDE_PORTC_HOTPLUG_CPT;
1046 break;
1047 case PORT_D:
1048 bit = SDE_PORTD_HOTPLUG_CPT;
1049 break;
1050 default:
1051 return true;
1052 }
1053 }
1054
1055 return I915_READ(SDEISR) & bit;
1056 }
1057
1058 static const char *state_string(bool enabled)
1059 {
1060 return enabled ? "on" : "off";
1061 }
1062
1063 /* Only for pre-ILK configs */
1064 void assert_pll(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 int reg;
1068 u32 val;
1069 bool cur_state;
1070
1071 reg = DPLL(pipe);
1072 val = I915_READ(reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 I915_STATE_WARN(cur_state != state,
1075 "PLL state assertion failure (expected %s, current %s)\n",
1076 state_string(state), state_string(cur_state));
1077 }
1078
1079 /* XXX: the dsi pll is shared between MIPI DSI ports */
1080 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1081 {
1082 u32 val;
1083 bool cur_state;
1084
1085 mutex_lock(&dev_priv->dpio_lock);
1086 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1087 mutex_unlock(&dev_priv->dpio_lock);
1088
1089 cur_state = val & DSI_PLL_VCO_EN;
1090 I915_STATE_WARN(cur_state != state,
1091 "DSI PLL state assertion failure (expected %s, current %s)\n",
1092 state_string(state), state_string(cur_state));
1093 }
1094 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1095 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1096
1097 struct intel_shared_dpll *
1098 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1099 {
1100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1101
1102 if (crtc->config->shared_dpll < 0)
1103 return NULL;
1104
1105 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1106 }
1107
1108 /* For ILK+ */
1109 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1110 struct intel_shared_dpll *pll,
1111 bool state)
1112 {
1113 bool cur_state;
1114 struct intel_dpll_hw_state hw_state;
1115
1116 if (WARN (!pll,
1117 "asserting DPLL %s with no DPLL\n", state_string(state)))
1118 return;
1119
1120 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1121 I915_STATE_WARN(cur_state != state,
1122 "%s assertion failure (expected %s, current %s)\n",
1123 pll->name, state_string(state), state_string(cur_state));
1124 }
1125
1126 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state)
1128 {
1129 int reg;
1130 u32 val;
1131 bool cur_state;
1132 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133 pipe);
1134
1135 if (HAS_DDI(dev_priv->dev)) {
1136 /* DDI does not have a specific FDI_TX register */
1137 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1138 val = I915_READ(reg);
1139 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1140 } else {
1141 reg = FDI_TX_CTL(pipe);
1142 val = I915_READ(reg);
1143 cur_state = !!(val & FDI_TX_ENABLE);
1144 }
1145 I915_STATE_WARN(cur_state != state,
1146 "FDI TX state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1148 }
1149 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1150 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1151
1152 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1153 enum pipe pipe, bool state)
1154 {
1155 int reg;
1156 u32 val;
1157 bool cur_state;
1158
1159 reg = FDI_RX_CTL(pipe);
1160 val = I915_READ(reg);
1161 cur_state = !!(val & FDI_RX_ENABLE);
1162 I915_STATE_WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171 {
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1177 return;
1178
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (HAS_DDI(dev_priv->dev))
1181 return;
1182
1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 int reg;
1192 u32 val;
1193 bool cur_state;
1194
1195 reg = FDI_RX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1198 I915_STATE_WARN(cur_state != state,
1199 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1200 state_string(state), state_string(cur_state));
1201 }
1202
1203 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205 {
1206 struct drm_device *dev = dev_priv->dev;
1207 int pp_reg;
1208 u32 val;
1209 enum pipe panel_pipe = PIPE_A;
1210 bool locked = true;
1211
1212 if (WARN_ON(HAS_DDI(dev)))
1213 return;
1214
1215 if (HAS_PCH_SPLIT(dev)) {
1216 u32 port_sel;
1217
1218 pp_reg = PCH_PP_CONTROL;
1219 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1220
1221 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1222 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1224 /* XXX: else fix for eDP */
1225 } else if (IS_VALLEYVIEW(dev)) {
1226 /* presumably write lock depends on pipe, not port select */
1227 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1228 panel_pipe = pipe;
1229 } else {
1230 pp_reg = PP_CONTROL;
1231 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1232 panel_pipe = PIPE_B;
1233 }
1234
1235 val = I915_READ(pp_reg);
1236 if (!(val & PANEL_POWER_ON) ||
1237 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1238 locked = false;
1239
1240 I915_STATE_WARN(panel_pipe == pipe && locked,
1241 "panel assertion failure, pipe %c regs locked\n",
1242 pipe_name(pipe));
1243 }
1244
1245 static void assert_cursor(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1247 {
1248 struct drm_device *dev = dev_priv->dev;
1249 bool cur_state;
1250
1251 if (IS_845G(dev) || IS_I865G(dev))
1252 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1253 else
1254 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1255
1256 I915_STATE_WARN(cur_state != state,
1257 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1258 pipe_name(pipe), state_string(state), state_string(cur_state));
1259 }
1260 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1261 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1262
1263 void assert_pipe(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, bool state)
1265 {
1266 int reg;
1267 u32 val;
1268 bool cur_state;
1269 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1270 pipe);
1271
1272 /* if we need the pipe quirk it must be always on */
1273 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1274 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1275 state = true;
1276
1277 if (!intel_display_power_is_enabled(dev_priv,
1278 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1279 cur_state = false;
1280 } else {
1281 reg = PIPECONF(cpu_transcoder);
1282 val = I915_READ(reg);
1283 cur_state = !!(val & PIPECONF_ENABLE);
1284 }
1285
1286 I915_STATE_WARN(cur_state != state,
1287 "pipe %c assertion failure (expected %s, current %s)\n",
1288 pipe_name(pipe), state_string(state), state_string(cur_state));
1289 }
1290
1291 static void assert_plane(struct drm_i915_private *dev_priv,
1292 enum plane plane, bool state)
1293 {
1294 int reg;
1295 u32 val;
1296 bool cur_state;
1297
1298 reg = DSPCNTR(plane);
1299 val = I915_READ(reg);
1300 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1301 I915_STATE_WARN(cur_state != state,
1302 "plane %c assertion failure (expected %s, current %s)\n",
1303 plane_name(plane), state_string(state), state_string(cur_state));
1304 }
1305
1306 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1307 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1308
1309 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311 {
1312 struct drm_device *dev = dev_priv->dev;
1313 int reg, i;
1314 u32 val;
1315 int cur_pipe;
1316
1317 /* Primary planes are fixed to pipes on gen4+ */
1318 if (INTEL_INFO(dev)->gen >= 4) {
1319 reg = DSPCNTR(pipe);
1320 val = I915_READ(reg);
1321 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1322 "plane %c assertion failure, should be disabled but not\n",
1323 plane_name(pipe));
1324 return;
1325 }
1326
1327 /* Need to check both planes against the pipe */
1328 for_each_pipe(dev_priv, i) {
1329 reg = DSPCNTR(i);
1330 val = I915_READ(reg);
1331 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1332 DISPPLANE_SEL_PIPE_SHIFT;
1333 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1334 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(i), pipe_name(pipe));
1336 }
1337 }
1338
1339 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341 {
1342 struct drm_device *dev = dev_priv->dev;
1343 int reg, sprite;
1344 u32 val;
1345
1346 if (INTEL_INFO(dev)->gen >= 9) {
1347 for_each_sprite(dev_priv, pipe, sprite) {
1348 val = I915_READ(PLANE_CTL(pipe, sprite));
1349 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1350 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1351 sprite, pipe_name(pipe));
1352 }
1353 } else if (IS_VALLEYVIEW(dev)) {
1354 for_each_sprite(dev_priv, pipe, sprite) {
1355 reg = SPCNTR(pipe, sprite);
1356 val = I915_READ(reg);
1357 I915_STATE_WARN(val & SP_ENABLE,
1358 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1359 sprite_name(pipe, sprite), pipe_name(pipe));
1360 }
1361 } else if (INTEL_INFO(dev)->gen >= 7) {
1362 reg = SPRCTL(pipe);
1363 val = I915_READ(reg);
1364 I915_STATE_WARN(val & SPRITE_ENABLE,
1365 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1366 plane_name(pipe), pipe_name(pipe));
1367 } else if (INTEL_INFO(dev)->gen >= 5) {
1368 reg = DVSCNTR(pipe);
1369 val = I915_READ(reg);
1370 I915_STATE_WARN(val & DVS_ENABLE,
1371 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1372 plane_name(pipe), pipe_name(pipe));
1373 }
1374 }
1375
1376 static void assert_vblank_disabled(struct drm_crtc *crtc)
1377 {
1378 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1379 drm_crtc_vblank_put(crtc);
1380 }
1381
1382 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1383 {
1384 u32 val;
1385 bool enabled;
1386
1387 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1388
1389 val = I915_READ(PCH_DREF_CONTROL);
1390 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1391 DREF_SUPERSPREAD_SOURCE_MASK));
1392 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1393 }
1394
1395 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397 {
1398 int reg;
1399 u32 val;
1400 bool enabled;
1401
1402 reg = PCH_TRANSCONF(pipe);
1403 val = I915_READ(reg);
1404 enabled = !!(val & TRANS_ENABLE);
1405 I915_STATE_WARN(enabled,
1406 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407 pipe_name(pipe));
1408 }
1409
1410 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 port_sel, u32 val)
1412 {
1413 if ((val & DP_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1418 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1419 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420 return false;
1421 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1422 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423 return false;
1424 } else {
1425 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426 return false;
1427 }
1428 return true;
1429 }
1430
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1433 {
1434 if ((val & SDVO_ENABLE) == 0)
1435 return false;
1436
1437 if (HAS_PCH_CPT(dev_priv->dev)) {
1438 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439 return false;
1440 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1441 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442 return false;
1443 } else {
1444 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445 return false;
1446 }
1447 return true;
1448 }
1449
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, u32 val)
1452 {
1453 if ((val & LVDS_PORT_EN) == 0)
1454 return false;
1455
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461 return false;
1462 }
1463 return true;
1464 }
1465
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 val)
1468 {
1469 if ((val & ADPA_DAC_ENABLE) == 0)
1470 return false;
1471 if (HAS_PCH_CPT(dev_priv->dev)) {
1472 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473 return false;
1474 } else {
1475 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476 return false;
1477 }
1478 return true;
1479 }
1480
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, int reg, u32 port_sel)
1483 {
1484 u32 val = I915_READ(reg);
1485 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1486 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1487 reg, pipe_name(pipe));
1488
1489 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1490 && (val & DP_PIPEB_SELECT),
1491 "IBX PCH dp port still using transcoder B\n");
1492 }
1493
1494 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, int reg)
1496 {
1497 u32 val = I915_READ(reg);
1498 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1499 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1500 reg, pipe_name(pipe));
1501
1502 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1503 && (val & SDVO_PIPE_B_SELECT),
1504 "IBX PCH hdmi port still using transcoder B\n");
1505 }
1506
1507 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508 enum pipe pipe)
1509 {
1510 int reg;
1511 u32 val;
1512
1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517 reg = PCH_ADPA;
1518 val = I915_READ(reg);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1521 pipe_name(pipe));
1522
1523 reg = PCH_LVDS;
1524 val = I915_READ(reg);
1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1527 pipe_name(pipe));
1528
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1532 }
1533
1534 static void intel_init_dpio(struct drm_device *dev)
1535 {
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 if (!IS_VALLEYVIEW(dev))
1539 return;
1540
1541 /*
1542 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1543 * CHV x1 PHY (DP/HDMI D)
1544 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1545 */
1546 if (IS_CHERRYVIEW(dev)) {
1547 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1548 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1549 } else {
1550 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1551 }
1552 }
1553
1554 static void vlv_enable_pll(struct intel_crtc *crtc,
1555 const struct intel_crtc_state *pipe_config)
1556 {
1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int reg = DPLL(crtc->pipe);
1560 u32 dpll = pipe_config->dpll_hw_state.dpll;
1561
1562 assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564 /* No really, not for ILK+ */
1565 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1566
1567 /* PLL is protected by panel, make sure we can write it */
1568 if (IS_MOBILE(dev_priv->dev))
1569 assert_panel_unlocked(dev_priv, crtc->pipe);
1570
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150);
1574
1575 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1577
1578 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1579 POSTING_READ(DPLL_MD(crtc->pipe));
1580
1581 /* We do this three times for luck */
1582 I915_WRITE(reg, dpll);
1583 POSTING_READ(reg);
1584 udelay(150); /* wait for warmup */
1585 I915_WRITE(reg, dpll);
1586 POSTING_READ(reg);
1587 udelay(150); /* wait for warmup */
1588 I915_WRITE(reg, dpll);
1589 POSTING_READ(reg);
1590 udelay(150); /* wait for warmup */
1591 }
1592
1593 static void chv_enable_pll(struct intel_crtc *crtc,
1594 const struct intel_crtc_state *pipe_config)
1595 {
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 int pipe = crtc->pipe;
1599 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1600 u32 tmp;
1601
1602 assert_pipe_disabled(dev_priv, crtc->pipe);
1603
1604 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1605
1606 mutex_lock(&dev_priv->dpio_lock);
1607
1608 /* Enable back the 10bit clock to display controller */
1609 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 tmp |= DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1612
1613 /*
1614 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1615 */
1616 udelay(1);
1617
1618 /* Enable PLL */
1619 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1620
1621 /* Check PLL is locked */
1622 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1623 DRM_ERROR("PLL %d failed to lock\n", pipe);
1624
1625 /* not sure when this should be written */
1626 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1627 POSTING_READ(DPLL_MD(pipe));
1628
1629 mutex_unlock(&dev_priv->dpio_lock);
1630 }
1631
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1633 {
1634 struct intel_crtc *crtc;
1635 int count = 0;
1636
1637 for_each_intel_crtc(dev, crtc)
1638 count += crtc->active &&
1639 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641 return count;
1642 }
1643
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1645 {
1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 int reg = DPLL(crtc->pipe);
1649 u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651 assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653 /* No really, not for ILK+ */
1654 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1655
1656 /* PLL is protected by panel, make sure we can write it */
1657 if (IS_MOBILE(dev) && !IS_I830(dev))
1658 assert_panel_unlocked(dev_priv, crtc->pipe);
1659
1660 /* Enable DVO 2x clock on both PLLs if necessary */
1661 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1662 /*
1663 * It appears to be important that we don't enable this
1664 * for the current pipe before otherwise configuring the
1665 * PLL. No idea how this should be handled if multiple
1666 * DVO outputs are enabled simultaneosly.
1667 */
1668 dpll |= DPLL_DVO_2X_MODE;
1669 I915_WRITE(DPLL(!crtc->pipe),
1670 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1671 }
1672
1673 /* Wait for the clocks to stabilize. */
1674 POSTING_READ(reg);
1675 udelay(150);
1676
1677 if (INTEL_INFO(dev)->gen >= 4) {
1678 I915_WRITE(DPLL_MD(crtc->pipe),
1679 crtc->config->dpll_hw_state.dpll_md);
1680 } else {
1681 /* The pixel multiplier can only be updated once the
1682 * DPLL is enabled and the clocks are stable.
1683 *
1684 * So write it again.
1685 */
1686 I915_WRITE(reg, dpll);
1687 }
1688
1689 /* We do this three times for luck */
1690 I915_WRITE(reg, dpll);
1691 POSTING_READ(reg);
1692 udelay(150); /* wait for warmup */
1693 I915_WRITE(reg, dpll);
1694 POSTING_READ(reg);
1695 udelay(150); /* wait for warmup */
1696 I915_WRITE(reg, dpll);
1697 POSTING_READ(reg);
1698 udelay(150); /* wait for warmup */
1699 }
1700
1701 /**
1702 * i9xx_disable_pll - disable a PLL
1703 * @dev_priv: i915 private structure
1704 * @pipe: pipe PLL to disable
1705 *
1706 * Disable the PLL for @pipe, making sure the pipe is off first.
1707 *
1708 * Note! This is for pre-ILK only.
1709 */
1710 static void i9xx_disable_pll(struct intel_crtc *crtc)
1711 {
1712 struct drm_device *dev = crtc->base.dev;
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 enum pipe pipe = crtc->pipe;
1715
1716 /* Disable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) &&
1718 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1719 intel_num_dvo_pipes(dev) == 1) {
1720 I915_WRITE(DPLL(PIPE_B),
1721 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1722 I915_WRITE(DPLL(PIPE_A),
1723 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1724 }
1725
1726 /* Don't disable pipe or pipe PLLs if needed */
1727 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1728 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1729 return;
1730
1731 /* Make sure the pipe isn't still relying on us */
1732 assert_pipe_disabled(dev_priv, pipe);
1733
1734 I915_WRITE(DPLL(pipe), 0);
1735 POSTING_READ(DPLL(pipe));
1736 }
1737
1738 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1739 {
1740 u32 val = 0;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
1745 /*
1746 * Leave integrated clock source and reference clock enabled for pipe B.
1747 * The latter is needed for VGA hotplug / manual detection.
1748 */
1749 if (pipe == PIPE_B)
1750 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
1753
1754 }
1755
1756 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757 {
1758 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1759 u32 val;
1760
1761 /* Make sure the pipe isn't still relying on us */
1762 assert_pipe_disabled(dev_priv, pipe);
1763
1764 /* Set PLL en = 0 */
1765 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1766 if (pipe != PIPE_A)
1767 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1768 I915_WRITE(DPLL(pipe), val);
1769 POSTING_READ(DPLL(pipe));
1770
1771 mutex_lock(&dev_priv->dpio_lock);
1772
1773 /* Disable 10bit clock to display controller */
1774 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1775 val &= ~DPIO_DCLKP_EN;
1776 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1777
1778 /* disable left/right clock distribution */
1779 if (pipe != PIPE_B) {
1780 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1781 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1782 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1783 } else {
1784 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1785 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1786 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1787 }
1788
1789 mutex_unlock(&dev_priv->dpio_lock);
1790 }
1791
1792 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1793 struct intel_digital_port *dport)
1794 {
1795 u32 port_mask;
1796 int dpll_reg;
1797
1798 switch (dport->port) {
1799 case PORT_B:
1800 port_mask = DPLL_PORTB_READY_MASK;
1801 dpll_reg = DPLL(0);
1802 break;
1803 case PORT_C:
1804 port_mask = DPLL_PORTC_READY_MASK;
1805 dpll_reg = DPLL(0);
1806 break;
1807 case PORT_D:
1808 port_mask = DPLL_PORTD_READY_MASK;
1809 dpll_reg = DPIO_PHY_STATUS;
1810 break;
1811 default:
1812 BUG();
1813 }
1814
1815 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1816 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1817 port_name(dport->port), I915_READ(dpll_reg));
1818 }
1819
1820 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1821 {
1822 struct drm_device *dev = crtc->base.dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1825
1826 if (WARN_ON(pll == NULL))
1827 return;
1828
1829 WARN_ON(!pll->config.crtc_mask);
1830 if (pll->active == 0) {
1831 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1832 WARN_ON(pll->on);
1833 assert_shared_dpll_disabled(dev_priv, pll);
1834
1835 pll->mode_set(dev_priv, pll);
1836 }
1837 }
1838
1839 /**
1840 * intel_enable_shared_dpll - enable PCH PLL
1841 * @dev_priv: i915 private structure
1842 * @pipe: pipe PLL to enable
1843 *
1844 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1845 * drives the transcoder clock.
1846 */
1847 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1848 {
1849 struct drm_device *dev = crtc->base.dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1852
1853 if (WARN_ON(pll == NULL))
1854 return;
1855
1856 if (WARN_ON(pll->config.crtc_mask == 0))
1857 return;
1858
1859 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1860 pll->name, pll->active, pll->on,
1861 crtc->base.base.id);
1862
1863 if (pll->active++) {
1864 WARN_ON(!pll->on);
1865 assert_shared_dpll_enabled(dev_priv, pll);
1866 return;
1867 }
1868 WARN_ON(pll->on);
1869
1870 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1871
1872 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1873 pll->enable(dev_priv, pll);
1874 pll->on = true;
1875 }
1876
1877 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1878 {
1879 struct drm_device *dev = crtc->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1882
1883 /* PCH only available on ILK+ */
1884 BUG_ON(INTEL_INFO(dev)->gen < 5);
1885 if (WARN_ON(pll == NULL))
1886 return;
1887
1888 if (WARN_ON(pll->config.crtc_mask == 0))
1889 return;
1890
1891 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1892 pll->name, pll->active, pll->on,
1893 crtc->base.base.id);
1894
1895 if (WARN_ON(pll->active == 0)) {
1896 assert_shared_dpll_disabled(dev_priv, pll);
1897 return;
1898 }
1899
1900 assert_shared_dpll_enabled(dev_priv, pll);
1901 WARN_ON(!pll->on);
1902 if (--pll->active)
1903 return;
1904
1905 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1906 pll->disable(dev_priv, pll);
1907 pll->on = false;
1908
1909 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1910 }
1911
1912 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1913 enum pipe pipe)
1914 {
1915 struct drm_device *dev = dev_priv->dev;
1916 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1918 uint32_t reg, val, pipeconf_val;
1919
1920 /* PCH only available on ILK+ */
1921 BUG_ON(!HAS_PCH_SPLIT(dev));
1922
1923 /* Make sure PCH DPLL is enabled */
1924 assert_shared_dpll_enabled(dev_priv,
1925 intel_crtc_to_shared_dpll(intel_crtc));
1926
1927 /* FDI must be feeding us bits for PCH ports */
1928 assert_fdi_tx_enabled(dev_priv, pipe);
1929 assert_fdi_rx_enabled(dev_priv, pipe);
1930
1931 if (HAS_PCH_CPT(dev)) {
1932 /* Workaround: Set the timing override bit before enabling the
1933 * pch transcoder. */
1934 reg = TRANS_CHICKEN2(pipe);
1935 val = I915_READ(reg);
1936 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1937 I915_WRITE(reg, val);
1938 }
1939
1940 reg = PCH_TRANSCONF(pipe);
1941 val = I915_READ(reg);
1942 pipeconf_val = I915_READ(PIPECONF(pipe));
1943
1944 if (HAS_PCH_IBX(dev_priv->dev)) {
1945 /*
1946 * make the BPC in transcoder be consistent with
1947 * that in pipeconf reg.
1948 */
1949 val &= ~PIPECONF_BPC_MASK;
1950 val |= pipeconf_val & PIPECONF_BPC_MASK;
1951 }
1952
1953 val &= ~TRANS_INTERLACE_MASK;
1954 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1955 if (HAS_PCH_IBX(dev_priv->dev) &&
1956 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1957 val |= TRANS_LEGACY_INTERLACED_ILK;
1958 else
1959 val |= TRANS_INTERLACED;
1960 else
1961 val |= TRANS_PROGRESSIVE;
1962
1963 I915_WRITE(reg, val | TRANS_ENABLE);
1964 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1965 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1966 }
1967
1968 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum transcoder cpu_transcoder)
1970 {
1971 u32 val, pipeconf_val;
1972
1973 /* PCH only available on ILK+ */
1974 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1975
1976 /* FDI must be feeding us bits for PCH ports */
1977 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1978 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1979
1980 /* Workaround: set timing override bit. */
1981 val = I915_READ(_TRANSA_CHICKEN2);
1982 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1983 I915_WRITE(_TRANSA_CHICKEN2, val);
1984
1985 val = TRANS_ENABLE;
1986 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1987
1988 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1989 PIPECONF_INTERLACED_ILK)
1990 val |= TRANS_INTERLACED;
1991 else
1992 val |= TRANS_PROGRESSIVE;
1993
1994 I915_WRITE(LPT_TRANSCONF, val);
1995 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1996 DRM_ERROR("Failed to enable PCH transcoder\n");
1997 }
1998
1999 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2000 enum pipe pipe)
2001 {
2002 struct drm_device *dev = dev_priv->dev;
2003 uint32_t reg, val;
2004
2005 /* FDI relies on the transcoder */
2006 assert_fdi_tx_disabled(dev_priv, pipe);
2007 assert_fdi_rx_disabled(dev_priv, pipe);
2008
2009 /* Ports must be off as well */
2010 assert_pch_ports_disabled(dev_priv, pipe);
2011
2012 reg = PCH_TRANSCONF(pipe);
2013 val = I915_READ(reg);
2014 val &= ~TRANS_ENABLE;
2015 I915_WRITE(reg, val);
2016 /* wait for PCH transcoder off, transcoder state */
2017 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2018 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2019
2020 if (!HAS_PCH_IBX(dev)) {
2021 /* Workaround: Clear the timing override chicken bit again. */
2022 reg = TRANS_CHICKEN2(pipe);
2023 val = I915_READ(reg);
2024 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(reg, val);
2026 }
2027 }
2028
2029 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2030 {
2031 u32 val;
2032
2033 val = I915_READ(LPT_TRANSCONF);
2034 val &= ~TRANS_ENABLE;
2035 I915_WRITE(LPT_TRANSCONF, val);
2036 /* wait for PCH transcoder off, transcoder state */
2037 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2038 DRM_ERROR("Failed to disable PCH transcoder\n");
2039
2040 /* Workaround: clear timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
2042 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044 }
2045
2046 /**
2047 * intel_enable_pipe - enable a pipe, asserting requirements
2048 * @crtc: crtc responsible for the pipe
2049 *
2050 * Enable @crtc's pipe, making sure that various hardware specific requirements
2051 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2052 */
2053 static void intel_enable_pipe(struct intel_crtc *crtc)
2054 {
2055 struct drm_device *dev = crtc->base.dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 enum pipe pipe = crtc->pipe;
2058 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059 pipe);
2060 enum pipe pch_transcoder;
2061 int reg;
2062 u32 val;
2063
2064 assert_planes_disabled(dev_priv, pipe);
2065 assert_cursor_disabled(dev_priv, pipe);
2066 assert_sprites_disabled(dev_priv, pipe);
2067
2068 if (HAS_PCH_LPT(dev_priv->dev))
2069 pch_transcoder = TRANSCODER_A;
2070 else
2071 pch_transcoder = pipe;
2072
2073 /*
2074 * A pipe without a PLL won't actually be able to drive bits from
2075 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2076 * need the check.
2077 */
2078 if (!HAS_PCH_SPLIT(dev_priv->dev))
2079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2080 assert_dsi_pll_enabled(dev_priv);
2081 else
2082 assert_pll_enabled(dev_priv, pipe);
2083 else {
2084 if (crtc->config->has_pch_encoder) {
2085 /* if driving the PCH, we need FDI enabled */
2086 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2087 assert_fdi_tx_pll_enabled(dev_priv,
2088 (enum pipe) cpu_transcoder);
2089 }
2090 /* FIXME: assert CPU port conditions for SNB+ */
2091 }
2092
2093 reg = PIPECONF(cpu_transcoder);
2094 val = I915_READ(reg);
2095 if (val & PIPECONF_ENABLE) {
2096 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2097 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2098 return;
2099 }
2100
2101 I915_WRITE(reg, val | PIPECONF_ENABLE);
2102 POSTING_READ(reg);
2103 }
2104
2105 /**
2106 * intel_disable_pipe - disable a pipe, asserting requirements
2107 * @crtc: crtc whose pipes is to be disabled
2108 *
2109 * Disable the pipe of @crtc, making sure that various hardware
2110 * specific requirements are met, if applicable, e.g. plane
2111 * disabled, panel fitter off, etc.
2112 *
2113 * Will wait until the pipe has shut down before returning.
2114 */
2115 static void intel_disable_pipe(struct intel_crtc *crtc)
2116 {
2117 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2118 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2119 enum pipe pipe = crtc->pipe;
2120 int reg;
2121 u32 val;
2122
2123 /*
2124 * Make sure planes won't keep trying to pump pixels to us,
2125 * or we might hang the display.
2126 */
2127 assert_planes_disabled(dev_priv, pipe);
2128 assert_cursor_disabled(dev_priv, pipe);
2129 assert_sprites_disabled(dev_priv, pipe);
2130
2131 reg = PIPECONF(cpu_transcoder);
2132 val = I915_READ(reg);
2133 if ((val & PIPECONF_ENABLE) == 0)
2134 return;
2135
2136 /*
2137 * Double wide has implications for planes
2138 * so best keep it disabled when not needed.
2139 */
2140 if (crtc->config->double_wide)
2141 val &= ~PIPECONF_DOUBLE_WIDE;
2142
2143 /* Don't disable pipe or pipe PLLs if needed */
2144 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2145 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2146 val &= ~PIPECONF_ENABLE;
2147
2148 I915_WRITE(reg, val);
2149 if ((val & PIPECONF_ENABLE) == 0)
2150 intel_wait_for_pipe_off(crtc);
2151 }
2152
2153 /*
2154 * Plane regs are double buffered, going from enabled->disabled needs a
2155 * trigger in order to latch. The display address reg provides this.
2156 */
2157 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2158 enum plane plane)
2159 {
2160 struct drm_device *dev = dev_priv->dev;
2161 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2162
2163 I915_WRITE(reg, I915_READ(reg));
2164 POSTING_READ(reg);
2165 }
2166
2167 /**
2168 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2169 * @plane: plane to be enabled
2170 * @crtc: crtc for the plane
2171 *
2172 * Enable @plane on @crtc, making sure that the pipe is running first.
2173 */
2174 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2175 struct drm_crtc *crtc)
2176 {
2177 struct drm_device *dev = plane->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2182 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2183
2184 if (intel_crtc->primary_enabled)
2185 return;
2186
2187 intel_crtc->primary_enabled = true;
2188
2189 dev_priv->display.update_primary_plane(crtc, plane->fb,
2190 crtc->x, crtc->y);
2191
2192 /*
2193 * BDW signals flip done immediately if the plane
2194 * is disabled, even if the plane enable is already
2195 * armed to occur at the next vblank :(
2196 */
2197 if (IS_BROADWELL(dev))
2198 intel_wait_for_vblank(dev, intel_crtc->pipe);
2199 }
2200
2201 /**
2202 * intel_disable_primary_hw_plane - disable the primary hardware plane
2203 * @plane: plane to be disabled
2204 * @crtc: crtc for the plane
2205 *
2206 * Disable @plane on @crtc, making sure that the pipe is running first.
2207 */
2208 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2209 struct drm_crtc *crtc)
2210 {
2211 struct drm_device *dev = plane->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214
2215 if (WARN_ON(!intel_crtc->active))
2216 return;
2217
2218 if (!intel_crtc->primary_enabled)
2219 return;
2220
2221 intel_crtc->primary_enabled = false;
2222
2223 dev_priv->display.update_primary_plane(crtc, plane->fb,
2224 crtc->x, crtc->y);
2225 }
2226
2227 static bool need_vtd_wa(struct drm_device *dev)
2228 {
2229 #ifdef CONFIG_INTEL_IOMMU
2230 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2231 return true;
2232 #endif
2233 return false;
2234 }
2235
2236 static unsigned int
2237 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2238 uint64_t fb_format_modifier)
2239 {
2240 unsigned int tile_height;
2241 uint32_t pixel_bytes;
2242
2243 switch (fb_format_modifier) {
2244 case DRM_FORMAT_MOD_NONE:
2245 tile_height = 1;
2246 break;
2247 case I915_FORMAT_MOD_X_TILED:
2248 tile_height = IS_GEN2(dev) ? 16 : 8;
2249 break;
2250 case I915_FORMAT_MOD_Y_TILED:
2251 tile_height = 32;
2252 break;
2253 case I915_FORMAT_MOD_Yf_TILED:
2254 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2255 switch (pixel_bytes) {
2256 default:
2257 case 1:
2258 tile_height = 64;
2259 break;
2260 case 2:
2261 case 4:
2262 tile_height = 32;
2263 break;
2264 case 8:
2265 tile_height = 16;
2266 break;
2267 case 16:
2268 WARN_ONCE(1,
2269 "128-bit pixels are not supported for display!");
2270 tile_height = 16;
2271 break;
2272 }
2273 break;
2274 default:
2275 MISSING_CASE(fb_format_modifier);
2276 tile_height = 1;
2277 break;
2278 }
2279
2280 return tile_height;
2281 }
2282
2283 unsigned int
2284 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2285 uint32_t pixel_format, uint64_t fb_format_modifier)
2286 {
2287 return ALIGN(height, intel_tile_height(dev, pixel_format,
2288 fb_format_modifier));
2289 }
2290
2291 int
2292 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2293 struct drm_framebuffer *fb,
2294 struct intel_engine_cs *pipelined)
2295 {
2296 struct drm_device *dev = fb->dev;
2297 struct drm_i915_private *dev_priv = dev->dev_private;
2298 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2299 u32 alignment;
2300 int ret;
2301
2302 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2303
2304 switch (fb->modifier[0]) {
2305 case DRM_FORMAT_MOD_NONE:
2306 if (INTEL_INFO(dev)->gen >= 9)
2307 alignment = 256 * 1024;
2308 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2309 alignment = 128 * 1024;
2310 else if (INTEL_INFO(dev)->gen >= 4)
2311 alignment = 4 * 1024;
2312 else
2313 alignment = 64 * 1024;
2314 break;
2315 case I915_FORMAT_MOD_X_TILED:
2316 if (INTEL_INFO(dev)->gen >= 9)
2317 alignment = 256 * 1024;
2318 else {
2319 /* pin() will align the object as required by fence */
2320 alignment = 0;
2321 }
2322 break;
2323 case I915_FORMAT_MOD_Y_TILED:
2324 case I915_FORMAT_MOD_Yf_TILED:
2325 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2326 "Y tiling bo slipped through, driver bug!\n"))
2327 return -EINVAL;
2328 alignment = 1 * 1024 * 1024;
2329 break;
2330 default:
2331 MISSING_CASE(fb->modifier[0]);
2332 return -EINVAL;
2333 }
2334
2335 /* Note that the w/a also requires 64 PTE of padding following the
2336 * bo. We currently fill all unused PTE with the shadow page and so
2337 * we should always have valid PTE following the scanout preventing
2338 * the VT-d warning.
2339 */
2340 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2341 alignment = 256 * 1024;
2342
2343 /*
2344 * Global gtt pte registers are special registers which actually forward
2345 * writes to a chunk of system memory. Which means that there is no risk
2346 * that the register values disappear as soon as we call
2347 * intel_runtime_pm_put(), so it is correct to wrap only the
2348 * pin/unpin/fence and not more.
2349 */
2350 intel_runtime_pm_get(dev_priv);
2351
2352 dev_priv->mm.interruptible = false;
2353 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2354 &i915_ggtt_view_normal);
2355 if (ret)
2356 goto err_interruptible;
2357
2358 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2359 * fence, whereas 965+ only requires a fence if using
2360 * framebuffer compression. For simplicity, we always install
2361 * a fence as the cost is not that onerous.
2362 */
2363 ret = i915_gem_object_get_fence(obj);
2364 if (ret)
2365 goto err_unpin;
2366
2367 i915_gem_object_pin_fence(obj);
2368
2369 dev_priv->mm.interruptible = true;
2370 intel_runtime_pm_put(dev_priv);
2371 return 0;
2372
2373 err_unpin:
2374 i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal);
2375 err_interruptible:
2376 dev_priv->mm.interruptible = true;
2377 intel_runtime_pm_put(dev_priv);
2378 return ret;
2379 }
2380
2381 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2382 {
2383 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2384
2385 i915_gem_object_unpin_fence(obj);
2386 i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal);
2387 }
2388
2389 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2390 * is assumed to be a power-of-two. */
2391 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2392 unsigned int tiling_mode,
2393 unsigned int cpp,
2394 unsigned int pitch)
2395 {
2396 if (tiling_mode != I915_TILING_NONE) {
2397 unsigned int tile_rows, tiles;
2398
2399 tile_rows = *y / 8;
2400 *y %= 8;
2401
2402 tiles = *x / (512/cpp);
2403 *x %= 512/cpp;
2404
2405 return tile_rows * pitch * 8 + tiles * 4096;
2406 } else {
2407 unsigned int offset;
2408
2409 offset = *y * pitch + *x * cpp;
2410 *y = 0;
2411 *x = (offset & 4095) / cpp;
2412 return offset & -4096;
2413 }
2414 }
2415
2416 static int i9xx_format_to_fourcc(int format)
2417 {
2418 switch (format) {
2419 case DISPPLANE_8BPP:
2420 return DRM_FORMAT_C8;
2421 case DISPPLANE_BGRX555:
2422 return DRM_FORMAT_XRGB1555;
2423 case DISPPLANE_BGRX565:
2424 return DRM_FORMAT_RGB565;
2425 default:
2426 case DISPPLANE_BGRX888:
2427 return DRM_FORMAT_XRGB8888;
2428 case DISPPLANE_RGBX888:
2429 return DRM_FORMAT_XBGR8888;
2430 case DISPPLANE_BGRX101010:
2431 return DRM_FORMAT_XRGB2101010;
2432 case DISPPLANE_RGBX101010:
2433 return DRM_FORMAT_XBGR2101010;
2434 }
2435 }
2436
2437 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2438 {
2439 switch (format) {
2440 case PLANE_CTL_FORMAT_RGB_565:
2441 return DRM_FORMAT_RGB565;
2442 default:
2443 case PLANE_CTL_FORMAT_XRGB_8888:
2444 if (rgb_order) {
2445 if (alpha)
2446 return DRM_FORMAT_ABGR8888;
2447 else
2448 return DRM_FORMAT_XBGR8888;
2449 } else {
2450 if (alpha)
2451 return DRM_FORMAT_ARGB8888;
2452 else
2453 return DRM_FORMAT_XRGB8888;
2454 }
2455 case PLANE_CTL_FORMAT_XRGB_2101010:
2456 if (rgb_order)
2457 return DRM_FORMAT_XBGR2101010;
2458 else
2459 return DRM_FORMAT_XRGB2101010;
2460 }
2461 }
2462
2463 static bool
2464 intel_alloc_plane_obj(struct intel_crtc *crtc,
2465 struct intel_initial_plane_config *plane_config)
2466 {
2467 struct drm_device *dev = crtc->base.dev;
2468 struct drm_i915_gem_object *obj = NULL;
2469 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2470 struct drm_framebuffer *fb = &plane_config->fb->base;
2471 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2472 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2473 PAGE_SIZE);
2474
2475 size_aligned -= base_aligned;
2476
2477 if (plane_config->size == 0)
2478 return false;
2479
2480 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2481 base_aligned,
2482 base_aligned,
2483 size_aligned);
2484 if (!obj)
2485 return false;
2486
2487 obj->tiling_mode = plane_config->tiling;
2488 if (obj->tiling_mode == I915_TILING_X)
2489 obj->stride = fb->pitches[0];
2490
2491 mode_cmd.pixel_format = fb->pixel_format;
2492 mode_cmd.width = fb->width;
2493 mode_cmd.height = fb->height;
2494 mode_cmd.pitches[0] = fb->pitches[0];
2495 mode_cmd.modifier[0] = fb->modifier[0];
2496 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2497
2498 mutex_lock(&dev->struct_mutex);
2499
2500 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2501 &mode_cmd, obj)) {
2502 DRM_DEBUG_KMS("intel fb init failed\n");
2503 goto out_unref_obj;
2504 }
2505
2506 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2507 mutex_unlock(&dev->struct_mutex);
2508
2509 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2510 return true;
2511
2512 out_unref_obj:
2513 drm_gem_object_unreference(&obj->base);
2514 mutex_unlock(&dev->struct_mutex);
2515 return false;
2516 }
2517
2518 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2519 static void
2520 update_state_fb(struct drm_plane *plane)
2521 {
2522 if (plane->fb == plane->state->fb)
2523 return;
2524
2525 if (plane->state->fb)
2526 drm_framebuffer_unreference(plane->state->fb);
2527 plane->state->fb = plane->fb;
2528 if (plane->state->fb)
2529 drm_framebuffer_reference(plane->state->fb);
2530 }
2531
2532 static void
2533 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2534 struct intel_initial_plane_config *plane_config)
2535 {
2536 struct drm_device *dev = intel_crtc->base.dev;
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2538 struct drm_crtc *c;
2539 struct intel_crtc *i;
2540 struct drm_i915_gem_object *obj;
2541
2542 if (!plane_config->fb)
2543 return;
2544
2545 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2546 struct drm_plane *primary = intel_crtc->base.primary;
2547
2548 primary->fb = &plane_config->fb->base;
2549 primary->state->crtc = &intel_crtc->base;
2550 update_state_fb(primary);
2551
2552 return;
2553 }
2554
2555 kfree(plane_config->fb);
2556
2557 /*
2558 * Failed to alloc the obj, check to see if we should share
2559 * an fb with another CRTC instead
2560 */
2561 for_each_crtc(dev, c) {
2562 i = to_intel_crtc(c);
2563
2564 if (c == &intel_crtc->base)
2565 continue;
2566
2567 if (!i->active)
2568 continue;
2569
2570 obj = intel_fb_obj(c->primary->fb);
2571 if (obj == NULL)
2572 continue;
2573
2574 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2575 struct drm_plane *primary = intel_crtc->base.primary;
2576
2577 if (obj->tiling_mode != I915_TILING_NONE)
2578 dev_priv->preserve_bios_swizzle = true;
2579
2580 drm_framebuffer_reference(c->primary->fb);
2581 primary->fb = c->primary->fb;
2582 primary->state->crtc = &intel_crtc->base;
2583 update_state_fb(intel_crtc->base.primary);
2584 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2585 break;
2586 }
2587 }
2588 }
2589
2590 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2591 struct drm_framebuffer *fb,
2592 int x, int y)
2593 {
2594 struct drm_device *dev = crtc->dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 struct drm_i915_gem_object *obj;
2598 int plane = intel_crtc->plane;
2599 unsigned long linear_offset;
2600 u32 dspcntr;
2601 u32 reg = DSPCNTR(plane);
2602 int pixel_size;
2603
2604 if (!intel_crtc->primary_enabled) {
2605 I915_WRITE(reg, 0);
2606 if (INTEL_INFO(dev)->gen >= 4)
2607 I915_WRITE(DSPSURF(plane), 0);
2608 else
2609 I915_WRITE(DSPADDR(plane), 0);
2610 POSTING_READ(reg);
2611 return;
2612 }
2613
2614 obj = intel_fb_obj(fb);
2615 if (WARN_ON(obj == NULL))
2616 return;
2617
2618 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2619
2620 dspcntr = DISPPLANE_GAMMA_ENABLE;
2621
2622 dspcntr |= DISPLAY_PLANE_ENABLE;
2623
2624 if (INTEL_INFO(dev)->gen < 4) {
2625 if (intel_crtc->pipe == PIPE_B)
2626 dspcntr |= DISPPLANE_SEL_PIPE_B;
2627
2628 /* pipesrc and dspsize control the size that is scaled from,
2629 * which should always be the user's requested size.
2630 */
2631 I915_WRITE(DSPSIZE(plane),
2632 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2633 (intel_crtc->config->pipe_src_w - 1));
2634 I915_WRITE(DSPPOS(plane), 0);
2635 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2636 I915_WRITE(PRIMSIZE(plane),
2637 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2638 (intel_crtc->config->pipe_src_w - 1));
2639 I915_WRITE(PRIMPOS(plane), 0);
2640 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2641 }
2642
2643 switch (fb->pixel_format) {
2644 case DRM_FORMAT_C8:
2645 dspcntr |= DISPPLANE_8BPP;
2646 break;
2647 case DRM_FORMAT_XRGB1555:
2648 case DRM_FORMAT_ARGB1555:
2649 dspcntr |= DISPPLANE_BGRX555;
2650 break;
2651 case DRM_FORMAT_RGB565:
2652 dspcntr |= DISPPLANE_BGRX565;
2653 break;
2654 case DRM_FORMAT_XRGB8888:
2655 case DRM_FORMAT_ARGB8888:
2656 dspcntr |= DISPPLANE_BGRX888;
2657 break;
2658 case DRM_FORMAT_XBGR8888:
2659 case DRM_FORMAT_ABGR8888:
2660 dspcntr |= DISPPLANE_RGBX888;
2661 break;
2662 case DRM_FORMAT_XRGB2101010:
2663 case DRM_FORMAT_ARGB2101010:
2664 dspcntr |= DISPPLANE_BGRX101010;
2665 break;
2666 case DRM_FORMAT_XBGR2101010:
2667 case DRM_FORMAT_ABGR2101010:
2668 dspcntr |= DISPPLANE_RGBX101010;
2669 break;
2670 default:
2671 BUG();
2672 }
2673
2674 if (INTEL_INFO(dev)->gen >= 4 &&
2675 obj->tiling_mode != I915_TILING_NONE)
2676 dspcntr |= DISPPLANE_TILED;
2677
2678 if (IS_G4X(dev))
2679 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2680
2681 linear_offset = y * fb->pitches[0] + x * pixel_size;
2682
2683 if (INTEL_INFO(dev)->gen >= 4) {
2684 intel_crtc->dspaddr_offset =
2685 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2686 pixel_size,
2687 fb->pitches[0]);
2688 linear_offset -= intel_crtc->dspaddr_offset;
2689 } else {
2690 intel_crtc->dspaddr_offset = linear_offset;
2691 }
2692
2693 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2694 dspcntr |= DISPPLANE_ROTATE_180;
2695
2696 x += (intel_crtc->config->pipe_src_w - 1);
2697 y += (intel_crtc->config->pipe_src_h - 1);
2698
2699 /* Finding the last pixel of the last line of the display
2700 data and adding to linear_offset*/
2701 linear_offset +=
2702 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2703 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2704 }
2705
2706 I915_WRITE(reg, dspcntr);
2707
2708 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2709 if (INTEL_INFO(dev)->gen >= 4) {
2710 I915_WRITE(DSPSURF(plane),
2711 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2712 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2713 I915_WRITE(DSPLINOFF(plane), linear_offset);
2714 } else
2715 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2716 POSTING_READ(reg);
2717 }
2718
2719 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2720 struct drm_framebuffer *fb,
2721 int x, int y)
2722 {
2723 struct drm_device *dev = crtc->dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726 struct drm_i915_gem_object *obj;
2727 int plane = intel_crtc->plane;
2728 unsigned long linear_offset;
2729 u32 dspcntr;
2730 u32 reg = DSPCNTR(plane);
2731 int pixel_size;
2732
2733 if (!intel_crtc->primary_enabled) {
2734 I915_WRITE(reg, 0);
2735 I915_WRITE(DSPSURF(plane), 0);
2736 POSTING_READ(reg);
2737 return;
2738 }
2739
2740 obj = intel_fb_obj(fb);
2741 if (WARN_ON(obj == NULL))
2742 return;
2743
2744 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2745
2746 dspcntr = DISPPLANE_GAMMA_ENABLE;
2747
2748 dspcntr |= DISPLAY_PLANE_ENABLE;
2749
2750 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2751 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2752
2753 switch (fb->pixel_format) {
2754 case DRM_FORMAT_C8:
2755 dspcntr |= DISPPLANE_8BPP;
2756 break;
2757 case DRM_FORMAT_RGB565:
2758 dspcntr |= DISPPLANE_BGRX565;
2759 break;
2760 case DRM_FORMAT_XRGB8888:
2761 case DRM_FORMAT_ARGB8888:
2762 dspcntr |= DISPPLANE_BGRX888;
2763 break;
2764 case DRM_FORMAT_XBGR8888:
2765 case DRM_FORMAT_ABGR8888:
2766 dspcntr |= DISPPLANE_RGBX888;
2767 break;
2768 case DRM_FORMAT_XRGB2101010:
2769 case DRM_FORMAT_ARGB2101010:
2770 dspcntr |= DISPPLANE_BGRX101010;
2771 break;
2772 case DRM_FORMAT_XBGR2101010:
2773 case DRM_FORMAT_ABGR2101010:
2774 dspcntr |= DISPPLANE_RGBX101010;
2775 break;
2776 default:
2777 BUG();
2778 }
2779
2780 if (obj->tiling_mode != I915_TILING_NONE)
2781 dspcntr |= DISPPLANE_TILED;
2782
2783 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2784 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2785
2786 linear_offset = y * fb->pitches[0] + x * pixel_size;
2787 intel_crtc->dspaddr_offset =
2788 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2789 pixel_size,
2790 fb->pitches[0]);
2791 linear_offset -= intel_crtc->dspaddr_offset;
2792 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2793 dspcntr |= DISPPLANE_ROTATE_180;
2794
2795 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2796 x += (intel_crtc->config->pipe_src_w - 1);
2797 y += (intel_crtc->config->pipe_src_h - 1);
2798
2799 /* Finding the last pixel of the last line of the display
2800 data and adding to linear_offset*/
2801 linear_offset +=
2802 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2803 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2804 }
2805 }
2806
2807 I915_WRITE(reg, dspcntr);
2808
2809 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2810 I915_WRITE(DSPSURF(plane),
2811 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2813 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2814 } else {
2815 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2816 I915_WRITE(DSPLINOFF(plane), linear_offset);
2817 }
2818 POSTING_READ(reg);
2819 }
2820
2821 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2822 uint32_t pixel_format)
2823 {
2824 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2825
2826 /*
2827 * The stride is either expressed as a multiple of 64 bytes
2828 * chunks for linear buffers or in number of tiles for tiled
2829 * buffers.
2830 */
2831 switch (fb_modifier) {
2832 case DRM_FORMAT_MOD_NONE:
2833 return 64;
2834 case I915_FORMAT_MOD_X_TILED:
2835 if (INTEL_INFO(dev)->gen == 2)
2836 return 128;
2837 return 512;
2838 case I915_FORMAT_MOD_Y_TILED:
2839 /* No need to check for old gens and Y tiling since this is
2840 * about the display engine and those will be blocked before
2841 * we get here.
2842 */
2843 return 128;
2844 case I915_FORMAT_MOD_Yf_TILED:
2845 if (bits_per_pixel == 8)
2846 return 64;
2847 else
2848 return 128;
2849 default:
2850 MISSING_CASE(fb_modifier);
2851 return 64;
2852 }
2853 }
2854
2855 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2856 struct drm_framebuffer *fb,
2857 int x, int y)
2858 {
2859 struct drm_device *dev = crtc->dev;
2860 struct drm_i915_private *dev_priv = dev->dev_private;
2861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2862 struct drm_i915_gem_object *obj;
2863 int pipe = intel_crtc->pipe;
2864 u32 plane_ctl, stride_div;
2865
2866 if (!intel_crtc->primary_enabled) {
2867 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2868 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2869 POSTING_READ(PLANE_CTL(pipe, 0));
2870 return;
2871 }
2872
2873 plane_ctl = PLANE_CTL_ENABLE |
2874 PLANE_CTL_PIPE_GAMMA_ENABLE |
2875 PLANE_CTL_PIPE_CSC_ENABLE;
2876
2877 switch (fb->pixel_format) {
2878 case DRM_FORMAT_RGB565:
2879 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2880 break;
2881 case DRM_FORMAT_XRGB8888:
2882 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2883 break;
2884 case DRM_FORMAT_ARGB8888:
2885 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2886 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2887 break;
2888 case DRM_FORMAT_XBGR8888:
2889 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2890 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2891 break;
2892 case DRM_FORMAT_ABGR8888:
2893 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2894 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2895 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2896 break;
2897 case DRM_FORMAT_XRGB2101010:
2898 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2899 break;
2900 case DRM_FORMAT_XBGR2101010:
2901 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2902 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2903 break;
2904 default:
2905 BUG();
2906 }
2907
2908 switch (fb->modifier[0]) {
2909 case DRM_FORMAT_MOD_NONE:
2910 break;
2911 case I915_FORMAT_MOD_X_TILED:
2912 plane_ctl |= PLANE_CTL_TILED_X;
2913 break;
2914 case I915_FORMAT_MOD_Y_TILED:
2915 plane_ctl |= PLANE_CTL_TILED_Y;
2916 break;
2917 case I915_FORMAT_MOD_Yf_TILED:
2918 plane_ctl |= PLANE_CTL_TILED_YF;
2919 break;
2920 default:
2921 MISSING_CASE(fb->modifier[0]);
2922 }
2923
2924 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2925 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2926 plane_ctl |= PLANE_CTL_ROTATE_180;
2927
2928 obj = intel_fb_obj(fb);
2929 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2930 fb->pixel_format);
2931
2932 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2933
2934 I915_WRITE(PLANE_POS(pipe, 0), 0);
2935 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2936 I915_WRITE(PLANE_SIZE(pipe, 0),
2937 (intel_crtc->config->pipe_src_h - 1) << 16 |
2938 (intel_crtc->config->pipe_src_w - 1));
2939 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2940 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2941
2942 POSTING_READ(PLANE_SURF(pipe, 0));
2943 }
2944
2945 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2946 static int
2947 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2948 int x, int y, enum mode_set_atomic state)
2949 {
2950 struct drm_device *dev = crtc->dev;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952
2953 if (dev_priv->display.disable_fbc)
2954 dev_priv->display.disable_fbc(dev);
2955
2956 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2957
2958 return 0;
2959 }
2960
2961 static void intel_complete_page_flips(struct drm_device *dev)
2962 {
2963 struct drm_crtc *crtc;
2964
2965 for_each_crtc(dev, crtc) {
2966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2967 enum plane plane = intel_crtc->plane;
2968
2969 intel_prepare_page_flip(dev, plane);
2970 intel_finish_page_flip_plane(dev, plane);
2971 }
2972 }
2973
2974 static void intel_update_primary_planes(struct drm_device *dev)
2975 {
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct drm_crtc *crtc;
2978
2979 for_each_crtc(dev, crtc) {
2980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2981
2982 drm_modeset_lock(&crtc->mutex, NULL);
2983 /*
2984 * FIXME: Once we have proper support for primary planes (and
2985 * disabling them without disabling the entire crtc) allow again
2986 * a NULL crtc->primary->fb.
2987 */
2988 if (intel_crtc->active && crtc->primary->fb)
2989 dev_priv->display.update_primary_plane(crtc,
2990 crtc->primary->fb,
2991 crtc->x,
2992 crtc->y);
2993 drm_modeset_unlock(&crtc->mutex);
2994 }
2995 }
2996
2997 void intel_prepare_reset(struct drm_device *dev)
2998 {
2999 struct drm_i915_private *dev_priv = to_i915(dev);
3000 struct intel_crtc *crtc;
3001
3002 /* no reset support for gen2 */
3003 if (IS_GEN2(dev))
3004 return;
3005
3006 /* reset doesn't touch the display */
3007 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3008 return;
3009
3010 drm_modeset_lock_all(dev);
3011
3012 /*
3013 * Disabling the crtcs gracefully seems nicer. Also the
3014 * g33 docs say we should at least disable all the planes.
3015 */
3016 for_each_intel_crtc(dev, crtc) {
3017 if (crtc->active)
3018 dev_priv->display.crtc_disable(&crtc->base);
3019 }
3020 }
3021
3022 void intel_finish_reset(struct drm_device *dev)
3023 {
3024 struct drm_i915_private *dev_priv = to_i915(dev);
3025
3026 /*
3027 * Flips in the rings will be nuked by the reset,
3028 * so complete all pending flips so that user space
3029 * will get its events and not get stuck.
3030 */
3031 intel_complete_page_flips(dev);
3032
3033 /* no reset support for gen2 */
3034 if (IS_GEN2(dev))
3035 return;
3036
3037 /* reset doesn't touch the display */
3038 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3039 /*
3040 * Flips in the rings have been nuked by the reset,
3041 * so update the base address of all primary
3042 * planes to the the last fb to make sure we're
3043 * showing the correct fb after a reset.
3044 */
3045 intel_update_primary_planes(dev);
3046 return;
3047 }
3048
3049 /*
3050 * The display has been reset as well,
3051 * so need a full re-initialization.
3052 */
3053 intel_runtime_pm_disable_interrupts(dev_priv);
3054 intel_runtime_pm_enable_interrupts(dev_priv);
3055
3056 intel_modeset_init_hw(dev);
3057
3058 spin_lock_irq(&dev_priv->irq_lock);
3059 if (dev_priv->display.hpd_irq_setup)
3060 dev_priv->display.hpd_irq_setup(dev);
3061 spin_unlock_irq(&dev_priv->irq_lock);
3062
3063 intel_modeset_setup_hw_state(dev, true);
3064
3065 intel_hpd_init(dev_priv);
3066
3067 drm_modeset_unlock_all(dev);
3068 }
3069
3070 static int
3071 intel_finish_fb(struct drm_framebuffer *old_fb)
3072 {
3073 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3074 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3075 bool was_interruptible = dev_priv->mm.interruptible;
3076 int ret;
3077
3078 /* Big Hammer, we also need to ensure that any pending
3079 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3080 * current scanout is retired before unpinning the old
3081 * framebuffer.
3082 *
3083 * This should only fail upon a hung GPU, in which case we
3084 * can safely continue.
3085 */
3086 dev_priv->mm.interruptible = false;
3087 ret = i915_gem_object_finish_gpu(obj);
3088 dev_priv->mm.interruptible = was_interruptible;
3089
3090 return ret;
3091 }
3092
3093 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3094 {
3095 struct drm_device *dev = crtc->dev;
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3098 bool pending;
3099
3100 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3101 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3102 return false;
3103
3104 spin_lock_irq(&dev->event_lock);
3105 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3106 spin_unlock_irq(&dev->event_lock);
3107
3108 return pending;
3109 }
3110
3111 static void intel_update_pipe_size(struct intel_crtc *crtc)
3112 {
3113 struct drm_device *dev = crtc->base.dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 const struct drm_display_mode *adjusted_mode;
3116
3117 if (!i915.fastboot)
3118 return;
3119
3120 /*
3121 * Update pipe size and adjust fitter if needed: the reason for this is
3122 * that in compute_mode_changes we check the native mode (not the pfit
3123 * mode) to see if we can flip rather than do a full mode set. In the
3124 * fastboot case, we'll flip, but if we don't update the pipesrc and
3125 * pfit state, we'll end up with a big fb scanned out into the wrong
3126 * sized surface.
3127 *
3128 * To fix this properly, we need to hoist the checks up into
3129 * compute_mode_changes (or above), check the actual pfit state and
3130 * whether the platform allows pfit disable with pipe active, and only
3131 * then update the pipesrc and pfit state, even on the flip path.
3132 */
3133
3134 adjusted_mode = &crtc->config->base.adjusted_mode;
3135
3136 I915_WRITE(PIPESRC(crtc->pipe),
3137 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3138 (adjusted_mode->crtc_vdisplay - 1));
3139 if (!crtc->config->pch_pfit.enabled &&
3140 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3141 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3142 I915_WRITE(PF_CTL(crtc->pipe), 0);
3143 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3144 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3145 }
3146 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3147 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3148 }
3149
3150 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3151 {
3152 struct drm_device *dev = crtc->dev;
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3155 int pipe = intel_crtc->pipe;
3156 u32 reg, temp;
3157
3158 /* enable normal train */
3159 reg = FDI_TX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 if (IS_IVYBRIDGE(dev)) {
3162 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3163 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3164 } else {
3165 temp &= ~FDI_LINK_TRAIN_NONE;
3166 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3167 }
3168 I915_WRITE(reg, temp);
3169
3170 reg = FDI_RX_CTL(pipe);
3171 temp = I915_READ(reg);
3172 if (HAS_PCH_CPT(dev)) {
3173 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3174 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3175 } else {
3176 temp &= ~FDI_LINK_TRAIN_NONE;
3177 temp |= FDI_LINK_TRAIN_NONE;
3178 }
3179 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3180
3181 /* wait one idle pattern time */
3182 POSTING_READ(reg);
3183 udelay(1000);
3184
3185 /* IVB wants error correction enabled */
3186 if (IS_IVYBRIDGE(dev))
3187 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3188 FDI_FE_ERRC_ENABLE);
3189 }
3190
3191 /* The FDI link training functions for ILK/Ibexpeak. */
3192 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3193 {
3194 struct drm_device *dev = crtc->dev;
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3197 int pipe = intel_crtc->pipe;
3198 u32 reg, temp, tries;
3199
3200 /* FDI needs bits from pipe first */
3201 assert_pipe_enabled(dev_priv, pipe);
3202
3203 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3204 for train result */
3205 reg = FDI_RX_IMR(pipe);
3206 temp = I915_READ(reg);
3207 temp &= ~FDI_RX_SYMBOL_LOCK;
3208 temp &= ~FDI_RX_BIT_LOCK;
3209 I915_WRITE(reg, temp);
3210 I915_READ(reg);
3211 udelay(150);
3212
3213 /* enable CPU FDI TX and PCH FDI RX */
3214 reg = FDI_TX_CTL(pipe);
3215 temp = I915_READ(reg);
3216 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3217 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3218 temp &= ~FDI_LINK_TRAIN_NONE;
3219 temp |= FDI_LINK_TRAIN_PATTERN_1;
3220 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3221
3222 reg = FDI_RX_CTL(pipe);
3223 temp = I915_READ(reg);
3224 temp &= ~FDI_LINK_TRAIN_NONE;
3225 temp |= FDI_LINK_TRAIN_PATTERN_1;
3226 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3227
3228 POSTING_READ(reg);
3229 udelay(150);
3230
3231 /* Ironlake workaround, enable clock pointer after FDI enable*/
3232 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3233 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3234 FDI_RX_PHASE_SYNC_POINTER_EN);
3235
3236 reg = FDI_RX_IIR(pipe);
3237 for (tries = 0; tries < 5; tries++) {
3238 temp = I915_READ(reg);
3239 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3240
3241 if ((temp & FDI_RX_BIT_LOCK)) {
3242 DRM_DEBUG_KMS("FDI train 1 done.\n");
3243 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3244 break;
3245 }
3246 }
3247 if (tries == 5)
3248 DRM_ERROR("FDI train 1 fail!\n");
3249
3250 /* Train 2 */
3251 reg = FDI_TX_CTL(pipe);
3252 temp = I915_READ(reg);
3253 temp &= ~FDI_LINK_TRAIN_NONE;
3254 temp |= FDI_LINK_TRAIN_PATTERN_2;
3255 I915_WRITE(reg, temp);
3256
3257 reg = FDI_RX_CTL(pipe);
3258 temp = I915_READ(reg);
3259 temp &= ~FDI_LINK_TRAIN_NONE;
3260 temp |= FDI_LINK_TRAIN_PATTERN_2;
3261 I915_WRITE(reg, temp);
3262
3263 POSTING_READ(reg);
3264 udelay(150);
3265
3266 reg = FDI_RX_IIR(pipe);
3267 for (tries = 0; tries < 5; tries++) {
3268 temp = I915_READ(reg);
3269 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3270
3271 if (temp & FDI_RX_SYMBOL_LOCK) {
3272 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3273 DRM_DEBUG_KMS("FDI train 2 done.\n");
3274 break;
3275 }
3276 }
3277 if (tries == 5)
3278 DRM_ERROR("FDI train 2 fail!\n");
3279
3280 DRM_DEBUG_KMS("FDI train done\n");
3281
3282 }
3283
3284 static const int snb_b_fdi_train_param[] = {
3285 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3286 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3287 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3288 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3289 };
3290
3291 /* The FDI link training functions for SNB/Cougarpoint. */
3292 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3293 {
3294 struct drm_device *dev = crtc->dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3297 int pipe = intel_crtc->pipe;
3298 u32 reg, temp, i, retry;
3299
3300 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3301 for train result */
3302 reg = FDI_RX_IMR(pipe);
3303 temp = I915_READ(reg);
3304 temp &= ~FDI_RX_SYMBOL_LOCK;
3305 temp &= ~FDI_RX_BIT_LOCK;
3306 I915_WRITE(reg, temp);
3307
3308 POSTING_READ(reg);
3309 udelay(150);
3310
3311 /* enable CPU FDI TX and PCH FDI RX */
3312 reg = FDI_TX_CTL(pipe);
3313 temp = I915_READ(reg);
3314 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3315 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3316 temp &= ~FDI_LINK_TRAIN_NONE;
3317 temp |= FDI_LINK_TRAIN_PATTERN_1;
3318 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3319 /* SNB-B */
3320 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3321 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3322
3323 I915_WRITE(FDI_RX_MISC(pipe),
3324 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3325
3326 reg = FDI_RX_CTL(pipe);
3327 temp = I915_READ(reg);
3328 if (HAS_PCH_CPT(dev)) {
3329 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3330 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3331 } else {
3332 temp &= ~FDI_LINK_TRAIN_NONE;
3333 temp |= FDI_LINK_TRAIN_PATTERN_1;
3334 }
3335 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3336
3337 POSTING_READ(reg);
3338 udelay(150);
3339
3340 for (i = 0; i < 4; i++) {
3341 reg = FDI_TX_CTL(pipe);
3342 temp = I915_READ(reg);
3343 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3344 temp |= snb_b_fdi_train_param[i];
3345 I915_WRITE(reg, temp);
3346
3347 POSTING_READ(reg);
3348 udelay(500);
3349
3350 for (retry = 0; retry < 5; retry++) {
3351 reg = FDI_RX_IIR(pipe);
3352 temp = I915_READ(reg);
3353 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3354 if (temp & FDI_RX_BIT_LOCK) {
3355 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3356 DRM_DEBUG_KMS("FDI train 1 done.\n");
3357 break;
3358 }
3359 udelay(50);
3360 }
3361 if (retry < 5)
3362 break;
3363 }
3364 if (i == 4)
3365 DRM_ERROR("FDI train 1 fail!\n");
3366
3367 /* Train 2 */
3368 reg = FDI_TX_CTL(pipe);
3369 temp = I915_READ(reg);
3370 temp &= ~FDI_LINK_TRAIN_NONE;
3371 temp |= FDI_LINK_TRAIN_PATTERN_2;
3372 if (IS_GEN6(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3374 /* SNB-B */
3375 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3376 }
3377 I915_WRITE(reg, temp);
3378
3379 reg = FDI_RX_CTL(pipe);
3380 temp = I915_READ(reg);
3381 if (HAS_PCH_CPT(dev)) {
3382 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3383 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3384 } else {
3385 temp &= ~FDI_LINK_TRAIN_NONE;
3386 temp |= FDI_LINK_TRAIN_PATTERN_2;
3387 }
3388 I915_WRITE(reg, temp);
3389
3390 POSTING_READ(reg);
3391 udelay(150);
3392
3393 for (i = 0; i < 4; i++) {
3394 reg = FDI_TX_CTL(pipe);
3395 temp = I915_READ(reg);
3396 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3397 temp |= snb_b_fdi_train_param[i];
3398 I915_WRITE(reg, temp);
3399
3400 POSTING_READ(reg);
3401 udelay(500);
3402
3403 for (retry = 0; retry < 5; retry++) {
3404 reg = FDI_RX_IIR(pipe);
3405 temp = I915_READ(reg);
3406 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3407 if (temp & FDI_RX_SYMBOL_LOCK) {
3408 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3409 DRM_DEBUG_KMS("FDI train 2 done.\n");
3410 break;
3411 }
3412 udelay(50);
3413 }
3414 if (retry < 5)
3415 break;
3416 }
3417 if (i == 4)
3418 DRM_ERROR("FDI train 2 fail!\n");
3419
3420 DRM_DEBUG_KMS("FDI train done.\n");
3421 }
3422
3423 /* Manual link training for Ivy Bridge A0 parts */
3424 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3425 {
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429 int pipe = intel_crtc->pipe;
3430 u32 reg, temp, i, j;
3431
3432 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3433 for train result */
3434 reg = FDI_RX_IMR(pipe);
3435 temp = I915_READ(reg);
3436 temp &= ~FDI_RX_SYMBOL_LOCK;
3437 temp &= ~FDI_RX_BIT_LOCK;
3438 I915_WRITE(reg, temp);
3439
3440 POSTING_READ(reg);
3441 udelay(150);
3442
3443 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3444 I915_READ(FDI_RX_IIR(pipe)));
3445
3446 /* Try each vswing and preemphasis setting twice before moving on */
3447 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3448 /* disable first in case we need to retry */
3449 reg = FDI_TX_CTL(pipe);
3450 temp = I915_READ(reg);
3451 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3452 temp &= ~FDI_TX_ENABLE;
3453 I915_WRITE(reg, temp);
3454
3455 reg = FDI_RX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~FDI_LINK_TRAIN_AUTO;
3458 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3459 temp &= ~FDI_RX_ENABLE;
3460 I915_WRITE(reg, temp);
3461
3462 /* enable CPU FDI TX and PCH FDI RX */
3463 reg = FDI_TX_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3466 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3467 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3468 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3469 temp |= snb_b_fdi_train_param[j/2];
3470 temp |= FDI_COMPOSITE_SYNC;
3471 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3472
3473 I915_WRITE(FDI_RX_MISC(pipe),
3474 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3475
3476 reg = FDI_RX_CTL(pipe);
3477 temp = I915_READ(reg);
3478 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3479 temp |= FDI_COMPOSITE_SYNC;
3480 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3481
3482 POSTING_READ(reg);
3483 udelay(1); /* should be 0.5us */
3484
3485 for (i = 0; i < 4; i++) {
3486 reg = FDI_RX_IIR(pipe);
3487 temp = I915_READ(reg);
3488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3489
3490 if (temp & FDI_RX_BIT_LOCK ||
3491 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3492 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3493 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3494 i);
3495 break;
3496 }
3497 udelay(1); /* should be 0.5us */
3498 }
3499 if (i == 4) {
3500 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3501 continue;
3502 }
3503
3504 /* Train 2 */
3505 reg = FDI_TX_CTL(pipe);
3506 temp = I915_READ(reg);
3507 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3508 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3509 I915_WRITE(reg, temp);
3510
3511 reg = FDI_RX_CTL(pipe);
3512 temp = I915_READ(reg);
3513 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3514 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3515 I915_WRITE(reg, temp);
3516
3517 POSTING_READ(reg);
3518 udelay(2); /* should be 1.5us */
3519
3520 for (i = 0; i < 4; i++) {
3521 reg = FDI_RX_IIR(pipe);
3522 temp = I915_READ(reg);
3523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3524
3525 if (temp & FDI_RX_SYMBOL_LOCK ||
3526 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3527 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3528 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3529 i);
3530 goto train_done;
3531 }
3532 udelay(2); /* should be 1.5us */
3533 }
3534 if (i == 4)
3535 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3536 }
3537
3538 train_done:
3539 DRM_DEBUG_KMS("FDI train done.\n");
3540 }
3541
3542 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3543 {
3544 struct drm_device *dev = intel_crtc->base.dev;
3545 struct drm_i915_private *dev_priv = dev->dev_private;
3546 int pipe = intel_crtc->pipe;
3547 u32 reg, temp;
3548
3549
3550 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3551 reg = FDI_RX_CTL(pipe);
3552 temp = I915_READ(reg);
3553 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3554 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3555 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3556 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3557
3558 POSTING_READ(reg);
3559 udelay(200);
3560
3561 /* Switch from Rawclk to PCDclk */
3562 temp = I915_READ(reg);
3563 I915_WRITE(reg, temp | FDI_PCDCLK);
3564
3565 POSTING_READ(reg);
3566 udelay(200);
3567
3568 /* Enable CPU FDI TX PLL, always on for Ironlake */
3569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3572 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3573
3574 POSTING_READ(reg);
3575 udelay(100);
3576 }
3577 }
3578
3579 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3580 {
3581 struct drm_device *dev = intel_crtc->base.dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 int pipe = intel_crtc->pipe;
3584 u32 reg, temp;
3585
3586 /* Switch from PCDclk to Rawclk */
3587 reg = FDI_RX_CTL(pipe);
3588 temp = I915_READ(reg);
3589 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3590
3591 /* Disable CPU FDI TX PLL */
3592 reg = FDI_TX_CTL(pipe);
3593 temp = I915_READ(reg);
3594 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3595
3596 POSTING_READ(reg);
3597 udelay(100);
3598
3599 reg = FDI_RX_CTL(pipe);
3600 temp = I915_READ(reg);
3601 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3602
3603 /* Wait for the clocks to turn off. */
3604 POSTING_READ(reg);
3605 udelay(100);
3606 }
3607
3608 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3609 {
3610 struct drm_device *dev = crtc->dev;
3611 struct drm_i915_private *dev_priv = dev->dev_private;
3612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3613 int pipe = intel_crtc->pipe;
3614 u32 reg, temp;
3615
3616 /* disable CPU FDI tx and PCH FDI rx */
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3620 POSTING_READ(reg);
3621
3622 reg = FDI_RX_CTL(pipe);
3623 temp = I915_READ(reg);
3624 temp &= ~(0x7 << 16);
3625 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3626 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3627
3628 POSTING_READ(reg);
3629 udelay(100);
3630
3631 /* Ironlake workaround, disable clock pointer after downing FDI */
3632 if (HAS_PCH_IBX(dev))
3633 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3634
3635 /* still set train pattern 1 */
3636 reg = FDI_TX_CTL(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_LINK_TRAIN_NONE;
3639 temp |= FDI_LINK_TRAIN_PATTERN_1;
3640 I915_WRITE(reg, temp);
3641
3642 reg = FDI_RX_CTL(pipe);
3643 temp = I915_READ(reg);
3644 if (HAS_PCH_CPT(dev)) {
3645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3646 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3647 } else {
3648 temp &= ~FDI_LINK_TRAIN_NONE;
3649 temp |= FDI_LINK_TRAIN_PATTERN_1;
3650 }
3651 /* BPC in FDI rx is consistent with that in PIPECONF */
3652 temp &= ~(0x07 << 16);
3653 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3654 I915_WRITE(reg, temp);
3655
3656 POSTING_READ(reg);
3657 udelay(100);
3658 }
3659
3660 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3661 {
3662 struct intel_crtc *crtc;
3663
3664 /* Note that we don't need to be called with mode_config.lock here
3665 * as our list of CRTC objects is static for the lifetime of the
3666 * device and so cannot disappear as we iterate. Similarly, we can
3667 * happily treat the predicates as racy, atomic checks as userspace
3668 * cannot claim and pin a new fb without at least acquring the
3669 * struct_mutex and so serialising with us.
3670 */
3671 for_each_intel_crtc(dev, crtc) {
3672 if (atomic_read(&crtc->unpin_work_count) == 0)
3673 continue;
3674
3675 if (crtc->unpin_work)
3676 intel_wait_for_vblank(dev, crtc->pipe);
3677
3678 return true;
3679 }
3680
3681 return false;
3682 }
3683
3684 static void page_flip_completed(struct intel_crtc *intel_crtc)
3685 {
3686 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3687 struct intel_unpin_work *work = intel_crtc->unpin_work;
3688
3689 /* ensure that the unpin work is consistent wrt ->pending. */
3690 smp_rmb();
3691 intel_crtc->unpin_work = NULL;
3692
3693 if (work->event)
3694 drm_send_vblank_event(intel_crtc->base.dev,
3695 intel_crtc->pipe,
3696 work->event);
3697
3698 drm_crtc_vblank_put(&intel_crtc->base);
3699
3700 wake_up_all(&dev_priv->pending_flip_queue);
3701 queue_work(dev_priv->wq, &work->work);
3702
3703 trace_i915_flip_complete(intel_crtc->plane,
3704 work->pending_flip_obj);
3705 }
3706
3707 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3708 {
3709 struct drm_device *dev = crtc->dev;
3710 struct drm_i915_private *dev_priv = dev->dev_private;
3711
3712 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3713 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3714 !intel_crtc_has_pending_flip(crtc),
3715 60*HZ) == 0)) {
3716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3717
3718 spin_lock_irq(&dev->event_lock);
3719 if (intel_crtc->unpin_work) {
3720 WARN_ONCE(1, "Removing stuck page flip\n");
3721 page_flip_completed(intel_crtc);
3722 }
3723 spin_unlock_irq(&dev->event_lock);
3724 }
3725
3726 if (crtc->primary->fb) {
3727 mutex_lock(&dev->struct_mutex);
3728 intel_finish_fb(crtc->primary->fb);
3729 mutex_unlock(&dev->struct_mutex);
3730 }
3731 }
3732
3733 /* Program iCLKIP clock to the desired frequency */
3734 static void lpt_program_iclkip(struct drm_crtc *crtc)
3735 {
3736 struct drm_device *dev = crtc->dev;
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3739 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3740 u32 temp;
3741
3742 mutex_lock(&dev_priv->dpio_lock);
3743
3744 /* It is necessary to ungate the pixclk gate prior to programming
3745 * the divisors, and gate it back when it is done.
3746 */
3747 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3748
3749 /* Disable SSCCTL */
3750 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3751 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3752 SBI_SSCCTL_DISABLE,
3753 SBI_ICLK);
3754
3755 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3756 if (clock == 20000) {
3757 auxdiv = 1;
3758 divsel = 0x41;
3759 phaseinc = 0x20;
3760 } else {
3761 /* The iCLK virtual clock root frequency is in MHz,
3762 * but the adjusted_mode->crtc_clock in in KHz. To get the
3763 * divisors, it is necessary to divide one by another, so we
3764 * convert the virtual clock precision to KHz here for higher
3765 * precision.
3766 */
3767 u32 iclk_virtual_root_freq = 172800 * 1000;
3768 u32 iclk_pi_range = 64;
3769 u32 desired_divisor, msb_divisor_value, pi_value;
3770
3771 desired_divisor = (iclk_virtual_root_freq / clock);
3772 msb_divisor_value = desired_divisor / iclk_pi_range;
3773 pi_value = desired_divisor % iclk_pi_range;
3774
3775 auxdiv = 0;
3776 divsel = msb_divisor_value - 2;
3777 phaseinc = pi_value;
3778 }
3779
3780 /* This should not happen with any sane values */
3781 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3782 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3783 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3784 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3785
3786 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3787 clock,
3788 auxdiv,
3789 divsel,
3790 phasedir,
3791 phaseinc);
3792
3793 /* Program SSCDIVINTPHASE6 */
3794 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3795 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3796 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3797 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3798 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3799 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3800 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3801 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3802
3803 /* Program SSCAUXDIV */
3804 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3805 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3806 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3807 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3808
3809 /* Enable modulator and associated divider */
3810 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3811 temp &= ~SBI_SSCCTL_DISABLE;
3812 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3813
3814 /* Wait for initialization time */
3815 udelay(24);
3816
3817 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3818
3819 mutex_unlock(&dev_priv->dpio_lock);
3820 }
3821
3822 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3823 enum pipe pch_transcoder)
3824 {
3825 struct drm_device *dev = crtc->base.dev;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3828
3829 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3830 I915_READ(HTOTAL(cpu_transcoder)));
3831 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3832 I915_READ(HBLANK(cpu_transcoder)));
3833 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3834 I915_READ(HSYNC(cpu_transcoder)));
3835
3836 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3837 I915_READ(VTOTAL(cpu_transcoder)));
3838 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3839 I915_READ(VBLANK(cpu_transcoder)));
3840 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3841 I915_READ(VSYNC(cpu_transcoder)));
3842 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3843 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3844 }
3845
3846 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3847 {
3848 struct drm_i915_private *dev_priv = dev->dev_private;
3849 uint32_t temp;
3850
3851 temp = I915_READ(SOUTH_CHICKEN1);
3852 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3853 return;
3854
3855 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3856 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3857
3858 temp &= ~FDI_BC_BIFURCATION_SELECT;
3859 if (enable)
3860 temp |= FDI_BC_BIFURCATION_SELECT;
3861
3862 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3863 I915_WRITE(SOUTH_CHICKEN1, temp);
3864 POSTING_READ(SOUTH_CHICKEN1);
3865 }
3866
3867 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3868 {
3869 struct drm_device *dev = intel_crtc->base.dev;
3870
3871 switch (intel_crtc->pipe) {
3872 case PIPE_A:
3873 break;
3874 case PIPE_B:
3875 if (intel_crtc->config->fdi_lanes > 2)
3876 cpt_set_fdi_bc_bifurcation(dev, false);
3877 else
3878 cpt_set_fdi_bc_bifurcation(dev, true);
3879
3880 break;
3881 case PIPE_C:
3882 cpt_set_fdi_bc_bifurcation(dev, true);
3883
3884 break;
3885 default:
3886 BUG();
3887 }
3888 }
3889
3890 /*
3891 * Enable PCH resources required for PCH ports:
3892 * - PCH PLLs
3893 * - FDI training & RX/TX
3894 * - update transcoder timings
3895 * - DP transcoding bits
3896 * - transcoder
3897 */
3898 static void ironlake_pch_enable(struct drm_crtc *crtc)
3899 {
3900 struct drm_device *dev = crtc->dev;
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3903 int pipe = intel_crtc->pipe;
3904 u32 reg, temp;
3905
3906 assert_pch_transcoder_disabled(dev_priv, pipe);
3907
3908 if (IS_IVYBRIDGE(dev))
3909 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3910
3911 /* Write the TU size bits before fdi link training, so that error
3912 * detection works. */
3913 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3914 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3915
3916 /* For PCH output, training FDI link */
3917 dev_priv->display.fdi_link_train(crtc);
3918
3919 /* We need to program the right clock selection before writing the pixel
3920 * mutliplier into the DPLL. */
3921 if (HAS_PCH_CPT(dev)) {
3922 u32 sel;
3923
3924 temp = I915_READ(PCH_DPLL_SEL);
3925 temp |= TRANS_DPLL_ENABLE(pipe);
3926 sel = TRANS_DPLLB_SEL(pipe);
3927 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3928 temp |= sel;
3929 else
3930 temp &= ~sel;
3931 I915_WRITE(PCH_DPLL_SEL, temp);
3932 }
3933
3934 /* XXX: pch pll's can be enabled any time before we enable the PCH
3935 * transcoder, and we actually should do this to not upset any PCH
3936 * transcoder that already use the clock when we share it.
3937 *
3938 * Note that enable_shared_dpll tries to do the right thing, but
3939 * get_shared_dpll unconditionally resets the pll - we need that to have
3940 * the right LVDS enable sequence. */
3941 intel_enable_shared_dpll(intel_crtc);
3942
3943 /* set transcoder timing, panel must allow it */
3944 assert_panel_unlocked(dev_priv, pipe);
3945 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3946
3947 intel_fdi_normal_train(crtc);
3948
3949 /* For PCH DP, enable TRANS_DP_CTL */
3950 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3951 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3952 reg = TRANS_DP_CTL(pipe);
3953 temp = I915_READ(reg);
3954 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3955 TRANS_DP_SYNC_MASK |
3956 TRANS_DP_BPC_MASK);
3957 temp |= (TRANS_DP_OUTPUT_ENABLE |
3958 TRANS_DP_ENH_FRAMING);
3959 temp |= bpc << 9; /* same format but at 11:9 */
3960
3961 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3962 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3963 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3964 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3965
3966 switch (intel_trans_dp_port_sel(crtc)) {
3967 case PCH_DP_B:
3968 temp |= TRANS_DP_PORT_SEL_B;
3969 break;
3970 case PCH_DP_C:
3971 temp |= TRANS_DP_PORT_SEL_C;
3972 break;
3973 case PCH_DP_D:
3974 temp |= TRANS_DP_PORT_SEL_D;
3975 break;
3976 default:
3977 BUG();
3978 }
3979
3980 I915_WRITE(reg, temp);
3981 }
3982
3983 ironlake_enable_pch_transcoder(dev_priv, pipe);
3984 }
3985
3986 static void lpt_pch_enable(struct drm_crtc *crtc)
3987 {
3988 struct drm_device *dev = crtc->dev;
3989 struct drm_i915_private *dev_priv = dev->dev_private;
3990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3991 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3992
3993 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3994
3995 lpt_program_iclkip(crtc);
3996
3997 /* Set transcoder timing. */
3998 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3999
4000 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4001 }
4002
4003 void intel_put_shared_dpll(struct intel_crtc *crtc)
4004 {
4005 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4006
4007 if (pll == NULL)
4008 return;
4009
4010 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4011 WARN(1, "bad %s crtc mask\n", pll->name);
4012 return;
4013 }
4014
4015 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4016 if (pll->config.crtc_mask == 0) {
4017 WARN_ON(pll->on);
4018 WARN_ON(pll->active);
4019 }
4020
4021 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4022 }
4023
4024 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4025 struct intel_crtc_state *crtc_state)
4026 {
4027 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4028 struct intel_shared_dpll *pll;
4029 enum intel_dpll_id i;
4030
4031 if (HAS_PCH_IBX(dev_priv->dev)) {
4032 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4033 i = (enum intel_dpll_id) crtc->pipe;
4034 pll = &dev_priv->shared_dplls[i];
4035
4036 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4037 crtc->base.base.id, pll->name);
4038
4039 WARN_ON(pll->new_config->crtc_mask);
4040
4041 goto found;
4042 }
4043
4044 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4045 pll = &dev_priv->shared_dplls[i];
4046
4047 /* Only want to check enabled timings first */
4048 if (pll->new_config->crtc_mask == 0)
4049 continue;
4050
4051 if (memcmp(&crtc_state->dpll_hw_state,
4052 &pll->new_config->hw_state,
4053 sizeof(pll->new_config->hw_state)) == 0) {
4054 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4055 crtc->base.base.id, pll->name,
4056 pll->new_config->crtc_mask,
4057 pll->active);
4058 goto found;
4059 }
4060 }
4061
4062 /* Ok no matching timings, maybe there's a free one? */
4063 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4064 pll = &dev_priv->shared_dplls[i];
4065 if (pll->new_config->crtc_mask == 0) {
4066 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4067 crtc->base.base.id, pll->name);
4068 goto found;
4069 }
4070 }
4071
4072 return NULL;
4073
4074 found:
4075 if (pll->new_config->crtc_mask == 0)
4076 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4077
4078 crtc_state->shared_dpll = i;
4079 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4080 pipe_name(crtc->pipe));
4081
4082 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4083
4084 return pll;
4085 }
4086
4087 /**
4088 * intel_shared_dpll_start_config - start a new PLL staged config
4089 * @dev_priv: DRM device
4090 * @clear_pipes: mask of pipes that will have their PLLs freed
4091 *
4092 * Starts a new PLL staged config, copying the current config but
4093 * releasing the references of pipes specified in clear_pipes.
4094 */
4095 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4096 unsigned clear_pipes)
4097 {
4098 struct intel_shared_dpll *pll;
4099 enum intel_dpll_id i;
4100
4101 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4102 pll = &dev_priv->shared_dplls[i];
4103
4104 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4105 GFP_KERNEL);
4106 if (!pll->new_config)
4107 goto cleanup;
4108
4109 pll->new_config->crtc_mask &= ~clear_pipes;
4110 }
4111
4112 return 0;
4113
4114 cleanup:
4115 while (--i >= 0) {
4116 pll = &dev_priv->shared_dplls[i];
4117 kfree(pll->new_config);
4118 pll->new_config = NULL;
4119 }
4120
4121 return -ENOMEM;
4122 }
4123
4124 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4125 {
4126 struct intel_shared_dpll *pll;
4127 enum intel_dpll_id i;
4128
4129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4130 pll = &dev_priv->shared_dplls[i];
4131
4132 WARN_ON(pll->new_config == &pll->config);
4133
4134 pll->config = *pll->new_config;
4135 kfree(pll->new_config);
4136 pll->new_config = NULL;
4137 }
4138 }
4139
4140 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4141 {
4142 struct intel_shared_dpll *pll;
4143 enum intel_dpll_id i;
4144
4145 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4146 pll = &dev_priv->shared_dplls[i];
4147
4148 WARN_ON(pll->new_config == &pll->config);
4149
4150 kfree(pll->new_config);
4151 pll->new_config = NULL;
4152 }
4153 }
4154
4155 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4156 {
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 int dslreg = PIPEDSL(pipe);
4159 u32 temp;
4160
4161 temp = I915_READ(dslreg);
4162 udelay(500);
4163 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4164 if (wait_for(I915_READ(dslreg) != temp, 5))
4165 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4166 }
4167 }
4168
4169 static void skylake_pfit_enable(struct intel_crtc *crtc)
4170 {
4171 struct drm_device *dev = crtc->base.dev;
4172 struct drm_i915_private *dev_priv = dev->dev_private;
4173 int pipe = crtc->pipe;
4174
4175 if (crtc->config->pch_pfit.enabled) {
4176 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4177 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4178 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4179 }
4180 }
4181
4182 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4183 {
4184 struct drm_device *dev = crtc->base.dev;
4185 struct drm_i915_private *dev_priv = dev->dev_private;
4186 int pipe = crtc->pipe;
4187
4188 if (crtc->config->pch_pfit.enabled) {
4189 /* Force use of hard-coded filter coefficients
4190 * as some pre-programmed values are broken,
4191 * e.g. x201.
4192 */
4193 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4194 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4195 PF_PIPE_SEL_IVB(pipe));
4196 else
4197 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4198 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4199 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4200 }
4201 }
4202
4203 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4204 {
4205 struct drm_device *dev = crtc->dev;
4206 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4207 struct drm_plane *plane;
4208 struct intel_plane *intel_plane;
4209
4210 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4211 intel_plane = to_intel_plane(plane);
4212 if (intel_plane->pipe == pipe)
4213 intel_plane_restore(&intel_plane->base);
4214 }
4215 }
4216
4217 /*
4218 * Disable a plane internally without actually modifying the plane's state.
4219 * This will allow us to easily restore the plane later by just reprogramming
4220 * its state.
4221 */
4222 static void disable_plane_internal(struct drm_plane *plane)
4223 {
4224 struct intel_plane *intel_plane = to_intel_plane(plane);
4225 struct drm_plane_state *state =
4226 plane->funcs->atomic_duplicate_state(plane);
4227 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4228
4229 intel_state->visible = false;
4230 intel_plane->commit_plane(plane, intel_state);
4231
4232 intel_plane_destroy_state(plane, state);
4233 }
4234
4235 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4236 {
4237 struct drm_device *dev = crtc->dev;
4238 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4239 struct drm_plane *plane;
4240 struct intel_plane *intel_plane;
4241
4242 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4243 intel_plane = to_intel_plane(plane);
4244 if (plane->fb && intel_plane->pipe == pipe)
4245 disable_plane_internal(plane);
4246 }
4247 }
4248
4249 void hsw_enable_ips(struct intel_crtc *crtc)
4250 {
4251 struct drm_device *dev = crtc->base.dev;
4252 struct drm_i915_private *dev_priv = dev->dev_private;
4253
4254 if (!crtc->config->ips_enabled)
4255 return;
4256
4257 /* We can only enable IPS after we enable a plane and wait for a vblank */
4258 intel_wait_for_vblank(dev, crtc->pipe);
4259
4260 assert_plane_enabled(dev_priv, crtc->plane);
4261 if (IS_BROADWELL(dev)) {
4262 mutex_lock(&dev_priv->rps.hw_lock);
4263 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4264 mutex_unlock(&dev_priv->rps.hw_lock);
4265 /* Quoting Art Runyan: "its not safe to expect any particular
4266 * value in IPS_CTL bit 31 after enabling IPS through the
4267 * mailbox." Moreover, the mailbox may return a bogus state,
4268 * so we need to just enable it and continue on.
4269 */
4270 } else {
4271 I915_WRITE(IPS_CTL, IPS_ENABLE);
4272 /* The bit only becomes 1 in the next vblank, so this wait here
4273 * is essentially intel_wait_for_vblank. If we don't have this
4274 * and don't wait for vblanks until the end of crtc_enable, then
4275 * the HW state readout code will complain that the expected
4276 * IPS_CTL value is not the one we read. */
4277 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4278 DRM_ERROR("Timed out waiting for IPS enable\n");
4279 }
4280 }
4281
4282 void hsw_disable_ips(struct intel_crtc *crtc)
4283 {
4284 struct drm_device *dev = crtc->base.dev;
4285 struct drm_i915_private *dev_priv = dev->dev_private;
4286
4287 if (!crtc->config->ips_enabled)
4288 return;
4289
4290 assert_plane_enabled(dev_priv, crtc->plane);
4291 if (IS_BROADWELL(dev)) {
4292 mutex_lock(&dev_priv->rps.hw_lock);
4293 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4294 mutex_unlock(&dev_priv->rps.hw_lock);
4295 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4296 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4297 DRM_ERROR("Timed out waiting for IPS disable\n");
4298 } else {
4299 I915_WRITE(IPS_CTL, 0);
4300 POSTING_READ(IPS_CTL);
4301 }
4302
4303 /* We need to wait for a vblank before we can disable the plane. */
4304 intel_wait_for_vblank(dev, crtc->pipe);
4305 }
4306
4307 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4308 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4309 {
4310 struct drm_device *dev = crtc->dev;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313 enum pipe pipe = intel_crtc->pipe;
4314 int palreg = PALETTE(pipe);
4315 int i;
4316 bool reenable_ips = false;
4317
4318 /* The clocks have to be on to load the palette. */
4319 if (!crtc->state->enable || !intel_crtc->active)
4320 return;
4321
4322 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4323 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4324 assert_dsi_pll_enabled(dev_priv);
4325 else
4326 assert_pll_enabled(dev_priv, pipe);
4327 }
4328
4329 /* use legacy palette for Ironlake */
4330 if (!HAS_GMCH_DISPLAY(dev))
4331 palreg = LGC_PALETTE(pipe);
4332
4333 /* Workaround : Do not read or write the pipe palette/gamma data while
4334 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4335 */
4336 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4337 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4338 GAMMA_MODE_MODE_SPLIT)) {
4339 hsw_disable_ips(intel_crtc);
4340 reenable_ips = true;
4341 }
4342
4343 for (i = 0; i < 256; i++) {
4344 I915_WRITE(palreg + 4 * i,
4345 (intel_crtc->lut_r[i] << 16) |
4346 (intel_crtc->lut_g[i] << 8) |
4347 intel_crtc->lut_b[i]);
4348 }
4349
4350 if (reenable_ips)
4351 hsw_enable_ips(intel_crtc);
4352 }
4353
4354 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4355 {
4356 if (!enable && intel_crtc->overlay) {
4357 struct drm_device *dev = intel_crtc->base.dev;
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4359
4360 mutex_lock(&dev->struct_mutex);
4361 dev_priv->mm.interruptible = false;
4362 (void) intel_overlay_switch_off(intel_crtc->overlay);
4363 dev_priv->mm.interruptible = true;
4364 mutex_unlock(&dev->struct_mutex);
4365 }
4366
4367 /* Let userspace switch the overlay on again. In most cases userspace
4368 * has to recompute where to put it anyway.
4369 */
4370 }
4371
4372 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4373 {
4374 struct drm_device *dev = crtc->dev;
4375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4376 int pipe = intel_crtc->pipe;
4377
4378 intel_enable_primary_hw_plane(crtc->primary, crtc);
4379 intel_enable_sprite_planes(crtc);
4380 intel_crtc_update_cursor(crtc, true);
4381 intel_crtc_dpms_overlay(intel_crtc, true);
4382
4383 hsw_enable_ips(intel_crtc);
4384
4385 mutex_lock(&dev->struct_mutex);
4386 intel_fbc_update(dev);
4387 mutex_unlock(&dev->struct_mutex);
4388
4389 /*
4390 * FIXME: Once we grow proper nuclear flip support out of this we need
4391 * to compute the mask of flip planes precisely. For the time being
4392 * consider this a flip from a NULL plane.
4393 */
4394 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4395 }
4396
4397 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4398 {
4399 struct drm_device *dev = crtc->dev;
4400 struct drm_i915_private *dev_priv = dev->dev_private;
4401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4402 int pipe = intel_crtc->pipe;
4403
4404 intel_crtc_wait_for_pending_flips(crtc);
4405
4406 if (dev_priv->fbc.crtc == intel_crtc)
4407 intel_fbc_disable(dev);
4408
4409 hsw_disable_ips(intel_crtc);
4410
4411 intel_crtc_dpms_overlay(intel_crtc, false);
4412 intel_crtc_update_cursor(crtc, false);
4413 intel_disable_sprite_planes(crtc);
4414 intel_disable_primary_hw_plane(crtc->primary, crtc);
4415
4416 /*
4417 * FIXME: Once we grow proper nuclear flip support out of this we need
4418 * to compute the mask of flip planes precisely. For the time being
4419 * consider this a flip to a NULL plane.
4420 */
4421 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4422 }
4423
4424 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4425 {
4426 struct drm_device *dev = crtc->dev;
4427 struct drm_i915_private *dev_priv = dev->dev_private;
4428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4429 struct intel_encoder *encoder;
4430 int pipe = intel_crtc->pipe;
4431
4432 WARN_ON(!crtc->state->enable);
4433
4434 if (intel_crtc->active)
4435 return;
4436
4437 if (intel_crtc->config->has_pch_encoder)
4438 intel_prepare_shared_dpll(intel_crtc);
4439
4440 if (intel_crtc->config->has_dp_encoder)
4441 intel_dp_set_m_n(intel_crtc, M1_N1);
4442
4443 intel_set_pipe_timings(intel_crtc);
4444
4445 if (intel_crtc->config->has_pch_encoder) {
4446 intel_cpu_transcoder_set_m_n(intel_crtc,
4447 &intel_crtc->config->fdi_m_n, NULL);
4448 }
4449
4450 ironlake_set_pipeconf(crtc);
4451
4452 intel_crtc->active = true;
4453
4454 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4455 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4456
4457 for_each_encoder_on_crtc(dev, crtc, encoder)
4458 if (encoder->pre_enable)
4459 encoder->pre_enable(encoder);
4460
4461 if (intel_crtc->config->has_pch_encoder) {
4462 /* Note: FDI PLL enabling _must_ be done before we enable the
4463 * cpu pipes, hence this is separate from all the other fdi/pch
4464 * enabling. */
4465 ironlake_fdi_pll_enable(intel_crtc);
4466 } else {
4467 assert_fdi_tx_disabled(dev_priv, pipe);
4468 assert_fdi_rx_disabled(dev_priv, pipe);
4469 }
4470
4471 ironlake_pfit_enable(intel_crtc);
4472
4473 /*
4474 * On ILK+ LUT must be loaded before the pipe is running but with
4475 * clocks enabled
4476 */
4477 intel_crtc_load_lut(crtc);
4478
4479 intel_update_watermarks(crtc);
4480 intel_enable_pipe(intel_crtc);
4481
4482 if (intel_crtc->config->has_pch_encoder)
4483 ironlake_pch_enable(crtc);
4484
4485 assert_vblank_disabled(crtc);
4486 drm_crtc_vblank_on(crtc);
4487
4488 for_each_encoder_on_crtc(dev, crtc, encoder)
4489 encoder->enable(encoder);
4490
4491 if (HAS_PCH_CPT(dev))
4492 cpt_verify_modeset(dev, intel_crtc->pipe);
4493
4494 intel_crtc_enable_planes(crtc);
4495 }
4496
4497 /* IPS only exists on ULT machines and is tied to pipe A. */
4498 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4499 {
4500 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4501 }
4502
4503 /*
4504 * This implements the workaround described in the "notes" section of the mode
4505 * set sequence documentation. When going from no pipes or single pipe to
4506 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4507 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4508 */
4509 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4510 {
4511 struct drm_device *dev = crtc->base.dev;
4512 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4513
4514 /* We want to get the other_active_crtc only if there's only 1 other
4515 * active crtc. */
4516 for_each_intel_crtc(dev, crtc_it) {
4517 if (!crtc_it->active || crtc_it == crtc)
4518 continue;
4519
4520 if (other_active_crtc)
4521 return;
4522
4523 other_active_crtc = crtc_it;
4524 }
4525 if (!other_active_crtc)
4526 return;
4527
4528 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4529 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4530 }
4531
4532 static void haswell_crtc_enable(struct drm_crtc *crtc)
4533 {
4534 struct drm_device *dev = crtc->dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4537 struct intel_encoder *encoder;
4538 int pipe = intel_crtc->pipe;
4539
4540 WARN_ON(!crtc->state->enable);
4541
4542 if (intel_crtc->active)
4543 return;
4544
4545 if (intel_crtc_to_shared_dpll(intel_crtc))
4546 intel_enable_shared_dpll(intel_crtc);
4547
4548 if (intel_crtc->config->has_dp_encoder)
4549 intel_dp_set_m_n(intel_crtc, M1_N1);
4550
4551 intel_set_pipe_timings(intel_crtc);
4552
4553 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4554 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4555 intel_crtc->config->pixel_multiplier - 1);
4556 }
4557
4558 if (intel_crtc->config->has_pch_encoder) {
4559 intel_cpu_transcoder_set_m_n(intel_crtc,
4560 &intel_crtc->config->fdi_m_n, NULL);
4561 }
4562
4563 haswell_set_pipeconf(crtc);
4564
4565 intel_set_pipe_csc(crtc);
4566
4567 intel_crtc->active = true;
4568
4569 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4570 for_each_encoder_on_crtc(dev, crtc, encoder)
4571 if (encoder->pre_enable)
4572 encoder->pre_enable(encoder);
4573
4574 if (intel_crtc->config->has_pch_encoder) {
4575 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4576 true);
4577 dev_priv->display.fdi_link_train(crtc);
4578 }
4579
4580 intel_ddi_enable_pipe_clock(intel_crtc);
4581
4582 if (IS_SKYLAKE(dev))
4583 skylake_pfit_enable(intel_crtc);
4584 else
4585 ironlake_pfit_enable(intel_crtc);
4586
4587 /*
4588 * On ILK+ LUT must be loaded before the pipe is running but with
4589 * clocks enabled
4590 */
4591 intel_crtc_load_lut(crtc);
4592
4593 intel_ddi_set_pipe_settings(crtc);
4594 intel_ddi_enable_transcoder_func(crtc);
4595
4596 intel_update_watermarks(crtc);
4597 intel_enable_pipe(intel_crtc);
4598
4599 if (intel_crtc->config->has_pch_encoder)
4600 lpt_pch_enable(crtc);
4601
4602 if (intel_crtc->config->dp_encoder_is_mst)
4603 intel_ddi_set_vc_payload_alloc(crtc, true);
4604
4605 assert_vblank_disabled(crtc);
4606 drm_crtc_vblank_on(crtc);
4607
4608 for_each_encoder_on_crtc(dev, crtc, encoder) {
4609 encoder->enable(encoder);
4610 intel_opregion_notify_encoder(encoder, true);
4611 }
4612
4613 /* If we change the relative order between pipe/planes enabling, we need
4614 * to change the workaround. */
4615 haswell_mode_set_planes_workaround(intel_crtc);
4616 intel_crtc_enable_planes(crtc);
4617 }
4618
4619 static void skylake_pfit_disable(struct intel_crtc *crtc)
4620 {
4621 struct drm_device *dev = crtc->base.dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 int pipe = crtc->pipe;
4624
4625 /* To avoid upsetting the power well on haswell only disable the pfit if
4626 * it's in use. The hw state code will make sure we get this right. */
4627 if (crtc->config->pch_pfit.enabled) {
4628 I915_WRITE(PS_CTL(pipe), 0);
4629 I915_WRITE(PS_WIN_POS(pipe), 0);
4630 I915_WRITE(PS_WIN_SZ(pipe), 0);
4631 }
4632 }
4633
4634 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4635 {
4636 struct drm_device *dev = crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638 int pipe = crtc->pipe;
4639
4640 /* To avoid upsetting the power well on haswell only disable the pfit if
4641 * it's in use. The hw state code will make sure we get this right. */
4642 if (crtc->config->pch_pfit.enabled) {
4643 I915_WRITE(PF_CTL(pipe), 0);
4644 I915_WRITE(PF_WIN_POS(pipe), 0);
4645 I915_WRITE(PF_WIN_SZ(pipe), 0);
4646 }
4647 }
4648
4649 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4650 {
4651 struct drm_device *dev = crtc->dev;
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4654 struct intel_encoder *encoder;
4655 int pipe = intel_crtc->pipe;
4656 u32 reg, temp;
4657
4658 if (!intel_crtc->active)
4659 return;
4660
4661 intel_crtc_disable_planes(crtc);
4662
4663 for_each_encoder_on_crtc(dev, crtc, encoder)
4664 encoder->disable(encoder);
4665
4666 drm_crtc_vblank_off(crtc);
4667 assert_vblank_disabled(crtc);
4668
4669 if (intel_crtc->config->has_pch_encoder)
4670 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4671
4672 intel_disable_pipe(intel_crtc);
4673
4674 ironlake_pfit_disable(intel_crtc);
4675
4676 for_each_encoder_on_crtc(dev, crtc, encoder)
4677 if (encoder->post_disable)
4678 encoder->post_disable(encoder);
4679
4680 if (intel_crtc->config->has_pch_encoder) {
4681 ironlake_fdi_disable(crtc);
4682
4683 ironlake_disable_pch_transcoder(dev_priv, pipe);
4684
4685 if (HAS_PCH_CPT(dev)) {
4686 /* disable TRANS_DP_CTL */
4687 reg = TRANS_DP_CTL(pipe);
4688 temp = I915_READ(reg);
4689 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4690 TRANS_DP_PORT_SEL_MASK);
4691 temp |= TRANS_DP_PORT_SEL_NONE;
4692 I915_WRITE(reg, temp);
4693
4694 /* disable DPLL_SEL */
4695 temp = I915_READ(PCH_DPLL_SEL);
4696 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4697 I915_WRITE(PCH_DPLL_SEL, temp);
4698 }
4699
4700 /* disable PCH DPLL */
4701 intel_disable_shared_dpll(intel_crtc);
4702
4703 ironlake_fdi_pll_disable(intel_crtc);
4704 }
4705
4706 intel_crtc->active = false;
4707 intel_update_watermarks(crtc);
4708
4709 mutex_lock(&dev->struct_mutex);
4710 intel_fbc_update(dev);
4711 mutex_unlock(&dev->struct_mutex);
4712 }
4713
4714 static void haswell_crtc_disable(struct drm_crtc *crtc)
4715 {
4716 struct drm_device *dev = crtc->dev;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719 struct intel_encoder *encoder;
4720 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4721
4722 if (!intel_crtc->active)
4723 return;
4724
4725 intel_crtc_disable_planes(crtc);
4726
4727 for_each_encoder_on_crtc(dev, crtc, encoder) {
4728 intel_opregion_notify_encoder(encoder, false);
4729 encoder->disable(encoder);
4730 }
4731
4732 drm_crtc_vblank_off(crtc);
4733 assert_vblank_disabled(crtc);
4734
4735 if (intel_crtc->config->has_pch_encoder)
4736 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4737 false);
4738 intel_disable_pipe(intel_crtc);
4739
4740 if (intel_crtc->config->dp_encoder_is_mst)
4741 intel_ddi_set_vc_payload_alloc(crtc, false);
4742
4743 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4744
4745 if (IS_SKYLAKE(dev))
4746 skylake_pfit_disable(intel_crtc);
4747 else
4748 ironlake_pfit_disable(intel_crtc);
4749
4750 intel_ddi_disable_pipe_clock(intel_crtc);
4751
4752 if (intel_crtc->config->has_pch_encoder) {
4753 lpt_disable_pch_transcoder(dev_priv);
4754 intel_ddi_fdi_disable(crtc);
4755 }
4756
4757 for_each_encoder_on_crtc(dev, crtc, encoder)
4758 if (encoder->post_disable)
4759 encoder->post_disable(encoder);
4760
4761 intel_crtc->active = false;
4762 intel_update_watermarks(crtc);
4763
4764 mutex_lock(&dev->struct_mutex);
4765 intel_fbc_update(dev);
4766 mutex_unlock(&dev->struct_mutex);
4767
4768 if (intel_crtc_to_shared_dpll(intel_crtc))
4769 intel_disable_shared_dpll(intel_crtc);
4770 }
4771
4772 static void ironlake_crtc_off(struct drm_crtc *crtc)
4773 {
4774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4775 intel_put_shared_dpll(intel_crtc);
4776 }
4777
4778
4779 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4780 {
4781 struct drm_device *dev = crtc->base.dev;
4782 struct drm_i915_private *dev_priv = dev->dev_private;
4783 struct intel_crtc_state *pipe_config = crtc->config;
4784
4785 if (!pipe_config->gmch_pfit.control)
4786 return;
4787
4788 /*
4789 * The panel fitter should only be adjusted whilst the pipe is disabled,
4790 * according to register description and PRM.
4791 */
4792 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4793 assert_pipe_disabled(dev_priv, crtc->pipe);
4794
4795 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4796 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4797
4798 /* Border color in case we don't scale up to the full screen. Black by
4799 * default, change to something else for debugging. */
4800 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4801 }
4802
4803 static enum intel_display_power_domain port_to_power_domain(enum port port)
4804 {
4805 switch (port) {
4806 case PORT_A:
4807 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4808 case PORT_B:
4809 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4810 case PORT_C:
4811 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4812 case PORT_D:
4813 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4814 default:
4815 WARN_ON_ONCE(1);
4816 return POWER_DOMAIN_PORT_OTHER;
4817 }
4818 }
4819
4820 #define for_each_power_domain(domain, mask) \
4821 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4822 if ((1 << (domain)) & (mask))
4823
4824 enum intel_display_power_domain
4825 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4826 {
4827 struct drm_device *dev = intel_encoder->base.dev;
4828 struct intel_digital_port *intel_dig_port;
4829
4830 switch (intel_encoder->type) {
4831 case INTEL_OUTPUT_UNKNOWN:
4832 /* Only DDI platforms should ever use this output type */
4833 WARN_ON_ONCE(!HAS_DDI(dev));
4834 case INTEL_OUTPUT_DISPLAYPORT:
4835 case INTEL_OUTPUT_HDMI:
4836 case INTEL_OUTPUT_EDP:
4837 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4838 return port_to_power_domain(intel_dig_port->port);
4839 case INTEL_OUTPUT_DP_MST:
4840 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4841 return port_to_power_domain(intel_dig_port->port);
4842 case INTEL_OUTPUT_ANALOG:
4843 return POWER_DOMAIN_PORT_CRT;
4844 case INTEL_OUTPUT_DSI:
4845 return POWER_DOMAIN_PORT_DSI;
4846 default:
4847 return POWER_DOMAIN_PORT_OTHER;
4848 }
4849 }
4850
4851 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4852 {
4853 struct drm_device *dev = crtc->dev;
4854 struct intel_encoder *intel_encoder;
4855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4856 enum pipe pipe = intel_crtc->pipe;
4857 unsigned long mask;
4858 enum transcoder transcoder;
4859
4860 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4861
4862 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4863 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4864 if (intel_crtc->config->pch_pfit.enabled ||
4865 intel_crtc->config->pch_pfit.force_thru)
4866 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4867
4868 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4869 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4870
4871 return mask;
4872 }
4873
4874 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4875 {
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4877 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4878 struct intel_crtc *crtc;
4879
4880 /*
4881 * First get all needed power domains, then put all unneeded, to avoid
4882 * any unnecessary toggling of the power wells.
4883 */
4884 for_each_intel_crtc(dev, crtc) {
4885 enum intel_display_power_domain domain;
4886
4887 if (!crtc->base.state->enable)
4888 continue;
4889
4890 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4891
4892 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4893 intel_display_power_get(dev_priv, domain);
4894 }
4895
4896 if (dev_priv->display.modeset_global_resources)
4897 dev_priv->display.modeset_global_resources(dev);
4898
4899 for_each_intel_crtc(dev, crtc) {
4900 enum intel_display_power_domain domain;
4901
4902 for_each_power_domain(domain, crtc->enabled_power_domains)
4903 intel_display_power_put(dev_priv, domain);
4904
4905 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4906 }
4907
4908 intel_display_set_init_power(dev_priv, false);
4909 }
4910
4911 /* returns HPLL frequency in kHz */
4912 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4913 {
4914 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4915
4916 /* Obtain SKU information */
4917 mutex_lock(&dev_priv->dpio_lock);
4918 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4919 CCK_FUSE_HPLL_FREQ_MASK;
4920 mutex_unlock(&dev_priv->dpio_lock);
4921
4922 return vco_freq[hpll_freq] * 1000;
4923 }
4924
4925 static void vlv_update_cdclk(struct drm_device *dev)
4926 {
4927 struct drm_i915_private *dev_priv = dev->dev_private;
4928
4929 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4930 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4931 dev_priv->vlv_cdclk_freq);
4932
4933 /*
4934 * Program the gmbus_freq based on the cdclk frequency.
4935 * BSpec erroneously claims we should aim for 4MHz, but
4936 * in fact 1MHz is the correct frequency.
4937 */
4938 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4939 }
4940
4941 /* Adjust CDclk dividers to allow high res or save power if possible */
4942 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4943 {
4944 struct drm_i915_private *dev_priv = dev->dev_private;
4945 u32 val, cmd;
4946
4947 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4948
4949 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4950 cmd = 2;
4951 else if (cdclk == 266667)
4952 cmd = 1;
4953 else
4954 cmd = 0;
4955
4956 mutex_lock(&dev_priv->rps.hw_lock);
4957 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4958 val &= ~DSPFREQGUAR_MASK;
4959 val |= (cmd << DSPFREQGUAR_SHIFT);
4960 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4961 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4962 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4963 50)) {
4964 DRM_ERROR("timed out waiting for CDclk change\n");
4965 }
4966 mutex_unlock(&dev_priv->rps.hw_lock);
4967
4968 if (cdclk == 400000) {
4969 u32 divider;
4970
4971 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4972
4973 mutex_lock(&dev_priv->dpio_lock);
4974 /* adjust cdclk divider */
4975 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4976 val &= ~DISPLAY_FREQUENCY_VALUES;
4977 val |= divider;
4978 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4979
4980 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4981 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4982 50))
4983 DRM_ERROR("timed out waiting for CDclk change\n");
4984 mutex_unlock(&dev_priv->dpio_lock);
4985 }
4986
4987 mutex_lock(&dev_priv->dpio_lock);
4988 /* adjust self-refresh exit latency value */
4989 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4990 val &= ~0x7f;
4991
4992 /*
4993 * For high bandwidth configs, we set a higher latency in the bunit
4994 * so that the core display fetch happens in time to avoid underruns.
4995 */
4996 if (cdclk == 400000)
4997 val |= 4500 / 250; /* 4.5 usec */
4998 else
4999 val |= 3000 / 250; /* 3.0 usec */
5000 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5001 mutex_unlock(&dev_priv->dpio_lock);
5002
5003 vlv_update_cdclk(dev);
5004 }
5005
5006 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5007 {
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009 u32 val, cmd;
5010
5011 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5012
5013 switch (cdclk) {
5014 case 333333:
5015 case 320000:
5016 case 266667:
5017 case 200000:
5018 break;
5019 default:
5020 MISSING_CASE(cdclk);
5021 return;
5022 }
5023
5024 /*
5025 * Specs are full of misinformation, but testing on actual
5026 * hardware has shown that we just need to write the desired
5027 * CCK divider into the Punit register.
5028 */
5029 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5030
5031 mutex_lock(&dev_priv->rps.hw_lock);
5032 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5033 val &= ~DSPFREQGUAR_MASK_CHV;
5034 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5035 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5036 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5037 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5038 50)) {
5039 DRM_ERROR("timed out waiting for CDclk change\n");
5040 }
5041 mutex_unlock(&dev_priv->rps.hw_lock);
5042
5043 vlv_update_cdclk(dev);
5044 }
5045
5046 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5047 int max_pixclk)
5048 {
5049 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5050 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5051
5052 /*
5053 * Really only a few cases to deal with, as only 4 CDclks are supported:
5054 * 200MHz
5055 * 267MHz
5056 * 320/333MHz (depends on HPLL freq)
5057 * 400MHz (VLV only)
5058 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5059 * of the lower bin and adjust if needed.
5060 *
5061 * We seem to get an unstable or solid color picture at 200MHz.
5062 * Not sure what's wrong. For now use 200MHz only when all pipes
5063 * are off.
5064 */
5065 if (!IS_CHERRYVIEW(dev_priv) &&
5066 max_pixclk > freq_320*limit/100)
5067 return 400000;
5068 else if (max_pixclk > 266667*limit/100)
5069 return freq_320;
5070 else if (max_pixclk > 0)
5071 return 266667;
5072 else
5073 return 200000;
5074 }
5075
5076 /* compute the max pixel clock for new configuration */
5077 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5078 {
5079 struct drm_device *dev = dev_priv->dev;
5080 struct intel_crtc *intel_crtc;
5081 int max_pixclk = 0;
5082
5083 for_each_intel_crtc(dev, intel_crtc) {
5084 if (intel_crtc->new_enabled)
5085 max_pixclk = max(max_pixclk,
5086 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5087 }
5088
5089 return max_pixclk;
5090 }
5091
5092 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5093 unsigned *prepare_pipes)
5094 {
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096 struct intel_crtc *intel_crtc;
5097 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5098
5099 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5100 dev_priv->vlv_cdclk_freq)
5101 return;
5102
5103 /* disable/enable all currently active pipes while we change cdclk */
5104 for_each_intel_crtc(dev, intel_crtc)
5105 if (intel_crtc->base.state->enable)
5106 *prepare_pipes |= (1 << intel_crtc->pipe);
5107 }
5108
5109 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5110 {
5111 unsigned int credits, default_credits;
5112
5113 if (IS_CHERRYVIEW(dev_priv))
5114 default_credits = PFI_CREDIT(12);
5115 else
5116 default_credits = PFI_CREDIT(8);
5117
5118 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5119 /* CHV suggested value is 31 or 63 */
5120 if (IS_CHERRYVIEW(dev_priv))
5121 credits = PFI_CREDIT_31;
5122 else
5123 credits = PFI_CREDIT(15);
5124 } else {
5125 credits = default_credits;
5126 }
5127
5128 /*
5129 * WA - write default credits before re-programming
5130 * FIXME: should we also set the resend bit here?
5131 */
5132 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5133 default_credits);
5134
5135 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5136 credits | PFI_CREDIT_RESEND);
5137
5138 /*
5139 * FIXME is this guaranteed to clear
5140 * immediately or should we poll for it?
5141 */
5142 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5143 }
5144
5145 static void valleyview_modeset_global_resources(struct drm_device *dev)
5146 {
5147 struct drm_i915_private *dev_priv = dev->dev_private;
5148 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5149 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5150
5151 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5152 /*
5153 * FIXME: We can end up here with all power domains off, yet
5154 * with a CDCLK frequency other than the minimum. To account
5155 * for this take the PIPE-A power domain, which covers the HW
5156 * blocks needed for the following programming. This can be
5157 * removed once it's guaranteed that we get here either with
5158 * the minimum CDCLK set, or the required power domains
5159 * enabled.
5160 */
5161 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5162
5163 if (IS_CHERRYVIEW(dev))
5164 cherryview_set_cdclk(dev, req_cdclk);
5165 else
5166 valleyview_set_cdclk(dev, req_cdclk);
5167
5168 vlv_program_pfi_credits(dev_priv);
5169
5170 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5171 }
5172 }
5173
5174 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5175 {
5176 struct drm_device *dev = crtc->dev;
5177 struct drm_i915_private *dev_priv = to_i915(dev);
5178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5179 struct intel_encoder *encoder;
5180 int pipe = intel_crtc->pipe;
5181 bool is_dsi;
5182
5183 WARN_ON(!crtc->state->enable);
5184
5185 if (intel_crtc->active)
5186 return;
5187
5188 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5189
5190 if (!is_dsi) {
5191 if (IS_CHERRYVIEW(dev))
5192 chv_prepare_pll(intel_crtc, intel_crtc->config);
5193 else
5194 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5195 }
5196
5197 if (intel_crtc->config->has_dp_encoder)
5198 intel_dp_set_m_n(intel_crtc, M1_N1);
5199
5200 intel_set_pipe_timings(intel_crtc);
5201
5202 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204
5205 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5206 I915_WRITE(CHV_CANVAS(pipe), 0);
5207 }
5208
5209 i9xx_set_pipeconf(intel_crtc);
5210
5211 intel_crtc->active = true;
5212
5213 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5214
5215 for_each_encoder_on_crtc(dev, crtc, encoder)
5216 if (encoder->pre_pll_enable)
5217 encoder->pre_pll_enable(encoder);
5218
5219 if (!is_dsi) {
5220 if (IS_CHERRYVIEW(dev))
5221 chv_enable_pll(intel_crtc, intel_crtc->config);
5222 else
5223 vlv_enable_pll(intel_crtc, intel_crtc->config);
5224 }
5225
5226 for_each_encoder_on_crtc(dev, crtc, encoder)
5227 if (encoder->pre_enable)
5228 encoder->pre_enable(encoder);
5229
5230 i9xx_pfit_enable(intel_crtc);
5231
5232 intel_crtc_load_lut(crtc);
5233
5234 intel_update_watermarks(crtc);
5235 intel_enable_pipe(intel_crtc);
5236
5237 assert_vblank_disabled(crtc);
5238 drm_crtc_vblank_on(crtc);
5239
5240 for_each_encoder_on_crtc(dev, crtc, encoder)
5241 encoder->enable(encoder);
5242
5243 intel_crtc_enable_planes(crtc);
5244
5245 /* Underruns don't raise interrupts, so check manually. */
5246 i9xx_check_fifo_underruns(dev_priv);
5247 }
5248
5249 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5250 {
5251 struct drm_device *dev = crtc->base.dev;
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253
5254 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5255 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5256 }
5257
5258 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5259 {
5260 struct drm_device *dev = crtc->dev;
5261 struct drm_i915_private *dev_priv = to_i915(dev);
5262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5263 struct intel_encoder *encoder;
5264 int pipe = intel_crtc->pipe;
5265
5266 WARN_ON(!crtc->state->enable);
5267
5268 if (intel_crtc->active)
5269 return;
5270
5271 i9xx_set_pll_dividers(intel_crtc);
5272
5273 if (intel_crtc->config->has_dp_encoder)
5274 intel_dp_set_m_n(intel_crtc, M1_N1);
5275
5276 intel_set_pipe_timings(intel_crtc);
5277
5278 i9xx_set_pipeconf(intel_crtc);
5279
5280 intel_crtc->active = true;
5281
5282 if (!IS_GEN2(dev))
5283 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5284
5285 for_each_encoder_on_crtc(dev, crtc, encoder)
5286 if (encoder->pre_enable)
5287 encoder->pre_enable(encoder);
5288
5289 i9xx_enable_pll(intel_crtc);
5290
5291 i9xx_pfit_enable(intel_crtc);
5292
5293 intel_crtc_load_lut(crtc);
5294
5295 intel_update_watermarks(crtc);
5296 intel_enable_pipe(intel_crtc);
5297
5298 assert_vblank_disabled(crtc);
5299 drm_crtc_vblank_on(crtc);
5300
5301 for_each_encoder_on_crtc(dev, crtc, encoder)
5302 encoder->enable(encoder);
5303
5304 intel_crtc_enable_planes(crtc);
5305
5306 /*
5307 * Gen2 reports pipe underruns whenever all planes are disabled.
5308 * So don't enable underrun reporting before at least some planes
5309 * are enabled.
5310 * FIXME: Need to fix the logic to work when we turn off all planes
5311 * but leave the pipe running.
5312 */
5313 if (IS_GEN2(dev))
5314 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5315
5316 /* Underruns don't raise interrupts, so check manually. */
5317 i9xx_check_fifo_underruns(dev_priv);
5318 }
5319
5320 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5321 {
5322 struct drm_device *dev = crtc->base.dev;
5323 struct drm_i915_private *dev_priv = dev->dev_private;
5324
5325 if (!crtc->config->gmch_pfit.control)
5326 return;
5327
5328 assert_pipe_disabled(dev_priv, crtc->pipe);
5329
5330 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5331 I915_READ(PFIT_CONTROL));
5332 I915_WRITE(PFIT_CONTROL, 0);
5333 }
5334
5335 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5336 {
5337 struct drm_device *dev = crtc->dev;
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5340 struct intel_encoder *encoder;
5341 int pipe = intel_crtc->pipe;
5342
5343 if (!intel_crtc->active)
5344 return;
5345
5346 /*
5347 * Gen2 reports pipe underruns whenever all planes are disabled.
5348 * So diasble underrun reporting before all the planes get disabled.
5349 * FIXME: Need to fix the logic to work when we turn off all planes
5350 * but leave the pipe running.
5351 */
5352 if (IS_GEN2(dev))
5353 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5354
5355 /*
5356 * Vblank time updates from the shadow to live plane control register
5357 * are blocked if the memory self-refresh mode is active at that
5358 * moment. So to make sure the plane gets truly disabled, disable
5359 * first the self-refresh mode. The self-refresh enable bit in turn
5360 * will be checked/applied by the HW only at the next frame start
5361 * event which is after the vblank start event, so we need to have a
5362 * wait-for-vblank between disabling the plane and the pipe.
5363 */
5364 intel_set_memory_cxsr(dev_priv, false);
5365 intel_crtc_disable_planes(crtc);
5366
5367 /*
5368 * On gen2 planes are double buffered but the pipe isn't, so we must
5369 * wait for planes to fully turn off before disabling the pipe.
5370 * We also need to wait on all gmch platforms because of the
5371 * self-refresh mode constraint explained above.
5372 */
5373 intel_wait_for_vblank(dev, pipe);
5374
5375 for_each_encoder_on_crtc(dev, crtc, encoder)
5376 encoder->disable(encoder);
5377
5378 drm_crtc_vblank_off(crtc);
5379 assert_vblank_disabled(crtc);
5380
5381 intel_disable_pipe(intel_crtc);
5382
5383 i9xx_pfit_disable(intel_crtc);
5384
5385 for_each_encoder_on_crtc(dev, crtc, encoder)
5386 if (encoder->post_disable)
5387 encoder->post_disable(encoder);
5388
5389 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5390 if (IS_CHERRYVIEW(dev))
5391 chv_disable_pll(dev_priv, pipe);
5392 else if (IS_VALLEYVIEW(dev))
5393 vlv_disable_pll(dev_priv, pipe);
5394 else
5395 i9xx_disable_pll(intel_crtc);
5396 }
5397
5398 if (!IS_GEN2(dev))
5399 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5400
5401 intel_crtc->active = false;
5402 intel_update_watermarks(crtc);
5403
5404 mutex_lock(&dev->struct_mutex);
5405 intel_fbc_update(dev);
5406 mutex_unlock(&dev->struct_mutex);
5407 }
5408
5409 static void i9xx_crtc_off(struct drm_crtc *crtc)
5410 {
5411 }
5412
5413 /* Master function to enable/disable CRTC and corresponding power wells */
5414 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5415 {
5416 struct drm_device *dev = crtc->dev;
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419 enum intel_display_power_domain domain;
5420 unsigned long domains;
5421
5422 if (enable) {
5423 if (!intel_crtc->active) {
5424 domains = get_crtc_power_domains(crtc);
5425 for_each_power_domain(domain, domains)
5426 intel_display_power_get(dev_priv, domain);
5427 intel_crtc->enabled_power_domains = domains;
5428
5429 dev_priv->display.crtc_enable(crtc);
5430 }
5431 } else {
5432 if (intel_crtc->active) {
5433 dev_priv->display.crtc_disable(crtc);
5434
5435 domains = intel_crtc->enabled_power_domains;
5436 for_each_power_domain(domain, domains)
5437 intel_display_power_put(dev_priv, domain);
5438 intel_crtc->enabled_power_domains = 0;
5439 }
5440 }
5441 }
5442
5443 /**
5444 * Sets the power management mode of the pipe and plane.
5445 */
5446 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5447 {
5448 struct drm_device *dev = crtc->dev;
5449 struct intel_encoder *intel_encoder;
5450 bool enable = false;
5451
5452 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5453 enable |= intel_encoder->connectors_active;
5454
5455 intel_crtc_control(crtc, enable);
5456 }
5457
5458 static void intel_crtc_disable(struct drm_crtc *crtc)
5459 {
5460 struct drm_device *dev = crtc->dev;
5461 struct drm_connector *connector;
5462 struct drm_i915_private *dev_priv = dev->dev_private;
5463
5464 /* crtc should still be enabled when we disable it. */
5465 WARN_ON(!crtc->state->enable);
5466
5467 dev_priv->display.crtc_disable(crtc);
5468 dev_priv->display.off(crtc);
5469
5470 crtc->primary->funcs->disable_plane(crtc->primary);
5471
5472 /* Update computed state. */
5473 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5474 if (!connector->encoder || !connector->encoder->crtc)
5475 continue;
5476
5477 if (connector->encoder->crtc != crtc)
5478 continue;
5479
5480 connector->dpms = DRM_MODE_DPMS_OFF;
5481 to_intel_encoder(connector->encoder)->connectors_active = false;
5482 }
5483 }
5484
5485 void intel_encoder_destroy(struct drm_encoder *encoder)
5486 {
5487 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5488
5489 drm_encoder_cleanup(encoder);
5490 kfree(intel_encoder);
5491 }
5492
5493 /* Simple dpms helper for encoders with just one connector, no cloning and only
5494 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5495 * state of the entire output pipe. */
5496 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5497 {
5498 if (mode == DRM_MODE_DPMS_ON) {
5499 encoder->connectors_active = true;
5500
5501 intel_crtc_update_dpms(encoder->base.crtc);
5502 } else {
5503 encoder->connectors_active = false;
5504
5505 intel_crtc_update_dpms(encoder->base.crtc);
5506 }
5507 }
5508
5509 /* Cross check the actual hw state with our own modeset state tracking (and it's
5510 * internal consistency). */
5511 static void intel_connector_check_state(struct intel_connector *connector)
5512 {
5513 if (connector->get_hw_state(connector)) {
5514 struct intel_encoder *encoder = connector->encoder;
5515 struct drm_crtc *crtc;
5516 bool encoder_enabled;
5517 enum pipe pipe;
5518
5519 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5520 connector->base.base.id,
5521 connector->base.name);
5522
5523 /* there is no real hw state for MST connectors */
5524 if (connector->mst_port)
5525 return;
5526
5527 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5528 "wrong connector dpms state\n");
5529 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5530 "active connector not linked to encoder\n");
5531
5532 if (encoder) {
5533 I915_STATE_WARN(!encoder->connectors_active,
5534 "encoder->connectors_active not set\n");
5535
5536 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5537 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5538 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5539 return;
5540
5541 crtc = encoder->base.crtc;
5542
5543 I915_STATE_WARN(!crtc->state->enable,
5544 "crtc not enabled\n");
5545 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5546 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5547 "encoder active on the wrong pipe\n");
5548 }
5549 }
5550 }
5551
5552 /* Even simpler default implementation, if there's really no special case to
5553 * consider. */
5554 void intel_connector_dpms(struct drm_connector *connector, int mode)
5555 {
5556 /* All the simple cases only support two dpms states. */
5557 if (mode != DRM_MODE_DPMS_ON)
5558 mode = DRM_MODE_DPMS_OFF;
5559
5560 if (mode == connector->dpms)
5561 return;
5562
5563 connector->dpms = mode;
5564
5565 /* Only need to change hw state when actually enabled */
5566 if (connector->encoder)
5567 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5568
5569 intel_modeset_check_state(connector->dev);
5570 }
5571
5572 /* Simple connector->get_hw_state implementation for encoders that support only
5573 * one connector and no cloning and hence the encoder state determines the state
5574 * of the connector. */
5575 bool intel_connector_get_hw_state(struct intel_connector *connector)
5576 {
5577 enum pipe pipe = 0;
5578 struct intel_encoder *encoder = connector->encoder;
5579
5580 return encoder->get_hw_state(encoder, &pipe);
5581 }
5582
5583 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5584 {
5585 struct intel_crtc *crtc =
5586 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5587
5588 if (crtc->base.state->enable &&
5589 crtc->config->has_pch_encoder)
5590 return crtc->config->fdi_lanes;
5591
5592 return 0;
5593 }
5594
5595 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5596 struct intel_crtc_state *pipe_config)
5597 {
5598 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5599 pipe_name(pipe), pipe_config->fdi_lanes);
5600 if (pipe_config->fdi_lanes > 4) {
5601 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5602 pipe_name(pipe), pipe_config->fdi_lanes);
5603 return false;
5604 }
5605
5606 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5607 if (pipe_config->fdi_lanes > 2) {
5608 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5609 pipe_config->fdi_lanes);
5610 return false;
5611 } else {
5612 return true;
5613 }
5614 }
5615
5616 if (INTEL_INFO(dev)->num_pipes == 2)
5617 return true;
5618
5619 /* Ivybridge 3 pipe is really complicated */
5620 switch (pipe) {
5621 case PIPE_A:
5622 return true;
5623 case PIPE_B:
5624 if (pipe_config->fdi_lanes > 2 &&
5625 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5626 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5627 pipe_name(pipe), pipe_config->fdi_lanes);
5628 return false;
5629 }
5630 return true;
5631 case PIPE_C:
5632 if (pipe_config->fdi_lanes > 2) {
5633 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5634 pipe_name(pipe), pipe_config->fdi_lanes);
5635 return false;
5636 }
5637 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5638 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5639 return false;
5640 }
5641 return true;
5642 default:
5643 BUG();
5644 }
5645 }
5646
5647 #define RETRY 1
5648 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5649 struct intel_crtc_state *pipe_config)
5650 {
5651 struct drm_device *dev = intel_crtc->base.dev;
5652 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5653 int lane, link_bw, fdi_dotclock;
5654 bool setup_ok, needs_recompute = false;
5655
5656 retry:
5657 /* FDI is a binary signal running at ~2.7GHz, encoding
5658 * each output octet as 10 bits. The actual frequency
5659 * is stored as a divider into a 100MHz clock, and the
5660 * mode pixel clock is stored in units of 1KHz.
5661 * Hence the bw of each lane in terms of the mode signal
5662 * is:
5663 */
5664 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5665
5666 fdi_dotclock = adjusted_mode->crtc_clock;
5667
5668 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5669 pipe_config->pipe_bpp);
5670
5671 pipe_config->fdi_lanes = lane;
5672
5673 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5674 link_bw, &pipe_config->fdi_m_n);
5675
5676 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5677 intel_crtc->pipe, pipe_config);
5678 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5679 pipe_config->pipe_bpp -= 2*3;
5680 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5681 pipe_config->pipe_bpp);
5682 needs_recompute = true;
5683 pipe_config->bw_constrained = true;
5684
5685 goto retry;
5686 }
5687
5688 if (needs_recompute)
5689 return RETRY;
5690
5691 return setup_ok ? 0 : -EINVAL;
5692 }
5693
5694 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5695 struct intel_crtc_state *pipe_config)
5696 {
5697 pipe_config->ips_enabled = i915.enable_ips &&
5698 hsw_crtc_supports_ips(crtc) &&
5699 pipe_config->pipe_bpp <= 24;
5700 }
5701
5702 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5703 struct intel_crtc_state *pipe_config)
5704 {
5705 struct drm_device *dev = crtc->base.dev;
5706 struct drm_i915_private *dev_priv = dev->dev_private;
5707 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5708
5709 /* FIXME should check pixel clock limits on all platforms */
5710 if (INTEL_INFO(dev)->gen < 4) {
5711 int clock_limit =
5712 dev_priv->display.get_display_clock_speed(dev);
5713
5714 /*
5715 * Enable pixel doubling when the dot clock
5716 * is > 90% of the (display) core speed.
5717 *
5718 * GDG double wide on either pipe,
5719 * otherwise pipe A only.
5720 */
5721 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5722 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5723 clock_limit *= 2;
5724 pipe_config->double_wide = true;
5725 }
5726
5727 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5728 return -EINVAL;
5729 }
5730
5731 /*
5732 * Pipe horizontal size must be even in:
5733 * - DVO ganged mode
5734 * - LVDS dual channel mode
5735 * - Double wide pipe
5736 */
5737 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5738 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5739 pipe_config->pipe_src_w &= ~1;
5740
5741 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5742 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5743 */
5744 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5745 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5746 return -EINVAL;
5747
5748 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5749 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5750 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5751 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5752 * for lvds. */
5753 pipe_config->pipe_bpp = 8*3;
5754 }
5755
5756 if (HAS_IPS(dev))
5757 hsw_compute_ips_config(crtc, pipe_config);
5758
5759 if (pipe_config->has_pch_encoder)
5760 return ironlake_fdi_compute_config(crtc, pipe_config);
5761
5762 return 0;
5763 }
5764
5765 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5766 {
5767 struct drm_i915_private *dev_priv = dev->dev_private;
5768 u32 val;
5769 int divider;
5770
5771 if (dev_priv->hpll_freq == 0)
5772 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5773
5774 mutex_lock(&dev_priv->dpio_lock);
5775 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5776 mutex_unlock(&dev_priv->dpio_lock);
5777
5778 divider = val & DISPLAY_FREQUENCY_VALUES;
5779
5780 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5781 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5782 "cdclk change in progress\n");
5783
5784 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5785 }
5786
5787 static int i945_get_display_clock_speed(struct drm_device *dev)
5788 {
5789 return 400000;
5790 }
5791
5792 static int i915_get_display_clock_speed(struct drm_device *dev)
5793 {
5794 return 333000;
5795 }
5796
5797 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5798 {
5799 return 200000;
5800 }
5801
5802 static int pnv_get_display_clock_speed(struct drm_device *dev)
5803 {
5804 u16 gcfgc = 0;
5805
5806 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5807
5808 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5809 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5810 return 267000;
5811 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5812 return 333000;
5813 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5814 return 444000;
5815 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5816 return 200000;
5817 default:
5818 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5819 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5820 return 133000;
5821 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5822 return 167000;
5823 }
5824 }
5825
5826 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5827 {
5828 u16 gcfgc = 0;
5829
5830 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5831
5832 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5833 return 133000;
5834 else {
5835 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5836 case GC_DISPLAY_CLOCK_333_MHZ:
5837 return 333000;
5838 default:
5839 case GC_DISPLAY_CLOCK_190_200_MHZ:
5840 return 190000;
5841 }
5842 }
5843 }
5844
5845 static int i865_get_display_clock_speed(struct drm_device *dev)
5846 {
5847 return 266000;
5848 }
5849
5850 static int i855_get_display_clock_speed(struct drm_device *dev)
5851 {
5852 u16 hpllcc = 0;
5853 /* Assume that the hardware is in the high speed state. This
5854 * should be the default.
5855 */
5856 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5857 case GC_CLOCK_133_200:
5858 case GC_CLOCK_100_200:
5859 return 200000;
5860 case GC_CLOCK_166_250:
5861 return 250000;
5862 case GC_CLOCK_100_133:
5863 return 133000;
5864 }
5865
5866 /* Shouldn't happen */
5867 return 0;
5868 }
5869
5870 static int i830_get_display_clock_speed(struct drm_device *dev)
5871 {
5872 return 133000;
5873 }
5874
5875 static void
5876 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5877 {
5878 while (*num > DATA_LINK_M_N_MASK ||
5879 *den > DATA_LINK_M_N_MASK) {
5880 *num >>= 1;
5881 *den >>= 1;
5882 }
5883 }
5884
5885 static void compute_m_n(unsigned int m, unsigned int n,
5886 uint32_t *ret_m, uint32_t *ret_n)
5887 {
5888 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5889 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5890 intel_reduce_m_n_ratio(ret_m, ret_n);
5891 }
5892
5893 void
5894 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5895 int pixel_clock, int link_clock,
5896 struct intel_link_m_n *m_n)
5897 {
5898 m_n->tu = 64;
5899
5900 compute_m_n(bits_per_pixel * pixel_clock,
5901 link_clock * nlanes * 8,
5902 &m_n->gmch_m, &m_n->gmch_n);
5903
5904 compute_m_n(pixel_clock, link_clock,
5905 &m_n->link_m, &m_n->link_n);
5906 }
5907
5908 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5909 {
5910 if (i915.panel_use_ssc >= 0)
5911 return i915.panel_use_ssc != 0;
5912 return dev_priv->vbt.lvds_use_ssc
5913 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5914 }
5915
5916 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5917 {
5918 struct drm_device *dev = crtc->base.dev;
5919 struct drm_i915_private *dev_priv = dev->dev_private;
5920 int refclk;
5921
5922 if (IS_VALLEYVIEW(dev)) {
5923 refclk = 100000;
5924 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5925 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5926 refclk = dev_priv->vbt.lvds_ssc_freq;
5927 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5928 } else if (!IS_GEN2(dev)) {
5929 refclk = 96000;
5930 } else {
5931 refclk = 48000;
5932 }
5933
5934 return refclk;
5935 }
5936
5937 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5938 {
5939 return (1 << dpll->n) << 16 | dpll->m2;
5940 }
5941
5942 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5943 {
5944 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5945 }
5946
5947 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5948 struct intel_crtc_state *crtc_state,
5949 intel_clock_t *reduced_clock)
5950 {
5951 struct drm_device *dev = crtc->base.dev;
5952 u32 fp, fp2 = 0;
5953
5954 if (IS_PINEVIEW(dev)) {
5955 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5956 if (reduced_clock)
5957 fp2 = pnv_dpll_compute_fp(reduced_clock);
5958 } else {
5959 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5960 if (reduced_clock)
5961 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5962 }
5963
5964 crtc_state->dpll_hw_state.fp0 = fp;
5965
5966 crtc->lowfreq_avail = false;
5967 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5968 reduced_clock && i915.powersave) {
5969 crtc_state->dpll_hw_state.fp1 = fp2;
5970 crtc->lowfreq_avail = true;
5971 } else {
5972 crtc_state->dpll_hw_state.fp1 = fp;
5973 }
5974 }
5975
5976 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5977 pipe)
5978 {
5979 u32 reg_val;
5980
5981 /*
5982 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5983 * and set it to a reasonable value instead.
5984 */
5985 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5986 reg_val &= 0xffffff00;
5987 reg_val |= 0x00000030;
5988 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5989
5990 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5991 reg_val &= 0x8cffffff;
5992 reg_val = 0x8c000000;
5993 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5994
5995 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5996 reg_val &= 0xffffff00;
5997 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5998
5999 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6000 reg_val &= 0x00ffffff;
6001 reg_val |= 0xb0000000;
6002 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6003 }
6004
6005 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6006 struct intel_link_m_n *m_n)
6007 {
6008 struct drm_device *dev = crtc->base.dev;
6009 struct drm_i915_private *dev_priv = dev->dev_private;
6010 int pipe = crtc->pipe;
6011
6012 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6013 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6014 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6015 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6016 }
6017
6018 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6019 struct intel_link_m_n *m_n,
6020 struct intel_link_m_n *m2_n2)
6021 {
6022 struct drm_device *dev = crtc->base.dev;
6023 struct drm_i915_private *dev_priv = dev->dev_private;
6024 int pipe = crtc->pipe;
6025 enum transcoder transcoder = crtc->config->cpu_transcoder;
6026
6027 if (INTEL_INFO(dev)->gen >= 5) {
6028 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6029 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6030 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6031 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6032 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6033 * for gen < 8) and if DRRS is supported (to make sure the
6034 * registers are not unnecessarily accessed).
6035 */
6036 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6037 crtc->config->has_drrs) {
6038 I915_WRITE(PIPE_DATA_M2(transcoder),
6039 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6040 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6041 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6042 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6043 }
6044 } else {
6045 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6046 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6047 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6048 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6049 }
6050 }
6051
6052 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6053 {
6054 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6055
6056 if (m_n == M1_N1) {
6057 dp_m_n = &crtc->config->dp_m_n;
6058 dp_m2_n2 = &crtc->config->dp_m2_n2;
6059 } else if (m_n == M2_N2) {
6060
6061 /*
6062 * M2_N2 registers are not supported. Hence m2_n2 divider value
6063 * needs to be programmed into M1_N1.
6064 */
6065 dp_m_n = &crtc->config->dp_m2_n2;
6066 } else {
6067 DRM_ERROR("Unsupported divider value\n");
6068 return;
6069 }
6070
6071 if (crtc->config->has_pch_encoder)
6072 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6073 else
6074 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6075 }
6076
6077 static void vlv_update_pll(struct intel_crtc *crtc,
6078 struct intel_crtc_state *pipe_config)
6079 {
6080 u32 dpll, dpll_md;
6081
6082 /*
6083 * Enable DPIO clock input. We should never disable the reference
6084 * clock for pipe B, since VGA hotplug / manual detection depends
6085 * on it.
6086 */
6087 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6088 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6089 /* We should never disable this, set it here for state tracking */
6090 if (crtc->pipe == PIPE_B)
6091 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6092 dpll |= DPLL_VCO_ENABLE;
6093 pipe_config->dpll_hw_state.dpll = dpll;
6094
6095 dpll_md = (pipe_config->pixel_multiplier - 1)
6096 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6097 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6098 }
6099
6100 static void vlv_prepare_pll(struct intel_crtc *crtc,
6101 const struct intel_crtc_state *pipe_config)
6102 {
6103 struct drm_device *dev = crtc->base.dev;
6104 struct drm_i915_private *dev_priv = dev->dev_private;
6105 int pipe = crtc->pipe;
6106 u32 mdiv;
6107 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6108 u32 coreclk, reg_val;
6109
6110 mutex_lock(&dev_priv->dpio_lock);
6111
6112 bestn = pipe_config->dpll.n;
6113 bestm1 = pipe_config->dpll.m1;
6114 bestm2 = pipe_config->dpll.m2;
6115 bestp1 = pipe_config->dpll.p1;
6116 bestp2 = pipe_config->dpll.p2;
6117
6118 /* See eDP HDMI DPIO driver vbios notes doc */
6119
6120 /* PLL B needs special handling */
6121 if (pipe == PIPE_B)
6122 vlv_pllb_recal_opamp(dev_priv, pipe);
6123
6124 /* Set up Tx target for periodic Rcomp update */
6125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6126
6127 /* Disable target IRef on PLL */
6128 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6129 reg_val &= 0x00ffffff;
6130 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6131
6132 /* Disable fast lock */
6133 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6134
6135 /* Set idtafcrecal before PLL is enabled */
6136 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6137 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6138 mdiv |= ((bestn << DPIO_N_SHIFT));
6139 mdiv |= (1 << DPIO_K_SHIFT);
6140
6141 /*
6142 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6143 * but we don't support that).
6144 * Note: don't use the DAC post divider as it seems unstable.
6145 */
6146 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6147 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6148
6149 mdiv |= DPIO_ENABLE_CALIBRATION;
6150 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6151
6152 /* Set HBR and RBR LPF coefficients */
6153 if (pipe_config->port_clock == 162000 ||
6154 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6155 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6156 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6157 0x009f0003);
6158 else
6159 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6160 0x00d0000f);
6161
6162 if (pipe_config->has_dp_encoder) {
6163 /* Use SSC source */
6164 if (pipe == PIPE_A)
6165 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6166 0x0df40000);
6167 else
6168 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6169 0x0df70000);
6170 } else { /* HDMI or VGA */
6171 /* Use bend source */
6172 if (pipe == PIPE_A)
6173 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6174 0x0df70000);
6175 else
6176 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6177 0x0df40000);
6178 }
6179
6180 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6181 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6182 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6183 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6184 coreclk |= 0x01000000;
6185 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6186
6187 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6188 mutex_unlock(&dev_priv->dpio_lock);
6189 }
6190
6191 static void chv_update_pll(struct intel_crtc *crtc,
6192 struct intel_crtc_state *pipe_config)
6193 {
6194 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6195 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6196 DPLL_VCO_ENABLE;
6197 if (crtc->pipe != PIPE_A)
6198 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6199
6200 pipe_config->dpll_hw_state.dpll_md =
6201 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6202 }
6203
6204 static void chv_prepare_pll(struct intel_crtc *crtc,
6205 const struct intel_crtc_state *pipe_config)
6206 {
6207 struct drm_device *dev = crtc->base.dev;
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209 int pipe = crtc->pipe;
6210 int dpll_reg = DPLL(crtc->pipe);
6211 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6212 u32 loopfilter, tribuf_calcntr;
6213 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6214 u32 dpio_val;
6215 int vco;
6216
6217 bestn = pipe_config->dpll.n;
6218 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6219 bestm1 = pipe_config->dpll.m1;
6220 bestm2 = pipe_config->dpll.m2 >> 22;
6221 bestp1 = pipe_config->dpll.p1;
6222 bestp2 = pipe_config->dpll.p2;
6223 vco = pipe_config->dpll.vco;
6224 dpio_val = 0;
6225 loopfilter = 0;
6226
6227 /*
6228 * Enable Refclk and SSC
6229 */
6230 I915_WRITE(dpll_reg,
6231 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6232
6233 mutex_lock(&dev_priv->dpio_lock);
6234
6235 /* p1 and p2 divider */
6236 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6237 5 << DPIO_CHV_S1_DIV_SHIFT |
6238 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6239 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6240 1 << DPIO_CHV_K_DIV_SHIFT);
6241
6242 /* Feedback post-divider - m2 */
6243 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6244
6245 /* Feedback refclk divider - n and m1 */
6246 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6247 DPIO_CHV_M1_DIV_BY_2 |
6248 1 << DPIO_CHV_N_DIV_SHIFT);
6249
6250 /* M2 fraction division */
6251 if (bestm2_frac)
6252 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6253
6254 /* M2 fraction division enable */
6255 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6256 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6257 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6258 if (bestm2_frac)
6259 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6260 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6261
6262 /* Program digital lock detect threshold */
6263 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6264 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6265 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6266 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6267 if (!bestm2_frac)
6268 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6269 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6270
6271 /* Loop filter */
6272 if (vco == 5400000) {
6273 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6274 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6275 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6276 tribuf_calcntr = 0x9;
6277 } else if (vco <= 6200000) {
6278 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6279 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6280 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6281 tribuf_calcntr = 0x9;
6282 } else if (vco <= 6480000) {
6283 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6284 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6285 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6286 tribuf_calcntr = 0x8;
6287 } else {
6288 /* Not supported. Apply the same limits as in the max case */
6289 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6290 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6291 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6292 tribuf_calcntr = 0;
6293 }
6294 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6295
6296 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6297 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6298 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6299 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6300
6301 /* AFC Recal */
6302 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6303 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6304 DPIO_AFC_RECAL);
6305
6306 mutex_unlock(&dev_priv->dpio_lock);
6307 }
6308
6309 /**
6310 * vlv_force_pll_on - forcibly enable just the PLL
6311 * @dev_priv: i915 private structure
6312 * @pipe: pipe PLL to enable
6313 * @dpll: PLL configuration
6314 *
6315 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6316 * in cases where we need the PLL enabled even when @pipe is not going to
6317 * be enabled.
6318 */
6319 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6320 const struct dpll *dpll)
6321 {
6322 struct intel_crtc *crtc =
6323 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6324 struct intel_crtc_state pipe_config = {
6325 .pixel_multiplier = 1,
6326 .dpll = *dpll,
6327 };
6328
6329 if (IS_CHERRYVIEW(dev)) {
6330 chv_update_pll(crtc, &pipe_config);
6331 chv_prepare_pll(crtc, &pipe_config);
6332 chv_enable_pll(crtc, &pipe_config);
6333 } else {
6334 vlv_update_pll(crtc, &pipe_config);
6335 vlv_prepare_pll(crtc, &pipe_config);
6336 vlv_enable_pll(crtc, &pipe_config);
6337 }
6338 }
6339
6340 /**
6341 * vlv_force_pll_off - forcibly disable just the PLL
6342 * @dev_priv: i915 private structure
6343 * @pipe: pipe PLL to disable
6344 *
6345 * Disable the PLL for @pipe. To be used in cases where we need
6346 * the PLL enabled even when @pipe is not going to be enabled.
6347 */
6348 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6349 {
6350 if (IS_CHERRYVIEW(dev))
6351 chv_disable_pll(to_i915(dev), pipe);
6352 else
6353 vlv_disable_pll(to_i915(dev), pipe);
6354 }
6355
6356 static void i9xx_update_pll(struct intel_crtc *crtc,
6357 struct intel_crtc_state *crtc_state,
6358 intel_clock_t *reduced_clock,
6359 int num_connectors)
6360 {
6361 struct drm_device *dev = crtc->base.dev;
6362 struct drm_i915_private *dev_priv = dev->dev_private;
6363 u32 dpll;
6364 bool is_sdvo;
6365 struct dpll *clock = &crtc_state->dpll;
6366
6367 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6368
6369 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6370 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6371
6372 dpll = DPLL_VGA_MODE_DIS;
6373
6374 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6375 dpll |= DPLLB_MODE_LVDS;
6376 else
6377 dpll |= DPLLB_MODE_DAC_SERIAL;
6378
6379 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6380 dpll |= (crtc_state->pixel_multiplier - 1)
6381 << SDVO_MULTIPLIER_SHIFT_HIRES;
6382 }
6383
6384 if (is_sdvo)
6385 dpll |= DPLL_SDVO_HIGH_SPEED;
6386
6387 if (crtc_state->has_dp_encoder)
6388 dpll |= DPLL_SDVO_HIGH_SPEED;
6389
6390 /* compute bitmask from p1 value */
6391 if (IS_PINEVIEW(dev))
6392 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6393 else {
6394 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6395 if (IS_G4X(dev) && reduced_clock)
6396 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6397 }
6398 switch (clock->p2) {
6399 case 5:
6400 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6401 break;
6402 case 7:
6403 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6404 break;
6405 case 10:
6406 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6407 break;
6408 case 14:
6409 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6410 break;
6411 }
6412 if (INTEL_INFO(dev)->gen >= 4)
6413 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6414
6415 if (crtc_state->sdvo_tv_clock)
6416 dpll |= PLL_REF_INPUT_TVCLKINBC;
6417 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6418 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6419 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6420 else
6421 dpll |= PLL_REF_INPUT_DREFCLK;
6422
6423 dpll |= DPLL_VCO_ENABLE;
6424 crtc_state->dpll_hw_state.dpll = dpll;
6425
6426 if (INTEL_INFO(dev)->gen >= 4) {
6427 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6428 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6429 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6430 }
6431 }
6432
6433 static void i8xx_update_pll(struct intel_crtc *crtc,
6434 struct intel_crtc_state *crtc_state,
6435 intel_clock_t *reduced_clock,
6436 int num_connectors)
6437 {
6438 struct drm_device *dev = crtc->base.dev;
6439 struct drm_i915_private *dev_priv = dev->dev_private;
6440 u32 dpll;
6441 struct dpll *clock = &crtc_state->dpll;
6442
6443 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6444
6445 dpll = DPLL_VGA_MODE_DIS;
6446
6447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6448 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6449 } else {
6450 if (clock->p1 == 2)
6451 dpll |= PLL_P1_DIVIDE_BY_TWO;
6452 else
6453 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6454 if (clock->p2 == 4)
6455 dpll |= PLL_P2_DIVIDE_BY_4;
6456 }
6457
6458 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6459 dpll |= DPLL_DVO_2X_MODE;
6460
6461 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6462 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6463 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6464 else
6465 dpll |= PLL_REF_INPUT_DREFCLK;
6466
6467 dpll |= DPLL_VCO_ENABLE;
6468 crtc_state->dpll_hw_state.dpll = dpll;
6469 }
6470
6471 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6472 {
6473 struct drm_device *dev = intel_crtc->base.dev;
6474 struct drm_i915_private *dev_priv = dev->dev_private;
6475 enum pipe pipe = intel_crtc->pipe;
6476 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6477 struct drm_display_mode *adjusted_mode =
6478 &intel_crtc->config->base.adjusted_mode;
6479 uint32_t crtc_vtotal, crtc_vblank_end;
6480 int vsyncshift = 0;
6481
6482 /* We need to be careful not to changed the adjusted mode, for otherwise
6483 * the hw state checker will get angry at the mismatch. */
6484 crtc_vtotal = adjusted_mode->crtc_vtotal;
6485 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6486
6487 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6488 /* the chip adds 2 halflines automatically */
6489 crtc_vtotal -= 1;
6490 crtc_vblank_end -= 1;
6491
6492 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6493 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6494 else
6495 vsyncshift = adjusted_mode->crtc_hsync_start -
6496 adjusted_mode->crtc_htotal / 2;
6497 if (vsyncshift < 0)
6498 vsyncshift += adjusted_mode->crtc_htotal;
6499 }
6500
6501 if (INTEL_INFO(dev)->gen > 3)
6502 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6503
6504 I915_WRITE(HTOTAL(cpu_transcoder),
6505 (adjusted_mode->crtc_hdisplay - 1) |
6506 ((adjusted_mode->crtc_htotal - 1) << 16));
6507 I915_WRITE(HBLANK(cpu_transcoder),
6508 (adjusted_mode->crtc_hblank_start - 1) |
6509 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6510 I915_WRITE(HSYNC(cpu_transcoder),
6511 (adjusted_mode->crtc_hsync_start - 1) |
6512 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6513
6514 I915_WRITE(VTOTAL(cpu_transcoder),
6515 (adjusted_mode->crtc_vdisplay - 1) |
6516 ((crtc_vtotal - 1) << 16));
6517 I915_WRITE(VBLANK(cpu_transcoder),
6518 (adjusted_mode->crtc_vblank_start - 1) |
6519 ((crtc_vblank_end - 1) << 16));
6520 I915_WRITE(VSYNC(cpu_transcoder),
6521 (adjusted_mode->crtc_vsync_start - 1) |
6522 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6523
6524 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6525 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6526 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6527 * bits. */
6528 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6529 (pipe == PIPE_B || pipe == PIPE_C))
6530 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6531
6532 /* pipesrc controls the size that is scaled from, which should
6533 * always be the user's requested size.
6534 */
6535 I915_WRITE(PIPESRC(pipe),
6536 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6537 (intel_crtc->config->pipe_src_h - 1));
6538 }
6539
6540 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6541 struct intel_crtc_state *pipe_config)
6542 {
6543 struct drm_device *dev = crtc->base.dev;
6544 struct drm_i915_private *dev_priv = dev->dev_private;
6545 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6546 uint32_t tmp;
6547
6548 tmp = I915_READ(HTOTAL(cpu_transcoder));
6549 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6550 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6551 tmp = I915_READ(HBLANK(cpu_transcoder));
6552 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6553 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6554 tmp = I915_READ(HSYNC(cpu_transcoder));
6555 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6556 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6557
6558 tmp = I915_READ(VTOTAL(cpu_transcoder));
6559 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6560 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6561 tmp = I915_READ(VBLANK(cpu_transcoder));
6562 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6563 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6564 tmp = I915_READ(VSYNC(cpu_transcoder));
6565 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6566 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6567
6568 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6569 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6570 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6571 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6572 }
6573
6574 tmp = I915_READ(PIPESRC(crtc->pipe));
6575 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6576 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6577
6578 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6579 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6580 }
6581
6582 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6583 struct intel_crtc_state *pipe_config)
6584 {
6585 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6586 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6587 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6588 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6589
6590 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6591 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6592 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6593 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6594
6595 mode->flags = pipe_config->base.adjusted_mode.flags;
6596
6597 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6598 mode->flags |= pipe_config->base.adjusted_mode.flags;
6599 }
6600
6601 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6602 {
6603 struct drm_device *dev = intel_crtc->base.dev;
6604 struct drm_i915_private *dev_priv = dev->dev_private;
6605 uint32_t pipeconf;
6606
6607 pipeconf = 0;
6608
6609 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6610 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6611 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6612
6613 if (intel_crtc->config->double_wide)
6614 pipeconf |= PIPECONF_DOUBLE_WIDE;
6615
6616 /* only g4x and later have fancy bpc/dither controls */
6617 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6618 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6619 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6620 pipeconf |= PIPECONF_DITHER_EN |
6621 PIPECONF_DITHER_TYPE_SP;
6622
6623 switch (intel_crtc->config->pipe_bpp) {
6624 case 18:
6625 pipeconf |= PIPECONF_6BPC;
6626 break;
6627 case 24:
6628 pipeconf |= PIPECONF_8BPC;
6629 break;
6630 case 30:
6631 pipeconf |= PIPECONF_10BPC;
6632 break;
6633 default:
6634 /* Case prevented by intel_choose_pipe_bpp_dither. */
6635 BUG();
6636 }
6637 }
6638
6639 if (HAS_PIPE_CXSR(dev)) {
6640 if (intel_crtc->lowfreq_avail) {
6641 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6642 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6643 } else {
6644 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6645 }
6646 }
6647
6648 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6649 if (INTEL_INFO(dev)->gen < 4 ||
6650 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6651 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6652 else
6653 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6654 } else
6655 pipeconf |= PIPECONF_PROGRESSIVE;
6656
6657 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6658 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6659
6660 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6661 POSTING_READ(PIPECONF(intel_crtc->pipe));
6662 }
6663
6664 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6665 struct intel_crtc_state *crtc_state)
6666 {
6667 struct drm_device *dev = crtc->base.dev;
6668 struct drm_i915_private *dev_priv = dev->dev_private;
6669 int refclk, num_connectors = 0;
6670 intel_clock_t clock, reduced_clock;
6671 bool ok, has_reduced_clock = false;
6672 bool is_lvds = false, is_dsi = false;
6673 struct intel_encoder *encoder;
6674 const intel_limit_t *limit;
6675
6676 for_each_intel_encoder(dev, encoder) {
6677 if (encoder->new_crtc != crtc)
6678 continue;
6679
6680 switch (encoder->type) {
6681 case INTEL_OUTPUT_LVDS:
6682 is_lvds = true;
6683 break;
6684 case INTEL_OUTPUT_DSI:
6685 is_dsi = true;
6686 break;
6687 default:
6688 break;
6689 }
6690
6691 num_connectors++;
6692 }
6693
6694 if (is_dsi)
6695 return 0;
6696
6697 if (!crtc_state->clock_set) {
6698 refclk = i9xx_get_refclk(crtc, num_connectors);
6699
6700 /*
6701 * Returns a set of divisors for the desired target clock with
6702 * the given refclk, or FALSE. The returned values represent
6703 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6704 * 2) / p1 / p2.
6705 */
6706 limit = intel_limit(crtc, refclk);
6707 ok = dev_priv->display.find_dpll(limit, crtc,
6708 crtc_state->port_clock,
6709 refclk, NULL, &clock);
6710 if (!ok) {
6711 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6712 return -EINVAL;
6713 }
6714
6715 if (is_lvds && dev_priv->lvds_downclock_avail) {
6716 /*
6717 * Ensure we match the reduced clock's P to the target
6718 * clock. If the clocks don't match, we can't switch
6719 * the display clock by using the FP0/FP1. In such case
6720 * we will disable the LVDS downclock feature.
6721 */
6722 has_reduced_clock =
6723 dev_priv->display.find_dpll(limit, crtc,
6724 dev_priv->lvds_downclock,
6725 refclk, &clock,
6726 &reduced_clock);
6727 }
6728 /* Compat-code for transition, will disappear. */
6729 crtc_state->dpll.n = clock.n;
6730 crtc_state->dpll.m1 = clock.m1;
6731 crtc_state->dpll.m2 = clock.m2;
6732 crtc_state->dpll.p1 = clock.p1;
6733 crtc_state->dpll.p2 = clock.p2;
6734 }
6735
6736 if (IS_GEN2(dev)) {
6737 i8xx_update_pll(crtc, crtc_state,
6738 has_reduced_clock ? &reduced_clock : NULL,
6739 num_connectors);
6740 } else if (IS_CHERRYVIEW(dev)) {
6741 chv_update_pll(crtc, crtc_state);
6742 } else if (IS_VALLEYVIEW(dev)) {
6743 vlv_update_pll(crtc, crtc_state);
6744 } else {
6745 i9xx_update_pll(crtc, crtc_state,
6746 has_reduced_clock ? &reduced_clock : NULL,
6747 num_connectors);
6748 }
6749
6750 return 0;
6751 }
6752
6753 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6754 struct intel_crtc_state *pipe_config)
6755 {
6756 struct drm_device *dev = crtc->base.dev;
6757 struct drm_i915_private *dev_priv = dev->dev_private;
6758 uint32_t tmp;
6759
6760 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6761 return;
6762
6763 tmp = I915_READ(PFIT_CONTROL);
6764 if (!(tmp & PFIT_ENABLE))
6765 return;
6766
6767 /* Check whether the pfit is attached to our pipe. */
6768 if (INTEL_INFO(dev)->gen < 4) {
6769 if (crtc->pipe != PIPE_B)
6770 return;
6771 } else {
6772 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6773 return;
6774 }
6775
6776 pipe_config->gmch_pfit.control = tmp;
6777 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6778 if (INTEL_INFO(dev)->gen < 5)
6779 pipe_config->gmch_pfit.lvds_border_bits =
6780 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6781 }
6782
6783 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6784 struct intel_crtc_state *pipe_config)
6785 {
6786 struct drm_device *dev = crtc->base.dev;
6787 struct drm_i915_private *dev_priv = dev->dev_private;
6788 int pipe = pipe_config->cpu_transcoder;
6789 intel_clock_t clock;
6790 u32 mdiv;
6791 int refclk = 100000;
6792
6793 /* In case of MIPI DPLL will not even be used */
6794 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6795 return;
6796
6797 mutex_lock(&dev_priv->dpio_lock);
6798 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6799 mutex_unlock(&dev_priv->dpio_lock);
6800
6801 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6802 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6803 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6804 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6805 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6806
6807 vlv_clock(refclk, &clock);
6808
6809 /* clock.dot is the fast clock */
6810 pipe_config->port_clock = clock.dot / 5;
6811 }
6812
6813 static void
6814 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6815 struct intel_initial_plane_config *plane_config)
6816 {
6817 struct drm_device *dev = crtc->base.dev;
6818 struct drm_i915_private *dev_priv = dev->dev_private;
6819 u32 val, base, offset;
6820 int pipe = crtc->pipe, plane = crtc->plane;
6821 int fourcc, pixel_format;
6822 unsigned int aligned_height;
6823 struct drm_framebuffer *fb;
6824 struct intel_framebuffer *intel_fb;
6825
6826 val = I915_READ(DSPCNTR(plane));
6827 if (!(val & DISPLAY_PLANE_ENABLE))
6828 return;
6829
6830 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6831 if (!intel_fb) {
6832 DRM_DEBUG_KMS("failed to alloc fb\n");
6833 return;
6834 }
6835
6836 fb = &intel_fb->base;
6837
6838 if (INTEL_INFO(dev)->gen >= 4) {
6839 if (val & DISPPLANE_TILED) {
6840 plane_config->tiling = I915_TILING_X;
6841 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6842 }
6843 }
6844
6845 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6846 fourcc = i9xx_format_to_fourcc(pixel_format);
6847 fb->pixel_format = fourcc;
6848 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6849
6850 if (INTEL_INFO(dev)->gen >= 4) {
6851 if (plane_config->tiling)
6852 offset = I915_READ(DSPTILEOFF(plane));
6853 else
6854 offset = I915_READ(DSPLINOFF(plane));
6855 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6856 } else {
6857 base = I915_READ(DSPADDR(plane));
6858 }
6859 plane_config->base = base;
6860
6861 val = I915_READ(PIPESRC(pipe));
6862 fb->width = ((val >> 16) & 0xfff) + 1;
6863 fb->height = ((val >> 0) & 0xfff) + 1;
6864
6865 val = I915_READ(DSPSTRIDE(pipe));
6866 fb->pitches[0] = val & 0xffffffc0;
6867
6868 aligned_height = intel_fb_align_height(dev, fb->height,
6869 fb->pixel_format,
6870 fb->modifier[0]);
6871
6872 plane_config->size = fb->pitches[0] * aligned_height;
6873
6874 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6875 pipe_name(pipe), plane, fb->width, fb->height,
6876 fb->bits_per_pixel, base, fb->pitches[0],
6877 plane_config->size);
6878
6879 plane_config->fb = intel_fb;
6880 }
6881
6882 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6883 struct intel_crtc_state *pipe_config)
6884 {
6885 struct drm_device *dev = crtc->base.dev;
6886 struct drm_i915_private *dev_priv = dev->dev_private;
6887 int pipe = pipe_config->cpu_transcoder;
6888 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6889 intel_clock_t clock;
6890 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6891 int refclk = 100000;
6892
6893 mutex_lock(&dev_priv->dpio_lock);
6894 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6895 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6896 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6897 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6898 mutex_unlock(&dev_priv->dpio_lock);
6899
6900 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6901 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6902 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6903 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6904 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6905
6906 chv_clock(refclk, &clock);
6907
6908 /* clock.dot is the fast clock */
6909 pipe_config->port_clock = clock.dot / 5;
6910 }
6911
6912 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6913 struct intel_crtc_state *pipe_config)
6914 {
6915 struct drm_device *dev = crtc->base.dev;
6916 struct drm_i915_private *dev_priv = dev->dev_private;
6917 uint32_t tmp;
6918
6919 if (!intel_display_power_is_enabled(dev_priv,
6920 POWER_DOMAIN_PIPE(crtc->pipe)))
6921 return false;
6922
6923 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6924 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6925
6926 tmp = I915_READ(PIPECONF(crtc->pipe));
6927 if (!(tmp & PIPECONF_ENABLE))
6928 return false;
6929
6930 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6931 switch (tmp & PIPECONF_BPC_MASK) {
6932 case PIPECONF_6BPC:
6933 pipe_config->pipe_bpp = 18;
6934 break;
6935 case PIPECONF_8BPC:
6936 pipe_config->pipe_bpp = 24;
6937 break;
6938 case PIPECONF_10BPC:
6939 pipe_config->pipe_bpp = 30;
6940 break;
6941 default:
6942 break;
6943 }
6944 }
6945
6946 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6947 pipe_config->limited_color_range = true;
6948
6949 if (INTEL_INFO(dev)->gen < 4)
6950 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6951
6952 intel_get_pipe_timings(crtc, pipe_config);
6953
6954 i9xx_get_pfit_config(crtc, pipe_config);
6955
6956 if (INTEL_INFO(dev)->gen >= 4) {
6957 tmp = I915_READ(DPLL_MD(crtc->pipe));
6958 pipe_config->pixel_multiplier =
6959 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6960 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6961 pipe_config->dpll_hw_state.dpll_md = tmp;
6962 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6963 tmp = I915_READ(DPLL(crtc->pipe));
6964 pipe_config->pixel_multiplier =
6965 ((tmp & SDVO_MULTIPLIER_MASK)
6966 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6967 } else {
6968 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6969 * port and will be fixed up in the encoder->get_config
6970 * function. */
6971 pipe_config->pixel_multiplier = 1;
6972 }
6973 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6974 if (!IS_VALLEYVIEW(dev)) {
6975 /*
6976 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6977 * on 830. Filter it out here so that we don't
6978 * report errors due to that.
6979 */
6980 if (IS_I830(dev))
6981 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6982
6983 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6984 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6985 } else {
6986 /* Mask out read-only status bits. */
6987 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6988 DPLL_PORTC_READY_MASK |
6989 DPLL_PORTB_READY_MASK);
6990 }
6991
6992 if (IS_CHERRYVIEW(dev))
6993 chv_crtc_clock_get(crtc, pipe_config);
6994 else if (IS_VALLEYVIEW(dev))
6995 vlv_crtc_clock_get(crtc, pipe_config);
6996 else
6997 i9xx_crtc_clock_get(crtc, pipe_config);
6998
6999 return true;
7000 }
7001
7002 static void ironlake_init_pch_refclk(struct drm_device *dev)
7003 {
7004 struct drm_i915_private *dev_priv = dev->dev_private;
7005 struct intel_encoder *encoder;
7006 u32 val, final;
7007 bool has_lvds = false;
7008 bool has_cpu_edp = false;
7009 bool has_panel = false;
7010 bool has_ck505 = false;
7011 bool can_ssc = false;
7012
7013 /* We need to take the global config into account */
7014 for_each_intel_encoder(dev, encoder) {
7015 switch (encoder->type) {
7016 case INTEL_OUTPUT_LVDS:
7017 has_panel = true;
7018 has_lvds = true;
7019 break;
7020 case INTEL_OUTPUT_EDP:
7021 has_panel = true;
7022 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7023 has_cpu_edp = true;
7024 break;
7025 default:
7026 break;
7027 }
7028 }
7029
7030 if (HAS_PCH_IBX(dev)) {
7031 has_ck505 = dev_priv->vbt.display_clock_mode;
7032 can_ssc = has_ck505;
7033 } else {
7034 has_ck505 = false;
7035 can_ssc = true;
7036 }
7037
7038 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7039 has_panel, has_lvds, has_ck505);
7040
7041 /* Ironlake: try to setup display ref clock before DPLL
7042 * enabling. This is only under driver's control after
7043 * PCH B stepping, previous chipset stepping should be
7044 * ignoring this setting.
7045 */
7046 val = I915_READ(PCH_DREF_CONTROL);
7047
7048 /* As we must carefully and slowly disable/enable each source in turn,
7049 * compute the final state we want first and check if we need to
7050 * make any changes at all.
7051 */
7052 final = val;
7053 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7054 if (has_ck505)
7055 final |= DREF_NONSPREAD_CK505_ENABLE;
7056 else
7057 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7058
7059 final &= ~DREF_SSC_SOURCE_MASK;
7060 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7061 final &= ~DREF_SSC1_ENABLE;
7062
7063 if (has_panel) {
7064 final |= DREF_SSC_SOURCE_ENABLE;
7065
7066 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7067 final |= DREF_SSC1_ENABLE;
7068
7069 if (has_cpu_edp) {
7070 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7071 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7072 else
7073 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7074 } else
7075 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7076 } else {
7077 final |= DREF_SSC_SOURCE_DISABLE;
7078 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7079 }
7080
7081 if (final == val)
7082 return;
7083
7084 /* Always enable nonspread source */
7085 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7086
7087 if (has_ck505)
7088 val |= DREF_NONSPREAD_CK505_ENABLE;
7089 else
7090 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7091
7092 if (has_panel) {
7093 val &= ~DREF_SSC_SOURCE_MASK;
7094 val |= DREF_SSC_SOURCE_ENABLE;
7095
7096 /* SSC must be turned on before enabling the CPU output */
7097 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7098 DRM_DEBUG_KMS("Using SSC on panel\n");
7099 val |= DREF_SSC1_ENABLE;
7100 } else
7101 val &= ~DREF_SSC1_ENABLE;
7102
7103 /* Get SSC going before enabling the outputs */
7104 I915_WRITE(PCH_DREF_CONTROL, val);
7105 POSTING_READ(PCH_DREF_CONTROL);
7106 udelay(200);
7107
7108 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7109
7110 /* Enable CPU source on CPU attached eDP */
7111 if (has_cpu_edp) {
7112 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7113 DRM_DEBUG_KMS("Using SSC on eDP\n");
7114 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7115 } else
7116 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7117 } else
7118 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7119
7120 I915_WRITE(PCH_DREF_CONTROL, val);
7121 POSTING_READ(PCH_DREF_CONTROL);
7122 udelay(200);
7123 } else {
7124 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7125
7126 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7127
7128 /* Turn off CPU output */
7129 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7130
7131 I915_WRITE(PCH_DREF_CONTROL, val);
7132 POSTING_READ(PCH_DREF_CONTROL);
7133 udelay(200);
7134
7135 /* Turn off the SSC source */
7136 val &= ~DREF_SSC_SOURCE_MASK;
7137 val |= DREF_SSC_SOURCE_DISABLE;
7138
7139 /* Turn off SSC1 */
7140 val &= ~DREF_SSC1_ENABLE;
7141
7142 I915_WRITE(PCH_DREF_CONTROL, val);
7143 POSTING_READ(PCH_DREF_CONTROL);
7144 udelay(200);
7145 }
7146
7147 BUG_ON(val != final);
7148 }
7149
7150 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7151 {
7152 uint32_t tmp;
7153
7154 tmp = I915_READ(SOUTH_CHICKEN2);
7155 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7156 I915_WRITE(SOUTH_CHICKEN2, tmp);
7157
7158 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7159 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7160 DRM_ERROR("FDI mPHY reset assert timeout\n");
7161
7162 tmp = I915_READ(SOUTH_CHICKEN2);
7163 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7164 I915_WRITE(SOUTH_CHICKEN2, tmp);
7165
7166 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7167 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7168 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7169 }
7170
7171 /* WaMPhyProgramming:hsw */
7172 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7173 {
7174 uint32_t tmp;
7175
7176 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7177 tmp &= ~(0xFF << 24);
7178 tmp |= (0x12 << 24);
7179 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7180
7181 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7182 tmp |= (1 << 11);
7183 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7184
7185 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7186 tmp |= (1 << 11);
7187 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7188
7189 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7190 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7191 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7192
7193 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7194 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7195 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7196
7197 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7198 tmp &= ~(7 << 13);
7199 tmp |= (5 << 13);
7200 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7201
7202 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7203 tmp &= ~(7 << 13);
7204 tmp |= (5 << 13);
7205 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7206
7207 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7208 tmp &= ~0xFF;
7209 tmp |= 0x1C;
7210 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7211
7212 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7213 tmp &= ~0xFF;
7214 tmp |= 0x1C;
7215 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7216
7217 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7218 tmp &= ~(0xFF << 16);
7219 tmp |= (0x1C << 16);
7220 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7221
7222 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7223 tmp &= ~(0xFF << 16);
7224 tmp |= (0x1C << 16);
7225 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7226
7227 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7228 tmp |= (1 << 27);
7229 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7230
7231 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7232 tmp |= (1 << 27);
7233 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7234
7235 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7236 tmp &= ~(0xF << 28);
7237 tmp |= (4 << 28);
7238 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7239
7240 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7241 tmp &= ~(0xF << 28);
7242 tmp |= (4 << 28);
7243 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7244 }
7245
7246 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7247 * Programming" based on the parameters passed:
7248 * - Sequence to enable CLKOUT_DP
7249 * - Sequence to enable CLKOUT_DP without spread
7250 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7251 */
7252 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7253 bool with_fdi)
7254 {
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256 uint32_t reg, tmp;
7257
7258 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7259 with_spread = true;
7260 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7261 with_fdi, "LP PCH doesn't have FDI\n"))
7262 with_fdi = false;
7263
7264 mutex_lock(&dev_priv->dpio_lock);
7265
7266 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7267 tmp &= ~SBI_SSCCTL_DISABLE;
7268 tmp |= SBI_SSCCTL_PATHALT;
7269 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7270
7271 udelay(24);
7272
7273 if (with_spread) {
7274 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7275 tmp &= ~SBI_SSCCTL_PATHALT;
7276 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7277
7278 if (with_fdi) {
7279 lpt_reset_fdi_mphy(dev_priv);
7280 lpt_program_fdi_mphy(dev_priv);
7281 }
7282 }
7283
7284 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7285 SBI_GEN0 : SBI_DBUFF0;
7286 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7287 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7288 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7289
7290 mutex_unlock(&dev_priv->dpio_lock);
7291 }
7292
7293 /* Sequence to disable CLKOUT_DP */
7294 static void lpt_disable_clkout_dp(struct drm_device *dev)
7295 {
7296 struct drm_i915_private *dev_priv = dev->dev_private;
7297 uint32_t reg, tmp;
7298
7299 mutex_lock(&dev_priv->dpio_lock);
7300
7301 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7302 SBI_GEN0 : SBI_DBUFF0;
7303 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7304 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7305 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7306
7307 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7308 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7309 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7310 tmp |= SBI_SSCCTL_PATHALT;
7311 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7312 udelay(32);
7313 }
7314 tmp |= SBI_SSCCTL_DISABLE;
7315 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7316 }
7317
7318 mutex_unlock(&dev_priv->dpio_lock);
7319 }
7320
7321 static void lpt_init_pch_refclk(struct drm_device *dev)
7322 {
7323 struct intel_encoder *encoder;
7324 bool has_vga = false;
7325
7326 for_each_intel_encoder(dev, encoder) {
7327 switch (encoder->type) {
7328 case INTEL_OUTPUT_ANALOG:
7329 has_vga = true;
7330 break;
7331 default:
7332 break;
7333 }
7334 }
7335
7336 if (has_vga)
7337 lpt_enable_clkout_dp(dev, true, true);
7338 else
7339 lpt_disable_clkout_dp(dev);
7340 }
7341
7342 /*
7343 * Initialize reference clocks when the driver loads
7344 */
7345 void intel_init_pch_refclk(struct drm_device *dev)
7346 {
7347 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7348 ironlake_init_pch_refclk(dev);
7349 else if (HAS_PCH_LPT(dev))
7350 lpt_init_pch_refclk(dev);
7351 }
7352
7353 static int ironlake_get_refclk(struct drm_crtc *crtc)
7354 {
7355 struct drm_device *dev = crtc->dev;
7356 struct drm_i915_private *dev_priv = dev->dev_private;
7357 struct intel_encoder *encoder;
7358 int num_connectors = 0;
7359 bool is_lvds = false;
7360
7361 for_each_intel_encoder(dev, encoder) {
7362 if (encoder->new_crtc != to_intel_crtc(crtc))
7363 continue;
7364
7365 switch (encoder->type) {
7366 case INTEL_OUTPUT_LVDS:
7367 is_lvds = true;
7368 break;
7369 default:
7370 break;
7371 }
7372 num_connectors++;
7373 }
7374
7375 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7376 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7377 dev_priv->vbt.lvds_ssc_freq);
7378 return dev_priv->vbt.lvds_ssc_freq;
7379 }
7380
7381 return 120000;
7382 }
7383
7384 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7385 {
7386 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7388 int pipe = intel_crtc->pipe;
7389 uint32_t val;
7390
7391 val = 0;
7392
7393 switch (intel_crtc->config->pipe_bpp) {
7394 case 18:
7395 val |= PIPECONF_6BPC;
7396 break;
7397 case 24:
7398 val |= PIPECONF_8BPC;
7399 break;
7400 case 30:
7401 val |= PIPECONF_10BPC;
7402 break;
7403 case 36:
7404 val |= PIPECONF_12BPC;
7405 break;
7406 default:
7407 /* Case prevented by intel_choose_pipe_bpp_dither. */
7408 BUG();
7409 }
7410
7411 if (intel_crtc->config->dither)
7412 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7413
7414 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7415 val |= PIPECONF_INTERLACED_ILK;
7416 else
7417 val |= PIPECONF_PROGRESSIVE;
7418
7419 if (intel_crtc->config->limited_color_range)
7420 val |= PIPECONF_COLOR_RANGE_SELECT;
7421
7422 I915_WRITE(PIPECONF(pipe), val);
7423 POSTING_READ(PIPECONF(pipe));
7424 }
7425
7426 /*
7427 * Set up the pipe CSC unit.
7428 *
7429 * Currently only full range RGB to limited range RGB conversion
7430 * is supported, but eventually this should handle various
7431 * RGB<->YCbCr scenarios as well.
7432 */
7433 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7434 {
7435 struct drm_device *dev = crtc->dev;
7436 struct drm_i915_private *dev_priv = dev->dev_private;
7437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7438 int pipe = intel_crtc->pipe;
7439 uint16_t coeff = 0x7800; /* 1.0 */
7440
7441 /*
7442 * TODO: Check what kind of values actually come out of the pipe
7443 * with these coeff/postoff values and adjust to get the best
7444 * accuracy. Perhaps we even need to take the bpc value into
7445 * consideration.
7446 */
7447
7448 if (intel_crtc->config->limited_color_range)
7449 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7450
7451 /*
7452 * GY/GU and RY/RU should be the other way around according
7453 * to BSpec, but reality doesn't agree. Just set them up in
7454 * a way that results in the correct picture.
7455 */
7456 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7457 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7458
7459 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7460 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7461
7462 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7463 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7464
7465 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7466 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7467 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7468
7469 if (INTEL_INFO(dev)->gen > 6) {
7470 uint16_t postoff = 0;
7471
7472 if (intel_crtc->config->limited_color_range)
7473 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7474
7475 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7476 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7477 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7478
7479 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7480 } else {
7481 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7482
7483 if (intel_crtc->config->limited_color_range)
7484 mode |= CSC_BLACK_SCREEN_OFFSET;
7485
7486 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7487 }
7488 }
7489
7490 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7491 {
7492 struct drm_device *dev = crtc->dev;
7493 struct drm_i915_private *dev_priv = dev->dev_private;
7494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7495 enum pipe pipe = intel_crtc->pipe;
7496 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7497 uint32_t val;
7498
7499 val = 0;
7500
7501 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7502 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7503
7504 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7505 val |= PIPECONF_INTERLACED_ILK;
7506 else
7507 val |= PIPECONF_PROGRESSIVE;
7508
7509 I915_WRITE(PIPECONF(cpu_transcoder), val);
7510 POSTING_READ(PIPECONF(cpu_transcoder));
7511
7512 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7513 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7514
7515 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7516 val = 0;
7517
7518 switch (intel_crtc->config->pipe_bpp) {
7519 case 18:
7520 val |= PIPEMISC_DITHER_6_BPC;
7521 break;
7522 case 24:
7523 val |= PIPEMISC_DITHER_8_BPC;
7524 break;
7525 case 30:
7526 val |= PIPEMISC_DITHER_10_BPC;
7527 break;
7528 case 36:
7529 val |= PIPEMISC_DITHER_12_BPC;
7530 break;
7531 default:
7532 /* Case prevented by pipe_config_set_bpp. */
7533 BUG();
7534 }
7535
7536 if (intel_crtc->config->dither)
7537 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7538
7539 I915_WRITE(PIPEMISC(pipe), val);
7540 }
7541 }
7542
7543 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7544 struct intel_crtc_state *crtc_state,
7545 intel_clock_t *clock,
7546 bool *has_reduced_clock,
7547 intel_clock_t *reduced_clock)
7548 {
7549 struct drm_device *dev = crtc->dev;
7550 struct drm_i915_private *dev_priv = dev->dev_private;
7551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7552 int refclk;
7553 const intel_limit_t *limit;
7554 bool ret, is_lvds = false;
7555
7556 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7557
7558 refclk = ironlake_get_refclk(crtc);
7559
7560 /*
7561 * Returns a set of divisors for the desired target clock with the given
7562 * refclk, or FALSE. The returned values represent the clock equation:
7563 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7564 */
7565 limit = intel_limit(intel_crtc, refclk);
7566 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7567 crtc_state->port_clock,
7568 refclk, NULL, clock);
7569 if (!ret)
7570 return false;
7571
7572 if (is_lvds && dev_priv->lvds_downclock_avail) {
7573 /*
7574 * Ensure we match the reduced clock's P to the target clock.
7575 * If the clocks don't match, we can't switch the display clock
7576 * by using the FP0/FP1. In such case we will disable the LVDS
7577 * downclock feature.
7578 */
7579 *has_reduced_clock =
7580 dev_priv->display.find_dpll(limit, intel_crtc,
7581 dev_priv->lvds_downclock,
7582 refclk, clock,
7583 reduced_clock);
7584 }
7585
7586 return true;
7587 }
7588
7589 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7590 {
7591 /*
7592 * Account for spread spectrum to avoid
7593 * oversubscribing the link. Max center spread
7594 * is 2.5%; use 5% for safety's sake.
7595 */
7596 u32 bps = target_clock * bpp * 21 / 20;
7597 return DIV_ROUND_UP(bps, link_bw * 8);
7598 }
7599
7600 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7601 {
7602 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7603 }
7604
7605 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7606 struct intel_crtc_state *crtc_state,
7607 u32 *fp,
7608 intel_clock_t *reduced_clock, u32 *fp2)
7609 {
7610 struct drm_crtc *crtc = &intel_crtc->base;
7611 struct drm_device *dev = crtc->dev;
7612 struct drm_i915_private *dev_priv = dev->dev_private;
7613 struct intel_encoder *intel_encoder;
7614 uint32_t dpll;
7615 int factor, num_connectors = 0;
7616 bool is_lvds = false, is_sdvo = false;
7617
7618 for_each_intel_encoder(dev, intel_encoder) {
7619 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7620 continue;
7621
7622 switch (intel_encoder->type) {
7623 case INTEL_OUTPUT_LVDS:
7624 is_lvds = true;
7625 break;
7626 case INTEL_OUTPUT_SDVO:
7627 case INTEL_OUTPUT_HDMI:
7628 is_sdvo = true;
7629 break;
7630 default:
7631 break;
7632 }
7633
7634 num_connectors++;
7635 }
7636
7637 /* Enable autotuning of the PLL clock (if permissible) */
7638 factor = 21;
7639 if (is_lvds) {
7640 if ((intel_panel_use_ssc(dev_priv) &&
7641 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7642 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7643 factor = 25;
7644 } else if (crtc_state->sdvo_tv_clock)
7645 factor = 20;
7646
7647 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7648 *fp |= FP_CB_TUNE;
7649
7650 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7651 *fp2 |= FP_CB_TUNE;
7652
7653 dpll = 0;
7654
7655 if (is_lvds)
7656 dpll |= DPLLB_MODE_LVDS;
7657 else
7658 dpll |= DPLLB_MODE_DAC_SERIAL;
7659
7660 dpll |= (crtc_state->pixel_multiplier - 1)
7661 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7662
7663 if (is_sdvo)
7664 dpll |= DPLL_SDVO_HIGH_SPEED;
7665 if (crtc_state->has_dp_encoder)
7666 dpll |= DPLL_SDVO_HIGH_SPEED;
7667
7668 /* compute bitmask from p1 value */
7669 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7670 /* also FPA1 */
7671 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7672
7673 switch (crtc_state->dpll.p2) {
7674 case 5:
7675 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7676 break;
7677 case 7:
7678 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7679 break;
7680 case 10:
7681 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7682 break;
7683 case 14:
7684 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7685 break;
7686 }
7687
7688 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7689 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7690 else
7691 dpll |= PLL_REF_INPUT_DREFCLK;
7692
7693 return dpll | DPLL_VCO_ENABLE;
7694 }
7695
7696 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7697 struct intel_crtc_state *crtc_state)
7698 {
7699 struct drm_device *dev = crtc->base.dev;
7700 intel_clock_t clock, reduced_clock;
7701 u32 dpll = 0, fp = 0, fp2 = 0;
7702 bool ok, has_reduced_clock = false;
7703 bool is_lvds = false;
7704 struct intel_shared_dpll *pll;
7705
7706 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7707
7708 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7709 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7710
7711 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7712 &has_reduced_clock, &reduced_clock);
7713 if (!ok && !crtc_state->clock_set) {
7714 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7715 return -EINVAL;
7716 }
7717 /* Compat-code for transition, will disappear. */
7718 if (!crtc_state->clock_set) {
7719 crtc_state->dpll.n = clock.n;
7720 crtc_state->dpll.m1 = clock.m1;
7721 crtc_state->dpll.m2 = clock.m2;
7722 crtc_state->dpll.p1 = clock.p1;
7723 crtc_state->dpll.p2 = clock.p2;
7724 }
7725
7726 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7727 if (crtc_state->has_pch_encoder) {
7728 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7729 if (has_reduced_clock)
7730 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7731
7732 dpll = ironlake_compute_dpll(crtc, crtc_state,
7733 &fp, &reduced_clock,
7734 has_reduced_clock ? &fp2 : NULL);
7735
7736 crtc_state->dpll_hw_state.dpll = dpll;
7737 crtc_state->dpll_hw_state.fp0 = fp;
7738 if (has_reduced_clock)
7739 crtc_state->dpll_hw_state.fp1 = fp2;
7740 else
7741 crtc_state->dpll_hw_state.fp1 = fp;
7742
7743 pll = intel_get_shared_dpll(crtc, crtc_state);
7744 if (pll == NULL) {
7745 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7746 pipe_name(crtc->pipe));
7747 return -EINVAL;
7748 }
7749 }
7750
7751 if (is_lvds && has_reduced_clock && i915.powersave)
7752 crtc->lowfreq_avail = true;
7753 else
7754 crtc->lowfreq_avail = false;
7755
7756 return 0;
7757 }
7758
7759 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7760 struct intel_link_m_n *m_n)
7761 {
7762 struct drm_device *dev = crtc->base.dev;
7763 struct drm_i915_private *dev_priv = dev->dev_private;
7764 enum pipe pipe = crtc->pipe;
7765
7766 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7767 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7768 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7769 & ~TU_SIZE_MASK;
7770 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7771 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7772 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7773 }
7774
7775 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7776 enum transcoder transcoder,
7777 struct intel_link_m_n *m_n,
7778 struct intel_link_m_n *m2_n2)
7779 {
7780 struct drm_device *dev = crtc->base.dev;
7781 struct drm_i915_private *dev_priv = dev->dev_private;
7782 enum pipe pipe = crtc->pipe;
7783
7784 if (INTEL_INFO(dev)->gen >= 5) {
7785 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7786 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7787 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7788 & ~TU_SIZE_MASK;
7789 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7790 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7791 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7792 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7793 * gen < 8) and if DRRS is supported (to make sure the
7794 * registers are not unnecessarily read).
7795 */
7796 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7797 crtc->config->has_drrs) {
7798 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7799 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7800 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7801 & ~TU_SIZE_MASK;
7802 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7803 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7804 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7805 }
7806 } else {
7807 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7808 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7809 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7810 & ~TU_SIZE_MASK;
7811 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7812 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7813 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7814 }
7815 }
7816
7817 void intel_dp_get_m_n(struct intel_crtc *crtc,
7818 struct intel_crtc_state *pipe_config)
7819 {
7820 if (pipe_config->has_pch_encoder)
7821 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7822 else
7823 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7824 &pipe_config->dp_m_n,
7825 &pipe_config->dp_m2_n2);
7826 }
7827
7828 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7829 struct intel_crtc_state *pipe_config)
7830 {
7831 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7832 &pipe_config->fdi_m_n, NULL);
7833 }
7834
7835 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7836 struct intel_crtc_state *pipe_config)
7837 {
7838 struct drm_device *dev = crtc->base.dev;
7839 struct drm_i915_private *dev_priv = dev->dev_private;
7840 uint32_t tmp;
7841
7842 tmp = I915_READ(PS_CTL(crtc->pipe));
7843
7844 if (tmp & PS_ENABLE) {
7845 pipe_config->pch_pfit.enabled = true;
7846 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7847 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7848 }
7849 }
7850
7851 static void
7852 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7853 struct intel_initial_plane_config *plane_config)
7854 {
7855 struct drm_device *dev = crtc->base.dev;
7856 struct drm_i915_private *dev_priv = dev->dev_private;
7857 u32 val, base, offset, stride_mult, tiling;
7858 int pipe = crtc->pipe;
7859 int fourcc, pixel_format;
7860 unsigned int aligned_height;
7861 struct drm_framebuffer *fb;
7862 struct intel_framebuffer *intel_fb;
7863
7864 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7865 if (!intel_fb) {
7866 DRM_DEBUG_KMS("failed to alloc fb\n");
7867 return;
7868 }
7869
7870 fb = &intel_fb->base;
7871
7872 val = I915_READ(PLANE_CTL(pipe, 0));
7873 if (!(val & PLANE_CTL_ENABLE))
7874 goto error;
7875
7876 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7877 fourcc = skl_format_to_fourcc(pixel_format,
7878 val & PLANE_CTL_ORDER_RGBX,
7879 val & PLANE_CTL_ALPHA_MASK);
7880 fb->pixel_format = fourcc;
7881 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7882
7883 tiling = val & PLANE_CTL_TILED_MASK;
7884 switch (tiling) {
7885 case PLANE_CTL_TILED_LINEAR:
7886 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7887 break;
7888 case PLANE_CTL_TILED_X:
7889 plane_config->tiling = I915_TILING_X;
7890 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7891 break;
7892 case PLANE_CTL_TILED_Y:
7893 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7894 break;
7895 case PLANE_CTL_TILED_YF:
7896 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7897 break;
7898 default:
7899 MISSING_CASE(tiling);
7900 goto error;
7901 }
7902
7903 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7904 plane_config->base = base;
7905
7906 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7907
7908 val = I915_READ(PLANE_SIZE(pipe, 0));
7909 fb->height = ((val >> 16) & 0xfff) + 1;
7910 fb->width = ((val >> 0) & 0x1fff) + 1;
7911
7912 val = I915_READ(PLANE_STRIDE(pipe, 0));
7913 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7914 fb->pixel_format);
7915 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7916
7917 aligned_height = intel_fb_align_height(dev, fb->height,
7918 fb->pixel_format,
7919 fb->modifier[0]);
7920
7921 plane_config->size = fb->pitches[0] * aligned_height;
7922
7923 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7924 pipe_name(pipe), fb->width, fb->height,
7925 fb->bits_per_pixel, base, fb->pitches[0],
7926 plane_config->size);
7927
7928 plane_config->fb = intel_fb;
7929 return;
7930
7931 error:
7932 kfree(fb);
7933 }
7934
7935 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7936 struct intel_crtc_state *pipe_config)
7937 {
7938 struct drm_device *dev = crtc->base.dev;
7939 struct drm_i915_private *dev_priv = dev->dev_private;
7940 uint32_t tmp;
7941
7942 tmp = I915_READ(PF_CTL(crtc->pipe));
7943
7944 if (tmp & PF_ENABLE) {
7945 pipe_config->pch_pfit.enabled = true;
7946 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7947 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7948
7949 /* We currently do not free assignements of panel fitters on
7950 * ivb/hsw (since we don't use the higher upscaling modes which
7951 * differentiates them) so just WARN about this case for now. */
7952 if (IS_GEN7(dev)) {
7953 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7954 PF_PIPE_SEL_IVB(crtc->pipe));
7955 }
7956 }
7957 }
7958
7959 static void
7960 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7961 struct intel_initial_plane_config *plane_config)
7962 {
7963 struct drm_device *dev = crtc->base.dev;
7964 struct drm_i915_private *dev_priv = dev->dev_private;
7965 u32 val, base, offset;
7966 int pipe = crtc->pipe;
7967 int fourcc, pixel_format;
7968 unsigned int aligned_height;
7969 struct drm_framebuffer *fb;
7970 struct intel_framebuffer *intel_fb;
7971
7972 val = I915_READ(DSPCNTR(pipe));
7973 if (!(val & DISPLAY_PLANE_ENABLE))
7974 return;
7975
7976 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7977 if (!intel_fb) {
7978 DRM_DEBUG_KMS("failed to alloc fb\n");
7979 return;
7980 }
7981
7982 fb = &intel_fb->base;
7983
7984 if (INTEL_INFO(dev)->gen >= 4) {
7985 if (val & DISPPLANE_TILED) {
7986 plane_config->tiling = I915_TILING_X;
7987 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7988 }
7989 }
7990
7991 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7992 fourcc = i9xx_format_to_fourcc(pixel_format);
7993 fb->pixel_format = fourcc;
7994 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7995
7996 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7997 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7998 offset = I915_READ(DSPOFFSET(pipe));
7999 } else {
8000 if (plane_config->tiling)
8001 offset = I915_READ(DSPTILEOFF(pipe));
8002 else
8003 offset = I915_READ(DSPLINOFF(pipe));
8004 }
8005 plane_config->base = base;
8006
8007 val = I915_READ(PIPESRC(pipe));
8008 fb->width = ((val >> 16) & 0xfff) + 1;
8009 fb->height = ((val >> 0) & 0xfff) + 1;
8010
8011 val = I915_READ(DSPSTRIDE(pipe));
8012 fb->pitches[0] = val & 0xffffffc0;
8013
8014 aligned_height = intel_fb_align_height(dev, fb->height,
8015 fb->pixel_format,
8016 fb->modifier[0]);
8017
8018 plane_config->size = fb->pitches[0] * aligned_height;
8019
8020 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8021 pipe_name(pipe), fb->width, fb->height,
8022 fb->bits_per_pixel, base, fb->pitches[0],
8023 plane_config->size);
8024
8025 plane_config->fb = intel_fb;
8026 }
8027
8028 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8029 struct intel_crtc_state *pipe_config)
8030 {
8031 struct drm_device *dev = crtc->base.dev;
8032 struct drm_i915_private *dev_priv = dev->dev_private;
8033 uint32_t tmp;
8034
8035 if (!intel_display_power_is_enabled(dev_priv,
8036 POWER_DOMAIN_PIPE(crtc->pipe)))
8037 return false;
8038
8039 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8040 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8041
8042 tmp = I915_READ(PIPECONF(crtc->pipe));
8043 if (!(tmp & PIPECONF_ENABLE))
8044 return false;
8045
8046 switch (tmp & PIPECONF_BPC_MASK) {
8047 case PIPECONF_6BPC:
8048 pipe_config->pipe_bpp = 18;
8049 break;
8050 case PIPECONF_8BPC:
8051 pipe_config->pipe_bpp = 24;
8052 break;
8053 case PIPECONF_10BPC:
8054 pipe_config->pipe_bpp = 30;
8055 break;
8056 case PIPECONF_12BPC:
8057 pipe_config->pipe_bpp = 36;
8058 break;
8059 default:
8060 break;
8061 }
8062
8063 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8064 pipe_config->limited_color_range = true;
8065
8066 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8067 struct intel_shared_dpll *pll;
8068
8069 pipe_config->has_pch_encoder = true;
8070
8071 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8072 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8073 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8074
8075 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8076
8077 if (HAS_PCH_IBX(dev_priv->dev)) {
8078 pipe_config->shared_dpll =
8079 (enum intel_dpll_id) crtc->pipe;
8080 } else {
8081 tmp = I915_READ(PCH_DPLL_SEL);
8082 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8083 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8084 else
8085 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8086 }
8087
8088 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8089
8090 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8091 &pipe_config->dpll_hw_state));
8092
8093 tmp = pipe_config->dpll_hw_state.dpll;
8094 pipe_config->pixel_multiplier =
8095 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8096 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8097
8098 ironlake_pch_clock_get(crtc, pipe_config);
8099 } else {
8100 pipe_config->pixel_multiplier = 1;
8101 }
8102
8103 intel_get_pipe_timings(crtc, pipe_config);
8104
8105 ironlake_get_pfit_config(crtc, pipe_config);
8106
8107 return true;
8108 }
8109
8110 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8111 {
8112 struct drm_device *dev = dev_priv->dev;
8113 struct intel_crtc *crtc;
8114
8115 for_each_intel_crtc(dev, crtc)
8116 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8117 pipe_name(crtc->pipe));
8118
8119 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8120 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8121 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8122 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8123 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8124 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8125 "CPU PWM1 enabled\n");
8126 if (IS_HASWELL(dev))
8127 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8128 "CPU PWM2 enabled\n");
8129 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8130 "PCH PWM1 enabled\n");
8131 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8132 "Utility pin enabled\n");
8133 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8134
8135 /*
8136 * In theory we can still leave IRQs enabled, as long as only the HPD
8137 * interrupts remain enabled. We used to check for that, but since it's
8138 * gen-specific and since we only disable LCPLL after we fully disable
8139 * the interrupts, the check below should be enough.
8140 */
8141 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8142 }
8143
8144 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8145 {
8146 struct drm_device *dev = dev_priv->dev;
8147
8148 if (IS_HASWELL(dev))
8149 return I915_READ(D_COMP_HSW);
8150 else
8151 return I915_READ(D_COMP_BDW);
8152 }
8153
8154 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8155 {
8156 struct drm_device *dev = dev_priv->dev;
8157
8158 if (IS_HASWELL(dev)) {
8159 mutex_lock(&dev_priv->rps.hw_lock);
8160 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8161 val))
8162 DRM_ERROR("Failed to write to D_COMP\n");
8163 mutex_unlock(&dev_priv->rps.hw_lock);
8164 } else {
8165 I915_WRITE(D_COMP_BDW, val);
8166 POSTING_READ(D_COMP_BDW);
8167 }
8168 }
8169
8170 /*
8171 * This function implements pieces of two sequences from BSpec:
8172 * - Sequence for display software to disable LCPLL
8173 * - Sequence for display software to allow package C8+
8174 * The steps implemented here are just the steps that actually touch the LCPLL
8175 * register. Callers should take care of disabling all the display engine
8176 * functions, doing the mode unset, fixing interrupts, etc.
8177 */
8178 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8179 bool switch_to_fclk, bool allow_power_down)
8180 {
8181 uint32_t val;
8182
8183 assert_can_disable_lcpll(dev_priv);
8184
8185 val = I915_READ(LCPLL_CTL);
8186
8187 if (switch_to_fclk) {
8188 val |= LCPLL_CD_SOURCE_FCLK;
8189 I915_WRITE(LCPLL_CTL, val);
8190
8191 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8192 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8193 DRM_ERROR("Switching to FCLK failed\n");
8194
8195 val = I915_READ(LCPLL_CTL);
8196 }
8197
8198 val |= LCPLL_PLL_DISABLE;
8199 I915_WRITE(LCPLL_CTL, val);
8200 POSTING_READ(LCPLL_CTL);
8201
8202 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8203 DRM_ERROR("LCPLL still locked\n");
8204
8205 val = hsw_read_dcomp(dev_priv);
8206 val |= D_COMP_COMP_DISABLE;
8207 hsw_write_dcomp(dev_priv, val);
8208 ndelay(100);
8209
8210 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8211 1))
8212 DRM_ERROR("D_COMP RCOMP still in progress\n");
8213
8214 if (allow_power_down) {
8215 val = I915_READ(LCPLL_CTL);
8216 val |= LCPLL_POWER_DOWN_ALLOW;
8217 I915_WRITE(LCPLL_CTL, val);
8218 POSTING_READ(LCPLL_CTL);
8219 }
8220 }
8221
8222 /*
8223 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8224 * source.
8225 */
8226 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8227 {
8228 uint32_t val;
8229
8230 val = I915_READ(LCPLL_CTL);
8231
8232 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8233 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8234 return;
8235
8236 /*
8237 * Make sure we're not on PC8 state before disabling PC8, otherwise
8238 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8239 */
8240 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8241
8242 if (val & LCPLL_POWER_DOWN_ALLOW) {
8243 val &= ~LCPLL_POWER_DOWN_ALLOW;
8244 I915_WRITE(LCPLL_CTL, val);
8245 POSTING_READ(LCPLL_CTL);
8246 }
8247
8248 val = hsw_read_dcomp(dev_priv);
8249 val |= D_COMP_COMP_FORCE;
8250 val &= ~D_COMP_COMP_DISABLE;
8251 hsw_write_dcomp(dev_priv, val);
8252
8253 val = I915_READ(LCPLL_CTL);
8254 val &= ~LCPLL_PLL_DISABLE;
8255 I915_WRITE(LCPLL_CTL, val);
8256
8257 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8258 DRM_ERROR("LCPLL not locked yet\n");
8259
8260 if (val & LCPLL_CD_SOURCE_FCLK) {
8261 val = I915_READ(LCPLL_CTL);
8262 val &= ~LCPLL_CD_SOURCE_FCLK;
8263 I915_WRITE(LCPLL_CTL, val);
8264
8265 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8266 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8267 DRM_ERROR("Switching back to LCPLL failed\n");
8268 }
8269
8270 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8271 }
8272
8273 /*
8274 * Package states C8 and deeper are really deep PC states that can only be
8275 * reached when all the devices on the system allow it, so even if the graphics
8276 * device allows PC8+, it doesn't mean the system will actually get to these
8277 * states. Our driver only allows PC8+ when going into runtime PM.
8278 *
8279 * The requirements for PC8+ are that all the outputs are disabled, the power
8280 * well is disabled and most interrupts are disabled, and these are also
8281 * requirements for runtime PM. When these conditions are met, we manually do
8282 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8283 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8284 * hang the machine.
8285 *
8286 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8287 * the state of some registers, so when we come back from PC8+ we need to
8288 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8289 * need to take care of the registers kept by RC6. Notice that this happens even
8290 * if we don't put the device in PCI D3 state (which is what currently happens
8291 * because of the runtime PM support).
8292 *
8293 * For more, read "Display Sequences for Package C8" on the hardware
8294 * documentation.
8295 */
8296 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8297 {
8298 struct drm_device *dev = dev_priv->dev;
8299 uint32_t val;
8300
8301 DRM_DEBUG_KMS("Enabling package C8+\n");
8302
8303 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8304 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8305 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8306 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8307 }
8308
8309 lpt_disable_clkout_dp(dev);
8310 hsw_disable_lcpll(dev_priv, true, true);
8311 }
8312
8313 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8314 {
8315 struct drm_device *dev = dev_priv->dev;
8316 uint32_t val;
8317
8318 DRM_DEBUG_KMS("Disabling package C8+\n");
8319
8320 hsw_restore_lcpll(dev_priv);
8321 lpt_init_pch_refclk(dev);
8322
8323 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8324 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8325 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8326 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8327 }
8328
8329 intel_prepare_ddi(dev);
8330 }
8331
8332 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8333 struct intel_crtc_state *crtc_state)
8334 {
8335 if (!intel_ddi_pll_select(crtc, crtc_state))
8336 return -EINVAL;
8337
8338 crtc->lowfreq_avail = false;
8339
8340 return 0;
8341 }
8342
8343 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8344 enum port port,
8345 struct intel_crtc_state *pipe_config)
8346 {
8347 u32 temp, dpll_ctl1;
8348
8349 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8350 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8351
8352 switch (pipe_config->ddi_pll_sel) {
8353 case SKL_DPLL0:
8354 /*
8355 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8356 * of the shared DPLL framework and thus needs to be read out
8357 * separately
8358 */
8359 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8360 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8361 break;
8362 case SKL_DPLL1:
8363 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8364 break;
8365 case SKL_DPLL2:
8366 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8367 break;
8368 case SKL_DPLL3:
8369 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8370 break;
8371 }
8372 }
8373
8374 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8375 enum port port,
8376 struct intel_crtc_state *pipe_config)
8377 {
8378 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8379
8380 switch (pipe_config->ddi_pll_sel) {
8381 case PORT_CLK_SEL_WRPLL1:
8382 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8383 break;
8384 case PORT_CLK_SEL_WRPLL2:
8385 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8386 break;
8387 }
8388 }
8389
8390 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8391 struct intel_crtc_state *pipe_config)
8392 {
8393 struct drm_device *dev = crtc->base.dev;
8394 struct drm_i915_private *dev_priv = dev->dev_private;
8395 struct intel_shared_dpll *pll;
8396 enum port port;
8397 uint32_t tmp;
8398
8399 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8400
8401 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8402
8403 if (IS_SKYLAKE(dev))
8404 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8405 else
8406 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8407
8408 if (pipe_config->shared_dpll >= 0) {
8409 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8410
8411 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8412 &pipe_config->dpll_hw_state));
8413 }
8414
8415 /*
8416 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8417 * DDI E. So just check whether this pipe is wired to DDI E and whether
8418 * the PCH transcoder is on.
8419 */
8420 if (INTEL_INFO(dev)->gen < 9 &&
8421 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8422 pipe_config->has_pch_encoder = true;
8423
8424 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8425 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8426 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8427
8428 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8429 }
8430 }
8431
8432 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8433 struct intel_crtc_state *pipe_config)
8434 {
8435 struct drm_device *dev = crtc->base.dev;
8436 struct drm_i915_private *dev_priv = dev->dev_private;
8437 enum intel_display_power_domain pfit_domain;
8438 uint32_t tmp;
8439
8440 if (!intel_display_power_is_enabled(dev_priv,
8441 POWER_DOMAIN_PIPE(crtc->pipe)))
8442 return false;
8443
8444 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8445 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8446
8447 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8448 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8449 enum pipe trans_edp_pipe;
8450 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8451 default:
8452 WARN(1, "unknown pipe linked to edp transcoder\n");
8453 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8454 case TRANS_DDI_EDP_INPUT_A_ON:
8455 trans_edp_pipe = PIPE_A;
8456 break;
8457 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8458 trans_edp_pipe = PIPE_B;
8459 break;
8460 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8461 trans_edp_pipe = PIPE_C;
8462 break;
8463 }
8464
8465 if (trans_edp_pipe == crtc->pipe)
8466 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8467 }
8468
8469 if (!intel_display_power_is_enabled(dev_priv,
8470 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8471 return false;
8472
8473 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8474 if (!(tmp & PIPECONF_ENABLE))
8475 return false;
8476
8477 haswell_get_ddi_port_state(crtc, pipe_config);
8478
8479 intel_get_pipe_timings(crtc, pipe_config);
8480
8481 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8482 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8483 if (IS_SKYLAKE(dev))
8484 skylake_get_pfit_config(crtc, pipe_config);
8485 else
8486 ironlake_get_pfit_config(crtc, pipe_config);
8487 }
8488
8489 if (IS_HASWELL(dev))
8490 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8491 (I915_READ(IPS_CTL) & IPS_ENABLE);
8492
8493 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8494 pipe_config->pixel_multiplier =
8495 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8496 } else {
8497 pipe_config->pixel_multiplier = 1;
8498 }
8499
8500 return true;
8501 }
8502
8503 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8504 {
8505 struct drm_device *dev = crtc->dev;
8506 struct drm_i915_private *dev_priv = dev->dev_private;
8507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8508 uint32_t cntl = 0, size = 0;
8509
8510 if (base) {
8511 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8512 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8513 unsigned int stride = roundup_pow_of_two(width) * 4;
8514
8515 switch (stride) {
8516 default:
8517 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8518 width, stride);
8519 stride = 256;
8520 /* fallthrough */
8521 case 256:
8522 case 512:
8523 case 1024:
8524 case 2048:
8525 break;
8526 }
8527
8528 cntl |= CURSOR_ENABLE |
8529 CURSOR_GAMMA_ENABLE |
8530 CURSOR_FORMAT_ARGB |
8531 CURSOR_STRIDE(stride);
8532
8533 size = (height << 12) | width;
8534 }
8535
8536 if (intel_crtc->cursor_cntl != 0 &&
8537 (intel_crtc->cursor_base != base ||
8538 intel_crtc->cursor_size != size ||
8539 intel_crtc->cursor_cntl != cntl)) {
8540 /* On these chipsets we can only modify the base/size/stride
8541 * whilst the cursor is disabled.
8542 */
8543 I915_WRITE(_CURACNTR, 0);
8544 POSTING_READ(_CURACNTR);
8545 intel_crtc->cursor_cntl = 0;
8546 }
8547
8548 if (intel_crtc->cursor_base != base) {
8549 I915_WRITE(_CURABASE, base);
8550 intel_crtc->cursor_base = base;
8551 }
8552
8553 if (intel_crtc->cursor_size != size) {
8554 I915_WRITE(CURSIZE, size);
8555 intel_crtc->cursor_size = size;
8556 }
8557
8558 if (intel_crtc->cursor_cntl != cntl) {
8559 I915_WRITE(_CURACNTR, cntl);
8560 POSTING_READ(_CURACNTR);
8561 intel_crtc->cursor_cntl = cntl;
8562 }
8563 }
8564
8565 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8566 {
8567 struct drm_device *dev = crtc->dev;
8568 struct drm_i915_private *dev_priv = dev->dev_private;
8569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8570 int pipe = intel_crtc->pipe;
8571 uint32_t cntl;
8572
8573 cntl = 0;
8574 if (base) {
8575 cntl = MCURSOR_GAMMA_ENABLE;
8576 switch (intel_crtc->base.cursor->state->crtc_w) {
8577 case 64:
8578 cntl |= CURSOR_MODE_64_ARGB_AX;
8579 break;
8580 case 128:
8581 cntl |= CURSOR_MODE_128_ARGB_AX;
8582 break;
8583 case 256:
8584 cntl |= CURSOR_MODE_256_ARGB_AX;
8585 break;
8586 default:
8587 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8588 return;
8589 }
8590 cntl |= pipe << 28; /* Connect to correct pipe */
8591
8592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8593 cntl |= CURSOR_PIPE_CSC_ENABLE;
8594 }
8595
8596 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8597 cntl |= CURSOR_ROTATE_180;
8598
8599 if (intel_crtc->cursor_cntl != cntl) {
8600 I915_WRITE(CURCNTR(pipe), cntl);
8601 POSTING_READ(CURCNTR(pipe));
8602 intel_crtc->cursor_cntl = cntl;
8603 }
8604
8605 /* and commit changes on next vblank */
8606 I915_WRITE(CURBASE(pipe), base);
8607 POSTING_READ(CURBASE(pipe));
8608
8609 intel_crtc->cursor_base = base;
8610 }
8611
8612 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8613 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8614 bool on)
8615 {
8616 struct drm_device *dev = crtc->dev;
8617 struct drm_i915_private *dev_priv = dev->dev_private;
8618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8619 int pipe = intel_crtc->pipe;
8620 int x = crtc->cursor_x;
8621 int y = crtc->cursor_y;
8622 u32 base = 0, pos = 0;
8623
8624 if (on)
8625 base = intel_crtc->cursor_addr;
8626
8627 if (x >= intel_crtc->config->pipe_src_w)
8628 base = 0;
8629
8630 if (y >= intel_crtc->config->pipe_src_h)
8631 base = 0;
8632
8633 if (x < 0) {
8634 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8635 base = 0;
8636
8637 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8638 x = -x;
8639 }
8640 pos |= x << CURSOR_X_SHIFT;
8641
8642 if (y < 0) {
8643 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8644 base = 0;
8645
8646 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8647 y = -y;
8648 }
8649 pos |= y << CURSOR_Y_SHIFT;
8650
8651 if (base == 0 && intel_crtc->cursor_base == 0)
8652 return;
8653
8654 I915_WRITE(CURPOS(pipe), pos);
8655
8656 /* ILK+ do this automagically */
8657 if (HAS_GMCH_DISPLAY(dev) &&
8658 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8659 base += (intel_crtc->base.cursor->state->crtc_h *
8660 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8661 }
8662
8663 if (IS_845G(dev) || IS_I865G(dev))
8664 i845_update_cursor(crtc, base);
8665 else
8666 i9xx_update_cursor(crtc, base);
8667 }
8668
8669 static bool cursor_size_ok(struct drm_device *dev,
8670 uint32_t width, uint32_t height)
8671 {
8672 if (width == 0 || height == 0)
8673 return false;
8674
8675 /*
8676 * 845g/865g are special in that they are only limited by
8677 * the width of their cursors, the height is arbitrary up to
8678 * the precision of the register. Everything else requires
8679 * square cursors, limited to a few power-of-two sizes.
8680 */
8681 if (IS_845G(dev) || IS_I865G(dev)) {
8682 if ((width & 63) != 0)
8683 return false;
8684
8685 if (width > (IS_845G(dev) ? 64 : 512))
8686 return false;
8687
8688 if (height > 1023)
8689 return false;
8690 } else {
8691 switch (width | height) {
8692 case 256:
8693 case 128:
8694 if (IS_GEN2(dev))
8695 return false;
8696 case 64:
8697 break;
8698 default:
8699 return false;
8700 }
8701 }
8702
8703 return true;
8704 }
8705
8706 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8707 u16 *blue, uint32_t start, uint32_t size)
8708 {
8709 int end = (start + size > 256) ? 256 : start + size, i;
8710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8711
8712 for (i = start; i < end; i++) {
8713 intel_crtc->lut_r[i] = red[i] >> 8;
8714 intel_crtc->lut_g[i] = green[i] >> 8;
8715 intel_crtc->lut_b[i] = blue[i] >> 8;
8716 }
8717
8718 intel_crtc_load_lut(crtc);
8719 }
8720
8721 /* VESA 640x480x72Hz mode to set on the pipe */
8722 static struct drm_display_mode load_detect_mode = {
8723 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8724 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8725 };
8726
8727 struct drm_framebuffer *
8728 __intel_framebuffer_create(struct drm_device *dev,
8729 struct drm_mode_fb_cmd2 *mode_cmd,
8730 struct drm_i915_gem_object *obj)
8731 {
8732 struct intel_framebuffer *intel_fb;
8733 int ret;
8734
8735 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8736 if (!intel_fb) {
8737 drm_gem_object_unreference(&obj->base);
8738 return ERR_PTR(-ENOMEM);
8739 }
8740
8741 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8742 if (ret)
8743 goto err;
8744
8745 return &intel_fb->base;
8746 err:
8747 drm_gem_object_unreference(&obj->base);
8748 kfree(intel_fb);
8749
8750 return ERR_PTR(ret);
8751 }
8752
8753 static struct drm_framebuffer *
8754 intel_framebuffer_create(struct drm_device *dev,
8755 struct drm_mode_fb_cmd2 *mode_cmd,
8756 struct drm_i915_gem_object *obj)
8757 {
8758 struct drm_framebuffer *fb;
8759 int ret;
8760
8761 ret = i915_mutex_lock_interruptible(dev);
8762 if (ret)
8763 return ERR_PTR(ret);
8764 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8765 mutex_unlock(&dev->struct_mutex);
8766
8767 return fb;
8768 }
8769
8770 static u32
8771 intel_framebuffer_pitch_for_width(int width, int bpp)
8772 {
8773 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8774 return ALIGN(pitch, 64);
8775 }
8776
8777 static u32
8778 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8779 {
8780 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8781 return PAGE_ALIGN(pitch * mode->vdisplay);
8782 }
8783
8784 static struct drm_framebuffer *
8785 intel_framebuffer_create_for_mode(struct drm_device *dev,
8786 struct drm_display_mode *mode,
8787 int depth, int bpp)
8788 {
8789 struct drm_i915_gem_object *obj;
8790 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8791
8792 obj = i915_gem_alloc_object(dev,
8793 intel_framebuffer_size_for_mode(mode, bpp));
8794 if (obj == NULL)
8795 return ERR_PTR(-ENOMEM);
8796
8797 mode_cmd.width = mode->hdisplay;
8798 mode_cmd.height = mode->vdisplay;
8799 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8800 bpp);
8801 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8802
8803 return intel_framebuffer_create(dev, &mode_cmd, obj);
8804 }
8805
8806 static struct drm_framebuffer *
8807 mode_fits_in_fbdev(struct drm_device *dev,
8808 struct drm_display_mode *mode)
8809 {
8810 #ifdef CONFIG_DRM_I915_FBDEV
8811 struct drm_i915_private *dev_priv = dev->dev_private;
8812 struct drm_i915_gem_object *obj;
8813 struct drm_framebuffer *fb;
8814
8815 if (!dev_priv->fbdev)
8816 return NULL;
8817
8818 if (!dev_priv->fbdev->fb)
8819 return NULL;
8820
8821 obj = dev_priv->fbdev->fb->obj;
8822 BUG_ON(!obj);
8823
8824 fb = &dev_priv->fbdev->fb->base;
8825 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8826 fb->bits_per_pixel))
8827 return NULL;
8828
8829 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8830 return NULL;
8831
8832 return fb;
8833 #else
8834 return NULL;
8835 #endif
8836 }
8837
8838 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8839 struct drm_display_mode *mode,
8840 struct intel_load_detect_pipe *old,
8841 struct drm_modeset_acquire_ctx *ctx)
8842 {
8843 struct intel_crtc *intel_crtc;
8844 struct intel_encoder *intel_encoder =
8845 intel_attached_encoder(connector);
8846 struct drm_crtc *possible_crtc;
8847 struct drm_encoder *encoder = &intel_encoder->base;
8848 struct drm_crtc *crtc = NULL;
8849 struct drm_device *dev = encoder->dev;
8850 struct drm_framebuffer *fb;
8851 struct drm_mode_config *config = &dev->mode_config;
8852 int ret, i = -1;
8853
8854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8855 connector->base.id, connector->name,
8856 encoder->base.id, encoder->name);
8857
8858 retry:
8859 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8860 if (ret)
8861 goto fail_unlock;
8862
8863 /*
8864 * Algorithm gets a little messy:
8865 *
8866 * - if the connector already has an assigned crtc, use it (but make
8867 * sure it's on first)
8868 *
8869 * - try to find the first unused crtc that can drive this connector,
8870 * and use that if we find one
8871 */
8872
8873 /* See if we already have a CRTC for this connector */
8874 if (encoder->crtc) {
8875 crtc = encoder->crtc;
8876
8877 ret = drm_modeset_lock(&crtc->mutex, ctx);
8878 if (ret)
8879 goto fail_unlock;
8880 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8881 if (ret)
8882 goto fail_unlock;
8883
8884 old->dpms_mode = connector->dpms;
8885 old->load_detect_temp = false;
8886
8887 /* Make sure the crtc and connector are running */
8888 if (connector->dpms != DRM_MODE_DPMS_ON)
8889 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8890
8891 return true;
8892 }
8893
8894 /* Find an unused one (if possible) */
8895 for_each_crtc(dev, possible_crtc) {
8896 i++;
8897 if (!(encoder->possible_crtcs & (1 << i)))
8898 continue;
8899 if (possible_crtc->state->enable)
8900 continue;
8901 /* This can occur when applying the pipe A quirk on resume. */
8902 if (to_intel_crtc(possible_crtc)->new_enabled)
8903 continue;
8904
8905 crtc = possible_crtc;
8906 break;
8907 }
8908
8909 /*
8910 * If we didn't find an unused CRTC, don't use any.
8911 */
8912 if (!crtc) {
8913 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8914 goto fail_unlock;
8915 }
8916
8917 ret = drm_modeset_lock(&crtc->mutex, ctx);
8918 if (ret)
8919 goto fail_unlock;
8920 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8921 if (ret)
8922 goto fail_unlock;
8923 intel_encoder->new_crtc = to_intel_crtc(crtc);
8924 to_intel_connector(connector)->new_encoder = intel_encoder;
8925
8926 intel_crtc = to_intel_crtc(crtc);
8927 intel_crtc->new_enabled = true;
8928 intel_crtc->new_config = intel_crtc->config;
8929 old->dpms_mode = connector->dpms;
8930 old->load_detect_temp = true;
8931 old->release_fb = NULL;
8932
8933 if (!mode)
8934 mode = &load_detect_mode;
8935
8936 /* We need a framebuffer large enough to accommodate all accesses
8937 * that the plane may generate whilst we perform load detection.
8938 * We can not rely on the fbcon either being present (we get called
8939 * during its initialisation to detect all boot displays, or it may
8940 * not even exist) or that it is large enough to satisfy the
8941 * requested mode.
8942 */
8943 fb = mode_fits_in_fbdev(dev, mode);
8944 if (fb == NULL) {
8945 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8946 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8947 old->release_fb = fb;
8948 } else
8949 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8950 if (IS_ERR(fb)) {
8951 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8952 goto fail;
8953 }
8954
8955 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8956 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8957 if (old->release_fb)
8958 old->release_fb->funcs->destroy(old->release_fb);
8959 goto fail;
8960 }
8961 crtc->primary->crtc = crtc;
8962
8963 /* let the connector get through one full cycle before testing */
8964 intel_wait_for_vblank(dev, intel_crtc->pipe);
8965 return true;
8966
8967 fail:
8968 intel_crtc->new_enabled = crtc->state->enable;
8969 if (intel_crtc->new_enabled)
8970 intel_crtc->new_config = intel_crtc->config;
8971 else
8972 intel_crtc->new_config = NULL;
8973 fail_unlock:
8974 if (ret == -EDEADLK) {
8975 drm_modeset_backoff(ctx);
8976 goto retry;
8977 }
8978
8979 return false;
8980 }
8981
8982 void intel_release_load_detect_pipe(struct drm_connector *connector,
8983 struct intel_load_detect_pipe *old)
8984 {
8985 struct intel_encoder *intel_encoder =
8986 intel_attached_encoder(connector);
8987 struct drm_encoder *encoder = &intel_encoder->base;
8988 struct drm_crtc *crtc = encoder->crtc;
8989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8990
8991 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8992 connector->base.id, connector->name,
8993 encoder->base.id, encoder->name);
8994
8995 if (old->load_detect_temp) {
8996 to_intel_connector(connector)->new_encoder = NULL;
8997 intel_encoder->new_crtc = NULL;
8998 intel_crtc->new_enabled = false;
8999 intel_crtc->new_config = NULL;
9000 intel_set_mode(crtc, NULL, 0, 0, NULL);
9001
9002 if (old->release_fb) {
9003 drm_framebuffer_unregister_private(old->release_fb);
9004 drm_framebuffer_unreference(old->release_fb);
9005 }
9006
9007 return;
9008 }
9009
9010 /* Switch crtc and encoder back off if necessary */
9011 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9012 connector->funcs->dpms(connector, old->dpms_mode);
9013 }
9014
9015 static int i9xx_pll_refclk(struct drm_device *dev,
9016 const struct intel_crtc_state *pipe_config)
9017 {
9018 struct drm_i915_private *dev_priv = dev->dev_private;
9019 u32 dpll = pipe_config->dpll_hw_state.dpll;
9020
9021 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9022 return dev_priv->vbt.lvds_ssc_freq;
9023 else if (HAS_PCH_SPLIT(dev))
9024 return 120000;
9025 else if (!IS_GEN2(dev))
9026 return 96000;
9027 else
9028 return 48000;
9029 }
9030
9031 /* Returns the clock of the currently programmed mode of the given pipe. */
9032 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9033 struct intel_crtc_state *pipe_config)
9034 {
9035 struct drm_device *dev = crtc->base.dev;
9036 struct drm_i915_private *dev_priv = dev->dev_private;
9037 int pipe = pipe_config->cpu_transcoder;
9038 u32 dpll = pipe_config->dpll_hw_state.dpll;
9039 u32 fp;
9040 intel_clock_t clock;
9041 int refclk = i9xx_pll_refclk(dev, pipe_config);
9042
9043 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9044 fp = pipe_config->dpll_hw_state.fp0;
9045 else
9046 fp = pipe_config->dpll_hw_state.fp1;
9047
9048 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9049 if (IS_PINEVIEW(dev)) {
9050 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9051 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9052 } else {
9053 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9054 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9055 }
9056
9057 if (!IS_GEN2(dev)) {
9058 if (IS_PINEVIEW(dev))
9059 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9060 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9061 else
9062 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9063 DPLL_FPA01_P1_POST_DIV_SHIFT);
9064
9065 switch (dpll & DPLL_MODE_MASK) {
9066 case DPLLB_MODE_DAC_SERIAL:
9067 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9068 5 : 10;
9069 break;
9070 case DPLLB_MODE_LVDS:
9071 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9072 7 : 14;
9073 break;
9074 default:
9075 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9076 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9077 return;
9078 }
9079
9080 if (IS_PINEVIEW(dev))
9081 pineview_clock(refclk, &clock);
9082 else
9083 i9xx_clock(refclk, &clock);
9084 } else {
9085 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9086 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9087
9088 if (is_lvds) {
9089 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9090 DPLL_FPA01_P1_POST_DIV_SHIFT);
9091
9092 if (lvds & LVDS_CLKB_POWER_UP)
9093 clock.p2 = 7;
9094 else
9095 clock.p2 = 14;
9096 } else {
9097 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9098 clock.p1 = 2;
9099 else {
9100 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9101 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9102 }
9103 if (dpll & PLL_P2_DIVIDE_BY_4)
9104 clock.p2 = 4;
9105 else
9106 clock.p2 = 2;
9107 }
9108
9109 i9xx_clock(refclk, &clock);
9110 }
9111
9112 /*
9113 * This value includes pixel_multiplier. We will use
9114 * port_clock to compute adjusted_mode.crtc_clock in the
9115 * encoder's get_config() function.
9116 */
9117 pipe_config->port_clock = clock.dot;
9118 }
9119
9120 int intel_dotclock_calculate(int link_freq,
9121 const struct intel_link_m_n *m_n)
9122 {
9123 /*
9124 * The calculation for the data clock is:
9125 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9126 * But we want to avoid losing precison if possible, so:
9127 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9128 *
9129 * and the link clock is simpler:
9130 * link_clock = (m * link_clock) / n
9131 */
9132
9133 if (!m_n->link_n)
9134 return 0;
9135
9136 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9137 }
9138
9139 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9140 struct intel_crtc_state *pipe_config)
9141 {
9142 struct drm_device *dev = crtc->base.dev;
9143
9144 /* read out port_clock from the DPLL */
9145 i9xx_crtc_clock_get(crtc, pipe_config);
9146
9147 /*
9148 * This value does not include pixel_multiplier.
9149 * We will check that port_clock and adjusted_mode.crtc_clock
9150 * agree once we know their relationship in the encoder's
9151 * get_config() function.
9152 */
9153 pipe_config->base.adjusted_mode.crtc_clock =
9154 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9155 &pipe_config->fdi_m_n);
9156 }
9157
9158 /** Returns the currently programmed mode of the given pipe. */
9159 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9160 struct drm_crtc *crtc)
9161 {
9162 struct drm_i915_private *dev_priv = dev->dev_private;
9163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9164 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9165 struct drm_display_mode *mode;
9166 struct intel_crtc_state pipe_config;
9167 int htot = I915_READ(HTOTAL(cpu_transcoder));
9168 int hsync = I915_READ(HSYNC(cpu_transcoder));
9169 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9170 int vsync = I915_READ(VSYNC(cpu_transcoder));
9171 enum pipe pipe = intel_crtc->pipe;
9172
9173 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9174 if (!mode)
9175 return NULL;
9176
9177 /*
9178 * Construct a pipe_config sufficient for getting the clock info
9179 * back out of crtc_clock_get.
9180 *
9181 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9182 * to use a real value here instead.
9183 */
9184 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9185 pipe_config.pixel_multiplier = 1;
9186 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9187 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9188 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9189 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9190
9191 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9192 mode->hdisplay = (htot & 0xffff) + 1;
9193 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9194 mode->hsync_start = (hsync & 0xffff) + 1;
9195 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9196 mode->vdisplay = (vtot & 0xffff) + 1;
9197 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9198 mode->vsync_start = (vsync & 0xffff) + 1;
9199 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9200
9201 drm_mode_set_name(mode);
9202
9203 return mode;
9204 }
9205
9206 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9207 {
9208 struct drm_device *dev = crtc->dev;
9209 struct drm_i915_private *dev_priv = dev->dev_private;
9210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9211
9212 if (!HAS_GMCH_DISPLAY(dev))
9213 return;
9214
9215 if (!dev_priv->lvds_downclock_avail)
9216 return;
9217
9218 /*
9219 * Since this is called by a timer, we should never get here in
9220 * the manual case.
9221 */
9222 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9223 int pipe = intel_crtc->pipe;
9224 int dpll_reg = DPLL(pipe);
9225 int dpll;
9226
9227 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9228
9229 assert_panel_unlocked(dev_priv, pipe);
9230
9231 dpll = I915_READ(dpll_reg);
9232 dpll |= DISPLAY_RATE_SELECT_FPA1;
9233 I915_WRITE(dpll_reg, dpll);
9234 intel_wait_for_vblank(dev, pipe);
9235 dpll = I915_READ(dpll_reg);
9236 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9237 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9238 }
9239
9240 }
9241
9242 void intel_mark_busy(struct drm_device *dev)
9243 {
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245
9246 if (dev_priv->mm.busy)
9247 return;
9248
9249 intel_runtime_pm_get(dev_priv);
9250 i915_update_gfx_val(dev_priv);
9251 if (INTEL_INFO(dev)->gen >= 6)
9252 gen6_rps_busy(dev_priv);
9253 dev_priv->mm.busy = true;
9254 }
9255
9256 void intel_mark_idle(struct drm_device *dev)
9257 {
9258 struct drm_i915_private *dev_priv = dev->dev_private;
9259 struct drm_crtc *crtc;
9260
9261 if (!dev_priv->mm.busy)
9262 return;
9263
9264 dev_priv->mm.busy = false;
9265
9266 if (!i915.powersave)
9267 goto out;
9268
9269 for_each_crtc(dev, crtc) {
9270 if (!crtc->primary->fb)
9271 continue;
9272
9273 intel_decrease_pllclock(crtc);
9274 }
9275
9276 if (INTEL_INFO(dev)->gen >= 6)
9277 gen6_rps_idle(dev->dev_private);
9278
9279 out:
9280 intel_runtime_pm_put(dev_priv);
9281 }
9282
9283 static void intel_crtc_set_state(struct intel_crtc *crtc,
9284 struct intel_crtc_state *crtc_state)
9285 {
9286 kfree(crtc->config);
9287 crtc->config = crtc_state;
9288 crtc->base.state = &crtc_state->base;
9289 }
9290
9291 static void intel_crtc_destroy(struct drm_crtc *crtc)
9292 {
9293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9294 struct drm_device *dev = crtc->dev;
9295 struct intel_unpin_work *work;
9296
9297 spin_lock_irq(&dev->event_lock);
9298 work = intel_crtc->unpin_work;
9299 intel_crtc->unpin_work = NULL;
9300 spin_unlock_irq(&dev->event_lock);
9301
9302 if (work) {
9303 cancel_work_sync(&work->work);
9304 kfree(work);
9305 }
9306
9307 intel_crtc_set_state(intel_crtc, NULL);
9308 drm_crtc_cleanup(crtc);
9309
9310 kfree(intel_crtc);
9311 }
9312
9313 static void intel_unpin_work_fn(struct work_struct *__work)
9314 {
9315 struct intel_unpin_work *work =
9316 container_of(__work, struct intel_unpin_work, work);
9317 struct drm_device *dev = work->crtc->dev;
9318 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9319
9320 mutex_lock(&dev->struct_mutex);
9321 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9322 drm_gem_object_unreference(&work->pending_flip_obj->base);
9323
9324 intel_fbc_update(dev);
9325
9326 if (work->flip_queued_req)
9327 i915_gem_request_assign(&work->flip_queued_req, NULL);
9328 mutex_unlock(&dev->struct_mutex);
9329
9330 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9331 drm_framebuffer_unreference(work->old_fb);
9332
9333 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9334 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9335
9336 kfree(work);
9337 }
9338
9339 static void do_intel_finish_page_flip(struct drm_device *dev,
9340 struct drm_crtc *crtc)
9341 {
9342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9343 struct intel_unpin_work *work;
9344 unsigned long flags;
9345
9346 /* Ignore early vblank irqs */
9347 if (intel_crtc == NULL)
9348 return;
9349
9350 /*
9351 * This is called both by irq handlers and the reset code (to complete
9352 * lost pageflips) so needs the full irqsave spinlocks.
9353 */
9354 spin_lock_irqsave(&dev->event_lock, flags);
9355 work = intel_crtc->unpin_work;
9356
9357 /* Ensure we don't miss a work->pending update ... */
9358 smp_rmb();
9359
9360 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9361 spin_unlock_irqrestore(&dev->event_lock, flags);
9362 return;
9363 }
9364
9365 page_flip_completed(intel_crtc);
9366
9367 spin_unlock_irqrestore(&dev->event_lock, flags);
9368 }
9369
9370 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9371 {
9372 struct drm_i915_private *dev_priv = dev->dev_private;
9373 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9374
9375 do_intel_finish_page_flip(dev, crtc);
9376 }
9377
9378 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9379 {
9380 struct drm_i915_private *dev_priv = dev->dev_private;
9381 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9382
9383 do_intel_finish_page_flip(dev, crtc);
9384 }
9385
9386 /* Is 'a' after or equal to 'b'? */
9387 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9388 {
9389 return !((a - b) & 0x80000000);
9390 }
9391
9392 static bool page_flip_finished(struct intel_crtc *crtc)
9393 {
9394 struct drm_device *dev = crtc->base.dev;
9395 struct drm_i915_private *dev_priv = dev->dev_private;
9396
9397 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9398 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9399 return true;
9400
9401 /*
9402 * The relevant registers doen't exist on pre-ctg.
9403 * As the flip done interrupt doesn't trigger for mmio
9404 * flips on gmch platforms, a flip count check isn't
9405 * really needed there. But since ctg has the registers,
9406 * include it in the check anyway.
9407 */
9408 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9409 return true;
9410
9411 /*
9412 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9413 * used the same base address. In that case the mmio flip might
9414 * have completed, but the CS hasn't even executed the flip yet.
9415 *
9416 * A flip count check isn't enough as the CS might have updated
9417 * the base address just after start of vblank, but before we
9418 * managed to process the interrupt. This means we'd complete the
9419 * CS flip too soon.
9420 *
9421 * Combining both checks should get us a good enough result. It may
9422 * still happen that the CS flip has been executed, but has not
9423 * yet actually completed. But in case the base address is the same
9424 * anyway, we don't really care.
9425 */
9426 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9427 crtc->unpin_work->gtt_offset &&
9428 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9429 crtc->unpin_work->flip_count);
9430 }
9431
9432 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9433 {
9434 struct drm_i915_private *dev_priv = dev->dev_private;
9435 struct intel_crtc *intel_crtc =
9436 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9437 unsigned long flags;
9438
9439
9440 /*
9441 * This is called both by irq handlers and the reset code (to complete
9442 * lost pageflips) so needs the full irqsave spinlocks.
9443 *
9444 * NB: An MMIO update of the plane base pointer will also
9445 * generate a page-flip completion irq, i.e. every modeset
9446 * is also accompanied by a spurious intel_prepare_page_flip().
9447 */
9448 spin_lock_irqsave(&dev->event_lock, flags);
9449 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9450 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9451 spin_unlock_irqrestore(&dev->event_lock, flags);
9452 }
9453
9454 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9455 {
9456 /* Ensure that the work item is consistent when activating it ... */
9457 smp_wmb();
9458 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9459 /* and that it is marked active as soon as the irq could fire. */
9460 smp_wmb();
9461 }
9462
9463 static int intel_gen2_queue_flip(struct drm_device *dev,
9464 struct drm_crtc *crtc,
9465 struct drm_framebuffer *fb,
9466 struct drm_i915_gem_object *obj,
9467 struct intel_engine_cs *ring,
9468 uint32_t flags)
9469 {
9470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9471 u32 flip_mask;
9472 int ret;
9473
9474 ret = intel_ring_begin(ring, 6);
9475 if (ret)
9476 return ret;
9477
9478 /* Can't queue multiple flips, so wait for the previous
9479 * one to finish before executing the next.
9480 */
9481 if (intel_crtc->plane)
9482 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9483 else
9484 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9485 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9486 intel_ring_emit(ring, MI_NOOP);
9487 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9488 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9489 intel_ring_emit(ring, fb->pitches[0]);
9490 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9491 intel_ring_emit(ring, 0); /* aux display base address, unused */
9492
9493 intel_mark_page_flip_active(intel_crtc);
9494 __intel_ring_advance(ring);
9495 return 0;
9496 }
9497
9498 static int intel_gen3_queue_flip(struct drm_device *dev,
9499 struct drm_crtc *crtc,
9500 struct drm_framebuffer *fb,
9501 struct drm_i915_gem_object *obj,
9502 struct intel_engine_cs *ring,
9503 uint32_t flags)
9504 {
9505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9506 u32 flip_mask;
9507 int ret;
9508
9509 ret = intel_ring_begin(ring, 6);
9510 if (ret)
9511 return ret;
9512
9513 if (intel_crtc->plane)
9514 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9515 else
9516 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9517 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9518 intel_ring_emit(ring, MI_NOOP);
9519 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9520 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9521 intel_ring_emit(ring, fb->pitches[0]);
9522 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9523 intel_ring_emit(ring, MI_NOOP);
9524
9525 intel_mark_page_flip_active(intel_crtc);
9526 __intel_ring_advance(ring);
9527 return 0;
9528 }
9529
9530 static int intel_gen4_queue_flip(struct drm_device *dev,
9531 struct drm_crtc *crtc,
9532 struct drm_framebuffer *fb,
9533 struct drm_i915_gem_object *obj,
9534 struct intel_engine_cs *ring,
9535 uint32_t flags)
9536 {
9537 struct drm_i915_private *dev_priv = dev->dev_private;
9538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9539 uint32_t pf, pipesrc;
9540 int ret;
9541
9542 ret = intel_ring_begin(ring, 4);
9543 if (ret)
9544 return ret;
9545
9546 /* i965+ uses the linear or tiled offsets from the
9547 * Display Registers (which do not change across a page-flip)
9548 * so we need only reprogram the base address.
9549 */
9550 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9551 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9552 intel_ring_emit(ring, fb->pitches[0]);
9553 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9554 obj->tiling_mode);
9555
9556 /* XXX Enabling the panel-fitter across page-flip is so far
9557 * untested on non-native modes, so ignore it for now.
9558 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9559 */
9560 pf = 0;
9561 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9562 intel_ring_emit(ring, pf | pipesrc);
9563
9564 intel_mark_page_flip_active(intel_crtc);
9565 __intel_ring_advance(ring);
9566 return 0;
9567 }
9568
9569 static int intel_gen6_queue_flip(struct drm_device *dev,
9570 struct drm_crtc *crtc,
9571 struct drm_framebuffer *fb,
9572 struct drm_i915_gem_object *obj,
9573 struct intel_engine_cs *ring,
9574 uint32_t flags)
9575 {
9576 struct drm_i915_private *dev_priv = dev->dev_private;
9577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9578 uint32_t pf, pipesrc;
9579 int ret;
9580
9581 ret = intel_ring_begin(ring, 4);
9582 if (ret)
9583 return ret;
9584
9585 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9586 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9587 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9588 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9589
9590 /* Contrary to the suggestions in the documentation,
9591 * "Enable Panel Fitter" does not seem to be required when page
9592 * flipping with a non-native mode, and worse causes a normal
9593 * modeset to fail.
9594 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9595 */
9596 pf = 0;
9597 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9598 intel_ring_emit(ring, pf | pipesrc);
9599
9600 intel_mark_page_flip_active(intel_crtc);
9601 __intel_ring_advance(ring);
9602 return 0;
9603 }
9604
9605 static int intel_gen7_queue_flip(struct drm_device *dev,
9606 struct drm_crtc *crtc,
9607 struct drm_framebuffer *fb,
9608 struct drm_i915_gem_object *obj,
9609 struct intel_engine_cs *ring,
9610 uint32_t flags)
9611 {
9612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9613 uint32_t plane_bit = 0;
9614 int len, ret;
9615
9616 switch (intel_crtc->plane) {
9617 case PLANE_A:
9618 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9619 break;
9620 case PLANE_B:
9621 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9622 break;
9623 case PLANE_C:
9624 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9625 break;
9626 default:
9627 WARN_ONCE(1, "unknown plane in flip command\n");
9628 return -ENODEV;
9629 }
9630
9631 len = 4;
9632 if (ring->id == RCS) {
9633 len += 6;
9634 /*
9635 * On Gen 8, SRM is now taking an extra dword to accommodate
9636 * 48bits addresses, and we need a NOOP for the batch size to
9637 * stay even.
9638 */
9639 if (IS_GEN8(dev))
9640 len += 2;
9641 }
9642
9643 /*
9644 * BSpec MI_DISPLAY_FLIP for IVB:
9645 * "The full packet must be contained within the same cache line."
9646 *
9647 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9648 * cacheline, if we ever start emitting more commands before
9649 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9650 * then do the cacheline alignment, and finally emit the
9651 * MI_DISPLAY_FLIP.
9652 */
9653 ret = intel_ring_cacheline_align(ring);
9654 if (ret)
9655 return ret;
9656
9657 ret = intel_ring_begin(ring, len);
9658 if (ret)
9659 return ret;
9660
9661 /* Unmask the flip-done completion message. Note that the bspec says that
9662 * we should do this for both the BCS and RCS, and that we must not unmask
9663 * more than one flip event at any time (or ensure that one flip message
9664 * can be sent by waiting for flip-done prior to queueing new flips).
9665 * Experimentation says that BCS works despite DERRMR masking all
9666 * flip-done completion events and that unmasking all planes at once
9667 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9668 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9669 */
9670 if (ring->id == RCS) {
9671 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9672 intel_ring_emit(ring, DERRMR);
9673 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9674 DERRMR_PIPEB_PRI_FLIP_DONE |
9675 DERRMR_PIPEC_PRI_FLIP_DONE));
9676 if (IS_GEN8(dev))
9677 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9678 MI_SRM_LRM_GLOBAL_GTT);
9679 else
9680 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9681 MI_SRM_LRM_GLOBAL_GTT);
9682 intel_ring_emit(ring, DERRMR);
9683 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9684 if (IS_GEN8(dev)) {
9685 intel_ring_emit(ring, 0);
9686 intel_ring_emit(ring, MI_NOOP);
9687 }
9688 }
9689
9690 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9691 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9692 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9693 intel_ring_emit(ring, (MI_NOOP));
9694
9695 intel_mark_page_flip_active(intel_crtc);
9696 __intel_ring_advance(ring);
9697 return 0;
9698 }
9699
9700 static bool use_mmio_flip(struct intel_engine_cs *ring,
9701 struct drm_i915_gem_object *obj)
9702 {
9703 /*
9704 * This is not being used for older platforms, because
9705 * non-availability of flip done interrupt forces us to use
9706 * CS flips. Older platforms derive flip done using some clever
9707 * tricks involving the flip_pending status bits and vblank irqs.
9708 * So using MMIO flips there would disrupt this mechanism.
9709 */
9710
9711 if (ring == NULL)
9712 return true;
9713
9714 if (INTEL_INFO(ring->dev)->gen < 5)
9715 return false;
9716
9717 if (i915.use_mmio_flip < 0)
9718 return false;
9719 else if (i915.use_mmio_flip > 0)
9720 return true;
9721 else if (i915.enable_execlists)
9722 return true;
9723 else
9724 return ring != i915_gem_request_get_ring(obj->last_read_req);
9725 }
9726
9727 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9728 {
9729 struct drm_device *dev = intel_crtc->base.dev;
9730 struct drm_i915_private *dev_priv = dev->dev_private;
9731 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9732 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9733 struct drm_i915_gem_object *obj = intel_fb->obj;
9734 const enum pipe pipe = intel_crtc->pipe;
9735 u32 ctl, stride;
9736
9737 ctl = I915_READ(PLANE_CTL(pipe, 0));
9738 ctl &= ~PLANE_CTL_TILED_MASK;
9739 if (obj->tiling_mode == I915_TILING_X)
9740 ctl |= PLANE_CTL_TILED_X;
9741
9742 /*
9743 * The stride is either expressed as a multiple of 64 bytes chunks for
9744 * linear buffers or in number of tiles for tiled buffers.
9745 */
9746 stride = fb->pitches[0] >> 6;
9747 if (obj->tiling_mode == I915_TILING_X)
9748 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9749
9750 /*
9751 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9752 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9753 */
9754 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9755 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9756
9757 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9758 POSTING_READ(PLANE_SURF(pipe, 0));
9759 }
9760
9761 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9762 {
9763 struct drm_device *dev = intel_crtc->base.dev;
9764 struct drm_i915_private *dev_priv = dev->dev_private;
9765 struct intel_framebuffer *intel_fb =
9766 to_intel_framebuffer(intel_crtc->base.primary->fb);
9767 struct drm_i915_gem_object *obj = intel_fb->obj;
9768 u32 dspcntr;
9769 u32 reg;
9770
9771 reg = DSPCNTR(intel_crtc->plane);
9772 dspcntr = I915_READ(reg);
9773
9774 if (obj->tiling_mode != I915_TILING_NONE)
9775 dspcntr |= DISPPLANE_TILED;
9776 else
9777 dspcntr &= ~DISPPLANE_TILED;
9778
9779 I915_WRITE(reg, dspcntr);
9780
9781 I915_WRITE(DSPSURF(intel_crtc->plane),
9782 intel_crtc->unpin_work->gtt_offset);
9783 POSTING_READ(DSPSURF(intel_crtc->plane));
9784
9785 }
9786
9787 /*
9788 * XXX: This is the temporary way to update the plane registers until we get
9789 * around to using the usual plane update functions for MMIO flips
9790 */
9791 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9792 {
9793 struct drm_device *dev = intel_crtc->base.dev;
9794 bool atomic_update;
9795 u32 start_vbl_count;
9796
9797 intel_mark_page_flip_active(intel_crtc);
9798
9799 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9800
9801 if (INTEL_INFO(dev)->gen >= 9)
9802 skl_do_mmio_flip(intel_crtc);
9803 else
9804 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9805 ilk_do_mmio_flip(intel_crtc);
9806
9807 if (atomic_update)
9808 intel_pipe_update_end(intel_crtc, start_vbl_count);
9809 }
9810
9811 static void intel_mmio_flip_work_func(struct work_struct *work)
9812 {
9813 struct intel_crtc *crtc =
9814 container_of(work, struct intel_crtc, mmio_flip.work);
9815 struct intel_mmio_flip *mmio_flip;
9816
9817 mmio_flip = &crtc->mmio_flip;
9818 if (mmio_flip->req)
9819 WARN_ON(__i915_wait_request(mmio_flip->req,
9820 crtc->reset_counter,
9821 false, NULL, NULL) != 0);
9822
9823 intel_do_mmio_flip(crtc);
9824 if (mmio_flip->req) {
9825 mutex_lock(&crtc->base.dev->struct_mutex);
9826 i915_gem_request_assign(&mmio_flip->req, NULL);
9827 mutex_unlock(&crtc->base.dev->struct_mutex);
9828 }
9829 }
9830
9831 static int intel_queue_mmio_flip(struct drm_device *dev,
9832 struct drm_crtc *crtc,
9833 struct drm_framebuffer *fb,
9834 struct drm_i915_gem_object *obj,
9835 struct intel_engine_cs *ring,
9836 uint32_t flags)
9837 {
9838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9839
9840 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9841 obj->last_write_req);
9842
9843 schedule_work(&intel_crtc->mmio_flip.work);
9844
9845 return 0;
9846 }
9847
9848 static int intel_default_queue_flip(struct drm_device *dev,
9849 struct drm_crtc *crtc,
9850 struct drm_framebuffer *fb,
9851 struct drm_i915_gem_object *obj,
9852 struct intel_engine_cs *ring,
9853 uint32_t flags)
9854 {
9855 return -ENODEV;
9856 }
9857
9858 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9859 struct drm_crtc *crtc)
9860 {
9861 struct drm_i915_private *dev_priv = dev->dev_private;
9862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9863 struct intel_unpin_work *work = intel_crtc->unpin_work;
9864 u32 addr;
9865
9866 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9867 return true;
9868
9869 if (!work->enable_stall_check)
9870 return false;
9871
9872 if (work->flip_ready_vblank == 0) {
9873 if (work->flip_queued_req &&
9874 !i915_gem_request_completed(work->flip_queued_req, true))
9875 return false;
9876
9877 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9878 }
9879
9880 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9881 return false;
9882
9883 /* Potential stall - if we see that the flip has happened,
9884 * assume a missed interrupt. */
9885 if (INTEL_INFO(dev)->gen >= 4)
9886 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9887 else
9888 addr = I915_READ(DSPADDR(intel_crtc->plane));
9889
9890 /* There is a potential issue here with a false positive after a flip
9891 * to the same address. We could address this by checking for a
9892 * non-incrementing frame counter.
9893 */
9894 return addr == work->gtt_offset;
9895 }
9896
9897 void intel_check_page_flip(struct drm_device *dev, int pipe)
9898 {
9899 struct drm_i915_private *dev_priv = dev->dev_private;
9900 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9902
9903 WARN_ON(!in_interrupt());
9904
9905 if (crtc == NULL)
9906 return;
9907
9908 spin_lock(&dev->event_lock);
9909 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9910 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9911 intel_crtc->unpin_work->flip_queued_vblank,
9912 drm_vblank_count(dev, pipe));
9913 page_flip_completed(intel_crtc);
9914 }
9915 spin_unlock(&dev->event_lock);
9916 }
9917
9918 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9919 struct drm_framebuffer *fb,
9920 struct drm_pending_vblank_event *event,
9921 uint32_t page_flip_flags)
9922 {
9923 struct drm_device *dev = crtc->dev;
9924 struct drm_i915_private *dev_priv = dev->dev_private;
9925 struct drm_framebuffer *old_fb = crtc->primary->fb;
9926 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9928 struct drm_plane *primary = crtc->primary;
9929 enum pipe pipe = intel_crtc->pipe;
9930 struct intel_unpin_work *work;
9931 struct intel_engine_cs *ring;
9932 int ret;
9933
9934 /*
9935 * drm_mode_page_flip_ioctl() should already catch this, but double
9936 * check to be safe. In the future we may enable pageflipping from
9937 * a disabled primary plane.
9938 */
9939 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9940 return -EBUSY;
9941
9942 /* Can't change pixel format via MI display flips. */
9943 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9944 return -EINVAL;
9945
9946 /*
9947 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9948 * Note that pitch changes could also affect these register.
9949 */
9950 if (INTEL_INFO(dev)->gen > 3 &&
9951 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9952 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9953 return -EINVAL;
9954
9955 if (i915_terminally_wedged(&dev_priv->gpu_error))
9956 goto out_hang;
9957
9958 work = kzalloc(sizeof(*work), GFP_KERNEL);
9959 if (work == NULL)
9960 return -ENOMEM;
9961
9962 work->event = event;
9963 work->crtc = crtc;
9964 work->old_fb = old_fb;
9965 INIT_WORK(&work->work, intel_unpin_work_fn);
9966
9967 ret = drm_crtc_vblank_get(crtc);
9968 if (ret)
9969 goto free_work;
9970
9971 /* We borrow the event spin lock for protecting unpin_work */
9972 spin_lock_irq(&dev->event_lock);
9973 if (intel_crtc->unpin_work) {
9974 /* Before declaring the flip queue wedged, check if
9975 * the hardware completed the operation behind our backs.
9976 */
9977 if (__intel_pageflip_stall_check(dev, crtc)) {
9978 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9979 page_flip_completed(intel_crtc);
9980 } else {
9981 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9982 spin_unlock_irq(&dev->event_lock);
9983
9984 drm_crtc_vblank_put(crtc);
9985 kfree(work);
9986 return -EBUSY;
9987 }
9988 }
9989 intel_crtc->unpin_work = work;
9990 spin_unlock_irq(&dev->event_lock);
9991
9992 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9993 flush_workqueue(dev_priv->wq);
9994
9995 /* Reference the objects for the scheduled work. */
9996 drm_framebuffer_reference(work->old_fb);
9997 drm_gem_object_reference(&obj->base);
9998
9999 crtc->primary->fb = fb;
10000 update_state_fb(crtc->primary);
10001
10002 work->pending_flip_obj = obj;
10003
10004 ret = i915_mutex_lock_interruptible(dev);
10005 if (ret)
10006 goto cleanup;
10007
10008 atomic_inc(&intel_crtc->unpin_work_count);
10009 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10010
10011 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10012 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10013
10014 if (IS_VALLEYVIEW(dev)) {
10015 ring = &dev_priv->ring[BCS];
10016 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10017 /* vlv: DISPLAY_FLIP fails to change tiling */
10018 ring = NULL;
10019 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10020 ring = &dev_priv->ring[BCS];
10021 } else if (INTEL_INFO(dev)->gen >= 7) {
10022 ring = i915_gem_request_get_ring(obj->last_read_req);
10023 if (ring == NULL || ring->id != RCS)
10024 ring = &dev_priv->ring[BCS];
10025 } else {
10026 ring = &dev_priv->ring[RCS];
10027 }
10028
10029 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
10030 if (ret)
10031 goto cleanup_pending;
10032
10033 work->gtt_offset =
10034 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10035
10036 if (use_mmio_flip(ring, obj)) {
10037 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10038 page_flip_flags);
10039 if (ret)
10040 goto cleanup_unpin;
10041
10042 i915_gem_request_assign(&work->flip_queued_req,
10043 obj->last_write_req);
10044 } else {
10045 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10046 page_flip_flags);
10047 if (ret)
10048 goto cleanup_unpin;
10049
10050 i915_gem_request_assign(&work->flip_queued_req,
10051 intel_ring_get_request(ring));
10052 }
10053
10054 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10055 work->enable_stall_check = true;
10056
10057 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10058 INTEL_FRONTBUFFER_PRIMARY(pipe));
10059
10060 intel_fbc_disable(dev);
10061 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10062 mutex_unlock(&dev->struct_mutex);
10063
10064 trace_i915_flip_request(intel_crtc->plane, obj);
10065
10066 return 0;
10067
10068 cleanup_unpin:
10069 intel_unpin_fb_obj(obj);
10070 cleanup_pending:
10071 atomic_dec(&intel_crtc->unpin_work_count);
10072 mutex_unlock(&dev->struct_mutex);
10073 cleanup:
10074 crtc->primary->fb = old_fb;
10075 update_state_fb(crtc->primary);
10076
10077 drm_gem_object_unreference_unlocked(&obj->base);
10078 drm_framebuffer_unreference(work->old_fb);
10079
10080 spin_lock_irq(&dev->event_lock);
10081 intel_crtc->unpin_work = NULL;
10082 spin_unlock_irq(&dev->event_lock);
10083
10084 drm_crtc_vblank_put(crtc);
10085 free_work:
10086 kfree(work);
10087
10088 if (ret == -EIO) {
10089 out_hang:
10090 ret = intel_plane_restore(primary);
10091 if (ret == 0 && event) {
10092 spin_lock_irq(&dev->event_lock);
10093 drm_send_vblank_event(dev, pipe, event);
10094 spin_unlock_irq(&dev->event_lock);
10095 }
10096 }
10097 return ret;
10098 }
10099
10100 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10101 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10102 .load_lut = intel_crtc_load_lut,
10103 .atomic_begin = intel_begin_crtc_commit,
10104 .atomic_flush = intel_finish_crtc_commit,
10105 };
10106
10107 /**
10108 * intel_modeset_update_staged_output_state
10109 *
10110 * Updates the staged output configuration state, e.g. after we've read out the
10111 * current hw state.
10112 */
10113 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10114 {
10115 struct intel_crtc *crtc;
10116 struct intel_encoder *encoder;
10117 struct intel_connector *connector;
10118
10119 for_each_intel_connector(dev, connector) {
10120 connector->new_encoder =
10121 to_intel_encoder(connector->base.encoder);
10122 }
10123
10124 for_each_intel_encoder(dev, encoder) {
10125 encoder->new_crtc =
10126 to_intel_crtc(encoder->base.crtc);
10127 }
10128
10129 for_each_intel_crtc(dev, crtc) {
10130 crtc->new_enabled = crtc->base.state->enable;
10131
10132 if (crtc->new_enabled)
10133 crtc->new_config = crtc->config;
10134 else
10135 crtc->new_config = NULL;
10136 }
10137 }
10138
10139 /**
10140 * intel_modeset_commit_output_state
10141 *
10142 * This function copies the stage display pipe configuration to the real one.
10143 */
10144 static void intel_modeset_commit_output_state(struct drm_device *dev)
10145 {
10146 struct intel_crtc *crtc;
10147 struct intel_encoder *encoder;
10148 struct intel_connector *connector;
10149
10150 for_each_intel_connector(dev, connector) {
10151 connector->base.encoder = &connector->new_encoder->base;
10152 }
10153
10154 for_each_intel_encoder(dev, encoder) {
10155 encoder->base.crtc = &encoder->new_crtc->base;
10156 }
10157
10158 for_each_intel_crtc(dev, crtc) {
10159 crtc->base.state->enable = crtc->new_enabled;
10160 crtc->base.enabled = crtc->new_enabled;
10161 }
10162 }
10163
10164 static void
10165 connected_sink_compute_bpp(struct intel_connector *connector,
10166 struct intel_crtc_state *pipe_config)
10167 {
10168 int bpp = pipe_config->pipe_bpp;
10169
10170 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10171 connector->base.base.id,
10172 connector->base.name);
10173
10174 /* Don't use an invalid EDID bpc value */
10175 if (connector->base.display_info.bpc &&
10176 connector->base.display_info.bpc * 3 < bpp) {
10177 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10178 bpp, connector->base.display_info.bpc*3);
10179 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10180 }
10181
10182 /* Clamp bpp to 8 on screens without EDID 1.4 */
10183 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10184 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10185 bpp);
10186 pipe_config->pipe_bpp = 24;
10187 }
10188 }
10189
10190 static int
10191 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10192 struct drm_framebuffer *fb,
10193 struct intel_crtc_state *pipe_config)
10194 {
10195 struct drm_device *dev = crtc->base.dev;
10196 struct intel_connector *connector;
10197 int bpp;
10198
10199 switch (fb->pixel_format) {
10200 case DRM_FORMAT_C8:
10201 bpp = 8*3; /* since we go through a colormap */
10202 break;
10203 case DRM_FORMAT_XRGB1555:
10204 case DRM_FORMAT_ARGB1555:
10205 /* checked in intel_framebuffer_init already */
10206 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10207 return -EINVAL;
10208 case DRM_FORMAT_RGB565:
10209 bpp = 6*3; /* min is 18bpp */
10210 break;
10211 case DRM_FORMAT_XBGR8888:
10212 case DRM_FORMAT_ABGR8888:
10213 /* checked in intel_framebuffer_init already */
10214 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10215 return -EINVAL;
10216 case DRM_FORMAT_XRGB8888:
10217 case DRM_FORMAT_ARGB8888:
10218 bpp = 8*3;
10219 break;
10220 case DRM_FORMAT_XRGB2101010:
10221 case DRM_FORMAT_ARGB2101010:
10222 case DRM_FORMAT_XBGR2101010:
10223 case DRM_FORMAT_ABGR2101010:
10224 /* checked in intel_framebuffer_init already */
10225 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10226 return -EINVAL;
10227 bpp = 10*3;
10228 break;
10229 /* TODO: gen4+ supports 16 bpc floating point, too. */
10230 default:
10231 DRM_DEBUG_KMS("unsupported depth\n");
10232 return -EINVAL;
10233 }
10234
10235 pipe_config->pipe_bpp = bpp;
10236
10237 /* Clamp display bpp to EDID value */
10238 for_each_intel_connector(dev, connector) {
10239 if (!connector->new_encoder ||
10240 connector->new_encoder->new_crtc != crtc)
10241 continue;
10242
10243 connected_sink_compute_bpp(connector, pipe_config);
10244 }
10245
10246 return bpp;
10247 }
10248
10249 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10250 {
10251 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10252 "type: 0x%x flags: 0x%x\n",
10253 mode->crtc_clock,
10254 mode->crtc_hdisplay, mode->crtc_hsync_start,
10255 mode->crtc_hsync_end, mode->crtc_htotal,
10256 mode->crtc_vdisplay, mode->crtc_vsync_start,
10257 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10258 }
10259
10260 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10261 struct intel_crtc_state *pipe_config,
10262 const char *context)
10263 {
10264 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10265 context, pipe_name(crtc->pipe));
10266
10267 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10268 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10269 pipe_config->pipe_bpp, pipe_config->dither);
10270 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10271 pipe_config->has_pch_encoder,
10272 pipe_config->fdi_lanes,
10273 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10274 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10275 pipe_config->fdi_m_n.tu);
10276 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10277 pipe_config->has_dp_encoder,
10278 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10279 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10280 pipe_config->dp_m_n.tu);
10281
10282 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10283 pipe_config->has_dp_encoder,
10284 pipe_config->dp_m2_n2.gmch_m,
10285 pipe_config->dp_m2_n2.gmch_n,
10286 pipe_config->dp_m2_n2.link_m,
10287 pipe_config->dp_m2_n2.link_n,
10288 pipe_config->dp_m2_n2.tu);
10289
10290 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10291 pipe_config->has_audio,
10292 pipe_config->has_infoframe);
10293
10294 DRM_DEBUG_KMS("requested mode:\n");
10295 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10296 DRM_DEBUG_KMS("adjusted mode:\n");
10297 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10298 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10299 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10300 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10301 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10302 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10303 pipe_config->gmch_pfit.control,
10304 pipe_config->gmch_pfit.pgm_ratios,
10305 pipe_config->gmch_pfit.lvds_border_bits);
10306 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10307 pipe_config->pch_pfit.pos,
10308 pipe_config->pch_pfit.size,
10309 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10310 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10311 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10312 }
10313
10314 static bool encoders_cloneable(const struct intel_encoder *a,
10315 const struct intel_encoder *b)
10316 {
10317 /* masks could be asymmetric, so check both ways */
10318 return a == b || (a->cloneable & (1 << b->type) &&
10319 b->cloneable & (1 << a->type));
10320 }
10321
10322 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10323 struct intel_encoder *encoder)
10324 {
10325 struct drm_device *dev = crtc->base.dev;
10326 struct intel_encoder *source_encoder;
10327
10328 for_each_intel_encoder(dev, source_encoder) {
10329 if (source_encoder->new_crtc != crtc)
10330 continue;
10331
10332 if (!encoders_cloneable(encoder, source_encoder))
10333 return false;
10334 }
10335
10336 return true;
10337 }
10338
10339 static bool check_encoder_cloning(struct intel_crtc *crtc)
10340 {
10341 struct drm_device *dev = crtc->base.dev;
10342 struct intel_encoder *encoder;
10343
10344 for_each_intel_encoder(dev, encoder) {
10345 if (encoder->new_crtc != crtc)
10346 continue;
10347
10348 if (!check_single_encoder_cloning(crtc, encoder))
10349 return false;
10350 }
10351
10352 return true;
10353 }
10354
10355 static bool check_digital_port_conflicts(struct drm_device *dev)
10356 {
10357 struct intel_connector *connector;
10358 unsigned int used_ports = 0;
10359
10360 /*
10361 * Walk the connector list instead of the encoder
10362 * list to detect the problem on ddi platforms
10363 * where there's just one encoder per digital port.
10364 */
10365 for_each_intel_connector(dev, connector) {
10366 struct intel_encoder *encoder = connector->new_encoder;
10367
10368 if (!encoder)
10369 continue;
10370
10371 WARN_ON(!encoder->new_crtc);
10372
10373 switch (encoder->type) {
10374 unsigned int port_mask;
10375 case INTEL_OUTPUT_UNKNOWN:
10376 if (WARN_ON(!HAS_DDI(dev)))
10377 break;
10378 case INTEL_OUTPUT_DISPLAYPORT:
10379 case INTEL_OUTPUT_HDMI:
10380 case INTEL_OUTPUT_EDP:
10381 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10382
10383 /* the same port mustn't appear more than once */
10384 if (used_ports & port_mask)
10385 return false;
10386
10387 used_ports |= port_mask;
10388 default:
10389 break;
10390 }
10391 }
10392
10393 return true;
10394 }
10395
10396 static struct intel_crtc_state *
10397 intel_modeset_pipe_config(struct drm_crtc *crtc,
10398 struct drm_framebuffer *fb,
10399 struct drm_display_mode *mode)
10400 {
10401 struct drm_device *dev = crtc->dev;
10402 struct intel_encoder *encoder;
10403 struct intel_crtc_state *pipe_config;
10404 int plane_bpp, ret = -EINVAL;
10405 bool retry = true;
10406
10407 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10408 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10409 return ERR_PTR(-EINVAL);
10410 }
10411
10412 if (!check_digital_port_conflicts(dev)) {
10413 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10414 return ERR_PTR(-EINVAL);
10415 }
10416
10417 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10418 if (!pipe_config)
10419 return ERR_PTR(-ENOMEM);
10420
10421 pipe_config->base.crtc = crtc;
10422 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10423 drm_mode_copy(&pipe_config->base.mode, mode);
10424
10425 pipe_config->cpu_transcoder =
10426 (enum transcoder) to_intel_crtc(crtc)->pipe;
10427 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10428
10429 /*
10430 * Sanitize sync polarity flags based on requested ones. If neither
10431 * positive or negative polarity is requested, treat this as meaning
10432 * negative polarity.
10433 */
10434 if (!(pipe_config->base.adjusted_mode.flags &
10435 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10436 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10437
10438 if (!(pipe_config->base.adjusted_mode.flags &
10439 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10440 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10441
10442 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10443 * plane pixel format and any sink constraints into account. Returns the
10444 * source plane bpp so that dithering can be selected on mismatches
10445 * after encoders and crtc also have had their say. */
10446 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10447 fb, pipe_config);
10448 if (plane_bpp < 0)
10449 goto fail;
10450
10451 /*
10452 * Determine the real pipe dimensions. Note that stereo modes can
10453 * increase the actual pipe size due to the frame doubling and
10454 * insertion of additional space for blanks between the frame. This
10455 * is stored in the crtc timings. We use the requested mode to do this
10456 * computation to clearly distinguish it from the adjusted mode, which
10457 * can be changed by the connectors in the below retry loop.
10458 */
10459 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10460 &pipe_config->pipe_src_w,
10461 &pipe_config->pipe_src_h);
10462
10463 encoder_retry:
10464 /* Ensure the port clock defaults are reset when retrying. */
10465 pipe_config->port_clock = 0;
10466 pipe_config->pixel_multiplier = 1;
10467
10468 /* Fill in default crtc timings, allow encoders to overwrite them. */
10469 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10470 CRTC_STEREO_DOUBLE);
10471
10472 /* Pass our mode to the connectors and the CRTC to give them a chance to
10473 * adjust it according to limitations or connector properties, and also
10474 * a chance to reject the mode entirely.
10475 */
10476 for_each_intel_encoder(dev, encoder) {
10477
10478 if (&encoder->new_crtc->base != crtc)
10479 continue;
10480
10481 if (!(encoder->compute_config(encoder, pipe_config))) {
10482 DRM_DEBUG_KMS("Encoder config failure\n");
10483 goto fail;
10484 }
10485 }
10486
10487 /* Set default port clock if not overwritten by the encoder. Needs to be
10488 * done afterwards in case the encoder adjusts the mode. */
10489 if (!pipe_config->port_clock)
10490 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10491 * pipe_config->pixel_multiplier;
10492
10493 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10494 if (ret < 0) {
10495 DRM_DEBUG_KMS("CRTC fixup failed\n");
10496 goto fail;
10497 }
10498
10499 if (ret == RETRY) {
10500 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10501 ret = -EINVAL;
10502 goto fail;
10503 }
10504
10505 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10506 retry = false;
10507 goto encoder_retry;
10508 }
10509
10510 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10511 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10512 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10513
10514 return pipe_config;
10515 fail:
10516 kfree(pipe_config);
10517 return ERR_PTR(ret);
10518 }
10519
10520 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10521 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10522 static void
10523 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10524 unsigned *prepare_pipes, unsigned *disable_pipes)
10525 {
10526 struct intel_crtc *intel_crtc;
10527 struct drm_device *dev = crtc->dev;
10528 struct intel_encoder *encoder;
10529 struct intel_connector *connector;
10530 struct drm_crtc *tmp_crtc;
10531
10532 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10533
10534 /* Check which crtcs have changed outputs connected to them, these need
10535 * to be part of the prepare_pipes mask. We don't (yet) support global
10536 * modeset across multiple crtcs, so modeset_pipes will only have one
10537 * bit set at most. */
10538 for_each_intel_connector(dev, connector) {
10539 if (connector->base.encoder == &connector->new_encoder->base)
10540 continue;
10541
10542 if (connector->base.encoder) {
10543 tmp_crtc = connector->base.encoder->crtc;
10544
10545 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10546 }
10547
10548 if (connector->new_encoder)
10549 *prepare_pipes |=
10550 1 << connector->new_encoder->new_crtc->pipe;
10551 }
10552
10553 for_each_intel_encoder(dev, encoder) {
10554 if (encoder->base.crtc == &encoder->new_crtc->base)
10555 continue;
10556
10557 if (encoder->base.crtc) {
10558 tmp_crtc = encoder->base.crtc;
10559
10560 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10561 }
10562
10563 if (encoder->new_crtc)
10564 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10565 }
10566
10567 /* Check for pipes that will be enabled/disabled ... */
10568 for_each_intel_crtc(dev, intel_crtc) {
10569 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10570 continue;
10571
10572 if (!intel_crtc->new_enabled)
10573 *disable_pipes |= 1 << intel_crtc->pipe;
10574 else
10575 *prepare_pipes |= 1 << intel_crtc->pipe;
10576 }
10577
10578
10579 /* set_mode is also used to update properties on life display pipes. */
10580 intel_crtc = to_intel_crtc(crtc);
10581 if (intel_crtc->new_enabled)
10582 *prepare_pipes |= 1 << intel_crtc->pipe;
10583
10584 /*
10585 * For simplicity do a full modeset on any pipe where the output routing
10586 * changed. We could be more clever, but that would require us to be
10587 * more careful with calling the relevant encoder->mode_set functions.
10588 */
10589 if (*prepare_pipes)
10590 *modeset_pipes = *prepare_pipes;
10591
10592 /* ... and mask these out. */
10593 *modeset_pipes &= ~(*disable_pipes);
10594 *prepare_pipes &= ~(*disable_pipes);
10595
10596 /*
10597 * HACK: We don't (yet) fully support global modesets. intel_set_config
10598 * obies this rule, but the modeset restore mode of
10599 * intel_modeset_setup_hw_state does not.
10600 */
10601 *modeset_pipes &= 1 << intel_crtc->pipe;
10602 *prepare_pipes &= 1 << intel_crtc->pipe;
10603
10604 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10605 *modeset_pipes, *prepare_pipes, *disable_pipes);
10606 }
10607
10608 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10609 {
10610 struct drm_encoder *encoder;
10611 struct drm_device *dev = crtc->dev;
10612
10613 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10614 if (encoder->crtc == crtc)
10615 return true;
10616
10617 return false;
10618 }
10619
10620 static void
10621 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10622 {
10623 struct drm_i915_private *dev_priv = dev->dev_private;
10624 struct intel_encoder *intel_encoder;
10625 struct intel_crtc *intel_crtc;
10626 struct drm_connector *connector;
10627
10628 intel_shared_dpll_commit(dev_priv);
10629
10630 for_each_intel_encoder(dev, intel_encoder) {
10631 if (!intel_encoder->base.crtc)
10632 continue;
10633
10634 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10635
10636 if (prepare_pipes & (1 << intel_crtc->pipe))
10637 intel_encoder->connectors_active = false;
10638 }
10639
10640 intel_modeset_commit_output_state(dev);
10641
10642 /* Double check state. */
10643 for_each_intel_crtc(dev, intel_crtc) {
10644 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10645 WARN_ON(intel_crtc->new_config &&
10646 intel_crtc->new_config != intel_crtc->config);
10647 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10648 }
10649
10650 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10651 if (!connector->encoder || !connector->encoder->crtc)
10652 continue;
10653
10654 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10655
10656 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10657 struct drm_property *dpms_property =
10658 dev->mode_config.dpms_property;
10659
10660 connector->dpms = DRM_MODE_DPMS_ON;
10661 drm_object_property_set_value(&connector->base,
10662 dpms_property,
10663 DRM_MODE_DPMS_ON);
10664
10665 intel_encoder = to_intel_encoder(connector->encoder);
10666 intel_encoder->connectors_active = true;
10667 }
10668 }
10669
10670 }
10671
10672 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10673 {
10674 int diff;
10675
10676 if (clock1 == clock2)
10677 return true;
10678
10679 if (!clock1 || !clock2)
10680 return false;
10681
10682 diff = abs(clock1 - clock2);
10683
10684 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10685 return true;
10686
10687 return false;
10688 }
10689
10690 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10691 list_for_each_entry((intel_crtc), \
10692 &(dev)->mode_config.crtc_list, \
10693 base.head) \
10694 if (mask & (1 <<(intel_crtc)->pipe))
10695
10696 static bool
10697 intel_pipe_config_compare(struct drm_device *dev,
10698 struct intel_crtc_state *current_config,
10699 struct intel_crtc_state *pipe_config)
10700 {
10701 #define PIPE_CONF_CHECK_X(name) \
10702 if (current_config->name != pipe_config->name) { \
10703 DRM_ERROR("mismatch in " #name " " \
10704 "(expected 0x%08x, found 0x%08x)\n", \
10705 current_config->name, \
10706 pipe_config->name); \
10707 return false; \
10708 }
10709
10710 #define PIPE_CONF_CHECK_I(name) \
10711 if (current_config->name != pipe_config->name) { \
10712 DRM_ERROR("mismatch in " #name " " \
10713 "(expected %i, found %i)\n", \
10714 current_config->name, \
10715 pipe_config->name); \
10716 return false; \
10717 }
10718
10719 /* This is required for BDW+ where there is only one set of registers for
10720 * switching between high and low RR.
10721 * This macro can be used whenever a comparison has to be made between one
10722 * hw state and multiple sw state variables.
10723 */
10724 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10725 if ((current_config->name != pipe_config->name) && \
10726 (current_config->alt_name != pipe_config->name)) { \
10727 DRM_ERROR("mismatch in " #name " " \
10728 "(expected %i or %i, found %i)\n", \
10729 current_config->name, \
10730 current_config->alt_name, \
10731 pipe_config->name); \
10732 return false; \
10733 }
10734
10735 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10736 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10737 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10738 "(expected %i, found %i)\n", \
10739 current_config->name & (mask), \
10740 pipe_config->name & (mask)); \
10741 return false; \
10742 }
10743
10744 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10745 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10746 DRM_ERROR("mismatch in " #name " " \
10747 "(expected %i, found %i)\n", \
10748 current_config->name, \
10749 pipe_config->name); \
10750 return false; \
10751 }
10752
10753 #define PIPE_CONF_QUIRK(quirk) \
10754 ((current_config->quirks | pipe_config->quirks) & (quirk))
10755
10756 PIPE_CONF_CHECK_I(cpu_transcoder);
10757
10758 PIPE_CONF_CHECK_I(has_pch_encoder);
10759 PIPE_CONF_CHECK_I(fdi_lanes);
10760 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10761 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10762 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10763 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10764 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10765
10766 PIPE_CONF_CHECK_I(has_dp_encoder);
10767
10768 if (INTEL_INFO(dev)->gen < 8) {
10769 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10770 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10771 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10772 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10773 PIPE_CONF_CHECK_I(dp_m_n.tu);
10774
10775 if (current_config->has_drrs) {
10776 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10777 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10778 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10779 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10780 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10781 }
10782 } else {
10783 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10784 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10785 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10786 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10787 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10788 }
10789
10790 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10791 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10792 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10793 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10794 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10795 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10796
10797 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10798 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10799 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10800 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10801 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10802 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10803
10804 PIPE_CONF_CHECK_I(pixel_multiplier);
10805 PIPE_CONF_CHECK_I(has_hdmi_sink);
10806 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10807 IS_VALLEYVIEW(dev))
10808 PIPE_CONF_CHECK_I(limited_color_range);
10809 PIPE_CONF_CHECK_I(has_infoframe);
10810
10811 PIPE_CONF_CHECK_I(has_audio);
10812
10813 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10814 DRM_MODE_FLAG_INTERLACE);
10815
10816 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10817 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10818 DRM_MODE_FLAG_PHSYNC);
10819 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10820 DRM_MODE_FLAG_NHSYNC);
10821 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10822 DRM_MODE_FLAG_PVSYNC);
10823 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10824 DRM_MODE_FLAG_NVSYNC);
10825 }
10826
10827 PIPE_CONF_CHECK_I(pipe_src_w);
10828 PIPE_CONF_CHECK_I(pipe_src_h);
10829
10830 /*
10831 * FIXME: BIOS likes to set up a cloned config with lvds+external
10832 * screen. Since we don't yet re-compute the pipe config when moving
10833 * just the lvds port away to another pipe the sw tracking won't match.
10834 *
10835 * Proper atomic modesets with recomputed global state will fix this.
10836 * Until then just don't check gmch state for inherited modes.
10837 */
10838 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10839 PIPE_CONF_CHECK_I(gmch_pfit.control);
10840 /* pfit ratios are autocomputed by the hw on gen4+ */
10841 if (INTEL_INFO(dev)->gen < 4)
10842 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10843 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10844 }
10845
10846 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10847 if (current_config->pch_pfit.enabled) {
10848 PIPE_CONF_CHECK_I(pch_pfit.pos);
10849 PIPE_CONF_CHECK_I(pch_pfit.size);
10850 }
10851
10852 /* BDW+ don't expose a synchronous way to read the state */
10853 if (IS_HASWELL(dev))
10854 PIPE_CONF_CHECK_I(ips_enabled);
10855
10856 PIPE_CONF_CHECK_I(double_wide);
10857
10858 PIPE_CONF_CHECK_X(ddi_pll_sel);
10859
10860 PIPE_CONF_CHECK_I(shared_dpll);
10861 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10862 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10863 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10864 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10865 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10866 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10867 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10868 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10869
10870 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10871 PIPE_CONF_CHECK_I(pipe_bpp);
10872
10873 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10874 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10875
10876 #undef PIPE_CONF_CHECK_X
10877 #undef PIPE_CONF_CHECK_I
10878 #undef PIPE_CONF_CHECK_I_ALT
10879 #undef PIPE_CONF_CHECK_FLAGS
10880 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10881 #undef PIPE_CONF_QUIRK
10882
10883 return true;
10884 }
10885
10886 static void check_wm_state(struct drm_device *dev)
10887 {
10888 struct drm_i915_private *dev_priv = dev->dev_private;
10889 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10890 struct intel_crtc *intel_crtc;
10891 int plane;
10892
10893 if (INTEL_INFO(dev)->gen < 9)
10894 return;
10895
10896 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10897 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10898
10899 for_each_intel_crtc(dev, intel_crtc) {
10900 struct skl_ddb_entry *hw_entry, *sw_entry;
10901 const enum pipe pipe = intel_crtc->pipe;
10902
10903 if (!intel_crtc->active)
10904 continue;
10905
10906 /* planes */
10907 for_each_plane(dev_priv, pipe, plane) {
10908 hw_entry = &hw_ddb.plane[pipe][plane];
10909 sw_entry = &sw_ddb->plane[pipe][plane];
10910
10911 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10912 continue;
10913
10914 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10915 "(expected (%u,%u), found (%u,%u))\n",
10916 pipe_name(pipe), plane + 1,
10917 sw_entry->start, sw_entry->end,
10918 hw_entry->start, hw_entry->end);
10919 }
10920
10921 /* cursor */
10922 hw_entry = &hw_ddb.cursor[pipe];
10923 sw_entry = &sw_ddb->cursor[pipe];
10924
10925 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10926 continue;
10927
10928 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10929 "(expected (%u,%u), found (%u,%u))\n",
10930 pipe_name(pipe),
10931 sw_entry->start, sw_entry->end,
10932 hw_entry->start, hw_entry->end);
10933 }
10934 }
10935
10936 static void
10937 check_connector_state(struct drm_device *dev)
10938 {
10939 struct intel_connector *connector;
10940
10941 for_each_intel_connector(dev, connector) {
10942 /* This also checks the encoder/connector hw state with the
10943 * ->get_hw_state callbacks. */
10944 intel_connector_check_state(connector);
10945
10946 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10947 "connector's staged encoder doesn't match current encoder\n");
10948 }
10949 }
10950
10951 static void
10952 check_encoder_state(struct drm_device *dev)
10953 {
10954 struct intel_encoder *encoder;
10955 struct intel_connector *connector;
10956
10957 for_each_intel_encoder(dev, encoder) {
10958 bool enabled = false;
10959 bool active = false;
10960 enum pipe pipe, tracked_pipe;
10961
10962 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10963 encoder->base.base.id,
10964 encoder->base.name);
10965
10966 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10967 "encoder's stage crtc doesn't match current crtc\n");
10968 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10969 "encoder's active_connectors set, but no crtc\n");
10970
10971 for_each_intel_connector(dev, connector) {
10972 if (connector->base.encoder != &encoder->base)
10973 continue;
10974 enabled = true;
10975 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10976 active = true;
10977 }
10978 /*
10979 * for MST connectors if we unplug the connector is gone
10980 * away but the encoder is still connected to a crtc
10981 * until a modeset happens in response to the hotplug.
10982 */
10983 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10984 continue;
10985
10986 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10987 "encoder's enabled state mismatch "
10988 "(expected %i, found %i)\n",
10989 !!encoder->base.crtc, enabled);
10990 I915_STATE_WARN(active && !encoder->base.crtc,
10991 "active encoder with no crtc\n");
10992
10993 I915_STATE_WARN(encoder->connectors_active != active,
10994 "encoder's computed active state doesn't match tracked active state "
10995 "(expected %i, found %i)\n", active, encoder->connectors_active);
10996
10997 active = encoder->get_hw_state(encoder, &pipe);
10998 I915_STATE_WARN(active != encoder->connectors_active,
10999 "encoder's hw state doesn't match sw tracking "
11000 "(expected %i, found %i)\n",
11001 encoder->connectors_active, active);
11002
11003 if (!encoder->base.crtc)
11004 continue;
11005
11006 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11007 I915_STATE_WARN(active && pipe != tracked_pipe,
11008 "active encoder's pipe doesn't match"
11009 "(expected %i, found %i)\n",
11010 tracked_pipe, pipe);
11011
11012 }
11013 }
11014
11015 static void
11016 check_crtc_state(struct drm_device *dev)
11017 {
11018 struct drm_i915_private *dev_priv = dev->dev_private;
11019 struct intel_crtc *crtc;
11020 struct intel_encoder *encoder;
11021 struct intel_crtc_state pipe_config;
11022
11023 for_each_intel_crtc(dev, crtc) {
11024 bool enabled = false;
11025 bool active = false;
11026
11027 memset(&pipe_config, 0, sizeof(pipe_config));
11028
11029 DRM_DEBUG_KMS("[CRTC:%d]\n",
11030 crtc->base.base.id);
11031
11032 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11033 "active crtc, but not enabled in sw tracking\n");
11034
11035 for_each_intel_encoder(dev, encoder) {
11036 if (encoder->base.crtc != &crtc->base)
11037 continue;
11038 enabled = true;
11039 if (encoder->connectors_active)
11040 active = true;
11041 }
11042
11043 I915_STATE_WARN(active != crtc->active,
11044 "crtc's computed active state doesn't match tracked active state "
11045 "(expected %i, found %i)\n", active, crtc->active);
11046 I915_STATE_WARN(enabled != crtc->base.state->enable,
11047 "crtc's computed enabled state doesn't match tracked enabled state "
11048 "(expected %i, found %i)\n", enabled,
11049 crtc->base.state->enable);
11050
11051 active = dev_priv->display.get_pipe_config(crtc,
11052 &pipe_config);
11053
11054 /* hw state is inconsistent with the pipe quirk */
11055 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11056 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11057 active = crtc->active;
11058
11059 for_each_intel_encoder(dev, encoder) {
11060 enum pipe pipe;
11061 if (encoder->base.crtc != &crtc->base)
11062 continue;
11063 if (encoder->get_hw_state(encoder, &pipe))
11064 encoder->get_config(encoder, &pipe_config);
11065 }
11066
11067 I915_STATE_WARN(crtc->active != active,
11068 "crtc active state doesn't match with hw state "
11069 "(expected %i, found %i)\n", crtc->active, active);
11070
11071 if (active &&
11072 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11073 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11074 intel_dump_pipe_config(crtc, &pipe_config,
11075 "[hw state]");
11076 intel_dump_pipe_config(crtc, crtc->config,
11077 "[sw state]");
11078 }
11079 }
11080 }
11081
11082 static void
11083 check_shared_dpll_state(struct drm_device *dev)
11084 {
11085 struct drm_i915_private *dev_priv = dev->dev_private;
11086 struct intel_crtc *crtc;
11087 struct intel_dpll_hw_state dpll_hw_state;
11088 int i;
11089
11090 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11091 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11092 int enabled_crtcs = 0, active_crtcs = 0;
11093 bool active;
11094
11095 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11096
11097 DRM_DEBUG_KMS("%s\n", pll->name);
11098
11099 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11100
11101 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11102 "more active pll users than references: %i vs %i\n",
11103 pll->active, hweight32(pll->config.crtc_mask));
11104 I915_STATE_WARN(pll->active && !pll->on,
11105 "pll in active use but not on in sw tracking\n");
11106 I915_STATE_WARN(pll->on && !pll->active,
11107 "pll in on but not on in use in sw tracking\n");
11108 I915_STATE_WARN(pll->on != active,
11109 "pll on state mismatch (expected %i, found %i)\n",
11110 pll->on, active);
11111
11112 for_each_intel_crtc(dev, crtc) {
11113 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11114 enabled_crtcs++;
11115 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11116 active_crtcs++;
11117 }
11118 I915_STATE_WARN(pll->active != active_crtcs,
11119 "pll active crtcs mismatch (expected %i, found %i)\n",
11120 pll->active, active_crtcs);
11121 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11122 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11123 hweight32(pll->config.crtc_mask), enabled_crtcs);
11124
11125 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11126 sizeof(dpll_hw_state)),
11127 "pll hw state mismatch\n");
11128 }
11129 }
11130
11131 void
11132 intel_modeset_check_state(struct drm_device *dev)
11133 {
11134 check_wm_state(dev);
11135 check_connector_state(dev);
11136 check_encoder_state(dev);
11137 check_crtc_state(dev);
11138 check_shared_dpll_state(dev);
11139 }
11140
11141 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11142 int dotclock)
11143 {
11144 /*
11145 * FDI already provided one idea for the dotclock.
11146 * Yell if the encoder disagrees.
11147 */
11148 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11149 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11150 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11151 }
11152
11153 static void update_scanline_offset(struct intel_crtc *crtc)
11154 {
11155 struct drm_device *dev = crtc->base.dev;
11156
11157 /*
11158 * The scanline counter increments at the leading edge of hsync.
11159 *
11160 * On most platforms it starts counting from vtotal-1 on the
11161 * first active line. That means the scanline counter value is
11162 * always one less than what we would expect. Ie. just after
11163 * start of vblank, which also occurs at start of hsync (on the
11164 * last active line), the scanline counter will read vblank_start-1.
11165 *
11166 * On gen2 the scanline counter starts counting from 1 instead
11167 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11168 * to keep the value positive), instead of adding one.
11169 *
11170 * On HSW+ the behaviour of the scanline counter depends on the output
11171 * type. For DP ports it behaves like most other platforms, but on HDMI
11172 * there's an extra 1 line difference. So we need to add two instead of
11173 * one to the value.
11174 */
11175 if (IS_GEN2(dev)) {
11176 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11177 int vtotal;
11178
11179 vtotal = mode->crtc_vtotal;
11180 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11181 vtotal /= 2;
11182
11183 crtc->scanline_offset = vtotal - 1;
11184 } else if (HAS_DDI(dev) &&
11185 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11186 crtc->scanline_offset = 2;
11187 } else
11188 crtc->scanline_offset = 1;
11189 }
11190
11191 static struct intel_crtc_state *
11192 intel_modeset_compute_config(struct drm_crtc *crtc,
11193 struct drm_display_mode *mode,
11194 struct drm_framebuffer *fb,
11195 unsigned *modeset_pipes,
11196 unsigned *prepare_pipes,
11197 unsigned *disable_pipes)
11198 {
11199 struct intel_crtc_state *pipe_config = NULL;
11200
11201 intel_modeset_affected_pipes(crtc, modeset_pipes,
11202 prepare_pipes, disable_pipes);
11203
11204 if ((*modeset_pipes) == 0)
11205 goto out;
11206
11207 /*
11208 * Note this needs changes when we start tracking multiple modes
11209 * and crtcs. At that point we'll need to compute the whole config
11210 * (i.e. one pipe_config for each crtc) rather than just the one
11211 * for this crtc.
11212 */
11213 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11214 if (IS_ERR(pipe_config)) {
11215 goto out;
11216 }
11217 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11218 "[modeset]");
11219
11220 out:
11221 return pipe_config;
11222 }
11223
11224 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11225 unsigned modeset_pipes,
11226 unsigned disable_pipes)
11227 {
11228 struct drm_i915_private *dev_priv = to_i915(dev);
11229 unsigned clear_pipes = modeset_pipes | disable_pipes;
11230 struct intel_crtc *intel_crtc;
11231 int ret = 0;
11232
11233 if (!dev_priv->display.crtc_compute_clock)
11234 return 0;
11235
11236 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11237 if (ret)
11238 goto done;
11239
11240 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11241 struct intel_crtc_state *state = intel_crtc->new_config;
11242 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11243 state);
11244 if (ret) {
11245 intel_shared_dpll_abort_config(dev_priv);
11246 goto done;
11247 }
11248 }
11249
11250 done:
11251 return ret;
11252 }
11253
11254 static int __intel_set_mode(struct drm_crtc *crtc,
11255 struct drm_display_mode *mode,
11256 int x, int y, struct drm_framebuffer *fb,
11257 struct intel_crtc_state *pipe_config,
11258 unsigned modeset_pipes,
11259 unsigned prepare_pipes,
11260 unsigned disable_pipes)
11261 {
11262 struct drm_device *dev = crtc->dev;
11263 struct drm_i915_private *dev_priv = dev->dev_private;
11264 struct drm_display_mode *saved_mode;
11265 struct intel_crtc *intel_crtc;
11266 int ret = 0;
11267
11268 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11269 if (!saved_mode)
11270 return -ENOMEM;
11271
11272 *saved_mode = crtc->mode;
11273
11274 if (modeset_pipes)
11275 to_intel_crtc(crtc)->new_config = pipe_config;
11276
11277 /*
11278 * See if the config requires any additional preparation, e.g.
11279 * to adjust global state with pipes off. We need to do this
11280 * here so we can get the modeset_pipe updated config for the new
11281 * mode set on this crtc. For other crtcs we need to use the
11282 * adjusted_mode bits in the crtc directly.
11283 */
11284 if (IS_VALLEYVIEW(dev)) {
11285 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11286
11287 /* may have added more to prepare_pipes than we should */
11288 prepare_pipes &= ~disable_pipes;
11289 }
11290
11291 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11292 if (ret)
11293 goto done;
11294
11295 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11296 intel_crtc_disable(&intel_crtc->base);
11297
11298 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11299 if (intel_crtc->base.state->enable)
11300 dev_priv->display.crtc_disable(&intel_crtc->base);
11301 }
11302
11303 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11304 * to set it here already despite that we pass it down the callchain.
11305 *
11306 * Note we'll need to fix this up when we start tracking multiple
11307 * pipes; here we assume a single modeset_pipe and only track the
11308 * single crtc and mode.
11309 */
11310 if (modeset_pipes) {
11311 crtc->mode = *mode;
11312 /* mode_set/enable/disable functions rely on a correct pipe
11313 * config. */
11314 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11315
11316 /*
11317 * Calculate and store various constants which
11318 * are later needed by vblank and swap-completion
11319 * timestamping. They are derived from true hwmode.
11320 */
11321 drm_calc_timestamping_constants(crtc,
11322 &pipe_config->base.adjusted_mode);
11323 }
11324
11325 /* Only after disabling all output pipelines that will be changed can we
11326 * update the the output configuration. */
11327 intel_modeset_update_state(dev, prepare_pipes);
11328
11329 modeset_update_crtc_power_domains(dev);
11330
11331 /* Set up the DPLL and any encoders state that needs to adjust or depend
11332 * on the DPLL.
11333 */
11334 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11335 struct drm_plane *primary = intel_crtc->base.primary;
11336 int vdisplay, hdisplay;
11337
11338 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11339 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11340 fb, 0, 0,
11341 hdisplay, vdisplay,
11342 x << 16, y << 16,
11343 hdisplay << 16, vdisplay << 16);
11344 }
11345
11346 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11347 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11348 update_scanline_offset(intel_crtc);
11349
11350 dev_priv->display.crtc_enable(&intel_crtc->base);
11351 }
11352
11353 /* FIXME: add subpixel order */
11354 done:
11355 if (ret && crtc->state->enable)
11356 crtc->mode = *saved_mode;
11357
11358 kfree(saved_mode);
11359 return ret;
11360 }
11361
11362 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11363 struct drm_display_mode *mode,
11364 int x, int y, struct drm_framebuffer *fb,
11365 struct intel_crtc_state *pipe_config,
11366 unsigned modeset_pipes,
11367 unsigned prepare_pipes,
11368 unsigned disable_pipes)
11369 {
11370 int ret;
11371
11372 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11373 prepare_pipes, disable_pipes);
11374
11375 if (ret == 0)
11376 intel_modeset_check_state(crtc->dev);
11377
11378 return ret;
11379 }
11380
11381 static int intel_set_mode(struct drm_crtc *crtc,
11382 struct drm_display_mode *mode,
11383 int x, int y, struct drm_framebuffer *fb)
11384 {
11385 struct intel_crtc_state *pipe_config;
11386 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11387
11388 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11389 &modeset_pipes,
11390 &prepare_pipes,
11391 &disable_pipes);
11392
11393 if (IS_ERR(pipe_config))
11394 return PTR_ERR(pipe_config);
11395
11396 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11397 modeset_pipes, prepare_pipes,
11398 disable_pipes);
11399 }
11400
11401 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11402 {
11403 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11404 }
11405
11406 #undef for_each_intel_crtc_masked
11407
11408 static void intel_set_config_free(struct intel_set_config *config)
11409 {
11410 if (!config)
11411 return;
11412
11413 kfree(config->save_connector_encoders);
11414 kfree(config->save_encoder_crtcs);
11415 kfree(config->save_crtc_enabled);
11416 kfree(config);
11417 }
11418
11419 static int intel_set_config_save_state(struct drm_device *dev,
11420 struct intel_set_config *config)
11421 {
11422 struct drm_crtc *crtc;
11423 struct drm_encoder *encoder;
11424 struct drm_connector *connector;
11425 int count;
11426
11427 config->save_crtc_enabled =
11428 kcalloc(dev->mode_config.num_crtc,
11429 sizeof(bool), GFP_KERNEL);
11430 if (!config->save_crtc_enabled)
11431 return -ENOMEM;
11432
11433 config->save_encoder_crtcs =
11434 kcalloc(dev->mode_config.num_encoder,
11435 sizeof(struct drm_crtc *), GFP_KERNEL);
11436 if (!config->save_encoder_crtcs)
11437 return -ENOMEM;
11438
11439 config->save_connector_encoders =
11440 kcalloc(dev->mode_config.num_connector,
11441 sizeof(struct drm_encoder *), GFP_KERNEL);
11442 if (!config->save_connector_encoders)
11443 return -ENOMEM;
11444
11445 /* Copy data. Note that driver private data is not affected.
11446 * Should anything bad happen only the expected state is
11447 * restored, not the drivers personal bookkeeping.
11448 */
11449 count = 0;
11450 for_each_crtc(dev, crtc) {
11451 config->save_crtc_enabled[count++] = crtc->state->enable;
11452 }
11453
11454 count = 0;
11455 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11456 config->save_encoder_crtcs[count++] = encoder->crtc;
11457 }
11458
11459 count = 0;
11460 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11461 config->save_connector_encoders[count++] = connector->encoder;
11462 }
11463
11464 return 0;
11465 }
11466
11467 static void intel_set_config_restore_state(struct drm_device *dev,
11468 struct intel_set_config *config)
11469 {
11470 struct intel_crtc *crtc;
11471 struct intel_encoder *encoder;
11472 struct intel_connector *connector;
11473 int count;
11474
11475 count = 0;
11476 for_each_intel_crtc(dev, crtc) {
11477 crtc->new_enabled = config->save_crtc_enabled[count++];
11478
11479 if (crtc->new_enabled)
11480 crtc->new_config = crtc->config;
11481 else
11482 crtc->new_config = NULL;
11483 }
11484
11485 count = 0;
11486 for_each_intel_encoder(dev, encoder) {
11487 encoder->new_crtc =
11488 to_intel_crtc(config->save_encoder_crtcs[count++]);
11489 }
11490
11491 count = 0;
11492 for_each_intel_connector(dev, connector) {
11493 connector->new_encoder =
11494 to_intel_encoder(config->save_connector_encoders[count++]);
11495 }
11496 }
11497
11498 static bool
11499 is_crtc_connector_off(struct drm_mode_set *set)
11500 {
11501 int i;
11502
11503 if (set->num_connectors == 0)
11504 return false;
11505
11506 if (WARN_ON(set->connectors == NULL))
11507 return false;
11508
11509 for (i = 0; i < set->num_connectors; i++)
11510 if (set->connectors[i]->encoder &&
11511 set->connectors[i]->encoder->crtc == set->crtc &&
11512 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11513 return true;
11514
11515 return false;
11516 }
11517
11518 static void
11519 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11520 struct intel_set_config *config)
11521 {
11522
11523 /* We should be able to check here if the fb has the same properties
11524 * and then just flip_or_move it */
11525 if (is_crtc_connector_off(set)) {
11526 config->mode_changed = true;
11527 } else if (set->crtc->primary->fb != set->fb) {
11528 /*
11529 * If we have no fb, we can only flip as long as the crtc is
11530 * active, otherwise we need a full mode set. The crtc may
11531 * be active if we've only disabled the primary plane, or
11532 * in fastboot situations.
11533 */
11534 if (set->crtc->primary->fb == NULL) {
11535 struct intel_crtc *intel_crtc =
11536 to_intel_crtc(set->crtc);
11537
11538 if (intel_crtc->active) {
11539 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11540 config->fb_changed = true;
11541 } else {
11542 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11543 config->mode_changed = true;
11544 }
11545 } else if (set->fb == NULL) {
11546 config->mode_changed = true;
11547 } else if (set->fb->pixel_format !=
11548 set->crtc->primary->fb->pixel_format) {
11549 config->mode_changed = true;
11550 } else {
11551 config->fb_changed = true;
11552 }
11553 }
11554
11555 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11556 config->fb_changed = true;
11557
11558 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11559 DRM_DEBUG_KMS("modes are different, full mode set\n");
11560 drm_mode_debug_printmodeline(&set->crtc->mode);
11561 drm_mode_debug_printmodeline(set->mode);
11562 config->mode_changed = true;
11563 }
11564
11565 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11566 set->crtc->base.id, config->mode_changed, config->fb_changed);
11567 }
11568
11569 static int
11570 intel_modeset_stage_output_state(struct drm_device *dev,
11571 struct drm_mode_set *set,
11572 struct intel_set_config *config)
11573 {
11574 struct intel_connector *connector;
11575 struct intel_encoder *encoder;
11576 struct intel_crtc *crtc;
11577 int ro;
11578
11579 /* The upper layers ensure that we either disable a crtc or have a list
11580 * of connectors. For paranoia, double-check this. */
11581 WARN_ON(!set->fb && (set->num_connectors != 0));
11582 WARN_ON(set->fb && (set->num_connectors == 0));
11583
11584 for_each_intel_connector(dev, connector) {
11585 /* Otherwise traverse passed in connector list and get encoders
11586 * for them. */
11587 for (ro = 0; ro < set->num_connectors; ro++) {
11588 if (set->connectors[ro] == &connector->base) {
11589 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11590 break;
11591 }
11592 }
11593
11594 /* If we disable the crtc, disable all its connectors. Also, if
11595 * the connector is on the changing crtc but not on the new
11596 * connector list, disable it. */
11597 if ((!set->fb || ro == set->num_connectors) &&
11598 connector->base.encoder &&
11599 connector->base.encoder->crtc == set->crtc) {
11600 connector->new_encoder = NULL;
11601
11602 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11603 connector->base.base.id,
11604 connector->base.name);
11605 }
11606
11607
11608 if (&connector->new_encoder->base != connector->base.encoder) {
11609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11610 connector->base.base.id,
11611 connector->base.name);
11612 config->mode_changed = true;
11613 }
11614 }
11615 /* connector->new_encoder is now updated for all connectors. */
11616
11617 /* Update crtc of enabled connectors. */
11618 for_each_intel_connector(dev, connector) {
11619 struct drm_crtc *new_crtc;
11620
11621 if (!connector->new_encoder)
11622 continue;
11623
11624 new_crtc = connector->new_encoder->base.crtc;
11625
11626 for (ro = 0; ro < set->num_connectors; ro++) {
11627 if (set->connectors[ro] == &connector->base)
11628 new_crtc = set->crtc;
11629 }
11630
11631 /* Make sure the new CRTC will work with the encoder */
11632 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11633 new_crtc)) {
11634 return -EINVAL;
11635 }
11636 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11637
11638 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11639 connector->base.base.id,
11640 connector->base.name,
11641 new_crtc->base.id);
11642 }
11643
11644 /* Check for any encoders that needs to be disabled. */
11645 for_each_intel_encoder(dev, encoder) {
11646 int num_connectors = 0;
11647 for_each_intel_connector(dev, connector) {
11648 if (connector->new_encoder == encoder) {
11649 WARN_ON(!connector->new_encoder->new_crtc);
11650 num_connectors++;
11651 }
11652 }
11653
11654 if (num_connectors == 0)
11655 encoder->new_crtc = NULL;
11656 else if (num_connectors > 1)
11657 return -EINVAL;
11658
11659 /* Only now check for crtc changes so we don't miss encoders
11660 * that will be disabled. */
11661 if (&encoder->new_crtc->base != encoder->base.crtc) {
11662 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11663 encoder->base.base.id,
11664 encoder->base.name);
11665 config->mode_changed = true;
11666 }
11667 }
11668 /* Now we've also updated encoder->new_crtc for all encoders. */
11669 for_each_intel_connector(dev, connector) {
11670 if (connector->new_encoder)
11671 if (connector->new_encoder != connector->encoder)
11672 connector->encoder = connector->new_encoder;
11673 }
11674 for_each_intel_crtc(dev, crtc) {
11675 crtc->new_enabled = false;
11676
11677 for_each_intel_encoder(dev, encoder) {
11678 if (encoder->new_crtc == crtc) {
11679 crtc->new_enabled = true;
11680 break;
11681 }
11682 }
11683
11684 if (crtc->new_enabled != crtc->base.state->enable) {
11685 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11686 crtc->base.base.id,
11687 crtc->new_enabled ? "en" : "dis");
11688 config->mode_changed = true;
11689 }
11690
11691 if (crtc->new_enabled)
11692 crtc->new_config = crtc->config;
11693 else
11694 crtc->new_config = NULL;
11695 }
11696
11697 return 0;
11698 }
11699
11700 static void disable_crtc_nofb(struct intel_crtc *crtc)
11701 {
11702 struct drm_device *dev = crtc->base.dev;
11703 struct intel_encoder *encoder;
11704 struct intel_connector *connector;
11705
11706 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11707 pipe_name(crtc->pipe));
11708
11709 for_each_intel_connector(dev, connector) {
11710 if (connector->new_encoder &&
11711 connector->new_encoder->new_crtc == crtc)
11712 connector->new_encoder = NULL;
11713 }
11714
11715 for_each_intel_encoder(dev, encoder) {
11716 if (encoder->new_crtc == crtc)
11717 encoder->new_crtc = NULL;
11718 }
11719
11720 crtc->new_enabled = false;
11721 crtc->new_config = NULL;
11722 }
11723
11724 static int intel_crtc_set_config(struct drm_mode_set *set)
11725 {
11726 struct drm_device *dev;
11727 struct drm_mode_set save_set;
11728 struct intel_set_config *config;
11729 struct intel_crtc_state *pipe_config;
11730 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11731 int ret;
11732
11733 BUG_ON(!set);
11734 BUG_ON(!set->crtc);
11735 BUG_ON(!set->crtc->helper_private);
11736
11737 /* Enforce sane interface api - has been abused by the fb helper. */
11738 BUG_ON(!set->mode && set->fb);
11739 BUG_ON(set->fb && set->num_connectors == 0);
11740
11741 if (set->fb) {
11742 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11743 set->crtc->base.id, set->fb->base.id,
11744 (int)set->num_connectors, set->x, set->y);
11745 } else {
11746 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11747 }
11748
11749 dev = set->crtc->dev;
11750
11751 ret = -ENOMEM;
11752 config = kzalloc(sizeof(*config), GFP_KERNEL);
11753 if (!config)
11754 goto out_config;
11755
11756 ret = intel_set_config_save_state(dev, config);
11757 if (ret)
11758 goto out_config;
11759
11760 save_set.crtc = set->crtc;
11761 save_set.mode = &set->crtc->mode;
11762 save_set.x = set->crtc->x;
11763 save_set.y = set->crtc->y;
11764 save_set.fb = set->crtc->primary->fb;
11765
11766 /* Compute whether we need a full modeset, only an fb base update or no
11767 * change at all. In the future we might also check whether only the
11768 * mode changed, e.g. for LVDS where we only change the panel fitter in
11769 * such cases. */
11770 intel_set_config_compute_mode_changes(set, config);
11771
11772 ret = intel_modeset_stage_output_state(dev, set, config);
11773 if (ret)
11774 goto fail;
11775
11776 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11777 set->fb,
11778 &modeset_pipes,
11779 &prepare_pipes,
11780 &disable_pipes);
11781 if (IS_ERR(pipe_config)) {
11782 ret = PTR_ERR(pipe_config);
11783 goto fail;
11784 } else if (pipe_config) {
11785 if (pipe_config->has_audio !=
11786 to_intel_crtc(set->crtc)->config->has_audio)
11787 config->mode_changed = true;
11788
11789 /*
11790 * Note we have an issue here with infoframes: current code
11791 * only updates them on the full mode set path per hw
11792 * requirements. So here we should be checking for any
11793 * required changes and forcing a mode set.
11794 */
11795 }
11796
11797 /* set_mode will free it in the mode_changed case */
11798 if (!config->mode_changed)
11799 kfree(pipe_config);
11800
11801 intel_update_pipe_size(to_intel_crtc(set->crtc));
11802
11803 if (config->mode_changed) {
11804 ret = intel_set_mode_pipes(set->crtc, set->mode,
11805 set->x, set->y, set->fb, pipe_config,
11806 modeset_pipes, prepare_pipes,
11807 disable_pipes);
11808 } else if (config->fb_changed) {
11809 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11810 struct drm_plane *primary = set->crtc->primary;
11811 int vdisplay, hdisplay;
11812
11813 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11814 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11815 0, 0, hdisplay, vdisplay,
11816 set->x << 16, set->y << 16,
11817 hdisplay << 16, vdisplay << 16);
11818
11819 /*
11820 * We need to make sure the primary plane is re-enabled if it
11821 * has previously been turned off.
11822 */
11823 if (!intel_crtc->primary_enabled && ret == 0) {
11824 WARN_ON(!intel_crtc->active);
11825 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11826 }
11827
11828 /*
11829 * In the fastboot case this may be our only check of the
11830 * state after boot. It would be better to only do it on
11831 * the first update, but we don't have a nice way of doing that
11832 * (and really, set_config isn't used much for high freq page
11833 * flipping, so increasing its cost here shouldn't be a big
11834 * deal).
11835 */
11836 if (i915.fastboot && ret == 0)
11837 intel_modeset_check_state(set->crtc->dev);
11838 }
11839
11840 if (ret) {
11841 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11842 set->crtc->base.id, ret);
11843 fail:
11844 intel_set_config_restore_state(dev, config);
11845
11846 /*
11847 * HACK: if the pipe was on, but we didn't have a framebuffer,
11848 * force the pipe off to avoid oopsing in the modeset code
11849 * due to fb==NULL. This should only happen during boot since
11850 * we don't yet reconstruct the FB from the hardware state.
11851 */
11852 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11853 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11854
11855 /* Try to restore the config */
11856 if (config->mode_changed &&
11857 intel_set_mode(save_set.crtc, save_set.mode,
11858 save_set.x, save_set.y, save_set.fb))
11859 DRM_ERROR("failed to restore config after modeset failure\n");
11860 }
11861
11862 out_config:
11863 intel_set_config_free(config);
11864 return ret;
11865 }
11866
11867 static const struct drm_crtc_funcs intel_crtc_funcs = {
11868 .gamma_set = intel_crtc_gamma_set,
11869 .set_config = intel_crtc_set_config,
11870 .destroy = intel_crtc_destroy,
11871 .page_flip = intel_crtc_page_flip,
11872 .atomic_duplicate_state = intel_crtc_duplicate_state,
11873 .atomic_destroy_state = intel_crtc_destroy_state,
11874 };
11875
11876 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11877 struct intel_shared_dpll *pll,
11878 struct intel_dpll_hw_state *hw_state)
11879 {
11880 uint32_t val;
11881
11882 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11883 return false;
11884
11885 val = I915_READ(PCH_DPLL(pll->id));
11886 hw_state->dpll = val;
11887 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11888 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11889
11890 return val & DPLL_VCO_ENABLE;
11891 }
11892
11893 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11894 struct intel_shared_dpll *pll)
11895 {
11896 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11897 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11898 }
11899
11900 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11901 struct intel_shared_dpll *pll)
11902 {
11903 /* PCH refclock must be enabled first */
11904 ibx_assert_pch_refclk_enabled(dev_priv);
11905
11906 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11907
11908 /* Wait for the clocks to stabilize. */
11909 POSTING_READ(PCH_DPLL(pll->id));
11910 udelay(150);
11911
11912 /* The pixel multiplier can only be updated once the
11913 * DPLL is enabled and the clocks are stable.
11914 *
11915 * So write it again.
11916 */
11917 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11918 POSTING_READ(PCH_DPLL(pll->id));
11919 udelay(200);
11920 }
11921
11922 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11923 struct intel_shared_dpll *pll)
11924 {
11925 struct drm_device *dev = dev_priv->dev;
11926 struct intel_crtc *crtc;
11927
11928 /* Make sure no transcoder isn't still depending on us. */
11929 for_each_intel_crtc(dev, crtc) {
11930 if (intel_crtc_to_shared_dpll(crtc) == pll)
11931 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11932 }
11933
11934 I915_WRITE(PCH_DPLL(pll->id), 0);
11935 POSTING_READ(PCH_DPLL(pll->id));
11936 udelay(200);
11937 }
11938
11939 static char *ibx_pch_dpll_names[] = {
11940 "PCH DPLL A",
11941 "PCH DPLL B",
11942 };
11943
11944 static void ibx_pch_dpll_init(struct drm_device *dev)
11945 {
11946 struct drm_i915_private *dev_priv = dev->dev_private;
11947 int i;
11948
11949 dev_priv->num_shared_dpll = 2;
11950
11951 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11952 dev_priv->shared_dplls[i].id = i;
11953 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11954 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11955 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11956 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11957 dev_priv->shared_dplls[i].get_hw_state =
11958 ibx_pch_dpll_get_hw_state;
11959 }
11960 }
11961
11962 static void intel_shared_dpll_init(struct drm_device *dev)
11963 {
11964 struct drm_i915_private *dev_priv = dev->dev_private;
11965
11966 if (HAS_DDI(dev))
11967 intel_ddi_pll_init(dev);
11968 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11969 ibx_pch_dpll_init(dev);
11970 else
11971 dev_priv->num_shared_dpll = 0;
11972
11973 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11974 }
11975
11976 /**
11977 * intel_prepare_plane_fb - Prepare fb for usage on plane
11978 * @plane: drm plane to prepare for
11979 * @fb: framebuffer to prepare for presentation
11980 *
11981 * Prepares a framebuffer for usage on a display plane. Generally this
11982 * involves pinning the underlying object and updating the frontbuffer tracking
11983 * bits. Some older platforms need special physical address handling for
11984 * cursor planes.
11985 *
11986 * Returns 0 on success, negative error code on failure.
11987 */
11988 int
11989 intel_prepare_plane_fb(struct drm_plane *plane,
11990 struct drm_framebuffer *fb,
11991 const struct drm_plane_state *new_state)
11992 {
11993 struct drm_device *dev = plane->dev;
11994 struct intel_plane *intel_plane = to_intel_plane(plane);
11995 enum pipe pipe = intel_plane->pipe;
11996 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11997 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11998 unsigned frontbuffer_bits = 0;
11999 int ret = 0;
12000
12001 if (!obj)
12002 return 0;
12003
12004 switch (plane->type) {
12005 case DRM_PLANE_TYPE_PRIMARY:
12006 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12007 break;
12008 case DRM_PLANE_TYPE_CURSOR:
12009 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12010 break;
12011 case DRM_PLANE_TYPE_OVERLAY:
12012 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12013 break;
12014 }
12015
12016 mutex_lock(&dev->struct_mutex);
12017
12018 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12019 INTEL_INFO(dev)->cursor_needs_physical) {
12020 int align = IS_I830(dev) ? 16 * 1024 : 256;
12021 ret = i915_gem_object_attach_phys(obj, align);
12022 if (ret)
12023 DRM_DEBUG_KMS("failed to attach phys object\n");
12024 } else {
12025 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
12026 }
12027
12028 if (ret == 0)
12029 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12030
12031 mutex_unlock(&dev->struct_mutex);
12032
12033 return ret;
12034 }
12035
12036 /**
12037 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12038 * @plane: drm plane to clean up for
12039 * @fb: old framebuffer that was on plane
12040 *
12041 * Cleans up a framebuffer that has just been removed from a plane.
12042 */
12043 void
12044 intel_cleanup_plane_fb(struct drm_plane *plane,
12045 struct drm_framebuffer *fb,
12046 const struct drm_plane_state *old_state)
12047 {
12048 struct drm_device *dev = plane->dev;
12049 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12050
12051 if (WARN_ON(!obj))
12052 return;
12053
12054 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12055 !INTEL_INFO(dev)->cursor_needs_physical) {
12056 mutex_lock(&dev->struct_mutex);
12057 intel_unpin_fb_obj(obj);
12058 mutex_unlock(&dev->struct_mutex);
12059 }
12060 }
12061
12062 static int
12063 intel_check_primary_plane(struct drm_plane *plane,
12064 struct intel_plane_state *state)
12065 {
12066 struct drm_device *dev = plane->dev;
12067 struct drm_i915_private *dev_priv = dev->dev_private;
12068 struct drm_crtc *crtc = state->base.crtc;
12069 struct intel_crtc *intel_crtc;
12070 struct drm_framebuffer *fb = state->base.fb;
12071 struct drm_rect *dest = &state->dst;
12072 struct drm_rect *src = &state->src;
12073 const struct drm_rect *clip = &state->clip;
12074 int ret;
12075
12076 crtc = crtc ? crtc : plane->crtc;
12077 intel_crtc = to_intel_crtc(crtc);
12078
12079 ret = drm_plane_helper_check_update(plane, crtc, fb,
12080 src, dest, clip,
12081 DRM_PLANE_HELPER_NO_SCALING,
12082 DRM_PLANE_HELPER_NO_SCALING,
12083 false, true, &state->visible);
12084 if (ret)
12085 return ret;
12086
12087 if (intel_crtc->active) {
12088 intel_crtc->atomic.wait_for_flips = true;
12089
12090 /*
12091 * FBC does not work on some platforms for rotated
12092 * planes, so disable it when rotation is not 0 and
12093 * update it when rotation is set back to 0.
12094 *
12095 * FIXME: This is redundant with the fbc update done in
12096 * the primary plane enable function except that that
12097 * one is done too late. We eventually need to unify
12098 * this.
12099 */
12100 if (intel_crtc->primary_enabled &&
12101 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12102 dev_priv->fbc.crtc == intel_crtc &&
12103 state->base.rotation != BIT(DRM_ROTATE_0)) {
12104 intel_crtc->atomic.disable_fbc = true;
12105 }
12106
12107 if (state->visible) {
12108 /*
12109 * BDW signals flip done immediately if the plane
12110 * is disabled, even if the plane enable is already
12111 * armed to occur at the next vblank :(
12112 */
12113 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12114 intel_crtc->atomic.wait_vblank = true;
12115 }
12116
12117 intel_crtc->atomic.fb_bits |=
12118 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12119
12120 intel_crtc->atomic.update_fbc = true;
12121
12122 /* Update watermarks on tiling changes. */
12123 if (!plane->state->fb || !state->base.fb ||
12124 plane->state->fb->modifier[0] !=
12125 state->base.fb->modifier[0])
12126 intel_crtc->atomic.update_wm = true;
12127 }
12128
12129 return 0;
12130 }
12131
12132 static void
12133 intel_commit_primary_plane(struct drm_plane *plane,
12134 struct intel_plane_state *state)
12135 {
12136 struct drm_crtc *crtc = state->base.crtc;
12137 struct drm_framebuffer *fb = state->base.fb;
12138 struct drm_device *dev = plane->dev;
12139 struct drm_i915_private *dev_priv = dev->dev_private;
12140 struct intel_crtc *intel_crtc;
12141 struct drm_rect *src = &state->src;
12142
12143 crtc = crtc ? crtc : plane->crtc;
12144 intel_crtc = to_intel_crtc(crtc);
12145
12146 plane->fb = fb;
12147 crtc->x = src->x1 >> 16;
12148 crtc->y = src->y1 >> 16;
12149
12150 if (intel_crtc->active) {
12151 if (state->visible) {
12152 /* FIXME: kill this fastboot hack */
12153 intel_update_pipe_size(intel_crtc);
12154
12155 intel_crtc->primary_enabled = true;
12156
12157 dev_priv->display.update_primary_plane(crtc, plane->fb,
12158 crtc->x, crtc->y);
12159 } else {
12160 /*
12161 * If clipping results in a non-visible primary plane,
12162 * we'll disable the primary plane. Note that this is
12163 * a bit different than what happens if userspace
12164 * explicitly disables the plane by passing fb=0
12165 * because plane->fb still gets set and pinned.
12166 */
12167 intel_disable_primary_hw_plane(plane, crtc);
12168 }
12169 }
12170 }
12171
12172 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12173 {
12174 struct drm_device *dev = crtc->dev;
12175 struct drm_i915_private *dev_priv = dev->dev_private;
12176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12177 struct intel_plane *intel_plane;
12178 struct drm_plane *p;
12179 unsigned fb_bits = 0;
12180
12181 /* Track fb's for any planes being disabled */
12182 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12183 intel_plane = to_intel_plane(p);
12184
12185 if (intel_crtc->atomic.disabled_planes &
12186 (1 << drm_plane_index(p))) {
12187 switch (p->type) {
12188 case DRM_PLANE_TYPE_PRIMARY:
12189 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12190 break;
12191 case DRM_PLANE_TYPE_CURSOR:
12192 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12193 break;
12194 case DRM_PLANE_TYPE_OVERLAY:
12195 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12196 break;
12197 }
12198
12199 mutex_lock(&dev->struct_mutex);
12200 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12201 mutex_unlock(&dev->struct_mutex);
12202 }
12203 }
12204
12205 if (intel_crtc->atomic.wait_for_flips)
12206 intel_crtc_wait_for_pending_flips(crtc);
12207
12208 if (intel_crtc->atomic.disable_fbc)
12209 intel_fbc_disable(dev);
12210
12211 if (intel_crtc->atomic.pre_disable_primary)
12212 intel_pre_disable_primary(crtc);
12213
12214 if (intel_crtc->atomic.update_wm)
12215 intel_update_watermarks(crtc);
12216
12217 intel_runtime_pm_get(dev_priv);
12218
12219 /* Perform vblank evasion around commit operation */
12220 if (intel_crtc->active)
12221 intel_crtc->atomic.evade =
12222 intel_pipe_update_start(intel_crtc,
12223 &intel_crtc->atomic.start_vbl_count);
12224 }
12225
12226 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12227 {
12228 struct drm_device *dev = crtc->dev;
12229 struct drm_i915_private *dev_priv = dev->dev_private;
12230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12231 struct drm_plane *p;
12232
12233 if (intel_crtc->atomic.evade)
12234 intel_pipe_update_end(intel_crtc,
12235 intel_crtc->atomic.start_vbl_count);
12236
12237 intel_runtime_pm_put(dev_priv);
12238
12239 if (intel_crtc->atomic.wait_vblank)
12240 intel_wait_for_vblank(dev, intel_crtc->pipe);
12241
12242 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12243
12244 if (intel_crtc->atomic.update_fbc) {
12245 mutex_lock(&dev->struct_mutex);
12246 intel_fbc_update(dev);
12247 mutex_unlock(&dev->struct_mutex);
12248 }
12249
12250 if (intel_crtc->atomic.post_enable_primary)
12251 intel_post_enable_primary(crtc);
12252
12253 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12254 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12255 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12256 false, false);
12257
12258 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12259 }
12260
12261 /**
12262 * intel_plane_destroy - destroy a plane
12263 * @plane: plane to destroy
12264 *
12265 * Common destruction function for all types of planes (primary, cursor,
12266 * sprite).
12267 */
12268 void intel_plane_destroy(struct drm_plane *plane)
12269 {
12270 struct intel_plane *intel_plane = to_intel_plane(plane);
12271 drm_plane_cleanup(plane);
12272 kfree(intel_plane);
12273 }
12274
12275 const struct drm_plane_funcs intel_plane_funcs = {
12276 .update_plane = drm_plane_helper_update,
12277 .disable_plane = drm_plane_helper_disable,
12278 .destroy = intel_plane_destroy,
12279 .set_property = drm_atomic_helper_plane_set_property,
12280 .atomic_get_property = intel_plane_atomic_get_property,
12281 .atomic_set_property = intel_plane_atomic_set_property,
12282 .atomic_duplicate_state = intel_plane_duplicate_state,
12283 .atomic_destroy_state = intel_plane_destroy_state,
12284
12285 };
12286
12287 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12288 int pipe)
12289 {
12290 struct intel_plane *primary;
12291 struct intel_plane_state *state;
12292 const uint32_t *intel_primary_formats;
12293 int num_formats;
12294
12295 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12296 if (primary == NULL)
12297 return NULL;
12298
12299 state = intel_create_plane_state(&primary->base);
12300 if (!state) {
12301 kfree(primary);
12302 return NULL;
12303 }
12304 primary->base.state = &state->base;
12305
12306 primary->can_scale = false;
12307 primary->max_downscale = 1;
12308 primary->pipe = pipe;
12309 primary->plane = pipe;
12310 primary->check_plane = intel_check_primary_plane;
12311 primary->commit_plane = intel_commit_primary_plane;
12312 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12313 primary->plane = !pipe;
12314
12315 if (INTEL_INFO(dev)->gen <= 3) {
12316 intel_primary_formats = intel_primary_formats_gen2;
12317 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12318 } else {
12319 intel_primary_formats = intel_primary_formats_gen4;
12320 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12321 }
12322
12323 drm_universal_plane_init(dev, &primary->base, 0,
12324 &intel_plane_funcs,
12325 intel_primary_formats, num_formats,
12326 DRM_PLANE_TYPE_PRIMARY);
12327
12328 if (INTEL_INFO(dev)->gen >= 4) {
12329 if (!dev->mode_config.rotation_property)
12330 dev->mode_config.rotation_property =
12331 drm_mode_create_rotation_property(dev,
12332 BIT(DRM_ROTATE_0) |
12333 BIT(DRM_ROTATE_180));
12334 if (dev->mode_config.rotation_property)
12335 drm_object_attach_property(&primary->base.base,
12336 dev->mode_config.rotation_property,
12337 state->base.rotation);
12338 }
12339
12340 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12341
12342 return &primary->base;
12343 }
12344
12345 static int
12346 intel_check_cursor_plane(struct drm_plane *plane,
12347 struct intel_plane_state *state)
12348 {
12349 struct drm_crtc *crtc = state->base.crtc;
12350 struct drm_device *dev = plane->dev;
12351 struct drm_framebuffer *fb = state->base.fb;
12352 struct drm_rect *dest = &state->dst;
12353 struct drm_rect *src = &state->src;
12354 const struct drm_rect *clip = &state->clip;
12355 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12356 struct intel_crtc *intel_crtc;
12357 unsigned stride;
12358 int ret;
12359
12360 crtc = crtc ? crtc : plane->crtc;
12361 intel_crtc = to_intel_crtc(crtc);
12362
12363 ret = drm_plane_helper_check_update(plane, crtc, fb,
12364 src, dest, clip,
12365 DRM_PLANE_HELPER_NO_SCALING,
12366 DRM_PLANE_HELPER_NO_SCALING,
12367 true, true, &state->visible);
12368 if (ret)
12369 return ret;
12370
12371
12372 /* if we want to turn off the cursor ignore width and height */
12373 if (!obj)
12374 goto finish;
12375
12376 /* Check for which cursor types we support */
12377 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12378 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12379 state->base.crtc_w, state->base.crtc_h);
12380 return -EINVAL;
12381 }
12382
12383 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12384 if (obj->base.size < stride * state->base.crtc_h) {
12385 DRM_DEBUG_KMS("buffer is too small\n");
12386 return -ENOMEM;
12387 }
12388
12389 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12390 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12391 ret = -EINVAL;
12392 }
12393
12394 finish:
12395 if (intel_crtc->active) {
12396 if (plane->state->crtc_w != state->base.crtc_w)
12397 intel_crtc->atomic.update_wm = true;
12398
12399 intel_crtc->atomic.fb_bits |=
12400 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12401 }
12402
12403 return ret;
12404 }
12405
12406 static void
12407 intel_commit_cursor_plane(struct drm_plane *plane,
12408 struct intel_plane_state *state)
12409 {
12410 struct drm_crtc *crtc = state->base.crtc;
12411 struct drm_device *dev = plane->dev;
12412 struct intel_crtc *intel_crtc;
12413 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12414 uint32_t addr;
12415
12416 crtc = crtc ? crtc : plane->crtc;
12417 intel_crtc = to_intel_crtc(crtc);
12418
12419 plane->fb = state->base.fb;
12420 crtc->cursor_x = state->base.crtc_x;
12421 crtc->cursor_y = state->base.crtc_y;
12422
12423 if (intel_crtc->cursor_bo == obj)
12424 goto update;
12425
12426 if (!obj)
12427 addr = 0;
12428 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12429 addr = i915_gem_obj_ggtt_offset(obj);
12430 else
12431 addr = obj->phys_handle->busaddr;
12432
12433 intel_crtc->cursor_addr = addr;
12434 intel_crtc->cursor_bo = obj;
12435 update:
12436
12437 if (intel_crtc->active)
12438 intel_crtc_update_cursor(crtc, state->visible);
12439 }
12440
12441 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12442 int pipe)
12443 {
12444 struct intel_plane *cursor;
12445 struct intel_plane_state *state;
12446
12447 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12448 if (cursor == NULL)
12449 return NULL;
12450
12451 state = intel_create_plane_state(&cursor->base);
12452 if (!state) {
12453 kfree(cursor);
12454 return NULL;
12455 }
12456 cursor->base.state = &state->base;
12457
12458 cursor->can_scale = false;
12459 cursor->max_downscale = 1;
12460 cursor->pipe = pipe;
12461 cursor->plane = pipe;
12462 cursor->check_plane = intel_check_cursor_plane;
12463 cursor->commit_plane = intel_commit_cursor_plane;
12464
12465 drm_universal_plane_init(dev, &cursor->base, 0,
12466 &intel_plane_funcs,
12467 intel_cursor_formats,
12468 ARRAY_SIZE(intel_cursor_formats),
12469 DRM_PLANE_TYPE_CURSOR);
12470
12471 if (INTEL_INFO(dev)->gen >= 4) {
12472 if (!dev->mode_config.rotation_property)
12473 dev->mode_config.rotation_property =
12474 drm_mode_create_rotation_property(dev,
12475 BIT(DRM_ROTATE_0) |
12476 BIT(DRM_ROTATE_180));
12477 if (dev->mode_config.rotation_property)
12478 drm_object_attach_property(&cursor->base.base,
12479 dev->mode_config.rotation_property,
12480 state->base.rotation);
12481 }
12482
12483 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12484
12485 return &cursor->base;
12486 }
12487
12488 static void intel_crtc_init(struct drm_device *dev, int pipe)
12489 {
12490 struct drm_i915_private *dev_priv = dev->dev_private;
12491 struct intel_crtc *intel_crtc;
12492 struct intel_crtc_state *crtc_state = NULL;
12493 struct drm_plane *primary = NULL;
12494 struct drm_plane *cursor = NULL;
12495 int i, ret;
12496
12497 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12498 if (intel_crtc == NULL)
12499 return;
12500
12501 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12502 if (!crtc_state)
12503 goto fail;
12504 intel_crtc_set_state(intel_crtc, crtc_state);
12505 crtc_state->base.crtc = &intel_crtc->base;
12506
12507 primary = intel_primary_plane_create(dev, pipe);
12508 if (!primary)
12509 goto fail;
12510
12511 cursor = intel_cursor_plane_create(dev, pipe);
12512 if (!cursor)
12513 goto fail;
12514
12515 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12516 cursor, &intel_crtc_funcs);
12517 if (ret)
12518 goto fail;
12519
12520 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12521 for (i = 0; i < 256; i++) {
12522 intel_crtc->lut_r[i] = i;
12523 intel_crtc->lut_g[i] = i;
12524 intel_crtc->lut_b[i] = i;
12525 }
12526
12527 /*
12528 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12529 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12530 */
12531 intel_crtc->pipe = pipe;
12532 intel_crtc->plane = pipe;
12533 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12534 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12535 intel_crtc->plane = !pipe;
12536 }
12537
12538 intel_crtc->cursor_base = ~0;
12539 intel_crtc->cursor_cntl = ~0;
12540 intel_crtc->cursor_size = ~0;
12541
12542 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12543 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12544 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12545 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12546
12547 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12548
12549 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12550
12551 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12552 return;
12553
12554 fail:
12555 if (primary)
12556 drm_plane_cleanup(primary);
12557 if (cursor)
12558 drm_plane_cleanup(cursor);
12559 kfree(crtc_state);
12560 kfree(intel_crtc);
12561 }
12562
12563 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12564 {
12565 struct drm_encoder *encoder = connector->base.encoder;
12566 struct drm_device *dev = connector->base.dev;
12567
12568 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12569
12570 if (!encoder || WARN_ON(!encoder->crtc))
12571 return INVALID_PIPE;
12572
12573 return to_intel_crtc(encoder->crtc)->pipe;
12574 }
12575
12576 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12577 struct drm_file *file)
12578 {
12579 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12580 struct drm_crtc *drmmode_crtc;
12581 struct intel_crtc *crtc;
12582
12583 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12584
12585 if (!drmmode_crtc) {
12586 DRM_ERROR("no such CRTC id\n");
12587 return -ENOENT;
12588 }
12589
12590 crtc = to_intel_crtc(drmmode_crtc);
12591 pipe_from_crtc_id->pipe = crtc->pipe;
12592
12593 return 0;
12594 }
12595
12596 static int intel_encoder_clones(struct intel_encoder *encoder)
12597 {
12598 struct drm_device *dev = encoder->base.dev;
12599 struct intel_encoder *source_encoder;
12600 int index_mask = 0;
12601 int entry = 0;
12602
12603 for_each_intel_encoder(dev, source_encoder) {
12604 if (encoders_cloneable(encoder, source_encoder))
12605 index_mask |= (1 << entry);
12606
12607 entry++;
12608 }
12609
12610 return index_mask;
12611 }
12612
12613 static bool has_edp_a(struct drm_device *dev)
12614 {
12615 struct drm_i915_private *dev_priv = dev->dev_private;
12616
12617 if (!IS_MOBILE(dev))
12618 return false;
12619
12620 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12621 return false;
12622
12623 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12624 return false;
12625
12626 return true;
12627 }
12628
12629 static bool intel_crt_present(struct drm_device *dev)
12630 {
12631 struct drm_i915_private *dev_priv = dev->dev_private;
12632
12633 if (INTEL_INFO(dev)->gen >= 9)
12634 return false;
12635
12636 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12637 return false;
12638
12639 if (IS_CHERRYVIEW(dev))
12640 return false;
12641
12642 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12643 return false;
12644
12645 return true;
12646 }
12647
12648 static void intel_setup_outputs(struct drm_device *dev)
12649 {
12650 struct drm_i915_private *dev_priv = dev->dev_private;
12651 struct intel_encoder *encoder;
12652 struct drm_connector *connector;
12653 bool dpd_is_edp = false;
12654
12655 intel_lvds_init(dev);
12656
12657 if (intel_crt_present(dev))
12658 intel_crt_init(dev);
12659
12660 if (HAS_DDI(dev)) {
12661 int found;
12662
12663 /*
12664 * Haswell uses DDI functions to detect digital outputs.
12665 * On SKL pre-D0 the strap isn't connected, so we assume
12666 * it's there.
12667 */
12668 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12669 /* WaIgnoreDDIAStrap: skl */
12670 if (found ||
12671 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12672 intel_ddi_init(dev, PORT_A);
12673
12674 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12675 * register */
12676 found = I915_READ(SFUSE_STRAP);
12677
12678 if (found & SFUSE_STRAP_DDIB_DETECTED)
12679 intel_ddi_init(dev, PORT_B);
12680 if (found & SFUSE_STRAP_DDIC_DETECTED)
12681 intel_ddi_init(dev, PORT_C);
12682 if (found & SFUSE_STRAP_DDID_DETECTED)
12683 intel_ddi_init(dev, PORT_D);
12684 } else if (HAS_PCH_SPLIT(dev)) {
12685 int found;
12686 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12687
12688 if (has_edp_a(dev))
12689 intel_dp_init(dev, DP_A, PORT_A);
12690
12691 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12692 /* PCH SDVOB multiplex with HDMIB */
12693 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12694 if (!found)
12695 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12696 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12697 intel_dp_init(dev, PCH_DP_B, PORT_B);
12698 }
12699
12700 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12701 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12702
12703 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12704 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12705
12706 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12707 intel_dp_init(dev, PCH_DP_C, PORT_C);
12708
12709 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12710 intel_dp_init(dev, PCH_DP_D, PORT_D);
12711 } else if (IS_VALLEYVIEW(dev)) {
12712 /*
12713 * The DP_DETECTED bit is the latched state of the DDC
12714 * SDA pin at boot. However since eDP doesn't require DDC
12715 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12716 * eDP ports may have been muxed to an alternate function.
12717 * Thus we can't rely on the DP_DETECTED bit alone to detect
12718 * eDP ports. Consult the VBT as well as DP_DETECTED to
12719 * detect eDP ports.
12720 */
12721 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12722 !intel_dp_is_edp(dev, PORT_B))
12723 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12724 PORT_B);
12725 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12726 intel_dp_is_edp(dev, PORT_B))
12727 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12728
12729 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12730 !intel_dp_is_edp(dev, PORT_C))
12731 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12732 PORT_C);
12733 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12734 intel_dp_is_edp(dev, PORT_C))
12735 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12736
12737 if (IS_CHERRYVIEW(dev)) {
12738 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12739 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12740 PORT_D);
12741 /* eDP not supported on port D, so don't check VBT */
12742 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12743 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12744 }
12745
12746 intel_dsi_init(dev);
12747 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12748 bool found = false;
12749
12750 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12751 DRM_DEBUG_KMS("probing SDVOB\n");
12752 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12753 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12754 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12755 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12756 }
12757
12758 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12759 intel_dp_init(dev, DP_B, PORT_B);
12760 }
12761
12762 /* Before G4X SDVOC doesn't have its own detect register */
12763
12764 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12765 DRM_DEBUG_KMS("probing SDVOC\n");
12766 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12767 }
12768
12769 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12770
12771 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12772 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12773 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12774 }
12775 if (SUPPORTS_INTEGRATED_DP(dev))
12776 intel_dp_init(dev, DP_C, PORT_C);
12777 }
12778
12779 if (SUPPORTS_INTEGRATED_DP(dev) &&
12780 (I915_READ(DP_D) & DP_DETECTED))
12781 intel_dp_init(dev, DP_D, PORT_D);
12782 } else if (IS_GEN2(dev))
12783 intel_dvo_init(dev);
12784
12785 if (SUPPORTS_TV(dev))
12786 intel_tv_init(dev);
12787
12788 /*
12789 * FIXME: We don't have full atomic support yet, but we want to be
12790 * able to enable/test plane updates via the atomic interface in the
12791 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12792 * will take some atomic codepaths to lookup properties during
12793 * drmModeGetConnector() that unconditionally dereference
12794 * connector->state.
12795 *
12796 * We create a dummy connector state here for each connector to ensure
12797 * the DRM core doesn't try to dereference a NULL connector->state.
12798 * The actual connector properties will never be updated or contain
12799 * useful information, but since we're doing this specifically for
12800 * testing/debug of the plane operations (and only when a specific
12801 * kernel module option is given), that shouldn't really matter.
12802 *
12803 * Once atomic support for crtc's + connectors lands, this loop should
12804 * be removed since we'll be setting up real connector state, which
12805 * will contain Intel-specific properties.
12806 */
12807 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12808 list_for_each_entry(connector,
12809 &dev->mode_config.connector_list,
12810 head) {
12811 if (!WARN_ON(connector->state)) {
12812 connector->state =
12813 kzalloc(sizeof(*connector->state),
12814 GFP_KERNEL);
12815 }
12816 }
12817 }
12818
12819 intel_psr_init(dev);
12820
12821 for_each_intel_encoder(dev, encoder) {
12822 encoder->base.possible_crtcs = encoder->crtc_mask;
12823 encoder->base.possible_clones =
12824 intel_encoder_clones(encoder);
12825 }
12826
12827 intel_init_pch_refclk(dev);
12828
12829 drm_helper_move_panel_connectors_to_head(dev);
12830 }
12831
12832 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12833 {
12834 struct drm_device *dev = fb->dev;
12835 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12836
12837 drm_framebuffer_cleanup(fb);
12838 mutex_lock(&dev->struct_mutex);
12839 WARN_ON(!intel_fb->obj->framebuffer_references--);
12840 drm_gem_object_unreference(&intel_fb->obj->base);
12841 mutex_unlock(&dev->struct_mutex);
12842 kfree(intel_fb);
12843 }
12844
12845 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12846 struct drm_file *file,
12847 unsigned int *handle)
12848 {
12849 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12850 struct drm_i915_gem_object *obj = intel_fb->obj;
12851
12852 return drm_gem_handle_create(file, &obj->base, handle);
12853 }
12854
12855 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12856 .destroy = intel_user_framebuffer_destroy,
12857 .create_handle = intel_user_framebuffer_create_handle,
12858 };
12859
12860 static
12861 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12862 uint32_t pixel_format)
12863 {
12864 u32 gen = INTEL_INFO(dev)->gen;
12865
12866 if (gen >= 9) {
12867 /* "The stride in bytes must not exceed the of the size of 8K
12868 * pixels and 32K bytes."
12869 */
12870 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12871 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12872 return 32*1024;
12873 } else if (gen >= 4) {
12874 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12875 return 16*1024;
12876 else
12877 return 32*1024;
12878 } else if (gen >= 3) {
12879 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12880 return 8*1024;
12881 else
12882 return 16*1024;
12883 } else {
12884 /* XXX DSPC is limited to 4k tiled */
12885 return 8*1024;
12886 }
12887 }
12888
12889 static int intel_framebuffer_init(struct drm_device *dev,
12890 struct intel_framebuffer *intel_fb,
12891 struct drm_mode_fb_cmd2 *mode_cmd,
12892 struct drm_i915_gem_object *obj)
12893 {
12894 unsigned int aligned_height;
12895 int ret;
12896 u32 pitch_limit, stride_alignment;
12897
12898 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12899
12900 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12901 /* Enforce that fb modifier and tiling mode match, but only for
12902 * X-tiled. This is needed for FBC. */
12903 if (!!(obj->tiling_mode == I915_TILING_X) !=
12904 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12905 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12906 return -EINVAL;
12907 }
12908 } else {
12909 if (obj->tiling_mode == I915_TILING_X)
12910 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12911 else if (obj->tiling_mode == I915_TILING_Y) {
12912 DRM_DEBUG("No Y tiling for legacy addfb\n");
12913 return -EINVAL;
12914 }
12915 }
12916
12917 /* Passed in modifier sanity checking. */
12918 switch (mode_cmd->modifier[0]) {
12919 case I915_FORMAT_MOD_Y_TILED:
12920 case I915_FORMAT_MOD_Yf_TILED:
12921 if (INTEL_INFO(dev)->gen < 9) {
12922 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12923 mode_cmd->modifier[0]);
12924 return -EINVAL;
12925 }
12926 case DRM_FORMAT_MOD_NONE:
12927 case I915_FORMAT_MOD_X_TILED:
12928 break;
12929 default:
12930 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12931 mode_cmd->modifier[0]);
12932 return -EINVAL;
12933 }
12934
12935 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12936 mode_cmd->pixel_format);
12937 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12938 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12939 mode_cmd->pitches[0], stride_alignment);
12940 return -EINVAL;
12941 }
12942
12943 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12944 mode_cmd->pixel_format);
12945 if (mode_cmd->pitches[0] > pitch_limit) {
12946 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12947 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12948 "tiled" : "linear",
12949 mode_cmd->pitches[0], pitch_limit);
12950 return -EINVAL;
12951 }
12952
12953 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12954 mode_cmd->pitches[0] != obj->stride) {
12955 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12956 mode_cmd->pitches[0], obj->stride);
12957 return -EINVAL;
12958 }
12959
12960 /* Reject formats not supported by any plane early. */
12961 switch (mode_cmd->pixel_format) {
12962 case DRM_FORMAT_C8:
12963 case DRM_FORMAT_RGB565:
12964 case DRM_FORMAT_XRGB8888:
12965 case DRM_FORMAT_ARGB8888:
12966 break;
12967 case DRM_FORMAT_XRGB1555:
12968 case DRM_FORMAT_ARGB1555:
12969 if (INTEL_INFO(dev)->gen > 3) {
12970 DRM_DEBUG("unsupported pixel format: %s\n",
12971 drm_get_format_name(mode_cmd->pixel_format));
12972 return -EINVAL;
12973 }
12974 break;
12975 case DRM_FORMAT_XBGR8888:
12976 case DRM_FORMAT_ABGR8888:
12977 case DRM_FORMAT_XRGB2101010:
12978 case DRM_FORMAT_ARGB2101010:
12979 case DRM_FORMAT_XBGR2101010:
12980 case DRM_FORMAT_ABGR2101010:
12981 if (INTEL_INFO(dev)->gen < 4) {
12982 DRM_DEBUG("unsupported pixel format: %s\n",
12983 drm_get_format_name(mode_cmd->pixel_format));
12984 return -EINVAL;
12985 }
12986 break;
12987 case DRM_FORMAT_YUYV:
12988 case DRM_FORMAT_UYVY:
12989 case DRM_FORMAT_YVYU:
12990 case DRM_FORMAT_VYUY:
12991 if (INTEL_INFO(dev)->gen < 5) {
12992 DRM_DEBUG("unsupported pixel format: %s\n",
12993 drm_get_format_name(mode_cmd->pixel_format));
12994 return -EINVAL;
12995 }
12996 break;
12997 default:
12998 DRM_DEBUG("unsupported pixel format: %s\n",
12999 drm_get_format_name(mode_cmd->pixel_format));
13000 return -EINVAL;
13001 }
13002
13003 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13004 if (mode_cmd->offsets[0] != 0)
13005 return -EINVAL;
13006
13007 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13008 mode_cmd->pixel_format,
13009 mode_cmd->modifier[0]);
13010 /* FIXME drm helper for size checks (especially planar formats)? */
13011 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13012 return -EINVAL;
13013
13014 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13015 intel_fb->obj = obj;
13016 intel_fb->obj->framebuffer_references++;
13017
13018 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13019 if (ret) {
13020 DRM_ERROR("framebuffer init failed %d\n", ret);
13021 return ret;
13022 }
13023
13024 return 0;
13025 }
13026
13027 static struct drm_framebuffer *
13028 intel_user_framebuffer_create(struct drm_device *dev,
13029 struct drm_file *filp,
13030 struct drm_mode_fb_cmd2 *mode_cmd)
13031 {
13032 struct drm_i915_gem_object *obj;
13033
13034 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13035 mode_cmd->handles[0]));
13036 if (&obj->base == NULL)
13037 return ERR_PTR(-ENOENT);
13038
13039 return intel_framebuffer_create(dev, mode_cmd, obj);
13040 }
13041
13042 #ifndef CONFIG_DRM_I915_FBDEV
13043 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13044 {
13045 }
13046 #endif
13047
13048 static const struct drm_mode_config_funcs intel_mode_funcs = {
13049 .fb_create = intel_user_framebuffer_create,
13050 .output_poll_changed = intel_fbdev_output_poll_changed,
13051 .atomic_check = intel_atomic_check,
13052 .atomic_commit = intel_atomic_commit,
13053 };
13054
13055 /* Set up chip specific display functions */
13056 static void intel_init_display(struct drm_device *dev)
13057 {
13058 struct drm_i915_private *dev_priv = dev->dev_private;
13059
13060 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13061 dev_priv->display.find_dpll = g4x_find_best_dpll;
13062 else if (IS_CHERRYVIEW(dev))
13063 dev_priv->display.find_dpll = chv_find_best_dpll;
13064 else if (IS_VALLEYVIEW(dev))
13065 dev_priv->display.find_dpll = vlv_find_best_dpll;
13066 else if (IS_PINEVIEW(dev))
13067 dev_priv->display.find_dpll = pnv_find_best_dpll;
13068 else
13069 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13070
13071 if (INTEL_INFO(dev)->gen >= 9) {
13072 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13073 dev_priv->display.get_initial_plane_config =
13074 skylake_get_initial_plane_config;
13075 dev_priv->display.crtc_compute_clock =
13076 haswell_crtc_compute_clock;
13077 dev_priv->display.crtc_enable = haswell_crtc_enable;
13078 dev_priv->display.crtc_disable = haswell_crtc_disable;
13079 dev_priv->display.off = ironlake_crtc_off;
13080 dev_priv->display.update_primary_plane =
13081 skylake_update_primary_plane;
13082 } else if (HAS_DDI(dev)) {
13083 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13084 dev_priv->display.get_initial_plane_config =
13085 ironlake_get_initial_plane_config;
13086 dev_priv->display.crtc_compute_clock =
13087 haswell_crtc_compute_clock;
13088 dev_priv->display.crtc_enable = haswell_crtc_enable;
13089 dev_priv->display.crtc_disable = haswell_crtc_disable;
13090 dev_priv->display.off = ironlake_crtc_off;
13091 dev_priv->display.update_primary_plane =
13092 ironlake_update_primary_plane;
13093 } else if (HAS_PCH_SPLIT(dev)) {
13094 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13095 dev_priv->display.get_initial_plane_config =
13096 ironlake_get_initial_plane_config;
13097 dev_priv->display.crtc_compute_clock =
13098 ironlake_crtc_compute_clock;
13099 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13100 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13101 dev_priv->display.off = ironlake_crtc_off;
13102 dev_priv->display.update_primary_plane =
13103 ironlake_update_primary_plane;
13104 } else if (IS_VALLEYVIEW(dev)) {
13105 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13106 dev_priv->display.get_initial_plane_config =
13107 i9xx_get_initial_plane_config;
13108 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13109 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13110 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13111 dev_priv->display.off = i9xx_crtc_off;
13112 dev_priv->display.update_primary_plane =
13113 i9xx_update_primary_plane;
13114 } else {
13115 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13116 dev_priv->display.get_initial_plane_config =
13117 i9xx_get_initial_plane_config;
13118 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13119 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13120 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13121 dev_priv->display.off = i9xx_crtc_off;
13122 dev_priv->display.update_primary_plane =
13123 i9xx_update_primary_plane;
13124 }
13125
13126 /* Returns the core display clock speed */
13127 if (IS_VALLEYVIEW(dev))
13128 dev_priv->display.get_display_clock_speed =
13129 valleyview_get_display_clock_speed;
13130 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13131 dev_priv->display.get_display_clock_speed =
13132 i945_get_display_clock_speed;
13133 else if (IS_I915G(dev))
13134 dev_priv->display.get_display_clock_speed =
13135 i915_get_display_clock_speed;
13136 else if (IS_I945GM(dev) || IS_845G(dev))
13137 dev_priv->display.get_display_clock_speed =
13138 i9xx_misc_get_display_clock_speed;
13139 else if (IS_PINEVIEW(dev))
13140 dev_priv->display.get_display_clock_speed =
13141 pnv_get_display_clock_speed;
13142 else if (IS_I915GM(dev))
13143 dev_priv->display.get_display_clock_speed =
13144 i915gm_get_display_clock_speed;
13145 else if (IS_I865G(dev))
13146 dev_priv->display.get_display_clock_speed =
13147 i865_get_display_clock_speed;
13148 else if (IS_I85X(dev))
13149 dev_priv->display.get_display_clock_speed =
13150 i855_get_display_clock_speed;
13151 else /* 852, 830 */
13152 dev_priv->display.get_display_clock_speed =
13153 i830_get_display_clock_speed;
13154
13155 if (IS_GEN5(dev)) {
13156 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13157 } else if (IS_GEN6(dev)) {
13158 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13159 } else if (IS_IVYBRIDGE(dev)) {
13160 /* FIXME: detect B0+ stepping and use auto training */
13161 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13162 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13163 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13164 } else if (IS_VALLEYVIEW(dev)) {
13165 dev_priv->display.modeset_global_resources =
13166 valleyview_modeset_global_resources;
13167 }
13168
13169 switch (INTEL_INFO(dev)->gen) {
13170 case 2:
13171 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13172 break;
13173
13174 case 3:
13175 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13176 break;
13177
13178 case 4:
13179 case 5:
13180 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13181 break;
13182
13183 case 6:
13184 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13185 break;
13186 case 7:
13187 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13188 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13189 break;
13190 case 9:
13191 /* Drop through - unsupported since execlist only. */
13192 default:
13193 /* Default just returns -ENODEV to indicate unsupported */
13194 dev_priv->display.queue_flip = intel_default_queue_flip;
13195 }
13196
13197 intel_panel_init_backlight_funcs(dev);
13198
13199 mutex_init(&dev_priv->pps_mutex);
13200 }
13201
13202 /*
13203 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13204 * resume, or other times. This quirk makes sure that's the case for
13205 * affected systems.
13206 */
13207 static void quirk_pipea_force(struct drm_device *dev)
13208 {
13209 struct drm_i915_private *dev_priv = dev->dev_private;
13210
13211 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13212 DRM_INFO("applying pipe a force quirk\n");
13213 }
13214
13215 static void quirk_pipeb_force(struct drm_device *dev)
13216 {
13217 struct drm_i915_private *dev_priv = dev->dev_private;
13218
13219 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13220 DRM_INFO("applying pipe b force quirk\n");
13221 }
13222
13223 /*
13224 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13225 */
13226 static void quirk_ssc_force_disable(struct drm_device *dev)
13227 {
13228 struct drm_i915_private *dev_priv = dev->dev_private;
13229 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13230 DRM_INFO("applying lvds SSC disable quirk\n");
13231 }
13232
13233 /*
13234 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13235 * brightness value
13236 */
13237 static void quirk_invert_brightness(struct drm_device *dev)
13238 {
13239 struct drm_i915_private *dev_priv = dev->dev_private;
13240 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13241 DRM_INFO("applying inverted panel brightness quirk\n");
13242 }
13243
13244 /* Some VBT's incorrectly indicate no backlight is present */
13245 static void quirk_backlight_present(struct drm_device *dev)
13246 {
13247 struct drm_i915_private *dev_priv = dev->dev_private;
13248 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13249 DRM_INFO("applying backlight present quirk\n");
13250 }
13251
13252 struct intel_quirk {
13253 int device;
13254 int subsystem_vendor;
13255 int subsystem_device;
13256 void (*hook)(struct drm_device *dev);
13257 };
13258
13259 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13260 struct intel_dmi_quirk {
13261 void (*hook)(struct drm_device *dev);
13262 const struct dmi_system_id (*dmi_id_list)[];
13263 };
13264
13265 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13266 {
13267 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13268 return 1;
13269 }
13270
13271 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13272 {
13273 .dmi_id_list = &(const struct dmi_system_id[]) {
13274 {
13275 .callback = intel_dmi_reverse_brightness,
13276 .ident = "NCR Corporation",
13277 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13278 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13279 },
13280 },
13281 { } /* terminating entry */
13282 },
13283 .hook = quirk_invert_brightness,
13284 },
13285 };
13286
13287 static struct intel_quirk intel_quirks[] = {
13288 /* HP Mini needs pipe A force quirk (LP: #322104) */
13289 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13290
13291 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13292 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13293
13294 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13295 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13296
13297 /* 830 needs to leave pipe A & dpll A up */
13298 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13299
13300 /* 830 needs to leave pipe B & dpll B up */
13301 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13302
13303 /* Lenovo U160 cannot use SSC on LVDS */
13304 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13305
13306 /* Sony Vaio Y cannot use SSC on LVDS */
13307 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13308
13309 /* Acer Aspire 5734Z must invert backlight brightness */
13310 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13311
13312 /* Acer/eMachines G725 */
13313 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13314
13315 /* Acer/eMachines e725 */
13316 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13317
13318 /* Acer/Packard Bell NCL20 */
13319 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13320
13321 /* Acer Aspire 4736Z */
13322 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13323
13324 /* Acer Aspire 5336 */
13325 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13326
13327 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13328 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13329
13330 /* Acer C720 Chromebook (Core i3 4005U) */
13331 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13332
13333 /* Apple Macbook 2,1 (Core 2 T7400) */
13334 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13335
13336 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13337 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13338
13339 /* HP Chromebook 14 (Celeron 2955U) */
13340 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13341
13342 /* Dell Chromebook 11 */
13343 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13344 };
13345
13346 static void intel_init_quirks(struct drm_device *dev)
13347 {
13348 struct pci_dev *d = dev->pdev;
13349 int i;
13350
13351 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13352 struct intel_quirk *q = &intel_quirks[i];
13353
13354 if (d->device == q->device &&
13355 (d->subsystem_vendor == q->subsystem_vendor ||
13356 q->subsystem_vendor == PCI_ANY_ID) &&
13357 (d->subsystem_device == q->subsystem_device ||
13358 q->subsystem_device == PCI_ANY_ID))
13359 q->hook(dev);
13360 }
13361 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13362 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13363 intel_dmi_quirks[i].hook(dev);
13364 }
13365 }
13366
13367 /* Disable the VGA plane that we never use */
13368 static void i915_disable_vga(struct drm_device *dev)
13369 {
13370 struct drm_i915_private *dev_priv = dev->dev_private;
13371 u8 sr1;
13372 u32 vga_reg = i915_vgacntrl_reg(dev);
13373
13374 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13375 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13376 outb(SR01, VGA_SR_INDEX);
13377 sr1 = inb(VGA_SR_DATA);
13378 outb(sr1 | 1<<5, VGA_SR_DATA);
13379 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13380 udelay(300);
13381
13382 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13383 POSTING_READ(vga_reg);
13384 }
13385
13386 void intel_modeset_init_hw(struct drm_device *dev)
13387 {
13388 intel_prepare_ddi(dev);
13389
13390 if (IS_VALLEYVIEW(dev))
13391 vlv_update_cdclk(dev);
13392
13393 intel_init_clock_gating(dev);
13394
13395 intel_enable_gt_powersave(dev);
13396 }
13397
13398 void intel_modeset_init(struct drm_device *dev)
13399 {
13400 struct drm_i915_private *dev_priv = dev->dev_private;
13401 int sprite, ret;
13402 enum pipe pipe;
13403 struct intel_crtc *crtc;
13404
13405 drm_mode_config_init(dev);
13406
13407 dev->mode_config.min_width = 0;
13408 dev->mode_config.min_height = 0;
13409
13410 dev->mode_config.preferred_depth = 24;
13411 dev->mode_config.prefer_shadow = 1;
13412
13413 dev->mode_config.allow_fb_modifiers = true;
13414
13415 dev->mode_config.funcs = &intel_mode_funcs;
13416
13417 intel_init_quirks(dev);
13418
13419 intel_init_pm(dev);
13420
13421 if (INTEL_INFO(dev)->num_pipes == 0)
13422 return;
13423
13424 intel_init_display(dev);
13425 intel_init_audio(dev);
13426
13427 if (IS_GEN2(dev)) {
13428 dev->mode_config.max_width = 2048;
13429 dev->mode_config.max_height = 2048;
13430 } else if (IS_GEN3(dev)) {
13431 dev->mode_config.max_width = 4096;
13432 dev->mode_config.max_height = 4096;
13433 } else {
13434 dev->mode_config.max_width = 8192;
13435 dev->mode_config.max_height = 8192;
13436 }
13437
13438 if (IS_845G(dev) || IS_I865G(dev)) {
13439 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13440 dev->mode_config.cursor_height = 1023;
13441 } else if (IS_GEN2(dev)) {
13442 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13443 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13444 } else {
13445 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13446 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13447 }
13448
13449 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13450
13451 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13452 INTEL_INFO(dev)->num_pipes,
13453 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13454
13455 for_each_pipe(dev_priv, pipe) {
13456 intel_crtc_init(dev, pipe);
13457 for_each_sprite(dev_priv, pipe, sprite) {
13458 ret = intel_plane_init(dev, pipe, sprite);
13459 if (ret)
13460 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13461 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13462 }
13463 }
13464
13465 intel_init_dpio(dev);
13466
13467 intel_shared_dpll_init(dev);
13468
13469 /* Just disable it once at startup */
13470 i915_disable_vga(dev);
13471 intel_setup_outputs(dev);
13472
13473 /* Just in case the BIOS is doing something questionable. */
13474 intel_fbc_disable(dev);
13475
13476 drm_modeset_lock_all(dev);
13477 intel_modeset_setup_hw_state(dev, false);
13478 drm_modeset_unlock_all(dev);
13479
13480 for_each_intel_crtc(dev, crtc) {
13481 if (!crtc->active)
13482 continue;
13483
13484 /*
13485 * Note that reserving the BIOS fb up front prevents us
13486 * from stuffing other stolen allocations like the ring
13487 * on top. This prevents some ugliness at boot time, and
13488 * can even allow for smooth boot transitions if the BIOS
13489 * fb is large enough for the active pipe configuration.
13490 */
13491 if (dev_priv->display.get_initial_plane_config) {
13492 dev_priv->display.get_initial_plane_config(crtc,
13493 &crtc->plane_config);
13494 /*
13495 * If the fb is shared between multiple heads, we'll
13496 * just get the first one.
13497 */
13498 intel_find_plane_obj(crtc, &crtc->plane_config);
13499 }
13500 }
13501 }
13502
13503 static void intel_enable_pipe_a(struct drm_device *dev)
13504 {
13505 struct intel_connector *connector;
13506 struct drm_connector *crt = NULL;
13507 struct intel_load_detect_pipe load_detect_temp;
13508 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13509
13510 /* We can't just switch on the pipe A, we need to set things up with a
13511 * proper mode and output configuration. As a gross hack, enable pipe A
13512 * by enabling the load detect pipe once. */
13513 for_each_intel_connector(dev, connector) {
13514 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13515 crt = &connector->base;
13516 break;
13517 }
13518 }
13519
13520 if (!crt)
13521 return;
13522
13523 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13524 intel_release_load_detect_pipe(crt, &load_detect_temp);
13525 }
13526
13527 static bool
13528 intel_check_plane_mapping(struct intel_crtc *crtc)
13529 {
13530 struct drm_device *dev = crtc->base.dev;
13531 struct drm_i915_private *dev_priv = dev->dev_private;
13532 u32 reg, val;
13533
13534 if (INTEL_INFO(dev)->num_pipes == 1)
13535 return true;
13536
13537 reg = DSPCNTR(!crtc->plane);
13538 val = I915_READ(reg);
13539
13540 if ((val & DISPLAY_PLANE_ENABLE) &&
13541 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13542 return false;
13543
13544 return true;
13545 }
13546
13547 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13548 {
13549 struct drm_device *dev = crtc->base.dev;
13550 struct drm_i915_private *dev_priv = dev->dev_private;
13551 u32 reg;
13552
13553 /* Clear any frame start delays used for debugging left by the BIOS */
13554 reg = PIPECONF(crtc->config->cpu_transcoder);
13555 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13556
13557 /* restore vblank interrupts to correct state */
13558 drm_crtc_vblank_reset(&crtc->base);
13559 if (crtc->active) {
13560 update_scanline_offset(crtc);
13561 drm_crtc_vblank_on(&crtc->base);
13562 }
13563
13564 /* We need to sanitize the plane -> pipe mapping first because this will
13565 * disable the crtc (and hence change the state) if it is wrong. Note
13566 * that gen4+ has a fixed plane -> pipe mapping. */
13567 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13568 struct intel_connector *connector;
13569 bool plane;
13570
13571 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13572 crtc->base.base.id);
13573
13574 /* Pipe has the wrong plane attached and the plane is active.
13575 * Temporarily change the plane mapping and disable everything
13576 * ... */
13577 plane = crtc->plane;
13578 crtc->plane = !plane;
13579 crtc->primary_enabled = true;
13580 dev_priv->display.crtc_disable(&crtc->base);
13581 crtc->plane = plane;
13582
13583 /* ... and break all links. */
13584 for_each_intel_connector(dev, connector) {
13585 if (connector->encoder->base.crtc != &crtc->base)
13586 continue;
13587
13588 connector->base.dpms = DRM_MODE_DPMS_OFF;
13589 connector->base.encoder = NULL;
13590 }
13591 /* multiple connectors may have the same encoder:
13592 * handle them and break crtc link separately */
13593 for_each_intel_connector(dev, connector)
13594 if (connector->encoder->base.crtc == &crtc->base) {
13595 connector->encoder->base.crtc = NULL;
13596 connector->encoder->connectors_active = false;
13597 }
13598
13599 WARN_ON(crtc->active);
13600 crtc->base.state->enable = false;
13601 crtc->base.enabled = false;
13602 }
13603
13604 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13605 crtc->pipe == PIPE_A && !crtc->active) {
13606 /* BIOS forgot to enable pipe A, this mostly happens after
13607 * resume. Force-enable the pipe to fix this, the update_dpms
13608 * call below we restore the pipe to the right state, but leave
13609 * the required bits on. */
13610 intel_enable_pipe_a(dev);
13611 }
13612
13613 /* Adjust the state of the output pipe according to whether we
13614 * have active connectors/encoders. */
13615 intel_crtc_update_dpms(&crtc->base);
13616
13617 if (crtc->active != crtc->base.state->enable) {
13618 struct intel_encoder *encoder;
13619
13620 /* This can happen either due to bugs in the get_hw_state
13621 * functions or because the pipe is force-enabled due to the
13622 * pipe A quirk. */
13623 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13624 crtc->base.base.id,
13625 crtc->base.state->enable ? "enabled" : "disabled",
13626 crtc->active ? "enabled" : "disabled");
13627
13628 crtc->base.state->enable = crtc->active;
13629 crtc->base.enabled = crtc->active;
13630
13631 /* Because we only establish the connector -> encoder ->
13632 * crtc links if something is active, this means the
13633 * crtc is now deactivated. Break the links. connector
13634 * -> encoder links are only establish when things are
13635 * actually up, hence no need to break them. */
13636 WARN_ON(crtc->active);
13637
13638 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13639 WARN_ON(encoder->connectors_active);
13640 encoder->base.crtc = NULL;
13641 }
13642 }
13643
13644 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13645 /*
13646 * We start out with underrun reporting disabled to avoid races.
13647 * For correct bookkeeping mark this on active crtcs.
13648 *
13649 * Also on gmch platforms we dont have any hardware bits to
13650 * disable the underrun reporting. Which means we need to start
13651 * out with underrun reporting disabled also on inactive pipes,
13652 * since otherwise we'll complain about the garbage we read when
13653 * e.g. coming up after runtime pm.
13654 *
13655 * No protection against concurrent access is required - at
13656 * worst a fifo underrun happens which also sets this to false.
13657 */
13658 crtc->cpu_fifo_underrun_disabled = true;
13659 crtc->pch_fifo_underrun_disabled = true;
13660 }
13661 }
13662
13663 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13664 {
13665 struct intel_connector *connector;
13666 struct drm_device *dev = encoder->base.dev;
13667
13668 /* We need to check both for a crtc link (meaning that the
13669 * encoder is active and trying to read from a pipe) and the
13670 * pipe itself being active. */
13671 bool has_active_crtc = encoder->base.crtc &&
13672 to_intel_crtc(encoder->base.crtc)->active;
13673
13674 if (encoder->connectors_active && !has_active_crtc) {
13675 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13676 encoder->base.base.id,
13677 encoder->base.name);
13678
13679 /* Connector is active, but has no active pipe. This is
13680 * fallout from our resume register restoring. Disable
13681 * the encoder manually again. */
13682 if (encoder->base.crtc) {
13683 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13684 encoder->base.base.id,
13685 encoder->base.name);
13686 encoder->disable(encoder);
13687 if (encoder->post_disable)
13688 encoder->post_disable(encoder);
13689 }
13690 encoder->base.crtc = NULL;
13691 encoder->connectors_active = false;
13692
13693 /* Inconsistent output/port/pipe state happens presumably due to
13694 * a bug in one of the get_hw_state functions. Or someplace else
13695 * in our code, like the register restore mess on resume. Clamp
13696 * things to off as a safer default. */
13697 for_each_intel_connector(dev, connector) {
13698 if (connector->encoder != encoder)
13699 continue;
13700 connector->base.dpms = DRM_MODE_DPMS_OFF;
13701 connector->base.encoder = NULL;
13702 }
13703 }
13704 /* Enabled encoders without active connectors will be fixed in
13705 * the crtc fixup. */
13706 }
13707
13708 void i915_redisable_vga_power_on(struct drm_device *dev)
13709 {
13710 struct drm_i915_private *dev_priv = dev->dev_private;
13711 u32 vga_reg = i915_vgacntrl_reg(dev);
13712
13713 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13714 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13715 i915_disable_vga(dev);
13716 }
13717 }
13718
13719 void i915_redisable_vga(struct drm_device *dev)
13720 {
13721 struct drm_i915_private *dev_priv = dev->dev_private;
13722
13723 /* This function can be called both from intel_modeset_setup_hw_state or
13724 * at a very early point in our resume sequence, where the power well
13725 * structures are not yet restored. Since this function is at a very
13726 * paranoid "someone might have enabled VGA while we were not looking"
13727 * level, just check if the power well is enabled instead of trying to
13728 * follow the "don't touch the power well if we don't need it" policy
13729 * the rest of the driver uses. */
13730 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13731 return;
13732
13733 i915_redisable_vga_power_on(dev);
13734 }
13735
13736 static bool primary_get_hw_state(struct intel_crtc *crtc)
13737 {
13738 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13739
13740 if (!crtc->active)
13741 return false;
13742
13743 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13744 }
13745
13746 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13747 {
13748 struct drm_i915_private *dev_priv = dev->dev_private;
13749 enum pipe pipe;
13750 struct intel_crtc *crtc;
13751 struct intel_encoder *encoder;
13752 struct intel_connector *connector;
13753 int i;
13754
13755 for_each_intel_crtc(dev, crtc) {
13756 memset(crtc->config, 0, sizeof(*crtc->config));
13757
13758 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13759
13760 crtc->active = dev_priv->display.get_pipe_config(crtc,
13761 crtc->config);
13762
13763 crtc->base.state->enable = crtc->active;
13764 crtc->base.enabled = crtc->active;
13765 crtc->primary_enabled = primary_get_hw_state(crtc);
13766
13767 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13768 crtc->base.base.id,
13769 crtc->active ? "enabled" : "disabled");
13770 }
13771
13772 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13773 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13774
13775 pll->on = pll->get_hw_state(dev_priv, pll,
13776 &pll->config.hw_state);
13777 pll->active = 0;
13778 pll->config.crtc_mask = 0;
13779 for_each_intel_crtc(dev, crtc) {
13780 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13781 pll->active++;
13782 pll->config.crtc_mask |= 1 << crtc->pipe;
13783 }
13784 }
13785
13786 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13787 pll->name, pll->config.crtc_mask, pll->on);
13788
13789 if (pll->config.crtc_mask)
13790 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13791 }
13792
13793 for_each_intel_encoder(dev, encoder) {
13794 pipe = 0;
13795
13796 if (encoder->get_hw_state(encoder, &pipe)) {
13797 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13798 encoder->base.crtc = &crtc->base;
13799 encoder->get_config(encoder, crtc->config);
13800 } else {
13801 encoder->base.crtc = NULL;
13802 }
13803
13804 encoder->connectors_active = false;
13805 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13806 encoder->base.base.id,
13807 encoder->base.name,
13808 encoder->base.crtc ? "enabled" : "disabled",
13809 pipe_name(pipe));
13810 }
13811
13812 for_each_intel_connector(dev, connector) {
13813 if (connector->get_hw_state(connector)) {
13814 connector->base.dpms = DRM_MODE_DPMS_ON;
13815 connector->encoder->connectors_active = true;
13816 connector->base.encoder = &connector->encoder->base;
13817 } else {
13818 connector->base.dpms = DRM_MODE_DPMS_OFF;
13819 connector->base.encoder = NULL;
13820 }
13821 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13822 connector->base.base.id,
13823 connector->base.name,
13824 connector->base.encoder ? "enabled" : "disabled");
13825 }
13826 }
13827
13828 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13829 * and i915 state tracking structures. */
13830 void intel_modeset_setup_hw_state(struct drm_device *dev,
13831 bool force_restore)
13832 {
13833 struct drm_i915_private *dev_priv = dev->dev_private;
13834 enum pipe pipe;
13835 struct intel_crtc *crtc;
13836 struct intel_encoder *encoder;
13837 int i;
13838
13839 intel_modeset_readout_hw_state(dev);
13840
13841 /*
13842 * Now that we have the config, copy it to each CRTC struct
13843 * Note that this could go away if we move to using crtc_config
13844 * checking everywhere.
13845 */
13846 for_each_intel_crtc(dev, crtc) {
13847 if (crtc->active && i915.fastboot) {
13848 intel_mode_from_pipe_config(&crtc->base.mode,
13849 crtc->config);
13850 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13851 crtc->base.base.id);
13852 drm_mode_debug_printmodeline(&crtc->base.mode);
13853 }
13854 }
13855
13856 /* HW state is read out, now we need to sanitize this mess. */
13857 for_each_intel_encoder(dev, encoder) {
13858 intel_sanitize_encoder(encoder);
13859 }
13860
13861 for_each_pipe(dev_priv, pipe) {
13862 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13863 intel_sanitize_crtc(crtc);
13864 intel_dump_pipe_config(crtc, crtc->config,
13865 "[setup_hw_state]");
13866 }
13867
13868 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13869 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13870
13871 if (!pll->on || pll->active)
13872 continue;
13873
13874 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13875
13876 pll->disable(dev_priv, pll);
13877 pll->on = false;
13878 }
13879
13880 if (IS_GEN9(dev))
13881 skl_wm_get_hw_state(dev);
13882 else if (HAS_PCH_SPLIT(dev))
13883 ilk_wm_get_hw_state(dev);
13884
13885 if (force_restore) {
13886 i915_redisable_vga(dev);
13887
13888 /*
13889 * We need to use raw interfaces for restoring state to avoid
13890 * checking (bogus) intermediate states.
13891 */
13892 for_each_pipe(dev_priv, pipe) {
13893 struct drm_crtc *crtc =
13894 dev_priv->pipe_to_crtc_mapping[pipe];
13895
13896 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13897 crtc->primary->fb);
13898 }
13899 } else {
13900 intel_modeset_update_staged_output_state(dev);
13901 }
13902
13903 intel_modeset_check_state(dev);
13904 }
13905
13906 void intel_modeset_gem_init(struct drm_device *dev)
13907 {
13908 struct drm_i915_private *dev_priv = dev->dev_private;
13909 struct drm_crtc *c;
13910 struct drm_i915_gem_object *obj;
13911
13912 mutex_lock(&dev->struct_mutex);
13913 intel_init_gt_powersave(dev);
13914 mutex_unlock(&dev->struct_mutex);
13915
13916 /*
13917 * There may be no VBT; and if the BIOS enabled SSC we can
13918 * just keep using it to avoid unnecessary flicker. Whereas if the
13919 * BIOS isn't using it, don't assume it will work even if the VBT
13920 * indicates as much.
13921 */
13922 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13923 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13924 DREF_SSC1_ENABLE);
13925
13926 intel_modeset_init_hw(dev);
13927
13928 intel_setup_overlay(dev);
13929
13930 /*
13931 * Make sure any fbs we allocated at startup are properly
13932 * pinned & fenced. When we do the allocation it's too early
13933 * for this.
13934 */
13935 mutex_lock(&dev->struct_mutex);
13936 for_each_crtc(dev, c) {
13937 obj = intel_fb_obj(c->primary->fb);
13938 if (obj == NULL)
13939 continue;
13940
13941 if (intel_pin_and_fence_fb_obj(c->primary,
13942 c->primary->fb,
13943 NULL)) {
13944 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13945 to_intel_crtc(c)->pipe);
13946 drm_framebuffer_unreference(c->primary->fb);
13947 c->primary->fb = NULL;
13948 update_state_fb(c->primary);
13949 }
13950 }
13951 mutex_unlock(&dev->struct_mutex);
13952
13953 intel_backlight_register(dev);
13954 }
13955
13956 void intel_connector_unregister(struct intel_connector *intel_connector)
13957 {
13958 struct drm_connector *connector = &intel_connector->base;
13959
13960 intel_panel_destroy_backlight(connector);
13961 drm_connector_unregister(connector);
13962 }
13963
13964 void intel_modeset_cleanup(struct drm_device *dev)
13965 {
13966 struct drm_i915_private *dev_priv = dev->dev_private;
13967 struct drm_connector *connector;
13968
13969 intel_disable_gt_powersave(dev);
13970
13971 intel_backlight_unregister(dev);
13972
13973 /*
13974 * Interrupts and polling as the first thing to avoid creating havoc.
13975 * Too much stuff here (turning of connectors, ...) would
13976 * experience fancy races otherwise.
13977 */
13978 intel_irq_uninstall(dev_priv);
13979
13980 /*
13981 * Due to the hpd irq storm handling the hotplug work can re-arm the
13982 * poll handlers. Hence disable polling after hpd handling is shut down.
13983 */
13984 drm_kms_helper_poll_fini(dev);
13985
13986 mutex_lock(&dev->struct_mutex);
13987
13988 intel_unregister_dsm_handler();
13989
13990 intel_fbc_disable(dev);
13991
13992 mutex_unlock(&dev->struct_mutex);
13993
13994 /* flush any delayed tasks or pending work */
13995 flush_scheduled_work();
13996
13997 /* destroy the backlight and sysfs files before encoders/connectors */
13998 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13999 struct intel_connector *intel_connector;
14000
14001 intel_connector = to_intel_connector(connector);
14002 intel_connector->unregister(intel_connector);
14003 }
14004
14005 drm_mode_config_cleanup(dev);
14006
14007 intel_cleanup_overlay(dev);
14008
14009 mutex_lock(&dev->struct_mutex);
14010 intel_cleanup_gt_powersave(dev);
14011 mutex_unlock(&dev->struct_mutex);
14012 }
14013
14014 /*
14015 * Return which encoder is currently attached for connector.
14016 */
14017 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14018 {
14019 return &intel_attached_encoder(connector)->base;
14020 }
14021
14022 void intel_connector_attach_encoder(struct intel_connector *connector,
14023 struct intel_encoder *encoder)
14024 {
14025 connector->encoder = encoder;
14026 drm_mode_connector_attach_encoder(&connector->base,
14027 &encoder->base);
14028 }
14029
14030 /*
14031 * set vga decode state - true == enable VGA decode
14032 */
14033 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14034 {
14035 struct drm_i915_private *dev_priv = dev->dev_private;
14036 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14037 u16 gmch_ctrl;
14038
14039 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14040 DRM_ERROR("failed to read control word\n");
14041 return -EIO;
14042 }
14043
14044 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14045 return 0;
14046
14047 if (state)
14048 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14049 else
14050 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14051
14052 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14053 DRM_ERROR("failed to write control word\n");
14054 return -EIO;
14055 }
14056
14057 return 0;
14058 }
14059
14060 struct intel_display_error_state {
14061
14062 u32 power_well_driver;
14063
14064 int num_transcoders;
14065
14066 struct intel_cursor_error_state {
14067 u32 control;
14068 u32 position;
14069 u32 base;
14070 u32 size;
14071 } cursor[I915_MAX_PIPES];
14072
14073 struct intel_pipe_error_state {
14074 bool power_domain_on;
14075 u32 source;
14076 u32 stat;
14077 } pipe[I915_MAX_PIPES];
14078
14079 struct intel_plane_error_state {
14080 u32 control;
14081 u32 stride;
14082 u32 size;
14083 u32 pos;
14084 u32 addr;
14085 u32 surface;
14086 u32 tile_offset;
14087 } plane[I915_MAX_PIPES];
14088
14089 struct intel_transcoder_error_state {
14090 bool power_domain_on;
14091 enum transcoder cpu_transcoder;
14092
14093 u32 conf;
14094
14095 u32 htotal;
14096 u32 hblank;
14097 u32 hsync;
14098 u32 vtotal;
14099 u32 vblank;
14100 u32 vsync;
14101 } transcoder[4];
14102 };
14103
14104 struct intel_display_error_state *
14105 intel_display_capture_error_state(struct drm_device *dev)
14106 {
14107 struct drm_i915_private *dev_priv = dev->dev_private;
14108 struct intel_display_error_state *error;
14109 int transcoders[] = {
14110 TRANSCODER_A,
14111 TRANSCODER_B,
14112 TRANSCODER_C,
14113 TRANSCODER_EDP,
14114 };
14115 int i;
14116
14117 if (INTEL_INFO(dev)->num_pipes == 0)
14118 return NULL;
14119
14120 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14121 if (error == NULL)
14122 return NULL;
14123
14124 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14125 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14126
14127 for_each_pipe(dev_priv, i) {
14128 error->pipe[i].power_domain_on =
14129 __intel_display_power_is_enabled(dev_priv,
14130 POWER_DOMAIN_PIPE(i));
14131 if (!error->pipe[i].power_domain_on)
14132 continue;
14133
14134 error->cursor[i].control = I915_READ(CURCNTR(i));
14135 error->cursor[i].position = I915_READ(CURPOS(i));
14136 error->cursor[i].base = I915_READ(CURBASE(i));
14137
14138 error->plane[i].control = I915_READ(DSPCNTR(i));
14139 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14140 if (INTEL_INFO(dev)->gen <= 3) {
14141 error->plane[i].size = I915_READ(DSPSIZE(i));
14142 error->plane[i].pos = I915_READ(DSPPOS(i));
14143 }
14144 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14145 error->plane[i].addr = I915_READ(DSPADDR(i));
14146 if (INTEL_INFO(dev)->gen >= 4) {
14147 error->plane[i].surface = I915_READ(DSPSURF(i));
14148 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14149 }
14150
14151 error->pipe[i].source = I915_READ(PIPESRC(i));
14152
14153 if (HAS_GMCH_DISPLAY(dev))
14154 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14155 }
14156
14157 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14158 if (HAS_DDI(dev_priv->dev))
14159 error->num_transcoders++; /* Account for eDP. */
14160
14161 for (i = 0; i < error->num_transcoders; i++) {
14162 enum transcoder cpu_transcoder = transcoders[i];
14163
14164 error->transcoder[i].power_domain_on =
14165 __intel_display_power_is_enabled(dev_priv,
14166 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14167 if (!error->transcoder[i].power_domain_on)
14168 continue;
14169
14170 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14171
14172 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14173 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14174 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14175 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14176 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14177 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14178 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14179 }
14180
14181 return error;
14182 }
14183
14184 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14185
14186 void
14187 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14188 struct drm_device *dev,
14189 struct intel_display_error_state *error)
14190 {
14191 struct drm_i915_private *dev_priv = dev->dev_private;
14192 int i;
14193
14194 if (!error)
14195 return;
14196
14197 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14198 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14199 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14200 error->power_well_driver);
14201 for_each_pipe(dev_priv, i) {
14202 err_printf(m, "Pipe [%d]:\n", i);
14203 err_printf(m, " Power: %s\n",
14204 error->pipe[i].power_domain_on ? "on" : "off");
14205 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14206 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14207
14208 err_printf(m, "Plane [%d]:\n", i);
14209 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14210 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14211 if (INTEL_INFO(dev)->gen <= 3) {
14212 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14213 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14214 }
14215 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14216 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14217 if (INTEL_INFO(dev)->gen >= 4) {
14218 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14219 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14220 }
14221
14222 err_printf(m, "Cursor [%d]:\n", i);
14223 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14224 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14225 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14226 }
14227
14228 for (i = 0; i < error->num_transcoders; i++) {
14229 err_printf(m, "CPU transcoder: %c\n",
14230 transcoder_name(error->transcoder[i].cpu_transcoder));
14231 err_printf(m, " Power: %s\n",
14232 error->transcoder[i].power_domain_on ? "on" : "off");
14233 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14234 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14235 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14236 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14237 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14238 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14239 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14240 }
14241 }
14242
14243 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14244 {
14245 struct intel_crtc *crtc;
14246
14247 for_each_intel_crtc(dev, crtc) {
14248 struct intel_unpin_work *work;
14249
14250 spin_lock_irq(&dev->event_lock);
14251
14252 work = crtc->unpin_work;
14253
14254 if (work && work->event &&
14255 work->event->base.file_priv == file) {
14256 kfree(work->event);
14257 work->event = NULL;
14258 }
14259
14260 spin_unlock_irq(&dev->event_lock);
14261 }
14262 }
Linux kernel - Deliverables
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