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drm/i915: Return more precise cdclk for gen2/3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
88 static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
92 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
97 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
98 static void haswell_set_pipeconf(struct drm_crtc *crtc);
99 static void intel_set_pipe_csc(struct drm_crtc *crtc);
100 static void vlv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void chv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
106
107 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108 {
109 if (!connector->mst_port)
110 return connector->encoder;
111 else
112 return &connector->mst_port->mst_encoders[pipe]->base;
113 }
114
115 typedef struct {
116 int min, max;
117 } intel_range_t;
118
119 typedef struct {
120 int dot_limit;
121 int p2_slow, p2_fast;
122 } intel_p2_t;
123
124 typedef struct intel_limit intel_limit_t;
125 struct intel_limit {
126 intel_range_t dot, vco, n, m, m1, m2, p, p1;
127 intel_p2_t p2;
128 };
129
130 int
131 intel_pch_rawclk(struct drm_device *dev)
132 {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134
135 WARN_ON(!HAS_PCH_SPLIT(dev));
136
137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 }
139
140 static inline u32 /* units of 100MHz */
141 intel_fdi_link_freq(struct drm_device *dev)
142 {
143 if (IS_GEN5(dev)) {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
146 } else
147 return 27;
148 }
149
150 static const intel_limit_t intel_limits_i8xx_dac = {
151 .dot = { .min = 25000, .max = 350000 },
152 .vco = { .min = 908000, .max = 1512000 },
153 .n = { .min = 2, .max = 16 },
154 .m = { .min = 96, .max = 140 },
155 .m1 = { .min = 18, .max = 26 },
156 .m2 = { .min = 6, .max = 16 },
157 .p = { .min = 4, .max = 128 },
158 .p1 = { .min = 2, .max = 33 },
159 .p2 = { .dot_limit = 165000,
160 .p2_slow = 4, .p2_fast = 2 },
161 };
162
163 static const intel_limit_t intel_limits_i8xx_dvo = {
164 .dot = { .min = 25000, .max = 350000 },
165 .vco = { .min = 908000, .max = 1512000 },
166 .n = { .min = 2, .max = 16 },
167 .m = { .min = 96, .max = 140 },
168 .m1 = { .min = 18, .max = 26 },
169 .m2 = { .min = 6, .max = 16 },
170 .p = { .min = 4, .max = 128 },
171 .p1 = { .min = 2, .max = 33 },
172 .p2 = { .dot_limit = 165000,
173 .p2_slow = 4, .p2_fast = 4 },
174 };
175
176 static const intel_limit_t intel_limits_i8xx_lvds = {
177 .dot = { .min = 25000, .max = 350000 },
178 .vco = { .min = 908000, .max = 1512000 },
179 .n = { .min = 2, .max = 16 },
180 .m = { .min = 96, .max = 140 },
181 .m1 = { .min = 18, .max = 26 },
182 .m2 = { .min = 6, .max = 16 },
183 .p = { .min = 4, .max = 128 },
184 .p1 = { .min = 1, .max = 6 },
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 14, .p2_fast = 7 },
187 };
188
189 static const intel_limit_t intel_limits_i9xx_sdvo = {
190 .dot = { .min = 20000, .max = 400000 },
191 .vco = { .min = 1400000, .max = 2800000 },
192 .n = { .min = 1, .max = 6 },
193 .m = { .min = 70, .max = 120 },
194 .m1 = { .min = 8, .max = 18 },
195 .m2 = { .min = 3, .max = 7 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8 },
198 .p2 = { .dot_limit = 200000,
199 .p2_slow = 10, .p2_fast = 5 },
200 };
201
202 static const intel_limit_t intel_limits_i9xx_lvds = {
203 .dot = { .min = 20000, .max = 400000 },
204 .vco = { .min = 1400000, .max = 2800000 },
205 .n = { .min = 1, .max = 6 },
206 .m = { .min = 70, .max = 120 },
207 .m1 = { .min = 8, .max = 18 },
208 .m2 = { .min = 3, .max = 7 },
209 .p = { .min = 7, .max = 98 },
210 .p1 = { .min = 1, .max = 8 },
211 .p2 = { .dot_limit = 112000,
212 .p2_slow = 14, .p2_fast = 7 },
213 };
214
215
216 static const intel_limit_t intel_limits_g4x_sdvo = {
217 .dot = { .min = 25000, .max = 270000 },
218 .vco = { .min = 1750000, .max = 3500000},
219 .n = { .min = 1, .max = 4 },
220 .m = { .min = 104, .max = 138 },
221 .m1 = { .min = 17, .max = 23 },
222 .m2 = { .min = 5, .max = 11 },
223 .p = { .min = 10, .max = 30 },
224 .p1 = { .min = 1, .max = 3},
225 .p2 = { .dot_limit = 270000,
226 .p2_slow = 10,
227 .p2_fast = 10
228 },
229 };
230
231 static const intel_limit_t intel_limits_g4x_hdmi = {
232 .dot = { .min = 22000, .max = 400000 },
233 .vco = { .min = 1750000, .max = 3500000},
234 .n = { .min = 1, .max = 4 },
235 .m = { .min = 104, .max = 138 },
236 .m1 = { .min = 16, .max = 23 },
237 .m2 = { .min = 5, .max = 11 },
238 .p = { .min = 5, .max = 80 },
239 .p1 = { .min = 1, .max = 8},
240 .p2 = { .dot_limit = 165000,
241 .p2_slow = 10, .p2_fast = 5 },
242 };
243
244 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
245 .dot = { .min = 20000, .max = 115000 },
246 .vco = { .min = 1750000, .max = 3500000 },
247 .n = { .min = 1, .max = 3 },
248 .m = { .min = 104, .max = 138 },
249 .m1 = { .min = 17, .max = 23 },
250 .m2 = { .min = 5, .max = 11 },
251 .p = { .min = 28, .max = 112 },
252 .p1 = { .min = 2, .max = 8 },
253 .p2 = { .dot_limit = 0,
254 .p2_slow = 14, .p2_fast = 14
255 },
256 };
257
258 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
259 .dot = { .min = 80000, .max = 224000 },
260 .vco = { .min = 1750000, .max = 3500000 },
261 .n = { .min = 1, .max = 3 },
262 .m = { .min = 104, .max = 138 },
263 .m1 = { .min = 17, .max = 23 },
264 .m2 = { .min = 5, .max = 11 },
265 .p = { .min = 14, .max = 42 },
266 .p1 = { .min = 2, .max = 6 },
267 .p2 = { .dot_limit = 0,
268 .p2_slow = 7, .p2_fast = 7
269 },
270 };
271
272 static const intel_limit_t intel_limits_pineview_sdvo = {
273 .dot = { .min = 20000, .max = 400000},
274 .vco = { .min = 1700000, .max = 3500000 },
275 /* Pineview's Ncounter is a ring counter */
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 /* Pineview only has one combined m divider, which we treat as m2. */
279 .m1 = { .min = 0, .max = 0 },
280 .m2 = { .min = 0, .max = 254 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 };
299
300 /* Ironlake / Sandybridge
301 *
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
304 */
305 static const intel_limit_t intel_limits_ironlake_dac = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 5 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 10, .p2_fast = 5 },
316 };
317
318 static const intel_limit_t intel_limits_ironlake_single_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 118 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 127 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 56 },
339 .p1 = { .min = 2, .max = 8 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 };
343
344 /* LVDS 100mhz refclk limits. */
345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000 },
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 79, .max = 126 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 28, .max = 112 },
353 .p1 = { .min = 2, .max = 8 },
354 .p2 = { .dot_limit = 225000,
355 .p2_slow = 14, .p2_fast = 14 },
356 };
357
358 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 3 },
362 .m = { .min = 79, .max = 126 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 14, .max = 42 },
366 .p1 = { .min = 2, .max = 6 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 7, .p2_fast = 7 },
369 };
370
371 static const intel_limit_t intel_limits_vlv = {
372 /*
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
377 */
378 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m1 = { .min = 2, .max = 3 },
382 .m2 = { .min = 11, .max = 156 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 };
386
387 static const intel_limit_t intel_limits_chv = {
388 /*
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
393 */
394 .dot = { .min = 25000 * 5, .max = 540000 * 5},
395 .vco = { .min = 4800000, .max = 6480000 },
396 .n = { .min = 1, .max = 1 },
397 .m1 = { .min = 2, .max = 2 },
398 .m2 = { .min = 24 << 22, .max = 175 << 22 },
399 .p1 = { .min = 2, .max = 4 },
400 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 };
402
403 static void vlv_clock(int refclk, intel_clock_t *clock)
404 {
405 clock->m = clock->m1 * clock->m2;
406 clock->p = clock->p1 * clock->p2;
407 if (WARN_ON(clock->n == 0 || clock->p == 0))
408 return;
409 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
410 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
411 }
412
413 /**
414 * Returns whether any output on the specified pipe is of the specified type
415 */
416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
417 {
418 struct drm_device *dev = crtc->base.dev;
419 struct intel_encoder *encoder;
420
421 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
422 if (encoder->type == type)
423 return true;
424
425 return false;
426 }
427
428 /**
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 * encoder->crtc.
433 */
434 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
435 int type)
436 {
437 struct drm_atomic_state *state = crtc_state->base.state;
438 struct drm_connector_state *connector_state;
439 struct intel_encoder *encoder;
440 int i, num_connectors = 0;
441
442 for (i = 0; i < state->num_connector; i++) {
443 if (!state->connectors[i])
444 continue;
445
446 connector_state = state->connector_states[i];
447 if (connector_state->crtc != crtc_state->base.crtc)
448 continue;
449
450 num_connectors++;
451
452 encoder = to_intel_encoder(connector_state->best_encoder);
453 if (encoder->type == type)
454 return true;
455 }
456
457 WARN_ON(num_connectors == 0);
458
459 return false;
460 }
461
462 static const intel_limit_t *
463 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
464 {
465 struct drm_device *dev = crtc_state->base.crtc->dev;
466 const intel_limit_t *limit;
467
468 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
469 if (intel_is_dual_link_lvds(dev)) {
470 if (refclk == 100000)
471 limit = &intel_limits_ironlake_dual_lvds_100m;
472 else
473 limit = &intel_limits_ironlake_dual_lvds;
474 } else {
475 if (refclk == 100000)
476 limit = &intel_limits_ironlake_single_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_single_lvds;
479 }
480 } else
481 limit = &intel_limits_ironlake_dac;
482
483 return limit;
484 }
485
486 static const intel_limit_t *
487 intel_g4x_limit(struct intel_crtc_state *crtc_state)
488 {
489 struct drm_device *dev = crtc_state->base.crtc->dev;
490 const intel_limit_t *limit;
491
492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
493 if (intel_is_dual_link_lvds(dev))
494 limit = &intel_limits_g4x_dual_channel_lvds;
495 else
496 limit = &intel_limits_g4x_single_channel_lvds;
497 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
498 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
499 limit = &intel_limits_g4x_hdmi;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
501 limit = &intel_limits_g4x_sdvo;
502 } else /* The option is for other outputs */
503 limit = &intel_limits_i9xx_sdvo;
504
505 return limit;
506 }
507
508 static const intel_limit_t *
509 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
510 {
511 struct drm_device *dev = crtc_state->base.crtc->dev;
512 const intel_limit_t *limit;
513
514 if (HAS_PCH_SPLIT(dev))
515 limit = intel_ironlake_limit(crtc_state, refclk);
516 else if (IS_G4X(dev)) {
517 limit = intel_g4x_limit(crtc_state);
518 } else if (IS_PINEVIEW(dev)) {
519 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
520 limit = &intel_limits_pineview_lvds;
521 else
522 limit = &intel_limits_pineview_sdvo;
523 } else if (IS_CHERRYVIEW(dev)) {
524 limit = &intel_limits_chv;
525 } else if (IS_VALLEYVIEW(dev)) {
526 limit = &intel_limits_vlv;
527 } else if (!IS_GEN2(dev)) {
528 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
529 limit = &intel_limits_i9xx_lvds;
530 else
531 limit = &intel_limits_i9xx_sdvo;
532 } else {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i8xx_lvds;
535 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
536 limit = &intel_limits_i8xx_dvo;
537 else
538 limit = &intel_limits_i8xx_dac;
539 }
540 return limit;
541 }
542
543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
544 static void pineview_clock(int refclk, intel_clock_t *clock)
545 {
546 clock->m = clock->m2 + 2;
547 clock->p = clock->p1 * clock->p2;
548 if (WARN_ON(clock->n == 0 || clock->p == 0))
549 return;
550 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
551 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
552 }
553
554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555 {
556 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557 }
558
559 static void i9xx_clock(int refclk, intel_clock_t *clock)
560 {
561 clock->m = i9xx_dpll_compute_m(clock);
562 clock->p = clock->p1 * clock->p2;
563 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564 return;
565 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
567 }
568
569 static void chv_clock(int refclk, intel_clock_t *clock)
570 {
571 clock->m = clock->m1 * clock->m2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
576 clock->n << 22);
577 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578 }
579
580 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
581 /**
582 * Returns whether the given set of divisors are valid for a given refclk with
583 * the given connectors.
584 */
585
586 static bool intel_PLL_is_valid(struct drm_device *dev,
587 const intel_limit_t *limit,
588 const intel_clock_t *clock)
589 {
590 if (clock->n < limit->n.min || limit->n.max < clock->n)
591 INTELPllInvalid("n out of range\n");
592 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
593 INTELPllInvalid("p1 out of range\n");
594 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
595 INTELPllInvalid("m2 out of range\n");
596 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
597 INTELPllInvalid("m1 out of range\n");
598
599 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
600 if (clock->m1 <= clock->m2)
601 INTELPllInvalid("m1 <= m2\n");
602
603 if (!IS_VALLEYVIEW(dev)) {
604 if (clock->p < limit->p.min || limit->p.max < clock->p)
605 INTELPllInvalid("p out of range\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 }
609
610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
611 INTELPllInvalid("vco out of range\n");
612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
616 INTELPllInvalid("dot out of range\n");
617
618 return true;
619 }
620
621 static bool
622 i9xx_find_best_dpll(const intel_limit_t *limit,
623 struct intel_crtc_state *crtc_state,
624 int target, int refclk, intel_clock_t *match_clock,
625 intel_clock_t *best_clock)
626 {
627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
628 struct drm_device *dev = crtc->base.dev;
629 intel_clock_t clock;
630 int err = target;
631
632 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
633 /*
634 * For LVDS just rely on its current settings for dual-channel.
635 * We haven't figured out how to reliably set up different
636 * single/dual channel state, if we even can.
637 */
638 if (intel_is_dual_link_lvds(dev))
639 clock.p2 = limit->p2.p2_fast;
640 else
641 clock.p2 = limit->p2.p2_slow;
642 } else {
643 if (target < limit->p2.dot_limit)
644 clock.p2 = limit->p2.p2_slow;
645 else
646 clock.p2 = limit->p2.p2_fast;
647 }
648
649 memset(best_clock, 0, sizeof(*best_clock));
650
651 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
652 clock.m1++) {
653 for (clock.m2 = limit->m2.min;
654 clock.m2 <= limit->m2.max; clock.m2++) {
655 if (clock.m2 >= clock.m1)
656 break;
657 for (clock.n = limit->n.min;
658 clock.n <= limit->n.max; clock.n++) {
659 for (clock.p1 = limit->p1.min;
660 clock.p1 <= limit->p1.max; clock.p1++) {
661 int this_err;
662
663 i9xx_clock(refclk, &clock);
664 if (!intel_PLL_is_valid(dev, limit,
665 &clock))
666 continue;
667 if (match_clock &&
668 clock.p != match_clock->p)
669 continue;
670
671 this_err = abs(clock.dot - target);
672 if (this_err < err) {
673 *best_clock = clock;
674 err = this_err;
675 }
676 }
677 }
678 }
679 }
680
681 return (err != target);
682 }
683
684 static bool
685 pnv_find_best_dpll(const intel_limit_t *limit,
686 struct intel_crtc_state *crtc_state,
687 int target, int refclk, intel_clock_t *match_clock,
688 intel_clock_t *best_clock)
689 {
690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
691 struct drm_device *dev = crtc->base.dev;
692 intel_clock_t clock;
693 int err = target;
694
695 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
696 /*
697 * For LVDS just rely on its current settings for dual-channel.
698 * We haven't figured out how to reliably set up different
699 * single/dual channel state, if we even can.
700 */
701 if (intel_is_dual_link_lvds(dev))
702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
712 memset(best_clock, 0, sizeof(*best_clock));
713
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 for (clock.n = limit->n.min;
719 clock.n <= limit->n.max; clock.n++) {
720 for (clock.p1 = limit->p1.min;
721 clock.p1 <= limit->p1.max; clock.p1++) {
722 int this_err;
723
724 pineview_clock(refclk, &clock);
725 if (!intel_PLL_is_valid(dev, limit,
726 &clock))
727 continue;
728 if (match_clock &&
729 clock.p != match_clock->p)
730 continue;
731
732 this_err = abs(clock.dot - target);
733 if (this_err < err) {
734 *best_clock = clock;
735 err = this_err;
736 }
737 }
738 }
739 }
740 }
741
742 return (err != target);
743 }
744
745 static bool
746 g4x_find_best_dpll(const intel_limit_t *limit,
747 struct intel_crtc_state *crtc_state,
748 int target, int refclk, intel_clock_t *match_clock,
749 intel_clock_t *best_clock)
750 {
751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
752 struct drm_device *dev = crtc->base.dev;
753 intel_clock_t clock;
754 int max_n;
755 bool found;
756 /* approximately equals target * 0.00585 */
757 int err_most = (target >> 8) + (target >> 9);
758 found = false;
759
760 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
761 if (intel_is_dual_link_lvds(dev))
762 clock.p2 = limit->p2.p2_fast;
763 else
764 clock.p2 = limit->p2.p2_slow;
765 } else {
766 if (target < limit->p2.dot_limit)
767 clock.p2 = limit->p2.p2_slow;
768 else
769 clock.p2 = limit->p2.p2_fast;
770 }
771
772 memset(best_clock, 0, sizeof(*best_clock));
773 max_n = limit->n.max;
774 /* based on hardware requirement, prefer smaller n to precision */
775 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
776 /* based on hardware requirement, prefere larger m1,m2 */
777 for (clock.m1 = limit->m1.max;
778 clock.m1 >= limit->m1.min; clock.m1--) {
779 for (clock.m2 = limit->m2.max;
780 clock.m2 >= limit->m2.min; clock.m2--) {
781 for (clock.p1 = limit->p1.max;
782 clock.p1 >= limit->p1.min; clock.p1--) {
783 int this_err;
784
785 i9xx_clock(refclk, &clock);
786 if (!intel_PLL_is_valid(dev, limit,
787 &clock))
788 continue;
789
790 this_err = abs(clock.dot - target);
791 if (this_err < err_most) {
792 *best_clock = clock;
793 err_most = this_err;
794 max_n = clock.n;
795 found = true;
796 }
797 }
798 }
799 }
800 }
801 return found;
802 }
803
804 /*
805 * Check if the calculated PLL configuration is more optimal compared to the
806 * best configuration and error found so far. Return the calculated error.
807 */
808 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
809 const intel_clock_t *calculated_clock,
810 const intel_clock_t *best_clock,
811 unsigned int best_error_ppm,
812 unsigned int *error_ppm)
813 {
814 /*
815 * For CHV ignore the error and consider only the P value.
816 * Prefer a bigger P value based on HW requirements.
817 */
818 if (IS_CHERRYVIEW(dev)) {
819 *error_ppm = 0;
820
821 return calculated_clock->p > best_clock->p;
822 }
823
824 if (WARN_ON_ONCE(!target_freq))
825 return false;
826
827 *error_ppm = div_u64(1000000ULL *
828 abs(target_freq - calculated_clock->dot),
829 target_freq);
830 /*
831 * Prefer a better P value over a better (smaller) error if the error
832 * is small. Ensure this preference for future configurations too by
833 * setting the error to 0.
834 */
835 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
836 *error_ppm = 0;
837
838 return true;
839 }
840
841 return *error_ppm + 10 < best_error_ppm;
842 }
843
844 static bool
845 vlv_find_best_dpll(const intel_limit_t *limit,
846 struct intel_crtc_state *crtc_state,
847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
849 {
850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
851 struct drm_device *dev = crtc->base.dev;
852 intel_clock_t clock;
853 unsigned int bestppm = 1000000;
854 /* min update 19.2 MHz */
855 int max_n = min(limit->n.max, refclk / 19200);
856 bool found = false;
857
858 target *= 5; /* fast clock */
859
860 memset(best_clock, 0, sizeof(*best_clock));
861
862 /* based on hardware requirement, prefer smaller n to precision */
863 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
864 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
865 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
866 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
867 clock.p = clock.p1 * clock.p2;
868 /* based on hardware requirement, prefer bigger m1,m2 values */
869 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
870 unsigned int ppm;
871
872 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
873 refclk * clock.m1);
874
875 vlv_clock(refclk, &clock);
876
877 if (!intel_PLL_is_valid(dev, limit,
878 &clock))
879 continue;
880
881 if (!vlv_PLL_is_optimal(dev, target,
882 &clock,
883 best_clock,
884 bestppm, &ppm))
885 continue;
886
887 *best_clock = clock;
888 bestppm = ppm;
889 found = true;
890 }
891 }
892 }
893 }
894
895 return found;
896 }
897
898 static bool
899 chv_find_best_dpll(const intel_limit_t *limit,
900 struct intel_crtc_state *crtc_state,
901 int target, int refclk, intel_clock_t *match_clock,
902 intel_clock_t *best_clock)
903 {
904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
905 struct drm_device *dev = crtc->base.dev;
906 unsigned int best_error_ppm;
907 intel_clock_t clock;
908 uint64_t m2;
909 int found = false;
910
911 memset(best_clock, 0, sizeof(*best_clock));
912 best_error_ppm = 1000000;
913
914 /*
915 * Based on hardware doc, the n always set to 1, and m1 always
916 * set to 2. If requires to support 200Mhz refclk, we need to
917 * revisit this because n may not 1 anymore.
918 */
919 clock.n = 1, clock.m1 = 2;
920 target *= 5; /* fast clock */
921
922 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
923 for (clock.p2 = limit->p2.p2_fast;
924 clock.p2 >= limit->p2.p2_slow;
925 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
926 unsigned int error_ppm;
927
928 clock.p = clock.p1 * clock.p2;
929
930 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
931 clock.n) << 22, refclk * clock.m1);
932
933 if (m2 > INT_MAX/clock.m1)
934 continue;
935
936 clock.m2 = m2;
937
938 chv_clock(refclk, &clock);
939
940 if (!intel_PLL_is_valid(dev, limit, &clock))
941 continue;
942
943 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
944 best_error_ppm, &error_ppm))
945 continue;
946
947 *best_clock = clock;
948 best_error_ppm = error_ppm;
949 found = true;
950 }
951 }
952
953 return found;
954 }
955
956 bool intel_crtc_active(struct drm_crtc *crtc)
957 {
958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
959
960 /* Be paranoid as we can arrive here with only partial
961 * state retrieved from the hardware during setup.
962 *
963 * We can ditch the adjusted_mode.crtc_clock check as soon
964 * as Haswell has gained clock readout/fastboot support.
965 *
966 * We can ditch the crtc->primary->fb check as soon as we can
967 * properly reconstruct framebuffers.
968 *
969 * FIXME: The intel_crtc->active here should be switched to
970 * crtc->state->active once we have proper CRTC states wired up
971 * for atomic.
972 */
973 return intel_crtc->active && crtc->primary->state->fb &&
974 intel_crtc->config->base.adjusted_mode.crtc_clock;
975 }
976
977 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979 {
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982
983 return intel_crtc->config->cpu_transcoder;
984 }
985
986 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
987 {
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 reg = PIPEDSL(pipe);
990 u32 line1, line2;
991 u32 line_mask;
992
993 if (IS_GEN2(dev))
994 line_mask = DSL_LINEMASK_GEN2;
995 else
996 line_mask = DSL_LINEMASK_GEN3;
997
998 line1 = I915_READ(reg) & line_mask;
999 mdelay(5);
1000 line2 = I915_READ(reg) & line_mask;
1001
1002 return line1 == line2;
1003 }
1004
1005 /*
1006 * intel_wait_for_pipe_off - wait for pipe to turn off
1007 * @crtc: crtc whose pipe to wait for
1008 *
1009 * After disabling a pipe, we can't wait for vblank in the usual way,
1010 * spinning on the vblank interrupt status bit, since we won't actually
1011 * see an interrupt when the pipe is disabled.
1012 *
1013 * On Gen4 and above:
1014 * wait for the pipe register state bit to turn off
1015 *
1016 * Otherwise:
1017 * wait for the display line value to settle (it usually
1018 * ends up stopping at the start of the next frame).
1019 *
1020 */
1021 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1022 {
1023 struct drm_device *dev = crtc->base.dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1026 enum pipe pipe = crtc->pipe;
1027
1028 if (INTEL_INFO(dev)->gen >= 4) {
1029 int reg = PIPECONF(cpu_transcoder);
1030
1031 /* Wait for the Pipe State to go off */
1032 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1033 100))
1034 WARN(1, "pipe_off wait timed out\n");
1035 } else {
1036 /* Wait for the display line to settle */
1037 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1038 WARN(1, "pipe_off wait timed out\n");
1039 }
1040 }
1041
1042 /*
1043 * ibx_digital_port_connected - is the specified port connected?
1044 * @dev_priv: i915 private structure
1045 * @port: the port to test
1046 *
1047 * Returns true if @port is connected, false otherwise.
1048 */
1049 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1050 struct intel_digital_port *port)
1051 {
1052 u32 bit;
1053
1054 if (HAS_PCH_IBX(dev_priv->dev)) {
1055 switch (port->port) {
1056 case PORT_B:
1057 bit = SDE_PORTB_HOTPLUG;
1058 break;
1059 case PORT_C:
1060 bit = SDE_PORTC_HOTPLUG;
1061 break;
1062 case PORT_D:
1063 bit = SDE_PORTD_HOTPLUG;
1064 break;
1065 default:
1066 return true;
1067 }
1068 } else {
1069 switch (port->port) {
1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG_CPT;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG_CPT;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG_CPT;
1078 break;
1079 default:
1080 return true;
1081 }
1082 }
1083
1084 return I915_READ(SDEISR) & bit;
1085 }
1086
1087 static const char *state_string(bool enabled)
1088 {
1089 return enabled ? "on" : "off";
1090 }
1091
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private *dev_priv,
1094 enum pipe pipe, bool state)
1095 {
1096 int reg;
1097 u32 val;
1098 bool cur_state;
1099
1100 reg = DPLL(pipe);
1101 val = I915_READ(reg);
1102 cur_state = !!(val & DPLL_VCO_ENABLE);
1103 I915_STATE_WARN(cur_state != state,
1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 state_string(state), state_string(cur_state));
1106 }
1107
1108 /* XXX: the dsi pll is shared between MIPI DSI ports */
1109 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1110 {
1111 u32 val;
1112 bool cur_state;
1113
1114 mutex_lock(&dev_priv->dpio_lock);
1115 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1116 mutex_unlock(&dev_priv->dpio_lock);
1117
1118 cur_state = val & DSI_PLL_VCO_EN;
1119 I915_STATE_WARN(cur_state != state,
1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 state_string(state), state_string(cur_state));
1122 }
1123 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1125
1126 struct intel_shared_dpll *
1127 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1128 {
1129 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1130
1131 if (crtc->config->shared_dpll < 0)
1132 return NULL;
1133
1134 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1135 }
1136
1137 /* For ILK+ */
1138 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1139 struct intel_shared_dpll *pll,
1140 bool state)
1141 {
1142 bool cur_state;
1143 struct intel_dpll_hw_state hw_state;
1144
1145 if (WARN (!pll,
1146 "asserting DPLL %s with no DPLL\n", state_string(state)))
1147 return;
1148
1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1150 I915_STATE_WARN(cur_state != state,
1151 "%s assertion failure (expected %s, current %s)\n",
1152 pll->name, state_string(state), state_string(cur_state));
1153 }
1154
1155 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1156 enum pipe pipe, bool state)
1157 {
1158 int reg;
1159 u32 val;
1160 bool cur_state;
1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1162 pipe);
1163
1164 if (HAS_DDI(dev_priv->dev)) {
1165 /* DDI does not have a specific FDI_TX register */
1166 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1167 val = I915_READ(reg);
1168 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1169 } else {
1170 reg = FDI_TX_CTL(pipe);
1171 val = I915_READ(reg);
1172 cur_state = !!(val & FDI_TX_ENABLE);
1173 }
1174 I915_STATE_WARN(cur_state != state,
1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 state_string(state), state_string(cur_state));
1177 }
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180
1181 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1183 {
1184 int reg;
1185 u32 val;
1186 bool cur_state;
1187
1188 reg = FDI_RX_CTL(pipe);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & FDI_RX_ENABLE);
1191 I915_STATE_WARN(cur_state != state,
1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1194 }
1195 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe)
1200 {
1201 int reg;
1202 u32 val;
1203
1204 /* ILK FDI PLL is always enabled */
1205 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1206 return;
1207
1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209 if (HAS_DDI(dev_priv->dev))
1210 return;
1211
1212 reg = FDI_TX_CTL(pipe);
1213 val = I915_READ(reg);
1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 int reg;
1221 u32 val;
1222 bool cur_state;
1223
1224 reg = FDI_RX_CTL(pipe);
1225 val = I915_READ(reg);
1226 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1227 I915_STATE_WARN(cur_state != state,
1228 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229 state_string(state), state_string(cur_state));
1230 }
1231
1232 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 struct drm_device *dev = dev_priv->dev;
1236 int pp_reg;
1237 u32 val;
1238 enum pipe panel_pipe = PIPE_A;
1239 bool locked = true;
1240
1241 if (WARN_ON(HAS_DDI(dev)))
1242 return;
1243
1244 if (HAS_PCH_SPLIT(dev)) {
1245 u32 port_sel;
1246
1247 pp_reg = PCH_PP_CONTROL;
1248 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1249
1250 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1251 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1252 panel_pipe = PIPE_B;
1253 /* XXX: else fix for eDP */
1254 } else if (IS_VALLEYVIEW(dev)) {
1255 /* presumably write lock depends on pipe, not port select */
1256 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1257 panel_pipe = pipe;
1258 } else {
1259 pp_reg = PP_CONTROL;
1260 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1261 panel_pipe = PIPE_B;
1262 }
1263
1264 val = I915_READ(pp_reg);
1265 if (!(val & PANEL_POWER_ON) ||
1266 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1267 locked = false;
1268
1269 I915_STATE_WARN(panel_pipe == pipe && locked,
1270 "panel assertion failure, pipe %c regs locked\n",
1271 pipe_name(pipe));
1272 }
1273
1274 static void assert_cursor(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, bool state)
1276 {
1277 struct drm_device *dev = dev_priv->dev;
1278 bool cur_state;
1279
1280 if (IS_845G(dev) || IS_I865G(dev))
1281 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1282 else
1283 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1284
1285 I915_STATE_WARN(cur_state != state,
1286 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287 pipe_name(pipe), state_string(state), state_string(cur_state));
1288 }
1289 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291
1292 void assert_pipe(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, bool state)
1294 {
1295 int reg;
1296 u32 val;
1297 bool cur_state;
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
1300
1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1304 state = true;
1305
1306 if (!intel_display_power_is_enabled(dev_priv,
1307 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1308 cur_state = false;
1309 } else {
1310 reg = PIPECONF(cpu_transcoder);
1311 val = I915_READ(reg);
1312 cur_state = !!(val & PIPECONF_ENABLE);
1313 }
1314
1315 I915_STATE_WARN(cur_state != state,
1316 "pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319
1320 static void assert_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, bool state)
1322 {
1323 int reg;
1324 u32 val;
1325 bool cur_state;
1326
1327 reg = DSPCNTR(plane);
1328 val = I915_READ(reg);
1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1330 I915_STATE_WARN(cur_state != state,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), state_string(state), state_string(cur_state));
1333 }
1334
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340 {
1341 struct drm_device *dev = dev_priv->dev;
1342 int reg, i;
1343 u32 val;
1344 int cur_pipe;
1345
1346 /* Primary planes are fixed to pipes on gen4+ */
1347 if (INTEL_INFO(dev)->gen >= 4) {
1348 reg = DSPCNTR(pipe);
1349 val = I915_READ(reg);
1350 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1351 "plane %c assertion failure, should be disabled but not\n",
1352 plane_name(pipe));
1353 return;
1354 }
1355
1356 /* Need to check both planes against the pipe */
1357 for_each_pipe(dev_priv, i) {
1358 reg = DSPCNTR(i);
1359 val = I915_READ(reg);
1360 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1361 DISPPLANE_SEL_PIPE_SHIFT;
1362 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1363 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(i), pipe_name(pipe));
1365 }
1366 }
1367
1368 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370 {
1371 struct drm_device *dev = dev_priv->dev;
1372 int reg, sprite;
1373 u32 val;
1374
1375 if (INTEL_INFO(dev)->gen >= 9) {
1376 for_each_sprite(dev_priv, pipe, sprite) {
1377 val = I915_READ(PLANE_CTL(pipe, sprite));
1378 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1379 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380 sprite, pipe_name(pipe));
1381 }
1382 } else if (IS_VALLEYVIEW(dev)) {
1383 for_each_sprite(dev_priv, pipe, sprite) {
1384 reg = SPCNTR(pipe, sprite);
1385 val = I915_READ(reg);
1386 I915_STATE_WARN(val & SP_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 sprite_name(pipe, sprite), pipe_name(pipe));
1389 }
1390 } else if (INTEL_INFO(dev)->gen >= 7) {
1391 reg = SPRCTL(pipe);
1392 val = I915_READ(reg);
1393 I915_STATE_WARN(val & SPRITE_ENABLE,
1394 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1395 plane_name(pipe), pipe_name(pipe));
1396 } else if (INTEL_INFO(dev)->gen >= 5) {
1397 reg = DVSCNTR(pipe);
1398 val = I915_READ(reg);
1399 I915_STATE_WARN(val & DVS_ENABLE,
1400 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1401 plane_name(pipe), pipe_name(pipe));
1402 }
1403 }
1404
1405 static void assert_vblank_disabled(struct drm_crtc *crtc)
1406 {
1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1408 drm_crtc_vblank_put(crtc);
1409 }
1410
1411 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1412 {
1413 u32 val;
1414 bool enabled;
1415
1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1417
1418 val = I915_READ(PCH_DREF_CONTROL);
1419 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1420 DREF_SUPERSPREAD_SOURCE_MASK));
1421 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1422 }
1423
1424 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1425 enum pipe pipe)
1426 {
1427 int reg;
1428 u32 val;
1429 bool enabled;
1430
1431 reg = PCH_TRANSCONF(pipe);
1432 val = I915_READ(reg);
1433 enabled = !!(val & TRANS_ENABLE);
1434 I915_STATE_WARN(enabled,
1435 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1436 pipe_name(pipe));
1437 }
1438
1439 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1440 enum pipe pipe, u32 port_sel, u32 val)
1441 {
1442 if ((val & DP_PORT_EN) == 0)
1443 return false;
1444
1445 if (HAS_PCH_CPT(dev_priv->dev)) {
1446 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1447 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1448 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1449 return false;
1450 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1451 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1452 return false;
1453 } else {
1454 if ((val & DP_PIPE_MASK) != (pipe << 30))
1455 return false;
1456 }
1457 return true;
1458 }
1459
1460 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, u32 val)
1462 {
1463 if ((val & SDVO_ENABLE) == 0)
1464 return false;
1465
1466 if (HAS_PCH_CPT(dev_priv->dev)) {
1467 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1468 return false;
1469 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1470 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1471 return false;
1472 } else {
1473 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1474 return false;
1475 }
1476 return true;
1477 }
1478
1479 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, u32 val)
1481 {
1482 if ((val & LVDS_PORT_EN) == 0)
1483 return false;
1484
1485 if (HAS_PCH_CPT(dev_priv->dev)) {
1486 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1487 return false;
1488 } else {
1489 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1490 return false;
1491 }
1492 return true;
1493 }
1494
1495 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497 {
1498 if ((val & ADPA_DAC_ENABLE) == 0)
1499 return false;
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1502 return false;
1503 } else {
1504 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1505 return false;
1506 }
1507 return true;
1508 }
1509
1510 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1511 enum pipe pipe, int reg, u32 port_sel)
1512 {
1513 u32 val = I915_READ(reg);
1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1516 reg, pipe_name(pipe));
1517
1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1519 && (val & DP_PIPEB_SELECT),
1520 "IBX PCH dp port still using transcoder B\n");
1521 }
1522
1523 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1524 enum pipe pipe, int reg)
1525 {
1526 u32 val = I915_READ(reg);
1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1529 reg, pipe_name(pipe));
1530
1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1532 && (val & SDVO_PIPE_B_SELECT),
1533 "IBX PCH hdmi port still using transcoder B\n");
1534 }
1535
1536 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
1538 {
1539 int reg;
1540 u32 val;
1541
1542 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1543 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1545
1546 reg = PCH_ADPA;
1547 val = I915_READ(reg);
1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1549 "PCH VGA enabled on transcoder %c, should be disabled\n",
1550 pipe_name(pipe));
1551
1552 reg = PCH_LVDS;
1553 val = I915_READ(reg);
1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1555 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1556 pipe_name(pipe));
1557
1558 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1559 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1561 }
1562
1563 static void intel_init_dpio(struct drm_device *dev)
1564 {
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566
1567 if (!IS_VALLEYVIEW(dev))
1568 return;
1569
1570 /*
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572 * CHV x1 PHY (DP/HDMI D)
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1574 */
1575 if (IS_CHERRYVIEW(dev)) {
1576 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1577 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1578 } else {
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1580 }
1581 }
1582
1583 static void vlv_enable_pll(struct intel_crtc *crtc,
1584 const struct intel_crtc_state *pipe_config)
1585 {
1586 struct drm_device *dev = crtc->base.dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 int reg = DPLL(crtc->pipe);
1589 u32 dpll = pipe_config->dpll_hw_state.dpll;
1590
1591 assert_pipe_disabled(dev_priv, crtc->pipe);
1592
1593 /* No really, not for ILK+ */
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1595
1596 /* PLL is protected by panel, make sure we can write it */
1597 if (IS_MOBILE(dev_priv->dev))
1598 assert_panel_unlocked(dev_priv, crtc->pipe);
1599
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150);
1603
1604 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1606
1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1608 POSTING_READ(DPLL_MD(crtc->pipe));
1609
1610 /* We do this three times for luck */
1611 I915_WRITE(reg, dpll);
1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150); /* wait for warmup */
1617 I915_WRITE(reg, dpll);
1618 POSTING_READ(reg);
1619 udelay(150); /* wait for warmup */
1620 }
1621
1622 static void chv_enable_pll(struct intel_crtc *crtc,
1623 const struct intel_crtc_state *pipe_config)
1624 {
1625 struct drm_device *dev = crtc->base.dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 int pipe = crtc->pipe;
1628 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1629 u32 tmp;
1630
1631 assert_pipe_disabled(dev_priv, crtc->pipe);
1632
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1634
1635 mutex_lock(&dev_priv->dpio_lock);
1636
1637 /* Enable back the 10bit clock to display controller */
1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1639 tmp |= DPIO_DCLKP_EN;
1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1641
1642 /*
1643 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1644 */
1645 udelay(1);
1646
1647 /* Enable PLL */
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1649
1650 /* Check PLL is locked */
1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1652 DRM_ERROR("PLL %d failed to lock\n", pipe);
1653
1654 /* not sure when this should be written */
1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1656 POSTING_READ(DPLL_MD(pipe));
1657
1658 mutex_unlock(&dev_priv->dpio_lock);
1659 }
1660
1661 static int intel_num_dvo_pipes(struct drm_device *dev)
1662 {
1663 struct intel_crtc *crtc;
1664 int count = 0;
1665
1666 for_each_intel_crtc(dev, crtc)
1667 count += crtc->active &&
1668 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1669
1670 return count;
1671 }
1672
1673 static void i9xx_enable_pll(struct intel_crtc *crtc)
1674 {
1675 struct drm_device *dev = crtc->base.dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 int reg = DPLL(crtc->pipe);
1678 u32 dpll = crtc->config->dpll_hw_state.dpll;
1679
1680 assert_pipe_disabled(dev_priv, crtc->pipe);
1681
1682 /* No really, not for ILK+ */
1683 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1684
1685 /* PLL is protected by panel, make sure we can write it */
1686 if (IS_MOBILE(dev) && !IS_I830(dev))
1687 assert_panel_unlocked(dev_priv, crtc->pipe);
1688
1689 /* Enable DVO 2x clock on both PLLs if necessary */
1690 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1691 /*
1692 * It appears to be important that we don't enable this
1693 * for the current pipe before otherwise configuring the
1694 * PLL. No idea how this should be handled if multiple
1695 * DVO outputs are enabled simultaneosly.
1696 */
1697 dpll |= DPLL_DVO_2X_MODE;
1698 I915_WRITE(DPLL(!crtc->pipe),
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1700 }
1701
1702 /* Wait for the clocks to stabilize. */
1703 POSTING_READ(reg);
1704 udelay(150);
1705
1706 if (INTEL_INFO(dev)->gen >= 4) {
1707 I915_WRITE(DPLL_MD(crtc->pipe),
1708 crtc->config->dpll_hw_state.dpll_md);
1709 } else {
1710 /* The pixel multiplier can only be updated once the
1711 * DPLL is enabled and the clocks are stable.
1712 *
1713 * So write it again.
1714 */
1715 I915_WRITE(reg, dpll);
1716 }
1717
1718 /* We do this three times for luck */
1719 I915_WRITE(reg, dpll);
1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
1722 I915_WRITE(reg, dpll);
1723 POSTING_READ(reg);
1724 udelay(150); /* wait for warmup */
1725 I915_WRITE(reg, dpll);
1726 POSTING_READ(reg);
1727 udelay(150); /* wait for warmup */
1728 }
1729
1730 /**
1731 * i9xx_disable_pll - disable a PLL
1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe PLL to disable
1734 *
1735 * Disable the PLL for @pipe, making sure the pipe is off first.
1736 *
1737 * Note! This is for pre-ILK only.
1738 */
1739 static void i9xx_disable_pll(struct intel_crtc *crtc)
1740 {
1741 struct drm_device *dev = crtc->base.dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 enum pipe pipe = crtc->pipe;
1744
1745 /* Disable DVO 2x clock on both PLLs if necessary */
1746 if (IS_I830(dev) &&
1747 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1748 intel_num_dvo_pipes(dev) == 1) {
1749 I915_WRITE(DPLL(PIPE_B),
1750 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1751 I915_WRITE(DPLL(PIPE_A),
1752 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1753 }
1754
1755 /* Don't disable pipe or pipe PLLs if needed */
1756 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1757 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1758 return;
1759
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv, pipe);
1762
1763 I915_WRITE(DPLL(pipe), 0);
1764 POSTING_READ(DPLL(pipe));
1765 }
1766
1767 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1768 {
1769 u32 val = 0;
1770
1771 /* Make sure the pipe isn't still relying on us */
1772 assert_pipe_disabled(dev_priv, pipe);
1773
1774 /*
1775 * Leave integrated clock source and reference clock enabled for pipe B.
1776 * The latter is needed for VGA hotplug / manual detection.
1777 */
1778 if (pipe == PIPE_B)
1779 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1780 I915_WRITE(DPLL(pipe), val);
1781 POSTING_READ(DPLL(pipe));
1782
1783 }
1784
1785 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1786 {
1787 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1788 u32 val;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
1793 /* Set PLL en = 0 */
1794 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1795 if (pipe != PIPE_A)
1796 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1797 I915_WRITE(DPLL(pipe), val);
1798 POSTING_READ(DPLL(pipe));
1799
1800 mutex_lock(&dev_priv->dpio_lock);
1801
1802 /* Disable 10bit clock to display controller */
1803 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1804 val &= ~DPIO_DCLKP_EN;
1805 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1806
1807 /* disable left/right clock distribution */
1808 if (pipe != PIPE_B) {
1809 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1810 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1811 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1812 } else {
1813 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1814 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1815 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1816 }
1817
1818 mutex_unlock(&dev_priv->dpio_lock);
1819 }
1820
1821 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1822 struct intel_digital_port *dport)
1823 {
1824 u32 port_mask;
1825 int dpll_reg;
1826
1827 switch (dport->port) {
1828 case PORT_B:
1829 port_mask = DPLL_PORTB_READY_MASK;
1830 dpll_reg = DPLL(0);
1831 break;
1832 case PORT_C:
1833 port_mask = DPLL_PORTC_READY_MASK;
1834 dpll_reg = DPLL(0);
1835 break;
1836 case PORT_D:
1837 port_mask = DPLL_PORTD_READY_MASK;
1838 dpll_reg = DPIO_PHY_STATUS;
1839 break;
1840 default:
1841 BUG();
1842 }
1843
1844 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1845 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1846 port_name(dport->port), I915_READ(dpll_reg));
1847 }
1848
1849 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1850 {
1851 struct drm_device *dev = crtc->base.dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1854
1855 if (WARN_ON(pll == NULL))
1856 return;
1857
1858 WARN_ON(!pll->config.crtc_mask);
1859 if (pll->active == 0) {
1860 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1861 WARN_ON(pll->on);
1862 assert_shared_dpll_disabled(dev_priv, pll);
1863
1864 pll->mode_set(dev_priv, pll);
1865 }
1866 }
1867
1868 /**
1869 * intel_enable_shared_dpll - enable PCH PLL
1870 * @dev_priv: i915 private structure
1871 * @pipe: pipe PLL to enable
1872 *
1873 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874 * drives the transcoder clock.
1875 */
1876 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1877 {
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
1882 if (WARN_ON(pll == NULL))
1883 return;
1884
1885 if (WARN_ON(pll->config.crtc_mask == 0))
1886 return;
1887
1888 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1889 pll->name, pll->active, pll->on,
1890 crtc->base.base.id);
1891
1892 if (pll->active++) {
1893 WARN_ON(!pll->on);
1894 assert_shared_dpll_enabled(dev_priv, pll);
1895 return;
1896 }
1897 WARN_ON(pll->on);
1898
1899 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1900
1901 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1902 pll->enable(dev_priv, pll);
1903 pll->on = true;
1904 }
1905
1906 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1907 {
1908 struct drm_device *dev = crtc->base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1911
1912 /* PCH only available on ILK+ */
1913 BUG_ON(INTEL_INFO(dev)->gen < 5);
1914 if (WARN_ON(pll == NULL))
1915 return;
1916
1917 if (WARN_ON(pll->config.crtc_mask == 0))
1918 return;
1919
1920 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
1922 crtc->base.base.id);
1923
1924 if (WARN_ON(pll->active == 0)) {
1925 assert_shared_dpll_disabled(dev_priv, pll);
1926 return;
1927 }
1928
1929 assert_shared_dpll_enabled(dev_priv, pll);
1930 WARN_ON(!pll->on);
1931 if (--pll->active)
1932 return;
1933
1934 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1935 pll->disable(dev_priv, pll);
1936 pll->on = false;
1937
1938 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1939 }
1940
1941 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
1943 {
1944 struct drm_device *dev = dev_priv->dev;
1945 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1947 uint32_t reg, val, pipeconf_val;
1948
1949 /* PCH only available on ILK+ */
1950 BUG_ON(!HAS_PCH_SPLIT(dev));
1951
1952 /* Make sure PCH DPLL is enabled */
1953 assert_shared_dpll_enabled(dev_priv,
1954 intel_crtc_to_shared_dpll(intel_crtc));
1955
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv, pipe);
1958 assert_fdi_rx_enabled(dev_priv, pipe);
1959
1960 if (HAS_PCH_CPT(dev)) {
1961 /* Workaround: Set the timing override bit before enabling the
1962 * pch transcoder. */
1963 reg = TRANS_CHICKEN2(pipe);
1964 val = I915_READ(reg);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(reg, val);
1967 }
1968
1969 reg = PCH_TRANSCONF(pipe);
1970 val = I915_READ(reg);
1971 pipeconf_val = I915_READ(PIPECONF(pipe));
1972
1973 if (HAS_PCH_IBX(dev_priv->dev)) {
1974 /*
1975 * make the BPC in transcoder be consistent with
1976 * that in pipeconf reg.
1977 */
1978 val &= ~PIPECONF_BPC_MASK;
1979 val |= pipeconf_val & PIPECONF_BPC_MASK;
1980 }
1981
1982 val &= ~TRANS_INTERLACE_MASK;
1983 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1984 if (HAS_PCH_IBX(dev_priv->dev) &&
1985 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1986 val |= TRANS_LEGACY_INTERLACED_ILK;
1987 else
1988 val |= TRANS_INTERLACED;
1989 else
1990 val |= TRANS_PROGRESSIVE;
1991
1992 I915_WRITE(reg, val | TRANS_ENABLE);
1993 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1994 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1995 }
1996
1997 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1998 enum transcoder cpu_transcoder)
1999 {
2000 u32 val, pipeconf_val;
2001
2002 /* PCH only available on ILK+ */
2003 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2004
2005 /* FDI must be feeding us bits for PCH ports */
2006 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2007 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2008
2009 /* Workaround: set timing override bit. */
2010 val = I915_READ(_TRANSA_CHICKEN2);
2011 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2012 I915_WRITE(_TRANSA_CHICKEN2, val);
2013
2014 val = TRANS_ENABLE;
2015 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2016
2017 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2018 PIPECONF_INTERLACED_ILK)
2019 val |= TRANS_INTERLACED;
2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
2023 I915_WRITE(LPT_TRANSCONF, val);
2024 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2025 DRM_ERROR("Failed to enable PCH transcoder\n");
2026 }
2027
2028 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum pipe pipe)
2030 {
2031 struct drm_device *dev = dev_priv->dev;
2032 uint32_t reg, val;
2033
2034 /* FDI relies on the transcoder */
2035 assert_fdi_tx_disabled(dev_priv, pipe);
2036 assert_fdi_rx_disabled(dev_priv, pipe);
2037
2038 /* Ports must be off as well */
2039 assert_pch_ports_disabled(dev_priv, pipe);
2040
2041 reg = PCH_TRANSCONF(pipe);
2042 val = I915_READ(reg);
2043 val &= ~TRANS_ENABLE;
2044 I915_WRITE(reg, val);
2045 /* wait for PCH transcoder off, transcoder state */
2046 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2047 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2048
2049 if (!HAS_PCH_IBX(dev)) {
2050 /* Workaround: Clear the timing override chicken bit again. */
2051 reg = TRANS_CHICKEN2(pipe);
2052 val = I915_READ(reg);
2053 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2054 I915_WRITE(reg, val);
2055 }
2056 }
2057
2058 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2059 {
2060 u32 val;
2061
2062 val = I915_READ(LPT_TRANSCONF);
2063 val &= ~TRANS_ENABLE;
2064 I915_WRITE(LPT_TRANSCONF, val);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2067 DRM_ERROR("Failed to disable PCH transcoder\n");
2068
2069 /* Workaround: clear timing override bit. */
2070 val = I915_READ(_TRANSA_CHICKEN2);
2071 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2072 I915_WRITE(_TRANSA_CHICKEN2, val);
2073 }
2074
2075 /**
2076 * intel_enable_pipe - enable a pipe, asserting requirements
2077 * @crtc: crtc responsible for the pipe
2078 *
2079 * Enable @crtc's pipe, making sure that various hardware specific requirements
2080 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2081 */
2082 static void intel_enable_pipe(struct intel_crtc *crtc)
2083 {
2084 struct drm_device *dev = crtc->base.dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 enum pipe pipe = crtc->pipe;
2087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2088 pipe);
2089 enum pipe pch_transcoder;
2090 int reg;
2091 u32 val;
2092
2093 assert_planes_disabled(dev_priv, pipe);
2094 assert_cursor_disabled(dev_priv, pipe);
2095 assert_sprites_disabled(dev_priv, pipe);
2096
2097 if (HAS_PCH_LPT(dev_priv->dev))
2098 pch_transcoder = TRANSCODER_A;
2099 else
2100 pch_transcoder = pipe;
2101
2102 /*
2103 * A pipe without a PLL won't actually be able to drive bits from
2104 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2105 * need the check.
2106 */
2107 if (!HAS_PCH_SPLIT(dev_priv->dev))
2108 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2109 assert_dsi_pll_enabled(dev_priv);
2110 else
2111 assert_pll_enabled(dev_priv, pipe);
2112 else {
2113 if (crtc->config->has_pch_encoder) {
2114 /* if driving the PCH, we need FDI enabled */
2115 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2116 assert_fdi_tx_pll_enabled(dev_priv,
2117 (enum pipe) cpu_transcoder);
2118 }
2119 /* FIXME: assert CPU port conditions for SNB+ */
2120 }
2121
2122 reg = PIPECONF(cpu_transcoder);
2123 val = I915_READ(reg);
2124 if (val & PIPECONF_ENABLE) {
2125 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2126 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2127 return;
2128 }
2129
2130 I915_WRITE(reg, val | PIPECONF_ENABLE);
2131 POSTING_READ(reg);
2132 }
2133
2134 /**
2135 * intel_disable_pipe - disable a pipe, asserting requirements
2136 * @crtc: crtc whose pipes is to be disabled
2137 *
2138 * Disable the pipe of @crtc, making sure that various hardware
2139 * specific requirements are met, if applicable, e.g. plane
2140 * disabled, panel fitter off, etc.
2141 *
2142 * Will wait until the pipe has shut down before returning.
2143 */
2144 static void intel_disable_pipe(struct intel_crtc *crtc)
2145 {
2146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2147 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2148 enum pipe pipe = crtc->pipe;
2149 int reg;
2150 u32 val;
2151
2152 /*
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2155 */
2156 assert_planes_disabled(dev_priv, pipe);
2157 assert_cursor_disabled(dev_priv, pipe);
2158 assert_sprites_disabled(dev_priv, pipe);
2159
2160 reg = PIPECONF(cpu_transcoder);
2161 val = I915_READ(reg);
2162 if ((val & PIPECONF_ENABLE) == 0)
2163 return;
2164
2165 /*
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2168 */
2169 if (crtc->config->double_wide)
2170 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172 /* Don't disable pipe or pipe PLLs if needed */
2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2175 val &= ~PIPECONF_ENABLE;
2176
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
2180 }
2181
2182 /*
2183 * Plane regs are double buffered, going from enabled->disabled needs a
2184 * trigger in order to latch. The display address reg provides this.
2185 */
2186 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2187 enum plane plane)
2188 {
2189 struct drm_device *dev = dev_priv->dev;
2190 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2191
2192 I915_WRITE(reg, I915_READ(reg));
2193 POSTING_READ(reg);
2194 }
2195
2196 /**
2197 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2198 * @plane: plane to be enabled
2199 * @crtc: crtc for the plane
2200 *
2201 * Enable @plane on @crtc, making sure that the pipe is running first.
2202 */
2203 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2204 struct drm_crtc *crtc)
2205 {
2206 struct drm_device *dev = plane->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2211 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2212
2213 if (intel_crtc->primary_enabled)
2214 return;
2215
2216 intel_crtc->primary_enabled = true;
2217
2218 dev_priv->display.update_primary_plane(crtc, plane->fb,
2219 crtc->x, crtc->y);
2220
2221 /*
2222 * BDW signals flip done immediately if the plane
2223 * is disabled, even if the plane enable is already
2224 * armed to occur at the next vblank :(
2225 */
2226 if (IS_BROADWELL(dev))
2227 intel_wait_for_vblank(dev, intel_crtc->pipe);
2228 }
2229
2230 /**
2231 * intel_disable_primary_hw_plane - disable the primary hardware plane
2232 * @plane: plane to be disabled
2233 * @crtc: crtc for the plane
2234 *
2235 * Disable @plane on @crtc, making sure that the pipe is running first.
2236 */
2237 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2238 struct drm_crtc *crtc)
2239 {
2240 struct drm_device *dev = plane->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243
2244 if (WARN_ON(!intel_crtc->active))
2245 return;
2246
2247 if (!intel_crtc->primary_enabled)
2248 return;
2249
2250 intel_crtc->primary_enabled = false;
2251
2252 dev_priv->display.update_primary_plane(crtc, plane->fb,
2253 crtc->x, crtc->y);
2254 }
2255
2256 static bool need_vtd_wa(struct drm_device *dev)
2257 {
2258 #ifdef CONFIG_INTEL_IOMMU
2259 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2260 return true;
2261 #endif
2262 return false;
2263 }
2264
2265 unsigned int
2266 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2267 uint64_t fb_format_modifier)
2268 {
2269 unsigned int tile_height;
2270 uint32_t pixel_bytes;
2271
2272 switch (fb_format_modifier) {
2273 case DRM_FORMAT_MOD_NONE:
2274 tile_height = 1;
2275 break;
2276 case I915_FORMAT_MOD_X_TILED:
2277 tile_height = IS_GEN2(dev) ? 16 : 8;
2278 break;
2279 case I915_FORMAT_MOD_Y_TILED:
2280 tile_height = 32;
2281 break;
2282 case I915_FORMAT_MOD_Yf_TILED:
2283 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2284 switch (pixel_bytes) {
2285 default:
2286 case 1:
2287 tile_height = 64;
2288 break;
2289 case 2:
2290 case 4:
2291 tile_height = 32;
2292 break;
2293 case 8:
2294 tile_height = 16;
2295 break;
2296 case 16:
2297 WARN_ONCE(1,
2298 "128-bit pixels are not supported for display!");
2299 tile_height = 16;
2300 break;
2301 }
2302 break;
2303 default:
2304 MISSING_CASE(fb_format_modifier);
2305 tile_height = 1;
2306 break;
2307 }
2308
2309 return tile_height;
2310 }
2311
2312 unsigned int
2313 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2314 uint32_t pixel_format, uint64_t fb_format_modifier)
2315 {
2316 return ALIGN(height, intel_tile_height(dev, pixel_format,
2317 fb_format_modifier));
2318 }
2319
2320 static int
2321 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2322 const struct drm_plane_state *plane_state)
2323 {
2324 struct intel_rotation_info *info = &view->rotation_info;
2325
2326 *view = i915_ggtt_view_normal;
2327
2328 if (!plane_state)
2329 return 0;
2330
2331 if (!intel_rotation_90_or_270(plane_state->rotation))
2332 return 0;
2333
2334 *view = i915_ggtt_view_rotated;
2335
2336 info->height = fb->height;
2337 info->pixel_format = fb->pixel_format;
2338 info->pitch = fb->pitches[0];
2339 info->fb_modifier = fb->modifier[0];
2340
2341 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2342 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2343 DRM_DEBUG_KMS(
2344 "Y or Yf tiling is needed for 90/270 rotation!\n");
2345 return -EINVAL;
2346 }
2347
2348 return 0;
2349 }
2350
2351 int
2352 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2353 struct drm_framebuffer *fb,
2354 const struct drm_plane_state *plane_state,
2355 struct intel_engine_cs *pipelined)
2356 {
2357 struct drm_device *dev = fb->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2360 struct i915_ggtt_view view;
2361 u32 alignment;
2362 int ret;
2363
2364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
2366 switch (fb->modifier[0]) {
2367 case DRM_FORMAT_MOD_NONE:
2368 if (INTEL_INFO(dev)->gen >= 9)
2369 alignment = 256 * 1024;
2370 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2371 alignment = 128 * 1024;
2372 else if (INTEL_INFO(dev)->gen >= 4)
2373 alignment = 4 * 1024;
2374 else
2375 alignment = 64 * 1024;
2376 break;
2377 case I915_FORMAT_MOD_X_TILED:
2378 if (INTEL_INFO(dev)->gen >= 9)
2379 alignment = 256 * 1024;
2380 else {
2381 /* pin() will align the object as required by fence */
2382 alignment = 0;
2383 }
2384 break;
2385 case I915_FORMAT_MOD_Y_TILED:
2386 case I915_FORMAT_MOD_Yf_TILED:
2387 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2388 "Y tiling bo slipped through, driver bug!\n"))
2389 return -EINVAL;
2390 alignment = 1 * 1024 * 1024;
2391 break;
2392 default:
2393 MISSING_CASE(fb->modifier[0]);
2394 return -EINVAL;
2395 }
2396
2397 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2398 if (ret)
2399 return ret;
2400
2401 /* Note that the w/a also requires 64 PTE of padding following the
2402 * bo. We currently fill all unused PTE with the shadow page and so
2403 * we should always have valid PTE following the scanout preventing
2404 * the VT-d warning.
2405 */
2406 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2407 alignment = 256 * 1024;
2408
2409 /*
2410 * Global gtt pte registers are special registers which actually forward
2411 * writes to a chunk of system memory. Which means that there is no risk
2412 * that the register values disappear as soon as we call
2413 * intel_runtime_pm_put(), so it is correct to wrap only the
2414 * pin/unpin/fence and not more.
2415 */
2416 intel_runtime_pm_get(dev_priv);
2417
2418 dev_priv->mm.interruptible = false;
2419 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2420 &view);
2421 if (ret)
2422 goto err_interruptible;
2423
2424 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2425 * fence, whereas 965+ only requires a fence if using
2426 * framebuffer compression. For simplicity, we always install
2427 * a fence as the cost is not that onerous.
2428 */
2429 ret = i915_gem_object_get_fence(obj);
2430 if (ret)
2431 goto err_unpin;
2432
2433 i915_gem_object_pin_fence(obj);
2434
2435 dev_priv->mm.interruptible = true;
2436 intel_runtime_pm_put(dev_priv);
2437 return 0;
2438
2439 err_unpin:
2440 i915_gem_object_unpin_from_display_plane(obj, &view);
2441 err_interruptible:
2442 dev_priv->mm.interruptible = true;
2443 intel_runtime_pm_put(dev_priv);
2444 return ret;
2445 }
2446
2447 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2448 const struct drm_plane_state *plane_state)
2449 {
2450 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2451 struct i915_ggtt_view view;
2452 int ret;
2453
2454 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2455
2456 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2457 WARN_ONCE(ret, "Couldn't get view from plane state!");
2458
2459 i915_gem_object_unpin_fence(obj);
2460 i915_gem_object_unpin_from_display_plane(obj, &view);
2461 }
2462
2463 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2464 * is assumed to be a power-of-two. */
2465 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2466 unsigned int tiling_mode,
2467 unsigned int cpp,
2468 unsigned int pitch)
2469 {
2470 if (tiling_mode != I915_TILING_NONE) {
2471 unsigned int tile_rows, tiles;
2472
2473 tile_rows = *y / 8;
2474 *y %= 8;
2475
2476 tiles = *x / (512/cpp);
2477 *x %= 512/cpp;
2478
2479 return tile_rows * pitch * 8 + tiles * 4096;
2480 } else {
2481 unsigned int offset;
2482
2483 offset = *y * pitch + *x * cpp;
2484 *y = 0;
2485 *x = (offset & 4095) / cpp;
2486 return offset & -4096;
2487 }
2488 }
2489
2490 static int i9xx_format_to_fourcc(int format)
2491 {
2492 switch (format) {
2493 case DISPPLANE_8BPP:
2494 return DRM_FORMAT_C8;
2495 case DISPPLANE_BGRX555:
2496 return DRM_FORMAT_XRGB1555;
2497 case DISPPLANE_BGRX565:
2498 return DRM_FORMAT_RGB565;
2499 default:
2500 case DISPPLANE_BGRX888:
2501 return DRM_FORMAT_XRGB8888;
2502 case DISPPLANE_RGBX888:
2503 return DRM_FORMAT_XBGR8888;
2504 case DISPPLANE_BGRX101010:
2505 return DRM_FORMAT_XRGB2101010;
2506 case DISPPLANE_RGBX101010:
2507 return DRM_FORMAT_XBGR2101010;
2508 }
2509 }
2510
2511 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2512 {
2513 switch (format) {
2514 case PLANE_CTL_FORMAT_RGB_565:
2515 return DRM_FORMAT_RGB565;
2516 default:
2517 case PLANE_CTL_FORMAT_XRGB_8888:
2518 if (rgb_order) {
2519 if (alpha)
2520 return DRM_FORMAT_ABGR8888;
2521 else
2522 return DRM_FORMAT_XBGR8888;
2523 } else {
2524 if (alpha)
2525 return DRM_FORMAT_ARGB8888;
2526 else
2527 return DRM_FORMAT_XRGB8888;
2528 }
2529 case PLANE_CTL_FORMAT_XRGB_2101010:
2530 if (rgb_order)
2531 return DRM_FORMAT_XBGR2101010;
2532 else
2533 return DRM_FORMAT_XRGB2101010;
2534 }
2535 }
2536
2537 static bool
2538 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2539 struct intel_initial_plane_config *plane_config)
2540 {
2541 struct drm_device *dev = crtc->base.dev;
2542 struct drm_i915_gem_object *obj = NULL;
2543 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2544 struct drm_framebuffer *fb = &plane_config->fb->base;
2545 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2546 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2547 PAGE_SIZE);
2548
2549 size_aligned -= base_aligned;
2550
2551 if (plane_config->size == 0)
2552 return false;
2553
2554 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555 base_aligned,
2556 base_aligned,
2557 size_aligned);
2558 if (!obj)
2559 return false;
2560
2561 obj->tiling_mode = plane_config->tiling;
2562 if (obj->tiling_mode == I915_TILING_X)
2563 obj->stride = fb->pitches[0];
2564
2565 mode_cmd.pixel_format = fb->pixel_format;
2566 mode_cmd.width = fb->width;
2567 mode_cmd.height = fb->height;
2568 mode_cmd.pitches[0] = fb->pitches[0];
2569 mode_cmd.modifier[0] = fb->modifier[0];
2570 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2571
2572 mutex_lock(&dev->struct_mutex);
2573 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2574 &mode_cmd, obj)) {
2575 DRM_DEBUG_KMS("intel fb init failed\n");
2576 goto out_unref_obj;
2577 }
2578 mutex_unlock(&dev->struct_mutex);
2579
2580 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2581 return true;
2582
2583 out_unref_obj:
2584 drm_gem_object_unreference(&obj->base);
2585 mutex_unlock(&dev->struct_mutex);
2586 return false;
2587 }
2588
2589 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2590 static void
2591 update_state_fb(struct drm_plane *plane)
2592 {
2593 if (plane->fb == plane->state->fb)
2594 return;
2595
2596 if (plane->state->fb)
2597 drm_framebuffer_unreference(plane->state->fb);
2598 plane->state->fb = plane->fb;
2599 if (plane->state->fb)
2600 drm_framebuffer_reference(plane->state->fb);
2601 }
2602
2603 static void
2604 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605 struct intel_initial_plane_config *plane_config)
2606 {
2607 struct drm_device *dev = intel_crtc->base.dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 struct drm_crtc *c;
2610 struct intel_crtc *i;
2611 struct drm_i915_gem_object *obj;
2612 struct drm_plane *primary = intel_crtc->base.primary;
2613 struct drm_framebuffer *fb;
2614
2615 if (!plane_config->fb)
2616 return;
2617
2618 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2619 fb = &plane_config->fb->base;
2620 goto valid_fb;
2621 }
2622
2623 kfree(plane_config->fb);
2624
2625 /*
2626 * Failed to alloc the obj, check to see if we should share
2627 * an fb with another CRTC instead
2628 */
2629 for_each_crtc(dev, c) {
2630 i = to_intel_crtc(c);
2631
2632 if (c == &intel_crtc->base)
2633 continue;
2634
2635 if (!i->active)
2636 continue;
2637
2638 fb = c->primary->fb;
2639 if (!fb)
2640 continue;
2641
2642 obj = intel_fb_obj(fb);
2643 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2644 drm_framebuffer_reference(fb);
2645 goto valid_fb;
2646 }
2647 }
2648
2649 return;
2650
2651 valid_fb:
2652 obj = intel_fb_obj(fb);
2653 if (obj->tiling_mode != I915_TILING_NONE)
2654 dev_priv->preserve_bios_swizzle = true;
2655
2656 primary->fb = fb;
2657 primary->state->crtc = &intel_crtc->base;
2658 primary->crtc = &intel_crtc->base;
2659 update_state_fb(primary);
2660 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2661 }
2662
2663 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2664 struct drm_framebuffer *fb,
2665 int x, int y)
2666 {
2667 struct drm_device *dev = crtc->dev;
2668 struct drm_i915_private *dev_priv = dev->dev_private;
2669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2670 struct drm_i915_gem_object *obj;
2671 int plane = intel_crtc->plane;
2672 unsigned long linear_offset;
2673 u32 dspcntr;
2674 u32 reg = DSPCNTR(plane);
2675 int pixel_size;
2676
2677 if (!intel_crtc->primary_enabled) {
2678 I915_WRITE(reg, 0);
2679 if (INTEL_INFO(dev)->gen >= 4)
2680 I915_WRITE(DSPSURF(plane), 0);
2681 else
2682 I915_WRITE(DSPADDR(plane), 0);
2683 POSTING_READ(reg);
2684 return;
2685 }
2686
2687 obj = intel_fb_obj(fb);
2688 if (WARN_ON(obj == NULL))
2689 return;
2690
2691 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2692
2693 dspcntr = DISPPLANE_GAMMA_ENABLE;
2694
2695 dspcntr |= DISPLAY_PLANE_ENABLE;
2696
2697 if (INTEL_INFO(dev)->gen < 4) {
2698 if (intel_crtc->pipe == PIPE_B)
2699 dspcntr |= DISPPLANE_SEL_PIPE_B;
2700
2701 /* pipesrc and dspsize control the size that is scaled from,
2702 * which should always be the user's requested size.
2703 */
2704 I915_WRITE(DSPSIZE(plane),
2705 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2706 (intel_crtc->config->pipe_src_w - 1));
2707 I915_WRITE(DSPPOS(plane), 0);
2708 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2709 I915_WRITE(PRIMSIZE(plane),
2710 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2711 (intel_crtc->config->pipe_src_w - 1));
2712 I915_WRITE(PRIMPOS(plane), 0);
2713 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2714 }
2715
2716 switch (fb->pixel_format) {
2717 case DRM_FORMAT_C8:
2718 dspcntr |= DISPPLANE_8BPP;
2719 break;
2720 case DRM_FORMAT_XRGB1555:
2721 case DRM_FORMAT_ARGB1555:
2722 dspcntr |= DISPPLANE_BGRX555;
2723 break;
2724 case DRM_FORMAT_RGB565:
2725 dspcntr |= DISPPLANE_BGRX565;
2726 break;
2727 case DRM_FORMAT_XRGB8888:
2728 case DRM_FORMAT_ARGB8888:
2729 dspcntr |= DISPPLANE_BGRX888;
2730 break;
2731 case DRM_FORMAT_XBGR8888:
2732 case DRM_FORMAT_ABGR8888:
2733 dspcntr |= DISPPLANE_RGBX888;
2734 break;
2735 case DRM_FORMAT_XRGB2101010:
2736 case DRM_FORMAT_ARGB2101010:
2737 dspcntr |= DISPPLANE_BGRX101010;
2738 break;
2739 case DRM_FORMAT_XBGR2101010:
2740 case DRM_FORMAT_ABGR2101010:
2741 dspcntr |= DISPPLANE_RGBX101010;
2742 break;
2743 default:
2744 BUG();
2745 }
2746
2747 if (INTEL_INFO(dev)->gen >= 4 &&
2748 obj->tiling_mode != I915_TILING_NONE)
2749 dspcntr |= DISPPLANE_TILED;
2750
2751 if (IS_G4X(dev))
2752 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2753
2754 linear_offset = y * fb->pitches[0] + x * pixel_size;
2755
2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 intel_crtc->dspaddr_offset =
2758 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2759 pixel_size,
2760 fb->pitches[0]);
2761 linear_offset -= intel_crtc->dspaddr_offset;
2762 } else {
2763 intel_crtc->dspaddr_offset = linear_offset;
2764 }
2765
2766 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2767 dspcntr |= DISPPLANE_ROTATE_180;
2768
2769 x += (intel_crtc->config->pipe_src_w - 1);
2770 y += (intel_crtc->config->pipe_src_h - 1);
2771
2772 /* Finding the last pixel of the last line of the display
2773 data and adding to linear_offset*/
2774 linear_offset +=
2775 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2776 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2777 }
2778
2779 I915_WRITE(reg, dspcntr);
2780
2781 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2782 if (INTEL_INFO(dev)->gen >= 4) {
2783 I915_WRITE(DSPSURF(plane),
2784 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2785 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2786 I915_WRITE(DSPLINOFF(plane), linear_offset);
2787 } else
2788 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2789 POSTING_READ(reg);
2790 }
2791
2792 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2793 struct drm_framebuffer *fb,
2794 int x, int y)
2795 {
2796 struct drm_device *dev = crtc->dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799 struct drm_i915_gem_object *obj;
2800 int plane = intel_crtc->plane;
2801 unsigned long linear_offset;
2802 u32 dspcntr;
2803 u32 reg = DSPCNTR(plane);
2804 int pixel_size;
2805
2806 if (!intel_crtc->primary_enabled) {
2807 I915_WRITE(reg, 0);
2808 I915_WRITE(DSPSURF(plane), 0);
2809 POSTING_READ(reg);
2810 return;
2811 }
2812
2813 obj = intel_fb_obj(fb);
2814 if (WARN_ON(obj == NULL))
2815 return;
2816
2817 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818
2819 dspcntr = DISPPLANE_GAMMA_ENABLE;
2820
2821 dspcntr |= DISPLAY_PLANE_ENABLE;
2822
2823 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2825
2826 switch (fb->pixel_format) {
2827 case DRM_FORMAT_C8:
2828 dspcntr |= DISPPLANE_8BPP;
2829 break;
2830 case DRM_FORMAT_RGB565:
2831 dspcntr |= DISPPLANE_BGRX565;
2832 break;
2833 case DRM_FORMAT_XRGB8888:
2834 case DRM_FORMAT_ARGB8888:
2835 dspcntr |= DISPPLANE_BGRX888;
2836 break;
2837 case DRM_FORMAT_XBGR8888:
2838 case DRM_FORMAT_ABGR8888:
2839 dspcntr |= DISPPLANE_RGBX888;
2840 break;
2841 case DRM_FORMAT_XRGB2101010:
2842 case DRM_FORMAT_ARGB2101010:
2843 dspcntr |= DISPPLANE_BGRX101010;
2844 break;
2845 case DRM_FORMAT_XBGR2101010:
2846 case DRM_FORMAT_ABGR2101010:
2847 dspcntr |= DISPPLANE_RGBX101010;
2848 break;
2849 default:
2850 BUG();
2851 }
2852
2853 if (obj->tiling_mode != I915_TILING_NONE)
2854 dspcntr |= DISPPLANE_TILED;
2855
2856 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2857 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2858
2859 linear_offset = y * fb->pitches[0] + x * pixel_size;
2860 intel_crtc->dspaddr_offset =
2861 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2862 pixel_size,
2863 fb->pitches[0]);
2864 linear_offset -= intel_crtc->dspaddr_offset;
2865 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2866 dspcntr |= DISPPLANE_ROTATE_180;
2867
2868 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2869 x += (intel_crtc->config->pipe_src_w - 1);
2870 y += (intel_crtc->config->pipe_src_h - 1);
2871
2872 /* Finding the last pixel of the last line of the display
2873 data and adding to linear_offset*/
2874 linear_offset +=
2875 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2876 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2877 }
2878 }
2879
2880 I915_WRITE(reg, dspcntr);
2881
2882 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2883 I915_WRITE(DSPSURF(plane),
2884 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2885 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2886 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887 } else {
2888 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890 }
2891 POSTING_READ(reg);
2892 }
2893
2894 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895 uint32_t pixel_format)
2896 {
2897 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898
2899 /*
2900 * The stride is either expressed as a multiple of 64 bytes
2901 * chunks for linear buffers or in number of tiles for tiled
2902 * buffers.
2903 */
2904 switch (fb_modifier) {
2905 case DRM_FORMAT_MOD_NONE:
2906 return 64;
2907 case I915_FORMAT_MOD_X_TILED:
2908 if (INTEL_INFO(dev)->gen == 2)
2909 return 128;
2910 return 512;
2911 case I915_FORMAT_MOD_Y_TILED:
2912 /* No need to check for old gens and Y tiling since this is
2913 * about the display engine and those will be blocked before
2914 * we get here.
2915 */
2916 return 128;
2917 case I915_FORMAT_MOD_Yf_TILED:
2918 if (bits_per_pixel == 8)
2919 return 64;
2920 else
2921 return 128;
2922 default:
2923 MISSING_CASE(fb_modifier);
2924 return 64;
2925 }
2926 }
2927
2928 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2929 struct drm_i915_gem_object *obj)
2930 {
2931 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2932
2933 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2934 view = &i915_ggtt_view_rotated;
2935
2936 return i915_gem_obj_ggtt_offset_view(obj, view);
2937 }
2938
2939 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2940 struct drm_framebuffer *fb,
2941 int x, int y)
2942 {
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2946 struct drm_i915_gem_object *obj;
2947 int pipe = intel_crtc->pipe;
2948 u32 plane_ctl, stride_div;
2949 unsigned long surf_addr;
2950
2951 if (!intel_crtc->primary_enabled) {
2952 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2953 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2954 POSTING_READ(PLANE_CTL(pipe, 0));
2955 return;
2956 }
2957
2958 plane_ctl = PLANE_CTL_ENABLE |
2959 PLANE_CTL_PIPE_GAMMA_ENABLE |
2960 PLANE_CTL_PIPE_CSC_ENABLE;
2961
2962 switch (fb->pixel_format) {
2963 case DRM_FORMAT_RGB565:
2964 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2965 break;
2966 case DRM_FORMAT_XRGB8888:
2967 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2968 break;
2969 case DRM_FORMAT_ARGB8888:
2970 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2971 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2972 break;
2973 case DRM_FORMAT_XBGR8888:
2974 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2975 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2976 break;
2977 case DRM_FORMAT_ABGR8888:
2978 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2979 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2980 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2981 break;
2982 case DRM_FORMAT_XRGB2101010:
2983 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2984 break;
2985 case DRM_FORMAT_XBGR2101010:
2986 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2987 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2988 break;
2989 default:
2990 BUG();
2991 }
2992
2993 switch (fb->modifier[0]) {
2994 case DRM_FORMAT_MOD_NONE:
2995 break;
2996 case I915_FORMAT_MOD_X_TILED:
2997 plane_ctl |= PLANE_CTL_TILED_X;
2998 break;
2999 case I915_FORMAT_MOD_Y_TILED:
3000 plane_ctl |= PLANE_CTL_TILED_Y;
3001 break;
3002 case I915_FORMAT_MOD_Yf_TILED:
3003 plane_ctl |= PLANE_CTL_TILED_YF;
3004 break;
3005 default:
3006 MISSING_CASE(fb->modifier[0]);
3007 }
3008
3009 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3010 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
3011 plane_ctl |= PLANE_CTL_ROTATE_180;
3012
3013 obj = intel_fb_obj(fb);
3014 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3015 fb->pixel_format);
3016 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
3017
3018 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3019 I915_WRITE(PLANE_POS(pipe, 0), 0);
3020 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
3021 I915_WRITE(PLANE_SIZE(pipe, 0),
3022 (intel_crtc->config->pipe_src_h - 1) << 16 |
3023 (intel_crtc->config->pipe_src_w - 1));
3024 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
3025 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3026
3027 POSTING_READ(PLANE_SURF(pipe, 0));
3028 }
3029
3030 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3031 static int
3032 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3033 int x, int y, enum mode_set_atomic state)
3034 {
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037
3038 if (dev_priv->display.disable_fbc)
3039 dev_priv->display.disable_fbc(dev);
3040
3041 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3042
3043 return 0;
3044 }
3045
3046 static void intel_complete_page_flips(struct drm_device *dev)
3047 {
3048 struct drm_crtc *crtc;
3049
3050 for_each_crtc(dev, crtc) {
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 enum plane plane = intel_crtc->plane;
3053
3054 intel_prepare_page_flip(dev, plane);
3055 intel_finish_page_flip_plane(dev, plane);
3056 }
3057 }
3058
3059 static void intel_update_primary_planes(struct drm_device *dev)
3060 {
3061 struct drm_i915_private *dev_priv = dev->dev_private;
3062 struct drm_crtc *crtc;
3063
3064 for_each_crtc(dev, crtc) {
3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066
3067 drm_modeset_lock(&crtc->mutex, NULL);
3068 /*
3069 * FIXME: Once we have proper support for primary planes (and
3070 * disabling them without disabling the entire crtc) allow again
3071 * a NULL crtc->primary->fb.
3072 */
3073 if (intel_crtc->active && crtc->primary->fb)
3074 dev_priv->display.update_primary_plane(crtc,
3075 crtc->primary->fb,
3076 crtc->x,
3077 crtc->y);
3078 drm_modeset_unlock(&crtc->mutex);
3079 }
3080 }
3081
3082 void intel_prepare_reset(struct drm_device *dev)
3083 {
3084 struct drm_i915_private *dev_priv = to_i915(dev);
3085 struct intel_crtc *crtc;
3086
3087 /* no reset support for gen2 */
3088 if (IS_GEN2(dev))
3089 return;
3090
3091 /* reset doesn't touch the display */
3092 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3093 return;
3094
3095 drm_modeset_lock_all(dev);
3096
3097 /*
3098 * Disabling the crtcs gracefully seems nicer. Also the
3099 * g33 docs say we should at least disable all the planes.
3100 */
3101 for_each_intel_crtc(dev, crtc) {
3102 if (crtc->active)
3103 dev_priv->display.crtc_disable(&crtc->base);
3104 }
3105 }
3106
3107 void intel_finish_reset(struct drm_device *dev)
3108 {
3109 struct drm_i915_private *dev_priv = to_i915(dev);
3110
3111 /*
3112 * Flips in the rings will be nuked by the reset,
3113 * so complete all pending flips so that user space
3114 * will get its events and not get stuck.
3115 */
3116 intel_complete_page_flips(dev);
3117
3118 /* no reset support for gen2 */
3119 if (IS_GEN2(dev))
3120 return;
3121
3122 /* reset doesn't touch the display */
3123 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3124 /*
3125 * Flips in the rings have been nuked by the reset,
3126 * so update the base address of all primary
3127 * planes to the the last fb to make sure we're
3128 * showing the correct fb after a reset.
3129 */
3130 intel_update_primary_planes(dev);
3131 return;
3132 }
3133
3134 /*
3135 * The display has been reset as well,
3136 * so need a full re-initialization.
3137 */
3138 intel_runtime_pm_disable_interrupts(dev_priv);
3139 intel_runtime_pm_enable_interrupts(dev_priv);
3140
3141 intel_modeset_init_hw(dev);
3142
3143 spin_lock_irq(&dev_priv->irq_lock);
3144 if (dev_priv->display.hpd_irq_setup)
3145 dev_priv->display.hpd_irq_setup(dev);
3146 spin_unlock_irq(&dev_priv->irq_lock);
3147
3148 intel_modeset_setup_hw_state(dev, true);
3149
3150 intel_hpd_init(dev_priv);
3151
3152 drm_modeset_unlock_all(dev);
3153 }
3154
3155 static int
3156 intel_finish_fb(struct drm_framebuffer *old_fb)
3157 {
3158 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3159 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3160 bool was_interruptible = dev_priv->mm.interruptible;
3161 int ret;
3162
3163 /* Big Hammer, we also need to ensure that any pending
3164 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3165 * current scanout is retired before unpinning the old
3166 * framebuffer.
3167 *
3168 * This should only fail upon a hung GPU, in which case we
3169 * can safely continue.
3170 */
3171 dev_priv->mm.interruptible = false;
3172 ret = i915_gem_object_finish_gpu(obj);
3173 dev_priv->mm.interruptible = was_interruptible;
3174
3175 return ret;
3176 }
3177
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179 {
3180 struct drm_device *dev = crtc->dev;
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3183 bool pending;
3184
3185 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3186 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3187 return false;
3188
3189 spin_lock_irq(&dev->event_lock);
3190 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3191 spin_unlock_irq(&dev->event_lock);
3192
3193 return pending;
3194 }
3195
3196 static void intel_update_pipe_size(struct intel_crtc *crtc)
3197 {
3198 struct drm_device *dev = crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 const struct drm_display_mode *adjusted_mode;
3201
3202 if (!i915.fastboot)
3203 return;
3204
3205 /*
3206 * Update pipe size and adjust fitter if needed: the reason for this is
3207 * that in compute_mode_changes we check the native mode (not the pfit
3208 * mode) to see if we can flip rather than do a full mode set. In the
3209 * fastboot case, we'll flip, but if we don't update the pipesrc and
3210 * pfit state, we'll end up with a big fb scanned out into the wrong
3211 * sized surface.
3212 *
3213 * To fix this properly, we need to hoist the checks up into
3214 * compute_mode_changes (or above), check the actual pfit state and
3215 * whether the platform allows pfit disable with pipe active, and only
3216 * then update the pipesrc and pfit state, even on the flip path.
3217 */
3218
3219 adjusted_mode = &crtc->config->base.adjusted_mode;
3220
3221 I915_WRITE(PIPESRC(crtc->pipe),
3222 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3223 (adjusted_mode->crtc_vdisplay - 1));
3224 if (!crtc->config->pch_pfit.enabled &&
3225 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3226 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3227 I915_WRITE(PF_CTL(crtc->pipe), 0);
3228 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3229 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3230 }
3231 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3232 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3233 }
3234
3235 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3236 {
3237 struct drm_device *dev = crtc->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3240 int pipe = intel_crtc->pipe;
3241 u32 reg, temp;
3242
3243 /* enable normal train */
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
3246 if (IS_IVYBRIDGE(dev)) {
3247 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3248 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3249 } else {
3250 temp &= ~FDI_LINK_TRAIN_NONE;
3251 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3252 }
3253 I915_WRITE(reg, temp);
3254
3255 reg = FDI_RX_CTL(pipe);
3256 temp = I915_READ(reg);
3257 if (HAS_PCH_CPT(dev)) {
3258 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3259 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3260 } else {
3261 temp &= ~FDI_LINK_TRAIN_NONE;
3262 temp |= FDI_LINK_TRAIN_NONE;
3263 }
3264 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3265
3266 /* wait one idle pattern time */
3267 POSTING_READ(reg);
3268 udelay(1000);
3269
3270 /* IVB wants error correction enabled */
3271 if (IS_IVYBRIDGE(dev))
3272 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3273 FDI_FE_ERRC_ENABLE);
3274 }
3275
3276 /* The FDI link training functions for ILK/Ibexpeak. */
3277 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3278 {
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282 int pipe = intel_crtc->pipe;
3283 u32 reg, temp, tries;
3284
3285 /* FDI needs bits from pipe first */
3286 assert_pipe_enabled(dev_priv, pipe);
3287
3288 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3289 for train result */
3290 reg = FDI_RX_IMR(pipe);
3291 temp = I915_READ(reg);
3292 temp &= ~FDI_RX_SYMBOL_LOCK;
3293 temp &= ~FDI_RX_BIT_LOCK;
3294 I915_WRITE(reg, temp);
3295 I915_READ(reg);
3296 udelay(150);
3297
3298 /* enable CPU FDI TX and PCH FDI RX */
3299 reg = FDI_TX_CTL(pipe);
3300 temp = I915_READ(reg);
3301 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3302 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3303 temp &= ~FDI_LINK_TRAIN_NONE;
3304 temp |= FDI_LINK_TRAIN_PATTERN_1;
3305 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3306
3307 reg = FDI_RX_CTL(pipe);
3308 temp = I915_READ(reg);
3309 temp &= ~FDI_LINK_TRAIN_NONE;
3310 temp |= FDI_LINK_TRAIN_PATTERN_1;
3311 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3312
3313 POSTING_READ(reg);
3314 udelay(150);
3315
3316 /* Ironlake workaround, enable clock pointer after FDI enable*/
3317 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3318 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3319 FDI_RX_PHASE_SYNC_POINTER_EN);
3320
3321 reg = FDI_RX_IIR(pipe);
3322 for (tries = 0; tries < 5; tries++) {
3323 temp = I915_READ(reg);
3324 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3325
3326 if ((temp & FDI_RX_BIT_LOCK)) {
3327 DRM_DEBUG_KMS("FDI train 1 done.\n");
3328 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3329 break;
3330 }
3331 }
3332 if (tries == 5)
3333 DRM_ERROR("FDI train 1 fail!\n");
3334
3335 /* Train 2 */
3336 reg = FDI_TX_CTL(pipe);
3337 temp = I915_READ(reg);
3338 temp &= ~FDI_LINK_TRAIN_NONE;
3339 temp |= FDI_LINK_TRAIN_PATTERN_2;
3340 I915_WRITE(reg, temp);
3341
3342 reg = FDI_RX_CTL(pipe);
3343 temp = I915_READ(reg);
3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_PATTERN_2;
3346 I915_WRITE(reg, temp);
3347
3348 POSTING_READ(reg);
3349 udelay(150);
3350
3351 reg = FDI_RX_IIR(pipe);
3352 for (tries = 0; tries < 5; tries++) {
3353 temp = I915_READ(reg);
3354 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3355
3356 if (temp & FDI_RX_SYMBOL_LOCK) {
3357 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3358 DRM_DEBUG_KMS("FDI train 2 done.\n");
3359 break;
3360 }
3361 }
3362 if (tries == 5)
3363 DRM_ERROR("FDI train 2 fail!\n");
3364
3365 DRM_DEBUG_KMS("FDI train done\n");
3366
3367 }
3368
3369 static const int snb_b_fdi_train_param[] = {
3370 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3371 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3372 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3373 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3374 };
3375
3376 /* The FDI link training functions for SNB/Cougarpoint. */
3377 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3378 {
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
3383 u32 reg, temp, i, retry;
3384
3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
3391 I915_WRITE(reg, temp);
3392
3393 POSTING_READ(reg);
3394 udelay(150);
3395
3396 /* enable CPU FDI TX and PCH FDI RX */
3397 reg = FDI_TX_CTL(pipe);
3398 temp = I915_READ(reg);
3399 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3400 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3401 temp &= ~FDI_LINK_TRAIN_NONE;
3402 temp |= FDI_LINK_TRAIN_PATTERN_1;
3403 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3404 /* SNB-B */
3405 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3407
3408 I915_WRITE(FDI_RX_MISC(pipe),
3409 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3410
3411 reg = FDI_RX_CTL(pipe);
3412 temp = I915_READ(reg);
3413 if (HAS_PCH_CPT(dev)) {
3414 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3415 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3416 } else {
3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
3419 }
3420 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3421
3422 POSTING_READ(reg);
3423 udelay(150);
3424
3425 for (i = 0; i < 4; i++) {
3426 reg = FDI_TX_CTL(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3429 temp |= snb_b_fdi_train_param[i];
3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
3433 udelay(500);
3434
3435 for (retry = 0; retry < 5; retry++) {
3436 reg = FDI_RX_IIR(pipe);
3437 temp = I915_READ(reg);
3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439 if (temp & FDI_RX_BIT_LOCK) {
3440 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3441 DRM_DEBUG_KMS("FDI train 1 done.\n");
3442 break;
3443 }
3444 udelay(50);
3445 }
3446 if (retry < 5)
3447 break;
3448 }
3449 if (i == 4)
3450 DRM_ERROR("FDI train 1 fail!\n");
3451
3452 /* Train 2 */
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 if (IS_GEN6(dev)) {
3458 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3459 /* SNB-B */
3460 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3461 }
3462 I915_WRITE(reg, temp);
3463
3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 if (HAS_PCH_CPT(dev)) {
3467 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3469 } else {
3470 temp &= ~FDI_LINK_TRAIN_NONE;
3471 temp |= FDI_LINK_TRAIN_PATTERN_2;
3472 }
3473 I915_WRITE(reg, temp);
3474
3475 POSTING_READ(reg);
3476 udelay(150);
3477
3478 for (i = 0; i < 4; i++) {
3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
3481 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3482 temp |= snb_b_fdi_train_param[i];
3483 I915_WRITE(reg, temp);
3484
3485 POSTING_READ(reg);
3486 udelay(500);
3487
3488 for (retry = 0; retry < 5; retry++) {
3489 reg = FDI_RX_IIR(pipe);
3490 temp = I915_READ(reg);
3491 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3492 if (temp & FDI_RX_SYMBOL_LOCK) {
3493 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3494 DRM_DEBUG_KMS("FDI train 2 done.\n");
3495 break;
3496 }
3497 udelay(50);
3498 }
3499 if (retry < 5)
3500 break;
3501 }
3502 if (i == 4)
3503 DRM_ERROR("FDI train 2 fail!\n");
3504
3505 DRM_DEBUG_KMS("FDI train done.\n");
3506 }
3507
3508 /* Manual link training for Ivy Bridge A0 parts */
3509 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3510 {
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 int pipe = intel_crtc->pipe;
3515 u32 reg, temp, i, j;
3516
3517 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3518 for train result */
3519 reg = FDI_RX_IMR(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_RX_SYMBOL_LOCK;
3522 temp &= ~FDI_RX_BIT_LOCK;
3523 I915_WRITE(reg, temp);
3524
3525 POSTING_READ(reg);
3526 udelay(150);
3527
3528 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3529 I915_READ(FDI_RX_IIR(pipe)));
3530
3531 /* Try each vswing and preemphasis setting twice before moving on */
3532 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3533 /* disable first in case we need to retry */
3534 reg = FDI_TX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3537 temp &= ~FDI_TX_ENABLE;
3538 I915_WRITE(reg, temp);
3539
3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_AUTO;
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp &= ~FDI_RX_ENABLE;
3545 I915_WRITE(reg, temp);
3546
3547 /* enable CPU FDI TX and PCH FDI RX */
3548 reg = FDI_TX_CTL(pipe);
3549 temp = I915_READ(reg);
3550 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3551 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3552 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3554 temp |= snb_b_fdi_train_param[j/2];
3555 temp |= FDI_COMPOSITE_SYNC;
3556 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3557
3558 I915_WRITE(FDI_RX_MISC(pipe),
3559 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3560
3561 reg = FDI_RX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3564 temp |= FDI_COMPOSITE_SYNC;
3565 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3566
3567 POSTING_READ(reg);
3568 udelay(1); /* should be 0.5us */
3569
3570 for (i = 0; i < 4; i++) {
3571 reg = FDI_RX_IIR(pipe);
3572 temp = I915_READ(reg);
3573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3574
3575 if (temp & FDI_RX_BIT_LOCK ||
3576 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3578 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3579 i);
3580 break;
3581 }
3582 udelay(1); /* should be 0.5us */
3583 }
3584 if (i == 4) {
3585 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3586 continue;
3587 }
3588
3589 /* Train 2 */
3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3593 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3594 I915_WRITE(reg, temp);
3595
3596 reg = FDI_RX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3599 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3600 I915_WRITE(reg, temp);
3601
3602 POSTING_READ(reg);
3603 udelay(2); /* should be 1.5us */
3604
3605 for (i = 0; i < 4; i++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609
3610 if (temp & FDI_RX_SYMBOL_LOCK ||
3611 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3612 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3613 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3614 i);
3615 goto train_done;
3616 }
3617 udelay(2); /* should be 1.5us */
3618 }
3619 if (i == 4)
3620 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3621 }
3622
3623 train_done:
3624 DRM_DEBUG_KMS("FDI train done.\n");
3625 }
3626
3627 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3628 {
3629 struct drm_device *dev = intel_crtc->base.dev;
3630 struct drm_i915_private *dev_priv = dev->dev_private;
3631 int pipe = intel_crtc->pipe;
3632 u32 reg, temp;
3633
3634
3635 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3636 reg = FDI_RX_CTL(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3639 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3640 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3641 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3642
3643 POSTING_READ(reg);
3644 udelay(200);
3645
3646 /* Switch from Rawclk to PCDclk */
3647 temp = I915_READ(reg);
3648 I915_WRITE(reg, temp | FDI_PCDCLK);
3649
3650 POSTING_READ(reg);
3651 udelay(200);
3652
3653 /* Enable CPU FDI TX PLL, always on for Ironlake */
3654 reg = FDI_TX_CTL(pipe);
3655 temp = I915_READ(reg);
3656 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3657 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3658
3659 POSTING_READ(reg);
3660 udelay(100);
3661 }
3662 }
3663
3664 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3665 {
3666 struct drm_device *dev = intel_crtc->base.dev;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 int pipe = intel_crtc->pipe;
3669 u32 reg, temp;
3670
3671 /* Switch from PCDclk to Rawclk */
3672 reg = FDI_RX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3675
3676 /* Disable CPU FDI TX PLL */
3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3680
3681 POSTING_READ(reg);
3682 udelay(100);
3683
3684 reg = FDI_RX_CTL(pipe);
3685 temp = I915_READ(reg);
3686 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3687
3688 /* Wait for the clocks to turn off. */
3689 POSTING_READ(reg);
3690 udelay(100);
3691 }
3692
3693 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3694 {
3695 struct drm_device *dev = crtc->dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698 int pipe = intel_crtc->pipe;
3699 u32 reg, temp;
3700
3701 /* disable CPU FDI tx and PCH FDI rx */
3702 reg = FDI_TX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3705 POSTING_READ(reg);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~(0x7 << 16);
3710 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3711 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3712
3713 POSTING_READ(reg);
3714 udelay(100);
3715
3716 /* Ironlake workaround, disable clock pointer after downing FDI */
3717 if (HAS_PCH_IBX(dev))
3718 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3719
3720 /* still set train pattern 1 */
3721 reg = FDI_TX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 temp &= ~FDI_LINK_TRAIN_NONE;
3724 temp |= FDI_LINK_TRAIN_PATTERN_1;
3725 I915_WRITE(reg, temp);
3726
3727 reg = FDI_RX_CTL(pipe);
3728 temp = I915_READ(reg);
3729 if (HAS_PCH_CPT(dev)) {
3730 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3731 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3732 } else {
3733 temp &= ~FDI_LINK_TRAIN_NONE;
3734 temp |= FDI_LINK_TRAIN_PATTERN_1;
3735 }
3736 /* BPC in FDI rx is consistent with that in PIPECONF */
3737 temp &= ~(0x07 << 16);
3738 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3739 I915_WRITE(reg, temp);
3740
3741 POSTING_READ(reg);
3742 udelay(100);
3743 }
3744
3745 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3746 {
3747 struct intel_crtc *crtc;
3748
3749 /* Note that we don't need to be called with mode_config.lock here
3750 * as our list of CRTC objects is static for the lifetime of the
3751 * device and so cannot disappear as we iterate. Similarly, we can
3752 * happily treat the predicates as racy, atomic checks as userspace
3753 * cannot claim and pin a new fb without at least acquring the
3754 * struct_mutex and so serialising with us.
3755 */
3756 for_each_intel_crtc(dev, crtc) {
3757 if (atomic_read(&crtc->unpin_work_count) == 0)
3758 continue;
3759
3760 if (crtc->unpin_work)
3761 intel_wait_for_vblank(dev, crtc->pipe);
3762
3763 return true;
3764 }
3765
3766 return false;
3767 }
3768
3769 static void page_flip_completed(struct intel_crtc *intel_crtc)
3770 {
3771 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3772 struct intel_unpin_work *work = intel_crtc->unpin_work;
3773
3774 /* ensure that the unpin work is consistent wrt ->pending. */
3775 smp_rmb();
3776 intel_crtc->unpin_work = NULL;
3777
3778 if (work->event)
3779 drm_send_vblank_event(intel_crtc->base.dev,
3780 intel_crtc->pipe,
3781 work->event);
3782
3783 drm_crtc_vblank_put(&intel_crtc->base);
3784
3785 wake_up_all(&dev_priv->pending_flip_queue);
3786 queue_work(dev_priv->wq, &work->work);
3787
3788 trace_i915_flip_complete(intel_crtc->plane,
3789 work->pending_flip_obj);
3790 }
3791
3792 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3793 {
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796
3797 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3798 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3799 !intel_crtc_has_pending_flip(crtc),
3800 60*HZ) == 0)) {
3801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3802
3803 spin_lock_irq(&dev->event_lock);
3804 if (intel_crtc->unpin_work) {
3805 WARN_ONCE(1, "Removing stuck page flip\n");
3806 page_flip_completed(intel_crtc);
3807 }
3808 spin_unlock_irq(&dev->event_lock);
3809 }
3810
3811 if (crtc->primary->fb) {
3812 mutex_lock(&dev->struct_mutex);
3813 intel_finish_fb(crtc->primary->fb);
3814 mutex_unlock(&dev->struct_mutex);
3815 }
3816 }
3817
3818 /* Program iCLKIP clock to the desired frequency */
3819 static void lpt_program_iclkip(struct drm_crtc *crtc)
3820 {
3821 struct drm_device *dev = crtc->dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3824 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3825 u32 temp;
3826
3827 mutex_lock(&dev_priv->dpio_lock);
3828
3829 /* It is necessary to ungate the pixclk gate prior to programming
3830 * the divisors, and gate it back when it is done.
3831 */
3832 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3833
3834 /* Disable SSCCTL */
3835 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3836 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3837 SBI_SSCCTL_DISABLE,
3838 SBI_ICLK);
3839
3840 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3841 if (clock == 20000) {
3842 auxdiv = 1;
3843 divsel = 0x41;
3844 phaseinc = 0x20;
3845 } else {
3846 /* The iCLK virtual clock root frequency is in MHz,
3847 * but the adjusted_mode->crtc_clock in in KHz. To get the
3848 * divisors, it is necessary to divide one by another, so we
3849 * convert the virtual clock precision to KHz here for higher
3850 * precision.
3851 */
3852 u32 iclk_virtual_root_freq = 172800 * 1000;
3853 u32 iclk_pi_range = 64;
3854 u32 desired_divisor, msb_divisor_value, pi_value;
3855
3856 desired_divisor = (iclk_virtual_root_freq / clock);
3857 msb_divisor_value = desired_divisor / iclk_pi_range;
3858 pi_value = desired_divisor % iclk_pi_range;
3859
3860 auxdiv = 0;
3861 divsel = msb_divisor_value - 2;
3862 phaseinc = pi_value;
3863 }
3864
3865 /* This should not happen with any sane values */
3866 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3867 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3868 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3869 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3870
3871 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3872 clock,
3873 auxdiv,
3874 divsel,
3875 phasedir,
3876 phaseinc);
3877
3878 /* Program SSCDIVINTPHASE6 */
3879 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3880 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3881 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3882 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3883 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3884 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3885 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3886 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3887
3888 /* Program SSCAUXDIV */
3889 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3890 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3891 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3892 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3893
3894 /* Enable modulator and associated divider */
3895 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3896 temp &= ~SBI_SSCCTL_DISABLE;
3897 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3898
3899 /* Wait for initialization time */
3900 udelay(24);
3901
3902 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3903
3904 mutex_unlock(&dev_priv->dpio_lock);
3905 }
3906
3907 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3908 enum pipe pch_transcoder)
3909 {
3910 struct drm_device *dev = crtc->base.dev;
3911 struct drm_i915_private *dev_priv = dev->dev_private;
3912 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3913
3914 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3915 I915_READ(HTOTAL(cpu_transcoder)));
3916 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3917 I915_READ(HBLANK(cpu_transcoder)));
3918 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3919 I915_READ(HSYNC(cpu_transcoder)));
3920
3921 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3922 I915_READ(VTOTAL(cpu_transcoder)));
3923 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3924 I915_READ(VBLANK(cpu_transcoder)));
3925 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3926 I915_READ(VSYNC(cpu_transcoder)));
3927 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3928 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3929 }
3930
3931 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3932 {
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 uint32_t temp;
3935
3936 temp = I915_READ(SOUTH_CHICKEN1);
3937 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3938 return;
3939
3940 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3941 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3942
3943 temp &= ~FDI_BC_BIFURCATION_SELECT;
3944 if (enable)
3945 temp |= FDI_BC_BIFURCATION_SELECT;
3946
3947 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3948 I915_WRITE(SOUTH_CHICKEN1, temp);
3949 POSTING_READ(SOUTH_CHICKEN1);
3950 }
3951
3952 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3953 {
3954 struct drm_device *dev = intel_crtc->base.dev;
3955
3956 switch (intel_crtc->pipe) {
3957 case PIPE_A:
3958 break;
3959 case PIPE_B:
3960 if (intel_crtc->config->fdi_lanes > 2)
3961 cpt_set_fdi_bc_bifurcation(dev, false);
3962 else
3963 cpt_set_fdi_bc_bifurcation(dev, true);
3964
3965 break;
3966 case PIPE_C:
3967 cpt_set_fdi_bc_bifurcation(dev, true);
3968
3969 break;
3970 default:
3971 BUG();
3972 }
3973 }
3974
3975 /*
3976 * Enable PCH resources required for PCH ports:
3977 * - PCH PLLs
3978 * - FDI training & RX/TX
3979 * - update transcoder timings
3980 * - DP transcoding bits
3981 * - transcoder
3982 */
3983 static void ironlake_pch_enable(struct drm_crtc *crtc)
3984 {
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988 int pipe = intel_crtc->pipe;
3989 u32 reg, temp;
3990
3991 assert_pch_transcoder_disabled(dev_priv, pipe);
3992
3993 if (IS_IVYBRIDGE(dev))
3994 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3995
3996 /* Write the TU size bits before fdi link training, so that error
3997 * detection works. */
3998 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3999 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4000
4001 /* For PCH output, training FDI link */
4002 dev_priv->display.fdi_link_train(crtc);
4003
4004 /* We need to program the right clock selection before writing the pixel
4005 * mutliplier into the DPLL. */
4006 if (HAS_PCH_CPT(dev)) {
4007 u32 sel;
4008
4009 temp = I915_READ(PCH_DPLL_SEL);
4010 temp |= TRANS_DPLL_ENABLE(pipe);
4011 sel = TRANS_DPLLB_SEL(pipe);
4012 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4013 temp |= sel;
4014 else
4015 temp &= ~sel;
4016 I915_WRITE(PCH_DPLL_SEL, temp);
4017 }
4018
4019 /* XXX: pch pll's can be enabled any time before we enable the PCH
4020 * transcoder, and we actually should do this to not upset any PCH
4021 * transcoder that already use the clock when we share it.
4022 *
4023 * Note that enable_shared_dpll tries to do the right thing, but
4024 * get_shared_dpll unconditionally resets the pll - we need that to have
4025 * the right LVDS enable sequence. */
4026 intel_enable_shared_dpll(intel_crtc);
4027
4028 /* set transcoder timing, panel must allow it */
4029 assert_panel_unlocked(dev_priv, pipe);
4030 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4031
4032 intel_fdi_normal_train(crtc);
4033
4034 /* For PCH DP, enable TRANS_DP_CTL */
4035 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4036 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4037 reg = TRANS_DP_CTL(pipe);
4038 temp = I915_READ(reg);
4039 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4040 TRANS_DP_SYNC_MASK |
4041 TRANS_DP_BPC_MASK);
4042 temp |= (TRANS_DP_OUTPUT_ENABLE |
4043 TRANS_DP_ENH_FRAMING);
4044 temp |= bpc << 9; /* same format but at 11:9 */
4045
4046 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4047 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4048 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4049 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4050
4051 switch (intel_trans_dp_port_sel(crtc)) {
4052 case PCH_DP_B:
4053 temp |= TRANS_DP_PORT_SEL_B;
4054 break;
4055 case PCH_DP_C:
4056 temp |= TRANS_DP_PORT_SEL_C;
4057 break;
4058 case PCH_DP_D:
4059 temp |= TRANS_DP_PORT_SEL_D;
4060 break;
4061 default:
4062 BUG();
4063 }
4064
4065 I915_WRITE(reg, temp);
4066 }
4067
4068 ironlake_enable_pch_transcoder(dev_priv, pipe);
4069 }
4070
4071 static void lpt_pch_enable(struct drm_crtc *crtc)
4072 {
4073 struct drm_device *dev = crtc->dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4076 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4077
4078 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4079
4080 lpt_program_iclkip(crtc);
4081
4082 /* Set transcoder timing. */
4083 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4084
4085 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4086 }
4087
4088 void intel_put_shared_dpll(struct intel_crtc *crtc)
4089 {
4090 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4091
4092 if (pll == NULL)
4093 return;
4094
4095 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4096 WARN(1, "bad %s crtc mask\n", pll->name);
4097 return;
4098 }
4099
4100 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4101 if (pll->config.crtc_mask == 0) {
4102 WARN_ON(pll->on);
4103 WARN_ON(pll->active);
4104 }
4105
4106 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4107 }
4108
4109 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4110 struct intel_crtc_state *crtc_state)
4111 {
4112 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4113 struct intel_shared_dpll *pll;
4114 enum intel_dpll_id i;
4115
4116 if (HAS_PCH_IBX(dev_priv->dev)) {
4117 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4118 i = (enum intel_dpll_id) crtc->pipe;
4119 pll = &dev_priv->shared_dplls[i];
4120
4121 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4122 crtc->base.base.id, pll->name);
4123
4124 WARN_ON(pll->new_config->crtc_mask);
4125
4126 goto found;
4127 }
4128
4129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4130 pll = &dev_priv->shared_dplls[i];
4131
4132 /* Only want to check enabled timings first */
4133 if (pll->new_config->crtc_mask == 0)
4134 continue;
4135
4136 if (memcmp(&crtc_state->dpll_hw_state,
4137 &pll->new_config->hw_state,
4138 sizeof(pll->new_config->hw_state)) == 0) {
4139 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4140 crtc->base.base.id, pll->name,
4141 pll->new_config->crtc_mask,
4142 pll->active);
4143 goto found;
4144 }
4145 }
4146
4147 /* Ok no matching timings, maybe there's a free one? */
4148 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4149 pll = &dev_priv->shared_dplls[i];
4150 if (pll->new_config->crtc_mask == 0) {
4151 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4152 crtc->base.base.id, pll->name);
4153 goto found;
4154 }
4155 }
4156
4157 return NULL;
4158
4159 found:
4160 if (pll->new_config->crtc_mask == 0)
4161 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4162
4163 crtc_state->shared_dpll = i;
4164 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4165 pipe_name(crtc->pipe));
4166
4167 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4168
4169 return pll;
4170 }
4171
4172 /**
4173 * intel_shared_dpll_start_config - start a new PLL staged config
4174 * @dev_priv: DRM device
4175 * @clear_pipes: mask of pipes that will have their PLLs freed
4176 *
4177 * Starts a new PLL staged config, copying the current config but
4178 * releasing the references of pipes specified in clear_pipes.
4179 */
4180 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4181 unsigned clear_pipes)
4182 {
4183 struct intel_shared_dpll *pll;
4184 enum intel_dpll_id i;
4185
4186 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4187 pll = &dev_priv->shared_dplls[i];
4188
4189 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4190 GFP_KERNEL);
4191 if (!pll->new_config)
4192 goto cleanup;
4193
4194 pll->new_config->crtc_mask &= ~clear_pipes;
4195 }
4196
4197 return 0;
4198
4199 cleanup:
4200 while (--i >= 0) {
4201 pll = &dev_priv->shared_dplls[i];
4202 kfree(pll->new_config);
4203 pll->new_config = NULL;
4204 }
4205
4206 return -ENOMEM;
4207 }
4208
4209 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4210 {
4211 struct intel_shared_dpll *pll;
4212 enum intel_dpll_id i;
4213
4214 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4215 pll = &dev_priv->shared_dplls[i];
4216
4217 WARN_ON(pll->new_config == &pll->config);
4218
4219 pll->config = *pll->new_config;
4220 kfree(pll->new_config);
4221 pll->new_config = NULL;
4222 }
4223 }
4224
4225 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4226 {
4227 struct intel_shared_dpll *pll;
4228 enum intel_dpll_id i;
4229
4230 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4231 pll = &dev_priv->shared_dplls[i];
4232
4233 WARN_ON(pll->new_config == &pll->config);
4234
4235 kfree(pll->new_config);
4236 pll->new_config = NULL;
4237 }
4238 }
4239
4240 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4241 {
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 int dslreg = PIPEDSL(pipe);
4244 u32 temp;
4245
4246 temp = I915_READ(dslreg);
4247 udelay(500);
4248 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4249 if (wait_for(I915_READ(dslreg) != temp, 5))
4250 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4251 }
4252 }
4253
4254 static void skylake_pfit_enable(struct intel_crtc *crtc)
4255 {
4256 struct drm_device *dev = crtc->base.dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 int pipe = crtc->pipe;
4259
4260 if (crtc->config->pch_pfit.enabled) {
4261 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4262 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4263 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4264 }
4265 }
4266
4267 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4268 {
4269 struct drm_device *dev = crtc->base.dev;
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 int pipe = crtc->pipe;
4272
4273 if (crtc->config->pch_pfit.enabled) {
4274 /* Force use of hard-coded filter coefficients
4275 * as some pre-programmed values are broken,
4276 * e.g. x201.
4277 */
4278 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4279 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4280 PF_PIPE_SEL_IVB(pipe));
4281 else
4282 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4283 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4284 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4285 }
4286 }
4287
4288 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4289 {
4290 struct drm_device *dev = crtc->dev;
4291 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4292 struct drm_plane *plane;
4293 struct intel_plane *intel_plane;
4294
4295 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4296 intel_plane = to_intel_plane(plane);
4297 if (intel_plane->pipe == pipe)
4298 intel_plane_restore(&intel_plane->base);
4299 }
4300 }
4301
4302 /*
4303 * Disable a plane internally without actually modifying the plane's state.
4304 * This will allow us to easily restore the plane later by just reprogramming
4305 * its state.
4306 */
4307 static void disable_plane_internal(struct drm_plane *plane)
4308 {
4309 struct intel_plane *intel_plane = to_intel_plane(plane);
4310 struct drm_plane_state *state =
4311 plane->funcs->atomic_duplicate_state(plane);
4312 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4313
4314 intel_state->visible = false;
4315 intel_plane->commit_plane(plane, intel_state);
4316
4317 intel_plane_destroy_state(plane, state);
4318 }
4319
4320 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4321 {
4322 struct drm_device *dev = crtc->dev;
4323 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4324 struct drm_plane *plane;
4325 struct intel_plane *intel_plane;
4326
4327 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4328 intel_plane = to_intel_plane(plane);
4329 if (plane->fb && intel_plane->pipe == pipe)
4330 disable_plane_internal(plane);
4331 }
4332 }
4333
4334 void hsw_enable_ips(struct intel_crtc *crtc)
4335 {
4336 struct drm_device *dev = crtc->base.dev;
4337 struct drm_i915_private *dev_priv = dev->dev_private;
4338
4339 if (!crtc->config->ips_enabled)
4340 return;
4341
4342 /* We can only enable IPS after we enable a plane and wait for a vblank */
4343 intel_wait_for_vblank(dev, crtc->pipe);
4344
4345 assert_plane_enabled(dev_priv, crtc->plane);
4346 if (IS_BROADWELL(dev)) {
4347 mutex_lock(&dev_priv->rps.hw_lock);
4348 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4349 mutex_unlock(&dev_priv->rps.hw_lock);
4350 /* Quoting Art Runyan: "its not safe to expect any particular
4351 * value in IPS_CTL bit 31 after enabling IPS through the
4352 * mailbox." Moreover, the mailbox may return a bogus state,
4353 * so we need to just enable it and continue on.
4354 */
4355 } else {
4356 I915_WRITE(IPS_CTL, IPS_ENABLE);
4357 /* The bit only becomes 1 in the next vblank, so this wait here
4358 * is essentially intel_wait_for_vblank. If we don't have this
4359 * and don't wait for vblanks until the end of crtc_enable, then
4360 * the HW state readout code will complain that the expected
4361 * IPS_CTL value is not the one we read. */
4362 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4363 DRM_ERROR("Timed out waiting for IPS enable\n");
4364 }
4365 }
4366
4367 void hsw_disable_ips(struct intel_crtc *crtc)
4368 {
4369 struct drm_device *dev = crtc->base.dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371
4372 if (!crtc->config->ips_enabled)
4373 return;
4374
4375 assert_plane_enabled(dev_priv, crtc->plane);
4376 if (IS_BROADWELL(dev)) {
4377 mutex_lock(&dev_priv->rps.hw_lock);
4378 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4379 mutex_unlock(&dev_priv->rps.hw_lock);
4380 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4381 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4382 DRM_ERROR("Timed out waiting for IPS disable\n");
4383 } else {
4384 I915_WRITE(IPS_CTL, 0);
4385 POSTING_READ(IPS_CTL);
4386 }
4387
4388 /* We need to wait for a vblank before we can disable the plane. */
4389 intel_wait_for_vblank(dev, crtc->pipe);
4390 }
4391
4392 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4393 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4394 {
4395 struct drm_device *dev = crtc->dev;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398 enum pipe pipe = intel_crtc->pipe;
4399 int palreg = PALETTE(pipe);
4400 int i;
4401 bool reenable_ips = false;
4402
4403 /* The clocks have to be on to load the palette. */
4404 if (!crtc->state->enable || !intel_crtc->active)
4405 return;
4406
4407 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4408 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4409 assert_dsi_pll_enabled(dev_priv);
4410 else
4411 assert_pll_enabled(dev_priv, pipe);
4412 }
4413
4414 /* use legacy palette for Ironlake */
4415 if (!HAS_GMCH_DISPLAY(dev))
4416 palreg = LGC_PALETTE(pipe);
4417
4418 /* Workaround : Do not read or write the pipe palette/gamma data while
4419 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4420 */
4421 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4422 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4423 GAMMA_MODE_MODE_SPLIT)) {
4424 hsw_disable_ips(intel_crtc);
4425 reenable_ips = true;
4426 }
4427
4428 for (i = 0; i < 256; i++) {
4429 I915_WRITE(palreg + 4 * i,
4430 (intel_crtc->lut_r[i] << 16) |
4431 (intel_crtc->lut_g[i] << 8) |
4432 intel_crtc->lut_b[i]);
4433 }
4434
4435 if (reenable_ips)
4436 hsw_enable_ips(intel_crtc);
4437 }
4438
4439 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4440 {
4441 if (!enable && intel_crtc->overlay) {
4442 struct drm_device *dev = intel_crtc->base.dev;
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444
4445 mutex_lock(&dev->struct_mutex);
4446 dev_priv->mm.interruptible = false;
4447 (void) intel_overlay_switch_off(intel_crtc->overlay);
4448 dev_priv->mm.interruptible = true;
4449 mutex_unlock(&dev->struct_mutex);
4450 }
4451
4452 /* Let userspace switch the overlay on again. In most cases userspace
4453 * has to recompute where to put it anyway.
4454 */
4455 }
4456
4457 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4458 {
4459 struct drm_device *dev = crtc->dev;
4460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461 int pipe = intel_crtc->pipe;
4462
4463 intel_enable_primary_hw_plane(crtc->primary, crtc);
4464 intel_enable_sprite_planes(crtc);
4465 intel_crtc_update_cursor(crtc, true);
4466 intel_crtc_dpms_overlay(intel_crtc, true);
4467
4468 hsw_enable_ips(intel_crtc);
4469
4470 mutex_lock(&dev->struct_mutex);
4471 intel_fbc_update(dev);
4472 mutex_unlock(&dev->struct_mutex);
4473
4474 /*
4475 * FIXME: Once we grow proper nuclear flip support out of this we need
4476 * to compute the mask of flip planes precisely. For the time being
4477 * consider this a flip from a NULL plane.
4478 */
4479 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4480 }
4481
4482 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4483 {
4484 struct drm_device *dev = crtc->dev;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4487 int pipe = intel_crtc->pipe;
4488
4489 intel_crtc_wait_for_pending_flips(crtc);
4490
4491 if (dev_priv->fbc.crtc == intel_crtc)
4492 intel_fbc_disable(dev);
4493
4494 hsw_disable_ips(intel_crtc);
4495
4496 intel_crtc_dpms_overlay(intel_crtc, false);
4497 intel_crtc_update_cursor(crtc, false);
4498 intel_disable_sprite_planes(crtc);
4499 intel_disable_primary_hw_plane(crtc->primary, crtc);
4500
4501 /*
4502 * FIXME: Once we grow proper nuclear flip support out of this we need
4503 * to compute the mask of flip planes precisely. For the time being
4504 * consider this a flip to a NULL plane.
4505 */
4506 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4507 }
4508
4509 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4510 {
4511 struct drm_device *dev = crtc->dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4514 struct intel_encoder *encoder;
4515 int pipe = intel_crtc->pipe;
4516
4517 WARN_ON(!crtc->state->enable);
4518
4519 if (intel_crtc->active)
4520 return;
4521
4522 if (intel_crtc->config->has_pch_encoder)
4523 intel_prepare_shared_dpll(intel_crtc);
4524
4525 if (intel_crtc->config->has_dp_encoder)
4526 intel_dp_set_m_n(intel_crtc, M1_N1);
4527
4528 intel_set_pipe_timings(intel_crtc);
4529
4530 if (intel_crtc->config->has_pch_encoder) {
4531 intel_cpu_transcoder_set_m_n(intel_crtc,
4532 &intel_crtc->config->fdi_m_n, NULL);
4533 }
4534
4535 ironlake_set_pipeconf(crtc);
4536
4537 intel_crtc->active = true;
4538
4539 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4540 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4541
4542 for_each_encoder_on_crtc(dev, crtc, encoder)
4543 if (encoder->pre_enable)
4544 encoder->pre_enable(encoder);
4545
4546 if (intel_crtc->config->has_pch_encoder) {
4547 /* Note: FDI PLL enabling _must_ be done before we enable the
4548 * cpu pipes, hence this is separate from all the other fdi/pch
4549 * enabling. */
4550 ironlake_fdi_pll_enable(intel_crtc);
4551 } else {
4552 assert_fdi_tx_disabled(dev_priv, pipe);
4553 assert_fdi_rx_disabled(dev_priv, pipe);
4554 }
4555
4556 ironlake_pfit_enable(intel_crtc);
4557
4558 /*
4559 * On ILK+ LUT must be loaded before the pipe is running but with
4560 * clocks enabled
4561 */
4562 intel_crtc_load_lut(crtc);
4563
4564 intel_update_watermarks(crtc);
4565 intel_enable_pipe(intel_crtc);
4566
4567 if (intel_crtc->config->has_pch_encoder)
4568 ironlake_pch_enable(crtc);
4569
4570 assert_vblank_disabled(crtc);
4571 drm_crtc_vblank_on(crtc);
4572
4573 for_each_encoder_on_crtc(dev, crtc, encoder)
4574 encoder->enable(encoder);
4575
4576 if (HAS_PCH_CPT(dev))
4577 cpt_verify_modeset(dev, intel_crtc->pipe);
4578
4579 intel_crtc_enable_planes(crtc);
4580 }
4581
4582 /* IPS only exists on ULT machines and is tied to pipe A. */
4583 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4584 {
4585 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4586 }
4587
4588 /*
4589 * This implements the workaround described in the "notes" section of the mode
4590 * set sequence documentation. When going from no pipes or single pipe to
4591 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4592 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4593 */
4594 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4595 {
4596 struct drm_device *dev = crtc->base.dev;
4597 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4598
4599 /* We want to get the other_active_crtc only if there's only 1 other
4600 * active crtc. */
4601 for_each_intel_crtc(dev, crtc_it) {
4602 if (!crtc_it->active || crtc_it == crtc)
4603 continue;
4604
4605 if (other_active_crtc)
4606 return;
4607
4608 other_active_crtc = crtc_it;
4609 }
4610 if (!other_active_crtc)
4611 return;
4612
4613 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4614 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4615 }
4616
4617 static void haswell_crtc_enable(struct drm_crtc *crtc)
4618 {
4619 struct drm_device *dev = crtc->dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4622 struct intel_encoder *encoder;
4623 int pipe = intel_crtc->pipe;
4624
4625 WARN_ON(!crtc->state->enable);
4626
4627 if (intel_crtc->active)
4628 return;
4629
4630 if (intel_crtc_to_shared_dpll(intel_crtc))
4631 intel_enable_shared_dpll(intel_crtc);
4632
4633 if (intel_crtc->config->has_dp_encoder)
4634 intel_dp_set_m_n(intel_crtc, M1_N1);
4635
4636 intel_set_pipe_timings(intel_crtc);
4637
4638 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4639 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4640 intel_crtc->config->pixel_multiplier - 1);
4641 }
4642
4643 if (intel_crtc->config->has_pch_encoder) {
4644 intel_cpu_transcoder_set_m_n(intel_crtc,
4645 &intel_crtc->config->fdi_m_n, NULL);
4646 }
4647
4648 haswell_set_pipeconf(crtc);
4649
4650 intel_set_pipe_csc(crtc);
4651
4652 intel_crtc->active = true;
4653
4654 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4655 for_each_encoder_on_crtc(dev, crtc, encoder)
4656 if (encoder->pre_enable)
4657 encoder->pre_enable(encoder);
4658
4659 if (intel_crtc->config->has_pch_encoder) {
4660 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4661 true);
4662 dev_priv->display.fdi_link_train(crtc);
4663 }
4664
4665 intel_ddi_enable_pipe_clock(intel_crtc);
4666
4667 if (IS_SKYLAKE(dev))
4668 skylake_pfit_enable(intel_crtc);
4669 else
4670 ironlake_pfit_enable(intel_crtc);
4671
4672 /*
4673 * On ILK+ LUT must be loaded before the pipe is running but with
4674 * clocks enabled
4675 */
4676 intel_crtc_load_lut(crtc);
4677
4678 intel_ddi_set_pipe_settings(crtc);
4679 intel_ddi_enable_transcoder_func(crtc);
4680
4681 intel_update_watermarks(crtc);
4682 intel_enable_pipe(intel_crtc);
4683
4684 if (intel_crtc->config->has_pch_encoder)
4685 lpt_pch_enable(crtc);
4686
4687 if (intel_crtc->config->dp_encoder_is_mst)
4688 intel_ddi_set_vc_payload_alloc(crtc, true);
4689
4690 assert_vblank_disabled(crtc);
4691 drm_crtc_vblank_on(crtc);
4692
4693 for_each_encoder_on_crtc(dev, crtc, encoder) {
4694 encoder->enable(encoder);
4695 intel_opregion_notify_encoder(encoder, true);
4696 }
4697
4698 /* If we change the relative order between pipe/planes enabling, we need
4699 * to change the workaround. */
4700 haswell_mode_set_planes_workaround(intel_crtc);
4701 intel_crtc_enable_planes(crtc);
4702 }
4703
4704 static void skylake_pfit_disable(struct intel_crtc *crtc)
4705 {
4706 struct drm_device *dev = crtc->base.dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 int pipe = crtc->pipe;
4709
4710 /* To avoid upsetting the power well on haswell only disable the pfit if
4711 * it's in use. The hw state code will make sure we get this right. */
4712 if (crtc->config->pch_pfit.enabled) {
4713 I915_WRITE(PS_CTL(pipe), 0);
4714 I915_WRITE(PS_WIN_POS(pipe), 0);
4715 I915_WRITE(PS_WIN_SZ(pipe), 0);
4716 }
4717 }
4718
4719 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4720 {
4721 struct drm_device *dev = crtc->base.dev;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 int pipe = crtc->pipe;
4724
4725 /* To avoid upsetting the power well on haswell only disable the pfit if
4726 * it's in use. The hw state code will make sure we get this right. */
4727 if (crtc->config->pch_pfit.enabled) {
4728 I915_WRITE(PF_CTL(pipe), 0);
4729 I915_WRITE(PF_WIN_POS(pipe), 0);
4730 I915_WRITE(PF_WIN_SZ(pipe), 0);
4731 }
4732 }
4733
4734 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4735 {
4736 struct drm_device *dev = crtc->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 struct intel_encoder *encoder;
4740 int pipe = intel_crtc->pipe;
4741 u32 reg, temp;
4742
4743 if (!intel_crtc->active)
4744 return;
4745
4746 intel_crtc_disable_planes(crtc);
4747
4748 for_each_encoder_on_crtc(dev, crtc, encoder)
4749 encoder->disable(encoder);
4750
4751 drm_crtc_vblank_off(crtc);
4752 assert_vblank_disabled(crtc);
4753
4754 if (intel_crtc->config->has_pch_encoder)
4755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4756
4757 intel_disable_pipe(intel_crtc);
4758
4759 ironlake_pfit_disable(intel_crtc);
4760
4761 for_each_encoder_on_crtc(dev, crtc, encoder)
4762 if (encoder->post_disable)
4763 encoder->post_disable(encoder);
4764
4765 if (intel_crtc->config->has_pch_encoder) {
4766 ironlake_fdi_disable(crtc);
4767
4768 ironlake_disable_pch_transcoder(dev_priv, pipe);
4769
4770 if (HAS_PCH_CPT(dev)) {
4771 /* disable TRANS_DP_CTL */
4772 reg = TRANS_DP_CTL(pipe);
4773 temp = I915_READ(reg);
4774 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4775 TRANS_DP_PORT_SEL_MASK);
4776 temp |= TRANS_DP_PORT_SEL_NONE;
4777 I915_WRITE(reg, temp);
4778
4779 /* disable DPLL_SEL */
4780 temp = I915_READ(PCH_DPLL_SEL);
4781 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4782 I915_WRITE(PCH_DPLL_SEL, temp);
4783 }
4784
4785 /* disable PCH DPLL */
4786 intel_disable_shared_dpll(intel_crtc);
4787
4788 ironlake_fdi_pll_disable(intel_crtc);
4789 }
4790
4791 intel_crtc->active = false;
4792 intel_update_watermarks(crtc);
4793
4794 mutex_lock(&dev->struct_mutex);
4795 intel_fbc_update(dev);
4796 mutex_unlock(&dev->struct_mutex);
4797 }
4798
4799 static void haswell_crtc_disable(struct drm_crtc *crtc)
4800 {
4801 struct drm_device *dev = crtc->dev;
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4804 struct intel_encoder *encoder;
4805 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4806
4807 if (!intel_crtc->active)
4808 return;
4809
4810 intel_crtc_disable_planes(crtc);
4811
4812 for_each_encoder_on_crtc(dev, crtc, encoder) {
4813 intel_opregion_notify_encoder(encoder, false);
4814 encoder->disable(encoder);
4815 }
4816
4817 drm_crtc_vblank_off(crtc);
4818 assert_vblank_disabled(crtc);
4819
4820 if (intel_crtc->config->has_pch_encoder)
4821 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4822 false);
4823 intel_disable_pipe(intel_crtc);
4824
4825 if (intel_crtc->config->dp_encoder_is_mst)
4826 intel_ddi_set_vc_payload_alloc(crtc, false);
4827
4828 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4829
4830 if (IS_SKYLAKE(dev))
4831 skylake_pfit_disable(intel_crtc);
4832 else
4833 ironlake_pfit_disable(intel_crtc);
4834
4835 intel_ddi_disable_pipe_clock(intel_crtc);
4836
4837 if (intel_crtc->config->has_pch_encoder) {
4838 lpt_disable_pch_transcoder(dev_priv);
4839 intel_ddi_fdi_disable(crtc);
4840 }
4841
4842 for_each_encoder_on_crtc(dev, crtc, encoder)
4843 if (encoder->post_disable)
4844 encoder->post_disable(encoder);
4845
4846 intel_crtc->active = false;
4847 intel_update_watermarks(crtc);
4848
4849 mutex_lock(&dev->struct_mutex);
4850 intel_fbc_update(dev);
4851 mutex_unlock(&dev->struct_mutex);
4852
4853 if (intel_crtc_to_shared_dpll(intel_crtc))
4854 intel_disable_shared_dpll(intel_crtc);
4855 }
4856
4857 static void ironlake_crtc_off(struct drm_crtc *crtc)
4858 {
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860 intel_put_shared_dpll(intel_crtc);
4861 }
4862
4863
4864 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4865 {
4866 struct drm_device *dev = crtc->base.dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 struct intel_crtc_state *pipe_config = crtc->config;
4869
4870 if (!pipe_config->gmch_pfit.control)
4871 return;
4872
4873 /*
4874 * The panel fitter should only be adjusted whilst the pipe is disabled,
4875 * according to register description and PRM.
4876 */
4877 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4878 assert_pipe_disabled(dev_priv, crtc->pipe);
4879
4880 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4881 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4882
4883 /* Border color in case we don't scale up to the full screen. Black by
4884 * default, change to something else for debugging. */
4885 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4886 }
4887
4888 static enum intel_display_power_domain port_to_power_domain(enum port port)
4889 {
4890 switch (port) {
4891 case PORT_A:
4892 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4893 case PORT_B:
4894 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4895 case PORT_C:
4896 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4897 case PORT_D:
4898 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4899 default:
4900 WARN_ON_ONCE(1);
4901 return POWER_DOMAIN_PORT_OTHER;
4902 }
4903 }
4904
4905 #define for_each_power_domain(domain, mask) \
4906 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4907 if ((1 << (domain)) & (mask))
4908
4909 enum intel_display_power_domain
4910 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4911 {
4912 struct drm_device *dev = intel_encoder->base.dev;
4913 struct intel_digital_port *intel_dig_port;
4914
4915 switch (intel_encoder->type) {
4916 case INTEL_OUTPUT_UNKNOWN:
4917 /* Only DDI platforms should ever use this output type */
4918 WARN_ON_ONCE(!HAS_DDI(dev));
4919 case INTEL_OUTPUT_DISPLAYPORT:
4920 case INTEL_OUTPUT_HDMI:
4921 case INTEL_OUTPUT_EDP:
4922 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4923 return port_to_power_domain(intel_dig_port->port);
4924 case INTEL_OUTPUT_DP_MST:
4925 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4926 return port_to_power_domain(intel_dig_port->port);
4927 case INTEL_OUTPUT_ANALOG:
4928 return POWER_DOMAIN_PORT_CRT;
4929 case INTEL_OUTPUT_DSI:
4930 return POWER_DOMAIN_PORT_DSI;
4931 default:
4932 return POWER_DOMAIN_PORT_OTHER;
4933 }
4934 }
4935
4936 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4937 {
4938 struct drm_device *dev = crtc->dev;
4939 struct intel_encoder *intel_encoder;
4940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941 enum pipe pipe = intel_crtc->pipe;
4942 unsigned long mask;
4943 enum transcoder transcoder;
4944
4945 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4946
4947 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4948 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4949 if (intel_crtc->config->pch_pfit.enabled ||
4950 intel_crtc->config->pch_pfit.force_thru)
4951 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4952
4953 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4954 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4955
4956 return mask;
4957 }
4958
4959 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
4960 {
4961 struct drm_device *dev = state->dev;
4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4964 struct intel_crtc *crtc;
4965
4966 /*
4967 * First get all needed power domains, then put all unneeded, to avoid
4968 * any unnecessary toggling of the power wells.
4969 */
4970 for_each_intel_crtc(dev, crtc) {
4971 enum intel_display_power_domain domain;
4972
4973 if (!crtc->base.state->enable)
4974 continue;
4975
4976 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4977
4978 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4979 intel_display_power_get(dev_priv, domain);
4980 }
4981
4982 if (dev_priv->display.modeset_global_resources)
4983 dev_priv->display.modeset_global_resources(state);
4984
4985 for_each_intel_crtc(dev, crtc) {
4986 enum intel_display_power_domain domain;
4987
4988 for_each_power_domain(domain, crtc->enabled_power_domains)
4989 intel_display_power_put(dev_priv, domain);
4990
4991 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4992 }
4993
4994 intel_display_set_init_power(dev_priv, false);
4995 }
4996
4997 /* returns HPLL frequency in kHz */
4998 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4999 {
5000 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5001
5002 /* Obtain SKU information */
5003 mutex_lock(&dev_priv->dpio_lock);
5004 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5005 CCK_FUSE_HPLL_FREQ_MASK;
5006 mutex_unlock(&dev_priv->dpio_lock);
5007
5008 return vco_freq[hpll_freq] * 1000;
5009 }
5010
5011 static void vlv_update_cdclk(struct drm_device *dev)
5012 {
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014
5015 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5016 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5017 dev_priv->vlv_cdclk_freq);
5018
5019 /*
5020 * Program the gmbus_freq based on the cdclk frequency.
5021 * BSpec erroneously claims we should aim for 4MHz, but
5022 * in fact 1MHz is the correct frequency.
5023 */
5024 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
5025 }
5026
5027 /* Adjust CDclk dividers to allow high res or save power if possible */
5028 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5029 {
5030 struct drm_i915_private *dev_priv = dev->dev_private;
5031 u32 val, cmd;
5032
5033 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5034
5035 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5036 cmd = 2;
5037 else if (cdclk == 266667)
5038 cmd = 1;
5039 else
5040 cmd = 0;
5041
5042 mutex_lock(&dev_priv->rps.hw_lock);
5043 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5044 val &= ~DSPFREQGUAR_MASK;
5045 val |= (cmd << DSPFREQGUAR_SHIFT);
5046 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5047 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5048 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5049 50)) {
5050 DRM_ERROR("timed out waiting for CDclk change\n");
5051 }
5052 mutex_unlock(&dev_priv->rps.hw_lock);
5053
5054 if (cdclk == 400000) {
5055 u32 divider;
5056
5057 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5058
5059 mutex_lock(&dev_priv->dpio_lock);
5060 /* adjust cdclk divider */
5061 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5062 val &= ~DISPLAY_FREQUENCY_VALUES;
5063 val |= divider;
5064 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5065
5066 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5067 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5068 50))
5069 DRM_ERROR("timed out waiting for CDclk change\n");
5070 mutex_unlock(&dev_priv->dpio_lock);
5071 }
5072
5073 mutex_lock(&dev_priv->dpio_lock);
5074 /* adjust self-refresh exit latency value */
5075 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5076 val &= ~0x7f;
5077
5078 /*
5079 * For high bandwidth configs, we set a higher latency in the bunit
5080 * so that the core display fetch happens in time to avoid underruns.
5081 */
5082 if (cdclk == 400000)
5083 val |= 4500 / 250; /* 4.5 usec */
5084 else
5085 val |= 3000 / 250; /* 3.0 usec */
5086 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5087 mutex_unlock(&dev_priv->dpio_lock);
5088
5089 vlv_update_cdclk(dev);
5090 }
5091
5092 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5093 {
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 u32 val, cmd;
5096
5097 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5098
5099 switch (cdclk) {
5100 case 333333:
5101 case 320000:
5102 case 266667:
5103 case 200000:
5104 break;
5105 default:
5106 MISSING_CASE(cdclk);
5107 return;
5108 }
5109
5110 /*
5111 * Specs are full of misinformation, but testing on actual
5112 * hardware has shown that we just need to write the desired
5113 * CCK divider into the Punit register.
5114 */
5115 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5116
5117 mutex_lock(&dev_priv->rps.hw_lock);
5118 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5119 val &= ~DSPFREQGUAR_MASK_CHV;
5120 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5121 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5122 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5123 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5124 50)) {
5125 DRM_ERROR("timed out waiting for CDclk change\n");
5126 }
5127 mutex_unlock(&dev_priv->rps.hw_lock);
5128
5129 vlv_update_cdclk(dev);
5130 }
5131
5132 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5133 int max_pixclk)
5134 {
5135 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5136 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5137
5138 /*
5139 * Really only a few cases to deal with, as only 4 CDclks are supported:
5140 * 200MHz
5141 * 267MHz
5142 * 320/333MHz (depends on HPLL freq)
5143 * 400MHz (VLV only)
5144 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5145 * of the lower bin and adjust if needed.
5146 *
5147 * We seem to get an unstable or solid color picture at 200MHz.
5148 * Not sure what's wrong. For now use 200MHz only when all pipes
5149 * are off.
5150 */
5151 if (!IS_CHERRYVIEW(dev_priv) &&
5152 max_pixclk > freq_320*limit/100)
5153 return 400000;
5154 else if (max_pixclk > 266667*limit/100)
5155 return freq_320;
5156 else if (max_pixclk > 0)
5157 return 266667;
5158 else
5159 return 200000;
5160 }
5161
5162 /* compute the max pixel clock for new configuration */
5163 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5164 {
5165 struct drm_device *dev = dev_priv->dev;
5166 struct intel_crtc *intel_crtc;
5167 int max_pixclk = 0;
5168
5169 for_each_intel_crtc(dev, intel_crtc) {
5170 if (intel_crtc->new_enabled)
5171 max_pixclk = max(max_pixclk,
5172 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5173 }
5174
5175 return max_pixclk;
5176 }
5177
5178 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5179 unsigned *prepare_pipes)
5180 {
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct intel_crtc *intel_crtc;
5183 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5184
5185 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5186 dev_priv->vlv_cdclk_freq)
5187 return;
5188
5189 /* disable/enable all currently active pipes while we change cdclk */
5190 for_each_intel_crtc(dev, intel_crtc)
5191 if (intel_crtc->base.state->enable)
5192 *prepare_pipes |= (1 << intel_crtc->pipe);
5193 }
5194
5195 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5196 {
5197 unsigned int credits, default_credits;
5198
5199 if (IS_CHERRYVIEW(dev_priv))
5200 default_credits = PFI_CREDIT(12);
5201 else
5202 default_credits = PFI_CREDIT(8);
5203
5204 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5205 /* CHV suggested value is 31 or 63 */
5206 if (IS_CHERRYVIEW(dev_priv))
5207 credits = PFI_CREDIT_31;
5208 else
5209 credits = PFI_CREDIT(15);
5210 } else {
5211 credits = default_credits;
5212 }
5213
5214 /*
5215 * WA - write default credits before re-programming
5216 * FIXME: should we also set the resend bit here?
5217 */
5218 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5219 default_credits);
5220
5221 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5222 credits | PFI_CREDIT_RESEND);
5223
5224 /*
5225 * FIXME is this guaranteed to clear
5226 * immediately or should we poll for it?
5227 */
5228 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5229 }
5230
5231 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
5232 {
5233 struct drm_device *dev = state->dev;
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5236 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5237
5238 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5239 /*
5240 * FIXME: We can end up here with all power domains off, yet
5241 * with a CDCLK frequency other than the minimum. To account
5242 * for this take the PIPE-A power domain, which covers the HW
5243 * blocks needed for the following programming. This can be
5244 * removed once it's guaranteed that we get here either with
5245 * the minimum CDCLK set, or the required power domains
5246 * enabled.
5247 */
5248 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5249
5250 if (IS_CHERRYVIEW(dev))
5251 cherryview_set_cdclk(dev, req_cdclk);
5252 else
5253 valleyview_set_cdclk(dev, req_cdclk);
5254
5255 vlv_program_pfi_credits(dev_priv);
5256
5257 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5258 }
5259 }
5260
5261 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5262 {
5263 struct drm_device *dev = crtc->dev;
5264 struct drm_i915_private *dev_priv = to_i915(dev);
5265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5266 struct intel_encoder *encoder;
5267 int pipe = intel_crtc->pipe;
5268 bool is_dsi;
5269
5270 WARN_ON(!crtc->state->enable);
5271
5272 if (intel_crtc->active)
5273 return;
5274
5275 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5276
5277 if (!is_dsi) {
5278 if (IS_CHERRYVIEW(dev))
5279 chv_prepare_pll(intel_crtc, intel_crtc->config);
5280 else
5281 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5282 }
5283
5284 if (intel_crtc->config->has_dp_encoder)
5285 intel_dp_set_m_n(intel_crtc, M1_N1);
5286
5287 intel_set_pipe_timings(intel_crtc);
5288
5289 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5290 struct drm_i915_private *dev_priv = dev->dev_private;
5291
5292 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5293 I915_WRITE(CHV_CANVAS(pipe), 0);
5294 }
5295
5296 i9xx_set_pipeconf(intel_crtc);
5297
5298 intel_crtc->active = true;
5299
5300 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5301
5302 for_each_encoder_on_crtc(dev, crtc, encoder)
5303 if (encoder->pre_pll_enable)
5304 encoder->pre_pll_enable(encoder);
5305
5306 if (!is_dsi) {
5307 if (IS_CHERRYVIEW(dev))
5308 chv_enable_pll(intel_crtc, intel_crtc->config);
5309 else
5310 vlv_enable_pll(intel_crtc, intel_crtc->config);
5311 }
5312
5313 for_each_encoder_on_crtc(dev, crtc, encoder)
5314 if (encoder->pre_enable)
5315 encoder->pre_enable(encoder);
5316
5317 i9xx_pfit_enable(intel_crtc);
5318
5319 intel_crtc_load_lut(crtc);
5320
5321 intel_update_watermarks(crtc);
5322 intel_enable_pipe(intel_crtc);
5323
5324 assert_vblank_disabled(crtc);
5325 drm_crtc_vblank_on(crtc);
5326
5327 for_each_encoder_on_crtc(dev, crtc, encoder)
5328 encoder->enable(encoder);
5329
5330 intel_crtc_enable_planes(crtc);
5331
5332 /* Underruns don't raise interrupts, so check manually. */
5333 i9xx_check_fifo_underruns(dev_priv);
5334 }
5335
5336 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5337 {
5338 struct drm_device *dev = crtc->base.dev;
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340
5341 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5342 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5343 }
5344
5345 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5346 {
5347 struct drm_device *dev = crtc->dev;
5348 struct drm_i915_private *dev_priv = to_i915(dev);
5349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5350 struct intel_encoder *encoder;
5351 int pipe = intel_crtc->pipe;
5352
5353 WARN_ON(!crtc->state->enable);
5354
5355 if (intel_crtc->active)
5356 return;
5357
5358 i9xx_set_pll_dividers(intel_crtc);
5359
5360 if (intel_crtc->config->has_dp_encoder)
5361 intel_dp_set_m_n(intel_crtc, M1_N1);
5362
5363 intel_set_pipe_timings(intel_crtc);
5364
5365 i9xx_set_pipeconf(intel_crtc);
5366
5367 intel_crtc->active = true;
5368
5369 if (!IS_GEN2(dev))
5370 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5371
5372 for_each_encoder_on_crtc(dev, crtc, encoder)
5373 if (encoder->pre_enable)
5374 encoder->pre_enable(encoder);
5375
5376 i9xx_enable_pll(intel_crtc);
5377
5378 i9xx_pfit_enable(intel_crtc);
5379
5380 intel_crtc_load_lut(crtc);
5381
5382 intel_update_watermarks(crtc);
5383 intel_enable_pipe(intel_crtc);
5384
5385 assert_vblank_disabled(crtc);
5386 drm_crtc_vblank_on(crtc);
5387
5388 for_each_encoder_on_crtc(dev, crtc, encoder)
5389 encoder->enable(encoder);
5390
5391 intel_crtc_enable_planes(crtc);
5392
5393 /*
5394 * Gen2 reports pipe underruns whenever all planes are disabled.
5395 * So don't enable underrun reporting before at least some planes
5396 * are enabled.
5397 * FIXME: Need to fix the logic to work when we turn off all planes
5398 * but leave the pipe running.
5399 */
5400 if (IS_GEN2(dev))
5401 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5402
5403 /* Underruns don't raise interrupts, so check manually. */
5404 i9xx_check_fifo_underruns(dev_priv);
5405 }
5406
5407 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5408 {
5409 struct drm_device *dev = crtc->base.dev;
5410 struct drm_i915_private *dev_priv = dev->dev_private;
5411
5412 if (!crtc->config->gmch_pfit.control)
5413 return;
5414
5415 assert_pipe_disabled(dev_priv, crtc->pipe);
5416
5417 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5418 I915_READ(PFIT_CONTROL));
5419 I915_WRITE(PFIT_CONTROL, 0);
5420 }
5421
5422 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5423 {
5424 struct drm_device *dev = crtc->dev;
5425 struct drm_i915_private *dev_priv = dev->dev_private;
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427 struct intel_encoder *encoder;
5428 int pipe = intel_crtc->pipe;
5429
5430 if (!intel_crtc->active)
5431 return;
5432
5433 /*
5434 * Gen2 reports pipe underruns whenever all planes are disabled.
5435 * So diasble underrun reporting before all the planes get disabled.
5436 * FIXME: Need to fix the logic to work when we turn off all planes
5437 * but leave the pipe running.
5438 */
5439 if (IS_GEN2(dev))
5440 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5441
5442 /*
5443 * Vblank time updates from the shadow to live plane control register
5444 * are blocked if the memory self-refresh mode is active at that
5445 * moment. So to make sure the plane gets truly disabled, disable
5446 * first the self-refresh mode. The self-refresh enable bit in turn
5447 * will be checked/applied by the HW only at the next frame start
5448 * event which is after the vblank start event, so we need to have a
5449 * wait-for-vblank between disabling the plane and the pipe.
5450 */
5451 intel_set_memory_cxsr(dev_priv, false);
5452 intel_crtc_disable_planes(crtc);
5453
5454 /*
5455 * On gen2 planes are double buffered but the pipe isn't, so we must
5456 * wait for planes to fully turn off before disabling the pipe.
5457 * We also need to wait on all gmch platforms because of the
5458 * self-refresh mode constraint explained above.
5459 */
5460 intel_wait_for_vblank(dev, pipe);
5461
5462 for_each_encoder_on_crtc(dev, crtc, encoder)
5463 encoder->disable(encoder);
5464
5465 drm_crtc_vblank_off(crtc);
5466 assert_vblank_disabled(crtc);
5467
5468 intel_disable_pipe(intel_crtc);
5469
5470 i9xx_pfit_disable(intel_crtc);
5471
5472 for_each_encoder_on_crtc(dev, crtc, encoder)
5473 if (encoder->post_disable)
5474 encoder->post_disable(encoder);
5475
5476 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5477 if (IS_CHERRYVIEW(dev))
5478 chv_disable_pll(dev_priv, pipe);
5479 else if (IS_VALLEYVIEW(dev))
5480 vlv_disable_pll(dev_priv, pipe);
5481 else
5482 i9xx_disable_pll(intel_crtc);
5483 }
5484
5485 if (!IS_GEN2(dev))
5486 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5487
5488 intel_crtc->active = false;
5489 intel_update_watermarks(crtc);
5490
5491 mutex_lock(&dev->struct_mutex);
5492 intel_fbc_update(dev);
5493 mutex_unlock(&dev->struct_mutex);
5494 }
5495
5496 static void i9xx_crtc_off(struct drm_crtc *crtc)
5497 {
5498 }
5499
5500 /* Master function to enable/disable CRTC and corresponding power wells */
5501 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5502 {
5503 struct drm_device *dev = crtc->dev;
5504 struct drm_i915_private *dev_priv = dev->dev_private;
5505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5506 enum intel_display_power_domain domain;
5507 unsigned long domains;
5508
5509 if (enable) {
5510 if (!intel_crtc->active) {
5511 domains = get_crtc_power_domains(crtc);
5512 for_each_power_domain(domain, domains)
5513 intel_display_power_get(dev_priv, domain);
5514 intel_crtc->enabled_power_domains = domains;
5515
5516 dev_priv->display.crtc_enable(crtc);
5517 }
5518 } else {
5519 if (intel_crtc->active) {
5520 dev_priv->display.crtc_disable(crtc);
5521
5522 domains = intel_crtc->enabled_power_domains;
5523 for_each_power_domain(domain, domains)
5524 intel_display_power_put(dev_priv, domain);
5525 intel_crtc->enabled_power_domains = 0;
5526 }
5527 }
5528 }
5529
5530 /**
5531 * Sets the power management mode of the pipe and plane.
5532 */
5533 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5534 {
5535 struct drm_device *dev = crtc->dev;
5536 struct intel_encoder *intel_encoder;
5537 bool enable = false;
5538
5539 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5540 enable |= intel_encoder->connectors_active;
5541
5542 intel_crtc_control(crtc, enable);
5543 }
5544
5545 static void intel_crtc_disable(struct drm_crtc *crtc)
5546 {
5547 struct drm_device *dev = crtc->dev;
5548 struct drm_connector *connector;
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550
5551 /* crtc should still be enabled when we disable it. */
5552 WARN_ON(!crtc->state->enable);
5553
5554 dev_priv->display.crtc_disable(crtc);
5555 dev_priv->display.off(crtc);
5556
5557 crtc->primary->funcs->disable_plane(crtc->primary);
5558
5559 /* Update computed state. */
5560 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5561 if (!connector->encoder || !connector->encoder->crtc)
5562 continue;
5563
5564 if (connector->encoder->crtc != crtc)
5565 continue;
5566
5567 connector->dpms = DRM_MODE_DPMS_OFF;
5568 to_intel_encoder(connector->encoder)->connectors_active = false;
5569 }
5570 }
5571
5572 void intel_encoder_destroy(struct drm_encoder *encoder)
5573 {
5574 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5575
5576 drm_encoder_cleanup(encoder);
5577 kfree(intel_encoder);
5578 }
5579
5580 /* Simple dpms helper for encoders with just one connector, no cloning and only
5581 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5582 * state of the entire output pipe. */
5583 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5584 {
5585 if (mode == DRM_MODE_DPMS_ON) {
5586 encoder->connectors_active = true;
5587
5588 intel_crtc_update_dpms(encoder->base.crtc);
5589 } else {
5590 encoder->connectors_active = false;
5591
5592 intel_crtc_update_dpms(encoder->base.crtc);
5593 }
5594 }
5595
5596 /* Cross check the actual hw state with our own modeset state tracking (and it's
5597 * internal consistency). */
5598 static void intel_connector_check_state(struct intel_connector *connector)
5599 {
5600 if (connector->get_hw_state(connector)) {
5601 struct intel_encoder *encoder = connector->encoder;
5602 struct drm_crtc *crtc;
5603 bool encoder_enabled;
5604 enum pipe pipe;
5605
5606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5607 connector->base.base.id,
5608 connector->base.name);
5609
5610 /* there is no real hw state for MST connectors */
5611 if (connector->mst_port)
5612 return;
5613
5614 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5615 "wrong connector dpms state\n");
5616 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5617 "active connector not linked to encoder\n");
5618
5619 if (encoder) {
5620 I915_STATE_WARN(!encoder->connectors_active,
5621 "encoder->connectors_active not set\n");
5622
5623 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5624 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5625 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5626 return;
5627
5628 crtc = encoder->base.crtc;
5629
5630 I915_STATE_WARN(!crtc->state->enable,
5631 "crtc not enabled\n");
5632 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5633 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5634 "encoder active on the wrong pipe\n");
5635 }
5636 }
5637 }
5638
5639 /* Even simpler default implementation, if there's really no special case to
5640 * consider. */
5641 void intel_connector_dpms(struct drm_connector *connector, int mode)
5642 {
5643 /* All the simple cases only support two dpms states. */
5644 if (mode != DRM_MODE_DPMS_ON)
5645 mode = DRM_MODE_DPMS_OFF;
5646
5647 if (mode == connector->dpms)
5648 return;
5649
5650 connector->dpms = mode;
5651
5652 /* Only need to change hw state when actually enabled */
5653 if (connector->encoder)
5654 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5655
5656 intel_modeset_check_state(connector->dev);
5657 }
5658
5659 /* Simple connector->get_hw_state implementation for encoders that support only
5660 * one connector and no cloning and hence the encoder state determines the state
5661 * of the connector. */
5662 bool intel_connector_get_hw_state(struct intel_connector *connector)
5663 {
5664 enum pipe pipe = 0;
5665 struct intel_encoder *encoder = connector->encoder;
5666
5667 return encoder->get_hw_state(encoder, &pipe);
5668 }
5669
5670 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
5671 {
5672 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5673 return crtc_state->fdi_lanes;
5674
5675 return 0;
5676 }
5677
5678 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5679 struct intel_crtc_state *pipe_config)
5680 {
5681 struct drm_atomic_state *state = pipe_config->base.state;
5682 struct intel_crtc *other_crtc;
5683 struct intel_crtc_state *other_crtc_state;
5684
5685 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5686 pipe_name(pipe), pipe_config->fdi_lanes);
5687 if (pipe_config->fdi_lanes > 4) {
5688 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5689 pipe_name(pipe), pipe_config->fdi_lanes);
5690 return -EINVAL;
5691 }
5692
5693 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5694 if (pipe_config->fdi_lanes > 2) {
5695 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5696 pipe_config->fdi_lanes);
5697 return -EINVAL;
5698 } else {
5699 return 0;
5700 }
5701 }
5702
5703 if (INTEL_INFO(dev)->num_pipes == 2)
5704 return 0;
5705
5706 /* Ivybridge 3 pipe is really complicated */
5707 switch (pipe) {
5708 case PIPE_A:
5709 return 0;
5710 case PIPE_B:
5711 if (pipe_config->fdi_lanes <= 2)
5712 return 0;
5713
5714 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
5715 other_crtc_state =
5716 intel_atomic_get_crtc_state(state, other_crtc);
5717 if (IS_ERR(other_crtc_state))
5718 return PTR_ERR(other_crtc_state);
5719
5720 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
5721 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5722 pipe_name(pipe), pipe_config->fdi_lanes);
5723 return -EINVAL;
5724 }
5725 return 0;
5726 case PIPE_C:
5727 if (pipe_config->fdi_lanes > 2) {
5728 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5729 pipe_name(pipe), pipe_config->fdi_lanes);
5730 return -EINVAL;
5731 }
5732
5733 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
5734 other_crtc_state =
5735 intel_atomic_get_crtc_state(state, other_crtc);
5736 if (IS_ERR(other_crtc_state))
5737 return PTR_ERR(other_crtc_state);
5738
5739 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
5740 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5741 return -EINVAL;
5742 }
5743 return 0;
5744 default:
5745 BUG();
5746 }
5747 }
5748
5749 #define RETRY 1
5750 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5751 struct intel_crtc_state *pipe_config)
5752 {
5753 struct drm_device *dev = intel_crtc->base.dev;
5754 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5755 int lane, link_bw, fdi_dotclock, ret;
5756 bool needs_recompute = false;
5757
5758 retry:
5759 /* FDI is a binary signal running at ~2.7GHz, encoding
5760 * each output octet as 10 bits. The actual frequency
5761 * is stored as a divider into a 100MHz clock, and the
5762 * mode pixel clock is stored in units of 1KHz.
5763 * Hence the bw of each lane in terms of the mode signal
5764 * is:
5765 */
5766 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5767
5768 fdi_dotclock = adjusted_mode->crtc_clock;
5769
5770 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5771 pipe_config->pipe_bpp);
5772
5773 pipe_config->fdi_lanes = lane;
5774
5775 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5776 link_bw, &pipe_config->fdi_m_n);
5777
5778 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5779 intel_crtc->pipe, pipe_config);
5780 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
5781 pipe_config->pipe_bpp -= 2*3;
5782 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5783 pipe_config->pipe_bpp);
5784 needs_recompute = true;
5785 pipe_config->bw_constrained = true;
5786
5787 goto retry;
5788 }
5789
5790 if (needs_recompute)
5791 return RETRY;
5792
5793 return ret;
5794 }
5795
5796 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5797 struct intel_crtc_state *pipe_config)
5798 {
5799 pipe_config->ips_enabled = i915.enable_ips &&
5800 hsw_crtc_supports_ips(crtc) &&
5801 pipe_config->pipe_bpp <= 24;
5802 }
5803
5804 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5805 struct intel_crtc_state *pipe_config)
5806 {
5807 struct drm_device *dev = crtc->base.dev;
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5810
5811 /* FIXME should check pixel clock limits on all platforms */
5812 if (INTEL_INFO(dev)->gen < 4) {
5813 int clock_limit =
5814 dev_priv->display.get_display_clock_speed(dev);
5815
5816 /*
5817 * Enable pixel doubling when the dot clock
5818 * is > 90% of the (display) core speed.
5819 *
5820 * GDG double wide on either pipe,
5821 * otherwise pipe A only.
5822 */
5823 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5824 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5825 clock_limit *= 2;
5826 pipe_config->double_wide = true;
5827 }
5828
5829 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5830 return -EINVAL;
5831 }
5832
5833 /*
5834 * Pipe horizontal size must be even in:
5835 * - DVO ganged mode
5836 * - LVDS dual channel mode
5837 * - Double wide pipe
5838 */
5839 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
5840 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5841 pipe_config->pipe_src_w &= ~1;
5842
5843 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5844 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5845 */
5846 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5847 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5848 return -EINVAL;
5849
5850 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5851 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5852 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5853 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5854 * for lvds. */
5855 pipe_config->pipe_bpp = 8*3;
5856 }
5857
5858 if (HAS_IPS(dev))
5859 hsw_compute_ips_config(crtc, pipe_config);
5860
5861 if (pipe_config->has_pch_encoder)
5862 return ironlake_fdi_compute_config(crtc, pipe_config);
5863
5864 return 0;
5865 }
5866
5867 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5868 {
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 u32 val;
5871 int divider;
5872
5873 if (dev_priv->hpll_freq == 0)
5874 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5875
5876 mutex_lock(&dev_priv->dpio_lock);
5877 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5878 mutex_unlock(&dev_priv->dpio_lock);
5879
5880 divider = val & DISPLAY_FREQUENCY_VALUES;
5881
5882 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5883 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5884 "cdclk change in progress\n");
5885
5886 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5887 }
5888
5889 static int i945_get_display_clock_speed(struct drm_device *dev)
5890 {
5891 return 400000;
5892 }
5893
5894 static int i915_get_display_clock_speed(struct drm_device *dev)
5895 {
5896 return 333333;
5897 }
5898
5899 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5900 {
5901 return 200000;
5902 }
5903
5904 static int pnv_get_display_clock_speed(struct drm_device *dev)
5905 {
5906 u16 gcfgc = 0;
5907
5908 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5909
5910 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5911 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5912 return 266667;
5913 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5914 return 333333;
5915 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5916 return 444444;
5917 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5918 return 200000;
5919 default:
5920 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5921 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5922 return 133333;
5923 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5924 return 166667;
5925 }
5926 }
5927
5928 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5929 {
5930 u16 gcfgc = 0;
5931
5932 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5933
5934 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5935 return 133333;
5936 else {
5937 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5938 case GC_DISPLAY_CLOCK_333_MHZ:
5939 return 333333;
5940 default:
5941 case GC_DISPLAY_CLOCK_190_200_MHZ:
5942 return 190000;
5943 }
5944 }
5945 }
5946
5947 static int i865_get_display_clock_speed(struct drm_device *dev)
5948 {
5949 return 266667;
5950 }
5951
5952 static int i855_get_display_clock_speed(struct drm_device *dev)
5953 {
5954 u16 hpllcc = 0;
5955 /* Assume that the hardware is in the high speed state. This
5956 * should be the default.
5957 */
5958 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5959 case GC_CLOCK_133_200:
5960 case GC_CLOCK_100_200:
5961 return 200000;
5962 case GC_CLOCK_166_250:
5963 return 250000;
5964 case GC_CLOCK_100_133:
5965 return 133333;
5966 }
5967
5968 /* Shouldn't happen */
5969 return 0;
5970 }
5971
5972 static int i830_get_display_clock_speed(struct drm_device *dev)
5973 {
5974 return 133333;
5975 }
5976
5977 static void
5978 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5979 {
5980 while (*num > DATA_LINK_M_N_MASK ||
5981 *den > DATA_LINK_M_N_MASK) {
5982 *num >>= 1;
5983 *den >>= 1;
5984 }
5985 }
5986
5987 static void compute_m_n(unsigned int m, unsigned int n,
5988 uint32_t *ret_m, uint32_t *ret_n)
5989 {
5990 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5991 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5992 intel_reduce_m_n_ratio(ret_m, ret_n);
5993 }
5994
5995 void
5996 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5997 int pixel_clock, int link_clock,
5998 struct intel_link_m_n *m_n)
5999 {
6000 m_n->tu = 64;
6001
6002 compute_m_n(bits_per_pixel * pixel_clock,
6003 link_clock * nlanes * 8,
6004 &m_n->gmch_m, &m_n->gmch_n);
6005
6006 compute_m_n(pixel_clock, link_clock,
6007 &m_n->link_m, &m_n->link_n);
6008 }
6009
6010 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6011 {
6012 if (i915.panel_use_ssc >= 0)
6013 return i915.panel_use_ssc != 0;
6014 return dev_priv->vbt.lvds_use_ssc
6015 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6016 }
6017
6018 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6019 int num_connectors)
6020 {
6021 struct drm_device *dev = crtc_state->base.crtc->dev;
6022 struct drm_i915_private *dev_priv = dev->dev_private;
6023 int refclk;
6024
6025 WARN_ON(!crtc_state->base.state);
6026
6027 if (IS_VALLEYVIEW(dev)) {
6028 refclk = 100000;
6029 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6030 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6031 refclk = dev_priv->vbt.lvds_ssc_freq;
6032 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6033 } else if (!IS_GEN2(dev)) {
6034 refclk = 96000;
6035 } else {
6036 refclk = 48000;
6037 }
6038
6039 return refclk;
6040 }
6041
6042 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6043 {
6044 return (1 << dpll->n) << 16 | dpll->m2;
6045 }
6046
6047 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6048 {
6049 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6050 }
6051
6052 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6053 struct intel_crtc_state *crtc_state,
6054 intel_clock_t *reduced_clock)
6055 {
6056 struct drm_device *dev = crtc->base.dev;
6057 u32 fp, fp2 = 0;
6058
6059 if (IS_PINEVIEW(dev)) {
6060 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6061 if (reduced_clock)
6062 fp2 = pnv_dpll_compute_fp(reduced_clock);
6063 } else {
6064 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6065 if (reduced_clock)
6066 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6067 }
6068
6069 crtc_state->dpll_hw_state.fp0 = fp;
6070
6071 crtc->lowfreq_avail = false;
6072 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6073 reduced_clock) {
6074 crtc_state->dpll_hw_state.fp1 = fp2;
6075 crtc->lowfreq_avail = true;
6076 } else {
6077 crtc_state->dpll_hw_state.fp1 = fp;
6078 }
6079 }
6080
6081 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6082 pipe)
6083 {
6084 u32 reg_val;
6085
6086 /*
6087 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6088 * and set it to a reasonable value instead.
6089 */
6090 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6091 reg_val &= 0xffffff00;
6092 reg_val |= 0x00000030;
6093 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6094
6095 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6096 reg_val &= 0x8cffffff;
6097 reg_val = 0x8c000000;
6098 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6099
6100 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6101 reg_val &= 0xffffff00;
6102 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6103
6104 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6105 reg_val &= 0x00ffffff;
6106 reg_val |= 0xb0000000;
6107 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6108 }
6109
6110 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6111 struct intel_link_m_n *m_n)
6112 {
6113 struct drm_device *dev = crtc->base.dev;
6114 struct drm_i915_private *dev_priv = dev->dev_private;
6115 int pipe = crtc->pipe;
6116
6117 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6118 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6119 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6120 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6121 }
6122
6123 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6124 struct intel_link_m_n *m_n,
6125 struct intel_link_m_n *m2_n2)
6126 {
6127 struct drm_device *dev = crtc->base.dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129 int pipe = crtc->pipe;
6130 enum transcoder transcoder = crtc->config->cpu_transcoder;
6131
6132 if (INTEL_INFO(dev)->gen >= 5) {
6133 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6134 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6135 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6136 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6137 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6138 * for gen < 8) and if DRRS is supported (to make sure the
6139 * registers are not unnecessarily accessed).
6140 */
6141 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6142 crtc->config->has_drrs) {
6143 I915_WRITE(PIPE_DATA_M2(transcoder),
6144 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6145 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6146 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6147 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6148 }
6149 } else {
6150 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6151 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6152 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6153 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6154 }
6155 }
6156
6157 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6158 {
6159 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6160
6161 if (m_n == M1_N1) {
6162 dp_m_n = &crtc->config->dp_m_n;
6163 dp_m2_n2 = &crtc->config->dp_m2_n2;
6164 } else if (m_n == M2_N2) {
6165
6166 /*
6167 * M2_N2 registers are not supported. Hence m2_n2 divider value
6168 * needs to be programmed into M1_N1.
6169 */
6170 dp_m_n = &crtc->config->dp_m2_n2;
6171 } else {
6172 DRM_ERROR("Unsupported divider value\n");
6173 return;
6174 }
6175
6176 if (crtc->config->has_pch_encoder)
6177 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6178 else
6179 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6180 }
6181
6182 static void vlv_update_pll(struct intel_crtc *crtc,
6183 struct intel_crtc_state *pipe_config)
6184 {
6185 u32 dpll, dpll_md;
6186
6187 /*
6188 * Enable DPIO clock input. We should never disable the reference
6189 * clock for pipe B, since VGA hotplug / manual detection depends
6190 * on it.
6191 */
6192 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6193 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6194 /* We should never disable this, set it here for state tracking */
6195 if (crtc->pipe == PIPE_B)
6196 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6197 dpll |= DPLL_VCO_ENABLE;
6198 pipe_config->dpll_hw_state.dpll = dpll;
6199
6200 dpll_md = (pipe_config->pixel_multiplier - 1)
6201 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6202 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6203 }
6204
6205 static void vlv_prepare_pll(struct intel_crtc *crtc,
6206 const struct intel_crtc_state *pipe_config)
6207 {
6208 struct drm_device *dev = crtc->base.dev;
6209 struct drm_i915_private *dev_priv = dev->dev_private;
6210 int pipe = crtc->pipe;
6211 u32 mdiv;
6212 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6213 u32 coreclk, reg_val;
6214
6215 mutex_lock(&dev_priv->dpio_lock);
6216
6217 bestn = pipe_config->dpll.n;
6218 bestm1 = pipe_config->dpll.m1;
6219 bestm2 = pipe_config->dpll.m2;
6220 bestp1 = pipe_config->dpll.p1;
6221 bestp2 = pipe_config->dpll.p2;
6222
6223 /* See eDP HDMI DPIO driver vbios notes doc */
6224
6225 /* PLL B needs special handling */
6226 if (pipe == PIPE_B)
6227 vlv_pllb_recal_opamp(dev_priv, pipe);
6228
6229 /* Set up Tx target for periodic Rcomp update */
6230 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6231
6232 /* Disable target IRef on PLL */
6233 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6234 reg_val &= 0x00ffffff;
6235 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6236
6237 /* Disable fast lock */
6238 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6239
6240 /* Set idtafcrecal before PLL is enabled */
6241 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6242 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6243 mdiv |= ((bestn << DPIO_N_SHIFT));
6244 mdiv |= (1 << DPIO_K_SHIFT);
6245
6246 /*
6247 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6248 * but we don't support that).
6249 * Note: don't use the DAC post divider as it seems unstable.
6250 */
6251 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6252 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6253
6254 mdiv |= DPIO_ENABLE_CALIBRATION;
6255 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6256
6257 /* Set HBR and RBR LPF coefficients */
6258 if (pipe_config->port_clock == 162000 ||
6259 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6260 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6261 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6262 0x009f0003);
6263 else
6264 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6265 0x00d0000f);
6266
6267 if (pipe_config->has_dp_encoder) {
6268 /* Use SSC source */
6269 if (pipe == PIPE_A)
6270 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6271 0x0df40000);
6272 else
6273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6274 0x0df70000);
6275 } else { /* HDMI or VGA */
6276 /* Use bend source */
6277 if (pipe == PIPE_A)
6278 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6279 0x0df70000);
6280 else
6281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6282 0x0df40000);
6283 }
6284
6285 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6286 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6287 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6288 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6289 coreclk |= 0x01000000;
6290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6291
6292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6293 mutex_unlock(&dev_priv->dpio_lock);
6294 }
6295
6296 static void chv_update_pll(struct intel_crtc *crtc,
6297 struct intel_crtc_state *pipe_config)
6298 {
6299 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6300 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6301 DPLL_VCO_ENABLE;
6302 if (crtc->pipe != PIPE_A)
6303 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6304
6305 pipe_config->dpll_hw_state.dpll_md =
6306 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6307 }
6308
6309 static void chv_prepare_pll(struct intel_crtc *crtc,
6310 const struct intel_crtc_state *pipe_config)
6311 {
6312 struct drm_device *dev = crtc->base.dev;
6313 struct drm_i915_private *dev_priv = dev->dev_private;
6314 int pipe = crtc->pipe;
6315 int dpll_reg = DPLL(crtc->pipe);
6316 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6317 u32 loopfilter, tribuf_calcntr;
6318 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6319 u32 dpio_val;
6320 int vco;
6321
6322 bestn = pipe_config->dpll.n;
6323 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6324 bestm1 = pipe_config->dpll.m1;
6325 bestm2 = pipe_config->dpll.m2 >> 22;
6326 bestp1 = pipe_config->dpll.p1;
6327 bestp2 = pipe_config->dpll.p2;
6328 vco = pipe_config->dpll.vco;
6329 dpio_val = 0;
6330 loopfilter = 0;
6331
6332 /*
6333 * Enable Refclk and SSC
6334 */
6335 I915_WRITE(dpll_reg,
6336 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6337
6338 mutex_lock(&dev_priv->dpio_lock);
6339
6340 /* p1 and p2 divider */
6341 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6342 5 << DPIO_CHV_S1_DIV_SHIFT |
6343 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6344 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6345 1 << DPIO_CHV_K_DIV_SHIFT);
6346
6347 /* Feedback post-divider - m2 */
6348 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6349
6350 /* Feedback refclk divider - n and m1 */
6351 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6352 DPIO_CHV_M1_DIV_BY_2 |
6353 1 << DPIO_CHV_N_DIV_SHIFT);
6354
6355 /* M2 fraction division */
6356 if (bestm2_frac)
6357 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6358
6359 /* M2 fraction division enable */
6360 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6361 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6362 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6363 if (bestm2_frac)
6364 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6365 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6366
6367 /* Program digital lock detect threshold */
6368 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6369 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6370 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6371 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6372 if (!bestm2_frac)
6373 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6374 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6375
6376 /* Loop filter */
6377 if (vco == 5400000) {
6378 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6379 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6380 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6381 tribuf_calcntr = 0x9;
6382 } else if (vco <= 6200000) {
6383 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6384 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6385 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6386 tribuf_calcntr = 0x9;
6387 } else if (vco <= 6480000) {
6388 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6389 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6390 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6391 tribuf_calcntr = 0x8;
6392 } else {
6393 /* Not supported. Apply the same limits as in the max case */
6394 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6395 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6396 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6397 tribuf_calcntr = 0;
6398 }
6399 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6400
6401 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6402 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6403 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6404 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6405
6406 /* AFC Recal */
6407 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6408 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6409 DPIO_AFC_RECAL);
6410
6411 mutex_unlock(&dev_priv->dpio_lock);
6412 }
6413
6414 /**
6415 * vlv_force_pll_on - forcibly enable just the PLL
6416 * @dev_priv: i915 private structure
6417 * @pipe: pipe PLL to enable
6418 * @dpll: PLL configuration
6419 *
6420 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6421 * in cases where we need the PLL enabled even when @pipe is not going to
6422 * be enabled.
6423 */
6424 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6425 const struct dpll *dpll)
6426 {
6427 struct intel_crtc *crtc =
6428 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6429 struct intel_crtc_state pipe_config = {
6430 .base.crtc = &crtc->base,
6431 .pixel_multiplier = 1,
6432 .dpll = *dpll,
6433 };
6434
6435 if (IS_CHERRYVIEW(dev)) {
6436 chv_update_pll(crtc, &pipe_config);
6437 chv_prepare_pll(crtc, &pipe_config);
6438 chv_enable_pll(crtc, &pipe_config);
6439 } else {
6440 vlv_update_pll(crtc, &pipe_config);
6441 vlv_prepare_pll(crtc, &pipe_config);
6442 vlv_enable_pll(crtc, &pipe_config);
6443 }
6444 }
6445
6446 /**
6447 * vlv_force_pll_off - forcibly disable just the PLL
6448 * @dev_priv: i915 private structure
6449 * @pipe: pipe PLL to disable
6450 *
6451 * Disable the PLL for @pipe. To be used in cases where we need
6452 * the PLL enabled even when @pipe is not going to be enabled.
6453 */
6454 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6455 {
6456 if (IS_CHERRYVIEW(dev))
6457 chv_disable_pll(to_i915(dev), pipe);
6458 else
6459 vlv_disable_pll(to_i915(dev), pipe);
6460 }
6461
6462 static void i9xx_update_pll(struct intel_crtc *crtc,
6463 struct intel_crtc_state *crtc_state,
6464 intel_clock_t *reduced_clock,
6465 int num_connectors)
6466 {
6467 struct drm_device *dev = crtc->base.dev;
6468 struct drm_i915_private *dev_priv = dev->dev_private;
6469 u32 dpll;
6470 bool is_sdvo;
6471 struct dpll *clock = &crtc_state->dpll;
6472
6473 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6474
6475 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6476 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
6477
6478 dpll = DPLL_VGA_MODE_DIS;
6479
6480 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
6481 dpll |= DPLLB_MODE_LVDS;
6482 else
6483 dpll |= DPLLB_MODE_DAC_SERIAL;
6484
6485 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6486 dpll |= (crtc_state->pixel_multiplier - 1)
6487 << SDVO_MULTIPLIER_SHIFT_HIRES;
6488 }
6489
6490 if (is_sdvo)
6491 dpll |= DPLL_SDVO_HIGH_SPEED;
6492
6493 if (crtc_state->has_dp_encoder)
6494 dpll |= DPLL_SDVO_HIGH_SPEED;
6495
6496 /* compute bitmask from p1 value */
6497 if (IS_PINEVIEW(dev))
6498 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6499 else {
6500 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6501 if (IS_G4X(dev) && reduced_clock)
6502 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6503 }
6504 switch (clock->p2) {
6505 case 5:
6506 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6507 break;
6508 case 7:
6509 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6510 break;
6511 case 10:
6512 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6513 break;
6514 case 14:
6515 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6516 break;
6517 }
6518 if (INTEL_INFO(dev)->gen >= 4)
6519 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6520
6521 if (crtc_state->sdvo_tv_clock)
6522 dpll |= PLL_REF_INPUT_TVCLKINBC;
6523 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6524 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6525 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6526 else
6527 dpll |= PLL_REF_INPUT_DREFCLK;
6528
6529 dpll |= DPLL_VCO_ENABLE;
6530 crtc_state->dpll_hw_state.dpll = dpll;
6531
6532 if (INTEL_INFO(dev)->gen >= 4) {
6533 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6534 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6535 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6536 }
6537 }
6538
6539 static void i8xx_update_pll(struct intel_crtc *crtc,
6540 struct intel_crtc_state *crtc_state,
6541 intel_clock_t *reduced_clock,
6542 int num_connectors)
6543 {
6544 struct drm_device *dev = crtc->base.dev;
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6546 u32 dpll;
6547 struct dpll *clock = &crtc_state->dpll;
6548
6549 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6550
6551 dpll = DPLL_VGA_MODE_DIS;
6552
6553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6555 } else {
6556 if (clock->p1 == 2)
6557 dpll |= PLL_P1_DIVIDE_BY_TWO;
6558 else
6559 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6560 if (clock->p2 == 4)
6561 dpll |= PLL_P2_DIVIDE_BY_4;
6562 }
6563
6564 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
6565 dpll |= DPLL_DVO_2X_MODE;
6566
6567 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6568 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6569 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6570 else
6571 dpll |= PLL_REF_INPUT_DREFCLK;
6572
6573 dpll |= DPLL_VCO_ENABLE;
6574 crtc_state->dpll_hw_state.dpll = dpll;
6575 }
6576
6577 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6578 {
6579 struct drm_device *dev = intel_crtc->base.dev;
6580 struct drm_i915_private *dev_priv = dev->dev_private;
6581 enum pipe pipe = intel_crtc->pipe;
6582 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6583 struct drm_display_mode *adjusted_mode =
6584 &intel_crtc->config->base.adjusted_mode;
6585 uint32_t crtc_vtotal, crtc_vblank_end;
6586 int vsyncshift = 0;
6587
6588 /* We need to be careful not to changed the adjusted mode, for otherwise
6589 * the hw state checker will get angry at the mismatch. */
6590 crtc_vtotal = adjusted_mode->crtc_vtotal;
6591 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6592
6593 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6594 /* the chip adds 2 halflines automatically */
6595 crtc_vtotal -= 1;
6596 crtc_vblank_end -= 1;
6597
6598 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6599 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6600 else
6601 vsyncshift = adjusted_mode->crtc_hsync_start -
6602 adjusted_mode->crtc_htotal / 2;
6603 if (vsyncshift < 0)
6604 vsyncshift += adjusted_mode->crtc_htotal;
6605 }
6606
6607 if (INTEL_INFO(dev)->gen > 3)
6608 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6609
6610 I915_WRITE(HTOTAL(cpu_transcoder),
6611 (adjusted_mode->crtc_hdisplay - 1) |
6612 ((adjusted_mode->crtc_htotal - 1) << 16));
6613 I915_WRITE(HBLANK(cpu_transcoder),
6614 (adjusted_mode->crtc_hblank_start - 1) |
6615 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6616 I915_WRITE(HSYNC(cpu_transcoder),
6617 (adjusted_mode->crtc_hsync_start - 1) |
6618 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6619
6620 I915_WRITE(VTOTAL(cpu_transcoder),
6621 (adjusted_mode->crtc_vdisplay - 1) |
6622 ((crtc_vtotal - 1) << 16));
6623 I915_WRITE(VBLANK(cpu_transcoder),
6624 (adjusted_mode->crtc_vblank_start - 1) |
6625 ((crtc_vblank_end - 1) << 16));
6626 I915_WRITE(VSYNC(cpu_transcoder),
6627 (adjusted_mode->crtc_vsync_start - 1) |
6628 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6629
6630 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6631 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6632 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6633 * bits. */
6634 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6635 (pipe == PIPE_B || pipe == PIPE_C))
6636 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6637
6638 /* pipesrc controls the size that is scaled from, which should
6639 * always be the user's requested size.
6640 */
6641 I915_WRITE(PIPESRC(pipe),
6642 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6643 (intel_crtc->config->pipe_src_h - 1));
6644 }
6645
6646 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6647 struct intel_crtc_state *pipe_config)
6648 {
6649 struct drm_device *dev = crtc->base.dev;
6650 struct drm_i915_private *dev_priv = dev->dev_private;
6651 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6652 uint32_t tmp;
6653
6654 tmp = I915_READ(HTOTAL(cpu_transcoder));
6655 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6656 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6657 tmp = I915_READ(HBLANK(cpu_transcoder));
6658 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6659 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6660 tmp = I915_READ(HSYNC(cpu_transcoder));
6661 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6662 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6663
6664 tmp = I915_READ(VTOTAL(cpu_transcoder));
6665 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6666 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6667 tmp = I915_READ(VBLANK(cpu_transcoder));
6668 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6669 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6670 tmp = I915_READ(VSYNC(cpu_transcoder));
6671 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6672 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6673
6674 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6675 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6676 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6677 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6678 }
6679
6680 tmp = I915_READ(PIPESRC(crtc->pipe));
6681 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6682 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6683
6684 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6685 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6686 }
6687
6688 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6689 struct intel_crtc_state *pipe_config)
6690 {
6691 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6692 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6693 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6694 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6695
6696 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6697 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6698 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6699 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6700
6701 mode->flags = pipe_config->base.adjusted_mode.flags;
6702
6703 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6704 mode->flags |= pipe_config->base.adjusted_mode.flags;
6705 }
6706
6707 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6708 {
6709 struct drm_device *dev = intel_crtc->base.dev;
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6711 uint32_t pipeconf;
6712
6713 pipeconf = 0;
6714
6715 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6716 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6717 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6718
6719 if (intel_crtc->config->double_wide)
6720 pipeconf |= PIPECONF_DOUBLE_WIDE;
6721
6722 /* only g4x and later have fancy bpc/dither controls */
6723 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6724 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6725 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6726 pipeconf |= PIPECONF_DITHER_EN |
6727 PIPECONF_DITHER_TYPE_SP;
6728
6729 switch (intel_crtc->config->pipe_bpp) {
6730 case 18:
6731 pipeconf |= PIPECONF_6BPC;
6732 break;
6733 case 24:
6734 pipeconf |= PIPECONF_8BPC;
6735 break;
6736 case 30:
6737 pipeconf |= PIPECONF_10BPC;
6738 break;
6739 default:
6740 /* Case prevented by intel_choose_pipe_bpp_dither. */
6741 BUG();
6742 }
6743 }
6744
6745 if (HAS_PIPE_CXSR(dev)) {
6746 if (intel_crtc->lowfreq_avail) {
6747 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6748 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6749 } else {
6750 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6751 }
6752 }
6753
6754 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6755 if (INTEL_INFO(dev)->gen < 4 ||
6756 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6757 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6758 else
6759 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6760 } else
6761 pipeconf |= PIPECONF_PROGRESSIVE;
6762
6763 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6764 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6765
6766 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6767 POSTING_READ(PIPECONF(intel_crtc->pipe));
6768 }
6769
6770 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6771 struct intel_crtc_state *crtc_state)
6772 {
6773 struct drm_device *dev = crtc->base.dev;
6774 struct drm_i915_private *dev_priv = dev->dev_private;
6775 int refclk, num_connectors = 0;
6776 intel_clock_t clock, reduced_clock;
6777 bool ok, has_reduced_clock = false;
6778 bool is_lvds = false, is_dsi = false;
6779 struct intel_encoder *encoder;
6780 const intel_limit_t *limit;
6781 struct drm_atomic_state *state = crtc_state->base.state;
6782 struct drm_connector_state *connector_state;
6783 int i;
6784
6785 for (i = 0; i < state->num_connector; i++) {
6786 if (!state->connectors[i])
6787 continue;
6788
6789 connector_state = state->connector_states[i];
6790 if (connector_state->crtc != &crtc->base)
6791 continue;
6792
6793 encoder = to_intel_encoder(connector_state->best_encoder);
6794
6795 switch (encoder->type) {
6796 case INTEL_OUTPUT_LVDS:
6797 is_lvds = true;
6798 break;
6799 case INTEL_OUTPUT_DSI:
6800 is_dsi = true;
6801 break;
6802 default:
6803 break;
6804 }
6805
6806 num_connectors++;
6807 }
6808
6809 if (is_dsi)
6810 return 0;
6811
6812 if (!crtc_state->clock_set) {
6813 refclk = i9xx_get_refclk(crtc_state, num_connectors);
6814
6815 /*
6816 * Returns a set of divisors for the desired target clock with
6817 * the given refclk, or FALSE. The returned values represent
6818 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6819 * 2) / p1 / p2.
6820 */
6821 limit = intel_limit(crtc_state, refclk);
6822 ok = dev_priv->display.find_dpll(limit, crtc_state,
6823 crtc_state->port_clock,
6824 refclk, NULL, &clock);
6825 if (!ok) {
6826 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6827 return -EINVAL;
6828 }
6829
6830 if (is_lvds && dev_priv->lvds_downclock_avail) {
6831 /*
6832 * Ensure we match the reduced clock's P to the target
6833 * clock. If the clocks don't match, we can't switch
6834 * the display clock by using the FP0/FP1. In such case
6835 * we will disable the LVDS downclock feature.
6836 */
6837 has_reduced_clock =
6838 dev_priv->display.find_dpll(limit, crtc_state,
6839 dev_priv->lvds_downclock,
6840 refclk, &clock,
6841 &reduced_clock);
6842 }
6843 /* Compat-code for transition, will disappear. */
6844 crtc_state->dpll.n = clock.n;
6845 crtc_state->dpll.m1 = clock.m1;
6846 crtc_state->dpll.m2 = clock.m2;
6847 crtc_state->dpll.p1 = clock.p1;
6848 crtc_state->dpll.p2 = clock.p2;
6849 }
6850
6851 if (IS_GEN2(dev)) {
6852 i8xx_update_pll(crtc, crtc_state,
6853 has_reduced_clock ? &reduced_clock : NULL,
6854 num_connectors);
6855 } else if (IS_CHERRYVIEW(dev)) {
6856 chv_update_pll(crtc, crtc_state);
6857 } else if (IS_VALLEYVIEW(dev)) {
6858 vlv_update_pll(crtc, crtc_state);
6859 } else {
6860 i9xx_update_pll(crtc, crtc_state,
6861 has_reduced_clock ? &reduced_clock : NULL,
6862 num_connectors);
6863 }
6864
6865 return 0;
6866 }
6867
6868 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6869 struct intel_crtc_state *pipe_config)
6870 {
6871 struct drm_device *dev = crtc->base.dev;
6872 struct drm_i915_private *dev_priv = dev->dev_private;
6873 uint32_t tmp;
6874
6875 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6876 return;
6877
6878 tmp = I915_READ(PFIT_CONTROL);
6879 if (!(tmp & PFIT_ENABLE))
6880 return;
6881
6882 /* Check whether the pfit is attached to our pipe. */
6883 if (INTEL_INFO(dev)->gen < 4) {
6884 if (crtc->pipe != PIPE_B)
6885 return;
6886 } else {
6887 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6888 return;
6889 }
6890
6891 pipe_config->gmch_pfit.control = tmp;
6892 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6893 if (INTEL_INFO(dev)->gen < 5)
6894 pipe_config->gmch_pfit.lvds_border_bits =
6895 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6896 }
6897
6898 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6899 struct intel_crtc_state *pipe_config)
6900 {
6901 struct drm_device *dev = crtc->base.dev;
6902 struct drm_i915_private *dev_priv = dev->dev_private;
6903 int pipe = pipe_config->cpu_transcoder;
6904 intel_clock_t clock;
6905 u32 mdiv;
6906 int refclk = 100000;
6907
6908 /* In case of MIPI DPLL will not even be used */
6909 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6910 return;
6911
6912 mutex_lock(&dev_priv->dpio_lock);
6913 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6914 mutex_unlock(&dev_priv->dpio_lock);
6915
6916 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6917 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6918 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6919 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6920 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6921
6922 vlv_clock(refclk, &clock);
6923
6924 /* clock.dot is the fast clock */
6925 pipe_config->port_clock = clock.dot / 5;
6926 }
6927
6928 static void
6929 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6930 struct intel_initial_plane_config *plane_config)
6931 {
6932 struct drm_device *dev = crtc->base.dev;
6933 struct drm_i915_private *dev_priv = dev->dev_private;
6934 u32 val, base, offset;
6935 int pipe = crtc->pipe, plane = crtc->plane;
6936 int fourcc, pixel_format;
6937 unsigned int aligned_height;
6938 struct drm_framebuffer *fb;
6939 struct intel_framebuffer *intel_fb;
6940
6941 val = I915_READ(DSPCNTR(plane));
6942 if (!(val & DISPLAY_PLANE_ENABLE))
6943 return;
6944
6945 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6946 if (!intel_fb) {
6947 DRM_DEBUG_KMS("failed to alloc fb\n");
6948 return;
6949 }
6950
6951 fb = &intel_fb->base;
6952
6953 if (INTEL_INFO(dev)->gen >= 4) {
6954 if (val & DISPPLANE_TILED) {
6955 plane_config->tiling = I915_TILING_X;
6956 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6957 }
6958 }
6959
6960 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6961 fourcc = i9xx_format_to_fourcc(pixel_format);
6962 fb->pixel_format = fourcc;
6963 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6964
6965 if (INTEL_INFO(dev)->gen >= 4) {
6966 if (plane_config->tiling)
6967 offset = I915_READ(DSPTILEOFF(plane));
6968 else
6969 offset = I915_READ(DSPLINOFF(plane));
6970 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6971 } else {
6972 base = I915_READ(DSPADDR(plane));
6973 }
6974 plane_config->base = base;
6975
6976 val = I915_READ(PIPESRC(pipe));
6977 fb->width = ((val >> 16) & 0xfff) + 1;
6978 fb->height = ((val >> 0) & 0xfff) + 1;
6979
6980 val = I915_READ(DSPSTRIDE(pipe));
6981 fb->pitches[0] = val & 0xffffffc0;
6982
6983 aligned_height = intel_fb_align_height(dev, fb->height,
6984 fb->pixel_format,
6985 fb->modifier[0]);
6986
6987 plane_config->size = fb->pitches[0] * aligned_height;
6988
6989 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6990 pipe_name(pipe), plane, fb->width, fb->height,
6991 fb->bits_per_pixel, base, fb->pitches[0],
6992 plane_config->size);
6993
6994 plane_config->fb = intel_fb;
6995 }
6996
6997 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6998 struct intel_crtc_state *pipe_config)
6999 {
7000 struct drm_device *dev = crtc->base.dev;
7001 struct drm_i915_private *dev_priv = dev->dev_private;
7002 int pipe = pipe_config->cpu_transcoder;
7003 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7004 intel_clock_t clock;
7005 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7006 int refclk = 100000;
7007
7008 mutex_lock(&dev_priv->dpio_lock);
7009 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7010 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7011 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7012 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7013 mutex_unlock(&dev_priv->dpio_lock);
7014
7015 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7016 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7017 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7018 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7019 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7020
7021 chv_clock(refclk, &clock);
7022
7023 /* clock.dot is the fast clock */
7024 pipe_config->port_clock = clock.dot / 5;
7025 }
7026
7027 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7028 struct intel_crtc_state *pipe_config)
7029 {
7030 struct drm_device *dev = crtc->base.dev;
7031 struct drm_i915_private *dev_priv = dev->dev_private;
7032 uint32_t tmp;
7033
7034 if (!intel_display_power_is_enabled(dev_priv,
7035 POWER_DOMAIN_PIPE(crtc->pipe)))
7036 return false;
7037
7038 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7039 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7040
7041 tmp = I915_READ(PIPECONF(crtc->pipe));
7042 if (!(tmp & PIPECONF_ENABLE))
7043 return false;
7044
7045 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7046 switch (tmp & PIPECONF_BPC_MASK) {
7047 case PIPECONF_6BPC:
7048 pipe_config->pipe_bpp = 18;
7049 break;
7050 case PIPECONF_8BPC:
7051 pipe_config->pipe_bpp = 24;
7052 break;
7053 case PIPECONF_10BPC:
7054 pipe_config->pipe_bpp = 30;
7055 break;
7056 default:
7057 break;
7058 }
7059 }
7060
7061 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7062 pipe_config->limited_color_range = true;
7063
7064 if (INTEL_INFO(dev)->gen < 4)
7065 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7066
7067 intel_get_pipe_timings(crtc, pipe_config);
7068
7069 i9xx_get_pfit_config(crtc, pipe_config);
7070
7071 if (INTEL_INFO(dev)->gen >= 4) {
7072 tmp = I915_READ(DPLL_MD(crtc->pipe));
7073 pipe_config->pixel_multiplier =
7074 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7075 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7076 pipe_config->dpll_hw_state.dpll_md = tmp;
7077 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7078 tmp = I915_READ(DPLL(crtc->pipe));
7079 pipe_config->pixel_multiplier =
7080 ((tmp & SDVO_MULTIPLIER_MASK)
7081 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7082 } else {
7083 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7084 * port and will be fixed up in the encoder->get_config
7085 * function. */
7086 pipe_config->pixel_multiplier = 1;
7087 }
7088 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7089 if (!IS_VALLEYVIEW(dev)) {
7090 /*
7091 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7092 * on 830. Filter it out here so that we don't
7093 * report errors due to that.
7094 */
7095 if (IS_I830(dev))
7096 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7097
7098 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7099 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7100 } else {
7101 /* Mask out read-only status bits. */
7102 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7103 DPLL_PORTC_READY_MASK |
7104 DPLL_PORTB_READY_MASK);
7105 }
7106
7107 if (IS_CHERRYVIEW(dev))
7108 chv_crtc_clock_get(crtc, pipe_config);
7109 else if (IS_VALLEYVIEW(dev))
7110 vlv_crtc_clock_get(crtc, pipe_config);
7111 else
7112 i9xx_crtc_clock_get(crtc, pipe_config);
7113
7114 return true;
7115 }
7116
7117 static void ironlake_init_pch_refclk(struct drm_device *dev)
7118 {
7119 struct drm_i915_private *dev_priv = dev->dev_private;
7120 struct intel_encoder *encoder;
7121 u32 val, final;
7122 bool has_lvds = false;
7123 bool has_cpu_edp = false;
7124 bool has_panel = false;
7125 bool has_ck505 = false;
7126 bool can_ssc = false;
7127
7128 /* We need to take the global config into account */
7129 for_each_intel_encoder(dev, encoder) {
7130 switch (encoder->type) {
7131 case INTEL_OUTPUT_LVDS:
7132 has_panel = true;
7133 has_lvds = true;
7134 break;
7135 case INTEL_OUTPUT_EDP:
7136 has_panel = true;
7137 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7138 has_cpu_edp = true;
7139 break;
7140 default:
7141 break;
7142 }
7143 }
7144
7145 if (HAS_PCH_IBX(dev)) {
7146 has_ck505 = dev_priv->vbt.display_clock_mode;
7147 can_ssc = has_ck505;
7148 } else {
7149 has_ck505 = false;
7150 can_ssc = true;
7151 }
7152
7153 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7154 has_panel, has_lvds, has_ck505);
7155
7156 /* Ironlake: try to setup display ref clock before DPLL
7157 * enabling. This is only under driver's control after
7158 * PCH B stepping, previous chipset stepping should be
7159 * ignoring this setting.
7160 */
7161 val = I915_READ(PCH_DREF_CONTROL);
7162
7163 /* As we must carefully and slowly disable/enable each source in turn,
7164 * compute the final state we want first and check if we need to
7165 * make any changes at all.
7166 */
7167 final = val;
7168 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7169 if (has_ck505)
7170 final |= DREF_NONSPREAD_CK505_ENABLE;
7171 else
7172 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7173
7174 final &= ~DREF_SSC_SOURCE_MASK;
7175 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7176 final &= ~DREF_SSC1_ENABLE;
7177
7178 if (has_panel) {
7179 final |= DREF_SSC_SOURCE_ENABLE;
7180
7181 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7182 final |= DREF_SSC1_ENABLE;
7183
7184 if (has_cpu_edp) {
7185 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7186 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7187 else
7188 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7189 } else
7190 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7191 } else {
7192 final |= DREF_SSC_SOURCE_DISABLE;
7193 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7194 }
7195
7196 if (final == val)
7197 return;
7198
7199 /* Always enable nonspread source */
7200 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7201
7202 if (has_ck505)
7203 val |= DREF_NONSPREAD_CK505_ENABLE;
7204 else
7205 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7206
7207 if (has_panel) {
7208 val &= ~DREF_SSC_SOURCE_MASK;
7209 val |= DREF_SSC_SOURCE_ENABLE;
7210
7211 /* SSC must be turned on before enabling the CPU output */
7212 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7213 DRM_DEBUG_KMS("Using SSC on panel\n");
7214 val |= DREF_SSC1_ENABLE;
7215 } else
7216 val &= ~DREF_SSC1_ENABLE;
7217
7218 /* Get SSC going before enabling the outputs */
7219 I915_WRITE(PCH_DREF_CONTROL, val);
7220 POSTING_READ(PCH_DREF_CONTROL);
7221 udelay(200);
7222
7223 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7224
7225 /* Enable CPU source on CPU attached eDP */
7226 if (has_cpu_edp) {
7227 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7228 DRM_DEBUG_KMS("Using SSC on eDP\n");
7229 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7230 } else
7231 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7232 } else
7233 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7234
7235 I915_WRITE(PCH_DREF_CONTROL, val);
7236 POSTING_READ(PCH_DREF_CONTROL);
7237 udelay(200);
7238 } else {
7239 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7240
7241 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7242
7243 /* Turn off CPU output */
7244 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7245
7246 I915_WRITE(PCH_DREF_CONTROL, val);
7247 POSTING_READ(PCH_DREF_CONTROL);
7248 udelay(200);
7249
7250 /* Turn off the SSC source */
7251 val &= ~DREF_SSC_SOURCE_MASK;
7252 val |= DREF_SSC_SOURCE_DISABLE;
7253
7254 /* Turn off SSC1 */
7255 val &= ~DREF_SSC1_ENABLE;
7256
7257 I915_WRITE(PCH_DREF_CONTROL, val);
7258 POSTING_READ(PCH_DREF_CONTROL);
7259 udelay(200);
7260 }
7261
7262 BUG_ON(val != final);
7263 }
7264
7265 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7266 {
7267 uint32_t tmp;
7268
7269 tmp = I915_READ(SOUTH_CHICKEN2);
7270 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7271 I915_WRITE(SOUTH_CHICKEN2, tmp);
7272
7273 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7274 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7275 DRM_ERROR("FDI mPHY reset assert timeout\n");
7276
7277 tmp = I915_READ(SOUTH_CHICKEN2);
7278 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7279 I915_WRITE(SOUTH_CHICKEN2, tmp);
7280
7281 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7282 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7283 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7284 }
7285
7286 /* WaMPhyProgramming:hsw */
7287 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7288 {
7289 uint32_t tmp;
7290
7291 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7292 tmp &= ~(0xFF << 24);
7293 tmp |= (0x12 << 24);
7294 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7295
7296 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7297 tmp |= (1 << 11);
7298 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7299
7300 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7301 tmp |= (1 << 11);
7302 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7303
7304 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7305 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7306 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7307
7308 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7309 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7310 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7311
7312 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7313 tmp &= ~(7 << 13);
7314 tmp |= (5 << 13);
7315 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7316
7317 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7318 tmp &= ~(7 << 13);
7319 tmp |= (5 << 13);
7320 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7321
7322 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7323 tmp &= ~0xFF;
7324 tmp |= 0x1C;
7325 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7326
7327 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7328 tmp &= ~0xFF;
7329 tmp |= 0x1C;
7330 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7331
7332 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7333 tmp &= ~(0xFF << 16);
7334 tmp |= (0x1C << 16);
7335 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7336
7337 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7338 tmp &= ~(0xFF << 16);
7339 tmp |= (0x1C << 16);
7340 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7341
7342 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7343 tmp |= (1 << 27);
7344 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7345
7346 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7347 tmp |= (1 << 27);
7348 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7349
7350 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7351 tmp &= ~(0xF << 28);
7352 tmp |= (4 << 28);
7353 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7354
7355 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7356 tmp &= ~(0xF << 28);
7357 tmp |= (4 << 28);
7358 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7359 }
7360
7361 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7362 * Programming" based on the parameters passed:
7363 * - Sequence to enable CLKOUT_DP
7364 * - Sequence to enable CLKOUT_DP without spread
7365 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7366 */
7367 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7368 bool with_fdi)
7369 {
7370 struct drm_i915_private *dev_priv = dev->dev_private;
7371 uint32_t reg, tmp;
7372
7373 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7374 with_spread = true;
7375 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7376 with_fdi, "LP PCH doesn't have FDI\n"))
7377 with_fdi = false;
7378
7379 mutex_lock(&dev_priv->dpio_lock);
7380
7381 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7382 tmp &= ~SBI_SSCCTL_DISABLE;
7383 tmp |= SBI_SSCCTL_PATHALT;
7384 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7385
7386 udelay(24);
7387
7388 if (with_spread) {
7389 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7390 tmp &= ~SBI_SSCCTL_PATHALT;
7391 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7392
7393 if (with_fdi) {
7394 lpt_reset_fdi_mphy(dev_priv);
7395 lpt_program_fdi_mphy(dev_priv);
7396 }
7397 }
7398
7399 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7400 SBI_GEN0 : SBI_DBUFF0;
7401 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7402 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7403 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7404
7405 mutex_unlock(&dev_priv->dpio_lock);
7406 }
7407
7408 /* Sequence to disable CLKOUT_DP */
7409 static void lpt_disable_clkout_dp(struct drm_device *dev)
7410 {
7411 struct drm_i915_private *dev_priv = dev->dev_private;
7412 uint32_t reg, tmp;
7413
7414 mutex_lock(&dev_priv->dpio_lock);
7415
7416 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7417 SBI_GEN0 : SBI_DBUFF0;
7418 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7419 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7420 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7421
7422 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7423 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7424 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7425 tmp |= SBI_SSCCTL_PATHALT;
7426 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7427 udelay(32);
7428 }
7429 tmp |= SBI_SSCCTL_DISABLE;
7430 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7431 }
7432
7433 mutex_unlock(&dev_priv->dpio_lock);
7434 }
7435
7436 static void lpt_init_pch_refclk(struct drm_device *dev)
7437 {
7438 struct intel_encoder *encoder;
7439 bool has_vga = false;
7440
7441 for_each_intel_encoder(dev, encoder) {
7442 switch (encoder->type) {
7443 case INTEL_OUTPUT_ANALOG:
7444 has_vga = true;
7445 break;
7446 default:
7447 break;
7448 }
7449 }
7450
7451 if (has_vga)
7452 lpt_enable_clkout_dp(dev, true, true);
7453 else
7454 lpt_disable_clkout_dp(dev);
7455 }
7456
7457 /*
7458 * Initialize reference clocks when the driver loads
7459 */
7460 void intel_init_pch_refclk(struct drm_device *dev)
7461 {
7462 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7463 ironlake_init_pch_refclk(dev);
7464 else if (HAS_PCH_LPT(dev))
7465 lpt_init_pch_refclk(dev);
7466 }
7467
7468 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
7469 {
7470 struct drm_device *dev = crtc_state->base.crtc->dev;
7471 struct drm_i915_private *dev_priv = dev->dev_private;
7472 struct drm_atomic_state *state = crtc_state->base.state;
7473 struct drm_connector_state *connector_state;
7474 struct intel_encoder *encoder;
7475 int num_connectors = 0, i;
7476 bool is_lvds = false;
7477
7478 for (i = 0; i < state->num_connector; i++) {
7479 if (!state->connectors[i])
7480 continue;
7481
7482 connector_state = state->connector_states[i];
7483 if (connector_state->crtc != crtc_state->base.crtc)
7484 continue;
7485
7486 encoder = to_intel_encoder(connector_state->best_encoder);
7487
7488 switch (encoder->type) {
7489 case INTEL_OUTPUT_LVDS:
7490 is_lvds = true;
7491 break;
7492 default:
7493 break;
7494 }
7495 num_connectors++;
7496 }
7497
7498 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7499 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7500 dev_priv->vbt.lvds_ssc_freq);
7501 return dev_priv->vbt.lvds_ssc_freq;
7502 }
7503
7504 return 120000;
7505 }
7506
7507 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7508 {
7509 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7511 int pipe = intel_crtc->pipe;
7512 uint32_t val;
7513
7514 val = 0;
7515
7516 switch (intel_crtc->config->pipe_bpp) {
7517 case 18:
7518 val |= PIPECONF_6BPC;
7519 break;
7520 case 24:
7521 val |= PIPECONF_8BPC;
7522 break;
7523 case 30:
7524 val |= PIPECONF_10BPC;
7525 break;
7526 case 36:
7527 val |= PIPECONF_12BPC;
7528 break;
7529 default:
7530 /* Case prevented by intel_choose_pipe_bpp_dither. */
7531 BUG();
7532 }
7533
7534 if (intel_crtc->config->dither)
7535 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7536
7537 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7538 val |= PIPECONF_INTERLACED_ILK;
7539 else
7540 val |= PIPECONF_PROGRESSIVE;
7541
7542 if (intel_crtc->config->limited_color_range)
7543 val |= PIPECONF_COLOR_RANGE_SELECT;
7544
7545 I915_WRITE(PIPECONF(pipe), val);
7546 POSTING_READ(PIPECONF(pipe));
7547 }
7548
7549 /*
7550 * Set up the pipe CSC unit.
7551 *
7552 * Currently only full range RGB to limited range RGB conversion
7553 * is supported, but eventually this should handle various
7554 * RGB<->YCbCr scenarios as well.
7555 */
7556 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7557 {
7558 struct drm_device *dev = crtc->dev;
7559 struct drm_i915_private *dev_priv = dev->dev_private;
7560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7561 int pipe = intel_crtc->pipe;
7562 uint16_t coeff = 0x7800; /* 1.0 */
7563
7564 /*
7565 * TODO: Check what kind of values actually come out of the pipe
7566 * with these coeff/postoff values and adjust to get the best
7567 * accuracy. Perhaps we even need to take the bpc value into
7568 * consideration.
7569 */
7570
7571 if (intel_crtc->config->limited_color_range)
7572 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7573
7574 /*
7575 * GY/GU and RY/RU should be the other way around according
7576 * to BSpec, but reality doesn't agree. Just set them up in
7577 * a way that results in the correct picture.
7578 */
7579 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7580 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7581
7582 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7583 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7584
7585 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7586 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7587
7588 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7589 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7590 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7591
7592 if (INTEL_INFO(dev)->gen > 6) {
7593 uint16_t postoff = 0;
7594
7595 if (intel_crtc->config->limited_color_range)
7596 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7597
7598 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7599 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7600 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7601
7602 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7603 } else {
7604 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7605
7606 if (intel_crtc->config->limited_color_range)
7607 mode |= CSC_BLACK_SCREEN_OFFSET;
7608
7609 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7610 }
7611 }
7612
7613 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7614 {
7615 struct drm_device *dev = crtc->dev;
7616 struct drm_i915_private *dev_priv = dev->dev_private;
7617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7618 enum pipe pipe = intel_crtc->pipe;
7619 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7620 uint32_t val;
7621
7622 val = 0;
7623
7624 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7625 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7626
7627 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7628 val |= PIPECONF_INTERLACED_ILK;
7629 else
7630 val |= PIPECONF_PROGRESSIVE;
7631
7632 I915_WRITE(PIPECONF(cpu_transcoder), val);
7633 POSTING_READ(PIPECONF(cpu_transcoder));
7634
7635 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7636 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7637
7638 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7639 val = 0;
7640
7641 switch (intel_crtc->config->pipe_bpp) {
7642 case 18:
7643 val |= PIPEMISC_DITHER_6_BPC;
7644 break;
7645 case 24:
7646 val |= PIPEMISC_DITHER_8_BPC;
7647 break;
7648 case 30:
7649 val |= PIPEMISC_DITHER_10_BPC;
7650 break;
7651 case 36:
7652 val |= PIPEMISC_DITHER_12_BPC;
7653 break;
7654 default:
7655 /* Case prevented by pipe_config_set_bpp. */
7656 BUG();
7657 }
7658
7659 if (intel_crtc->config->dither)
7660 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7661
7662 I915_WRITE(PIPEMISC(pipe), val);
7663 }
7664 }
7665
7666 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7667 struct intel_crtc_state *crtc_state,
7668 intel_clock_t *clock,
7669 bool *has_reduced_clock,
7670 intel_clock_t *reduced_clock)
7671 {
7672 struct drm_device *dev = crtc->dev;
7673 struct drm_i915_private *dev_priv = dev->dev_private;
7674 int refclk;
7675 const intel_limit_t *limit;
7676 bool ret, is_lvds = false;
7677
7678 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
7679
7680 refclk = ironlake_get_refclk(crtc_state);
7681
7682 /*
7683 * Returns a set of divisors for the desired target clock with the given
7684 * refclk, or FALSE. The returned values represent the clock equation:
7685 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7686 */
7687 limit = intel_limit(crtc_state, refclk);
7688 ret = dev_priv->display.find_dpll(limit, crtc_state,
7689 crtc_state->port_clock,
7690 refclk, NULL, clock);
7691 if (!ret)
7692 return false;
7693
7694 if (is_lvds && dev_priv->lvds_downclock_avail) {
7695 /*
7696 * Ensure we match the reduced clock's P to the target clock.
7697 * If the clocks don't match, we can't switch the display clock
7698 * by using the FP0/FP1. In such case we will disable the LVDS
7699 * downclock feature.
7700 */
7701 *has_reduced_clock =
7702 dev_priv->display.find_dpll(limit, crtc_state,
7703 dev_priv->lvds_downclock,
7704 refclk, clock,
7705 reduced_clock);
7706 }
7707
7708 return true;
7709 }
7710
7711 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7712 {
7713 /*
7714 * Account for spread spectrum to avoid
7715 * oversubscribing the link. Max center spread
7716 * is 2.5%; use 5% for safety's sake.
7717 */
7718 u32 bps = target_clock * bpp * 21 / 20;
7719 return DIV_ROUND_UP(bps, link_bw * 8);
7720 }
7721
7722 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7723 {
7724 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7725 }
7726
7727 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7728 struct intel_crtc_state *crtc_state,
7729 u32 *fp,
7730 intel_clock_t *reduced_clock, u32 *fp2)
7731 {
7732 struct drm_crtc *crtc = &intel_crtc->base;
7733 struct drm_device *dev = crtc->dev;
7734 struct drm_i915_private *dev_priv = dev->dev_private;
7735 struct drm_atomic_state *state = crtc_state->base.state;
7736 struct drm_connector_state *connector_state;
7737 struct intel_encoder *encoder;
7738 uint32_t dpll;
7739 int factor, num_connectors = 0, i;
7740 bool is_lvds = false, is_sdvo = false;
7741
7742 for (i = 0; i < state->num_connector; i++) {
7743 if (!state->connectors[i])
7744 continue;
7745
7746 connector_state = state->connector_states[i];
7747 if (connector_state->crtc != crtc_state->base.crtc)
7748 continue;
7749
7750 encoder = to_intel_encoder(connector_state->best_encoder);
7751
7752 switch (encoder->type) {
7753 case INTEL_OUTPUT_LVDS:
7754 is_lvds = true;
7755 break;
7756 case INTEL_OUTPUT_SDVO:
7757 case INTEL_OUTPUT_HDMI:
7758 is_sdvo = true;
7759 break;
7760 default:
7761 break;
7762 }
7763
7764 num_connectors++;
7765 }
7766
7767 /* Enable autotuning of the PLL clock (if permissible) */
7768 factor = 21;
7769 if (is_lvds) {
7770 if ((intel_panel_use_ssc(dev_priv) &&
7771 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7772 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7773 factor = 25;
7774 } else if (crtc_state->sdvo_tv_clock)
7775 factor = 20;
7776
7777 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7778 *fp |= FP_CB_TUNE;
7779
7780 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7781 *fp2 |= FP_CB_TUNE;
7782
7783 dpll = 0;
7784
7785 if (is_lvds)
7786 dpll |= DPLLB_MODE_LVDS;
7787 else
7788 dpll |= DPLLB_MODE_DAC_SERIAL;
7789
7790 dpll |= (crtc_state->pixel_multiplier - 1)
7791 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7792
7793 if (is_sdvo)
7794 dpll |= DPLL_SDVO_HIGH_SPEED;
7795 if (crtc_state->has_dp_encoder)
7796 dpll |= DPLL_SDVO_HIGH_SPEED;
7797
7798 /* compute bitmask from p1 value */
7799 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7800 /* also FPA1 */
7801 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7802
7803 switch (crtc_state->dpll.p2) {
7804 case 5:
7805 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7806 break;
7807 case 7:
7808 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7809 break;
7810 case 10:
7811 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7812 break;
7813 case 14:
7814 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7815 break;
7816 }
7817
7818 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7819 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7820 else
7821 dpll |= PLL_REF_INPUT_DREFCLK;
7822
7823 return dpll | DPLL_VCO_ENABLE;
7824 }
7825
7826 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7827 struct intel_crtc_state *crtc_state)
7828 {
7829 struct drm_device *dev = crtc->base.dev;
7830 intel_clock_t clock, reduced_clock;
7831 u32 dpll = 0, fp = 0, fp2 = 0;
7832 bool ok, has_reduced_clock = false;
7833 bool is_lvds = false;
7834 struct intel_shared_dpll *pll;
7835
7836 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7837
7838 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7839 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7840
7841 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7842 &has_reduced_clock, &reduced_clock);
7843 if (!ok && !crtc_state->clock_set) {
7844 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7845 return -EINVAL;
7846 }
7847 /* Compat-code for transition, will disappear. */
7848 if (!crtc_state->clock_set) {
7849 crtc_state->dpll.n = clock.n;
7850 crtc_state->dpll.m1 = clock.m1;
7851 crtc_state->dpll.m2 = clock.m2;
7852 crtc_state->dpll.p1 = clock.p1;
7853 crtc_state->dpll.p2 = clock.p2;
7854 }
7855
7856 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7857 if (crtc_state->has_pch_encoder) {
7858 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7859 if (has_reduced_clock)
7860 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7861
7862 dpll = ironlake_compute_dpll(crtc, crtc_state,
7863 &fp, &reduced_clock,
7864 has_reduced_clock ? &fp2 : NULL);
7865
7866 crtc_state->dpll_hw_state.dpll = dpll;
7867 crtc_state->dpll_hw_state.fp0 = fp;
7868 if (has_reduced_clock)
7869 crtc_state->dpll_hw_state.fp1 = fp2;
7870 else
7871 crtc_state->dpll_hw_state.fp1 = fp;
7872
7873 pll = intel_get_shared_dpll(crtc, crtc_state);
7874 if (pll == NULL) {
7875 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7876 pipe_name(crtc->pipe));
7877 return -EINVAL;
7878 }
7879 }
7880
7881 if (is_lvds && has_reduced_clock)
7882 crtc->lowfreq_avail = true;
7883 else
7884 crtc->lowfreq_avail = false;
7885
7886 return 0;
7887 }
7888
7889 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7890 struct intel_link_m_n *m_n)
7891 {
7892 struct drm_device *dev = crtc->base.dev;
7893 struct drm_i915_private *dev_priv = dev->dev_private;
7894 enum pipe pipe = crtc->pipe;
7895
7896 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7897 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7898 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7899 & ~TU_SIZE_MASK;
7900 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7901 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7902 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7903 }
7904
7905 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7906 enum transcoder transcoder,
7907 struct intel_link_m_n *m_n,
7908 struct intel_link_m_n *m2_n2)
7909 {
7910 struct drm_device *dev = crtc->base.dev;
7911 struct drm_i915_private *dev_priv = dev->dev_private;
7912 enum pipe pipe = crtc->pipe;
7913
7914 if (INTEL_INFO(dev)->gen >= 5) {
7915 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7916 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7917 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7918 & ~TU_SIZE_MASK;
7919 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7920 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7921 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7922 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7923 * gen < 8) and if DRRS is supported (to make sure the
7924 * registers are not unnecessarily read).
7925 */
7926 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7927 crtc->config->has_drrs) {
7928 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7929 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7930 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7931 & ~TU_SIZE_MASK;
7932 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7933 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7934 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7935 }
7936 } else {
7937 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7938 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7939 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7940 & ~TU_SIZE_MASK;
7941 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7942 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7943 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7944 }
7945 }
7946
7947 void intel_dp_get_m_n(struct intel_crtc *crtc,
7948 struct intel_crtc_state *pipe_config)
7949 {
7950 if (pipe_config->has_pch_encoder)
7951 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7952 else
7953 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7954 &pipe_config->dp_m_n,
7955 &pipe_config->dp_m2_n2);
7956 }
7957
7958 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7959 struct intel_crtc_state *pipe_config)
7960 {
7961 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7962 &pipe_config->fdi_m_n, NULL);
7963 }
7964
7965 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7966 struct intel_crtc_state *pipe_config)
7967 {
7968 struct drm_device *dev = crtc->base.dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7970 uint32_t tmp;
7971
7972 tmp = I915_READ(PS_CTL(crtc->pipe));
7973
7974 if (tmp & PS_ENABLE) {
7975 pipe_config->pch_pfit.enabled = true;
7976 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7977 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7978 }
7979 }
7980
7981 static void
7982 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7983 struct intel_initial_plane_config *plane_config)
7984 {
7985 struct drm_device *dev = crtc->base.dev;
7986 struct drm_i915_private *dev_priv = dev->dev_private;
7987 u32 val, base, offset, stride_mult, tiling;
7988 int pipe = crtc->pipe;
7989 int fourcc, pixel_format;
7990 unsigned int aligned_height;
7991 struct drm_framebuffer *fb;
7992 struct intel_framebuffer *intel_fb;
7993
7994 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7995 if (!intel_fb) {
7996 DRM_DEBUG_KMS("failed to alloc fb\n");
7997 return;
7998 }
7999
8000 fb = &intel_fb->base;
8001
8002 val = I915_READ(PLANE_CTL(pipe, 0));
8003 if (!(val & PLANE_CTL_ENABLE))
8004 goto error;
8005
8006 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8007 fourcc = skl_format_to_fourcc(pixel_format,
8008 val & PLANE_CTL_ORDER_RGBX,
8009 val & PLANE_CTL_ALPHA_MASK);
8010 fb->pixel_format = fourcc;
8011 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8012
8013 tiling = val & PLANE_CTL_TILED_MASK;
8014 switch (tiling) {
8015 case PLANE_CTL_TILED_LINEAR:
8016 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8017 break;
8018 case PLANE_CTL_TILED_X:
8019 plane_config->tiling = I915_TILING_X;
8020 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8021 break;
8022 case PLANE_CTL_TILED_Y:
8023 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8024 break;
8025 case PLANE_CTL_TILED_YF:
8026 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8027 break;
8028 default:
8029 MISSING_CASE(tiling);
8030 goto error;
8031 }
8032
8033 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8034 plane_config->base = base;
8035
8036 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8037
8038 val = I915_READ(PLANE_SIZE(pipe, 0));
8039 fb->height = ((val >> 16) & 0xfff) + 1;
8040 fb->width = ((val >> 0) & 0x1fff) + 1;
8041
8042 val = I915_READ(PLANE_STRIDE(pipe, 0));
8043 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8044 fb->pixel_format);
8045 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8046
8047 aligned_height = intel_fb_align_height(dev, fb->height,
8048 fb->pixel_format,
8049 fb->modifier[0]);
8050
8051 plane_config->size = fb->pitches[0] * aligned_height;
8052
8053 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8054 pipe_name(pipe), fb->width, fb->height,
8055 fb->bits_per_pixel, base, fb->pitches[0],
8056 plane_config->size);
8057
8058 plane_config->fb = intel_fb;
8059 return;
8060
8061 error:
8062 kfree(fb);
8063 }
8064
8065 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8066 struct intel_crtc_state *pipe_config)
8067 {
8068 struct drm_device *dev = crtc->base.dev;
8069 struct drm_i915_private *dev_priv = dev->dev_private;
8070 uint32_t tmp;
8071
8072 tmp = I915_READ(PF_CTL(crtc->pipe));
8073
8074 if (tmp & PF_ENABLE) {
8075 pipe_config->pch_pfit.enabled = true;
8076 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8077 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8078
8079 /* We currently do not free assignements of panel fitters on
8080 * ivb/hsw (since we don't use the higher upscaling modes which
8081 * differentiates them) so just WARN about this case for now. */
8082 if (IS_GEN7(dev)) {
8083 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8084 PF_PIPE_SEL_IVB(crtc->pipe));
8085 }
8086 }
8087 }
8088
8089 static void
8090 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8091 struct intel_initial_plane_config *plane_config)
8092 {
8093 struct drm_device *dev = crtc->base.dev;
8094 struct drm_i915_private *dev_priv = dev->dev_private;
8095 u32 val, base, offset;
8096 int pipe = crtc->pipe;
8097 int fourcc, pixel_format;
8098 unsigned int aligned_height;
8099 struct drm_framebuffer *fb;
8100 struct intel_framebuffer *intel_fb;
8101
8102 val = I915_READ(DSPCNTR(pipe));
8103 if (!(val & DISPLAY_PLANE_ENABLE))
8104 return;
8105
8106 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8107 if (!intel_fb) {
8108 DRM_DEBUG_KMS("failed to alloc fb\n");
8109 return;
8110 }
8111
8112 fb = &intel_fb->base;
8113
8114 if (INTEL_INFO(dev)->gen >= 4) {
8115 if (val & DISPPLANE_TILED) {
8116 plane_config->tiling = I915_TILING_X;
8117 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8118 }
8119 }
8120
8121 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8122 fourcc = i9xx_format_to_fourcc(pixel_format);
8123 fb->pixel_format = fourcc;
8124 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8125
8126 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8127 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8128 offset = I915_READ(DSPOFFSET(pipe));
8129 } else {
8130 if (plane_config->tiling)
8131 offset = I915_READ(DSPTILEOFF(pipe));
8132 else
8133 offset = I915_READ(DSPLINOFF(pipe));
8134 }
8135 plane_config->base = base;
8136
8137 val = I915_READ(PIPESRC(pipe));
8138 fb->width = ((val >> 16) & 0xfff) + 1;
8139 fb->height = ((val >> 0) & 0xfff) + 1;
8140
8141 val = I915_READ(DSPSTRIDE(pipe));
8142 fb->pitches[0] = val & 0xffffffc0;
8143
8144 aligned_height = intel_fb_align_height(dev, fb->height,
8145 fb->pixel_format,
8146 fb->modifier[0]);
8147
8148 plane_config->size = fb->pitches[0] * aligned_height;
8149
8150 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8151 pipe_name(pipe), fb->width, fb->height,
8152 fb->bits_per_pixel, base, fb->pitches[0],
8153 plane_config->size);
8154
8155 plane_config->fb = intel_fb;
8156 }
8157
8158 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8159 struct intel_crtc_state *pipe_config)
8160 {
8161 struct drm_device *dev = crtc->base.dev;
8162 struct drm_i915_private *dev_priv = dev->dev_private;
8163 uint32_t tmp;
8164
8165 if (!intel_display_power_is_enabled(dev_priv,
8166 POWER_DOMAIN_PIPE(crtc->pipe)))
8167 return false;
8168
8169 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8170 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8171
8172 tmp = I915_READ(PIPECONF(crtc->pipe));
8173 if (!(tmp & PIPECONF_ENABLE))
8174 return false;
8175
8176 switch (tmp & PIPECONF_BPC_MASK) {
8177 case PIPECONF_6BPC:
8178 pipe_config->pipe_bpp = 18;
8179 break;
8180 case PIPECONF_8BPC:
8181 pipe_config->pipe_bpp = 24;
8182 break;
8183 case PIPECONF_10BPC:
8184 pipe_config->pipe_bpp = 30;
8185 break;
8186 case PIPECONF_12BPC:
8187 pipe_config->pipe_bpp = 36;
8188 break;
8189 default:
8190 break;
8191 }
8192
8193 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8194 pipe_config->limited_color_range = true;
8195
8196 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8197 struct intel_shared_dpll *pll;
8198
8199 pipe_config->has_pch_encoder = true;
8200
8201 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8202 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8203 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8204
8205 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8206
8207 if (HAS_PCH_IBX(dev_priv->dev)) {
8208 pipe_config->shared_dpll =
8209 (enum intel_dpll_id) crtc->pipe;
8210 } else {
8211 tmp = I915_READ(PCH_DPLL_SEL);
8212 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8213 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8214 else
8215 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8216 }
8217
8218 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8219
8220 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8221 &pipe_config->dpll_hw_state));
8222
8223 tmp = pipe_config->dpll_hw_state.dpll;
8224 pipe_config->pixel_multiplier =
8225 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8226 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8227
8228 ironlake_pch_clock_get(crtc, pipe_config);
8229 } else {
8230 pipe_config->pixel_multiplier = 1;
8231 }
8232
8233 intel_get_pipe_timings(crtc, pipe_config);
8234
8235 ironlake_get_pfit_config(crtc, pipe_config);
8236
8237 return true;
8238 }
8239
8240 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8241 {
8242 struct drm_device *dev = dev_priv->dev;
8243 struct intel_crtc *crtc;
8244
8245 for_each_intel_crtc(dev, crtc)
8246 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8247 pipe_name(crtc->pipe));
8248
8249 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8250 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8251 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8252 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8253 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8254 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8255 "CPU PWM1 enabled\n");
8256 if (IS_HASWELL(dev))
8257 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8258 "CPU PWM2 enabled\n");
8259 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8260 "PCH PWM1 enabled\n");
8261 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8262 "Utility pin enabled\n");
8263 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8264
8265 /*
8266 * In theory we can still leave IRQs enabled, as long as only the HPD
8267 * interrupts remain enabled. We used to check for that, but since it's
8268 * gen-specific and since we only disable LCPLL after we fully disable
8269 * the interrupts, the check below should be enough.
8270 */
8271 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8272 }
8273
8274 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8275 {
8276 struct drm_device *dev = dev_priv->dev;
8277
8278 if (IS_HASWELL(dev))
8279 return I915_READ(D_COMP_HSW);
8280 else
8281 return I915_READ(D_COMP_BDW);
8282 }
8283
8284 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8285 {
8286 struct drm_device *dev = dev_priv->dev;
8287
8288 if (IS_HASWELL(dev)) {
8289 mutex_lock(&dev_priv->rps.hw_lock);
8290 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8291 val))
8292 DRM_ERROR("Failed to write to D_COMP\n");
8293 mutex_unlock(&dev_priv->rps.hw_lock);
8294 } else {
8295 I915_WRITE(D_COMP_BDW, val);
8296 POSTING_READ(D_COMP_BDW);
8297 }
8298 }
8299
8300 /*
8301 * This function implements pieces of two sequences from BSpec:
8302 * - Sequence for display software to disable LCPLL
8303 * - Sequence for display software to allow package C8+
8304 * The steps implemented here are just the steps that actually touch the LCPLL
8305 * register. Callers should take care of disabling all the display engine
8306 * functions, doing the mode unset, fixing interrupts, etc.
8307 */
8308 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8309 bool switch_to_fclk, bool allow_power_down)
8310 {
8311 uint32_t val;
8312
8313 assert_can_disable_lcpll(dev_priv);
8314
8315 val = I915_READ(LCPLL_CTL);
8316
8317 if (switch_to_fclk) {
8318 val |= LCPLL_CD_SOURCE_FCLK;
8319 I915_WRITE(LCPLL_CTL, val);
8320
8321 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8322 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8323 DRM_ERROR("Switching to FCLK failed\n");
8324
8325 val = I915_READ(LCPLL_CTL);
8326 }
8327
8328 val |= LCPLL_PLL_DISABLE;
8329 I915_WRITE(LCPLL_CTL, val);
8330 POSTING_READ(LCPLL_CTL);
8331
8332 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8333 DRM_ERROR("LCPLL still locked\n");
8334
8335 val = hsw_read_dcomp(dev_priv);
8336 val |= D_COMP_COMP_DISABLE;
8337 hsw_write_dcomp(dev_priv, val);
8338 ndelay(100);
8339
8340 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8341 1))
8342 DRM_ERROR("D_COMP RCOMP still in progress\n");
8343
8344 if (allow_power_down) {
8345 val = I915_READ(LCPLL_CTL);
8346 val |= LCPLL_POWER_DOWN_ALLOW;
8347 I915_WRITE(LCPLL_CTL, val);
8348 POSTING_READ(LCPLL_CTL);
8349 }
8350 }
8351
8352 /*
8353 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8354 * source.
8355 */
8356 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8357 {
8358 uint32_t val;
8359
8360 val = I915_READ(LCPLL_CTL);
8361
8362 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8363 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8364 return;
8365
8366 /*
8367 * Make sure we're not on PC8 state before disabling PC8, otherwise
8368 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8369 */
8370 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8371
8372 if (val & LCPLL_POWER_DOWN_ALLOW) {
8373 val &= ~LCPLL_POWER_DOWN_ALLOW;
8374 I915_WRITE(LCPLL_CTL, val);
8375 POSTING_READ(LCPLL_CTL);
8376 }
8377
8378 val = hsw_read_dcomp(dev_priv);
8379 val |= D_COMP_COMP_FORCE;
8380 val &= ~D_COMP_COMP_DISABLE;
8381 hsw_write_dcomp(dev_priv, val);
8382
8383 val = I915_READ(LCPLL_CTL);
8384 val &= ~LCPLL_PLL_DISABLE;
8385 I915_WRITE(LCPLL_CTL, val);
8386
8387 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8388 DRM_ERROR("LCPLL not locked yet\n");
8389
8390 if (val & LCPLL_CD_SOURCE_FCLK) {
8391 val = I915_READ(LCPLL_CTL);
8392 val &= ~LCPLL_CD_SOURCE_FCLK;
8393 I915_WRITE(LCPLL_CTL, val);
8394
8395 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8396 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8397 DRM_ERROR("Switching back to LCPLL failed\n");
8398 }
8399
8400 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8401 }
8402
8403 /*
8404 * Package states C8 and deeper are really deep PC states that can only be
8405 * reached when all the devices on the system allow it, so even if the graphics
8406 * device allows PC8+, it doesn't mean the system will actually get to these
8407 * states. Our driver only allows PC8+ when going into runtime PM.
8408 *
8409 * The requirements for PC8+ are that all the outputs are disabled, the power
8410 * well is disabled and most interrupts are disabled, and these are also
8411 * requirements for runtime PM. When these conditions are met, we manually do
8412 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8413 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8414 * hang the machine.
8415 *
8416 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8417 * the state of some registers, so when we come back from PC8+ we need to
8418 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8419 * need to take care of the registers kept by RC6. Notice that this happens even
8420 * if we don't put the device in PCI D3 state (which is what currently happens
8421 * because of the runtime PM support).
8422 *
8423 * For more, read "Display Sequences for Package C8" on the hardware
8424 * documentation.
8425 */
8426 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8427 {
8428 struct drm_device *dev = dev_priv->dev;
8429 uint32_t val;
8430
8431 DRM_DEBUG_KMS("Enabling package C8+\n");
8432
8433 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8434 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8435 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8436 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8437 }
8438
8439 lpt_disable_clkout_dp(dev);
8440 hsw_disable_lcpll(dev_priv, true, true);
8441 }
8442
8443 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8444 {
8445 struct drm_device *dev = dev_priv->dev;
8446 uint32_t val;
8447
8448 DRM_DEBUG_KMS("Disabling package C8+\n");
8449
8450 hsw_restore_lcpll(dev_priv);
8451 lpt_init_pch_refclk(dev);
8452
8453 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8454 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8455 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8456 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8457 }
8458
8459 intel_prepare_ddi(dev);
8460 }
8461
8462 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8463 struct intel_crtc_state *crtc_state)
8464 {
8465 if (!intel_ddi_pll_select(crtc, crtc_state))
8466 return -EINVAL;
8467
8468 crtc->lowfreq_avail = false;
8469
8470 return 0;
8471 }
8472
8473 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8474 enum port port,
8475 struct intel_crtc_state *pipe_config)
8476 {
8477 u32 temp, dpll_ctl1;
8478
8479 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8480 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8481
8482 switch (pipe_config->ddi_pll_sel) {
8483 case SKL_DPLL0:
8484 /*
8485 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8486 * of the shared DPLL framework and thus needs to be read out
8487 * separately
8488 */
8489 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8490 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8491 break;
8492 case SKL_DPLL1:
8493 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8494 break;
8495 case SKL_DPLL2:
8496 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8497 break;
8498 case SKL_DPLL3:
8499 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8500 break;
8501 }
8502 }
8503
8504 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8505 enum port port,
8506 struct intel_crtc_state *pipe_config)
8507 {
8508 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8509
8510 switch (pipe_config->ddi_pll_sel) {
8511 case PORT_CLK_SEL_WRPLL1:
8512 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8513 break;
8514 case PORT_CLK_SEL_WRPLL2:
8515 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8516 break;
8517 }
8518 }
8519
8520 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8521 struct intel_crtc_state *pipe_config)
8522 {
8523 struct drm_device *dev = crtc->base.dev;
8524 struct drm_i915_private *dev_priv = dev->dev_private;
8525 struct intel_shared_dpll *pll;
8526 enum port port;
8527 uint32_t tmp;
8528
8529 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8530
8531 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8532
8533 if (IS_SKYLAKE(dev))
8534 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8535 else
8536 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8537
8538 if (pipe_config->shared_dpll >= 0) {
8539 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8540
8541 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8542 &pipe_config->dpll_hw_state));
8543 }
8544
8545 /*
8546 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8547 * DDI E. So just check whether this pipe is wired to DDI E and whether
8548 * the PCH transcoder is on.
8549 */
8550 if (INTEL_INFO(dev)->gen < 9 &&
8551 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8552 pipe_config->has_pch_encoder = true;
8553
8554 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8555 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8556 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8557
8558 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8559 }
8560 }
8561
8562 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8563 struct intel_crtc_state *pipe_config)
8564 {
8565 struct drm_device *dev = crtc->base.dev;
8566 struct drm_i915_private *dev_priv = dev->dev_private;
8567 enum intel_display_power_domain pfit_domain;
8568 uint32_t tmp;
8569
8570 if (!intel_display_power_is_enabled(dev_priv,
8571 POWER_DOMAIN_PIPE(crtc->pipe)))
8572 return false;
8573
8574 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8575 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8576
8577 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8578 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8579 enum pipe trans_edp_pipe;
8580 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8581 default:
8582 WARN(1, "unknown pipe linked to edp transcoder\n");
8583 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8584 case TRANS_DDI_EDP_INPUT_A_ON:
8585 trans_edp_pipe = PIPE_A;
8586 break;
8587 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8588 trans_edp_pipe = PIPE_B;
8589 break;
8590 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8591 trans_edp_pipe = PIPE_C;
8592 break;
8593 }
8594
8595 if (trans_edp_pipe == crtc->pipe)
8596 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8597 }
8598
8599 if (!intel_display_power_is_enabled(dev_priv,
8600 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8601 return false;
8602
8603 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8604 if (!(tmp & PIPECONF_ENABLE))
8605 return false;
8606
8607 haswell_get_ddi_port_state(crtc, pipe_config);
8608
8609 intel_get_pipe_timings(crtc, pipe_config);
8610
8611 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8612 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8613 if (IS_SKYLAKE(dev))
8614 skylake_get_pfit_config(crtc, pipe_config);
8615 else
8616 ironlake_get_pfit_config(crtc, pipe_config);
8617 }
8618
8619 if (IS_HASWELL(dev))
8620 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8621 (I915_READ(IPS_CTL) & IPS_ENABLE);
8622
8623 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8624 pipe_config->pixel_multiplier =
8625 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8626 } else {
8627 pipe_config->pixel_multiplier = 1;
8628 }
8629
8630 return true;
8631 }
8632
8633 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8634 {
8635 struct drm_device *dev = crtc->dev;
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8638 uint32_t cntl = 0, size = 0;
8639
8640 if (base) {
8641 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8642 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8643 unsigned int stride = roundup_pow_of_two(width) * 4;
8644
8645 switch (stride) {
8646 default:
8647 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8648 width, stride);
8649 stride = 256;
8650 /* fallthrough */
8651 case 256:
8652 case 512:
8653 case 1024:
8654 case 2048:
8655 break;
8656 }
8657
8658 cntl |= CURSOR_ENABLE |
8659 CURSOR_GAMMA_ENABLE |
8660 CURSOR_FORMAT_ARGB |
8661 CURSOR_STRIDE(stride);
8662
8663 size = (height << 12) | width;
8664 }
8665
8666 if (intel_crtc->cursor_cntl != 0 &&
8667 (intel_crtc->cursor_base != base ||
8668 intel_crtc->cursor_size != size ||
8669 intel_crtc->cursor_cntl != cntl)) {
8670 /* On these chipsets we can only modify the base/size/stride
8671 * whilst the cursor is disabled.
8672 */
8673 I915_WRITE(_CURACNTR, 0);
8674 POSTING_READ(_CURACNTR);
8675 intel_crtc->cursor_cntl = 0;
8676 }
8677
8678 if (intel_crtc->cursor_base != base) {
8679 I915_WRITE(_CURABASE, base);
8680 intel_crtc->cursor_base = base;
8681 }
8682
8683 if (intel_crtc->cursor_size != size) {
8684 I915_WRITE(CURSIZE, size);
8685 intel_crtc->cursor_size = size;
8686 }
8687
8688 if (intel_crtc->cursor_cntl != cntl) {
8689 I915_WRITE(_CURACNTR, cntl);
8690 POSTING_READ(_CURACNTR);
8691 intel_crtc->cursor_cntl = cntl;
8692 }
8693 }
8694
8695 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8696 {
8697 struct drm_device *dev = crtc->dev;
8698 struct drm_i915_private *dev_priv = dev->dev_private;
8699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8700 int pipe = intel_crtc->pipe;
8701 uint32_t cntl;
8702
8703 cntl = 0;
8704 if (base) {
8705 cntl = MCURSOR_GAMMA_ENABLE;
8706 switch (intel_crtc->base.cursor->state->crtc_w) {
8707 case 64:
8708 cntl |= CURSOR_MODE_64_ARGB_AX;
8709 break;
8710 case 128:
8711 cntl |= CURSOR_MODE_128_ARGB_AX;
8712 break;
8713 case 256:
8714 cntl |= CURSOR_MODE_256_ARGB_AX;
8715 break;
8716 default:
8717 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8718 return;
8719 }
8720 cntl |= pipe << 28; /* Connect to correct pipe */
8721
8722 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8723 cntl |= CURSOR_PIPE_CSC_ENABLE;
8724 }
8725
8726 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8727 cntl |= CURSOR_ROTATE_180;
8728
8729 if (intel_crtc->cursor_cntl != cntl) {
8730 I915_WRITE(CURCNTR(pipe), cntl);
8731 POSTING_READ(CURCNTR(pipe));
8732 intel_crtc->cursor_cntl = cntl;
8733 }
8734
8735 /* and commit changes on next vblank */
8736 I915_WRITE(CURBASE(pipe), base);
8737 POSTING_READ(CURBASE(pipe));
8738
8739 intel_crtc->cursor_base = base;
8740 }
8741
8742 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8743 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8744 bool on)
8745 {
8746 struct drm_device *dev = crtc->dev;
8747 struct drm_i915_private *dev_priv = dev->dev_private;
8748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8749 int pipe = intel_crtc->pipe;
8750 int x = crtc->cursor_x;
8751 int y = crtc->cursor_y;
8752 u32 base = 0, pos = 0;
8753
8754 if (on)
8755 base = intel_crtc->cursor_addr;
8756
8757 if (x >= intel_crtc->config->pipe_src_w)
8758 base = 0;
8759
8760 if (y >= intel_crtc->config->pipe_src_h)
8761 base = 0;
8762
8763 if (x < 0) {
8764 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8765 base = 0;
8766
8767 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8768 x = -x;
8769 }
8770 pos |= x << CURSOR_X_SHIFT;
8771
8772 if (y < 0) {
8773 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8774 base = 0;
8775
8776 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8777 y = -y;
8778 }
8779 pos |= y << CURSOR_Y_SHIFT;
8780
8781 if (base == 0 && intel_crtc->cursor_base == 0)
8782 return;
8783
8784 I915_WRITE(CURPOS(pipe), pos);
8785
8786 /* ILK+ do this automagically */
8787 if (HAS_GMCH_DISPLAY(dev) &&
8788 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8789 base += (intel_crtc->base.cursor->state->crtc_h *
8790 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8791 }
8792
8793 if (IS_845G(dev) || IS_I865G(dev))
8794 i845_update_cursor(crtc, base);
8795 else
8796 i9xx_update_cursor(crtc, base);
8797 }
8798
8799 static bool cursor_size_ok(struct drm_device *dev,
8800 uint32_t width, uint32_t height)
8801 {
8802 if (width == 0 || height == 0)
8803 return false;
8804
8805 /*
8806 * 845g/865g are special in that they are only limited by
8807 * the width of their cursors, the height is arbitrary up to
8808 * the precision of the register. Everything else requires
8809 * square cursors, limited to a few power-of-two sizes.
8810 */
8811 if (IS_845G(dev) || IS_I865G(dev)) {
8812 if ((width & 63) != 0)
8813 return false;
8814
8815 if (width > (IS_845G(dev) ? 64 : 512))
8816 return false;
8817
8818 if (height > 1023)
8819 return false;
8820 } else {
8821 switch (width | height) {
8822 case 256:
8823 case 128:
8824 if (IS_GEN2(dev))
8825 return false;
8826 case 64:
8827 break;
8828 default:
8829 return false;
8830 }
8831 }
8832
8833 return true;
8834 }
8835
8836 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8837 u16 *blue, uint32_t start, uint32_t size)
8838 {
8839 int end = (start + size > 256) ? 256 : start + size, i;
8840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8841
8842 for (i = start; i < end; i++) {
8843 intel_crtc->lut_r[i] = red[i] >> 8;
8844 intel_crtc->lut_g[i] = green[i] >> 8;
8845 intel_crtc->lut_b[i] = blue[i] >> 8;
8846 }
8847
8848 intel_crtc_load_lut(crtc);
8849 }
8850
8851 /* VESA 640x480x72Hz mode to set on the pipe */
8852 static struct drm_display_mode load_detect_mode = {
8853 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8854 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8855 };
8856
8857 struct drm_framebuffer *
8858 __intel_framebuffer_create(struct drm_device *dev,
8859 struct drm_mode_fb_cmd2 *mode_cmd,
8860 struct drm_i915_gem_object *obj)
8861 {
8862 struct intel_framebuffer *intel_fb;
8863 int ret;
8864
8865 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8866 if (!intel_fb) {
8867 drm_gem_object_unreference(&obj->base);
8868 return ERR_PTR(-ENOMEM);
8869 }
8870
8871 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8872 if (ret)
8873 goto err;
8874
8875 return &intel_fb->base;
8876 err:
8877 drm_gem_object_unreference(&obj->base);
8878 kfree(intel_fb);
8879
8880 return ERR_PTR(ret);
8881 }
8882
8883 static struct drm_framebuffer *
8884 intel_framebuffer_create(struct drm_device *dev,
8885 struct drm_mode_fb_cmd2 *mode_cmd,
8886 struct drm_i915_gem_object *obj)
8887 {
8888 struct drm_framebuffer *fb;
8889 int ret;
8890
8891 ret = i915_mutex_lock_interruptible(dev);
8892 if (ret)
8893 return ERR_PTR(ret);
8894 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8895 mutex_unlock(&dev->struct_mutex);
8896
8897 return fb;
8898 }
8899
8900 static u32
8901 intel_framebuffer_pitch_for_width(int width, int bpp)
8902 {
8903 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8904 return ALIGN(pitch, 64);
8905 }
8906
8907 static u32
8908 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8909 {
8910 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8911 return PAGE_ALIGN(pitch * mode->vdisplay);
8912 }
8913
8914 static struct drm_framebuffer *
8915 intel_framebuffer_create_for_mode(struct drm_device *dev,
8916 struct drm_display_mode *mode,
8917 int depth, int bpp)
8918 {
8919 struct drm_i915_gem_object *obj;
8920 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8921
8922 obj = i915_gem_alloc_object(dev,
8923 intel_framebuffer_size_for_mode(mode, bpp));
8924 if (obj == NULL)
8925 return ERR_PTR(-ENOMEM);
8926
8927 mode_cmd.width = mode->hdisplay;
8928 mode_cmd.height = mode->vdisplay;
8929 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8930 bpp);
8931 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8932
8933 return intel_framebuffer_create(dev, &mode_cmd, obj);
8934 }
8935
8936 static struct drm_framebuffer *
8937 mode_fits_in_fbdev(struct drm_device *dev,
8938 struct drm_display_mode *mode)
8939 {
8940 #ifdef CONFIG_DRM_I915_FBDEV
8941 struct drm_i915_private *dev_priv = dev->dev_private;
8942 struct drm_i915_gem_object *obj;
8943 struct drm_framebuffer *fb;
8944
8945 if (!dev_priv->fbdev)
8946 return NULL;
8947
8948 if (!dev_priv->fbdev->fb)
8949 return NULL;
8950
8951 obj = dev_priv->fbdev->fb->obj;
8952 BUG_ON(!obj);
8953
8954 fb = &dev_priv->fbdev->fb->base;
8955 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8956 fb->bits_per_pixel))
8957 return NULL;
8958
8959 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8960 return NULL;
8961
8962 return fb;
8963 #else
8964 return NULL;
8965 #endif
8966 }
8967
8968 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8969 struct drm_display_mode *mode,
8970 struct intel_load_detect_pipe *old,
8971 struct drm_modeset_acquire_ctx *ctx)
8972 {
8973 struct intel_crtc *intel_crtc;
8974 struct intel_encoder *intel_encoder =
8975 intel_attached_encoder(connector);
8976 struct drm_crtc *possible_crtc;
8977 struct drm_encoder *encoder = &intel_encoder->base;
8978 struct drm_crtc *crtc = NULL;
8979 struct drm_device *dev = encoder->dev;
8980 struct drm_framebuffer *fb;
8981 struct drm_mode_config *config = &dev->mode_config;
8982 struct drm_atomic_state *state = NULL;
8983 struct drm_connector_state *connector_state;
8984 int ret, i = -1;
8985
8986 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8987 connector->base.id, connector->name,
8988 encoder->base.id, encoder->name);
8989
8990 retry:
8991 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8992 if (ret)
8993 goto fail_unlock;
8994
8995 /*
8996 * Algorithm gets a little messy:
8997 *
8998 * - if the connector already has an assigned crtc, use it (but make
8999 * sure it's on first)
9000 *
9001 * - try to find the first unused crtc that can drive this connector,
9002 * and use that if we find one
9003 */
9004
9005 /* See if we already have a CRTC for this connector */
9006 if (encoder->crtc) {
9007 crtc = encoder->crtc;
9008
9009 ret = drm_modeset_lock(&crtc->mutex, ctx);
9010 if (ret)
9011 goto fail_unlock;
9012 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9013 if (ret)
9014 goto fail_unlock;
9015
9016 old->dpms_mode = connector->dpms;
9017 old->load_detect_temp = false;
9018
9019 /* Make sure the crtc and connector are running */
9020 if (connector->dpms != DRM_MODE_DPMS_ON)
9021 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9022
9023 return true;
9024 }
9025
9026 /* Find an unused one (if possible) */
9027 for_each_crtc(dev, possible_crtc) {
9028 i++;
9029 if (!(encoder->possible_crtcs & (1 << i)))
9030 continue;
9031 if (possible_crtc->state->enable)
9032 continue;
9033 /* This can occur when applying the pipe A quirk on resume. */
9034 if (to_intel_crtc(possible_crtc)->new_enabled)
9035 continue;
9036
9037 crtc = possible_crtc;
9038 break;
9039 }
9040
9041 /*
9042 * If we didn't find an unused CRTC, don't use any.
9043 */
9044 if (!crtc) {
9045 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9046 goto fail_unlock;
9047 }
9048
9049 ret = drm_modeset_lock(&crtc->mutex, ctx);
9050 if (ret)
9051 goto fail_unlock;
9052 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9053 if (ret)
9054 goto fail_unlock;
9055 intel_encoder->new_crtc = to_intel_crtc(crtc);
9056 to_intel_connector(connector)->new_encoder = intel_encoder;
9057
9058 intel_crtc = to_intel_crtc(crtc);
9059 intel_crtc->new_enabled = true;
9060 intel_crtc->new_config = intel_crtc->config;
9061 old->dpms_mode = connector->dpms;
9062 old->load_detect_temp = true;
9063 old->release_fb = NULL;
9064
9065 state = drm_atomic_state_alloc(dev);
9066 if (!state)
9067 return false;
9068
9069 state->acquire_ctx = ctx;
9070
9071 connector_state = drm_atomic_get_connector_state(state, connector);
9072 if (IS_ERR(connector_state)) {
9073 ret = PTR_ERR(connector_state);
9074 goto fail;
9075 }
9076
9077 connector_state->crtc = crtc;
9078 connector_state->best_encoder = &intel_encoder->base;
9079
9080 if (!mode)
9081 mode = &load_detect_mode;
9082
9083 /* We need a framebuffer large enough to accommodate all accesses
9084 * that the plane may generate whilst we perform load detection.
9085 * We can not rely on the fbcon either being present (we get called
9086 * during its initialisation to detect all boot displays, or it may
9087 * not even exist) or that it is large enough to satisfy the
9088 * requested mode.
9089 */
9090 fb = mode_fits_in_fbdev(dev, mode);
9091 if (fb == NULL) {
9092 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9093 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9094 old->release_fb = fb;
9095 } else
9096 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9097 if (IS_ERR(fb)) {
9098 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9099 goto fail;
9100 }
9101
9102 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
9103 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9104 if (old->release_fb)
9105 old->release_fb->funcs->destroy(old->release_fb);
9106 goto fail;
9107 }
9108 crtc->primary->crtc = crtc;
9109
9110 /* let the connector get through one full cycle before testing */
9111 intel_wait_for_vblank(dev, intel_crtc->pipe);
9112 return true;
9113
9114 fail:
9115 intel_crtc->new_enabled = crtc->state->enable;
9116 if (intel_crtc->new_enabled)
9117 intel_crtc->new_config = intel_crtc->config;
9118 else
9119 intel_crtc->new_config = NULL;
9120 fail_unlock:
9121 if (state) {
9122 drm_atomic_state_free(state);
9123 state = NULL;
9124 }
9125
9126 if (ret == -EDEADLK) {
9127 drm_modeset_backoff(ctx);
9128 goto retry;
9129 }
9130
9131 return false;
9132 }
9133
9134 void intel_release_load_detect_pipe(struct drm_connector *connector,
9135 struct intel_load_detect_pipe *old,
9136 struct drm_modeset_acquire_ctx *ctx)
9137 {
9138 struct drm_device *dev = connector->dev;
9139 struct intel_encoder *intel_encoder =
9140 intel_attached_encoder(connector);
9141 struct drm_encoder *encoder = &intel_encoder->base;
9142 struct drm_crtc *crtc = encoder->crtc;
9143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9144 struct drm_atomic_state *state;
9145 struct drm_connector_state *connector_state;
9146
9147 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9148 connector->base.id, connector->name,
9149 encoder->base.id, encoder->name);
9150
9151 if (old->load_detect_temp) {
9152 state = drm_atomic_state_alloc(dev);
9153 if (!state)
9154 goto fail;
9155
9156 state->acquire_ctx = ctx;
9157
9158 connector_state = drm_atomic_get_connector_state(state, connector);
9159 if (IS_ERR(connector_state))
9160 goto fail;
9161
9162 to_intel_connector(connector)->new_encoder = NULL;
9163 intel_encoder->new_crtc = NULL;
9164 intel_crtc->new_enabled = false;
9165 intel_crtc->new_config = NULL;
9166
9167 connector_state->best_encoder = NULL;
9168 connector_state->crtc = NULL;
9169
9170 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9171
9172 drm_atomic_state_free(state);
9173
9174 if (old->release_fb) {
9175 drm_framebuffer_unregister_private(old->release_fb);
9176 drm_framebuffer_unreference(old->release_fb);
9177 }
9178
9179 return;
9180 }
9181
9182 /* Switch crtc and encoder back off if necessary */
9183 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9184 connector->funcs->dpms(connector, old->dpms_mode);
9185
9186 return;
9187 fail:
9188 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9189 drm_atomic_state_free(state);
9190 }
9191
9192 static int i9xx_pll_refclk(struct drm_device *dev,
9193 const struct intel_crtc_state *pipe_config)
9194 {
9195 struct drm_i915_private *dev_priv = dev->dev_private;
9196 u32 dpll = pipe_config->dpll_hw_state.dpll;
9197
9198 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9199 return dev_priv->vbt.lvds_ssc_freq;
9200 else if (HAS_PCH_SPLIT(dev))
9201 return 120000;
9202 else if (!IS_GEN2(dev))
9203 return 96000;
9204 else
9205 return 48000;
9206 }
9207
9208 /* Returns the clock of the currently programmed mode of the given pipe. */
9209 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9210 struct intel_crtc_state *pipe_config)
9211 {
9212 struct drm_device *dev = crtc->base.dev;
9213 struct drm_i915_private *dev_priv = dev->dev_private;
9214 int pipe = pipe_config->cpu_transcoder;
9215 u32 dpll = pipe_config->dpll_hw_state.dpll;
9216 u32 fp;
9217 intel_clock_t clock;
9218 int refclk = i9xx_pll_refclk(dev, pipe_config);
9219
9220 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9221 fp = pipe_config->dpll_hw_state.fp0;
9222 else
9223 fp = pipe_config->dpll_hw_state.fp1;
9224
9225 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9226 if (IS_PINEVIEW(dev)) {
9227 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9228 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9229 } else {
9230 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9231 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9232 }
9233
9234 if (!IS_GEN2(dev)) {
9235 if (IS_PINEVIEW(dev))
9236 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9237 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9238 else
9239 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9240 DPLL_FPA01_P1_POST_DIV_SHIFT);
9241
9242 switch (dpll & DPLL_MODE_MASK) {
9243 case DPLLB_MODE_DAC_SERIAL:
9244 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9245 5 : 10;
9246 break;
9247 case DPLLB_MODE_LVDS:
9248 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9249 7 : 14;
9250 break;
9251 default:
9252 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9253 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9254 return;
9255 }
9256
9257 if (IS_PINEVIEW(dev))
9258 pineview_clock(refclk, &clock);
9259 else
9260 i9xx_clock(refclk, &clock);
9261 } else {
9262 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9263 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9264
9265 if (is_lvds) {
9266 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9267 DPLL_FPA01_P1_POST_DIV_SHIFT);
9268
9269 if (lvds & LVDS_CLKB_POWER_UP)
9270 clock.p2 = 7;
9271 else
9272 clock.p2 = 14;
9273 } else {
9274 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9275 clock.p1 = 2;
9276 else {
9277 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9278 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9279 }
9280 if (dpll & PLL_P2_DIVIDE_BY_4)
9281 clock.p2 = 4;
9282 else
9283 clock.p2 = 2;
9284 }
9285
9286 i9xx_clock(refclk, &clock);
9287 }
9288
9289 /*
9290 * This value includes pixel_multiplier. We will use
9291 * port_clock to compute adjusted_mode.crtc_clock in the
9292 * encoder's get_config() function.
9293 */
9294 pipe_config->port_clock = clock.dot;
9295 }
9296
9297 int intel_dotclock_calculate(int link_freq,
9298 const struct intel_link_m_n *m_n)
9299 {
9300 /*
9301 * The calculation for the data clock is:
9302 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9303 * But we want to avoid losing precison if possible, so:
9304 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9305 *
9306 * and the link clock is simpler:
9307 * link_clock = (m * link_clock) / n
9308 */
9309
9310 if (!m_n->link_n)
9311 return 0;
9312
9313 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9314 }
9315
9316 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9317 struct intel_crtc_state *pipe_config)
9318 {
9319 struct drm_device *dev = crtc->base.dev;
9320
9321 /* read out port_clock from the DPLL */
9322 i9xx_crtc_clock_get(crtc, pipe_config);
9323
9324 /*
9325 * This value does not include pixel_multiplier.
9326 * We will check that port_clock and adjusted_mode.crtc_clock
9327 * agree once we know their relationship in the encoder's
9328 * get_config() function.
9329 */
9330 pipe_config->base.adjusted_mode.crtc_clock =
9331 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9332 &pipe_config->fdi_m_n);
9333 }
9334
9335 /** Returns the currently programmed mode of the given pipe. */
9336 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9337 struct drm_crtc *crtc)
9338 {
9339 struct drm_i915_private *dev_priv = dev->dev_private;
9340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9341 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9342 struct drm_display_mode *mode;
9343 struct intel_crtc_state pipe_config;
9344 int htot = I915_READ(HTOTAL(cpu_transcoder));
9345 int hsync = I915_READ(HSYNC(cpu_transcoder));
9346 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9347 int vsync = I915_READ(VSYNC(cpu_transcoder));
9348 enum pipe pipe = intel_crtc->pipe;
9349
9350 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9351 if (!mode)
9352 return NULL;
9353
9354 /*
9355 * Construct a pipe_config sufficient for getting the clock info
9356 * back out of crtc_clock_get.
9357 *
9358 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9359 * to use a real value here instead.
9360 */
9361 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9362 pipe_config.pixel_multiplier = 1;
9363 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9364 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9365 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9366 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9367
9368 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9369 mode->hdisplay = (htot & 0xffff) + 1;
9370 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9371 mode->hsync_start = (hsync & 0xffff) + 1;
9372 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9373 mode->vdisplay = (vtot & 0xffff) + 1;
9374 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9375 mode->vsync_start = (vsync & 0xffff) + 1;
9376 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9377
9378 drm_mode_set_name(mode);
9379
9380 return mode;
9381 }
9382
9383 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9384 {
9385 struct drm_device *dev = crtc->dev;
9386 struct drm_i915_private *dev_priv = dev->dev_private;
9387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9388
9389 if (!HAS_GMCH_DISPLAY(dev))
9390 return;
9391
9392 if (!dev_priv->lvds_downclock_avail)
9393 return;
9394
9395 /*
9396 * Since this is called by a timer, we should never get here in
9397 * the manual case.
9398 */
9399 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9400 int pipe = intel_crtc->pipe;
9401 int dpll_reg = DPLL(pipe);
9402 int dpll;
9403
9404 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9405
9406 assert_panel_unlocked(dev_priv, pipe);
9407
9408 dpll = I915_READ(dpll_reg);
9409 dpll |= DISPLAY_RATE_SELECT_FPA1;
9410 I915_WRITE(dpll_reg, dpll);
9411 intel_wait_for_vblank(dev, pipe);
9412 dpll = I915_READ(dpll_reg);
9413 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9414 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9415 }
9416
9417 }
9418
9419 void intel_mark_busy(struct drm_device *dev)
9420 {
9421 struct drm_i915_private *dev_priv = dev->dev_private;
9422
9423 if (dev_priv->mm.busy)
9424 return;
9425
9426 intel_runtime_pm_get(dev_priv);
9427 i915_update_gfx_val(dev_priv);
9428 if (INTEL_INFO(dev)->gen >= 6)
9429 gen6_rps_busy(dev_priv);
9430 dev_priv->mm.busy = true;
9431 }
9432
9433 void intel_mark_idle(struct drm_device *dev)
9434 {
9435 struct drm_i915_private *dev_priv = dev->dev_private;
9436 struct drm_crtc *crtc;
9437
9438 if (!dev_priv->mm.busy)
9439 return;
9440
9441 dev_priv->mm.busy = false;
9442
9443 for_each_crtc(dev, crtc) {
9444 if (!crtc->primary->fb)
9445 continue;
9446
9447 intel_decrease_pllclock(crtc);
9448 }
9449
9450 if (INTEL_INFO(dev)->gen >= 6)
9451 gen6_rps_idle(dev->dev_private);
9452
9453 intel_runtime_pm_put(dev_priv);
9454 }
9455
9456 static void intel_crtc_set_state(struct intel_crtc *crtc,
9457 struct intel_crtc_state *crtc_state)
9458 {
9459 kfree(crtc->config);
9460 crtc->config = crtc_state;
9461 crtc->base.state = &crtc_state->base;
9462 }
9463
9464 static void intel_crtc_destroy(struct drm_crtc *crtc)
9465 {
9466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9467 struct drm_device *dev = crtc->dev;
9468 struct intel_unpin_work *work;
9469
9470 spin_lock_irq(&dev->event_lock);
9471 work = intel_crtc->unpin_work;
9472 intel_crtc->unpin_work = NULL;
9473 spin_unlock_irq(&dev->event_lock);
9474
9475 if (work) {
9476 cancel_work_sync(&work->work);
9477 kfree(work);
9478 }
9479
9480 intel_crtc_set_state(intel_crtc, NULL);
9481 drm_crtc_cleanup(crtc);
9482
9483 kfree(intel_crtc);
9484 }
9485
9486 static void intel_unpin_work_fn(struct work_struct *__work)
9487 {
9488 struct intel_unpin_work *work =
9489 container_of(__work, struct intel_unpin_work, work);
9490 struct drm_device *dev = work->crtc->dev;
9491 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9492
9493 mutex_lock(&dev->struct_mutex);
9494 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9495 drm_gem_object_unreference(&work->pending_flip_obj->base);
9496
9497 intel_fbc_update(dev);
9498
9499 if (work->flip_queued_req)
9500 i915_gem_request_assign(&work->flip_queued_req, NULL);
9501 mutex_unlock(&dev->struct_mutex);
9502
9503 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9504 drm_framebuffer_unreference(work->old_fb);
9505
9506 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9507 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9508
9509 kfree(work);
9510 }
9511
9512 static void do_intel_finish_page_flip(struct drm_device *dev,
9513 struct drm_crtc *crtc)
9514 {
9515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9516 struct intel_unpin_work *work;
9517 unsigned long flags;
9518
9519 /* Ignore early vblank irqs */
9520 if (intel_crtc == NULL)
9521 return;
9522
9523 /*
9524 * This is called both by irq handlers and the reset code (to complete
9525 * lost pageflips) so needs the full irqsave spinlocks.
9526 */
9527 spin_lock_irqsave(&dev->event_lock, flags);
9528 work = intel_crtc->unpin_work;
9529
9530 /* Ensure we don't miss a work->pending update ... */
9531 smp_rmb();
9532
9533 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9534 spin_unlock_irqrestore(&dev->event_lock, flags);
9535 return;
9536 }
9537
9538 page_flip_completed(intel_crtc);
9539
9540 spin_unlock_irqrestore(&dev->event_lock, flags);
9541 }
9542
9543 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9544 {
9545 struct drm_i915_private *dev_priv = dev->dev_private;
9546 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9547
9548 do_intel_finish_page_flip(dev, crtc);
9549 }
9550
9551 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9552 {
9553 struct drm_i915_private *dev_priv = dev->dev_private;
9554 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9555
9556 do_intel_finish_page_flip(dev, crtc);
9557 }
9558
9559 /* Is 'a' after or equal to 'b'? */
9560 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9561 {
9562 return !((a - b) & 0x80000000);
9563 }
9564
9565 static bool page_flip_finished(struct intel_crtc *crtc)
9566 {
9567 struct drm_device *dev = crtc->base.dev;
9568 struct drm_i915_private *dev_priv = dev->dev_private;
9569
9570 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9571 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9572 return true;
9573
9574 /*
9575 * The relevant registers doen't exist on pre-ctg.
9576 * As the flip done interrupt doesn't trigger for mmio
9577 * flips on gmch platforms, a flip count check isn't
9578 * really needed there. But since ctg has the registers,
9579 * include it in the check anyway.
9580 */
9581 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9582 return true;
9583
9584 /*
9585 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9586 * used the same base address. In that case the mmio flip might
9587 * have completed, but the CS hasn't even executed the flip yet.
9588 *
9589 * A flip count check isn't enough as the CS might have updated
9590 * the base address just after start of vblank, but before we
9591 * managed to process the interrupt. This means we'd complete the
9592 * CS flip too soon.
9593 *
9594 * Combining both checks should get us a good enough result. It may
9595 * still happen that the CS flip has been executed, but has not
9596 * yet actually completed. But in case the base address is the same
9597 * anyway, we don't really care.
9598 */
9599 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9600 crtc->unpin_work->gtt_offset &&
9601 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9602 crtc->unpin_work->flip_count);
9603 }
9604
9605 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9606 {
9607 struct drm_i915_private *dev_priv = dev->dev_private;
9608 struct intel_crtc *intel_crtc =
9609 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9610 unsigned long flags;
9611
9612
9613 /*
9614 * This is called both by irq handlers and the reset code (to complete
9615 * lost pageflips) so needs the full irqsave spinlocks.
9616 *
9617 * NB: An MMIO update of the plane base pointer will also
9618 * generate a page-flip completion irq, i.e. every modeset
9619 * is also accompanied by a spurious intel_prepare_page_flip().
9620 */
9621 spin_lock_irqsave(&dev->event_lock, flags);
9622 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9623 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9624 spin_unlock_irqrestore(&dev->event_lock, flags);
9625 }
9626
9627 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9628 {
9629 /* Ensure that the work item is consistent when activating it ... */
9630 smp_wmb();
9631 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9632 /* and that it is marked active as soon as the irq could fire. */
9633 smp_wmb();
9634 }
9635
9636 static int intel_gen2_queue_flip(struct drm_device *dev,
9637 struct drm_crtc *crtc,
9638 struct drm_framebuffer *fb,
9639 struct drm_i915_gem_object *obj,
9640 struct intel_engine_cs *ring,
9641 uint32_t flags)
9642 {
9643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9644 u32 flip_mask;
9645 int ret;
9646
9647 ret = intel_ring_begin(ring, 6);
9648 if (ret)
9649 return ret;
9650
9651 /* Can't queue multiple flips, so wait for the previous
9652 * one to finish before executing the next.
9653 */
9654 if (intel_crtc->plane)
9655 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9656 else
9657 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9658 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9659 intel_ring_emit(ring, MI_NOOP);
9660 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9661 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9662 intel_ring_emit(ring, fb->pitches[0]);
9663 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9664 intel_ring_emit(ring, 0); /* aux display base address, unused */
9665
9666 intel_mark_page_flip_active(intel_crtc);
9667 __intel_ring_advance(ring);
9668 return 0;
9669 }
9670
9671 static int intel_gen3_queue_flip(struct drm_device *dev,
9672 struct drm_crtc *crtc,
9673 struct drm_framebuffer *fb,
9674 struct drm_i915_gem_object *obj,
9675 struct intel_engine_cs *ring,
9676 uint32_t flags)
9677 {
9678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9679 u32 flip_mask;
9680 int ret;
9681
9682 ret = intel_ring_begin(ring, 6);
9683 if (ret)
9684 return ret;
9685
9686 if (intel_crtc->plane)
9687 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9688 else
9689 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9690 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9691 intel_ring_emit(ring, MI_NOOP);
9692 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9693 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9694 intel_ring_emit(ring, fb->pitches[0]);
9695 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9696 intel_ring_emit(ring, MI_NOOP);
9697
9698 intel_mark_page_flip_active(intel_crtc);
9699 __intel_ring_advance(ring);
9700 return 0;
9701 }
9702
9703 static int intel_gen4_queue_flip(struct drm_device *dev,
9704 struct drm_crtc *crtc,
9705 struct drm_framebuffer *fb,
9706 struct drm_i915_gem_object *obj,
9707 struct intel_engine_cs *ring,
9708 uint32_t flags)
9709 {
9710 struct drm_i915_private *dev_priv = dev->dev_private;
9711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9712 uint32_t pf, pipesrc;
9713 int ret;
9714
9715 ret = intel_ring_begin(ring, 4);
9716 if (ret)
9717 return ret;
9718
9719 /* i965+ uses the linear or tiled offsets from the
9720 * Display Registers (which do not change across a page-flip)
9721 * so we need only reprogram the base address.
9722 */
9723 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9724 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9725 intel_ring_emit(ring, fb->pitches[0]);
9726 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9727 obj->tiling_mode);
9728
9729 /* XXX Enabling the panel-fitter across page-flip is so far
9730 * untested on non-native modes, so ignore it for now.
9731 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9732 */
9733 pf = 0;
9734 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9735 intel_ring_emit(ring, pf | pipesrc);
9736
9737 intel_mark_page_flip_active(intel_crtc);
9738 __intel_ring_advance(ring);
9739 return 0;
9740 }
9741
9742 static int intel_gen6_queue_flip(struct drm_device *dev,
9743 struct drm_crtc *crtc,
9744 struct drm_framebuffer *fb,
9745 struct drm_i915_gem_object *obj,
9746 struct intel_engine_cs *ring,
9747 uint32_t flags)
9748 {
9749 struct drm_i915_private *dev_priv = dev->dev_private;
9750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9751 uint32_t pf, pipesrc;
9752 int ret;
9753
9754 ret = intel_ring_begin(ring, 4);
9755 if (ret)
9756 return ret;
9757
9758 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9759 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9760 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9761 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9762
9763 /* Contrary to the suggestions in the documentation,
9764 * "Enable Panel Fitter" does not seem to be required when page
9765 * flipping with a non-native mode, and worse causes a normal
9766 * modeset to fail.
9767 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9768 */
9769 pf = 0;
9770 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9771 intel_ring_emit(ring, pf | pipesrc);
9772
9773 intel_mark_page_flip_active(intel_crtc);
9774 __intel_ring_advance(ring);
9775 return 0;
9776 }
9777
9778 static int intel_gen7_queue_flip(struct drm_device *dev,
9779 struct drm_crtc *crtc,
9780 struct drm_framebuffer *fb,
9781 struct drm_i915_gem_object *obj,
9782 struct intel_engine_cs *ring,
9783 uint32_t flags)
9784 {
9785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9786 uint32_t plane_bit = 0;
9787 int len, ret;
9788
9789 switch (intel_crtc->plane) {
9790 case PLANE_A:
9791 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9792 break;
9793 case PLANE_B:
9794 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9795 break;
9796 case PLANE_C:
9797 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9798 break;
9799 default:
9800 WARN_ONCE(1, "unknown plane in flip command\n");
9801 return -ENODEV;
9802 }
9803
9804 len = 4;
9805 if (ring->id == RCS) {
9806 len += 6;
9807 /*
9808 * On Gen 8, SRM is now taking an extra dword to accommodate
9809 * 48bits addresses, and we need a NOOP for the batch size to
9810 * stay even.
9811 */
9812 if (IS_GEN8(dev))
9813 len += 2;
9814 }
9815
9816 /*
9817 * BSpec MI_DISPLAY_FLIP for IVB:
9818 * "The full packet must be contained within the same cache line."
9819 *
9820 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9821 * cacheline, if we ever start emitting more commands before
9822 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9823 * then do the cacheline alignment, and finally emit the
9824 * MI_DISPLAY_FLIP.
9825 */
9826 ret = intel_ring_cacheline_align(ring);
9827 if (ret)
9828 return ret;
9829
9830 ret = intel_ring_begin(ring, len);
9831 if (ret)
9832 return ret;
9833
9834 /* Unmask the flip-done completion message. Note that the bspec says that
9835 * we should do this for both the BCS and RCS, and that we must not unmask
9836 * more than one flip event at any time (or ensure that one flip message
9837 * can be sent by waiting for flip-done prior to queueing new flips).
9838 * Experimentation says that BCS works despite DERRMR masking all
9839 * flip-done completion events and that unmasking all planes at once
9840 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9841 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9842 */
9843 if (ring->id == RCS) {
9844 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9845 intel_ring_emit(ring, DERRMR);
9846 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9847 DERRMR_PIPEB_PRI_FLIP_DONE |
9848 DERRMR_PIPEC_PRI_FLIP_DONE));
9849 if (IS_GEN8(dev))
9850 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9851 MI_SRM_LRM_GLOBAL_GTT);
9852 else
9853 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9854 MI_SRM_LRM_GLOBAL_GTT);
9855 intel_ring_emit(ring, DERRMR);
9856 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9857 if (IS_GEN8(dev)) {
9858 intel_ring_emit(ring, 0);
9859 intel_ring_emit(ring, MI_NOOP);
9860 }
9861 }
9862
9863 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9864 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9865 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9866 intel_ring_emit(ring, (MI_NOOP));
9867
9868 intel_mark_page_flip_active(intel_crtc);
9869 __intel_ring_advance(ring);
9870 return 0;
9871 }
9872
9873 static bool use_mmio_flip(struct intel_engine_cs *ring,
9874 struct drm_i915_gem_object *obj)
9875 {
9876 /*
9877 * This is not being used for older platforms, because
9878 * non-availability of flip done interrupt forces us to use
9879 * CS flips. Older platforms derive flip done using some clever
9880 * tricks involving the flip_pending status bits and vblank irqs.
9881 * So using MMIO flips there would disrupt this mechanism.
9882 */
9883
9884 if (ring == NULL)
9885 return true;
9886
9887 if (INTEL_INFO(ring->dev)->gen < 5)
9888 return false;
9889
9890 if (i915.use_mmio_flip < 0)
9891 return false;
9892 else if (i915.use_mmio_flip > 0)
9893 return true;
9894 else if (i915.enable_execlists)
9895 return true;
9896 else
9897 return ring != i915_gem_request_get_ring(obj->last_read_req);
9898 }
9899
9900 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9901 {
9902 struct drm_device *dev = intel_crtc->base.dev;
9903 struct drm_i915_private *dev_priv = dev->dev_private;
9904 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9905 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9906 struct drm_i915_gem_object *obj = intel_fb->obj;
9907 const enum pipe pipe = intel_crtc->pipe;
9908 u32 ctl, stride;
9909
9910 ctl = I915_READ(PLANE_CTL(pipe, 0));
9911 ctl &= ~PLANE_CTL_TILED_MASK;
9912 if (obj->tiling_mode == I915_TILING_X)
9913 ctl |= PLANE_CTL_TILED_X;
9914
9915 /*
9916 * The stride is either expressed as a multiple of 64 bytes chunks for
9917 * linear buffers or in number of tiles for tiled buffers.
9918 */
9919 stride = fb->pitches[0] >> 6;
9920 if (obj->tiling_mode == I915_TILING_X)
9921 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9922
9923 /*
9924 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9925 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9926 */
9927 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9928 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9929
9930 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9931 POSTING_READ(PLANE_SURF(pipe, 0));
9932 }
9933
9934 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9935 {
9936 struct drm_device *dev = intel_crtc->base.dev;
9937 struct drm_i915_private *dev_priv = dev->dev_private;
9938 struct intel_framebuffer *intel_fb =
9939 to_intel_framebuffer(intel_crtc->base.primary->fb);
9940 struct drm_i915_gem_object *obj = intel_fb->obj;
9941 u32 dspcntr;
9942 u32 reg;
9943
9944 reg = DSPCNTR(intel_crtc->plane);
9945 dspcntr = I915_READ(reg);
9946
9947 if (obj->tiling_mode != I915_TILING_NONE)
9948 dspcntr |= DISPPLANE_TILED;
9949 else
9950 dspcntr &= ~DISPPLANE_TILED;
9951
9952 I915_WRITE(reg, dspcntr);
9953
9954 I915_WRITE(DSPSURF(intel_crtc->plane),
9955 intel_crtc->unpin_work->gtt_offset);
9956 POSTING_READ(DSPSURF(intel_crtc->plane));
9957
9958 }
9959
9960 /*
9961 * XXX: This is the temporary way to update the plane registers until we get
9962 * around to using the usual plane update functions for MMIO flips
9963 */
9964 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9965 {
9966 struct drm_device *dev = intel_crtc->base.dev;
9967 bool atomic_update;
9968 u32 start_vbl_count;
9969
9970 intel_mark_page_flip_active(intel_crtc);
9971
9972 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9973
9974 if (INTEL_INFO(dev)->gen >= 9)
9975 skl_do_mmio_flip(intel_crtc);
9976 else
9977 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9978 ilk_do_mmio_flip(intel_crtc);
9979
9980 if (atomic_update)
9981 intel_pipe_update_end(intel_crtc, start_vbl_count);
9982 }
9983
9984 static void intel_mmio_flip_work_func(struct work_struct *work)
9985 {
9986 struct intel_crtc *crtc =
9987 container_of(work, struct intel_crtc, mmio_flip.work);
9988 struct intel_mmio_flip *mmio_flip;
9989
9990 mmio_flip = &crtc->mmio_flip;
9991 if (mmio_flip->req)
9992 WARN_ON(__i915_wait_request(mmio_flip->req,
9993 crtc->reset_counter,
9994 false, NULL, NULL) != 0);
9995
9996 intel_do_mmio_flip(crtc);
9997 if (mmio_flip->req) {
9998 mutex_lock(&crtc->base.dev->struct_mutex);
9999 i915_gem_request_assign(&mmio_flip->req, NULL);
10000 mutex_unlock(&crtc->base.dev->struct_mutex);
10001 }
10002 }
10003
10004 static int intel_queue_mmio_flip(struct drm_device *dev,
10005 struct drm_crtc *crtc,
10006 struct drm_framebuffer *fb,
10007 struct drm_i915_gem_object *obj,
10008 struct intel_engine_cs *ring,
10009 uint32_t flags)
10010 {
10011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10012
10013 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10014 obj->last_write_req);
10015
10016 schedule_work(&intel_crtc->mmio_flip.work);
10017
10018 return 0;
10019 }
10020
10021 static int intel_default_queue_flip(struct drm_device *dev,
10022 struct drm_crtc *crtc,
10023 struct drm_framebuffer *fb,
10024 struct drm_i915_gem_object *obj,
10025 struct intel_engine_cs *ring,
10026 uint32_t flags)
10027 {
10028 return -ENODEV;
10029 }
10030
10031 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10032 struct drm_crtc *crtc)
10033 {
10034 struct drm_i915_private *dev_priv = dev->dev_private;
10035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10036 struct intel_unpin_work *work = intel_crtc->unpin_work;
10037 u32 addr;
10038
10039 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10040 return true;
10041
10042 if (!work->enable_stall_check)
10043 return false;
10044
10045 if (work->flip_ready_vblank == 0) {
10046 if (work->flip_queued_req &&
10047 !i915_gem_request_completed(work->flip_queued_req, true))
10048 return false;
10049
10050 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10051 }
10052
10053 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10054 return false;
10055
10056 /* Potential stall - if we see that the flip has happened,
10057 * assume a missed interrupt. */
10058 if (INTEL_INFO(dev)->gen >= 4)
10059 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10060 else
10061 addr = I915_READ(DSPADDR(intel_crtc->plane));
10062
10063 /* There is a potential issue here with a false positive after a flip
10064 * to the same address. We could address this by checking for a
10065 * non-incrementing frame counter.
10066 */
10067 return addr == work->gtt_offset;
10068 }
10069
10070 void intel_check_page_flip(struct drm_device *dev, int pipe)
10071 {
10072 struct drm_i915_private *dev_priv = dev->dev_private;
10073 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10075
10076 WARN_ON(!in_interrupt());
10077
10078 if (crtc == NULL)
10079 return;
10080
10081 spin_lock(&dev->event_lock);
10082 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
10083 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10084 intel_crtc->unpin_work->flip_queued_vblank,
10085 drm_vblank_count(dev, pipe));
10086 page_flip_completed(intel_crtc);
10087 }
10088 spin_unlock(&dev->event_lock);
10089 }
10090
10091 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10092 struct drm_framebuffer *fb,
10093 struct drm_pending_vblank_event *event,
10094 uint32_t page_flip_flags)
10095 {
10096 struct drm_device *dev = crtc->dev;
10097 struct drm_i915_private *dev_priv = dev->dev_private;
10098 struct drm_framebuffer *old_fb = crtc->primary->fb;
10099 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10101 struct drm_plane *primary = crtc->primary;
10102 enum pipe pipe = intel_crtc->pipe;
10103 struct intel_unpin_work *work;
10104 struct intel_engine_cs *ring;
10105 int ret;
10106
10107 /*
10108 * drm_mode_page_flip_ioctl() should already catch this, but double
10109 * check to be safe. In the future we may enable pageflipping from
10110 * a disabled primary plane.
10111 */
10112 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10113 return -EBUSY;
10114
10115 /* Can't change pixel format via MI display flips. */
10116 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10117 return -EINVAL;
10118
10119 /*
10120 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10121 * Note that pitch changes could also affect these register.
10122 */
10123 if (INTEL_INFO(dev)->gen > 3 &&
10124 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10125 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10126 return -EINVAL;
10127
10128 if (i915_terminally_wedged(&dev_priv->gpu_error))
10129 goto out_hang;
10130
10131 work = kzalloc(sizeof(*work), GFP_KERNEL);
10132 if (work == NULL)
10133 return -ENOMEM;
10134
10135 work->event = event;
10136 work->crtc = crtc;
10137 work->old_fb = old_fb;
10138 INIT_WORK(&work->work, intel_unpin_work_fn);
10139
10140 ret = drm_crtc_vblank_get(crtc);
10141 if (ret)
10142 goto free_work;
10143
10144 /* We borrow the event spin lock for protecting unpin_work */
10145 spin_lock_irq(&dev->event_lock);
10146 if (intel_crtc->unpin_work) {
10147 /* Before declaring the flip queue wedged, check if
10148 * the hardware completed the operation behind our backs.
10149 */
10150 if (__intel_pageflip_stall_check(dev, crtc)) {
10151 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10152 page_flip_completed(intel_crtc);
10153 } else {
10154 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10155 spin_unlock_irq(&dev->event_lock);
10156
10157 drm_crtc_vblank_put(crtc);
10158 kfree(work);
10159 return -EBUSY;
10160 }
10161 }
10162 intel_crtc->unpin_work = work;
10163 spin_unlock_irq(&dev->event_lock);
10164
10165 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10166 flush_workqueue(dev_priv->wq);
10167
10168 /* Reference the objects for the scheduled work. */
10169 drm_framebuffer_reference(work->old_fb);
10170 drm_gem_object_reference(&obj->base);
10171
10172 crtc->primary->fb = fb;
10173 update_state_fb(crtc->primary);
10174
10175 work->pending_flip_obj = obj;
10176
10177 ret = i915_mutex_lock_interruptible(dev);
10178 if (ret)
10179 goto cleanup;
10180
10181 atomic_inc(&intel_crtc->unpin_work_count);
10182 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10183
10184 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10185 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10186
10187 if (IS_VALLEYVIEW(dev)) {
10188 ring = &dev_priv->ring[BCS];
10189 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10190 /* vlv: DISPLAY_FLIP fails to change tiling */
10191 ring = NULL;
10192 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10193 ring = &dev_priv->ring[BCS];
10194 } else if (INTEL_INFO(dev)->gen >= 7) {
10195 ring = i915_gem_request_get_ring(obj->last_read_req);
10196 if (ring == NULL || ring->id != RCS)
10197 ring = &dev_priv->ring[BCS];
10198 } else {
10199 ring = &dev_priv->ring[RCS];
10200 }
10201
10202 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10203 crtc->primary->state, ring);
10204 if (ret)
10205 goto cleanup_pending;
10206
10207 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10208 + intel_crtc->dspaddr_offset;
10209
10210 if (use_mmio_flip(ring, obj)) {
10211 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10212 page_flip_flags);
10213 if (ret)
10214 goto cleanup_unpin;
10215
10216 i915_gem_request_assign(&work->flip_queued_req,
10217 obj->last_write_req);
10218 } else {
10219 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10220 page_flip_flags);
10221 if (ret)
10222 goto cleanup_unpin;
10223
10224 i915_gem_request_assign(&work->flip_queued_req,
10225 intel_ring_get_request(ring));
10226 }
10227
10228 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10229 work->enable_stall_check = true;
10230
10231 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10232 INTEL_FRONTBUFFER_PRIMARY(pipe));
10233
10234 intel_fbc_disable(dev);
10235 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10236 mutex_unlock(&dev->struct_mutex);
10237
10238 trace_i915_flip_request(intel_crtc->plane, obj);
10239
10240 return 0;
10241
10242 cleanup_unpin:
10243 intel_unpin_fb_obj(fb, crtc->primary->state);
10244 cleanup_pending:
10245 atomic_dec(&intel_crtc->unpin_work_count);
10246 mutex_unlock(&dev->struct_mutex);
10247 cleanup:
10248 crtc->primary->fb = old_fb;
10249 update_state_fb(crtc->primary);
10250
10251 drm_gem_object_unreference_unlocked(&obj->base);
10252 drm_framebuffer_unreference(work->old_fb);
10253
10254 spin_lock_irq(&dev->event_lock);
10255 intel_crtc->unpin_work = NULL;
10256 spin_unlock_irq(&dev->event_lock);
10257
10258 drm_crtc_vblank_put(crtc);
10259 free_work:
10260 kfree(work);
10261
10262 if (ret == -EIO) {
10263 out_hang:
10264 ret = intel_plane_restore(primary);
10265 if (ret == 0 && event) {
10266 spin_lock_irq(&dev->event_lock);
10267 drm_send_vblank_event(dev, pipe, event);
10268 spin_unlock_irq(&dev->event_lock);
10269 }
10270 }
10271 return ret;
10272 }
10273
10274 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10275 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10276 .load_lut = intel_crtc_load_lut,
10277 .atomic_begin = intel_begin_crtc_commit,
10278 .atomic_flush = intel_finish_crtc_commit,
10279 };
10280
10281 /**
10282 * intel_modeset_update_staged_output_state
10283 *
10284 * Updates the staged output configuration state, e.g. after we've read out the
10285 * current hw state.
10286 */
10287 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10288 {
10289 struct intel_crtc *crtc;
10290 struct intel_encoder *encoder;
10291 struct intel_connector *connector;
10292
10293 for_each_intel_connector(dev, connector) {
10294 connector->new_encoder =
10295 to_intel_encoder(connector->base.encoder);
10296 }
10297
10298 for_each_intel_encoder(dev, encoder) {
10299 encoder->new_crtc =
10300 to_intel_crtc(encoder->base.crtc);
10301 }
10302
10303 for_each_intel_crtc(dev, crtc) {
10304 crtc->new_enabled = crtc->base.state->enable;
10305
10306 if (crtc->new_enabled)
10307 crtc->new_config = crtc->config;
10308 else
10309 crtc->new_config = NULL;
10310 }
10311 }
10312
10313 /* Transitional helper to copy current connector/encoder state to
10314 * connector->state. This is needed so that code that is partially
10315 * converted to atomic does the right thing.
10316 */
10317 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10318 {
10319 struct intel_connector *connector;
10320
10321 for_each_intel_connector(dev, connector) {
10322 if (connector->base.encoder) {
10323 connector->base.state->best_encoder =
10324 connector->base.encoder;
10325 connector->base.state->crtc =
10326 connector->base.encoder->crtc;
10327 } else {
10328 connector->base.state->best_encoder = NULL;
10329 connector->base.state->crtc = NULL;
10330 }
10331 }
10332 }
10333
10334 /**
10335 * intel_modeset_commit_output_state
10336 *
10337 * This function copies the stage display pipe configuration to the real one.
10338 */
10339 static void intel_modeset_commit_output_state(struct drm_device *dev)
10340 {
10341 struct intel_crtc *crtc;
10342 struct intel_encoder *encoder;
10343 struct intel_connector *connector;
10344
10345 for_each_intel_connector(dev, connector) {
10346 connector->base.encoder = &connector->new_encoder->base;
10347 }
10348
10349 for_each_intel_encoder(dev, encoder) {
10350 encoder->base.crtc = &encoder->new_crtc->base;
10351 }
10352
10353 for_each_intel_crtc(dev, crtc) {
10354 crtc->base.state->enable = crtc->new_enabled;
10355 crtc->base.enabled = crtc->new_enabled;
10356 }
10357
10358 intel_modeset_update_connector_atomic_state(dev);
10359 }
10360
10361 static void
10362 connected_sink_compute_bpp(struct intel_connector *connector,
10363 struct intel_crtc_state *pipe_config)
10364 {
10365 int bpp = pipe_config->pipe_bpp;
10366
10367 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10368 connector->base.base.id,
10369 connector->base.name);
10370
10371 /* Don't use an invalid EDID bpc value */
10372 if (connector->base.display_info.bpc &&
10373 connector->base.display_info.bpc * 3 < bpp) {
10374 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10375 bpp, connector->base.display_info.bpc*3);
10376 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10377 }
10378
10379 /* Clamp bpp to 8 on screens without EDID 1.4 */
10380 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10381 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10382 bpp);
10383 pipe_config->pipe_bpp = 24;
10384 }
10385 }
10386
10387 static int
10388 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10389 struct drm_framebuffer *fb,
10390 struct intel_crtc_state *pipe_config)
10391 {
10392 struct drm_device *dev = crtc->base.dev;
10393 struct drm_atomic_state *state;
10394 struct intel_connector *connector;
10395 int bpp, i;
10396
10397 switch (fb->pixel_format) {
10398 case DRM_FORMAT_C8:
10399 bpp = 8*3; /* since we go through a colormap */
10400 break;
10401 case DRM_FORMAT_XRGB1555:
10402 case DRM_FORMAT_ARGB1555:
10403 /* checked in intel_framebuffer_init already */
10404 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10405 return -EINVAL;
10406 case DRM_FORMAT_RGB565:
10407 bpp = 6*3; /* min is 18bpp */
10408 break;
10409 case DRM_FORMAT_XBGR8888:
10410 case DRM_FORMAT_ABGR8888:
10411 /* checked in intel_framebuffer_init already */
10412 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10413 return -EINVAL;
10414 case DRM_FORMAT_XRGB8888:
10415 case DRM_FORMAT_ARGB8888:
10416 bpp = 8*3;
10417 break;
10418 case DRM_FORMAT_XRGB2101010:
10419 case DRM_FORMAT_ARGB2101010:
10420 case DRM_FORMAT_XBGR2101010:
10421 case DRM_FORMAT_ABGR2101010:
10422 /* checked in intel_framebuffer_init already */
10423 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10424 return -EINVAL;
10425 bpp = 10*3;
10426 break;
10427 /* TODO: gen4+ supports 16 bpc floating point, too. */
10428 default:
10429 DRM_DEBUG_KMS("unsupported depth\n");
10430 return -EINVAL;
10431 }
10432
10433 pipe_config->pipe_bpp = bpp;
10434
10435 state = pipe_config->base.state;
10436
10437 /* Clamp display bpp to EDID value */
10438 for (i = 0; i < state->num_connector; i++) {
10439 if (!state->connectors[i])
10440 continue;
10441
10442 connector = to_intel_connector(state->connectors[i]);
10443 if (state->connector_states[i]->crtc != &crtc->base)
10444 continue;
10445
10446 connected_sink_compute_bpp(connector, pipe_config);
10447 }
10448
10449 return bpp;
10450 }
10451
10452 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10453 {
10454 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10455 "type: 0x%x flags: 0x%x\n",
10456 mode->crtc_clock,
10457 mode->crtc_hdisplay, mode->crtc_hsync_start,
10458 mode->crtc_hsync_end, mode->crtc_htotal,
10459 mode->crtc_vdisplay, mode->crtc_vsync_start,
10460 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10461 }
10462
10463 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10464 struct intel_crtc_state *pipe_config,
10465 const char *context)
10466 {
10467 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10468 context, pipe_name(crtc->pipe));
10469
10470 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10471 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10472 pipe_config->pipe_bpp, pipe_config->dither);
10473 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10474 pipe_config->has_pch_encoder,
10475 pipe_config->fdi_lanes,
10476 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10477 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10478 pipe_config->fdi_m_n.tu);
10479 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10480 pipe_config->has_dp_encoder,
10481 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10482 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10483 pipe_config->dp_m_n.tu);
10484
10485 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10486 pipe_config->has_dp_encoder,
10487 pipe_config->dp_m2_n2.gmch_m,
10488 pipe_config->dp_m2_n2.gmch_n,
10489 pipe_config->dp_m2_n2.link_m,
10490 pipe_config->dp_m2_n2.link_n,
10491 pipe_config->dp_m2_n2.tu);
10492
10493 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10494 pipe_config->has_audio,
10495 pipe_config->has_infoframe);
10496
10497 DRM_DEBUG_KMS("requested mode:\n");
10498 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10499 DRM_DEBUG_KMS("adjusted mode:\n");
10500 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10501 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10502 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10503 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10504 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10505 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10506 pipe_config->gmch_pfit.control,
10507 pipe_config->gmch_pfit.pgm_ratios,
10508 pipe_config->gmch_pfit.lvds_border_bits);
10509 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10510 pipe_config->pch_pfit.pos,
10511 pipe_config->pch_pfit.size,
10512 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10513 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10514 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10515 }
10516
10517 static bool encoders_cloneable(const struct intel_encoder *a,
10518 const struct intel_encoder *b)
10519 {
10520 /* masks could be asymmetric, so check both ways */
10521 return a == b || (a->cloneable & (1 << b->type) &&
10522 b->cloneable & (1 << a->type));
10523 }
10524
10525 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10526 struct intel_encoder *encoder)
10527 {
10528 struct drm_device *dev = crtc->base.dev;
10529 struct intel_encoder *source_encoder;
10530
10531 for_each_intel_encoder(dev, source_encoder) {
10532 if (source_encoder->new_crtc != crtc)
10533 continue;
10534
10535 if (!encoders_cloneable(encoder, source_encoder))
10536 return false;
10537 }
10538
10539 return true;
10540 }
10541
10542 static bool check_encoder_cloning(struct intel_crtc *crtc)
10543 {
10544 struct drm_device *dev = crtc->base.dev;
10545 struct intel_encoder *encoder;
10546
10547 for_each_intel_encoder(dev, encoder) {
10548 if (encoder->new_crtc != crtc)
10549 continue;
10550
10551 if (!check_single_encoder_cloning(crtc, encoder))
10552 return false;
10553 }
10554
10555 return true;
10556 }
10557
10558 static bool check_digital_port_conflicts(struct drm_device *dev)
10559 {
10560 struct intel_connector *connector;
10561 unsigned int used_ports = 0;
10562
10563 /*
10564 * Walk the connector list instead of the encoder
10565 * list to detect the problem on ddi platforms
10566 * where there's just one encoder per digital port.
10567 */
10568 for_each_intel_connector(dev, connector) {
10569 struct intel_encoder *encoder = connector->new_encoder;
10570
10571 if (!encoder)
10572 continue;
10573
10574 WARN_ON(!encoder->new_crtc);
10575
10576 switch (encoder->type) {
10577 unsigned int port_mask;
10578 case INTEL_OUTPUT_UNKNOWN:
10579 if (WARN_ON(!HAS_DDI(dev)))
10580 break;
10581 case INTEL_OUTPUT_DISPLAYPORT:
10582 case INTEL_OUTPUT_HDMI:
10583 case INTEL_OUTPUT_EDP:
10584 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10585
10586 /* the same port mustn't appear more than once */
10587 if (used_ports & port_mask)
10588 return false;
10589
10590 used_ports |= port_mask;
10591 default:
10592 break;
10593 }
10594 }
10595
10596 return true;
10597 }
10598
10599 static void
10600 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10601 {
10602 struct drm_crtc_state tmp_state;
10603
10604 /* Clear only the intel specific part of the crtc state */
10605 tmp_state = crtc_state->base;
10606 memset(crtc_state, 0, sizeof *crtc_state);
10607 crtc_state->base = tmp_state;
10608 }
10609
10610 static struct intel_crtc_state *
10611 intel_modeset_pipe_config(struct drm_crtc *crtc,
10612 struct drm_framebuffer *fb,
10613 struct drm_display_mode *mode,
10614 struct drm_atomic_state *state)
10615 {
10616 struct drm_device *dev = crtc->dev;
10617 struct intel_encoder *encoder;
10618 struct intel_connector *connector;
10619 struct drm_connector_state *connector_state;
10620 struct intel_crtc_state *pipe_config;
10621 int plane_bpp, ret = -EINVAL;
10622 int i;
10623 bool retry = true;
10624
10625 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10626 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10627 return ERR_PTR(-EINVAL);
10628 }
10629
10630 if (!check_digital_port_conflicts(dev)) {
10631 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10632 return ERR_PTR(-EINVAL);
10633 }
10634
10635 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10636 if (IS_ERR(pipe_config))
10637 return pipe_config;
10638
10639 clear_intel_crtc_state(pipe_config);
10640
10641 pipe_config->base.crtc = crtc;
10642 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10643 drm_mode_copy(&pipe_config->base.mode, mode);
10644
10645 pipe_config->cpu_transcoder =
10646 (enum transcoder) to_intel_crtc(crtc)->pipe;
10647 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10648
10649 /*
10650 * Sanitize sync polarity flags based on requested ones. If neither
10651 * positive or negative polarity is requested, treat this as meaning
10652 * negative polarity.
10653 */
10654 if (!(pipe_config->base.adjusted_mode.flags &
10655 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10656 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10657
10658 if (!(pipe_config->base.adjusted_mode.flags &
10659 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10660 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10661
10662 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10663 * plane pixel format and any sink constraints into account. Returns the
10664 * source plane bpp so that dithering can be selected on mismatches
10665 * after encoders and crtc also have had their say. */
10666 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10667 fb, pipe_config);
10668 if (plane_bpp < 0)
10669 goto fail;
10670
10671 /*
10672 * Determine the real pipe dimensions. Note that stereo modes can
10673 * increase the actual pipe size due to the frame doubling and
10674 * insertion of additional space for blanks between the frame. This
10675 * is stored in the crtc timings. We use the requested mode to do this
10676 * computation to clearly distinguish it from the adjusted mode, which
10677 * can be changed by the connectors in the below retry loop.
10678 */
10679 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10680 &pipe_config->pipe_src_w,
10681 &pipe_config->pipe_src_h);
10682
10683 encoder_retry:
10684 /* Ensure the port clock defaults are reset when retrying. */
10685 pipe_config->port_clock = 0;
10686 pipe_config->pixel_multiplier = 1;
10687
10688 /* Fill in default crtc timings, allow encoders to overwrite them. */
10689 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10690 CRTC_STEREO_DOUBLE);
10691
10692 /* Pass our mode to the connectors and the CRTC to give them a chance to
10693 * adjust it according to limitations or connector properties, and also
10694 * a chance to reject the mode entirely.
10695 */
10696 for (i = 0; i < state->num_connector; i++) {
10697 connector = to_intel_connector(state->connectors[i]);
10698 if (!connector)
10699 continue;
10700
10701 connector_state = state->connector_states[i];
10702 if (connector_state->crtc != crtc)
10703 continue;
10704
10705 encoder = to_intel_encoder(connector_state->best_encoder);
10706
10707 if (!(encoder->compute_config(encoder, pipe_config))) {
10708 DRM_DEBUG_KMS("Encoder config failure\n");
10709 goto fail;
10710 }
10711 }
10712
10713 /* Set default port clock if not overwritten by the encoder. Needs to be
10714 * done afterwards in case the encoder adjusts the mode. */
10715 if (!pipe_config->port_clock)
10716 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10717 * pipe_config->pixel_multiplier;
10718
10719 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10720 if (ret < 0) {
10721 DRM_DEBUG_KMS("CRTC fixup failed\n");
10722 goto fail;
10723 }
10724
10725 if (ret == RETRY) {
10726 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10727 ret = -EINVAL;
10728 goto fail;
10729 }
10730
10731 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10732 retry = false;
10733 goto encoder_retry;
10734 }
10735
10736 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10737 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10738 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10739
10740 return pipe_config;
10741 fail:
10742 return ERR_PTR(ret);
10743 }
10744
10745 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10746 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10747 static void
10748 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10749 unsigned *prepare_pipes, unsigned *disable_pipes)
10750 {
10751 struct intel_crtc *intel_crtc;
10752 struct drm_device *dev = crtc->dev;
10753 struct intel_encoder *encoder;
10754 struct intel_connector *connector;
10755 struct drm_crtc *tmp_crtc;
10756
10757 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10758
10759 /* Check which crtcs have changed outputs connected to them, these need
10760 * to be part of the prepare_pipes mask. We don't (yet) support global
10761 * modeset across multiple crtcs, so modeset_pipes will only have one
10762 * bit set at most. */
10763 for_each_intel_connector(dev, connector) {
10764 if (connector->base.encoder == &connector->new_encoder->base)
10765 continue;
10766
10767 if (connector->base.encoder) {
10768 tmp_crtc = connector->base.encoder->crtc;
10769
10770 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10771 }
10772
10773 if (connector->new_encoder)
10774 *prepare_pipes |=
10775 1 << connector->new_encoder->new_crtc->pipe;
10776 }
10777
10778 for_each_intel_encoder(dev, encoder) {
10779 if (encoder->base.crtc == &encoder->new_crtc->base)
10780 continue;
10781
10782 if (encoder->base.crtc) {
10783 tmp_crtc = encoder->base.crtc;
10784
10785 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10786 }
10787
10788 if (encoder->new_crtc)
10789 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10790 }
10791
10792 /* Check for pipes that will be enabled/disabled ... */
10793 for_each_intel_crtc(dev, intel_crtc) {
10794 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10795 continue;
10796
10797 if (!intel_crtc->new_enabled)
10798 *disable_pipes |= 1 << intel_crtc->pipe;
10799 else
10800 *prepare_pipes |= 1 << intel_crtc->pipe;
10801 }
10802
10803
10804 /* set_mode is also used to update properties on life display pipes. */
10805 intel_crtc = to_intel_crtc(crtc);
10806 if (intel_crtc->new_enabled)
10807 *prepare_pipes |= 1 << intel_crtc->pipe;
10808
10809 /*
10810 * For simplicity do a full modeset on any pipe where the output routing
10811 * changed. We could be more clever, but that would require us to be
10812 * more careful with calling the relevant encoder->mode_set functions.
10813 */
10814 if (*prepare_pipes)
10815 *modeset_pipes = *prepare_pipes;
10816
10817 /* ... and mask these out. */
10818 *modeset_pipes &= ~(*disable_pipes);
10819 *prepare_pipes &= ~(*disable_pipes);
10820
10821 /*
10822 * HACK: We don't (yet) fully support global modesets. intel_set_config
10823 * obies this rule, but the modeset restore mode of
10824 * intel_modeset_setup_hw_state does not.
10825 */
10826 *modeset_pipes &= 1 << intel_crtc->pipe;
10827 *prepare_pipes &= 1 << intel_crtc->pipe;
10828
10829 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10830 *modeset_pipes, *prepare_pipes, *disable_pipes);
10831 }
10832
10833 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10834 {
10835 struct drm_encoder *encoder;
10836 struct drm_device *dev = crtc->dev;
10837
10838 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10839 if (encoder->crtc == crtc)
10840 return true;
10841
10842 return false;
10843 }
10844
10845 static void
10846 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10847 {
10848 struct drm_i915_private *dev_priv = dev->dev_private;
10849 struct intel_encoder *intel_encoder;
10850 struct intel_crtc *intel_crtc;
10851 struct drm_connector *connector;
10852
10853 intel_shared_dpll_commit(dev_priv);
10854
10855 for_each_intel_encoder(dev, intel_encoder) {
10856 if (!intel_encoder->base.crtc)
10857 continue;
10858
10859 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10860
10861 if (prepare_pipes & (1 << intel_crtc->pipe))
10862 intel_encoder->connectors_active = false;
10863 }
10864
10865 intel_modeset_commit_output_state(dev);
10866
10867 /* Double check state. */
10868 for_each_intel_crtc(dev, intel_crtc) {
10869 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10870 WARN_ON(intel_crtc->new_config &&
10871 intel_crtc->new_config != intel_crtc->config);
10872 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10873 }
10874
10875 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10876 if (!connector->encoder || !connector->encoder->crtc)
10877 continue;
10878
10879 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10880
10881 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10882 struct drm_property *dpms_property =
10883 dev->mode_config.dpms_property;
10884
10885 connector->dpms = DRM_MODE_DPMS_ON;
10886 drm_object_property_set_value(&connector->base,
10887 dpms_property,
10888 DRM_MODE_DPMS_ON);
10889
10890 intel_encoder = to_intel_encoder(connector->encoder);
10891 intel_encoder->connectors_active = true;
10892 }
10893 }
10894
10895 }
10896
10897 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10898 {
10899 int diff;
10900
10901 if (clock1 == clock2)
10902 return true;
10903
10904 if (!clock1 || !clock2)
10905 return false;
10906
10907 diff = abs(clock1 - clock2);
10908
10909 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10910 return true;
10911
10912 return false;
10913 }
10914
10915 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10916 list_for_each_entry((intel_crtc), \
10917 &(dev)->mode_config.crtc_list, \
10918 base.head) \
10919 if (mask & (1 <<(intel_crtc)->pipe))
10920
10921 static bool
10922 intel_pipe_config_compare(struct drm_device *dev,
10923 struct intel_crtc_state *current_config,
10924 struct intel_crtc_state *pipe_config)
10925 {
10926 #define PIPE_CONF_CHECK_X(name) \
10927 if (current_config->name != pipe_config->name) { \
10928 DRM_ERROR("mismatch in " #name " " \
10929 "(expected 0x%08x, found 0x%08x)\n", \
10930 current_config->name, \
10931 pipe_config->name); \
10932 return false; \
10933 }
10934
10935 #define PIPE_CONF_CHECK_I(name) \
10936 if (current_config->name != pipe_config->name) { \
10937 DRM_ERROR("mismatch in " #name " " \
10938 "(expected %i, found %i)\n", \
10939 current_config->name, \
10940 pipe_config->name); \
10941 return false; \
10942 }
10943
10944 /* This is required for BDW+ where there is only one set of registers for
10945 * switching between high and low RR.
10946 * This macro can be used whenever a comparison has to be made between one
10947 * hw state and multiple sw state variables.
10948 */
10949 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10950 if ((current_config->name != pipe_config->name) && \
10951 (current_config->alt_name != pipe_config->name)) { \
10952 DRM_ERROR("mismatch in " #name " " \
10953 "(expected %i or %i, found %i)\n", \
10954 current_config->name, \
10955 current_config->alt_name, \
10956 pipe_config->name); \
10957 return false; \
10958 }
10959
10960 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10961 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10962 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10963 "(expected %i, found %i)\n", \
10964 current_config->name & (mask), \
10965 pipe_config->name & (mask)); \
10966 return false; \
10967 }
10968
10969 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10970 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10971 DRM_ERROR("mismatch in " #name " " \
10972 "(expected %i, found %i)\n", \
10973 current_config->name, \
10974 pipe_config->name); \
10975 return false; \
10976 }
10977
10978 #define PIPE_CONF_QUIRK(quirk) \
10979 ((current_config->quirks | pipe_config->quirks) & (quirk))
10980
10981 PIPE_CONF_CHECK_I(cpu_transcoder);
10982
10983 PIPE_CONF_CHECK_I(has_pch_encoder);
10984 PIPE_CONF_CHECK_I(fdi_lanes);
10985 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10986 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10987 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10988 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10989 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10990
10991 PIPE_CONF_CHECK_I(has_dp_encoder);
10992
10993 if (INTEL_INFO(dev)->gen < 8) {
10994 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10995 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10996 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10997 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10998 PIPE_CONF_CHECK_I(dp_m_n.tu);
10999
11000 if (current_config->has_drrs) {
11001 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11002 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11003 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11004 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11005 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11006 }
11007 } else {
11008 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11009 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11010 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11011 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11012 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11013 }
11014
11015 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11016 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11017 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11018 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11019 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11020 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11021
11022 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11023 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11024 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11025 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11026 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11027 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11028
11029 PIPE_CONF_CHECK_I(pixel_multiplier);
11030 PIPE_CONF_CHECK_I(has_hdmi_sink);
11031 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11032 IS_VALLEYVIEW(dev))
11033 PIPE_CONF_CHECK_I(limited_color_range);
11034 PIPE_CONF_CHECK_I(has_infoframe);
11035
11036 PIPE_CONF_CHECK_I(has_audio);
11037
11038 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11039 DRM_MODE_FLAG_INTERLACE);
11040
11041 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11042 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11043 DRM_MODE_FLAG_PHSYNC);
11044 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11045 DRM_MODE_FLAG_NHSYNC);
11046 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11047 DRM_MODE_FLAG_PVSYNC);
11048 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11049 DRM_MODE_FLAG_NVSYNC);
11050 }
11051
11052 PIPE_CONF_CHECK_I(pipe_src_w);
11053 PIPE_CONF_CHECK_I(pipe_src_h);
11054
11055 /*
11056 * FIXME: BIOS likes to set up a cloned config with lvds+external
11057 * screen. Since we don't yet re-compute the pipe config when moving
11058 * just the lvds port away to another pipe the sw tracking won't match.
11059 *
11060 * Proper atomic modesets with recomputed global state will fix this.
11061 * Until then just don't check gmch state for inherited modes.
11062 */
11063 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11064 PIPE_CONF_CHECK_I(gmch_pfit.control);
11065 /* pfit ratios are autocomputed by the hw on gen4+ */
11066 if (INTEL_INFO(dev)->gen < 4)
11067 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11068 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11069 }
11070
11071 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11072 if (current_config->pch_pfit.enabled) {
11073 PIPE_CONF_CHECK_I(pch_pfit.pos);
11074 PIPE_CONF_CHECK_I(pch_pfit.size);
11075 }
11076
11077 /* BDW+ don't expose a synchronous way to read the state */
11078 if (IS_HASWELL(dev))
11079 PIPE_CONF_CHECK_I(ips_enabled);
11080
11081 PIPE_CONF_CHECK_I(double_wide);
11082
11083 PIPE_CONF_CHECK_X(ddi_pll_sel);
11084
11085 PIPE_CONF_CHECK_I(shared_dpll);
11086 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11087 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11088 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11089 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11090 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11091 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11092 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11093 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11094
11095 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11096 PIPE_CONF_CHECK_I(pipe_bpp);
11097
11098 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11099 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11100
11101 #undef PIPE_CONF_CHECK_X
11102 #undef PIPE_CONF_CHECK_I
11103 #undef PIPE_CONF_CHECK_I_ALT
11104 #undef PIPE_CONF_CHECK_FLAGS
11105 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11106 #undef PIPE_CONF_QUIRK
11107
11108 return true;
11109 }
11110
11111 static void check_wm_state(struct drm_device *dev)
11112 {
11113 struct drm_i915_private *dev_priv = dev->dev_private;
11114 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11115 struct intel_crtc *intel_crtc;
11116 int plane;
11117
11118 if (INTEL_INFO(dev)->gen < 9)
11119 return;
11120
11121 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11122 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11123
11124 for_each_intel_crtc(dev, intel_crtc) {
11125 struct skl_ddb_entry *hw_entry, *sw_entry;
11126 const enum pipe pipe = intel_crtc->pipe;
11127
11128 if (!intel_crtc->active)
11129 continue;
11130
11131 /* planes */
11132 for_each_plane(dev_priv, pipe, plane) {
11133 hw_entry = &hw_ddb.plane[pipe][plane];
11134 sw_entry = &sw_ddb->plane[pipe][plane];
11135
11136 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11137 continue;
11138
11139 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11140 "(expected (%u,%u), found (%u,%u))\n",
11141 pipe_name(pipe), plane + 1,
11142 sw_entry->start, sw_entry->end,
11143 hw_entry->start, hw_entry->end);
11144 }
11145
11146 /* cursor */
11147 hw_entry = &hw_ddb.cursor[pipe];
11148 sw_entry = &sw_ddb->cursor[pipe];
11149
11150 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11151 continue;
11152
11153 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11154 "(expected (%u,%u), found (%u,%u))\n",
11155 pipe_name(pipe),
11156 sw_entry->start, sw_entry->end,
11157 hw_entry->start, hw_entry->end);
11158 }
11159 }
11160
11161 static void
11162 check_connector_state(struct drm_device *dev)
11163 {
11164 struct intel_connector *connector;
11165
11166 for_each_intel_connector(dev, connector) {
11167 /* This also checks the encoder/connector hw state with the
11168 * ->get_hw_state callbacks. */
11169 intel_connector_check_state(connector);
11170
11171 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11172 "connector's staged encoder doesn't match current encoder\n");
11173 }
11174 }
11175
11176 static void
11177 check_encoder_state(struct drm_device *dev)
11178 {
11179 struct intel_encoder *encoder;
11180 struct intel_connector *connector;
11181
11182 for_each_intel_encoder(dev, encoder) {
11183 bool enabled = false;
11184 bool active = false;
11185 enum pipe pipe, tracked_pipe;
11186
11187 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11188 encoder->base.base.id,
11189 encoder->base.name);
11190
11191 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11192 "encoder's stage crtc doesn't match current crtc\n");
11193 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11194 "encoder's active_connectors set, but no crtc\n");
11195
11196 for_each_intel_connector(dev, connector) {
11197 if (connector->base.encoder != &encoder->base)
11198 continue;
11199 enabled = true;
11200 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11201 active = true;
11202 }
11203 /*
11204 * for MST connectors if we unplug the connector is gone
11205 * away but the encoder is still connected to a crtc
11206 * until a modeset happens in response to the hotplug.
11207 */
11208 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11209 continue;
11210
11211 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11212 "encoder's enabled state mismatch "
11213 "(expected %i, found %i)\n",
11214 !!encoder->base.crtc, enabled);
11215 I915_STATE_WARN(active && !encoder->base.crtc,
11216 "active encoder with no crtc\n");
11217
11218 I915_STATE_WARN(encoder->connectors_active != active,
11219 "encoder's computed active state doesn't match tracked active state "
11220 "(expected %i, found %i)\n", active, encoder->connectors_active);
11221
11222 active = encoder->get_hw_state(encoder, &pipe);
11223 I915_STATE_WARN(active != encoder->connectors_active,
11224 "encoder's hw state doesn't match sw tracking "
11225 "(expected %i, found %i)\n",
11226 encoder->connectors_active, active);
11227
11228 if (!encoder->base.crtc)
11229 continue;
11230
11231 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11232 I915_STATE_WARN(active && pipe != tracked_pipe,
11233 "active encoder's pipe doesn't match"
11234 "(expected %i, found %i)\n",
11235 tracked_pipe, pipe);
11236
11237 }
11238 }
11239
11240 static void
11241 check_crtc_state(struct drm_device *dev)
11242 {
11243 struct drm_i915_private *dev_priv = dev->dev_private;
11244 struct intel_crtc *crtc;
11245 struct intel_encoder *encoder;
11246 struct intel_crtc_state pipe_config;
11247
11248 for_each_intel_crtc(dev, crtc) {
11249 bool enabled = false;
11250 bool active = false;
11251
11252 memset(&pipe_config, 0, sizeof(pipe_config));
11253
11254 DRM_DEBUG_KMS("[CRTC:%d]\n",
11255 crtc->base.base.id);
11256
11257 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11258 "active crtc, but not enabled in sw tracking\n");
11259
11260 for_each_intel_encoder(dev, encoder) {
11261 if (encoder->base.crtc != &crtc->base)
11262 continue;
11263 enabled = true;
11264 if (encoder->connectors_active)
11265 active = true;
11266 }
11267
11268 I915_STATE_WARN(active != crtc->active,
11269 "crtc's computed active state doesn't match tracked active state "
11270 "(expected %i, found %i)\n", active, crtc->active);
11271 I915_STATE_WARN(enabled != crtc->base.state->enable,
11272 "crtc's computed enabled state doesn't match tracked enabled state "
11273 "(expected %i, found %i)\n", enabled,
11274 crtc->base.state->enable);
11275
11276 active = dev_priv->display.get_pipe_config(crtc,
11277 &pipe_config);
11278
11279 /* hw state is inconsistent with the pipe quirk */
11280 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11281 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11282 active = crtc->active;
11283
11284 for_each_intel_encoder(dev, encoder) {
11285 enum pipe pipe;
11286 if (encoder->base.crtc != &crtc->base)
11287 continue;
11288 if (encoder->get_hw_state(encoder, &pipe))
11289 encoder->get_config(encoder, &pipe_config);
11290 }
11291
11292 I915_STATE_WARN(crtc->active != active,
11293 "crtc active state doesn't match with hw state "
11294 "(expected %i, found %i)\n", crtc->active, active);
11295
11296 if (active &&
11297 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11298 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11299 intel_dump_pipe_config(crtc, &pipe_config,
11300 "[hw state]");
11301 intel_dump_pipe_config(crtc, crtc->config,
11302 "[sw state]");
11303 }
11304 }
11305 }
11306
11307 static void
11308 check_shared_dpll_state(struct drm_device *dev)
11309 {
11310 struct drm_i915_private *dev_priv = dev->dev_private;
11311 struct intel_crtc *crtc;
11312 struct intel_dpll_hw_state dpll_hw_state;
11313 int i;
11314
11315 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11316 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11317 int enabled_crtcs = 0, active_crtcs = 0;
11318 bool active;
11319
11320 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11321
11322 DRM_DEBUG_KMS("%s\n", pll->name);
11323
11324 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11325
11326 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11327 "more active pll users than references: %i vs %i\n",
11328 pll->active, hweight32(pll->config.crtc_mask));
11329 I915_STATE_WARN(pll->active && !pll->on,
11330 "pll in active use but not on in sw tracking\n");
11331 I915_STATE_WARN(pll->on && !pll->active,
11332 "pll in on but not on in use in sw tracking\n");
11333 I915_STATE_WARN(pll->on != active,
11334 "pll on state mismatch (expected %i, found %i)\n",
11335 pll->on, active);
11336
11337 for_each_intel_crtc(dev, crtc) {
11338 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11339 enabled_crtcs++;
11340 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11341 active_crtcs++;
11342 }
11343 I915_STATE_WARN(pll->active != active_crtcs,
11344 "pll active crtcs mismatch (expected %i, found %i)\n",
11345 pll->active, active_crtcs);
11346 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11347 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11348 hweight32(pll->config.crtc_mask), enabled_crtcs);
11349
11350 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11351 sizeof(dpll_hw_state)),
11352 "pll hw state mismatch\n");
11353 }
11354 }
11355
11356 void
11357 intel_modeset_check_state(struct drm_device *dev)
11358 {
11359 check_wm_state(dev);
11360 check_connector_state(dev);
11361 check_encoder_state(dev);
11362 check_crtc_state(dev);
11363 check_shared_dpll_state(dev);
11364 }
11365
11366 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11367 int dotclock)
11368 {
11369 /*
11370 * FDI already provided one idea for the dotclock.
11371 * Yell if the encoder disagrees.
11372 */
11373 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11374 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11375 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11376 }
11377
11378 static void update_scanline_offset(struct intel_crtc *crtc)
11379 {
11380 struct drm_device *dev = crtc->base.dev;
11381
11382 /*
11383 * The scanline counter increments at the leading edge of hsync.
11384 *
11385 * On most platforms it starts counting from vtotal-1 on the
11386 * first active line. That means the scanline counter value is
11387 * always one less than what we would expect. Ie. just after
11388 * start of vblank, which also occurs at start of hsync (on the
11389 * last active line), the scanline counter will read vblank_start-1.
11390 *
11391 * On gen2 the scanline counter starts counting from 1 instead
11392 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11393 * to keep the value positive), instead of adding one.
11394 *
11395 * On HSW+ the behaviour of the scanline counter depends on the output
11396 * type. For DP ports it behaves like most other platforms, but on HDMI
11397 * there's an extra 1 line difference. So we need to add two instead of
11398 * one to the value.
11399 */
11400 if (IS_GEN2(dev)) {
11401 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11402 int vtotal;
11403
11404 vtotal = mode->crtc_vtotal;
11405 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11406 vtotal /= 2;
11407
11408 crtc->scanline_offset = vtotal - 1;
11409 } else if (HAS_DDI(dev) &&
11410 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11411 crtc->scanline_offset = 2;
11412 } else
11413 crtc->scanline_offset = 1;
11414 }
11415
11416 static struct intel_crtc_state *
11417 intel_modeset_compute_config(struct drm_crtc *crtc,
11418 struct drm_display_mode *mode,
11419 struct drm_framebuffer *fb,
11420 struct drm_atomic_state *state,
11421 unsigned *modeset_pipes,
11422 unsigned *prepare_pipes,
11423 unsigned *disable_pipes)
11424 {
11425 struct drm_device *dev = crtc->dev;
11426 struct intel_crtc_state *pipe_config = NULL;
11427 struct intel_crtc *intel_crtc;
11428 int ret = 0;
11429
11430 ret = drm_atomic_add_affected_connectors(state, crtc);
11431 if (ret)
11432 return ERR_PTR(ret);
11433
11434 intel_modeset_affected_pipes(crtc, modeset_pipes,
11435 prepare_pipes, disable_pipes);
11436
11437 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11438 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11439 if (IS_ERR(pipe_config))
11440 return pipe_config;
11441
11442 pipe_config->base.enable = false;
11443 }
11444
11445 /*
11446 * Note this needs changes when we start tracking multiple modes
11447 * and crtcs. At that point we'll need to compute the whole config
11448 * (i.e. one pipe_config for each crtc) rather than just the one
11449 * for this crtc.
11450 */
11451 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11452 /* FIXME: For now we still expect modeset_pipes has at most
11453 * one bit set. */
11454 if (WARN_ON(&intel_crtc->base != crtc))
11455 continue;
11456
11457 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11458 if (IS_ERR(pipe_config))
11459 return pipe_config;
11460
11461 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11462 "[modeset]");
11463 }
11464
11465 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
11466 }
11467
11468 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11469 unsigned modeset_pipes,
11470 unsigned disable_pipes)
11471 {
11472 struct drm_i915_private *dev_priv = to_i915(dev);
11473 unsigned clear_pipes = modeset_pipes | disable_pipes;
11474 struct intel_crtc *intel_crtc;
11475 int ret = 0;
11476
11477 if (!dev_priv->display.crtc_compute_clock)
11478 return 0;
11479
11480 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11481 if (ret)
11482 goto done;
11483
11484 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11485 struct intel_crtc_state *state = intel_crtc->new_config;
11486 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11487 state);
11488 if (ret) {
11489 intel_shared_dpll_abort_config(dev_priv);
11490 goto done;
11491 }
11492 }
11493
11494 done:
11495 return ret;
11496 }
11497
11498 static int __intel_set_mode(struct drm_crtc *crtc,
11499 struct drm_display_mode *mode,
11500 int x, int y, struct drm_framebuffer *fb,
11501 struct intel_crtc_state *pipe_config,
11502 unsigned modeset_pipes,
11503 unsigned prepare_pipes,
11504 unsigned disable_pipes)
11505 {
11506 struct drm_device *dev = crtc->dev;
11507 struct drm_i915_private *dev_priv = dev->dev_private;
11508 struct drm_display_mode *saved_mode;
11509 struct intel_crtc_state *crtc_state_copy = NULL;
11510 struct intel_crtc *intel_crtc;
11511 int ret = 0;
11512
11513 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11514 if (!saved_mode)
11515 return -ENOMEM;
11516
11517 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11518 if (!crtc_state_copy) {
11519 ret = -ENOMEM;
11520 goto done;
11521 }
11522
11523 *saved_mode = crtc->mode;
11524
11525 if (modeset_pipes)
11526 to_intel_crtc(crtc)->new_config = pipe_config;
11527
11528 /*
11529 * See if the config requires any additional preparation, e.g.
11530 * to adjust global state with pipes off. We need to do this
11531 * here so we can get the modeset_pipe updated config for the new
11532 * mode set on this crtc. For other crtcs we need to use the
11533 * adjusted_mode bits in the crtc directly.
11534 */
11535 if (IS_VALLEYVIEW(dev)) {
11536 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11537
11538 /* may have added more to prepare_pipes than we should */
11539 prepare_pipes &= ~disable_pipes;
11540 }
11541
11542 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11543 if (ret)
11544 goto done;
11545
11546 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11547 intel_crtc_disable(&intel_crtc->base);
11548
11549 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11550 if (intel_crtc->base.state->enable)
11551 dev_priv->display.crtc_disable(&intel_crtc->base);
11552 }
11553
11554 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11555 * to set it here already despite that we pass it down the callchain.
11556 *
11557 * Note we'll need to fix this up when we start tracking multiple
11558 * pipes; here we assume a single modeset_pipe and only track the
11559 * single crtc and mode.
11560 */
11561 if (modeset_pipes) {
11562 crtc->mode = *mode;
11563 /* mode_set/enable/disable functions rely on a correct pipe
11564 * config. */
11565 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11566
11567 /*
11568 * Calculate and store various constants which
11569 * are later needed by vblank and swap-completion
11570 * timestamping. They are derived from true hwmode.
11571 */
11572 drm_calc_timestamping_constants(crtc,
11573 &pipe_config->base.adjusted_mode);
11574 }
11575
11576 /* Only after disabling all output pipelines that will be changed can we
11577 * update the the output configuration. */
11578 intel_modeset_update_state(dev, prepare_pipes);
11579
11580 modeset_update_crtc_power_domains(pipe_config->base.state);
11581
11582 /* Set up the DPLL and any encoders state that needs to adjust or depend
11583 * on the DPLL.
11584 */
11585 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11586 struct drm_plane *primary = intel_crtc->base.primary;
11587 int vdisplay, hdisplay;
11588
11589 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11590 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11591 fb, 0, 0,
11592 hdisplay, vdisplay,
11593 x << 16, y << 16,
11594 hdisplay << 16, vdisplay << 16);
11595 }
11596
11597 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11598 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11599 update_scanline_offset(intel_crtc);
11600
11601 dev_priv->display.crtc_enable(&intel_crtc->base);
11602 }
11603
11604 /* FIXME: add subpixel order */
11605 done:
11606 if (ret && crtc->state->enable)
11607 crtc->mode = *saved_mode;
11608
11609 if (ret == 0 && pipe_config) {
11610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11611
11612 /* The pipe_config will be freed with the atomic state, so
11613 * make a copy. */
11614 memcpy(crtc_state_copy, intel_crtc->config,
11615 sizeof *crtc_state_copy);
11616 intel_crtc->config = crtc_state_copy;
11617 intel_crtc->base.state = &crtc_state_copy->base;
11618
11619 if (modeset_pipes)
11620 intel_crtc->new_config = intel_crtc->config;
11621 } else {
11622 kfree(crtc_state_copy);
11623 }
11624
11625 kfree(saved_mode);
11626 return ret;
11627 }
11628
11629 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11630 struct drm_display_mode *mode,
11631 int x, int y, struct drm_framebuffer *fb,
11632 struct intel_crtc_state *pipe_config,
11633 unsigned modeset_pipes,
11634 unsigned prepare_pipes,
11635 unsigned disable_pipes)
11636 {
11637 int ret;
11638
11639 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11640 prepare_pipes, disable_pipes);
11641
11642 if (ret == 0)
11643 intel_modeset_check_state(crtc->dev);
11644
11645 return ret;
11646 }
11647
11648 static int intel_set_mode(struct drm_crtc *crtc,
11649 struct drm_display_mode *mode,
11650 int x, int y, struct drm_framebuffer *fb,
11651 struct drm_atomic_state *state)
11652 {
11653 struct intel_crtc_state *pipe_config;
11654 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11655 int ret = 0;
11656
11657 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
11658 &modeset_pipes,
11659 &prepare_pipes,
11660 &disable_pipes);
11661
11662 if (IS_ERR(pipe_config)) {
11663 ret = PTR_ERR(pipe_config);
11664 goto out;
11665 }
11666
11667 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11668 modeset_pipes, prepare_pipes,
11669 disable_pipes);
11670 if (ret)
11671 goto out;
11672
11673 out:
11674 return ret;
11675 }
11676
11677 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11678 {
11679 struct drm_device *dev = crtc->dev;
11680 struct drm_atomic_state *state;
11681 struct intel_encoder *encoder;
11682 struct intel_connector *connector;
11683 struct drm_connector_state *connector_state;
11684
11685 state = drm_atomic_state_alloc(dev);
11686 if (!state) {
11687 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11688 crtc->base.id);
11689 return;
11690 }
11691
11692 state->acquire_ctx = dev->mode_config.acquire_ctx;
11693
11694 /* The force restore path in the HW readout code relies on the staged
11695 * config still keeping the user requested config while the actual
11696 * state has been overwritten by the configuration read from HW. We
11697 * need to copy the staged config to the atomic state, otherwise the
11698 * mode set will just reapply the state the HW is already in. */
11699 for_each_intel_encoder(dev, encoder) {
11700 if (&encoder->new_crtc->base != crtc)
11701 continue;
11702
11703 for_each_intel_connector(dev, connector) {
11704 if (connector->new_encoder != encoder)
11705 continue;
11706
11707 connector_state = drm_atomic_get_connector_state(state, &connector->base);
11708 if (IS_ERR(connector_state)) {
11709 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11710 connector->base.base.id,
11711 connector->base.name,
11712 PTR_ERR(connector_state));
11713 continue;
11714 }
11715
11716 connector_state->crtc = crtc;
11717 connector_state->best_encoder = &encoder->base;
11718 }
11719 }
11720
11721 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11722 state);
11723
11724 drm_atomic_state_free(state);
11725 }
11726
11727 #undef for_each_intel_crtc_masked
11728
11729 static void intel_set_config_free(struct intel_set_config *config)
11730 {
11731 if (!config)
11732 return;
11733
11734 kfree(config->save_connector_encoders);
11735 kfree(config->save_encoder_crtcs);
11736 kfree(config->save_crtc_enabled);
11737 kfree(config);
11738 }
11739
11740 static int intel_set_config_save_state(struct drm_device *dev,
11741 struct intel_set_config *config)
11742 {
11743 struct drm_crtc *crtc;
11744 struct drm_encoder *encoder;
11745 struct drm_connector *connector;
11746 int count;
11747
11748 config->save_crtc_enabled =
11749 kcalloc(dev->mode_config.num_crtc,
11750 sizeof(bool), GFP_KERNEL);
11751 if (!config->save_crtc_enabled)
11752 return -ENOMEM;
11753
11754 config->save_encoder_crtcs =
11755 kcalloc(dev->mode_config.num_encoder,
11756 sizeof(struct drm_crtc *), GFP_KERNEL);
11757 if (!config->save_encoder_crtcs)
11758 return -ENOMEM;
11759
11760 config->save_connector_encoders =
11761 kcalloc(dev->mode_config.num_connector,
11762 sizeof(struct drm_encoder *), GFP_KERNEL);
11763 if (!config->save_connector_encoders)
11764 return -ENOMEM;
11765
11766 /* Copy data. Note that driver private data is not affected.
11767 * Should anything bad happen only the expected state is
11768 * restored, not the drivers personal bookkeeping.
11769 */
11770 count = 0;
11771 for_each_crtc(dev, crtc) {
11772 config->save_crtc_enabled[count++] = crtc->state->enable;
11773 }
11774
11775 count = 0;
11776 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11777 config->save_encoder_crtcs[count++] = encoder->crtc;
11778 }
11779
11780 count = 0;
11781 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11782 config->save_connector_encoders[count++] = connector->encoder;
11783 }
11784
11785 return 0;
11786 }
11787
11788 static void intel_set_config_restore_state(struct drm_device *dev,
11789 struct intel_set_config *config)
11790 {
11791 struct intel_crtc *crtc;
11792 struct intel_encoder *encoder;
11793 struct intel_connector *connector;
11794 int count;
11795
11796 count = 0;
11797 for_each_intel_crtc(dev, crtc) {
11798 crtc->new_enabled = config->save_crtc_enabled[count++];
11799
11800 if (crtc->new_enabled)
11801 crtc->new_config = crtc->config;
11802 else
11803 crtc->new_config = NULL;
11804 }
11805
11806 count = 0;
11807 for_each_intel_encoder(dev, encoder) {
11808 encoder->new_crtc =
11809 to_intel_crtc(config->save_encoder_crtcs[count++]);
11810 }
11811
11812 count = 0;
11813 for_each_intel_connector(dev, connector) {
11814 connector->new_encoder =
11815 to_intel_encoder(config->save_connector_encoders[count++]);
11816 }
11817 }
11818
11819 static bool
11820 is_crtc_connector_off(struct drm_mode_set *set)
11821 {
11822 int i;
11823
11824 if (set->num_connectors == 0)
11825 return false;
11826
11827 if (WARN_ON(set->connectors == NULL))
11828 return false;
11829
11830 for (i = 0; i < set->num_connectors; i++)
11831 if (set->connectors[i]->encoder &&
11832 set->connectors[i]->encoder->crtc == set->crtc &&
11833 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11834 return true;
11835
11836 return false;
11837 }
11838
11839 static void
11840 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11841 struct intel_set_config *config)
11842 {
11843
11844 /* We should be able to check here if the fb has the same properties
11845 * and then just flip_or_move it */
11846 if (is_crtc_connector_off(set)) {
11847 config->mode_changed = true;
11848 } else if (set->crtc->primary->fb != set->fb) {
11849 /*
11850 * If we have no fb, we can only flip as long as the crtc is
11851 * active, otherwise we need a full mode set. The crtc may
11852 * be active if we've only disabled the primary plane, or
11853 * in fastboot situations.
11854 */
11855 if (set->crtc->primary->fb == NULL) {
11856 struct intel_crtc *intel_crtc =
11857 to_intel_crtc(set->crtc);
11858
11859 if (intel_crtc->active) {
11860 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11861 config->fb_changed = true;
11862 } else {
11863 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11864 config->mode_changed = true;
11865 }
11866 } else if (set->fb == NULL) {
11867 config->mode_changed = true;
11868 } else if (set->fb->pixel_format !=
11869 set->crtc->primary->fb->pixel_format) {
11870 config->mode_changed = true;
11871 } else {
11872 config->fb_changed = true;
11873 }
11874 }
11875
11876 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11877 config->fb_changed = true;
11878
11879 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11880 DRM_DEBUG_KMS("modes are different, full mode set\n");
11881 drm_mode_debug_printmodeline(&set->crtc->mode);
11882 drm_mode_debug_printmodeline(set->mode);
11883 config->mode_changed = true;
11884 }
11885
11886 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11887 set->crtc->base.id, config->mode_changed, config->fb_changed);
11888 }
11889
11890 static int
11891 intel_modeset_stage_output_state(struct drm_device *dev,
11892 struct drm_mode_set *set,
11893 struct intel_set_config *config,
11894 struct drm_atomic_state *state)
11895 {
11896 struct intel_connector *connector;
11897 struct drm_connector_state *connector_state;
11898 struct intel_encoder *encoder;
11899 struct intel_crtc *crtc;
11900 int ro;
11901
11902 /* The upper layers ensure that we either disable a crtc or have a list
11903 * of connectors. For paranoia, double-check this. */
11904 WARN_ON(!set->fb && (set->num_connectors != 0));
11905 WARN_ON(set->fb && (set->num_connectors == 0));
11906
11907 for_each_intel_connector(dev, connector) {
11908 /* Otherwise traverse passed in connector list and get encoders
11909 * for them. */
11910 for (ro = 0; ro < set->num_connectors; ro++) {
11911 if (set->connectors[ro] == &connector->base) {
11912 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11913 break;
11914 }
11915 }
11916
11917 /* If we disable the crtc, disable all its connectors. Also, if
11918 * the connector is on the changing crtc but not on the new
11919 * connector list, disable it. */
11920 if ((!set->fb || ro == set->num_connectors) &&
11921 connector->base.encoder &&
11922 connector->base.encoder->crtc == set->crtc) {
11923 connector->new_encoder = NULL;
11924
11925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11926 connector->base.base.id,
11927 connector->base.name);
11928 }
11929
11930
11931 if (&connector->new_encoder->base != connector->base.encoder) {
11932 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11933 connector->base.base.id,
11934 connector->base.name);
11935 config->mode_changed = true;
11936 }
11937 }
11938 /* connector->new_encoder is now updated for all connectors. */
11939
11940 /* Update crtc of enabled connectors. */
11941 for_each_intel_connector(dev, connector) {
11942 struct drm_crtc *new_crtc;
11943
11944 if (!connector->new_encoder)
11945 continue;
11946
11947 new_crtc = connector->new_encoder->base.crtc;
11948
11949 for (ro = 0; ro < set->num_connectors; ro++) {
11950 if (set->connectors[ro] == &connector->base)
11951 new_crtc = set->crtc;
11952 }
11953
11954 /* Make sure the new CRTC will work with the encoder */
11955 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11956 new_crtc)) {
11957 return -EINVAL;
11958 }
11959 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11960
11961 connector_state =
11962 drm_atomic_get_connector_state(state, &connector->base);
11963 if (IS_ERR(connector_state))
11964 return PTR_ERR(connector_state);
11965
11966 connector_state->crtc = new_crtc;
11967 connector_state->best_encoder = &connector->new_encoder->base;
11968
11969 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11970 connector->base.base.id,
11971 connector->base.name,
11972 new_crtc->base.id);
11973 }
11974
11975 /* Check for any encoders that needs to be disabled. */
11976 for_each_intel_encoder(dev, encoder) {
11977 int num_connectors = 0;
11978 for_each_intel_connector(dev, connector) {
11979 if (connector->new_encoder == encoder) {
11980 WARN_ON(!connector->new_encoder->new_crtc);
11981 num_connectors++;
11982 }
11983 }
11984
11985 if (num_connectors == 0)
11986 encoder->new_crtc = NULL;
11987 else if (num_connectors > 1)
11988 return -EINVAL;
11989
11990 /* Only now check for crtc changes so we don't miss encoders
11991 * that will be disabled. */
11992 if (&encoder->new_crtc->base != encoder->base.crtc) {
11993 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11994 encoder->base.base.id,
11995 encoder->base.name);
11996 config->mode_changed = true;
11997 }
11998 }
11999 /* Now we've also updated encoder->new_crtc for all encoders. */
12000 for_each_intel_connector(dev, connector) {
12001 connector_state =
12002 drm_atomic_get_connector_state(state, &connector->base);
12003 if (IS_ERR(connector_state))
12004 return PTR_ERR(connector_state);
12005
12006 if (connector->new_encoder) {
12007 if (connector->new_encoder != connector->encoder)
12008 connector->encoder = connector->new_encoder;
12009 } else {
12010 connector_state->crtc = NULL;
12011 }
12012 }
12013 for_each_intel_crtc(dev, crtc) {
12014 crtc->new_enabled = false;
12015
12016 for_each_intel_encoder(dev, encoder) {
12017 if (encoder->new_crtc == crtc) {
12018 crtc->new_enabled = true;
12019 break;
12020 }
12021 }
12022
12023 if (crtc->new_enabled != crtc->base.state->enable) {
12024 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12025 crtc->base.base.id,
12026 crtc->new_enabled ? "en" : "dis");
12027 config->mode_changed = true;
12028 }
12029
12030 if (crtc->new_enabled)
12031 crtc->new_config = crtc->config;
12032 else
12033 crtc->new_config = NULL;
12034 }
12035
12036 return 0;
12037 }
12038
12039 static void disable_crtc_nofb(struct intel_crtc *crtc)
12040 {
12041 struct drm_device *dev = crtc->base.dev;
12042 struct intel_encoder *encoder;
12043 struct intel_connector *connector;
12044
12045 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12046 pipe_name(crtc->pipe));
12047
12048 for_each_intel_connector(dev, connector) {
12049 if (connector->new_encoder &&
12050 connector->new_encoder->new_crtc == crtc)
12051 connector->new_encoder = NULL;
12052 }
12053
12054 for_each_intel_encoder(dev, encoder) {
12055 if (encoder->new_crtc == crtc)
12056 encoder->new_crtc = NULL;
12057 }
12058
12059 crtc->new_enabled = false;
12060 crtc->new_config = NULL;
12061 }
12062
12063 static int intel_crtc_set_config(struct drm_mode_set *set)
12064 {
12065 struct drm_device *dev;
12066 struct drm_mode_set save_set;
12067 struct drm_atomic_state *state = NULL;
12068 struct intel_set_config *config;
12069 struct intel_crtc_state *pipe_config;
12070 unsigned modeset_pipes, prepare_pipes, disable_pipes;
12071 int ret;
12072
12073 BUG_ON(!set);
12074 BUG_ON(!set->crtc);
12075 BUG_ON(!set->crtc->helper_private);
12076
12077 /* Enforce sane interface api - has been abused by the fb helper. */
12078 BUG_ON(!set->mode && set->fb);
12079 BUG_ON(set->fb && set->num_connectors == 0);
12080
12081 if (set->fb) {
12082 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12083 set->crtc->base.id, set->fb->base.id,
12084 (int)set->num_connectors, set->x, set->y);
12085 } else {
12086 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12087 }
12088
12089 dev = set->crtc->dev;
12090
12091 ret = -ENOMEM;
12092 config = kzalloc(sizeof(*config), GFP_KERNEL);
12093 if (!config)
12094 goto out_config;
12095
12096 ret = intel_set_config_save_state(dev, config);
12097 if (ret)
12098 goto out_config;
12099
12100 save_set.crtc = set->crtc;
12101 save_set.mode = &set->crtc->mode;
12102 save_set.x = set->crtc->x;
12103 save_set.y = set->crtc->y;
12104 save_set.fb = set->crtc->primary->fb;
12105
12106 /* Compute whether we need a full modeset, only an fb base update or no
12107 * change at all. In the future we might also check whether only the
12108 * mode changed, e.g. for LVDS where we only change the panel fitter in
12109 * such cases. */
12110 intel_set_config_compute_mode_changes(set, config);
12111
12112 state = drm_atomic_state_alloc(dev);
12113 if (!state) {
12114 ret = -ENOMEM;
12115 goto out_config;
12116 }
12117
12118 state->acquire_ctx = dev->mode_config.acquire_ctx;
12119
12120 ret = intel_modeset_stage_output_state(dev, set, config, state);
12121 if (ret)
12122 goto fail;
12123
12124 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
12125 set->fb, state,
12126 &modeset_pipes,
12127 &prepare_pipes,
12128 &disable_pipes);
12129 if (IS_ERR(pipe_config)) {
12130 ret = PTR_ERR(pipe_config);
12131 goto fail;
12132 } else if (pipe_config) {
12133 if (pipe_config->has_audio !=
12134 to_intel_crtc(set->crtc)->config->has_audio)
12135 config->mode_changed = true;
12136
12137 /*
12138 * Note we have an issue here with infoframes: current code
12139 * only updates them on the full mode set path per hw
12140 * requirements. So here we should be checking for any
12141 * required changes and forcing a mode set.
12142 */
12143 }
12144
12145 intel_update_pipe_size(to_intel_crtc(set->crtc));
12146
12147 if (config->mode_changed) {
12148 ret = intel_set_mode_pipes(set->crtc, set->mode,
12149 set->x, set->y, set->fb, pipe_config,
12150 modeset_pipes, prepare_pipes,
12151 disable_pipes);
12152 } else if (config->fb_changed) {
12153 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12154 struct drm_plane *primary = set->crtc->primary;
12155 int vdisplay, hdisplay;
12156
12157 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12158 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
12159 0, 0, hdisplay, vdisplay,
12160 set->x << 16, set->y << 16,
12161 hdisplay << 16, vdisplay << 16);
12162
12163 /*
12164 * We need to make sure the primary plane is re-enabled if it
12165 * has previously been turned off.
12166 */
12167 if (!intel_crtc->primary_enabled && ret == 0) {
12168 WARN_ON(!intel_crtc->active);
12169 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
12170 }
12171
12172 /*
12173 * In the fastboot case this may be our only check of the
12174 * state after boot. It would be better to only do it on
12175 * the first update, but we don't have a nice way of doing that
12176 * (and really, set_config isn't used much for high freq page
12177 * flipping, so increasing its cost here shouldn't be a big
12178 * deal).
12179 */
12180 if (i915.fastboot && ret == 0)
12181 intel_modeset_check_state(set->crtc->dev);
12182 }
12183
12184 if (ret) {
12185 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12186 set->crtc->base.id, ret);
12187 fail:
12188 intel_set_config_restore_state(dev, config);
12189
12190 drm_atomic_state_clear(state);
12191
12192 /*
12193 * HACK: if the pipe was on, but we didn't have a framebuffer,
12194 * force the pipe off to avoid oopsing in the modeset code
12195 * due to fb==NULL. This should only happen during boot since
12196 * we don't yet reconstruct the FB from the hardware state.
12197 */
12198 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12199 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12200
12201 /* Try to restore the config */
12202 if (config->mode_changed &&
12203 intel_set_mode(save_set.crtc, save_set.mode,
12204 save_set.x, save_set.y, save_set.fb,
12205 state))
12206 DRM_ERROR("failed to restore config after modeset failure\n");
12207 }
12208
12209 out_config:
12210 if (state)
12211 drm_atomic_state_free(state);
12212
12213 intel_set_config_free(config);
12214 return ret;
12215 }
12216
12217 static const struct drm_crtc_funcs intel_crtc_funcs = {
12218 .gamma_set = intel_crtc_gamma_set,
12219 .set_config = intel_crtc_set_config,
12220 .destroy = intel_crtc_destroy,
12221 .page_flip = intel_crtc_page_flip,
12222 .atomic_duplicate_state = intel_crtc_duplicate_state,
12223 .atomic_destroy_state = intel_crtc_destroy_state,
12224 };
12225
12226 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12227 struct intel_shared_dpll *pll,
12228 struct intel_dpll_hw_state *hw_state)
12229 {
12230 uint32_t val;
12231
12232 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12233 return false;
12234
12235 val = I915_READ(PCH_DPLL(pll->id));
12236 hw_state->dpll = val;
12237 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12238 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12239
12240 return val & DPLL_VCO_ENABLE;
12241 }
12242
12243 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12244 struct intel_shared_dpll *pll)
12245 {
12246 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12247 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12248 }
12249
12250 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12251 struct intel_shared_dpll *pll)
12252 {
12253 /* PCH refclock must be enabled first */
12254 ibx_assert_pch_refclk_enabled(dev_priv);
12255
12256 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12257
12258 /* Wait for the clocks to stabilize. */
12259 POSTING_READ(PCH_DPLL(pll->id));
12260 udelay(150);
12261
12262 /* The pixel multiplier can only be updated once the
12263 * DPLL is enabled and the clocks are stable.
12264 *
12265 * So write it again.
12266 */
12267 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12268 POSTING_READ(PCH_DPLL(pll->id));
12269 udelay(200);
12270 }
12271
12272 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12273 struct intel_shared_dpll *pll)
12274 {
12275 struct drm_device *dev = dev_priv->dev;
12276 struct intel_crtc *crtc;
12277
12278 /* Make sure no transcoder isn't still depending on us. */
12279 for_each_intel_crtc(dev, crtc) {
12280 if (intel_crtc_to_shared_dpll(crtc) == pll)
12281 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12282 }
12283
12284 I915_WRITE(PCH_DPLL(pll->id), 0);
12285 POSTING_READ(PCH_DPLL(pll->id));
12286 udelay(200);
12287 }
12288
12289 static char *ibx_pch_dpll_names[] = {
12290 "PCH DPLL A",
12291 "PCH DPLL B",
12292 };
12293
12294 static void ibx_pch_dpll_init(struct drm_device *dev)
12295 {
12296 struct drm_i915_private *dev_priv = dev->dev_private;
12297 int i;
12298
12299 dev_priv->num_shared_dpll = 2;
12300
12301 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12302 dev_priv->shared_dplls[i].id = i;
12303 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12304 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12305 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12306 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12307 dev_priv->shared_dplls[i].get_hw_state =
12308 ibx_pch_dpll_get_hw_state;
12309 }
12310 }
12311
12312 static void intel_shared_dpll_init(struct drm_device *dev)
12313 {
12314 struct drm_i915_private *dev_priv = dev->dev_private;
12315
12316 if (HAS_DDI(dev))
12317 intel_ddi_pll_init(dev);
12318 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12319 ibx_pch_dpll_init(dev);
12320 else
12321 dev_priv->num_shared_dpll = 0;
12322
12323 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12324 }
12325
12326 /**
12327 * intel_wm_need_update - Check whether watermarks need updating
12328 * @plane: drm plane
12329 * @state: new plane state
12330 *
12331 * Check current plane state versus the new one to determine whether
12332 * watermarks need to be recalculated.
12333 *
12334 * Returns true or false.
12335 */
12336 bool intel_wm_need_update(struct drm_plane *plane,
12337 struct drm_plane_state *state)
12338 {
12339 /* Update watermarks on tiling changes. */
12340 if (!plane->state->fb || !state->fb ||
12341 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12342 plane->state->rotation != state->rotation)
12343 return true;
12344
12345 return false;
12346 }
12347
12348 /**
12349 * intel_prepare_plane_fb - Prepare fb for usage on plane
12350 * @plane: drm plane to prepare for
12351 * @fb: framebuffer to prepare for presentation
12352 *
12353 * Prepares a framebuffer for usage on a display plane. Generally this
12354 * involves pinning the underlying object and updating the frontbuffer tracking
12355 * bits. Some older platforms need special physical address handling for
12356 * cursor planes.
12357 *
12358 * Returns 0 on success, negative error code on failure.
12359 */
12360 int
12361 intel_prepare_plane_fb(struct drm_plane *plane,
12362 struct drm_framebuffer *fb,
12363 const struct drm_plane_state *new_state)
12364 {
12365 struct drm_device *dev = plane->dev;
12366 struct intel_plane *intel_plane = to_intel_plane(plane);
12367 enum pipe pipe = intel_plane->pipe;
12368 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12369 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12370 unsigned frontbuffer_bits = 0;
12371 int ret = 0;
12372
12373 if (!obj)
12374 return 0;
12375
12376 switch (plane->type) {
12377 case DRM_PLANE_TYPE_PRIMARY:
12378 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12379 break;
12380 case DRM_PLANE_TYPE_CURSOR:
12381 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12382 break;
12383 case DRM_PLANE_TYPE_OVERLAY:
12384 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12385 break;
12386 }
12387
12388 mutex_lock(&dev->struct_mutex);
12389
12390 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12391 INTEL_INFO(dev)->cursor_needs_physical) {
12392 int align = IS_I830(dev) ? 16 * 1024 : 256;
12393 ret = i915_gem_object_attach_phys(obj, align);
12394 if (ret)
12395 DRM_DEBUG_KMS("failed to attach phys object\n");
12396 } else {
12397 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12398 }
12399
12400 if (ret == 0)
12401 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12402
12403 mutex_unlock(&dev->struct_mutex);
12404
12405 return ret;
12406 }
12407
12408 /**
12409 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12410 * @plane: drm plane to clean up for
12411 * @fb: old framebuffer that was on plane
12412 *
12413 * Cleans up a framebuffer that has just been removed from a plane.
12414 */
12415 void
12416 intel_cleanup_plane_fb(struct drm_plane *plane,
12417 struct drm_framebuffer *fb,
12418 const struct drm_plane_state *old_state)
12419 {
12420 struct drm_device *dev = plane->dev;
12421 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12422
12423 if (WARN_ON(!obj))
12424 return;
12425
12426 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12427 !INTEL_INFO(dev)->cursor_needs_physical) {
12428 mutex_lock(&dev->struct_mutex);
12429 intel_unpin_fb_obj(fb, old_state);
12430 mutex_unlock(&dev->struct_mutex);
12431 }
12432 }
12433
12434 static int
12435 intel_check_primary_plane(struct drm_plane *plane,
12436 struct intel_plane_state *state)
12437 {
12438 struct drm_device *dev = plane->dev;
12439 struct drm_i915_private *dev_priv = dev->dev_private;
12440 struct drm_crtc *crtc = state->base.crtc;
12441 struct intel_crtc *intel_crtc;
12442 struct drm_framebuffer *fb = state->base.fb;
12443 struct drm_rect *dest = &state->dst;
12444 struct drm_rect *src = &state->src;
12445 const struct drm_rect *clip = &state->clip;
12446 int ret;
12447
12448 crtc = crtc ? crtc : plane->crtc;
12449 intel_crtc = to_intel_crtc(crtc);
12450
12451 ret = drm_plane_helper_check_update(plane, crtc, fb,
12452 src, dest, clip,
12453 DRM_PLANE_HELPER_NO_SCALING,
12454 DRM_PLANE_HELPER_NO_SCALING,
12455 false, true, &state->visible);
12456 if (ret)
12457 return ret;
12458
12459 if (intel_crtc->active) {
12460 intel_crtc->atomic.wait_for_flips = true;
12461
12462 /*
12463 * FBC does not work on some platforms for rotated
12464 * planes, so disable it when rotation is not 0 and
12465 * update it when rotation is set back to 0.
12466 *
12467 * FIXME: This is redundant with the fbc update done in
12468 * the primary plane enable function except that that
12469 * one is done too late. We eventually need to unify
12470 * this.
12471 */
12472 if (intel_crtc->primary_enabled &&
12473 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12474 dev_priv->fbc.crtc == intel_crtc &&
12475 state->base.rotation != BIT(DRM_ROTATE_0)) {
12476 intel_crtc->atomic.disable_fbc = true;
12477 }
12478
12479 if (state->visible) {
12480 /*
12481 * BDW signals flip done immediately if the plane
12482 * is disabled, even if the plane enable is already
12483 * armed to occur at the next vblank :(
12484 */
12485 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12486 intel_crtc->atomic.wait_vblank = true;
12487 }
12488
12489 intel_crtc->atomic.fb_bits |=
12490 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12491
12492 intel_crtc->atomic.update_fbc = true;
12493
12494 if (intel_wm_need_update(plane, &state->base))
12495 intel_crtc->atomic.update_wm = true;
12496 }
12497
12498 return 0;
12499 }
12500
12501 static void
12502 intel_commit_primary_plane(struct drm_plane *plane,
12503 struct intel_plane_state *state)
12504 {
12505 struct drm_crtc *crtc = state->base.crtc;
12506 struct drm_framebuffer *fb = state->base.fb;
12507 struct drm_device *dev = plane->dev;
12508 struct drm_i915_private *dev_priv = dev->dev_private;
12509 struct intel_crtc *intel_crtc;
12510 struct drm_rect *src = &state->src;
12511
12512 crtc = crtc ? crtc : plane->crtc;
12513 intel_crtc = to_intel_crtc(crtc);
12514
12515 plane->fb = fb;
12516 crtc->x = src->x1 >> 16;
12517 crtc->y = src->y1 >> 16;
12518
12519 if (intel_crtc->active) {
12520 if (state->visible) {
12521 /* FIXME: kill this fastboot hack */
12522 intel_update_pipe_size(intel_crtc);
12523
12524 intel_crtc->primary_enabled = true;
12525
12526 dev_priv->display.update_primary_plane(crtc, plane->fb,
12527 crtc->x, crtc->y);
12528 } else {
12529 /*
12530 * If clipping results in a non-visible primary plane,
12531 * we'll disable the primary plane. Note that this is
12532 * a bit different than what happens if userspace
12533 * explicitly disables the plane by passing fb=0
12534 * because plane->fb still gets set and pinned.
12535 */
12536 intel_disable_primary_hw_plane(plane, crtc);
12537 }
12538 }
12539 }
12540
12541 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12542 {
12543 struct drm_device *dev = crtc->dev;
12544 struct drm_i915_private *dev_priv = dev->dev_private;
12545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12546 struct intel_plane *intel_plane;
12547 struct drm_plane *p;
12548 unsigned fb_bits = 0;
12549
12550 /* Track fb's for any planes being disabled */
12551 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12552 intel_plane = to_intel_plane(p);
12553
12554 if (intel_crtc->atomic.disabled_planes &
12555 (1 << drm_plane_index(p))) {
12556 switch (p->type) {
12557 case DRM_PLANE_TYPE_PRIMARY:
12558 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12559 break;
12560 case DRM_PLANE_TYPE_CURSOR:
12561 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12562 break;
12563 case DRM_PLANE_TYPE_OVERLAY:
12564 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12565 break;
12566 }
12567
12568 mutex_lock(&dev->struct_mutex);
12569 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12570 mutex_unlock(&dev->struct_mutex);
12571 }
12572 }
12573
12574 if (intel_crtc->atomic.wait_for_flips)
12575 intel_crtc_wait_for_pending_flips(crtc);
12576
12577 if (intel_crtc->atomic.disable_fbc)
12578 intel_fbc_disable(dev);
12579
12580 if (intel_crtc->atomic.pre_disable_primary)
12581 intel_pre_disable_primary(crtc);
12582
12583 if (intel_crtc->atomic.update_wm)
12584 intel_update_watermarks(crtc);
12585
12586 intel_runtime_pm_get(dev_priv);
12587
12588 /* Perform vblank evasion around commit operation */
12589 if (intel_crtc->active)
12590 intel_crtc->atomic.evade =
12591 intel_pipe_update_start(intel_crtc,
12592 &intel_crtc->atomic.start_vbl_count);
12593 }
12594
12595 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12596 {
12597 struct drm_device *dev = crtc->dev;
12598 struct drm_i915_private *dev_priv = dev->dev_private;
12599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12600 struct drm_plane *p;
12601
12602 if (intel_crtc->atomic.evade)
12603 intel_pipe_update_end(intel_crtc,
12604 intel_crtc->atomic.start_vbl_count);
12605
12606 intel_runtime_pm_put(dev_priv);
12607
12608 if (intel_crtc->atomic.wait_vblank)
12609 intel_wait_for_vblank(dev, intel_crtc->pipe);
12610
12611 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12612
12613 if (intel_crtc->atomic.update_fbc) {
12614 mutex_lock(&dev->struct_mutex);
12615 intel_fbc_update(dev);
12616 mutex_unlock(&dev->struct_mutex);
12617 }
12618
12619 if (intel_crtc->atomic.post_enable_primary)
12620 intel_post_enable_primary(crtc);
12621
12622 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12623 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12624 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12625 false, false);
12626
12627 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12628 }
12629
12630 /**
12631 * intel_plane_destroy - destroy a plane
12632 * @plane: plane to destroy
12633 *
12634 * Common destruction function for all types of planes (primary, cursor,
12635 * sprite).
12636 */
12637 void intel_plane_destroy(struct drm_plane *plane)
12638 {
12639 struct intel_plane *intel_plane = to_intel_plane(plane);
12640 drm_plane_cleanup(plane);
12641 kfree(intel_plane);
12642 }
12643
12644 const struct drm_plane_funcs intel_plane_funcs = {
12645 .update_plane = drm_plane_helper_update,
12646 .disable_plane = drm_plane_helper_disable,
12647 .destroy = intel_plane_destroy,
12648 .set_property = drm_atomic_helper_plane_set_property,
12649 .atomic_get_property = intel_plane_atomic_get_property,
12650 .atomic_set_property = intel_plane_atomic_set_property,
12651 .atomic_duplicate_state = intel_plane_duplicate_state,
12652 .atomic_destroy_state = intel_plane_destroy_state,
12653
12654 };
12655
12656 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12657 int pipe)
12658 {
12659 struct intel_plane *primary;
12660 struct intel_plane_state *state;
12661 const uint32_t *intel_primary_formats;
12662 int num_formats;
12663
12664 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12665 if (primary == NULL)
12666 return NULL;
12667
12668 state = intel_create_plane_state(&primary->base);
12669 if (!state) {
12670 kfree(primary);
12671 return NULL;
12672 }
12673 primary->base.state = &state->base;
12674
12675 primary->can_scale = false;
12676 primary->max_downscale = 1;
12677 primary->pipe = pipe;
12678 primary->plane = pipe;
12679 primary->check_plane = intel_check_primary_plane;
12680 primary->commit_plane = intel_commit_primary_plane;
12681 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12682 primary->plane = !pipe;
12683
12684 if (INTEL_INFO(dev)->gen <= 3) {
12685 intel_primary_formats = intel_primary_formats_gen2;
12686 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12687 } else {
12688 intel_primary_formats = intel_primary_formats_gen4;
12689 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12690 }
12691
12692 drm_universal_plane_init(dev, &primary->base, 0,
12693 &intel_plane_funcs,
12694 intel_primary_formats, num_formats,
12695 DRM_PLANE_TYPE_PRIMARY);
12696
12697 if (INTEL_INFO(dev)->gen >= 4) {
12698 if (!dev->mode_config.rotation_property)
12699 dev->mode_config.rotation_property =
12700 drm_mode_create_rotation_property(dev,
12701 BIT(DRM_ROTATE_0) |
12702 BIT(DRM_ROTATE_180));
12703 if (dev->mode_config.rotation_property)
12704 drm_object_attach_property(&primary->base.base,
12705 dev->mode_config.rotation_property,
12706 state->base.rotation);
12707 }
12708
12709 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12710
12711 return &primary->base;
12712 }
12713
12714 static int
12715 intel_check_cursor_plane(struct drm_plane *plane,
12716 struct intel_plane_state *state)
12717 {
12718 struct drm_crtc *crtc = state->base.crtc;
12719 struct drm_device *dev = plane->dev;
12720 struct drm_framebuffer *fb = state->base.fb;
12721 struct drm_rect *dest = &state->dst;
12722 struct drm_rect *src = &state->src;
12723 const struct drm_rect *clip = &state->clip;
12724 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12725 struct intel_crtc *intel_crtc;
12726 unsigned stride;
12727 int ret;
12728
12729 crtc = crtc ? crtc : plane->crtc;
12730 intel_crtc = to_intel_crtc(crtc);
12731
12732 ret = drm_plane_helper_check_update(plane, crtc, fb,
12733 src, dest, clip,
12734 DRM_PLANE_HELPER_NO_SCALING,
12735 DRM_PLANE_HELPER_NO_SCALING,
12736 true, true, &state->visible);
12737 if (ret)
12738 return ret;
12739
12740
12741 /* if we want to turn off the cursor ignore width and height */
12742 if (!obj)
12743 goto finish;
12744
12745 /* Check for which cursor types we support */
12746 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12747 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12748 state->base.crtc_w, state->base.crtc_h);
12749 return -EINVAL;
12750 }
12751
12752 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12753 if (obj->base.size < stride * state->base.crtc_h) {
12754 DRM_DEBUG_KMS("buffer is too small\n");
12755 return -ENOMEM;
12756 }
12757
12758 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12759 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12760 ret = -EINVAL;
12761 }
12762
12763 finish:
12764 if (intel_crtc->active) {
12765 if (plane->state->crtc_w != state->base.crtc_w)
12766 intel_crtc->atomic.update_wm = true;
12767
12768 intel_crtc->atomic.fb_bits |=
12769 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12770 }
12771
12772 return ret;
12773 }
12774
12775 static void
12776 intel_commit_cursor_plane(struct drm_plane *plane,
12777 struct intel_plane_state *state)
12778 {
12779 struct drm_crtc *crtc = state->base.crtc;
12780 struct drm_device *dev = plane->dev;
12781 struct intel_crtc *intel_crtc;
12782 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12783 uint32_t addr;
12784
12785 crtc = crtc ? crtc : plane->crtc;
12786 intel_crtc = to_intel_crtc(crtc);
12787
12788 plane->fb = state->base.fb;
12789 crtc->cursor_x = state->base.crtc_x;
12790 crtc->cursor_y = state->base.crtc_y;
12791
12792 if (intel_crtc->cursor_bo == obj)
12793 goto update;
12794
12795 if (!obj)
12796 addr = 0;
12797 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12798 addr = i915_gem_obj_ggtt_offset(obj);
12799 else
12800 addr = obj->phys_handle->busaddr;
12801
12802 intel_crtc->cursor_addr = addr;
12803 intel_crtc->cursor_bo = obj;
12804 update:
12805
12806 if (intel_crtc->active)
12807 intel_crtc_update_cursor(crtc, state->visible);
12808 }
12809
12810 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12811 int pipe)
12812 {
12813 struct intel_plane *cursor;
12814 struct intel_plane_state *state;
12815
12816 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12817 if (cursor == NULL)
12818 return NULL;
12819
12820 state = intel_create_plane_state(&cursor->base);
12821 if (!state) {
12822 kfree(cursor);
12823 return NULL;
12824 }
12825 cursor->base.state = &state->base;
12826
12827 cursor->can_scale = false;
12828 cursor->max_downscale = 1;
12829 cursor->pipe = pipe;
12830 cursor->plane = pipe;
12831 cursor->check_plane = intel_check_cursor_plane;
12832 cursor->commit_plane = intel_commit_cursor_plane;
12833
12834 drm_universal_plane_init(dev, &cursor->base, 0,
12835 &intel_plane_funcs,
12836 intel_cursor_formats,
12837 ARRAY_SIZE(intel_cursor_formats),
12838 DRM_PLANE_TYPE_CURSOR);
12839
12840 if (INTEL_INFO(dev)->gen >= 4) {
12841 if (!dev->mode_config.rotation_property)
12842 dev->mode_config.rotation_property =
12843 drm_mode_create_rotation_property(dev,
12844 BIT(DRM_ROTATE_0) |
12845 BIT(DRM_ROTATE_180));
12846 if (dev->mode_config.rotation_property)
12847 drm_object_attach_property(&cursor->base.base,
12848 dev->mode_config.rotation_property,
12849 state->base.rotation);
12850 }
12851
12852 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12853
12854 return &cursor->base;
12855 }
12856
12857 static void intel_crtc_init(struct drm_device *dev, int pipe)
12858 {
12859 struct drm_i915_private *dev_priv = dev->dev_private;
12860 struct intel_crtc *intel_crtc;
12861 struct intel_crtc_state *crtc_state = NULL;
12862 struct drm_plane *primary = NULL;
12863 struct drm_plane *cursor = NULL;
12864 int i, ret;
12865
12866 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12867 if (intel_crtc == NULL)
12868 return;
12869
12870 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12871 if (!crtc_state)
12872 goto fail;
12873 intel_crtc_set_state(intel_crtc, crtc_state);
12874 crtc_state->base.crtc = &intel_crtc->base;
12875
12876 primary = intel_primary_plane_create(dev, pipe);
12877 if (!primary)
12878 goto fail;
12879
12880 cursor = intel_cursor_plane_create(dev, pipe);
12881 if (!cursor)
12882 goto fail;
12883
12884 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12885 cursor, &intel_crtc_funcs);
12886 if (ret)
12887 goto fail;
12888
12889 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12890 for (i = 0; i < 256; i++) {
12891 intel_crtc->lut_r[i] = i;
12892 intel_crtc->lut_g[i] = i;
12893 intel_crtc->lut_b[i] = i;
12894 }
12895
12896 /*
12897 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12898 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12899 */
12900 intel_crtc->pipe = pipe;
12901 intel_crtc->plane = pipe;
12902 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12903 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12904 intel_crtc->plane = !pipe;
12905 }
12906
12907 intel_crtc->cursor_base = ~0;
12908 intel_crtc->cursor_cntl = ~0;
12909 intel_crtc->cursor_size = ~0;
12910
12911 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12912 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12913 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12914 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12915
12916 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12917
12918 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12919
12920 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12921 return;
12922
12923 fail:
12924 if (primary)
12925 drm_plane_cleanup(primary);
12926 if (cursor)
12927 drm_plane_cleanup(cursor);
12928 kfree(crtc_state);
12929 kfree(intel_crtc);
12930 }
12931
12932 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12933 {
12934 struct drm_encoder *encoder = connector->base.encoder;
12935 struct drm_device *dev = connector->base.dev;
12936
12937 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12938
12939 if (!encoder || WARN_ON(!encoder->crtc))
12940 return INVALID_PIPE;
12941
12942 return to_intel_crtc(encoder->crtc)->pipe;
12943 }
12944
12945 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12946 struct drm_file *file)
12947 {
12948 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12949 struct drm_crtc *drmmode_crtc;
12950 struct intel_crtc *crtc;
12951
12952 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12953
12954 if (!drmmode_crtc) {
12955 DRM_ERROR("no such CRTC id\n");
12956 return -ENOENT;
12957 }
12958
12959 crtc = to_intel_crtc(drmmode_crtc);
12960 pipe_from_crtc_id->pipe = crtc->pipe;
12961
12962 return 0;
12963 }
12964
12965 static int intel_encoder_clones(struct intel_encoder *encoder)
12966 {
12967 struct drm_device *dev = encoder->base.dev;
12968 struct intel_encoder *source_encoder;
12969 int index_mask = 0;
12970 int entry = 0;
12971
12972 for_each_intel_encoder(dev, source_encoder) {
12973 if (encoders_cloneable(encoder, source_encoder))
12974 index_mask |= (1 << entry);
12975
12976 entry++;
12977 }
12978
12979 return index_mask;
12980 }
12981
12982 static bool has_edp_a(struct drm_device *dev)
12983 {
12984 struct drm_i915_private *dev_priv = dev->dev_private;
12985
12986 if (!IS_MOBILE(dev))
12987 return false;
12988
12989 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12990 return false;
12991
12992 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12993 return false;
12994
12995 return true;
12996 }
12997
12998 static bool intel_crt_present(struct drm_device *dev)
12999 {
13000 struct drm_i915_private *dev_priv = dev->dev_private;
13001
13002 if (INTEL_INFO(dev)->gen >= 9)
13003 return false;
13004
13005 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13006 return false;
13007
13008 if (IS_CHERRYVIEW(dev))
13009 return false;
13010
13011 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13012 return false;
13013
13014 return true;
13015 }
13016
13017 static void intel_setup_outputs(struct drm_device *dev)
13018 {
13019 struct drm_i915_private *dev_priv = dev->dev_private;
13020 struct intel_encoder *encoder;
13021 struct drm_connector *connector;
13022 bool dpd_is_edp = false;
13023
13024 intel_lvds_init(dev);
13025
13026 if (intel_crt_present(dev))
13027 intel_crt_init(dev);
13028
13029 if (HAS_DDI(dev)) {
13030 int found;
13031
13032 /*
13033 * Haswell uses DDI functions to detect digital outputs.
13034 * On SKL pre-D0 the strap isn't connected, so we assume
13035 * it's there.
13036 */
13037 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13038 /* WaIgnoreDDIAStrap: skl */
13039 if (found ||
13040 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13041 intel_ddi_init(dev, PORT_A);
13042
13043 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13044 * register */
13045 found = I915_READ(SFUSE_STRAP);
13046
13047 if (found & SFUSE_STRAP_DDIB_DETECTED)
13048 intel_ddi_init(dev, PORT_B);
13049 if (found & SFUSE_STRAP_DDIC_DETECTED)
13050 intel_ddi_init(dev, PORT_C);
13051 if (found & SFUSE_STRAP_DDID_DETECTED)
13052 intel_ddi_init(dev, PORT_D);
13053 } else if (HAS_PCH_SPLIT(dev)) {
13054 int found;
13055 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13056
13057 if (has_edp_a(dev))
13058 intel_dp_init(dev, DP_A, PORT_A);
13059
13060 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13061 /* PCH SDVOB multiplex with HDMIB */
13062 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13063 if (!found)
13064 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13065 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13066 intel_dp_init(dev, PCH_DP_B, PORT_B);
13067 }
13068
13069 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13070 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13071
13072 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13073 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13074
13075 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13076 intel_dp_init(dev, PCH_DP_C, PORT_C);
13077
13078 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13079 intel_dp_init(dev, PCH_DP_D, PORT_D);
13080 } else if (IS_VALLEYVIEW(dev)) {
13081 /*
13082 * The DP_DETECTED bit is the latched state of the DDC
13083 * SDA pin at boot. However since eDP doesn't require DDC
13084 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13085 * eDP ports may have been muxed to an alternate function.
13086 * Thus we can't rely on the DP_DETECTED bit alone to detect
13087 * eDP ports. Consult the VBT as well as DP_DETECTED to
13088 * detect eDP ports.
13089 */
13090 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13091 !intel_dp_is_edp(dev, PORT_B))
13092 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13093 PORT_B);
13094 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13095 intel_dp_is_edp(dev, PORT_B))
13096 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13097
13098 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13099 !intel_dp_is_edp(dev, PORT_C))
13100 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13101 PORT_C);
13102 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13103 intel_dp_is_edp(dev, PORT_C))
13104 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13105
13106 if (IS_CHERRYVIEW(dev)) {
13107 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13108 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13109 PORT_D);
13110 /* eDP not supported on port D, so don't check VBT */
13111 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13112 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13113 }
13114
13115 intel_dsi_init(dev);
13116 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13117 bool found = false;
13118
13119 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13120 DRM_DEBUG_KMS("probing SDVOB\n");
13121 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13122 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13123 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13124 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13125 }
13126
13127 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13128 intel_dp_init(dev, DP_B, PORT_B);
13129 }
13130
13131 /* Before G4X SDVOC doesn't have its own detect register */
13132
13133 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13134 DRM_DEBUG_KMS("probing SDVOC\n");
13135 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13136 }
13137
13138 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13139
13140 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13141 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13142 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13143 }
13144 if (SUPPORTS_INTEGRATED_DP(dev))
13145 intel_dp_init(dev, DP_C, PORT_C);
13146 }
13147
13148 if (SUPPORTS_INTEGRATED_DP(dev) &&
13149 (I915_READ(DP_D) & DP_DETECTED))
13150 intel_dp_init(dev, DP_D, PORT_D);
13151 } else if (IS_GEN2(dev))
13152 intel_dvo_init(dev);
13153
13154 if (SUPPORTS_TV(dev))
13155 intel_tv_init(dev);
13156
13157 /*
13158 * FIXME: We don't have full atomic support yet, but we want to be
13159 * able to enable/test plane updates via the atomic interface in the
13160 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
13161 * will take some atomic codepaths to lookup properties during
13162 * drmModeGetConnector() that unconditionally dereference
13163 * connector->state.
13164 *
13165 * We create a dummy connector state here for each connector to ensure
13166 * the DRM core doesn't try to dereference a NULL connector->state.
13167 * The actual connector properties will never be updated or contain
13168 * useful information, but since we're doing this specifically for
13169 * testing/debug of the plane operations (and only when a specific
13170 * kernel module option is given), that shouldn't really matter.
13171 *
13172 * We are also relying on these states to convert the legacy mode set
13173 * to use a drm_atomic_state struct. The states are kept consistent
13174 * with actual state, so that it is safe to rely on that instead of
13175 * the staged config.
13176 *
13177 * Once atomic support for crtc's + connectors lands, this loop should
13178 * be removed since we'll be setting up real connector state, which
13179 * will contain Intel-specific properties.
13180 */
13181 list_for_each_entry(connector,
13182 &dev->mode_config.connector_list,
13183 head) {
13184 if (!WARN_ON(connector->state)) {
13185 connector->state = kzalloc(sizeof(*connector->state),
13186 GFP_KERNEL);
13187 }
13188 }
13189
13190 intel_psr_init(dev);
13191
13192 for_each_intel_encoder(dev, encoder) {
13193 encoder->base.possible_crtcs = encoder->crtc_mask;
13194 encoder->base.possible_clones =
13195 intel_encoder_clones(encoder);
13196 }
13197
13198 intel_init_pch_refclk(dev);
13199
13200 drm_helper_move_panel_connectors_to_head(dev);
13201 }
13202
13203 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13204 {
13205 struct drm_device *dev = fb->dev;
13206 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13207
13208 drm_framebuffer_cleanup(fb);
13209 mutex_lock(&dev->struct_mutex);
13210 WARN_ON(!intel_fb->obj->framebuffer_references--);
13211 drm_gem_object_unreference(&intel_fb->obj->base);
13212 mutex_unlock(&dev->struct_mutex);
13213 kfree(intel_fb);
13214 }
13215
13216 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13217 struct drm_file *file,
13218 unsigned int *handle)
13219 {
13220 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13221 struct drm_i915_gem_object *obj = intel_fb->obj;
13222
13223 return drm_gem_handle_create(file, &obj->base, handle);
13224 }
13225
13226 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13227 .destroy = intel_user_framebuffer_destroy,
13228 .create_handle = intel_user_framebuffer_create_handle,
13229 };
13230
13231 static
13232 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13233 uint32_t pixel_format)
13234 {
13235 u32 gen = INTEL_INFO(dev)->gen;
13236
13237 if (gen >= 9) {
13238 /* "The stride in bytes must not exceed the of the size of 8K
13239 * pixels and 32K bytes."
13240 */
13241 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13242 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13243 return 32*1024;
13244 } else if (gen >= 4) {
13245 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13246 return 16*1024;
13247 else
13248 return 32*1024;
13249 } else if (gen >= 3) {
13250 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13251 return 8*1024;
13252 else
13253 return 16*1024;
13254 } else {
13255 /* XXX DSPC is limited to 4k tiled */
13256 return 8*1024;
13257 }
13258 }
13259
13260 static int intel_framebuffer_init(struct drm_device *dev,
13261 struct intel_framebuffer *intel_fb,
13262 struct drm_mode_fb_cmd2 *mode_cmd,
13263 struct drm_i915_gem_object *obj)
13264 {
13265 unsigned int aligned_height;
13266 int ret;
13267 u32 pitch_limit, stride_alignment;
13268
13269 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13270
13271 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13272 /* Enforce that fb modifier and tiling mode match, but only for
13273 * X-tiled. This is needed for FBC. */
13274 if (!!(obj->tiling_mode == I915_TILING_X) !=
13275 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13276 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13277 return -EINVAL;
13278 }
13279 } else {
13280 if (obj->tiling_mode == I915_TILING_X)
13281 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13282 else if (obj->tiling_mode == I915_TILING_Y) {
13283 DRM_DEBUG("No Y tiling for legacy addfb\n");
13284 return -EINVAL;
13285 }
13286 }
13287
13288 /* Passed in modifier sanity checking. */
13289 switch (mode_cmd->modifier[0]) {
13290 case I915_FORMAT_MOD_Y_TILED:
13291 case I915_FORMAT_MOD_Yf_TILED:
13292 if (INTEL_INFO(dev)->gen < 9) {
13293 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13294 mode_cmd->modifier[0]);
13295 return -EINVAL;
13296 }
13297 case DRM_FORMAT_MOD_NONE:
13298 case I915_FORMAT_MOD_X_TILED:
13299 break;
13300 default:
13301 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13302 mode_cmd->modifier[0]);
13303 return -EINVAL;
13304 }
13305
13306 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13307 mode_cmd->pixel_format);
13308 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13309 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13310 mode_cmd->pitches[0], stride_alignment);
13311 return -EINVAL;
13312 }
13313
13314 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13315 mode_cmd->pixel_format);
13316 if (mode_cmd->pitches[0] > pitch_limit) {
13317 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13318 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13319 "tiled" : "linear",
13320 mode_cmd->pitches[0], pitch_limit);
13321 return -EINVAL;
13322 }
13323
13324 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13325 mode_cmd->pitches[0] != obj->stride) {
13326 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13327 mode_cmd->pitches[0], obj->stride);
13328 return -EINVAL;
13329 }
13330
13331 /* Reject formats not supported by any plane early. */
13332 switch (mode_cmd->pixel_format) {
13333 case DRM_FORMAT_C8:
13334 case DRM_FORMAT_RGB565:
13335 case DRM_FORMAT_XRGB8888:
13336 case DRM_FORMAT_ARGB8888:
13337 break;
13338 case DRM_FORMAT_XRGB1555:
13339 case DRM_FORMAT_ARGB1555:
13340 if (INTEL_INFO(dev)->gen > 3) {
13341 DRM_DEBUG("unsupported pixel format: %s\n",
13342 drm_get_format_name(mode_cmd->pixel_format));
13343 return -EINVAL;
13344 }
13345 break;
13346 case DRM_FORMAT_XBGR8888:
13347 case DRM_FORMAT_ABGR8888:
13348 case DRM_FORMAT_XRGB2101010:
13349 case DRM_FORMAT_ARGB2101010:
13350 case DRM_FORMAT_XBGR2101010:
13351 case DRM_FORMAT_ABGR2101010:
13352 if (INTEL_INFO(dev)->gen < 4) {
13353 DRM_DEBUG("unsupported pixel format: %s\n",
13354 drm_get_format_name(mode_cmd->pixel_format));
13355 return -EINVAL;
13356 }
13357 break;
13358 case DRM_FORMAT_YUYV:
13359 case DRM_FORMAT_UYVY:
13360 case DRM_FORMAT_YVYU:
13361 case DRM_FORMAT_VYUY:
13362 if (INTEL_INFO(dev)->gen < 5) {
13363 DRM_DEBUG("unsupported pixel format: %s\n",
13364 drm_get_format_name(mode_cmd->pixel_format));
13365 return -EINVAL;
13366 }
13367 break;
13368 default:
13369 DRM_DEBUG("unsupported pixel format: %s\n",
13370 drm_get_format_name(mode_cmd->pixel_format));
13371 return -EINVAL;
13372 }
13373
13374 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13375 if (mode_cmd->offsets[0] != 0)
13376 return -EINVAL;
13377
13378 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13379 mode_cmd->pixel_format,
13380 mode_cmd->modifier[0]);
13381 /* FIXME drm helper for size checks (especially planar formats)? */
13382 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13383 return -EINVAL;
13384
13385 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13386 intel_fb->obj = obj;
13387 intel_fb->obj->framebuffer_references++;
13388
13389 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13390 if (ret) {
13391 DRM_ERROR("framebuffer init failed %d\n", ret);
13392 return ret;
13393 }
13394
13395 return 0;
13396 }
13397
13398 static struct drm_framebuffer *
13399 intel_user_framebuffer_create(struct drm_device *dev,
13400 struct drm_file *filp,
13401 struct drm_mode_fb_cmd2 *mode_cmd)
13402 {
13403 struct drm_i915_gem_object *obj;
13404
13405 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13406 mode_cmd->handles[0]));
13407 if (&obj->base == NULL)
13408 return ERR_PTR(-ENOENT);
13409
13410 return intel_framebuffer_create(dev, mode_cmd, obj);
13411 }
13412
13413 #ifndef CONFIG_DRM_I915_FBDEV
13414 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13415 {
13416 }
13417 #endif
13418
13419 static const struct drm_mode_config_funcs intel_mode_funcs = {
13420 .fb_create = intel_user_framebuffer_create,
13421 .output_poll_changed = intel_fbdev_output_poll_changed,
13422 .atomic_check = intel_atomic_check,
13423 .atomic_commit = intel_atomic_commit,
13424 };
13425
13426 /* Set up chip specific display functions */
13427 static void intel_init_display(struct drm_device *dev)
13428 {
13429 struct drm_i915_private *dev_priv = dev->dev_private;
13430
13431 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13432 dev_priv->display.find_dpll = g4x_find_best_dpll;
13433 else if (IS_CHERRYVIEW(dev))
13434 dev_priv->display.find_dpll = chv_find_best_dpll;
13435 else if (IS_VALLEYVIEW(dev))
13436 dev_priv->display.find_dpll = vlv_find_best_dpll;
13437 else if (IS_PINEVIEW(dev))
13438 dev_priv->display.find_dpll = pnv_find_best_dpll;
13439 else
13440 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13441
13442 if (INTEL_INFO(dev)->gen >= 9) {
13443 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13444 dev_priv->display.get_initial_plane_config =
13445 skylake_get_initial_plane_config;
13446 dev_priv->display.crtc_compute_clock =
13447 haswell_crtc_compute_clock;
13448 dev_priv->display.crtc_enable = haswell_crtc_enable;
13449 dev_priv->display.crtc_disable = haswell_crtc_disable;
13450 dev_priv->display.off = ironlake_crtc_off;
13451 dev_priv->display.update_primary_plane =
13452 skylake_update_primary_plane;
13453 } else if (HAS_DDI(dev)) {
13454 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13455 dev_priv->display.get_initial_plane_config =
13456 ironlake_get_initial_plane_config;
13457 dev_priv->display.crtc_compute_clock =
13458 haswell_crtc_compute_clock;
13459 dev_priv->display.crtc_enable = haswell_crtc_enable;
13460 dev_priv->display.crtc_disable = haswell_crtc_disable;
13461 dev_priv->display.off = ironlake_crtc_off;
13462 dev_priv->display.update_primary_plane =
13463 ironlake_update_primary_plane;
13464 } else if (HAS_PCH_SPLIT(dev)) {
13465 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13466 dev_priv->display.get_initial_plane_config =
13467 ironlake_get_initial_plane_config;
13468 dev_priv->display.crtc_compute_clock =
13469 ironlake_crtc_compute_clock;
13470 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13471 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13472 dev_priv->display.off = ironlake_crtc_off;
13473 dev_priv->display.update_primary_plane =
13474 ironlake_update_primary_plane;
13475 } else if (IS_VALLEYVIEW(dev)) {
13476 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13477 dev_priv->display.get_initial_plane_config =
13478 i9xx_get_initial_plane_config;
13479 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13480 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13481 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13482 dev_priv->display.off = i9xx_crtc_off;
13483 dev_priv->display.update_primary_plane =
13484 i9xx_update_primary_plane;
13485 } else {
13486 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13487 dev_priv->display.get_initial_plane_config =
13488 i9xx_get_initial_plane_config;
13489 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13490 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13491 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13492 dev_priv->display.off = i9xx_crtc_off;
13493 dev_priv->display.update_primary_plane =
13494 i9xx_update_primary_plane;
13495 }
13496
13497 /* Returns the core display clock speed */
13498 if (IS_VALLEYVIEW(dev))
13499 dev_priv->display.get_display_clock_speed =
13500 valleyview_get_display_clock_speed;
13501 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13502 dev_priv->display.get_display_clock_speed =
13503 i945_get_display_clock_speed;
13504 else if (IS_I915G(dev))
13505 dev_priv->display.get_display_clock_speed =
13506 i915_get_display_clock_speed;
13507 else if (IS_I945GM(dev) || IS_845G(dev))
13508 dev_priv->display.get_display_clock_speed =
13509 i9xx_misc_get_display_clock_speed;
13510 else if (IS_PINEVIEW(dev))
13511 dev_priv->display.get_display_clock_speed =
13512 pnv_get_display_clock_speed;
13513 else if (IS_I915GM(dev))
13514 dev_priv->display.get_display_clock_speed =
13515 i915gm_get_display_clock_speed;
13516 else if (IS_I865G(dev))
13517 dev_priv->display.get_display_clock_speed =
13518 i865_get_display_clock_speed;
13519 else if (IS_I85X(dev))
13520 dev_priv->display.get_display_clock_speed =
13521 i855_get_display_clock_speed;
13522 else /* 852, 830 */
13523 dev_priv->display.get_display_clock_speed =
13524 i830_get_display_clock_speed;
13525
13526 if (IS_GEN5(dev)) {
13527 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13528 } else if (IS_GEN6(dev)) {
13529 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13530 } else if (IS_IVYBRIDGE(dev)) {
13531 /* FIXME: detect B0+ stepping and use auto training */
13532 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13533 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13534 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13535 } else if (IS_VALLEYVIEW(dev)) {
13536 dev_priv->display.modeset_global_resources =
13537 valleyview_modeset_global_resources;
13538 }
13539
13540 switch (INTEL_INFO(dev)->gen) {
13541 case 2:
13542 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13543 break;
13544
13545 case 3:
13546 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13547 break;
13548
13549 case 4:
13550 case 5:
13551 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13552 break;
13553
13554 case 6:
13555 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13556 break;
13557 case 7:
13558 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13559 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13560 break;
13561 case 9:
13562 /* Drop through - unsupported since execlist only. */
13563 default:
13564 /* Default just returns -ENODEV to indicate unsupported */
13565 dev_priv->display.queue_flip = intel_default_queue_flip;
13566 }
13567
13568 intel_panel_init_backlight_funcs(dev);
13569
13570 mutex_init(&dev_priv->pps_mutex);
13571 }
13572
13573 /*
13574 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13575 * resume, or other times. This quirk makes sure that's the case for
13576 * affected systems.
13577 */
13578 static void quirk_pipea_force(struct drm_device *dev)
13579 {
13580 struct drm_i915_private *dev_priv = dev->dev_private;
13581
13582 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13583 DRM_INFO("applying pipe a force quirk\n");
13584 }
13585
13586 static void quirk_pipeb_force(struct drm_device *dev)
13587 {
13588 struct drm_i915_private *dev_priv = dev->dev_private;
13589
13590 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13591 DRM_INFO("applying pipe b force quirk\n");
13592 }
13593
13594 /*
13595 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13596 */
13597 static void quirk_ssc_force_disable(struct drm_device *dev)
13598 {
13599 struct drm_i915_private *dev_priv = dev->dev_private;
13600 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13601 DRM_INFO("applying lvds SSC disable quirk\n");
13602 }
13603
13604 /*
13605 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13606 * brightness value
13607 */
13608 static void quirk_invert_brightness(struct drm_device *dev)
13609 {
13610 struct drm_i915_private *dev_priv = dev->dev_private;
13611 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13612 DRM_INFO("applying inverted panel brightness quirk\n");
13613 }
13614
13615 /* Some VBT's incorrectly indicate no backlight is present */
13616 static void quirk_backlight_present(struct drm_device *dev)
13617 {
13618 struct drm_i915_private *dev_priv = dev->dev_private;
13619 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13620 DRM_INFO("applying backlight present quirk\n");
13621 }
13622
13623 struct intel_quirk {
13624 int device;
13625 int subsystem_vendor;
13626 int subsystem_device;
13627 void (*hook)(struct drm_device *dev);
13628 };
13629
13630 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13631 struct intel_dmi_quirk {
13632 void (*hook)(struct drm_device *dev);
13633 const struct dmi_system_id (*dmi_id_list)[];
13634 };
13635
13636 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13637 {
13638 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13639 return 1;
13640 }
13641
13642 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13643 {
13644 .dmi_id_list = &(const struct dmi_system_id[]) {
13645 {
13646 .callback = intel_dmi_reverse_brightness,
13647 .ident = "NCR Corporation",
13648 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13649 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13650 },
13651 },
13652 { } /* terminating entry */
13653 },
13654 .hook = quirk_invert_brightness,
13655 },
13656 };
13657
13658 static struct intel_quirk intel_quirks[] = {
13659 /* HP Mini needs pipe A force quirk (LP: #322104) */
13660 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13661
13662 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13663 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13664
13665 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13666 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13667
13668 /* 830 needs to leave pipe A & dpll A up */
13669 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13670
13671 /* 830 needs to leave pipe B & dpll B up */
13672 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13673
13674 /* Lenovo U160 cannot use SSC on LVDS */
13675 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13676
13677 /* Sony Vaio Y cannot use SSC on LVDS */
13678 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13679
13680 /* Acer Aspire 5734Z must invert backlight brightness */
13681 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13682
13683 /* Acer/eMachines G725 */
13684 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13685
13686 /* Acer/eMachines e725 */
13687 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13688
13689 /* Acer/Packard Bell NCL20 */
13690 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13691
13692 /* Acer Aspire 4736Z */
13693 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13694
13695 /* Acer Aspire 5336 */
13696 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13697
13698 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13699 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13700
13701 /* Acer C720 Chromebook (Core i3 4005U) */
13702 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13703
13704 /* Apple Macbook 2,1 (Core 2 T7400) */
13705 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13706
13707 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13708 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13709
13710 /* HP Chromebook 14 (Celeron 2955U) */
13711 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13712
13713 /* Dell Chromebook 11 */
13714 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13715 };
13716
13717 static void intel_init_quirks(struct drm_device *dev)
13718 {
13719 struct pci_dev *d = dev->pdev;
13720 int i;
13721
13722 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13723 struct intel_quirk *q = &intel_quirks[i];
13724
13725 if (d->device == q->device &&
13726 (d->subsystem_vendor == q->subsystem_vendor ||
13727 q->subsystem_vendor == PCI_ANY_ID) &&
13728 (d->subsystem_device == q->subsystem_device ||
13729 q->subsystem_device == PCI_ANY_ID))
13730 q->hook(dev);
13731 }
13732 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13733 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13734 intel_dmi_quirks[i].hook(dev);
13735 }
13736 }
13737
13738 /* Disable the VGA plane that we never use */
13739 static void i915_disable_vga(struct drm_device *dev)
13740 {
13741 struct drm_i915_private *dev_priv = dev->dev_private;
13742 u8 sr1;
13743 u32 vga_reg = i915_vgacntrl_reg(dev);
13744
13745 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13746 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13747 outb(SR01, VGA_SR_INDEX);
13748 sr1 = inb(VGA_SR_DATA);
13749 outb(sr1 | 1<<5, VGA_SR_DATA);
13750 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13751 udelay(300);
13752
13753 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13754 POSTING_READ(vga_reg);
13755 }
13756
13757 void intel_modeset_init_hw(struct drm_device *dev)
13758 {
13759 intel_prepare_ddi(dev);
13760
13761 if (IS_VALLEYVIEW(dev))
13762 vlv_update_cdclk(dev);
13763
13764 intel_init_clock_gating(dev);
13765
13766 intel_enable_gt_powersave(dev);
13767 }
13768
13769 void intel_modeset_init(struct drm_device *dev)
13770 {
13771 struct drm_i915_private *dev_priv = dev->dev_private;
13772 int sprite, ret;
13773 enum pipe pipe;
13774 struct intel_crtc *crtc;
13775
13776 drm_mode_config_init(dev);
13777
13778 dev->mode_config.min_width = 0;
13779 dev->mode_config.min_height = 0;
13780
13781 dev->mode_config.preferred_depth = 24;
13782 dev->mode_config.prefer_shadow = 1;
13783
13784 dev->mode_config.allow_fb_modifiers = true;
13785
13786 dev->mode_config.funcs = &intel_mode_funcs;
13787
13788 intel_init_quirks(dev);
13789
13790 intel_init_pm(dev);
13791
13792 if (INTEL_INFO(dev)->num_pipes == 0)
13793 return;
13794
13795 intel_init_display(dev);
13796 intel_init_audio(dev);
13797
13798 if (IS_GEN2(dev)) {
13799 dev->mode_config.max_width = 2048;
13800 dev->mode_config.max_height = 2048;
13801 } else if (IS_GEN3(dev)) {
13802 dev->mode_config.max_width = 4096;
13803 dev->mode_config.max_height = 4096;
13804 } else {
13805 dev->mode_config.max_width = 8192;
13806 dev->mode_config.max_height = 8192;
13807 }
13808
13809 if (IS_845G(dev) || IS_I865G(dev)) {
13810 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13811 dev->mode_config.cursor_height = 1023;
13812 } else if (IS_GEN2(dev)) {
13813 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13814 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13815 } else {
13816 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13817 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13818 }
13819
13820 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13821
13822 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13823 INTEL_INFO(dev)->num_pipes,
13824 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13825
13826 for_each_pipe(dev_priv, pipe) {
13827 intel_crtc_init(dev, pipe);
13828 for_each_sprite(dev_priv, pipe, sprite) {
13829 ret = intel_plane_init(dev, pipe, sprite);
13830 if (ret)
13831 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13832 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13833 }
13834 }
13835
13836 intel_init_dpio(dev);
13837
13838 intel_shared_dpll_init(dev);
13839
13840 /* Just disable it once at startup */
13841 i915_disable_vga(dev);
13842 intel_setup_outputs(dev);
13843
13844 /* Just in case the BIOS is doing something questionable. */
13845 intel_fbc_disable(dev);
13846
13847 drm_modeset_lock_all(dev);
13848 intel_modeset_setup_hw_state(dev, false);
13849 drm_modeset_unlock_all(dev);
13850
13851 for_each_intel_crtc(dev, crtc) {
13852 if (!crtc->active)
13853 continue;
13854
13855 /*
13856 * Note that reserving the BIOS fb up front prevents us
13857 * from stuffing other stolen allocations like the ring
13858 * on top. This prevents some ugliness at boot time, and
13859 * can even allow for smooth boot transitions if the BIOS
13860 * fb is large enough for the active pipe configuration.
13861 */
13862 if (dev_priv->display.get_initial_plane_config) {
13863 dev_priv->display.get_initial_plane_config(crtc,
13864 &crtc->plane_config);
13865 /*
13866 * If the fb is shared between multiple heads, we'll
13867 * just get the first one.
13868 */
13869 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
13870 }
13871 }
13872 }
13873
13874 static void intel_enable_pipe_a(struct drm_device *dev)
13875 {
13876 struct intel_connector *connector;
13877 struct drm_connector *crt = NULL;
13878 struct intel_load_detect_pipe load_detect_temp;
13879 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13880
13881 /* We can't just switch on the pipe A, we need to set things up with a
13882 * proper mode and output configuration. As a gross hack, enable pipe A
13883 * by enabling the load detect pipe once. */
13884 for_each_intel_connector(dev, connector) {
13885 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13886 crt = &connector->base;
13887 break;
13888 }
13889 }
13890
13891 if (!crt)
13892 return;
13893
13894 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13895 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
13896 }
13897
13898 static bool
13899 intel_check_plane_mapping(struct intel_crtc *crtc)
13900 {
13901 struct drm_device *dev = crtc->base.dev;
13902 struct drm_i915_private *dev_priv = dev->dev_private;
13903 u32 reg, val;
13904
13905 if (INTEL_INFO(dev)->num_pipes == 1)
13906 return true;
13907
13908 reg = DSPCNTR(!crtc->plane);
13909 val = I915_READ(reg);
13910
13911 if ((val & DISPLAY_PLANE_ENABLE) &&
13912 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13913 return false;
13914
13915 return true;
13916 }
13917
13918 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13919 {
13920 struct drm_device *dev = crtc->base.dev;
13921 struct drm_i915_private *dev_priv = dev->dev_private;
13922 u32 reg;
13923
13924 /* Clear any frame start delays used for debugging left by the BIOS */
13925 reg = PIPECONF(crtc->config->cpu_transcoder);
13926 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13927
13928 /* restore vblank interrupts to correct state */
13929 drm_crtc_vblank_reset(&crtc->base);
13930 if (crtc->active) {
13931 update_scanline_offset(crtc);
13932 drm_crtc_vblank_on(&crtc->base);
13933 }
13934
13935 /* We need to sanitize the plane -> pipe mapping first because this will
13936 * disable the crtc (and hence change the state) if it is wrong. Note
13937 * that gen4+ has a fixed plane -> pipe mapping. */
13938 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13939 struct intel_connector *connector;
13940 bool plane;
13941
13942 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13943 crtc->base.base.id);
13944
13945 /* Pipe has the wrong plane attached and the plane is active.
13946 * Temporarily change the plane mapping and disable everything
13947 * ... */
13948 plane = crtc->plane;
13949 crtc->plane = !plane;
13950 crtc->primary_enabled = true;
13951 dev_priv->display.crtc_disable(&crtc->base);
13952 crtc->plane = plane;
13953
13954 /* ... and break all links. */
13955 for_each_intel_connector(dev, connector) {
13956 if (connector->encoder->base.crtc != &crtc->base)
13957 continue;
13958
13959 connector->base.dpms = DRM_MODE_DPMS_OFF;
13960 connector->base.encoder = NULL;
13961 }
13962 /* multiple connectors may have the same encoder:
13963 * handle them and break crtc link separately */
13964 for_each_intel_connector(dev, connector)
13965 if (connector->encoder->base.crtc == &crtc->base) {
13966 connector->encoder->base.crtc = NULL;
13967 connector->encoder->connectors_active = false;
13968 }
13969
13970 WARN_ON(crtc->active);
13971 crtc->base.state->enable = false;
13972 crtc->base.enabled = false;
13973 }
13974
13975 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13976 crtc->pipe == PIPE_A && !crtc->active) {
13977 /* BIOS forgot to enable pipe A, this mostly happens after
13978 * resume. Force-enable the pipe to fix this, the update_dpms
13979 * call below we restore the pipe to the right state, but leave
13980 * the required bits on. */
13981 intel_enable_pipe_a(dev);
13982 }
13983
13984 /* Adjust the state of the output pipe according to whether we
13985 * have active connectors/encoders. */
13986 intel_crtc_update_dpms(&crtc->base);
13987
13988 if (crtc->active != crtc->base.state->enable) {
13989 struct intel_encoder *encoder;
13990
13991 /* This can happen either due to bugs in the get_hw_state
13992 * functions or because the pipe is force-enabled due to the
13993 * pipe A quirk. */
13994 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13995 crtc->base.base.id,
13996 crtc->base.state->enable ? "enabled" : "disabled",
13997 crtc->active ? "enabled" : "disabled");
13998
13999 crtc->base.state->enable = crtc->active;
14000 crtc->base.enabled = crtc->active;
14001
14002 /* Because we only establish the connector -> encoder ->
14003 * crtc links if something is active, this means the
14004 * crtc is now deactivated. Break the links. connector
14005 * -> encoder links are only establish when things are
14006 * actually up, hence no need to break them. */
14007 WARN_ON(crtc->active);
14008
14009 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14010 WARN_ON(encoder->connectors_active);
14011 encoder->base.crtc = NULL;
14012 }
14013 }
14014
14015 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14016 /*
14017 * We start out with underrun reporting disabled to avoid races.
14018 * For correct bookkeeping mark this on active crtcs.
14019 *
14020 * Also on gmch platforms we dont have any hardware bits to
14021 * disable the underrun reporting. Which means we need to start
14022 * out with underrun reporting disabled also on inactive pipes,
14023 * since otherwise we'll complain about the garbage we read when
14024 * e.g. coming up after runtime pm.
14025 *
14026 * No protection against concurrent access is required - at
14027 * worst a fifo underrun happens which also sets this to false.
14028 */
14029 crtc->cpu_fifo_underrun_disabled = true;
14030 crtc->pch_fifo_underrun_disabled = true;
14031 }
14032 }
14033
14034 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14035 {
14036 struct intel_connector *connector;
14037 struct drm_device *dev = encoder->base.dev;
14038
14039 /* We need to check both for a crtc link (meaning that the
14040 * encoder is active and trying to read from a pipe) and the
14041 * pipe itself being active. */
14042 bool has_active_crtc = encoder->base.crtc &&
14043 to_intel_crtc(encoder->base.crtc)->active;
14044
14045 if (encoder->connectors_active && !has_active_crtc) {
14046 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14047 encoder->base.base.id,
14048 encoder->base.name);
14049
14050 /* Connector is active, but has no active pipe. This is
14051 * fallout from our resume register restoring. Disable
14052 * the encoder manually again. */
14053 if (encoder->base.crtc) {
14054 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14055 encoder->base.base.id,
14056 encoder->base.name);
14057 encoder->disable(encoder);
14058 if (encoder->post_disable)
14059 encoder->post_disable(encoder);
14060 }
14061 encoder->base.crtc = NULL;
14062 encoder->connectors_active = false;
14063
14064 /* Inconsistent output/port/pipe state happens presumably due to
14065 * a bug in one of the get_hw_state functions. Or someplace else
14066 * in our code, like the register restore mess on resume. Clamp
14067 * things to off as a safer default. */
14068 for_each_intel_connector(dev, connector) {
14069 if (connector->encoder != encoder)
14070 continue;
14071 connector->base.dpms = DRM_MODE_DPMS_OFF;
14072 connector->base.encoder = NULL;
14073 }
14074 }
14075 /* Enabled encoders without active connectors will be fixed in
14076 * the crtc fixup. */
14077 }
14078
14079 void i915_redisable_vga_power_on(struct drm_device *dev)
14080 {
14081 struct drm_i915_private *dev_priv = dev->dev_private;
14082 u32 vga_reg = i915_vgacntrl_reg(dev);
14083
14084 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14085 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14086 i915_disable_vga(dev);
14087 }
14088 }
14089
14090 void i915_redisable_vga(struct drm_device *dev)
14091 {
14092 struct drm_i915_private *dev_priv = dev->dev_private;
14093
14094 /* This function can be called both from intel_modeset_setup_hw_state or
14095 * at a very early point in our resume sequence, where the power well
14096 * structures are not yet restored. Since this function is at a very
14097 * paranoid "someone might have enabled VGA while we were not looking"
14098 * level, just check if the power well is enabled instead of trying to
14099 * follow the "don't touch the power well if we don't need it" policy
14100 * the rest of the driver uses. */
14101 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14102 return;
14103
14104 i915_redisable_vga_power_on(dev);
14105 }
14106
14107 static bool primary_get_hw_state(struct intel_crtc *crtc)
14108 {
14109 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14110
14111 if (!crtc->active)
14112 return false;
14113
14114 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14115 }
14116
14117 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14118 {
14119 struct drm_i915_private *dev_priv = dev->dev_private;
14120 enum pipe pipe;
14121 struct intel_crtc *crtc;
14122 struct intel_encoder *encoder;
14123 struct intel_connector *connector;
14124 int i;
14125
14126 for_each_intel_crtc(dev, crtc) {
14127 memset(crtc->config, 0, sizeof(*crtc->config));
14128
14129 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14130
14131 crtc->active = dev_priv->display.get_pipe_config(crtc,
14132 crtc->config);
14133
14134 crtc->base.state->enable = crtc->active;
14135 crtc->base.enabled = crtc->active;
14136 crtc->primary_enabled = primary_get_hw_state(crtc);
14137
14138 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14139 crtc->base.base.id,
14140 crtc->active ? "enabled" : "disabled");
14141 }
14142
14143 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14144 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14145
14146 pll->on = pll->get_hw_state(dev_priv, pll,
14147 &pll->config.hw_state);
14148 pll->active = 0;
14149 pll->config.crtc_mask = 0;
14150 for_each_intel_crtc(dev, crtc) {
14151 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14152 pll->active++;
14153 pll->config.crtc_mask |= 1 << crtc->pipe;
14154 }
14155 }
14156
14157 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14158 pll->name, pll->config.crtc_mask, pll->on);
14159
14160 if (pll->config.crtc_mask)
14161 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14162 }
14163
14164 for_each_intel_encoder(dev, encoder) {
14165 pipe = 0;
14166
14167 if (encoder->get_hw_state(encoder, &pipe)) {
14168 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14169 encoder->base.crtc = &crtc->base;
14170 encoder->get_config(encoder, crtc->config);
14171 } else {
14172 encoder->base.crtc = NULL;
14173 }
14174
14175 encoder->connectors_active = false;
14176 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14177 encoder->base.base.id,
14178 encoder->base.name,
14179 encoder->base.crtc ? "enabled" : "disabled",
14180 pipe_name(pipe));
14181 }
14182
14183 for_each_intel_connector(dev, connector) {
14184 if (connector->get_hw_state(connector)) {
14185 connector->base.dpms = DRM_MODE_DPMS_ON;
14186 connector->encoder->connectors_active = true;
14187 connector->base.encoder = &connector->encoder->base;
14188 } else {
14189 connector->base.dpms = DRM_MODE_DPMS_OFF;
14190 connector->base.encoder = NULL;
14191 }
14192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14193 connector->base.base.id,
14194 connector->base.name,
14195 connector->base.encoder ? "enabled" : "disabled");
14196 }
14197 }
14198
14199 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14200 * and i915 state tracking structures. */
14201 void intel_modeset_setup_hw_state(struct drm_device *dev,
14202 bool force_restore)
14203 {
14204 struct drm_i915_private *dev_priv = dev->dev_private;
14205 enum pipe pipe;
14206 struct intel_crtc *crtc;
14207 struct intel_encoder *encoder;
14208 int i;
14209
14210 intel_modeset_readout_hw_state(dev);
14211
14212 /*
14213 * Now that we have the config, copy it to each CRTC struct
14214 * Note that this could go away if we move to using crtc_config
14215 * checking everywhere.
14216 */
14217 for_each_intel_crtc(dev, crtc) {
14218 if (crtc->active && i915.fastboot) {
14219 intel_mode_from_pipe_config(&crtc->base.mode,
14220 crtc->config);
14221 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14222 crtc->base.base.id);
14223 drm_mode_debug_printmodeline(&crtc->base.mode);
14224 }
14225 }
14226
14227 /* HW state is read out, now we need to sanitize this mess. */
14228 for_each_intel_encoder(dev, encoder) {
14229 intel_sanitize_encoder(encoder);
14230 }
14231
14232 for_each_pipe(dev_priv, pipe) {
14233 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14234 intel_sanitize_crtc(crtc);
14235 intel_dump_pipe_config(crtc, crtc->config,
14236 "[setup_hw_state]");
14237 }
14238
14239 intel_modeset_update_connector_atomic_state(dev);
14240
14241 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14242 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14243
14244 if (!pll->on || pll->active)
14245 continue;
14246
14247 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14248
14249 pll->disable(dev_priv, pll);
14250 pll->on = false;
14251 }
14252
14253 if (IS_GEN9(dev))
14254 skl_wm_get_hw_state(dev);
14255 else if (HAS_PCH_SPLIT(dev))
14256 ilk_wm_get_hw_state(dev);
14257
14258 if (force_restore) {
14259 i915_redisable_vga(dev);
14260
14261 /*
14262 * We need to use raw interfaces for restoring state to avoid
14263 * checking (bogus) intermediate states.
14264 */
14265 for_each_pipe(dev_priv, pipe) {
14266 struct drm_crtc *crtc =
14267 dev_priv->pipe_to_crtc_mapping[pipe];
14268
14269 intel_crtc_restore_mode(crtc);
14270 }
14271 } else {
14272 intel_modeset_update_staged_output_state(dev);
14273 }
14274
14275 intel_modeset_check_state(dev);
14276 }
14277
14278 void intel_modeset_gem_init(struct drm_device *dev)
14279 {
14280 struct drm_i915_private *dev_priv = dev->dev_private;
14281 struct drm_crtc *c;
14282 struct drm_i915_gem_object *obj;
14283
14284 mutex_lock(&dev->struct_mutex);
14285 intel_init_gt_powersave(dev);
14286 mutex_unlock(&dev->struct_mutex);
14287
14288 /*
14289 * There may be no VBT; and if the BIOS enabled SSC we can
14290 * just keep using it to avoid unnecessary flicker. Whereas if the
14291 * BIOS isn't using it, don't assume it will work even if the VBT
14292 * indicates as much.
14293 */
14294 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14295 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14296 DREF_SSC1_ENABLE);
14297
14298 intel_modeset_init_hw(dev);
14299
14300 intel_setup_overlay(dev);
14301
14302 /*
14303 * Make sure any fbs we allocated at startup are properly
14304 * pinned & fenced. When we do the allocation it's too early
14305 * for this.
14306 */
14307 mutex_lock(&dev->struct_mutex);
14308 for_each_crtc(dev, c) {
14309 obj = intel_fb_obj(c->primary->fb);
14310 if (obj == NULL)
14311 continue;
14312
14313 if (intel_pin_and_fence_fb_obj(c->primary,
14314 c->primary->fb,
14315 c->primary->state,
14316 NULL)) {
14317 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14318 to_intel_crtc(c)->pipe);
14319 drm_framebuffer_unreference(c->primary->fb);
14320 c->primary->fb = NULL;
14321 update_state_fb(c->primary);
14322 }
14323 }
14324 mutex_unlock(&dev->struct_mutex);
14325
14326 intel_backlight_register(dev);
14327 }
14328
14329 void intel_connector_unregister(struct intel_connector *intel_connector)
14330 {
14331 struct drm_connector *connector = &intel_connector->base;
14332
14333 intel_panel_destroy_backlight(connector);
14334 drm_connector_unregister(connector);
14335 }
14336
14337 void intel_modeset_cleanup(struct drm_device *dev)
14338 {
14339 struct drm_i915_private *dev_priv = dev->dev_private;
14340 struct drm_connector *connector;
14341
14342 intel_disable_gt_powersave(dev);
14343
14344 intel_backlight_unregister(dev);
14345
14346 /*
14347 * Interrupts and polling as the first thing to avoid creating havoc.
14348 * Too much stuff here (turning of connectors, ...) would
14349 * experience fancy races otherwise.
14350 */
14351 intel_irq_uninstall(dev_priv);
14352
14353 /*
14354 * Due to the hpd irq storm handling the hotplug work can re-arm the
14355 * poll handlers. Hence disable polling after hpd handling is shut down.
14356 */
14357 drm_kms_helper_poll_fini(dev);
14358
14359 mutex_lock(&dev->struct_mutex);
14360
14361 intel_unregister_dsm_handler();
14362
14363 intel_fbc_disable(dev);
14364
14365 mutex_unlock(&dev->struct_mutex);
14366
14367 /* flush any delayed tasks or pending work */
14368 flush_scheduled_work();
14369
14370 /* destroy the backlight and sysfs files before encoders/connectors */
14371 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14372 struct intel_connector *intel_connector;
14373
14374 intel_connector = to_intel_connector(connector);
14375 intel_connector->unregister(intel_connector);
14376 }
14377
14378 drm_mode_config_cleanup(dev);
14379
14380 intel_cleanup_overlay(dev);
14381
14382 mutex_lock(&dev->struct_mutex);
14383 intel_cleanup_gt_powersave(dev);
14384 mutex_unlock(&dev->struct_mutex);
14385 }
14386
14387 /*
14388 * Return which encoder is currently attached for connector.
14389 */
14390 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14391 {
14392 return &intel_attached_encoder(connector)->base;
14393 }
14394
14395 void intel_connector_attach_encoder(struct intel_connector *connector,
14396 struct intel_encoder *encoder)
14397 {
14398 connector->encoder = encoder;
14399 drm_mode_connector_attach_encoder(&connector->base,
14400 &encoder->base);
14401 }
14402
14403 /*
14404 * set vga decode state - true == enable VGA decode
14405 */
14406 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14407 {
14408 struct drm_i915_private *dev_priv = dev->dev_private;
14409 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14410 u16 gmch_ctrl;
14411
14412 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14413 DRM_ERROR("failed to read control word\n");
14414 return -EIO;
14415 }
14416
14417 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14418 return 0;
14419
14420 if (state)
14421 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14422 else
14423 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14424
14425 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14426 DRM_ERROR("failed to write control word\n");
14427 return -EIO;
14428 }
14429
14430 return 0;
14431 }
14432
14433 struct intel_display_error_state {
14434
14435 u32 power_well_driver;
14436
14437 int num_transcoders;
14438
14439 struct intel_cursor_error_state {
14440 u32 control;
14441 u32 position;
14442 u32 base;
14443 u32 size;
14444 } cursor[I915_MAX_PIPES];
14445
14446 struct intel_pipe_error_state {
14447 bool power_domain_on;
14448 u32 source;
14449 u32 stat;
14450 } pipe[I915_MAX_PIPES];
14451
14452 struct intel_plane_error_state {
14453 u32 control;
14454 u32 stride;
14455 u32 size;
14456 u32 pos;
14457 u32 addr;
14458 u32 surface;
14459 u32 tile_offset;
14460 } plane[I915_MAX_PIPES];
14461
14462 struct intel_transcoder_error_state {
14463 bool power_domain_on;
14464 enum transcoder cpu_transcoder;
14465
14466 u32 conf;
14467
14468 u32 htotal;
14469 u32 hblank;
14470 u32 hsync;
14471 u32 vtotal;
14472 u32 vblank;
14473 u32 vsync;
14474 } transcoder[4];
14475 };
14476
14477 struct intel_display_error_state *
14478 intel_display_capture_error_state(struct drm_device *dev)
14479 {
14480 struct drm_i915_private *dev_priv = dev->dev_private;
14481 struct intel_display_error_state *error;
14482 int transcoders[] = {
14483 TRANSCODER_A,
14484 TRANSCODER_B,
14485 TRANSCODER_C,
14486 TRANSCODER_EDP,
14487 };
14488 int i;
14489
14490 if (INTEL_INFO(dev)->num_pipes == 0)
14491 return NULL;
14492
14493 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14494 if (error == NULL)
14495 return NULL;
14496
14497 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14498 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14499
14500 for_each_pipe(dev_priv, i) {
14501 error->pipe[i].power_domain_on =
14502 __intel_display_power_is_enabled(dev_priv,
14503 POWER_DOMAIN_PIPE(i));
14504 if (!error->pipe[i].power_domain_on)
14505 continue;
14506
14507 error->cursor[i].control = I915_READ(CURCNTR(i));
14508 error->cursor[i].position = I915_READ(CURPOS(i));
14509 error->cursor[i].base = I915_READ(CURBASE(i));
14510
14511 error->plane[i].control = I915_READ(DSPCNTR(i));
14512 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14513 if (INTEL_INFO(dev)->gen <= 3) {
14514 error->plane[i].size = I915_READ(DSPSIZE(i));
14515 error->plane[i].pos = I915_READ(DSPPOS(i));
14516 }
14517 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14518 error->plane[i].addr = I915_READ(DSPADDR(i));
14519 if (INTEL_INFO(dev)->gen >= 4) {
14520 error->plane[i].surface = I915_READ(DSPSURF(i));
14521 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14522 }
14523
14524 error->pipe[i].source = I915_READ(PIPESRC(i));
14525
14526 if (HAS_GMCH_DISPLAY(dev))
14527 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14528 }
14529
14530 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14531 if (HAS_DDI(dev_priv->dev))
14532 error->num_transcoders++; /* Account for eDP. */
14533
14534 for (i = 0; i < error->num_transcoders; i++) {
14535 enum transcoder cpu_transcoder = transcoders[i];
14536
14537 error->transcoder[i].power_domain_on =
14538 __intel_display_power_is_enabled(dev_priv,
14539 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14540 if (!error->transcoder[i].power_domain_on)
14541 continue;
14542
14543 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14544
14545 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14546 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14547 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14548 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14549 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14550 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14551 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14552 }
14553
14554 return error;
14555 }
14556
14557 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14558
14559 void
14560 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14561 struct drm_device *dev,
14562 struct intel_display_error_state *error)
14563 {
14564 struct drm_i915_private *dev_priv = dev->dev_private;
14565 int i;
14566
14567 if (!error)
14568 return;
14569
14570 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14571 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14572 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14573 error->power_well_driver);
14574 for_each_pipe(dev_priv, i) {
14575 err_printf(m, "Pipe [%d]:\n", i);
14576 err_printf(m, " Power: %s\n",
14577 error->pipe[i].power_domain_on ? "on" : "off");
14578 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14579 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14580
14581 err_printf(m, "Plane [%d]:\n", i);
14582 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14583 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14584 if (INTEL_INFO(dev)->gen <= 3) {
14585 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14586 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14587 }
14588 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14589 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14590 if (INTEL_INFO(dev)->gen >= 4) {
14591 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14592 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14593 }
14594
14595 err_printf(m, "Cursor [%d]:\n", i);
14596 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14597 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14598 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14599 }
14600
14601 for (i = 0; i < error->num_transcoders; i++) {
14602 err_printf(m, "CPU transcoder: %c\n",
14603 transcoder_name(error->transcoder[i].cpu_transcoder));
14604 err_printf(m, " Power: %s\n",
14605 error->transcoder[i].power_domain_on ? "on" : "off");
14606 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14607 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14608 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14609 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14610 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14611 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14612 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14613 }
14614 }
14615
14616 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14617 {
14618 struct intel_crtc *crtc;
14619
14620 for_each_intel_crtc(dev, crtc) {
14621 struct intel_unpin_work *work;
14622
14623 spin_lock_irq(&dev->event_lock);
14624
14625 work = crtc->unpin_work;
14626
14627 if (work && work->event &&
14628 work->event->base.file_priv == file) {
14629 kfree(work->event);
14630 work->event = NULL;
14631 }
14632
14633 spin_unlock_irq(&dev->event_lock);
14634 }
14635 }
Linux kernel - Deliverables
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