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Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static bool
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
108 {
109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
114 }
115
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
128 };
129
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
142 };
143
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
170 };
171
172
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
185 },
186 .find_pll = intel_g4x_find_best_PLL,
187 };
188
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
201 };
202
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
214 },
215 .find_pll = intel_g4x_find_best_PLL,
216 };
217
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
229 },
230 .find_pll = intel_g4x_find_best_PLL,
231 };
232
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
245 };
246
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
261 };
262
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
275 };
276
277 /* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
294 };
295
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
308 };
309
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
322 };
323
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
365 };
366
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379 };
380
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393 };
394
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407 };
408
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410 {
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429 out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432 }
433
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436 {
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452 out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454 }
455
456 static void vlv_init_dpio(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465 }
466
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468 {
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471 }
472
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483 };
484
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487 {
488 unsigned int val;
489
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511 }
512
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
515 {
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
536 else
537 limit = &intel_limits_ironlake_dac;
538
539 return limit;
540 }
541
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543 {
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
552 else
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
564
565 return limit;
566 }
567
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 {
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
580 else
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
597 else
598 limit = &intel_limits_i8xx_dvo;
599 }
600 return limit;
601 }
602
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
605 {
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610 }
611
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613 {
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
616 return;
617 }
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622 }
623
624 /**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628 {
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
631
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
634 return true;
635
636 return false;
637 }
638
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 /**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
648 {
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
670
671 return true;
672 }
673
674 static bool
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
683 int err = target;
684
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
704 memset(best_clock, 0, sizeof(*best_clock));
705
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
717 int this_err;
718
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
722 continue;
723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738 }
739
740 static bool
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
744 {
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
755 int lvds_reg;
756
757 if (HAS_PCH_SPLIT(dev))
758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
789 continue;
790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
793
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
805 return found;
806 }
807
808 static bool
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815
816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832 }
833
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
835 static bool
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
860 }
861 static bool
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
872 flag = 0;
873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928 }
929
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931 {
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939 }
940
941 /**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
953
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
979 DRM_DEBUG_KMS("vblank wait timed out\n");
980 }
981
982 /*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
997 *
998 */
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1005
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
1009 WARN(1, "pipe_off wait timed out\n");
1010 } else {
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 /* Wait for the display line to settle */
1021 do {
1022 last_line = I915_READ(reg) & line_mask;
1023 mdelay(5);
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 WARN(1, "pipe_off wait timed out\n");
1028 }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033 return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039 {
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
1059 {
1060 u32 val;
1061 bool cur_state;
1062
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070 return;
1071
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
1095 }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102 {
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126 {
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148 {
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167 {
1168 int reg;
1169 u32 val;
1170
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182 {
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
1186 bool locked = true;
1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1206 pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1211 {
1212 int reg;
1213 u32 val;
1214 bool cur_state;
1215
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1230 {
1231 int reg;
1232 u32 val;
1233 bool cur_state;
1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248 {
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
1260 return;
1261 }
1262
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1272 }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277 u32 val;
1278 bool enabled;
1279
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326 {
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342 {
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358 {
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1373 {
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
1381 "IBX PCH dp port still using transcoder B\n");
1382 }
1383
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, int reg)
1386 {
1387 u32 val = I915_READ(reg);
1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390 reg, pipe_name(pipe));
1391
1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
1394 "IBX PCH hdmi port still using transcoder B\n");
1395 }
1396
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399 {
1400 int reg;
1401 u32 val;
1402
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406
1407 reg = PCH_ADPA;
1408 val = I915_READ(reg);
1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1411 pipe_name(pipe));
1412
1413 reg = PCH_LVDS;
1414 val = I915_READ(reg);
1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417 pipe_name(pipe));
1418
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422 }
1423
1424 /**
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1428 *
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1432 *
1433 * Note! This is for pre-ILK only.
1434 *
1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1436 */
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1438 {
1439 int reg;
1440 u32 val;
1441
1442 /* No really, not for ILK+ */
1443 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1444
1445 /* PLL is protected by panel, make sure we can write it */
1446 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447 assert_panel_unlocked(dev_priv, pipe);
1448
1449 reg = DPLL(pipe);
1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1452
1453 /* We do this three times for luck */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463 }
1464
1465 /**
1466 * intel_disable_pll - disable a PLL
1467 * @dev_priv: i915 private structure
1468 * @pipe: pipe PLL to disable
1469 *
1470 * Disable the PLL for @pipe, making sure the pipe is off first.
1471 *
1472 * Note! This is for pre-ILK only.
1473 */
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475 {
1476 int reg;
1477 u32 val;
1478
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481 return;
1482
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv, pipe);
1485
1486 reg = DPLL(pipe);
1487 val = I915_READ(reg);
1488 val &= ~DPLL_VCO_ENABLE;
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 }
1492
1493 /* SBI access */
1494 static void
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496 {
1497 unsigned long flags;
1498
1499 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1501 100)) {
1502 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503 goto out_unlock;
1504 }
1505
1506 I915_WRITE(SBI_ADDR,
1507 (reg << 16));
1508 I915_WRITE(SBI_DATA,
1509 value);
1510 I915_WRITE(SBI_CTL_STAT,
1511 SBI_BUSY |
1512 SBI_CTL_OP_CRWR);
1513
1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517 goto out_unlock;
1518 }
1519
1520 out_unlock:
1521 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522 }
1523
1524 static u32
1525 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526 {
1527 unsigned long flags;
1528 u32 value = 0;
1529
1530 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1532 100)) {
1533 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534 goto out_unlock;
1535 }
1536
1537 I915_WRITE(SBI_ADDR,
1538 (reg << 16));
1539 I915_WRITE(SBI_CTL_STAT,
1540 SBI_BUSY |
1541 SBI_CTL_OP_CRRD);
1542
1543 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1544 100)) {
1545 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546 goto out_unlock;
1547 }
1548
1549 value = I915_READ(SBI_DATA);
1550
1551 out_unlock:
1552 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553 return value;
1554 }
1555
1556 /**
1557 * intel_enable_pch_pll - enable PCH PLL
1558 * @dev_priv: i915 private structure
1559 * @pipe: pipe PLL to enable
1560 *
1561 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562 * drives the transcoder clock.
1563 */
1564 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1565 {
1566 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567 struct intel_pch_pll *pll;
1568 int reg;
1569 u32 val;
1570
1571 /* PCH PLLs only available on ILK, SNB and IVB */
1572 BUG_ON(dev_priv->info->gen < 5);
1573 pll = intel_crtc->pch_pll;
1574 if (pll == NULL)
1575 return;
1576
1577 if (WARN_ON(pll->refcount == 0))
1578 return;
1579
1580 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
1583
1584 /* PCH refclock must be enabled first */
1585 assert_pch_refclk_enabled(dev_priv);
1586
1587 if (pll->active++ && pll->on) {
1588 assert_pch_pll_enabled(dev_priv, pll, NULL);
1589 return;
1590 }
1591
1592 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594 reg = pll->pll_reg;
1595 val = I915_READ(reg);
1596 val |= DPLL_VCO_ENABLE;
1597 I915_WRITE(reg, val);
1598 POSTING_READ(reg);
1599 udelay(200);
1600
1601 pll->on = true;
1602 }
1603
1604 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1605 {
1606 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1608 int reg;
1609 u32 val;
1610
1611 /* PCH only available on ILK+ */
1612 BUG_ON(dev_priv->info->gen < 5);
1613 if (pll == NULL)
1614 return;
1615
1616 if (WARN_ON(pll->refcount == 0))
1617 return;
1618
1619 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620 pll->pll_reg, pll->active, pll->on,
1621 intel_crtc->base.base.id);
1622
1623 if (WARN_ON(pll->active == 0)) {
1624 assert_pch_pll_disabled(dev_priv, pll, NULL);
1625 return;
1626 }
1627
1628 if (--pll->active) {
1629 assert_pch_pll_enabled(dev_priv, pll, NULL);
1630 return;
1631 }
1632
1633 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634
1635 /* Make sure transcoder isn't still depending on us */
1636 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637
1638 reg = pll->pll_reg;
1639 val = I915_READ(reg);
1640 val &= ~DPLL_VCO_ENABLE;
1641 I915_WRITE(reg, val);
1642 POSTING_READ(reg);
1643 udelay(200);
1644
1645 pll->on = false;
1646 }
1647
1648 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649 enum pipe pipe)
1650 {
1651 int reg;
1652 u32 val, pipeconf_val;
1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv->info->gen < 5);
1657
1658 /* Make sure PCH DPLL is enabled */
1659 assert_pch_pll_enabled(dev_priv,
1660 to_intel_crtc(crtc)->pch_pll,
1661 to_intel_crtc(crtc));
1662
1663 /* FDI must be feeding us bits for PCH ports */
1664 assert_fdi_tx_enabled(dev_priv, pipe);
1665 assert_fdi_rx_enabled(dev_priv, pipe);
1666
1667 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 return;
1670 }
1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
1673 pipeconf_val = I915_READ(PIPECONF(pipe));
1674
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1676 /*
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1679 */
1680 val &= ~PIPE_BPC_MASK;
1681 val |= pipeconf_val & PIPE_BPC_MASK;
1682 }
1683
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1689 else
1690 val |= TRANS_INTERLACED;
1691 else
1692 val |= TRANS_PROGRESSIVE;
1693
1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697 }
1698
1699 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701 {
1702 int reg;
1703 u32 val;
1704
1705 /* FDI relies on the transcoder */
1706 assert_fdi_tx_disabled(dev_priv, pipe);
1707 assert_fdi_rx_disabled(dev_priv, pipe);
1708
1709 /* Ports must be off as well */
1710 assert_pch_ports_disabled(dev_priv, pipe);
1711
1712 reg = TRANSCONF(pipe);
1713 val = I915_READ(reg);
1714 val &= ~TRANS_ENABLE;
1715 I915_WRITE(reg, val);
1716 /* wait for PCH transcoder off, transcoder state */
1717 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1719 }
1720
1721 /**
1722 * intel_enable_pipe - enable a pipe, asserting requirements
1723 * @dev_priv: i915 private structure
1724 * @pipe: pipe to enable
1725 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1726 *
1727 * Enable @pipe, making sure that various hardware specific requirements
1728 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729 *
1730 * @pipe should be %PIPE_A or %PIPE_B.
1731 *
1732 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 * returning.
1734 */
1735 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736 bool pch_port)
1737 {
1738 int reg;
1739 u32 val;
1740
1741 /*
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 * need the check.
1745 */
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
1747 assert_pll_enabled(dev_priv, pipe);
1748 else {
1749 if (pch_port) {
1750 /* if driving the PCH, we need FDI enabled */
1751 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753 }
1754 /* FIXME: assert CPU port conditions for SNB+ */
1755 }
1756
1757 reg = PIPECONF(pipe);
1758 val = I915_READ(reg);
1759 if (val & PIPECONF_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | PIPECONF_ENABLE);
1763 intel_wait_for_vblank(dev_priv->dev, pipe);
1764 }
1765
1766 /**
1767 * intel_disable_pipe - disable a pipe, asserting requirements
1768 * @dev_priv: i915 private structure
1769 * @pipe: pipe to disable
1770 *
1771 * Disable @pipe, making sure that various hardware specific requirements
1772 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773 *
1774 * @pipe should be %PIPE_A or %PIPE_B.
1775 *
1776 * Will wait until the pipe has shut down before returning.
1777 */
1778 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779 enum pipe pipe)
1780 {
1781 int reg;
1782 u32 val;
1783
1784 /*
1785 * Make sure planes won't keep trying to pump pixels to us,
1786 * or we might hang the display.
1787 */
1788 assert_planes_disabled(dev_priv, pipe);
1789
1790 /* Don't disable pipe A or pipe A PLLs if needed */
1791 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792 return;
1793
1794 reg = PIPECONF(pipe);
1795 val = I915_READ(reg);
1796 if ((val & PIPECONF_ENABLE) == 0)
1797 return;
1798
1799 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801 }
1802
1803 /*
1804 * Plane regs are double buffered, going from enabled->disabled needs a
1805 * trigger in order to latch. The display address reg provides this.
1806 */
1807 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1808 enum plane plane)
1809 {
1810 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812 }
1813
1814 /**
1815 * intel_enable_plane - enable a display plane on a given pipe
1816 * @dev_priv: i915 private structure
1817 * @plane: plane to enable
1818 * @pipe: pipe being fed
1819 *
1820 * Enable @plane on @pipe, making sure that @pipe is running first.
1821 */
1822 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823 enum plane plane, enum pipe pipe)
1824 {
1825 int reg;
1826 u32 val;
1827
1828 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829 assert_pipe_enabled(dev_priv, pipe);
1830
1831 reg = DSPCNTR(plane);
1832 val = I915_READ(reg);
1833 if (val & DISPLAY_PLANE_ENABLE)
1834 return;
1835
1836 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837 intel_flush_display_plane(dev_priv, plane);
1838 intel_wait_for_vblank(dev_priv->dev, pipe);
1839 }
1840
1841 /**
1842 * intel_disable_plane - disable a display plane
1843 * @dev_priv: i915 private structure
1844 * @plane: plane to disable
1845 * @pipe: pipe consuming the data
1846 *
1847 * Disable @plane; should be an independent operation.
1848 */
1849 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850 enum plane plane, enum pipe pipe)
1851 {
1852 int reg;
1853 u32 val;
1854
1855 reg = DSPCNTR(plane);
1856 val = I915_READ(reg);
1857 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858 return;
1859
1860 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861 intel_flush_display_plane(dev_priv, plane);
1862 intel_wait_for_vblank(dev_priv->dev, pipe);
1863 }
1864
1865 int
1866 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1867 struct drm_i915_gem_object *obj,
1868 struct intel_ring_buffer *pipelined)
1869 {
1870 struct drm_i915_private *dev_priv = dev->dev_private;
1871 u32 alignment;
1872 int ret;
1873
1874 switch (obj->tiling_mode) {
1875 case I915_TILING_NONE:
1876 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877 alignment = 128 * 1024;
1878 else if (INTEL_INFO(dev)->gen >= 4)
1879 alignment = 4 * 1024;
1880 else
1881 alignment = 64 * 1024;
1882 break;
1883 case I915_TILING_X:
1884 /* pin() will align the object as required by fence */
1885 alignment = 0;
1886 break;
1887 case I915_TILING_Y:
1888 /* FIXME: Is this true? */
1889 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890 return -EINVAL;
1891 default:
1892 BUG();
1893 }
1894
1895 dev_priv->mm.interruptible = false;
1896 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1897 if (ret)
1898 goto err_interruptible;
1899
1900 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901 * fence, whereas 965+ only requires a fence if using
1902 * framebuffer compression. For simplicity, we always install
1903 * a fence as the cost is not that onerous.
1904 */
1905 ret = i915_gem_object_get_fence(obj);
1906 if (ret)
1907 goto err_unpin;
1908
1909 i915_gem_object_pin_fence(obj);
1910
1911 dev_priv->mm.interruptible = true;
1912 return 0;
1913
1914 err_unpin:
1915 i915_gem_object_unpin(obj);
1916 err_interruptible:
1917 dev_priv->mm.interruptible = true;
1918 return ret;
1919 }
1920
1921 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922 {
1923 i915_gem_object_unpin_fence(obj);
1924 i915_gem_object_unpin(obj);
1925 }
1926
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928 * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930 unsigned int bpp,
1931 unsigned int pitch)
1932 {
1933 int tile_rows, tiles;
1934
1935 tile_rows = *y / 8;
1936 *y %= 8;
1937 tiles = *x / (512/bpp);
1938 *x %= 512/bpp;
1939
1940 return tile_rows * pitch * 8 + tiles * 4096;
1941 }
1942
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944 int x, int y)
1945 {
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
1950 struct drm_i915_gem_object *obj;
1951 int plane = intel_crtc->plane;
1952 unsigned long linear_offset;
1953 u32 dspcntr;
1954 u32 reg;
1955
1956 switch (plane) {
1957 case 0:
1958 case 1:
1959 break;
1960 default:
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962 return -EINVAL;
1963 }
1964
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
1967
1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972 switch (fb->bits_per_pixel) {
1973 case 8:
1974 dspcntr |= DISPPLANE_8BPP;
1975 break;
1976 case 16:
1977 if (fb->depth == 15)
1978 dspcntr |= DISPPLANE_15_16BPP;
1979 else
1980 dspcntr |= DISPPLANE_16BPP;
1981 break;
1982 case 24:
1983 case 32:
1984 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985 break;
1986 default:
1987 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988 return -EINVAL;
1989 }
1990 if (INTEL_INFO(dev)->gen >= 4) {
1991 if (obj->tiling_mode != I915_TILING_NONE)
1992 dspcntr |= DISPPLANE_TILED;
1993 else
1994 dspcntr &= ~DISPPLANE_TILED;
1995 }
1996
1997 I915_WRITE(reg, dspcntr);
1998
1999 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2000
2001 if (INTEL_INFO(dev)->gen >= 4) {
2002 intel_crtc->dspaddr_offset =
2003 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004 fb->bits_per_pixel / 8,
2005 fb->pitches[0]);
2006 linear_offset -= intel_crtc->dspaddr_offset;
2007 } else {
2008 intel_crtc->dspaddr_offset = linear_offset;
2009 }
2010
2011 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014 if (INTEL_INFO(dev)->gen >= 4) {
2015 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016 obj->gtt_offset + intel_crtc->dspaddr_offset);
2017 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018 I915_WRITE(DSPLINOFF(plane), linear_offset);
2019 } else
2020 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2021 POSTING_READ(reg);
2022
2023 return 0;
2024 }
2025
2026 static int ironlake_update_plane(struct drm_crtc *crtc,
2027 struct drm_framebuffer *fb, int x, int y)
2028 {
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 struct intel_framebuffer *intel_fb;
2033 struct drm_i915_gem_object *obj;
2034 int plane = intel_crtc->plane;
2035 unsigned long linear_offset;
2036 u32 dspcntr;
2037 u32 reg;
2038
2039 switch (plane) {
2040 case 0:
2041 case 1:
2042 case 2:
2043 break;
2044 default:
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046 return -EINVAL;
2047 }
2048
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
2051
2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2057 case 8:
2058 dspcntr |= DISPPLANE_8BPP;
2059 break;
2060 case 16:
2061 if (fb->depth != 16)
2062 return -EINVAL;
2063
2064 dspcntr |= DISPPLANE_16BPP;
2065 break;
2066 case 24:
2067 case 32:
2068 if (fb->depth == 24)
2069 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070 else if (fb->depth == 30)
2071 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072 else
2073 return -EINVAL;
2074 break;
2075 default:
2076 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077 return -EINVAL;
2078 }
2079
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084
2085 /* must disable */
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088 I915_WRITE(reg, dspcntr);
2089
2090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091 intel_crtc->dspaddr_offset =
2092 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
2095 linear_offset -= intel_crtc->dspaddr_offset;
2096
2097 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101 obj->gtt_offset + intel_crtc->dspaddr_offset);
2102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103 I915_WRITE(DSPLINOFF(plane), linear_offset);
2104 POSTING_READ(reg);
2105
2106 return 0;
2107 }
2108
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2110 static int
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2113 {
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116
2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
2119 intel_increase_pllclock(crtc);
2120
2121 return dev_priv->display.update_plane(crtc, fb, x, y);
2122 }
2123
2124 static int
2125 intel_finish_fb(struct drm_framebuffer *old_fb)
2126 {
2127 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129 bool was_interruptible = dev_priv->mm.interruptible;
2130 int ret;
2131
2132 wait_event(dev_priv->pending_flip_queue,
2133 atomic_read(&dev_priv->mm.wedged) ||
2134 atomic_read(&obj->pending_flip) == 0);
2135
2136 /* Big Hammer, we also need to ensure that any pending
2137 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138 * current scanout is retired before unpinning the old
2139 * framebuffer.
2140 *
2141 * This should only fail upon a hung GPU, in which case we
2142 * can safely continue.
2143 */
2144 dev_priv->mm.interruptible = false;
2145 ret = i915_gem_object_finish_gpu(obj);
2146 dev_priv->mm.interruptible = was_interruptible;
2147
2148 return ret;
2149 }
2150
2151 static int
2152 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153 struct drm_framebuffer *fb)
2154 {
2155 struct drm_device *dev = crtc->dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 struct drm_i915_master_private *master_priv;
2158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159 struct drm_framebuffer *old_fb;
2160 int ret;
2161
2162 /* no fb bound */
2163 if (!fb) {
2164 DRM_ERROR("No FB bound\n");
2165 return 0;
2166 }
2167
2168 if(intel_crtc->plane > dev_priv->num_pipe) {
2169 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170 intel_crtc->plane,
2171 dev_priv->num_pipe);
2172 return -EINVAL;
2173 }
2174
2175 mutex_lock(&dev->struct_mutex);
2176 ret = intel_pin_and_fence_fb_obj(dev,
2177 to_intel_framebuffer(fb)->obj,
2178 NULL);
2179 if (ret != 0) {
2180 mutex_unlock(&dev->struct_mutex);
2181 DRM_ERROR("pin & fence failed\n");
2182 return ret;
2183 }
2184
2185 if (crtc->fb)
2186 intel_finish_fb(crtc->fb);
2187
2188 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2189 if (ret) {
2190 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2191 mutex_unlock(&dev->struct_mutex);
2192 DRM_ERROR("failed to update base address\n");
2193 return ret;
2194 }
2195
2196 old_fb = crtc->fb;
2197 crtc->fb = fb;
2198 crtc->x = x;
2199 crtc->y = y;
2200
2201 if (old_fb) {
2202 intel_wait_for_vblank(dev, intel_crtc->pipe);
2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2204 }
2205
2206 intel_update_fbc(dev);
2207 mutex_unlock(&dev->struct_mutex);
2208
2209 if (!dev->primary->master)
2210 return 0;
2211
2212 master_priv = dev->primary->master->driver_priv;
2213 if (!master_priv->sarea_priv)
2214 return 0;
2215
2216 if (intel_crtc->pipe) {
2217 master_priv->sarea_priv->pipeB_x = x;
2218 master_priv->sarea_priv->pipeB_y = y;
2219 } else {
2220 master_priv->sarea_priv->pipeA_x = x;
2221 master_priv->sarea_priv->pipeA_y = y;
2222 }
2223
2224 return 0;
2225 }
2226
2227 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2228 {
2229 struct drm_device *dev = crtc->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 u32 dpa_ctl;
2232
2233 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234 dpa_ctl = I915_READ(DP_A);
2235 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237 if (clock < 200000) {
2238 u32 temp;
2239 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240 /* workaround for 160Mhz:
2241 1) program 0x4600c bits 15:0 = 0x8124
2242 2) program 0x46010 bit 0 = 1
2243 3) program 0x46034 bit 24 = 1
2244 4) program 0x64000 bit 14 = 1
2245 */
2246 temp = I915_READ(0x4600c);
2247 temp &= 0xffff0000;
2248 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250 temp = I915_READ(0x46010);
2251 I915_WRITE(0x46010, temp | 1);
2252
2253 temp = I915_READ(0x46034);
2254 I915_WRITE(0x46034, temp | (1 << 24));
2255 } else {
2256 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257 }
2258 I915_WRITE(DP_A, dpa_ctl);
2259
2260 POSTING_READ(DP_A);
2261 udelay(500);
2262 }
2263
2264 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265 {
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 int pipe = intel_crtc->pipe;
2270 u32 reg, temp;
2271
2272 /* enable normal train */
2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
2275 if (IS_IVYBRIDGE(dev)) {
2276 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2278 } else {
2279 temp &= ~FDI_LINK_TRAIN_NONE;
2280 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2281 }
2282 I915_WRITE(reg, temp);
2283
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 if (HAS_PCH_CPT(dev)) {
2287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289 } else {
2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_NONE;
2292 }
2293 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295 /* wait one idle pattern time */
2296 POSTING_READ(reg);
2297 udelay(1000);
2298
2299 /* IVB wants error correction enabled */
2300 if (IS_IVYBRIDGE(dev))
2301 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302 FDI_FE_ERRC_ENABLE);
2303 }
2304
2305 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306 {
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310 flags |= FDI_PHASE_SYNC_OVR(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312 flags |= FDI_PHASE_SYNC_EN(pipe);
2313 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314 POSTING_READ(SOUTH_CHICKEN1);
2315 }
2316
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319 {
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
2324 int plane = intel_crtc->plane;
2325 u32 reg, temp, tries;
2326
2327 /* FDI needs bits from pipe & plane first */
2328 assert_pipe_enabled(dev_priv, pipe);
2329 assert_plane_enabled(dev_priv, plane);
2330
2331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332 for train result */
2333 reg = FDI_RX_IMR(pipe);
2334 temp = I915_READ(reg);
2335 temp &= ~FDI_RX_SYMBOL_LOCK;
2336 temp &= ~FDI_RX_BIT_LOCK;
2337 I915_WRITE(reg, temp);
2338 I915_READ(reg);
2339 udelay(150);
2340
2341 /* enable CPU FDI TX and PCH FDI RX */
2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
2344 temp &= ~(7 << 19);
2345 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_PATTERN_1;
2348 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2349
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
2354 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356 POSTING_READ(reg);
2357 udelay(150);
2358
2359 /* Ironlake workaround, enable clock pointer after FDI enable*/
2360 if (HAS_PCH_IBX(dev)) {
2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
2364 }
2365
2366 reg = FDI_RX_IIR(pipe);
2367 for (tries = 0; tries < 5; tries++) {
2368 temp = I915_READ(reg);
2369 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371 if ((temp & FDI_RX_BIT_LOCK)) {
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2374 break;
2375 }
2376 }
2377 if (tries == 5)
2378 DRM_ERROR("FDI train 1 fail!\n");
2379
2380 /* Train 2 */
2381 reg = FDI_TX_CTL(pipe);
2382 temp = I915_READ(reg);
2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_2;
2385 I915_WRITE(reg, temp);
2386
2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_2;
2391 I915_WRITE(reg, temp);
2392
2393 POSTING_READ(reg);
2394 udelay(150);
2395
2396 reg = FDI_RX_IIR(pipe);
2397 for (tries = 0; tries < 5; tries++) {
2398 temp = I915_READ(reg);
2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401 if (temp & FDI_RX_SYMBOL_LOCK) {
2402 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403 DRM_DEBUG_KMS("FDI train 2 done.\n");
2404 break;
2405 }
2406 }
2407 if (tries == 5)
2408 DRM_ERROR("FDI train 2 fail!\n");
2409
2410 DRM_DEBUG_KMS("FDI train done\n");
2411
2412 }
2413
2414 static const int snb_b_fdi_train_param[] = {
2415 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419 };
2420
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423 {
2424 struct drm_device *dev = crtc->dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427 int pipe = intel_crtc->pipe;
2428 u32 reg, temp, i, retry;
2429
2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
2436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
2439 udelay(150);
2440
2441 /* enable CPU FDI TX and PCH FDI RX */
2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
2444 temp &= ~(7 << 19);
2445 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449 /* SNB-B */
2450 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2452
2453 reg = FDI_RX_CTL(pipe);
2454 temp = I915_READ(reg);
2455 if (HAS_PCH_CPT(dev)) {
2456 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458 } else {
2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461 }
2462 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464 POSTING_READ(reg);
2465 udelay(150);
2466
2467 if (HAS_PCH_CPT(dev))
2468 cpt_phase_pointer_enable(dev, pipe);
2469
2470 for (i = 0; i < 4; i++) {
2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474 temp |= snb_b_fdi_train_param[i];
2475 I915_WRITE(reg, temp);
2476
2477 POSTING_READ(reg);
2478 udelay(500);
2479
2480 for (retry = 0; retry < 5; retry++) {
2481 reg = FDI_RX_IIR(pipe);
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484 if (temp & FDI_RX_BIT_LOCK) {
2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487 break;
2488 }
2489 udelay(50);
2490 }
2491 if (retry < 5)
2492 break;
2493 }
2494 if (i == 4)
2495 DRM_ERROR("FDI train 1 fail!\n");
2496
2497 /* Train 2 */
2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_2;
2502 if (IS_GEN6(dev)) {
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504 /* SNB-B */
2505 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506 }
2507 I915_WRITE(reg, temp);
2508
2509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
2511 if (HAS_PCH_CPT(dev)) {
2512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514 } else {
2515 temp &= ~FDI_LINK_TRAIN_NONE;
2516 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517 }
2518 I915_WRITE(reg, temp);
2519
2520 POSTING_READ(reg);
2521 udelay(150);
2522
2523 for (i = 0; i < 4; i++) {
2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 temp |= snb_b_fdi_train_param[i];
2528 I915_WRITE(reg, temp);
2529
2530 POSTING_READ(reg);
2531 udelay(500);
2532
2533 for (retry = 0; retry < 5; retry++) {
2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537 if (temp & FDI_RX_SYMBOL_LOCK) {
2538 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540 break;
2541 }
2542 udelay(50);
2543 }
2544 if (retry < 5)
2545 break;
2546 }
2547 if (i == 4)
2548 DRM_ERROR("FDI train 2 fail!\n");
2549
2550 DRM_DEBUG_KMS("FDI train done.\n");
2551 }
2552
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555 {
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2560 u32 reg, temp, i;
2561
2562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563 for train result */
2564 reg = FDI_RX_IMR(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_RX_SYMBOL_LOCK;
2567 temp &= ~FDI_RX_BIT_LOCK;
2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
2571 udelay(150);
2572
2573 /* enable CPU FDI TX and PCH FDI RX */
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2576 temp &= ~(7 << 19);
2577 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582 temp |= FDI_COMPOSITE_SYNC;
2583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_LINK_TRAIN_AUTO;
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590 temp |= FDI_COMPOSITE_SYNC;
2591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593 POSTING_READ(reg);
2594 udelay(150);
2595
2596 if (HAS_PCH_CPT(dev))
2597 cpt_phase_pointer_enable(dev, pipe);
2598
2599 for (i = 0; i < 4; i++) {
2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
2607 udelay(500);
2608
2609 reg = FDI_RX_IIR(pipe);
2610 temp = I915_READ(reg);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613 if (temp & FDI_RX_BIT_LOCK ||
2614 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2617 break;
2618 }
2619 }
2620 if (i == 4)
2621 DRM_ERROR("FDI train 1 fail!\n");
2622
2623 /* Train 2 */
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 I915_WRITE(reg, temp);
2631
2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
2641 for (i = 0; i < 4; i++) {
2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(500);
2650
2651 reg = FDI_RX_IIR(pipe);
2652 temp = I915_READ(reg);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655 if (temp & FDI_RX_SYMBOL_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2658 break;
2659 }
2660 }
2661 if (i == 4)
2662 DRM_ERROR("FDI train 2 fail!\n");
2663
2664 DRM_DEBUG_KMS("FDI train done.\n");
2665 }
2666
2667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2668 {
2669 struct drm_device *dev = intel_crtc->base.dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 int pipe = intel_crtc->pipe;
2672 u32 reg, temp;
2673
2674 /* Write the TU size bits so error detection works */
2675 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2677
2678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679 reg = FDI_RX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~((0x7 << 19) | (0x7 << 16));
2682 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686 POSTING_READ(reg);
2687 udelay(200);
2688
2689 /* Switch from Rawclk to PCDclk */
2690 temp = I915_READ(reg);
2691 I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693 POSTING_READ(reg);
2694 udelay(200);
2695
2696 /* On Haswell, the PLL configuration for ports and pipes is handled
2697 * separately, as part of DDI setup */
2698 if (!IS_HASWELL(dev)) {
2699 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2704
2705 POSTING_READ(reg);
2706 udelay(100);
2707 }
2708 }
2709 }
2710
2711 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712 {
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2716 u32 reg, temp;
2717
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728 POSTING_READ(reg);
2729 udelay(100);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735 /* Wait for the clocks to turn off. */
2736 POSTING_READ(reg);
2737 udelay(100);
2738 }
2739
2740 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741 {
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749 POSTING_READ(SOUTH_CHICKEN1);
2750 }
2751 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752 {
2753 struct drm_device *dev = crtc->dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756 int pipe = intel_crtc->pipe;
2757 u32 reg, temp;
2758
2759 /* disable CPU FDI tx and PCH FDI rx */
2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763 POSTING_READ(reg);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(0x7 << 16);
2768 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(100);
2773
2774 /* Ironlake workaround, disable clock pointer after downing FDI */
2775 if (HAS_PCH_IBX(dev)) {
2776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778 I915_READ(FDI_RX_CHICKEN(pipe) &
2779 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780 } else if (HAS_PCH_CPT(dev)) {
2781 cpt_phase_pointer_disable(dev, pipe);
2782 }
2783
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796 } else {
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799 }
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(100);
2807 }
2808
2809 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2810 {
2811 struct drm_device *dev = crtc->dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 unsigned long flags;
2814 bool pending;
2815
2816 if (atomic_read(&dev_priv->mm.wedged))
2817 return false;
2818
2819 spin_lock_irqsave(&dev->event_lock, flags);
2820 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821 spin_unlock_irqrestore(&dev->event_lock, flags);
2822
2823 return pending;
2824 }
2825
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827 {
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830
2831 if (crtc->fb == NULL)
2832 return;
2833
2834 wait_event(dev_priv->pending_flip_queue,
2835 !intel_crtc_has_pending_flip(crtc));
2836
2837 mutex_lock(&dev->struct_mutex);
2838 intel_finish_fb(crtc->fb);
2839 mutex_unlock(&dev->struct_mutex);
2840 }
2841
2842 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2843 {
2844 struct drm_device *dev = crtc->dev;
2845 struct intel_encoder *intel_encoder;
2846
2847 /*
2848 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2849 * must be driven by its own crtc; no sharing is possible.
2850 */
2851 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2852
2853 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2854 * CPU handles all others */
2855 if (IS_HASWELL(dev)) {
2856 /* It is still unclear how this will work on PPT, so throw up a warning */
2857 WARN_ON(!HAS_PCH_LPT(dev));
2858
2859 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2860 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2861 return true;
2862 } else {
2863 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2864 intel_encoder->type);
2865 return false;
2866 }
2867 }
2868
2869 switch (intel_encoder->type) {
2870 case INTEL_OUTPUT_EDP:
2871 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2872 return false;
2873 continue;
2874 }
2875 }
2876
2877 return true;
2878 }
2879
2880 /* Program iCLKIP clock to the desired frequency */
2881 static void lpt_program_iclkip(struct drm_crtc *crtc)
2882 {
2883 struct drm_device *dev = crtc->dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2886 u32 temp;
2887
2888 /* It is necessary to ungate the pixclk gate prior to programming
2889 * the divisors, and gate it back when it is done.
2890 */
2891 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2892
2893 /* Disable SSCCTL */
2894 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2895 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2896 SBI_SSCCTL_DISABLE);
2897
2898 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2899 if (crtc->mode.clock == 20000) {
2900 auxdiv = 1;
2901 divsel = 0x41;
2902 phaseinc = 0x20;
2903 } else {
2904 /* The iCLK virtual clock root frequency is in MHz,
2905 * but the crtc->mode.clock in in KHz. To get the divisors,
2906 * it is necessary to divide one by another, so we
2907 * convert the virtual clock precision to KHz here for higher
2908 * precision.
2909 */
2910 u32 iclk_virtual_root_freq = 172800 * 1000;
2911 u32 iclk_pi_range = 64;
2912 u32 desired_divisor, msb_divisor_value, pi_value;
2913
2914 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2915 msb_divisor_value = desired_divisor / iclk_pi_range;
2916 pi_value = desired_divisor % iclk_pi_range;
2917
2918 auxdiv = 0;
2919 divsel = msb_divisor_value - 2;
2920 phaseinc = pi_value;
2921 }
2922
2923 /* This should not happen with any sane values */
2924 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2925 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2926 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2927 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2928
2929 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2930 crtc->mode.clock,
2931 auxdiv,
2932 divsel,
2933 phasedir,
2934 phaseinc);
2935
2936 /* Program SSCDIVINTPHASE6 */
2937 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2938 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2939 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2940 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2941 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2942 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2943 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2944
2945 intel_sbi_write(dev_priv,
2946 SBI_SSCDIVINTPHASE6,
2947 temp);
2948
2949 /* Program SSCAUXDIV */
2950 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2951 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2952 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2953 intel_sbi_write(dev_priv,
2954 SBI_SSCAUXDIV6,
2955 temp);
2956
2957
2958 /* Enable modulator and associated divider */
2959 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2960 temp &= ~SBI_SSCCTL_DISABLE;
2961 intel_sbi_write(dev_priv,
2962 SBI_SSCCTL6,
2963 temp);
2964
2965 /* Wait for initialization time */
2966 udelay(24);
2967
2968 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2969 }
2970
2971 /*
2972 * Enable PCH resources required for PCH ports:
2973 * - PCH PLLs
2974 * - FDI training & RX/TX
2975 * - update transcoder timings
2976 * - DP transcoding bits
2977 * - transcoder
2978 */
2979 static void ironlake_pch_enable(struct drm_crtc *crtc)
2980 {
2981 struct drm_device *dev = crtc->dev;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2984 int pipe = intel_crtc->pipe;
2985 u32 reg, temp;
2986
2987 assert_transcoder_disabled(dev_priv, pipe);
2988
2989 /* For PCH output, training FDI link */
2990 dev_priv->display.fdi_link_train(crtc);
2991
2992 intel_enable_pch_pll(intel_crtc);
2993
2994 if (HAS_PCH_LPT(dev)) {
2995 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2996 lpt_program_iclkip(crtc);
2997 } else if (HAS_PCH_CPT(dev)) {
2998 u32 sel;
2999
3000 temp = I915_READ(PCH_DPLL_SEL);
3001 switch (pipe) {
3002 default:
3003 case 0:
3004 temp |= TRANSA_DPLL_ENABLE;
3005 sel = TRANSA_DPLLB_SEL;
3006 break;
3007 case 1:
3008 temp |= TRANSB_DPLL_ENABLE;
3009 sel = TRANSB_DPLLB_SEL;
3010 break;
3011 case 2:
3012 temp |= TRANSC_DPLL_ENABLE;
3013 sel = TRANSC_DPLLB_SEL;
3014 break;
3015 }
3016 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3017 temp |= sel;
3018 else
3019 temp &= ~sel;
3020 I915_WRITE(PCH_DPLL_SEL, temp);
3021 }
3022
3023 /* set transcoder timing, panel must allow it */
3024 assert_panel_unlocked(dev_priv, pipe);
3025 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3026 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3027 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3028
3029 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3030 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3031 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3032 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3033
3034 if (!IS_HASWELL(dev))
3035 intel_fdi_normal_train(crtc);
3036
3037 /* For PCH DP, enable TRANS_DP_CTL */
3038 if (HAS_PCH_CPT(dev) &&
3039 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3040 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3041 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3042 reg = TRANS_DP_CTL(pipe);
3043 temp = I915_READ(reg);
3044 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3045 TRANS_DP_SYNC_MASK |
3046 TRANS_DP_BPC_MASK);
3047 temp |= (TRANS_DP_OUTPUT_ENABLE |
3048 TRANS_DP_ENH_FRAMING);
3049 temp |= bpc << 9; /* same format but at 11:9 */
3050
3051 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3052 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3053 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3054 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3055
3056 switch (intel_trans_dp_port_sel(crtc)) {
3057 case PCH_DP_B:
3058 temp |= TRANS_DP_PORT_SEL_B;
3059 break;
3060 case PCH_DP_C:
3061 temp |= TRANS_DP_PORT_SEL_C;
3062 break;
3063 case PCH_DP_D:
3064 temp |= TRANS_DP_PORT_SEL_D;
3065 break;
3066 default:
3067 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3068 temp |= TRANS_DP_PORT_SEL_B;
3069 break;
3070 }
3071
3072 I915_WRITE(reg, temp);
3073 }
3074
3075 intel_enable_transcoder(dev_priv, pipe);
3076 }
3077
3078 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3079 {
3080 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3081
3082 if (pll == NULL)
3083 return;
3084
3085 if (pll->refcount == 0) {
3086 WARN(1, "bad PCH PLL refcount\n");
3087 return;
3088 }
3089
3090 --pll->refcount;
3091 intel_crtc->pch_pll = NULL;
3092 }
3093
3094 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3095 {
3096 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3097 struct intel_pch_pll *pll;
3098 int i;
3099
3100 pll = intel_crtc->pch_pll;
3101 if (pll) {
3102 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3103 intel_crtc->base.base.id, pll->pll_reg);
3104 goto prepare;
3105 }
3106
3107 if (HAS_PCH_IBX(dev_priv->dev)) {
3108 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3109 i = intel_crtc->pipe;
3110 pll = &dev_priv->pch_plls[i];
3111
3112 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3113 intel_crtc->base.base.id, pll->pll_reg);
3114
3115 goto found;
3116 }
3117
3118 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119 pll = &dev_priv->pch_plls[i];
3120
3121 /* Only want to check enabled timings first */
3122 if (pll->refcount == 0)
3123 continue;
3124
3125 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3126 fp == I915_READ(pll->fp0_reg)) {
3127 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3128 intel_crtc->base.base.id,
3129 pll->pll_reg, pll->refcount, pll->active);
3130
3131 goto found;
3132 }
3133 }
3134
3135 /* Ok no matching timings, maybe there's a free one? */
3136 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3137 pll = &dev_priv->pch_plls[i];
3138 if (pll->refcount == 0) {
3139 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3140 intel_crtc->base.base.id, pll->pll_reg);
3141 goto found;
3142 }
3143 }
3144
3145 return NULL;
3146
3147 found:
3148 intel_crtc->pch_pll = pll;
3149 pll->refcount++;
3150 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3151 prepare: /* separate function? */
3152 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3153
3154 /* Wait for the clocks to stabilize before rewriting the regs */
3155 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3156 POSTING_READ(pll->pll_reg);
3157 udelay(150);
3158
3159 I915_WRITE(pll->fp0_reg, fp);
3160 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3161 pll->on = false;
3162 return pll;
3163 }
3164
3165 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3166 {
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3169 u32 temp;
3170
3171 temp = I915_READ(dslreg);
3172 udelay(500);
3173 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3174 /* Without this, mode sets may fail silently on FDI */
3175 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3176 udelay(250);
3177 I915_WRITE(tc2reg, 0);
3178 if (wait_for(I915_READ(dslreg) != temp, 5))
3179 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3180 }
3181 }
3182
3183 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3184 {
3185 struct drm_device *dev = crtc->dev;
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 struct intel_encoder *encoder;
3189 int pipe = intel_crtc->pipe;
3190 int plane = intel_crtc->plane;
3191 u32 temp;
3192 bool is_pch_port;
3193
3194 WARN_ON(!crtc->enabled);
3195
3196 if (intel_crtc->active)
3197 return;
3198
3199 intel_crtc->active = true;
3200 intel_update_watermarks(dev);
3201
3202 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3203 temp = I915_READ(PCH_LVDS);
3204 if ((temp & LVDS_PORT_EN) == 0)
3205 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3206 }
3207
3208 is_pch_port = intel_crtc_driving_pch(crtc);
3209
3210 if (is_pch_port) {
3211 ironlake_fdi_pll_enable(intel_crtc);
3212 } else {
3213 assert_fdi_tx_disabled(dev_priv, pipe);
3214 assert_fdi_rx_disabled(dev_priv, pipe);
3215 }
3216
3217 for_each_encoder_on_crtc(dev, crtc, encoder)
3218 if (encoder->pre_enable)
3219 encoder->pre_enable(encoder);
3220
3221 /* Enable panel fitting for LVDS */
3222 if (dev_priv->pch_pf_size &&
3223 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3224 /* Force use of hard-coded filter coefficients
3225 * as some pre-programmed values are broken,
3226 * e.g. x201.
3227 */
3228 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3229 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3230 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3231 }
3232
3233 /*
3234 * On ILK+ LUT must be loaded before the pipe is running but with
3235 * clocks enabled
3236 */
3237 intel_crtc_load_lut(crtc);
3238
3239 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3240 intel_enable_plane(dev_priv, plane, pipe);
3241
3242 if (is_pch_port)
3243 ironlake_pch_enable(crtc);
3244
3245 mutex_lock(&dev->struct_mutex);
3246 intel_update_fbc(dev);
3247 mutex_unlock(&dev->struct_mutex);
3248
3249 intel_crtc_update_cursor(crtc, true);
3250
3251 for_each_encoder_on_crtc(dev, crtc, encoder)
3252 encoder->enable(encoder);
3253
3254 if (HAS_PCH_CPT(dev))
3255 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3256 }
3257
3258 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3259 {
3260 struct drm_device *dev = crtc->dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3263 struct intel_encoder *encoder;
3264 int pipe = intel_crtc->pipe;
3265 int plane = intel_crtc->plane;
3266 u32 reg, temp;
3267
3268
3269 if (!intel_crtc->active)
3270 return;
3271
3272 for_each_encoder_on_crtc(dev, crtc, encoder)
3273 encoder->disable(encoder);
3274
3275 intel_crtc_wait_for_pending_flips(crtc);
3276 drm_vblank_off(dev, pipe);
3277 intel_crtc_update_cursor(crtc, false);
3278
3279 intel_disable_plane(dev_priv, plane, pipe);
3280
3281 if (dev_priv->cfb_plane == plane)
3282 intel_disable_fbc(dev);
3283
3284 intel_disable_pipe(dev_priv, pipe);
3285
3286 /* Disable PF */
3287 I915_WRITE(PF_CTL(pipe), 0);
3288 I915_WRITE(PF_WIN_SZ(pipe), 0);
3289
3290 for_each_encoder_on_crtc(dev, crtc, encoder)
3291 if (encoder->post_disable)
3292 encoder->post_disable(encoder);
3293
3294 ironlake_fdi_disable(crtc);
3295
3296 intel_disable_transcoder(dev_priv, pipe);
3297
3298 if (HAS_PCH_CPT(dev)) {
3299 /* disable TRANS_DP_CTL */
3300 reg = TRANS_DP_CTL(pipe);
3301 temp = I915_READ(reg);
3302 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3303 temp |= TRANS_DP_PORT_SEL_NONE;
3304 I915_WRITE(reg, temp);
3305
3306 /* disable DPLL_SEL */
3307 temp = I915_READ(PCH_DPLL_SEL);
3308 switch (pipe) {
3309 case 0:
3310 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3311 break;
3312 case 1:
3313 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3314 break;
3315 case 2:
3316 /* C shares PLL A or B */
3317 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3318 break;
3319 default:
3320 BUG(); /* wtf */
3321 }
3322 I915_WRITE(PCH_DPLL_SEL, temp);
3323 }
3324
3325 /* disable PCH DPLL */
3326 intel_disable_pch_pll(intel_crtc);
3327
3328 ironlake_fdi_pll_disable(intel_crtc);
3329
3330 intel_crtc->active = false;
3331 intel_update_watermarks(dev);
3332
3333 mutex_lock(&dev->struct_mutex);
3334 intel_update_fbc(dev);
3335 mutex_unlock(&dev->struct_mutex);
3336 }
3337
3338 static void ironlake_crtc_off(struct drm_crtc *crtc)
3339 {
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341 intel_put_pch_pll(intel_crtc);
3342 }
3343
3344 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3345 {
3346 if (!enable && intel_crtc->overlay) {
3347 struct drm_device *dev = intel_crtc->base.dev;
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349
3350 mutex_lock(&dev->struct_mutex);
3351 dev_priv->mm.interruptible = false;
3352 (void) intel_overlay_switch_off(intel_crtc->overlay);
3353 dev_priv->mm.interruptible = true;
3354 mutex_unlock(&dev->struct_mutex);
3355 }
3356
3357 /* Let userspace switch the overlay on again. In most cases userspace
3358 * has to recompute where to put it anyway.
3359 */
3360 }
3361
3362 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3363 {
3364 struct drm_device *dev = crtc->dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3367 struct intel_encoder *encoder;
3368 int pipe = intel_crtc->pipe;
3369 int plane = intel_crtc->plane;
3370
3371 WARN_ON(!crtc->enabled);
3372
3373 if (intel_crtc->active)
3374 return;
3375
3376 intel_crtc->active = true;
3377 intel_update_watermarks(dev);
3378
3379 intel_enable_pll(dev_priv, pipe);
3380 intel_enable_pipe(dev_priv, pipe, false);
3381 intel_enable_plane(dev_priv, plane, pipe);
3382
3383 intel_crtc_load_lut(crtc);
3384 intel_update_fbc(dev);
3385
3386 /* Give the overlay scaler a chance to enable if it's on this pipe */
3387 intel_crtc_dpms_overlay(intel_crtc, true);
3388 intel_crtc_update_cursor(crtc, true);
3389
3390 for_each_encoder_on_crtc(dev, crtc, encoder)
3391 encoder->enable(encoder);
3392 }
3393
3394 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3395 {
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 struct intel_encoder *encoder;
3400 int pipe = intel_crtc->pipe;
3401 int plane = intel_crtc->plane;
3402
3403
3404 if (!intel_crtc->active)
3405 return;
3406
3407 for_each_encoder_on_crtc(dev, crtc, encoder)
3408 encoder->disable(encoder);
3409
3410 /* Give the overlay scaler a chance to disable if it's on this pipe */
3411 intel_crtc_wait_for_pending_flips(crtc);
3412 drm_vblank_off(dev, pipe);
3413 intel_crtc_dpms_overlay(intel_crtc, false);
3414 intel_crtc_update_cursor(crtc, false);
3415
3416 if (dev_priv->cfb_plane == plane)
3417 intel_disable_fbc(dev);
3418
3419 intel_disable_plane(dev_priv, plane, pipe);
3420 intel_disable_pipe(dev_priv, pipe);
3421 intel_disable_pll(dev_priv, pipe);
3422
3423 intel_crtc->active = false;
3424 intel_update_fbc(dev);
3425 intel_update_watermarks(dev);
3426 }
3427
3428 static void i9xx_crtc_off(struct drm_crtc *crtc)
3429 {
3430 }
3431
3432 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3433 bool enabled)
3434 {
3435 struct drm_device *dev = crtc->dev;
3436 struct drm_i915_master_private *master_priv;
3437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438 int pipe = intel_crtc->pipe;
3439
3440 if (!dev->primary->master)
3441 return;
3442
3443 master_priv = dev->primary->master->driver_priv;
3444 if (!master_priv->sarea_priv)
3445 return;
3446
3447 switch (pipe) {
3448 case 0:
3449 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3450 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3451 break;
3452 case 1:
3453 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3454 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3455 break;
3456 default:
3457 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3458 break;
3459 }
3460 }
3461
3462 /**
3463 * Sets the power management mode of the pipe and plane.
3464 */
3465 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3466 {
3467 struct drm_device *dev = crtc->dev;
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469 struct intel_encoder *intel_encoder;
3470 bool enable = false;
3471
3472 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3473 enable |= intel_encoder->connectors_active;
3474
3475 if (enable)
3476 dev_priv->display.crtc_enable(crtc);
3477 else
3478 dev_priv->display.crtc_disable(crtc);
3479
3480 intel_crtc_update_sarea(crtc, enable);
3481 }
3482
3483 static void intel_crtc_noop(struct drm_crtc *crtc)
3484 {
3485 }
3486
3487 static void intel_crtc_disable(struct drm_crtc *crtc)
3488 {
3489 struct drm_device *dev = crtc->dev;
3490 struct drm_connector *connector;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492
3493 /* crtc should still be enabled when we disable it. */
3494 WARN_ON(!crtc->enabled);
3495
3496 dev_priv->display.crtc_disable(crtc);
3497 intel_crtc_update_sarea(crtc, false);
3498 dev_priv->display.off(crtc);
3499
3500 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3501 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3502
3503 if (crtc->fb) {
3504 mutex_lock(&dev->struct_mutex);
3505 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3506 mutex_unlock(&dev->struct_mutex);
3507 crtc->fb = NULL;
3508 }
3509
3510 /* Update computed state. */
3511 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3512 if (!connector->encoder || !connector->encoder->crtc)
3513 continue;
3514
3515 if (connector->encoder->crtc != crtc)
3516 continue;
3517
3518 connector->dpms = DRM_MODE_DPMS_OFF;
3519 to_intel_encoder(connector->encoder)->connectors_active = false;
3520 }
3521 }
3522
3523 void intel_modeset_disable(struct drm_device *dev)
3524 {
3525 struct drm_crtc *crtc;
3526
3527 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3528 if (crtc->enabled)
3529 intel_crtc_disable(crtc);
3530 }
3531 }
3532
3533 void intel_encoder_noop(struct drm_encoder *encoder)
3534 {
3535 }
3536
3537 void intel_encoder_destroy(struct drm_encoder *encoder)
3538 {
3539 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3540
3541 drm_encoder_cleanup(encoder);
3542 kfree(intel_encoder);
3543 }
3544
3545 /* Simple dpms helper for encodres with just one connector, no cloning and only
3546 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3547 * state of the entire output pipe. */
3548 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3549 {
3550 if (mode == DRM_MODE_DPMS_ON) {
3551 encoder->connectors_active = true;
3552
3553 intel_crtc_update_dpms(encoder->base.crtc);
3554 } else {
3555 encoder->connectors_active = false;
3556
3557 intel_crtc_update_dpms(encoder->base.crtc);
3558 }
3559 }
3560
3561 /* Cross check the actual hw state with our own modeset state tracking (and it's
3562 * internal consistency). */
3563 static void intel_connector_check_state(struct intel_connector *connector)
3564 {
3565 if (connector->get_hw_state(connector)) {
3566 struct intel_encoder *encoder = connector->encoder;
3567 struct drm_crtc *crtc;
3568 bool encoder_enabled;
3569 enum pipe pipe;
3570
3571 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3572 connector->base.base.id,
3573 drm_get_connector_name(&connector->base));
3574
3575 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3576 "wrong connector dpms state\n");
3577 WARN(connector->base.encoder != &encoder->base,
3578 "active connector not linked to encoder\n");
3579 WARN(!encoder->connectors_active,
3580 "encoder->connectors_active not set\n");
3581
3582 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3583 WARN(!encoder_enabled, "encoder not enabled\n");
3584 if (WARN_ON(!encoder->base.crtc))
3585 return;
3586
3587 crtc = encoder->base.crtc;
3588
3589 WARN(!crtc->enabled, "crtc not enabled\n");
3590 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3591 WARN(pipe != to_intel_crtc(crtc)->pipe,
3592 "encoder active on the wrong pipe\n");
3593 }
3594 }
3595
3596 /* Even simpler default implementation, if there's really no special case to
3597 * consider. */
3598 void intel_connector_dpms(struct drm_connector *connector, int mode)
3599 {
3600 struct intel_encoder *encoder = intel_attached_encoder(connector);
3601
3602 /* All the simple cases only support two dpms states. */
3603 if (mode != DRM_MODE_DPMS_ON)
3604 mode = DRM_MODE_DPMS_OFF;
3605
3606 if (mode == connector->dpms)
3607 return;
3608
3609 connector->dpms = mode;
3610
3611 /* Only need to change hw state when actually enabled */
3612 if (encoder->base.crtc)
3613 intel_encoder_dpms(encoder, mode);
3614 else
3615 WARN_ON(encoder->connectors_active != false);
3616
3617 intel_modeset_check_state(connector->dev);
3618 }
3619
3620 /* Simple connector->get_hw_state implementation for encoders that support only
3621 * one connector and no cloning and hence the encoder state determines the state
3622 * of the connector. */
3623 bool intel_connector_get_hw_state(struct intel_connector *connector)
3624 {
3625 enum pipe pipe = 0;
3626 struct intel_encoder *encoder = connector->encoder;
3627
3628 return encoder->get_hw_state(encoder, &pipe);
3629 }
3630
3631 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3632 const struct drm_display_mode *mode,
3633 struct drm_display_mode *adjusted_mode)
3634 {
3635 struct drm_device *dev = crtc->dev;
3636
3637 if (HAS_PCH_SPLIT(dev)) {
3638 /* FDI link clock is fixed at 2.7G */
3639 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3640 return false;
3641 }
3642
3643 /* All interlaced capable intel hw wants timings in frames. Note though
3644 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3645 * timings, so we need to be careful not to clobber these.*/
3646 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3647 drm_mode_set_crtcinfo(adjusted_mode, 0);
3648
3649 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3650 * with a hsync front porch of 0.
3651 */
3652 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3653 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3654 return false;
3655
3656 return true;
3657 }
3658
3659 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3660 {
3661 return 400000; /* FIXME */
3662 }
3663
3664 static int i945_get_display_clock_speed(struct drm_device *dev)
3665 {
3666 return 400000;
3667 }
3668
3669 static int i915_get_display_clock_speed(struct drm_device *dev)
3670 {
3671 return 333000;
3672 }
3673
3674 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3675 {
3676 return 200000;
3677 }
3678
3679 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3680 {
3681 u16 gcfgc = 0;
3682
3683 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3684
3685 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3686 return 133000;
3687 else {
3688 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3689 case GC_DISPLAY_CLOCK_333_MHZ:
3690 return 333000;
3691 default:
3692 case GC_DISPLAY_CLOCK_190_200_MHZ:
3693 return 190000;
3694 }
3695 }
3696 }
3697
3698 static int i865_get_display_clock_speed(struct drm_device *dev)
3699 {
3700 return 266000;
3701 }
3702
3703 static int i855_get_display_clock_speed(struct drm_device *dev)
3704 {
3705 u16 hpllcc = 0;
3706 /* Assume that the hardware is in the high speed state. This
3707 * should be the default.
3708 */
3709 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3710 case GC_CLOCK_133_200:
3711 case GC_CLOCK_100_200:
3712 return 200000;
3713 case GC_CLOCK_166_250:
3714 return 250000;
3715 case GC_CLOCK_100_133:
3716 return 133000;
3717 }
3718
3719 /* Shouldn't happen */
3720 return 0;
3721 }
3722
3723 static int i830_get_display_clock_speed(struct drm_device *dev)
3724 {
3725 return 133000;
3726 }
3727
3728 struct fdi_m_n {
3729 u32 tu;
3730 u32 gmch_m;
3731 u32 gmch_n;
3732 u32 link_m;
3733 u32 link_n;
3734 };
3735
3736 static void
3737 fdi_reduce_ratio(u32 *num, u32 *den)
3738 {
3739 while (*num > 0xffffff || *den > 0xffffff) {
3740 *num >>= 1;
3741 *den >>= 1;
3742 }
3743 }
3744
3745 static void
3746 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3747 int link_clock, struct fdi_m_n *m_n)
3748 {
3749 m_n->tu = 64; /* default size */
3750
3751 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3752 m_n->gmch_m = bits_per_pixel * pixel_clock;
3753 m_n->gmch_n = link_clock * nlanes * 8;
3754 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3755
3756 m_n->link_m = pixel_clock;
3757 m_n->link_n = link_clock;
3758 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3759 }
3760
3761 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3762 {
3763 if (i915_panel_use_ssc >= 0)
3764 return i915_panel_use_ssc != 0;
3765 return dev_priv->lvds_use_ssc
3766 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3767 }
3768
3769 /**
3770 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3771 * @crtc: CRTC structure
3772 * @mode: requested mode
3773 *
3774 * A pipe may be connected to one or more outputs. Based on the depth of the
3775 * attached framebuffer, choose a good color depth to use on the pipe.
3776 *
3777 * If possible, match the pipe depth to the fb depth. In some cases, this
3778 * isn't ideal, because the connected output supports a lesser or restricted
3779 * set of depths. Resolve that here:
3780 * LVDS typically supports only 6bpc, so clamp down in that case
3781 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3782 * Displays may support a restricted set as well, check EDID and clamp as
3783 * appropriate.
3784 * DP may want to dither down to 6bpc to fit larger modes
3785 *
3786 * RETURNS:
3787 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3788 * true if they don't match).
3789 */
3790 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3791 struct drm_framebuffer *fb,
3792 unsigned int *pipe_bpp,
3793 struct drm_display_mode *mode)
3794 {
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 struct drm_connector *connector;
3798 struct intel_encoder *intel_encoder;
3799 unsigned int display_bpc = UINT_MAX, bpc;
3800
3801 /* Walk the encoders & connectors on this crtc, get min bpc */
3802 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3803
3804 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3805 unsigned int lvds_bpc;
3806
3807 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3808 LVDS_A3_POWER_UP)
3809 lvds_bpc = 8;
3810 else
3811 lvds_bpc = 6;
3812
3813 if (lvds_bpc < display_bpc) {
3814 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3815 display_bpc = lvds_bpc;
3816 }
3817 continue;
3818 }
3819
3820 /* Not one of the known troublemakers, check the EDID */
3821 list_for_each_entry(connector, &dev->mode_config.connector_list,
3822 head) {
3823 if (connector->encoder != &intel_encoder->base)
3824 continue;
3825
3826 /* Don't use an invalid EDID bpc value */
3827 if (connector->display_info.bpc &&
3828 connector->display_info.bpc < display_bpc) {
3829 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3830 display_bpc = connector->display_info.bpc;
3831 }
3832 }
3833
3834 /*
3835 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3836 * through, clamp it down. (Note: >12bpc will be caught below.)
3837 */
3838 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3839 if (display_bpc > 8 && display_bpc < 12) {
3840 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3841 display_bpc = 12;
3842 } else {
3843 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3844 display_bpc = 8;
3845 }
3846 }
3847 }
3848
3849 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3850 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3851 display_bpc = 6;
3852 }
3853
3854 /*
3855 * We could just drive the pipe at the highest bpc all the time and
3856 * enable dithering as needed, but that costs bandwidth. So choose
3857 * the minimum value that expresses the full color range of the fb but
3858 * also stays within the max display bpc discovered above.
3859 */
3860
3861 switch (fb->depth) {
3862 case 8:
3863 bpc = 8; /* since we go through a colormap */
3864 break;
3865 case 15:
3866 case 16:
3867 bpc = 6; /* min is 18bpp */
3868 break;
3869 case 24:
3870 bpc = 8;
3871 break;
3872 case 30:
3873 bpc = 10;
3874 break;
3875 case 48:
3876 bpc = 12;
3877 break;
3878 default:
3879 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3880 bpc = min((unsigned int)8, display_bpc);
3881 break;
3882 }
3883
3884 display_bpc = min(display_bpc, bpc);
3885
3886 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3887 bpc, display_bpc);
3888
3889 *pipe_bpp = display_bpc * 3;
3890
3891 return display_bpc != bpc;
3892 }
3893
3894 static int vlv_get_refclk(struct drm_crtc *crtc)
3895 {
3896 struct drm_device *dev = crtc->dev;
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 int refclk = 27000; /* for DP & HDMI */
3899
3900 return 100000; /* only one validated so far */
3901
3902 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3903 refclk = 96000;
3904 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3905 if (intel_panel_use_ssc(dev_priv))
3906 refclk = 100000;
3907 else
3908 refclk = 96000;
3909 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3910 refclk = 100000;
3911 }
3912
3913 return refclk;
3914 }
3915
3916 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3917 {
3918 struct drm_device *dev = crtc->dev;
3919 struct drm_i915_private *dev_priv = dev->dev_private;
3920 int refclk;
3921
3922 if (IS_VALLEYVIEW(dev)) {
3923 refclk = vlv_get_refclk(crtc);
3924 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3925 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3926 refclk = dev_priv->lvds_ssc_freq * 1000;
3927 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3928 refclk / 1000);
3929 } else if (!IS_GEN2(dev)) {
3930 refclk = 96000;
3931 } else {
3932 refclk = 48000;
3933 }
3934
3935 return refclk;
3936 }
3937
3938 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3939 intel_clock_t *clock)
3940 {
3941 /* SDVO TV has fixed PLL values depend on its clock range,
3942 this mirrors vbios setting. */
3943 if (adjusted_mode->clock >= 100000
3944 && adjusted_mode->clock < 140500) {
3945 clock->p1 = 2;
3946 clock->p2 = 10;
3947 clock->n = 3;
3948 clock->m1 = 16;
3949 clock->m2 = 8;
3950 } else if (adjusted_mode->clock >= 140500
3951 && adjusted_mode->clock <= 200000) {
3952 clock->p1 = 1;
3953 clock->p2 = 10;
3954 clock->n = 6;
3955 clock->m1 = 12;
3956 clock->m2 = 8;
3957 }
3958 }
3959
3960 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3961 intel_clock_t *clock,
3962 intel_clock_t *reduced_clock)
3963 {
3964 struct drm_device *dev = crtc->dev;
3965 struct drm_i915_private *dev_priv = dev->dev_private;
3966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3967 int pipe = intel_crtc->pipe;
3968 u32 fp, fp2 = 0;
3969
3970 if (IS_PINEVIEW(dev)) {
3971 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3972 if (reduced_clock)
3973 fp2 = (1 << reduced_clock->n) << 16 |
3974 reduced_clock->m1 << 8 | reduced_clock->m2;
3975 } else {
3976 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3977 if (reduced_clock)
3978 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3979 reduced_clock->m2;
3980 }
3981
3982 I915_WRITE(FP0(pipe), fp);
3983
3984 intel_crtc->lowfreq_avail = false;
3985 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3986 reduced_clock && i915_powersave) {
3987 I915_WRITE(FP1(pipe), fp2);
3988 intel_crtc->lowfreq_avail = true;
3989 } else {
3990 I915_WRITE(FP1(pipe), fp);
3991 }
3992 }
3993
3994 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3995 struct drm_display_mode *adjusted_mode)
3996 {
3997 struct drm_device *dev = crtc->dev;
3998 struct drm_i915_private *dev_priv = dev->dev_private;
3999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4000 int pipe = intel_crtc->pipe;
4001 u32 temp;
4002
4003 temp = I915_READ(LVDS);
4004 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4005 if (pipe == 1) {
4006 temp |= LVDS_PIPEB_SELECT;
4007 } else {
4008 temp &= ~LVDS_PIPEB_SELECT;
4009 }
4010 /* set the corresponsding LVDS_BORDER bit */
4011 temp |= dev_priv->lvds_border_bits;
4012 /* Set the B0-B3 data pairs corresponding to whether we're going to
4013 * set the DPLLs for dual-channel mode or not.
4014 */
4015 if (clock->p2 == 7)
4016 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4017 else
4018 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4019
4020 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4021 * appropriately here, but we need to look more thoroughly into how
4022 * panels behave in the two modes.
4023 */
4024 /* set the dithering flag on LVDS as needed */
4025 if (INTEL_INFO(dev)->gen >= 4) {
4026 if (dev_priv->lvds_dither)
4027 temp |= LVDS_ENABLE_DITHER;
4028 else
4029 temp &= ~LVDS_ENABLE_DITHER;
4030 }
4031 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4032 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4033 temp |= LVDS_HSYNC_POLARITY;
4034 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4035 temp |= LVDS_VSYNC_POLARITY;
4036 I915_WRITE(LVDS, temp);
4037 }
4038
4039 static void vlv_update_pll(struct drm_crtc *crtc,
4040 struct drm_display_mode *mode,
4041 struct drm_display_mode *adjusted_mode,
4042 intel_clock_t *clock, intel_clock_t *reduced_clock,
4043 int refclk, int num_connectors)
4044 {
4045 struct drm_device *dev = crtc->dev;
4046 struct drm_i915_private *dev_priv = dev->dev_private;
4047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4048 int pipe = intel_crtc->pipe;
4049 u32 dpll, mdiv, pdiv;
4050 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4051 bool is_hdmi;
4052
4053 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4054
4055 bestn = clock->n;
4056 bestm1 = clock->m1;
4057 bestm2 = clock->m2;
4058 bestp1 = clock->p1;
4059 bestp2 = clock->p2;
4060
4061 /* Enable DPIO clock input */
4062 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4063 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4064 I915_WRITE(DPLL(pipe), dpll);
4065 POSTING_READ(DPLL(pipe));
4066
4067 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4068 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4069 mdiv |= ((bestn << DPIO_N_SHIFT));
4070 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4071 mdiv |= (1 << DPIO_K_SHIFT);
4072 mdiv |= DPIO_ENABLE_CALIBRATION;
4073 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4074
4075 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4076
4077 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4078 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4079 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4080 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4081
4082 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4083
4084 dpll |= DPLL_VCO_ENABLE;
4085 I915_WRITE(DPLL(pipe), dpll);
4086 POSTING_READ(DPLL(pipe));
4087 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4088 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4089
4090 if (is_hdmi) {
4091 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4092
4093 if (temp > 1)
4094 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4095 else
4096 temp = 0;
4097
4098 I915_WRITE(DPLL_MD(pipe), temp);
4099 POSTING_READ(DPLL_MD(pipe));
4100 }
4101
4102 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4103 }
4104
4105 static void i9xx_update_pll(struct drm_crtc *crtc,
4106 struct drm_display_mode *mode,
4107 struct drm_display_mode *adjusted_mode,
4108 intel_clock_t *clock, intel_clock_t *reduced_clock,
4109 int num_connectors)
4110 {
4111 struct drm_device *dev = crtc->dev;
4112 struct drm_i915_private *dev_priv = dev->dev_private;
4113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4114 int pipe = intel_crtc->pipe;
4115 u32 dpll;
4116 bool is_sdvo;
4117
4118 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4119 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4120
4121 dpll = DPLL_VGA_MODE_DIS;
4122
4123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4124 dpll |= DPLLB_MODE_LVDS;
4125 else
4126 dpll |= DPLLB_MODE_DAC_SERIAL;
4127 if (is_sdvo) {
4128 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4129 if (pixel_multiplier > 1) {
4130 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4131 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4132 }
4133 dpll |= DPLL_DVO_HIGH_SPEED;
4134 }
4135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4136 dpll |= DPLL_DVO_HIGH_SPEED;
4137
4138 /* compute bitmask from p1 value */
4139 if (IS_PINEVIEW(dev))
4140 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4141 else {
4142 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4143 if (IS_G4X(dev) && reduced_clock)
4144 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4145 }
4146 switch (clock->p2) {
4147 case 5:
4148 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4149 break;
4150 case 7:
4151 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4152 break;
4153 case 10:
4154 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4155 break;
4156 case 14:
4157 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4158 break;
4159 }
4160 if (INTEL_INFO(dev)->gen >= 4)
4161 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4162
4163 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4164 dpll |= PLL_REF_INPUT_TVCLKINBC;
4165 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4166 /* XXX: just matching BIOS for now */
4167 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4168 dpll |= 3;
4169 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4170 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4171 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4172 else
4173 dpll |= PLL_REF_INPUT_DREFCLK;
4174
4175 dpll |= DPLL_VCO_ENABLE;
4176 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4177 POSTING_READ(DPLL(pipe));
4178 udelay(150);
4179
4180 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4181 * This is an exception to the general rule that mode_set doesn't turn
4182 * things on.
4183 */
4184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4185 intel_update_lvds(crtc, clock, adjusted_mode);
4186
4187 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4188 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4189
4190 I915_WRITE(DPLL(pipe), dpll);
4191
4192 /* Wait for the clocks to stabilize. */
4193 POSTING_READ(DPLL(pipe));
4194 udelay(150);
4195
4196 if (INTEL_INFO(dev)->gen >= 4) {
4197 u32 temp = 0;
4198 if (is_sdvo) {
4199 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4200 if (temp > 1)
4201 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4202 else
4203 temp = 0;
4204 }
4205 I915_WRITE(DPLL_MD(pipe), temp);
4206 } else {
4207 /* The pixel multiplier can only be updated once the
4208 * DPLL is enabled and the clocks are stable.
4209 *
4210 * So write it again.
4211 */
4212 I915_WRITE(DPLL(pipe), dpll);
4213 }
4214 }
4215
4216 static void i8xx_update_pll(struct drm_crtc *crtc,
4217 struct drm_display_mode *adjusted_mode,
4218 intel_clock_t *clock,
4219 int num_connectors)
4220 {
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4224 int pipe = intel_crtc->pipe;
4225 u32 dpll;
4226
4227 dpll = DPLL_VGA_MODE_DIS;
4228
4229 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4230 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4231 } else {
4232 if (clock->p1 == 2)
4233 dpll |= PLL_P1_DIVIDE_BY_TWO;
4234 else
4235 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4236 if (clock->p2 == 4)
4237 dpll |= PLL_P2_DIVIDE_BY_4;
4238 }
4239
4240 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4241 /* XXX: just matching BIOS for now */
4242 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4243 dpll |= 3;
4244 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4245 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4246 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4247 else
4248 dpll |= PLL_REF_INPUT_DREFCLK;
4249
4250 dpll |= DPLL_VCO_ENABLE;
4251 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4252 POSTING_READ(DPLL(pipe));
4253 udelay(150);
4254
4255 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4256 * This is an exception to the general rule that mode_set doesn't turn
4257 * things on.
4258 */
4259 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4260 intel_update_lvds(crtc, clock, adjusted_mode);
4261
4262 I915_WRITE(DPLL(pipe), dpll);
4263
4264 /* Wait for the clocks to stabilize. */
4265 POSTING_READ(DPLL(pipe));
4266 udelay(150);
4267
4268 /* The pixel multiplier can only be updated once the
4269 * DPLL is enabled and the clocks are stable.
4270 *
4271 * So write it again.
4272 */
4273 I915_WRITE(DPLL(pipe), dpll);
4274 }
4275
4276 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4277 struct drm_display_mode *mode,
4278 struct drm_display_mode *adjusted_mode,
4279 int x, int y,
4280 struct drm_framebuffer *fb)
4281 {
4282 struct drm_device *dev = crtc->dev;
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285 int pipe = intel_crtc->pipe;
4286 int plane = intel_crtc->plane;
4287 int refclk, num_connectors = 0;
4288 intel_clock_t clock, reduced_clock;
4289 u32 dspcntr, pipeconf, vsyncshift;
4290 bool ok, has_reduced_clock = false, is_sdvo = false;
4291 bool is_lvds = false, is_tv = false, is_dp = false;
4292 struct intel_encoder *encoder;
4293 const intel_limit_t *limit;
4294 int ret;
4295
4296 for_each_encoder_on_crtc(dev, crtc, encoder) {
4297 switch (encoder->type) {
4298 case INTEL_OUTPUT_LVDS:
4299 is_lvds = true;
4300 break;
4301 case INTEL_OUTPUT_SDVO:
4302 case INTEL_OUTPUT_HDMI:
4303 is_sdvo = true;
4304 if (encoder->needs_tv_clock)
4305 is_tv = true;
4306 break;
4307 case INTEL_OUTPUT_TVOUT:
4308 is_tv = true;
4309 break;
4310 case INTEL_OUTPUT_DISPLAYPORT:
4311 is_dp = true;
4312 break;
4313 }
4314
4315 num_connectors++;
4316 }
4317
4318 refclk = i9xx_get_refclk(crtc, num_connectors);
4319
4320 /*
4321 * Returns a set of divisors for the desired target clock with the given
4322 * refclk, or FALSE. The returned values represent the clock equation:
4323 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4324 */
4325 limit = intel_limit(crtc, refclk);
4326 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4327 &clock);
4328 if (!ok) {
4329 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4330 return -EINVAL;
4331 }
4332
4333 /* Ensure that the cursor is valid for the new mode before changing... */
4334 intel_crtc_update_cursor(crtc, true);
4335
4336 if (is_lvds && dev_priv->lvds_downclock_avail) {
4337 /*
4338 * Ensure we match the reduced clock's P to the target clock.
4339 * If the clocks don't match, we can't switch the display clock
4340 * by using the FP0/FP1. In such case we will disable the LVDS
4341 * downclock feature.
4342 */
4343 has_reduced_clock = limit->find_pll(limit, crtc,
4344 dev_priv->lvds_downclock,
4345 refclk,
4346 &clock,
4347 &reduced_clock);
4348 }
4349
4350 if (is_sdvo && is_tv)
4351 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4352
4353 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4354 &reduced_clock : NULL);
4355
4356 if (IS_GEN2(dev))
4357 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4358 else if (IS_VALLEYVIEW(dev))
4359 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4360 refclk, num_connectors);
4361 else
4362 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4363 has_reduced_clock ? &reduced_clock : NULL,
4364 num_connectors);
4365
4366 /* setup pipeconf */
4367 pipeconf = I915_READ(PIPECONF(pipe));
4368
4369 /* Set up the display plane register */
4370 dspcntr = DISPPLANE_GAMMA_ENABLE;
4371
4372 if (pipe == 0)
4373 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4374 else
4375 dspcntr |= DISPPLANE_SEL_PIPE_B;
4376
4377 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4378 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4379 * core speed.
4380 *
4381 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4382 * pipe == 0 check?
4383 */
4384 if (mode->clock >
4385 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4386 pipeconf |= PIPECONF_DOUBLE_WIDE;
4387 else
4388 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4389 }
4390
4391 /* default to 8bpc */
4392 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4393 if (is_dp) {
4394 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4395 pipeconf |= PIPECONF_BPP_6 |
4396 PIPECONF_DITHER_EN |
4397 PIPECONF_DITHER_TYPE_SP;
4398 }
4399 }
4400
4401 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4402 drm_mode_debug_printmodeline(mode);
4403
4404 if (HAS_PIPE_CXSR(dev)) {
4405 if (intel_crtc->lowfreq_avail) {
4406 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4407 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4408 } else {
4409 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4410 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4411 }
4412 }
4413
4414 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4415 if (!IS_GEN2(dev) &&
4416 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4417 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4418 /* the chip adds 2 halflines automatically */
4419 adjusted_mode->crtc_vtotal -= 1;
4420 adjusted_mode->crtc_vblank_end -= 1;
4421 vsyncshift = adjusted_mode->crtc_hsync_start
4422 - adjusted_mode->crtc_htotal/2;
4423 } else {
4424 pipeconf |= PIPECONF_PROGRESSIVE;
4425 vsyncshift = 0;
4426 }
4427
4428 if (!IS_GEN3(dev))
4429 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4430
4431 I915_WRITE(HTOTAL(pipe),
4432 (adjusted_mode->crtc_hdisplay - 1) |
4433 ((adjusted_mode->crtc_htotal - 1) << 16));
4434 I915_WRITE(HBLANK(pipe),
4435 (adjusted_mode->crtc_hblank_start - 1) |
4436 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4437 I915_WRITE(HSYNC(pipe),
4438 (adjusted_mode->crtc_hsync_start - 1) |
4439 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4440
4441 I915_WRITE(VTOTAL(pipe),
4442 (adjusted_mode->crtc_vdisplay - 1) |
4443 ((adjusted_mode->crtc_vtotal - 1) << 16));
4444 I915_WRITE(VBLANK(pipe),
4445 (adjusted_mode->crtc_vblank_start - 1) |
4446 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4447 I915_WRITE(VSYNC(pipe),
4448 (adjusted_mode->crtc_vsync_start - 1) |
4449 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4450
4451 /* pipesrc and dspsize control the size that is scaled from,
4452 * which should always be the user's requested size.
4453 */
4454 I915_WRITE(DSPSIZE(plane),
4455 ((mode->vdisplay - 1) << 16) |
4456 (mode->hdisplay - 1));
4457 I915_WRITE(DSPPOS(plane), 0);
4458 I915_WRITE(PIPESRC(pipe),
4459 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4460
4461 I915_WRITE(PIPECONF(pipe), pipeconf);
4462 POSTING_READ(PIPECONF(pipe));
4463 intel_enable_pipe(dev_priv, pipe, false);
4464
4465 intel_wait_for_vblank(dev, pipe);
4466
4467 I915_WRITE(DSPCNTR(plane), dspcntr);
4468 POSTING_READ(DSPCNTR(plane));
4469
4470 ret = intel_pipe_set_base(crtc, x, y, fb);
4471
4472 intel_update_watermarks(dev);
4473
4474 return ret;
4475 }
4476
4477 /*
4478 * Initialize reference clocks when the driver loads
4479 */
4480 void ironlake_init_pch_refclk(struct drm_device *dev)
4481 {
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 struct drm_mode_config *mode_config = &dev->mode_config;
4484 struct intel_encoder *encoder;
4485 u32 temp;
4486 bool has_lvds = false;
4487 bool has_cpu_edp = false;
4488 bool has_pch_edp = false;
4489 bool has_panel = false;
4490 bool has_ck505 = false;
4491 bool can_ssc = false;
4492
4493 /* We need to take the global config into account */
4494 list_for_each_entry(encoder, &mode_config->encoder_list,
4495 base.head) {
4496 switch (encoder->type) {
4497 case INTEL_OUTPUT_LVDS:
4498 has_panel = true;
4499 has_lvds = true;
4500 break;
4501 case INTEL_OUTPUT_EDP:
4502 has_panel = true;
4503 if (intel_encoder_is_pch_edp(&encoder->base))
4504 has_pch_edp = true;
4505 else
4506 has_cpu_edp = true;
4507 break;
4508 }
4509 }
4510
4511 if (HAS_PCH_IBX(dev)) {
4512 has_ck505 = dev_priv->display_clock_mode;
4513 can_ssc = has_ck505;
4514 } else {
4515 has_ck505 = false;
4516 can_ssc = true;
4517 }
4518
4519 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4520 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4521 has_ck505);
4522
4523 /* Ironlake: try to setup display ref clock before DPLL
4524 * enabling. This is only under driver's control after
4525 * PCH B stepping, previous chipset stepping should be
4526 * ignoring this setting.
4527 */
4528 temp = I915_READ(PCH_DREF_CONTROL);
4529 /* Always enable nonspread source */
4530 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4531
4532 if (has_ck505)
4533 temp |= DREF_NONSPREAD_CK505_ENABLE;
4534 else
4535 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4536
4537 if (has_panel) {
4538 temp &= ~DREF_SSC_SOURCE_MASK;
4539 temp |= DREF_SSC_SOURCE_ENABLE;
4540
4541 /* SSC must be turned on before enabling the CPU output */
4542 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4543 DRM_DEBUG_KMS("Using SSC on panel\n");
4544 temp |= DREF_SSC1_ENABLE;
4545 } else
4546 temp &= ~DREF_SSC1_ENABLE;
4547
4548 /* Get SSC going before enabling the outputs */
4549 I915_WRITE(PCH_DREF_CONTROL, temp);
4550 POSTING_READ(PCH_DREF_CONTROL);
4551 udelay(200);
4552
4553 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4554
4555 /* Enable CPU source on CPU attached eDP */
4556 if (has_cpu_edp) {
4557 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4558 DRM_DEBUG_KMS("Using SSC on eDP\n");
4559 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4560 }
4561 else
4562 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4563 } else
4564 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4565
4566 I915_WRITE(PCH_DREF_CONTROL, temp);
4567 POSTING_READ(PCH_DREF_CONTROL);
4568 udelay(200);
4569 } else {
4570 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4571
4572 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4573
4574 /* Turn off CPU output */
4575 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4576
4577 I915_WRITE(PCH_DREF_CONTROL, temp);
4578 POSTING_READ(PCH_DREF_CONTROL);
4579 udelay(200);
4580
4581 /* Turn off the SSC source */
4582 temp &= ~DREF_SSC_SOURCE_MASK;
4583 temp |= DREF_SSC_SOURCE_DISABLE;
4584
4585 /* Turn off SSC1 */
4586 temp &= ~ DREF_SSC1_ENABLE;
4587
4588 I915_WRITE(PCH_DREF_CONTROL, temp);
4589 POSTING_READ(PCH_DREF_CONTROL);
4590 udelay(200);
4591 }
4592 }
4593
4594 static int ironlake_get_refclk(struct drm_crtc *crtc)
4595 {
4596 struct drm_device *dev = crtc->dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 struct intel_encoder *encoder;
4599 struct intel_encoder *edp_encoder = NULL;
4600 int num_connectors = 0;
4601 bool is_lvds = false;
4602
4603 for_each_encoder_on_crtc(dev, crtc, encoder) {
4604 switch (encoder->type) {
4605 case INTEL_OUTPUT_LVDS:
4606 is_lvds = true;
4607 break;
4608 case INTEL_OUTPUT_EDP:
4609 edp_encoder = encoder;
4610 break;
4611 }
4612 num_connectors++;
4613 }
4614
4615 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4616 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4617 dev_priv->lvds_ssc_freq);
4618 return dev_priv->lvds_ssc_freq * 1000;
4619 }
4620
4621 return 120000;
4622 }
4623
4624 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4625 struct drm_display_mode *adjusted_mode,
4626 bool dither)
4627 {
4628 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4630 int pipe = intel_crtc->pipe;
4631 uint32_t val;
4632
4633 val = I915_READ(PIPECONF(pipe));
4634
4635 val &= ~PIPE_BPC_MASK;
4636 switch (intel_crtc->bpp) {
4637 case 18:
4638 val |= PIPE_6BPC;
4639 break;
4640 case 24:
4641 val |= PIPE_8BPC;
4642 break;
4643 case 30:
4644 val |= PIPE_10BPC;
4645 break;
4646 case 36:
4647 val |= PIPE_12BPC;
4648 break;
4649 default:
4650 val |= PIPE_8BPC;
4651 break;
4652 }
4653
4654 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4655 if (dither)
4656 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4657
4658 val &= ~PIPECONF_INTERLACE_MASK;
4659 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4660 val |= PIPECONF_INTERLACED_ILK;
4661 else
4662 val |= PIPECONF_PROGRESSIVE;
4663
4664 I915_WRITE(PIPECONF(pipe), val);
4665 POSTING_READ(PIPECONF(pipe));
4666 }
4667
4668 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4669 struct drm_display_mode *adjusted_mode,
4670 intel_clock_t *clock,
4671 bool *has_reduced_clock,
4672 intel_clock_t *reduced_clock)
4673 {
4674 struct drm_device *dev = crtc->dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 struct intel_encoder *intel_encoder;
4677 int refclk;
4678 const intel_limit_t *limit;
4679 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4680
4681 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4682 switch (intel_encoder->type) {
4683 case INTEL_OUTPUT_LVDS:
4684 is_lvds = true;
4685 break;
4686 case INTEL_OUTPUT_SDVO:
4687 case INTEL_OUTPUT_HDMI:
4688 is_sdvo = true;
4689 if (intel_encoder->needs_tv_clock)
4690 is_tv = true;
4691 break;
4692 case INTEL_OUTPUT_TVOUT:
4693 is_tv = true;
4694 break;
4695 }
4696 }
4697
4698 refclk = ironlake_get_refclk(crtc);
4699
4700 /*
4701 * Returns a set of divisors for the desired target clock with the given
4702 * refclk, or FALSE. The returned values represent the clock equation:
4703 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4704 */
4705 limit = intel_limit(crtc, refclk);
4706 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4707 clock);
4708 if (!ret)
4709 return false;
4710
4711 if (is_lvds && dev_priv->lvds_downclock_avail) {
4712 /*
4713 * Ensure we match the reduced clock's P to the target clock.
4714 * If the clocks don't match, we can't switch the display clock
4715 * by using the FP0/FP1. In such case we will disable the LVDS
4716 * downclock feature.
4717 */
4718 *has_reduced_clock = limit->find_pll(limit, crtc,
4719 dev_priv->lvds_downclock,
4720 refclk,
4721 clock,
4722 reduced_clock);
4723 }
4724
4725 if (is_sdvo && is_tv)
4726 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4727
4728 return true;
4729 }
4730
4731 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4732 struct drm_display_mode *mode,
4733 struct drm_display_mode *adjusted_mode,
4734 int x, int y,
4735 struct drm_framebuffer *fb)
4736 {
4737 struct drm_device *dev = crtc->dev;
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740 int pipe = intel_crtc->pipe;
4741 int plane = intel_crtc->plane;
4742 int num_connectors = 0;
4743 intel_clock_t clock, reduced_clock;
4744 u32 dpll, fp = 0, fp2 = 0;
4745 bool ok, has_reduced_clock = false, is_sdvo = false;
4746 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4747 struct intel_encoder *encoder, *edp_encoder = NULL;
4748 int ret;
4749 struct fdi_m_n m_n = {0};
4750 u32 temp;
4751 int target_clock, pixel_multiplier, lane, link_bw, factor;
4752 unsigned int pipe_bpp;
4753 bool dither;
4754 bool is_cpu_edp = false, is_pch_edp = false;
4755
4756 for_each_encoder_on_crtc(dev, crtc, encoder) {
4757 switch (encoder->type) {
4758 case INTEL_OUTPUT_LVDS:
4759 is_lvds = true;
4760 break;
4761 case INTEL_OUTPUT_SDVO:
4762 case INTEL_OUTPUT_HDMI:
4763 is_sdvo = true;
4764 if (encoder->needs_tv_clock)
4765 is_tv = true;
4766 break;
4767 case INTEL_OUTPUT_TVOUT:
4768 is_tv = true;
4769 break;
4770 case INTEL_OUTPUT_ANALOG:
4771 is_crt = true;
4772 break;
4773 case INTEL_OUTPUT_DISPLAYPORT:
4774 is_dp = true;
4775 break;
4776 case INTEL_OUTPUT_EDP:
4777 is_dp = true;
4778 if (intel_encoder_is_pch_edp(&encoder->base))
4779 is_pch_edp = true;
4780 else
4781 is_cpu_edp = true;
4782 edp_encoder = encoder;
4783 break;
4784 }
4785
4786 num_connectors++;
4787 }
4788
4789 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
4790 &has_reduced_clock, &reduced_clock);
4791 if (!ok) {
4792 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4793 return -EINVAL;
4794 }
4795
4796 /* Ensure that the cursor is valid for the new mode before changing... */
4797 intel_crtc_update_cursor(crtc, true);
4798
4799 /* FDI link */
4800 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4801 lane = 0;
4802 /* CPU eDP doesn't require FDI link, so just set DP M/N
4803 according to current link config */
4804 if (is_cpu_edp) {
4805 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4806 } else {
4807 /* FDI is a binary signal running at ~2.7GHz, encoding
4808 * each output octet as 10 bits. The actual frequency
4809 * is stored as a divider into a 100MHz clock, and the
4810 * mode pixel clock is stored in units of 1KHz.
4811 * Hence the bw of each lane in terms of the mode signal
4812 * is:
4813 */
4814 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4815 }
4816
4817 /* [e]DP over FDI requires target mode clock instead of link clock. */
4818 if (edp_encoder)
4819 target_clock = intel_edp_target_clock(edp_encoder, mode);
4820 else if (is_dp)
4821 target_clock = mode->clock;
4822 else
4823 target_clock = adjusted_mode->clock;
4824
4825 /* determine panel color depth */
4826 dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp,
4827 adjusted_mode);
4828 if (is_lvds && dev_priv->lvds_dither)
4829 dither = true;
4830
4831 if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
4832 pipe_bpp != 36) {
4833 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4834 pipe_bpp);
4835 pipe_bpp = 24;
4836 }
4837 intel_crtc->bpp = pipe_bpp;
4838
4839 if (!lane) {
4840 /*
4841 * Account for spread spectrum to avoid
4842 * oversubscribing the link. Max center spread
4843 * is 2.5%; use 5% for safety's sake.
4844 */
4845 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4846 lane = bps / (link_bw * 8) + 1;
4847 }
4848
4849 intel_crtc->fdi_lanes = lane;
4850
4851 if (pixel_multiplier > 1)
4852 link_bw *= pixel_multiplier;
4853 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4854 &m_n);
4855
4856 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4857 if (has_reduced_clock)
4858 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4859 reduced_clock.m2;
4860
4861 /* Enable autotuning of the PLL clock (if permissible) */
4862 factor = 21;
4863 if (is_lvds) {
4864 if ((intel_panel_use_ssc(dev_priv) &&
4865 dev_priv->lvds_ssc_freq == 100) ||
4866 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4867 factor = 25;
4868 } else if (is_sdvo && is_tv)
4869 factor = 20;
4870
4871 if (clock.m < factor * clock.n)
4872 fp |= FP_CB_TUNE;
4873
4874 dpll = 0;
4875
4876 if (is_lvds)
4877 dpll |= DPLLB_MODE_LVDS;
4878 else
4879 dpll |= DPLLB_MODE_DAC_SERIAL;
4880 if (is_sdvo) {
4881 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4882 if (pixel_multiplier > 1) {
4883 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4884 }
4885 dpll |= DPLL_DVO_HIGH_SPEED;
4886 }
4887 if (is_dp && !is_cpu_edp)
4888 dpll |= DPLL_DVO_HIGH_SPEED;
4889
4890 /* compute bitmask from p1 value */
4891 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4892 /* also FPA1 */
4893 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4894
4895 switch (clock.p2) {
4896 case 5:
4897 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4898 break;
4899 case 7:
4900 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4901 break;
4902 case 10:
4903 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4904 break;
4905 case 14:
4906 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4907 break;
4908 }
4909
4910 if (is_sdvo && is_tv)
4911 dpll |= PLL_REF_INPUT_TVCLKINBC;
4912 else if (is_tv)
4913 /* XXX: just matching BIOS for now */
4914 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4915 dpll |= 3;
4916 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4917 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4918 else
4919 dpll |= PLL_REF_INPUT_DREFCLK;
4920
4921 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4922 drm_mode_debug_printmodeline(mode);
4923
4924 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4925 * pre-Haswell/LPT generation */
4926 if (HAS_PCH_LPT(dev)) {
4927 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4928 pipe);
4929 } else if (!is_cpu_edp) {
4930 struct intel_pch_pll *pll;
4931
4932 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4933 if (pll == NULL) {
4934 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4935 pipe);
4936 return -EINVAL;
4937 }
4938 } else
4939 intel_put_pch_pll(intel_crtc);
4940
4941 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4942 * This is an exception to the general rule that mode_set doesn't turn
4943 * things on.
4944 */
4945 if (is_lvds) {
4946 temp = I915_READ(PCH_LVDS);
4947 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4948 if (HAS_PCH_CPT(dev)) {
4949 temp &= ~PORT_TRANS_SEL_MASK;
4950 temp |= PORT_TRANS_SEL_CPT(pipe);
4951 } else {
4952 if (pipe == 1)
4953 temp |= LVDS_PIPEB_SELECT;
4954 else
4955 temp &= ~LVDS_PIPEB_SELECT;
4956 }
4957
4958 /* set the corresponsding LVDS_BORDER bit */
4959 temp |= dev_priv->lvds_border_bits;
4960 /* Set the B0-B3 data pairs corresponding to whether we're going to
4961 * set the DPLLs for dual-channel mode or not.
4962 */
4963 if (clock.p2 == 7)
4964 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4965 else
4966 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4967
4968 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4969 * appropriately here, but we need to look more thoroughly into how
4970 * panels behave in the two modes.
4971 */
4972 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4973 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4974 temp |= LVDS_HSYNC_POLARITY;
4975 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4976 temp |= LVDS_VSYNC_POLARITY;
4977 I915_WRITE(PCH_LVDS, temp);
4978 }
4979
4980 if (is_dp && !is_cpu_edp) {
4981 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4982 } else {
4983 /* For non-DP output, clear any trans DP clock recovery setting.*/
4984 I915_WRITE(TRANSDATA_M1(pipe), 0);
4985 I915_WRITE(TRANSDATA_N1(pipe), 0);
4986 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4987 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4988 }
4989
4990 if (intel_crtc->pch_pll) {
4991 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4992
4993 /* Wait for the clocks to stabilize. */
4994 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4995 udelay(150);
4996
4997 /* The pixel multiplier can only be updated once the
4998 * DPLL is enabled and the clocks are stable.
4999 *
5000 * So write it again.
5001 */
5002 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5003 }
5004
5005 intel_crtc->lowfreq_avail = false;
5006 if (intel_crtc->pch_pll) {
5007 if (is_lvds && has_reduced_clock && i915_powersave) {
5008 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5009 intel_crtc->lowfreq_avail = true;
5010 } else {
5011 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5012 }
5013 }
5014
5015 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5016 /* the chip adds 2 halflines automatically */
5017 adjusted_mode->crtc_vtotal -= 1;
5018 adjusted_mode->crtc_vblank_end -= 1;
5019 I915_WRITE(VSYNCSHIFT(pipe),
5020 adjusted_mode->crtc_hsync_start
5021 - adjusted_mode->crtc_htotal/2);
5022 } else {
5023 I915_WRITE(VSYNCSHIFT(pipe), 0);
5024 }
5025
5026 I915_WRITE(HTOTAL(pipe),
5027 (adjusted_mode->crtc_hdisplay - 1) |
5028 ((adjusted_mode->crtc_htotal - 1) << 16));
5029 I915_WRITE(HBLANK(pipe),
5030 (adjusted_mode->crtc_hblank_start - 1) |
5031 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5032 I915_WRITE(HSYNC(pipe),
5033 (adjusted_mode->crtc_hsync_start - 1) |
5034 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5035
5036 I915_WRITE(VTOTAL(pipe),
5037 (adjusted_mode->crtc_vdisplay - 1) |
5038 ((adjusted_mode->crtc_vtotal - 1) << 16));
5039 I915_WRITE(VBLANK(pipe),
5040 (adjusted_mode->crtc_vblank_start - 1) |
5041 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5042 I915_WRITE(VSYNC(pipe),
5043 (adjusted_mode->crtc_vsync_start - 1) |
5044 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5045
5046 /* pipesrc controls the size that is scaled from, which should
5047 * always be the user's requested size.
5048 */
5049 I915_WRITE(PIPESRC(pipe),
5050 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5051
5052 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5053 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5054 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5055 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5056
5057 if (is_cpu_edp)
5058 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5059
5060 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5061
5062 intel_wait_for_vblank(dev, pipe);
5063
5064 /* Set up the display plane register */
5065 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5066 POSTING_READ(DSPCNTR(plane));
5067
5068 ret = intel_pipe_set_base(crtc, x, y, fb);
5069
5070 intel_update_watermarks(dev);
5071
5072 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5073
5074 return ret;
5075 }
5076
5077 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5078 struct drm_display_mode *mode,
5079 struct drm_display_mode *adjusted_mode,
5080 int x, int y,
5081 struct drm_framebuffer *fb)
5082 {
5083 struct drm_device *dev = crtc->dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5086 int pipe = intel_crtc->pipe;
5087 int ret;
5088
5089 drm_vblank_pre_modeset(dev, pipe);
5090
5091 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5092 x, y, fb);
5093 drm_vblank_post_modeset(dev, pipe);
5094
5095 return ret;
5096 }
5097
5098 static bool intel_eld_uptodate(struct drm_connector *connector,
5099 int reg_eldv, uint32_t bits_eldv,
5100 int reg_elda, uint32_t bits_elda,
5101 int reg_edid)
5102 {
5103 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5104 uint8_t *eld = connector->eld;
5105 uint32_t i;
5106
5107 i = I915_READ(reg_eldv);
5108 i &= bits_eldv;
5109
5110 if (!eld[0])
5111 return !i;
5112
5113 if (!i)
5114 return false;
5115
5116 i = I915_READ(reg_elda);
5117 i &= ~bits_elda;
5118 I915_WRITE(reg_elda, i);
5119
5120 for (i = 0; i < eld[2]; i++)
5121 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5122 return false;
5123
5124 return true;
5125 }
5126
5127 static void g4x_write_eld(struct drm_connector *connector,
5128 struct drm_crtc *crtc)
5129 {
5130 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5131 uint8_t *eld = connector->eld;
5132 uint32_t eldv;
5133 uint32_t len;
5134 uint32_t i;
5135
5136 i = I915_READ(G4X_AUD_VID_DID);
5137
5138 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5139 eldv = G4X_ELDV_DEVCL_DEVBLC;
5140 else
5141 eldv = G4X_ELDV_DEVCTG;
5142
5143 if (intel_eld_uptodate(connector,
5144 G4X_AUD_CNTL_ST, eldv,
5145 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5146 G4X_HDMIW_HDMIEDID))
5147 return;
5148
5149 i = I915_READ(G4X_AUD_CNTL_ST);
5150 i &= ~(eldv | G4X_ELD_ADDR);
5151 len = (i >> 9) & 0x1f; /* ELD buffer size */
5152 I915_WRITE(G4X_AUD_CNTL_ST, i);
5153
5154 if (!eld[0])
5155 return;
5156
5157 len = min_t(uint8_t, eld[2], len);
5158 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5159 for (i = 0; i < len; i++)
5160 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5161
5162 i = I915_READ(G4X_AUD_CNTL_ST);
5163 i |= eldv;
5164 I915_WRITE(G4X_AUD_CNTL_ST, i);
5165 }
5166
5167 static void haswell_write_eld(struct drm_connector *connector,
5168 struct drm_crtc *crtc)
5169 {
5170 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5171 uint8_t *eld = connector->eld;
5172 struct drm_device *dev = crtc->dev;
5173 uint32_t eldv;
5174 uint32_t i;
5175 int len;
5176 int pipe = to_intel_crtc(crtc)->pipe;
5177 int tmp;
5178
5179 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5180 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5181 int aud_config = HSW_AUD_CFG(pipe);
5182 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5183
5184
5185 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5186
5187 /* Audio output enable */
5188 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5189 tmp = I915_READ(aud_cntrl_st2);
5190 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5191 I915_WRITE(aud_cntrl_st2, tmp);
5192
5193 /* Wait for 1 vertical blank */
5194 intel_wait_for_vblank(dev, pipe);
5195
5196 /* Set ELD valid state */
5197 tmp = I915_READ(aud_cntrl_st2);
5198 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5199 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5200 I915_WRITE(aud_cntrl_st2, tmp);
5201 tmp = I915_READ(aud_cntrl_st2);
5202 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5203
5204 /* Enable HDMI mode */
5205 tmp = I915_READ(aud_config);
5206 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5207 /* clear N_programing_enable and N_value_index */
5208 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5209 I915_WRITE(aud_config, tmp);
5210
5211 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5212
5213 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5214
5215 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5216 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5217 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5218 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5219 } else
5220 I915_WRITE(aud_config, 0);
5221
5222 if (intel_eld_uptodate(connector,
5223 aud_cntrl_st2, eldv,
5224 aud_cntl_st, IBX_ELD_ADDRESS,
5225 hdmiw_hdmiedid))
5226 return;
5227
5228 i = I915_READ(aud_cntrl_st2);
5229 i &= ~eldv;
5230 I915_WRITE(aud_cntrl_st2, i);
5231
5232 if (!eld[0])
5233 return;
5234
5235 i = I915_READ(aud_cntl_st);
5236 i &= ~IBX_ELD_ADDRESS;
5237 I915_WRITE(aud_cntl_st, i);
5238 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5239 DRM_DEBUG_DRIVER("port num:%d\n", i);
5240
5241 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5242 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5243 for (i = 0; i < len; i++)
5244 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5245
5246 i = I915_READ(aud_cntrl_st2);
5247 i |= eldv;
5248 I915_WRITE(aud_cntrl_st2, i);
5249
5250 }
5251
5252 static void ironlake_write_eld(struct drm_connector *connector,
5253 struct drm_crtc *crtc)
5254 {
5255 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5256 uint8_t *eld = connector->eld;
5257 uint32_t eldv;
5258 uint32_t i;
5259 int len;
5260 int hdmiw_hdmiedid;
5261 int aud_config;
5262 int aud_cntl_st;
5263 int aud_cntrl_st2;
5264 int pipe = to_intel_crtc(crtc)->pipe;
5265
5266 if (HAS_PCH_IBX(connector->dev)) {
5267 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5268 aud_config = IBX_AUD_CFG(pipe);
5269 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5270 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5271 } else {
5272 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5273 aud_config = CPT_AUD_CFG(pipe);
5274 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5275 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5276 }
5277
5278 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5279
5280 i = I915_READ(aud_cntl_st);
5281 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5282 if (!i) {
5283 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5284 /* operate blindly on all ports */
5285 eldv = IBX_ELD_VALIDB;
5286 eldv |= IBX_ELD_VALIDB << 4;
5287 eldv |= IBX_ELD_VALIDB << 8;
5288 } else {
5289 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5290 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5291 }
5292
5293 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5294 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5295 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5296 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5297 } else
5298 I915_WRITE(aud_config, 0);
5299
5300 if (intel_eld_uptodate(connector,
5301 aud_cntrl_st2, eldv,
5302 aud_cntl_st, IBX_ELD_ADDRESS,
5303 hdmiw_hdmiedid))
5304 return;
5305
5306 i = I915_READ(aud_cntrl_st2);
5307 i &= ~eldv;
5308 I915_WRITE(aud_cntrl_st2, i);
5309
5310 if (!eld[0])
5311 return;
5312
5313 i = I915_READ(aud_cntl_st);
5314 i &= ~IBX_ELD_ADDRESS;
5315 I915_WRITE(aud_cntl_st, i);
5316
5317 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5318 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5319 for (i = 0; i < len; i++)
5320 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5321
5322 i = I915_READ(aud_cntrl_st2);
5323 i |= eldv;
5324 I915_WRITE(aud_cntrl_st2, i);
5325 }
5326
5327 void intel_write_eld(struct drm_encoder *encoder,
5328 struct drm_display_mode *mode)
5329 {
5330 struct drm_crtc *crtc = encoder->crtc;
5331 struct drm_connector *connector;
5332 struct drm_device *dev = encoder->dev;
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334
5335 connector = drm_select_eld(encoder, mode);
5336 if (!connector)
5337 return;
5338
5339 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5340 connector->base.id,
5341 drm_get_connector_name(connector),
5342 connector->encoder->base.id,
5343 drm_get_encoder_name(connector->encoder));
5344
5345 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5346
5347 if (dev_priv->display.write_eld)
5348 dev_priv->display.write_eld(connector, crtc);
5349 }
5350
5351 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5352 void intel_crtc_load_lut(struct drm_crtc *crtc)
5353 {
5354 struct drm_device *dev = crtc->dev;
5355 struct drm_i915_private *dev_priv = dev->dev_private;
5356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5357 int palreg = PALETTE(intel_crtc->pipe);
5358 int i;
5359
5360 /* The clocks have to be on to load the palette. */
5361 if (!crtc->enabled || !intel_crtc->active)
5362 return;
5363
5364 /* use legacy palette for Ironlake */
5365 if (HAS_PCH_SPLIT(dev))
5366 palreg = LGC_PALETTE(intel_crtc->pipe);
5367
5368 for (i = 0; i < 256; i++) {
5369 I915_WRITE(palreg + 4 * i,
5370 (intel_crtc->lut_r[i] << 16) |
5371 (intel_crtc->lut_g[i] << 8) |
5372 intel_crtc->lut_b[i]);
5373 }
5374 }
5375
5376 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5377 {
5378 struct drm_device *dev = crtc->dev;
5379 struct drm_i915_private *dev_priv = dev->dev_private;
5380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5381 bool visible = base != 0;
5382 u32 cntl;
5383
5384 if (intel_crtc->cursor_visible == visible)
5385 return;
5386
5387 cntl = I915_READ(_CURACNTR);
5388 if (visible) {
5389 /* On these chipsets we can only modify the base whilst
5390 * the cursor is disabled.
5391 */
5392 I915_WRITE(_CURABASE, base);
5393
5394 cntl &= ~(CURSOR_FORMAT_MASK);
5395 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5396 cntl |= CURSOR_ENABLE |
5397 CURSOR_GAMMA_ENABLE |
5398 CURSOR_FORMAT_ARGB;
5399 } else
5400 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5401 I915_WRITE(_CURACNTR, cntl);
5402
5403 intel_crtc->cursor_visible = visible;
5404 }
5405
5406 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5407 {
5408 struct drm_device *dev = crtc->dev;
5409 struct drm_i915_private *dev_priv = dev->dev_private;
5410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5411 int pipe = intel_crtc->pipe;
5412 bool visible = base != 0;
5413
5414 if (intel_crtc->cursor_visible != visible) {
5415 uint32_t cntl = I915_READ(CURCNTR(pipe));
5416 if (base) {
5417 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5418 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5419 cntl |= pipe << 28; /* Connect to correct pipe */
5420 } else {
5421 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5422 cntl |= CURSOR_MODE_DISABLE;
5423 }
5424 I915_WRITE(CURCNTR(pipe), cntl);
5425
5426 intel_crtc->cursor_visible = visible;
5427 }
5428 /* and commit changes on next vblank */
5429 I915_WRITE(CURBASE(pipe), base);
5430 }
5431
5432 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5433 {
5434 struct drm_device *dev = crtc->dev;
5435 struct drm_i915_private *dev_priv = dev->dev_private;
5436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5437 int pipe = intel_crtc->pipe;
5438 bool visible = base != 0;
5439
5440 if (intel_crtc->cursor_visible != visible) {
5441 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5442 if (base) {
5443 cntl &= ~CURSOR_MODE;
5444 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5445 } else {
5446 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5447 cntl |= CURSOR_MODE_DISABLE;
5448 }
5449 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5450
5451 intel_crtc->cursor_visible = visible;
5452 }
5453 /* and commit changes on next vblank */
5454 I915_WRITE(CURBASE_IVB(pipe), base);
5455 }
5456
5457 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5458 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5459 bool on)
5460 {
5461 struct drm_device *dev = crtc->dev;
5462 struct drm_i915_private *dev_priv = dev->dev_private;
5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5464 int pipe = intel_crtc->pipe;
5465 int x = intel_crtc->cursor_x;
5466 int y = intel_crtc->cursor_y;
5467 u32 base, pos;
5468 bool visible;
5469
5470 pos = 0;
5471
5472 if (on && crtc->enabled && crtc->fb) {
5473 base = intel_crtc->cursor_addr;
5474 if (x > (int) crtc->fb->width)
5475 base = 0;
5476
5477 if (y > (int) crtc->fb->height)
5478 base = 0;
5479 } else
5480 base = 0;
5481
5482 if (x < 0) {
5483 if (x + intel_crtc->cursor_width < 0)
5484 base = 0;
5485
5486 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5487 x = -x;
5488 }
5489 pos |= x << CURSOR_X_SHIFT;
5490
5491 if (y < 0) {
5492 if (y + intel_crtc->cursor_height < 0)
5493 base = 0;
5494
5495 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5496 y = -y;
5497 }
5498 pos |= y << CURSOR_Y_SHIFT;
5499
5500 visible = base != 0;
5501 if (!visible && !intel_crtc->cursor_visible)
5502 return;
5503
5504 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5505 I915_WRITE(CURPOS_IVB(pipe), pos);
5506 ivb_update_cursor(crtc, base);
5507 } else {
5508 I915_WRITE(CURPOS(pipe), pos);
5509 if (IS_845G(dev) || IS_I865G(dev))
5510 i845_update_cursor(crtc, base);
5511 else
5512 i9xx_update_cursor(crtc, base);
5513 }
5514 }
5515
5516 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5517 struct drm_file *file,
5518 uint32_t handle,
5519 uint32_t width, uint32_t height)
5520 {
5521 struct drm_device *dev = crtc->dev;
5522 struct drm_i915_private *dev_priv = dev->dev_private;
5523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5524 struct drm_i915_gem_object *obj;
5525 uint32_t addr;
5526 int ret;
5527
5528 /* if we want to turn off the cursor ignore width and height */
5529 if (!handle) {
5530 DRM_DEBUG_KMS("cursor off\n");
5531 addr = 0;
5532 obj = NULL;
5533 mutex_lock(&dev->struct_mutex);
5534 goto finish;
5535 }
5536
5537 /* Currently we only support 64x64 cursors */
5538 if (width != 64 || height != 64) {
5539 DRM_ERROR("we currently only support 64x64 cursors\n");
5540 return -EINVAL;
5541 }
5542
5543 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5544 if (&obj->base == NULL)
5545 return -ENOENT;
5546
5547 if (obj->base.size < width * height * 4) {
5548 DRM_ERROR("buffer is to small\n");
5549 ret = -ENOMEM;
5550 goto fail;
5551 }
5552
5553 /* we only need to pin inside GTT if cursor is non-phy */
5554 mutex_lock(&dev->struct_mutex);
5555 if (!dev_priv->info->cursor_needs_physical) {
5556 if (obj->tiling_mode) {
5557 DRM_ERROR("cursor cannot be tiled\n");
5558 ret = -EINVAL;
5559 goto fail_locked;
5560 }
5561
5562 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5563 if (ret) {
5564 DRM_ERROR("failed to move cursor bo into the GTT\n");
5565 goto fail_locked;
5566 }
5567
5568 ret = i915_gem_object_put_fence(obj);
5569 if (ret) {
5570 DRM_ERROR("failed to release fence for cursor");
5571 goto fail_unpin;
5572 }
5573
5574 addr = obj->gtt_offset;
5575 } else {
5576 int align = IS_I830(dev) ? 16 * 1024 : 256;
5577 ret = i915_gem_attach_phys_object(dev, obj,
5578 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5579 align);
5580 if (ret) {
5581 DRM_ERROR("failed to attach phys object\n");
5582 goto fail_locked;
5583 }
5584 addr = obj->phys_obj->handle->busaddr;
5585 }
5586
5587 if (IS_GEN2(dev))
5588 I915_WRITE(CURSIZE, (height << 12) | width);
5589
5590 finish:
5591 if (intel_crtc->cursor_bo) {
5592 if (dev_priv->info->cursor_needs_physical) {
5593 if (intel_crtc->cursor_bo != obj)
5594 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5595 } else
5596 i915_gem_object_unpin(intel_crtc->cursor_bo);
5597 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5598 }
5599
5600 mutex_unlock(&dev->struct_mutex);
5601
5602 intel_crtc->cursor_addr = addr;
5603 intel_crtc->cursor_bo = obj;
5604 intel_crtc->cursor_width = width;
5605 intel_crtc->cursor_height = height;
5606
5607 intel_crtc_update_cursor(crtc, true);
5608
5609 return 0;
5610 fail_unpin:
5611 i915_gem_object_unpin(obj);
5612 fail_locked:
5613 mutex_unlock(&dev->struct_mutex);
5614 fail:
5615 drm_gem_object_unreference_unlocked(&obj->base);
5616 return ret;
5617 }
5618
5619 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5620 {
5621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5622
5623 intel_crtc->cursor_x = x;
5624 intel_crtc->cursor_y = y;
5625
5626 intel_crtc_update_cursor(crtc, true);
5627
5628 return 0;
5629 }
5630
5631 /** Sets the color ramps on behalf of RandR */
5632 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5633 u16 blue, int regno)
5634 {
5635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5636
5637 intel_crtc->lut_r[regno] = red >> 8;
5638 intel_crtc->lut_g[regno] = green >> 8;
5639 intel_crtc->lut_b[regno] = blue >> 8;
5640 }
5641
5642 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5643 u16 *blue, int regno)
5644 {
5645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5646
5647 *red = intel_crtc->lut_r[regno] << 8;
5648 *green = intel_crtc->lut_g[regno] << 8;
5649 *blue = intel_crtc->lut_b[regno] << 8;
5650 }
5651
5652 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5653 u16 *blue, uint32_t start, uint32_t size)
5654 {
5655 int end = (start + size > 256) ? 256 : start + size, i;
5656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5657
5658 for (i = start; i < end; i++) {
5659 intel_crtc->lut_r[i] = red[i] >> 8;
5660 intel_crtc->lut_g[i] = green[i] >> 8;
5661 intel_crtc->lut_b[i] = blue[i] >> 8;
5662 }
5663
5664 intel_crtc_load_lut(crtc);
5665 }
5666
5667 /**
5668 * Get a pipe with a simple mode set on it for doing load-based monitor
5669 * detection.
5670 *
5671 * It will be up to the load-detect code to adjust the pipe as appropriate for
5672 * its requirements. The pipe will be connected to no other encoders.
5673 *
5674 * Currently this code will only succeed if there is a pipe with no encoders
5675 * configured for it. In the future, it could choose to temporarily disable
5676 * some outputs to free up a pipe for its use.
5677 *
5678 * \return crtc, or NULL if no pipes are available.
5679 */
5680
5681 /* VESA 640x480x72Hz mode to set on the pipe */
5682 static struct drm_display_mode load_detect_mode = {
5683 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5684 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5685 };
5686
5687 static struct drm_framebuffer *
5688 intel_framebuffer_create(struct drm_device *dev,
5689 struct drm_mode_fb_cmd2 *mode_cmd,
5690 struct drm_i915_gem_object *obj)
5691 {
5692 struct intel_framebuffer *intel_fb;
5693 int ret;
5694
5695 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5696 if (!intel_fb) {
5697 drm_gem_object_unreference_unlocked(&obj->base);
5698 return ERR_PTR(-ENOMEM);
5699 }
5700
5701 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5702 if (ret) {
5703 drm_gem_object_unreference_unlocked(&obj->base);
5704 kfree(intel_fb);
5705 return ERR_PTR(ret);
5706 }
5707
5708 return &intel_fb->base;
5709 }
5710
5711 static u32
5712 intel_framebuffer_pitch_for_width(int width, int bpp)
5713 {
5714 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5715 return ALIGN(pitch, 64);
5716 }
5717
5718 static u32
5719 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5720 {
5721 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5722 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5723 }
5724
5725 static struct drm_framebuffer *
5726 intel_framebuffer_create_for_mode(struct drm_device *dev,
5727 struct drm_display_mode *mode,
5728 int depth, int bpp)
5729 {
5730 struct drm_i915_gem_object *obj;
5731 struct drm_mode_fb_cmd2 mode_cmd;
5732
5733 obj = i915_gem_alloc_object(dev,
5734 intel_framebuffer_size_for_mode(mode, bpp));
5735 if (obj == NULL)
5736 return ERR_PTR(-ENOMEM);
5737
5738 mode_cmd.width = mode->hdisplay;
5739 mode_cmd.height = mode->vdisplay;
5740 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5741 bpp);
5742 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5743
5744 return intel_framebuffer_create(dev, &mode_cmd, obj);
5745 }
5746
5747 static struct drm_framebuffer *
5748 mode_fits_in_fbdev(struct drm_device *dev,
5749 struct drm_display_mode *mode)
5750 {
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 struct drm_i915_gem_object *obj;
5753 struct drm_framebuffer *fb;
5754
5755 if (dev_priv->fbdev == NULL)
5756 return NULL;
5757
5758 obj = dev_priv->fbdev->ifb.obj;
5759 if (obj == NULL)
5760 return NULL;
5761
5762 fb = &dev_priv->fbdev->ifb.base;
5763 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5764 fb->bits_per_pixel))
5765 return NULL;
5766
5767 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5768 return NULL;
5769
5770 return fb;
5771 }
5772
5773 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5774 struct drm_display_mode *mode,
5775 struct intel_load_detect_pipe *old)
5776 {
5777 struct intel_crtc *intel_crtc;
5778 struct intel_encoder *intel_encoder =
5779 intel_attached_encoder(connector);
5780 struct drm_crtc *possible_crtc;
5781 struct drm_encoder *encoder = &intel_encoder->base;
5782 struct drm_crtc *crtc = NULL;
5783 struct drm_device *dev = encoder->dev;
5784 struct drm_framebuffer *fb;
5785 int i = -1;
5786
5787 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5788 connector->base.id, drm_get_connector_name(connector),
5789 encoder->base.id, drm_get_encoder_name(encoder));
5790
5791 /*
5792 * Algorithm gets a little messy:
5793 *
5794 * - if the connector already has an assigned crtc, use it (but make
5795 * sure it's on first)
5796 *
5797 * - try to find the first unused crtc that can drive this connector,
5798 * and use that if we find one
5799 */
5800
5801 /* See if we already have a CRTC for this connector */
5802 if (encoder->crtc) {
5803 crtc = encoder->crtc;
5804
5805 old->dpms_mode = connector->dpms;
5806 old->load_detect_temp = false;
5807
5808 /* Make sure the crtc and connector are running */
5809 if (connector->dpms != DRM_MODE_DPMS_ON)
5810 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5811
5812 return true;
5813 }
5814
5815 /* Find an unused one (if possible) */
5816 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5817 i++;
5818 if (!(encoder->possible_crtcs & (1 << i)))
5819 continue;
5820 if (!possible_crtc->enabled) {
5821 crtc = possible_crtc;
5822 break;
5823 }
5824 }
5825
5826 /*
5827 * If we didn't find an unused CRTC, don't use any.
5828 */
5829 if (!crtc) {
5830 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5831 return false;
5832 }
5833
5834 intel_encoder->new_crtc = to_intel_crtc(crtc);
5835 to_intel_connector(connector)->new_encoder = intel_encoder;
5836
5837 intel_crtc = to_intel_crtc(crtc);
5838 old->dpms_mode = connector->dpms;
5839 old->load_detect_temp = true;
5840 old->release_fb = NULL;
5841
5842 if (!mode)
5843 mode = &load_detect_mode;
5844
5845 /* We need a framebuffer large enough to accommodate all accesses
5846 * that the plane may generate whilst we perform load detection.
5847 * We can not rely on the fbcon either being present (we get called
5848 * during its initialisation to detect all boot displays, or it may
5849 * not even exist) or that it is large enough to satisfy the
5850 * requested mode.
5851 */
5852 fb = mode_fits_in_fbdev(dev, mode);
5853 if (fb == NULL) {
5854 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5855 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5856 old->release_fb = fb;
5857 } else
5858 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5859 if (IS_ERR(fb)) {
5860 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5861 goto fail;
5862 }
5863
5864 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
5865 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5866 if (old->release_fb)
5867 old->release_fb->funcs->destroy(old->release_fb);
5868 goto fail;
5869 }
5870
5871 /* let the connector get through one full cycle before testing */
5872 intel_wait_for_vblank(dev, intel_crtc->pipe);
5873
5874 return true;
5875 fail:
5876 connector->encoder = NULL;
5877 encoder->crtc = NULL;
5878 return false;
5879 }
5880
5881 void intel_release_load_detect_pipe(struct drm_connector *connector,
5882 struct intel_load_detect_pipe *old)
5883 {
5884 struct intel_encoder *intel_encoder =
5885 intel_attached_encoder(connector);
5886 struct drm_encoder *encoder = &intel_encoder->base;
5887
5888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5889 connector->base.id, drm_get_connector_name(connector),
5890 encoder->base.id, drm_get_encoder_name(encoder));
5891
5892 if (old->load_detect_temp) {
5893 struct drm_crtc *crtc = encoder->crtc;
5894
5895 to_intel_connector(connector)->new_encoder = NULL;
5896 intel_encoder->new_crtc = NULL;
5897 intel_set_mode(crtc, NULL, 0, 0, NULL);
5898
5899 if (old->release_fb)
5900 old->release_fb->funcs->destroy(old->release_fb);
5901
5902 return;
5903 }
5904
5905 /* Switch crtc and encoder back off if necessary */
5906 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5907 connector->funcs->dpms(connector, old->dpms_mode);
5908 }
5909
5910 /* Returns the clock of the currently programmed mode of the given pipe. */
5911 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5912 {
5913 struct drm_i915_private *dev_priv = dev->dev_private;
5914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5915 int pipe = intel_crtc->pipe;
5916 u32 dpll = I915_READ(DPLL(pipe));
5917 u32 fp;
5918 intel_clock_t clock;
5919
5920 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5921 fp = I915_READ(FP0(pipe));
5922 else
5923 fp = I915_READ(FP1(pipe));
5924
5925 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5926 if (IS_PINEVIEW(dev)) {
5927 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5928 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5929 } else {
5930 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5931 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5932 }
5933
5934 if (!IS_GEN2(dev)) {
5935 if (IS_PINEVIEW(dev))
5936 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5937 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5938 else
5939 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5940 DPLL_FPA01_P1_POST_DIV_SHIFT);
5941
5942 switch (dpll & DPLL_MODE_MASK) {
5943 case DPLLB_MODE_DAC_SERIAL:
5944 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5945 5 : 10;
5946 break;
5947 case DPLLB_MODE_LVDS:
5948 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5949 7 : 14;
5950 break;
5951 default:
5952 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5953 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5954 return 0;
5955 }
5956
5957 /* XXX: Handle the 100Mhz refclk */
5958 intel_clock(dev, 96000, &clock);
5959 } else {
5960 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5961
5962 if (is_lvds) {
5963 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5964 DPLL_FPA01_P1_POST_DIV_SHIFT);
5965 clock.p2 = 14;
5966
5967 if ((dpll & PLL_REF_INPUT_MASK) ==
5968 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5969 /* XXX: might not be 66MHz */
5970 intel_clock(dev, 66000, &clock);
5971 } else
5972 intel_clock(dev, 48000, &clock);
5973 } else {
5974 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5975 clock.p1 = 2;
5976 else {
5977 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5978 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5979 }
5980 if (dpll & PLL_P2_DIVIDE_BY_4)
5981 clock.p2 = 4;
5982 else
5983 clock.p2 = 2;
5984
5985 intel_clock(dev, 48000, &clock);
5986 }
5987 }
5988
5989 /* XXX: It would be nice to validate the clocks, but we can't reuse
5990 * i830PllIsValid() because it relies on the xf86_config connector
5991 * configuration being accurate, which it isn't necessarily.
5992 */
5993
5994 return clock.dot;
5995 }
5996
5997 /** Returns the currently programmed mode of the given pipe. */
5998 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5999 struct drm_crtc *crtc)
6000 {
6001 struct drm_i915_private *dev_priv = dev->dev_private;
6002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6003 int pipe = intel_crtc->pipe;
6004 struct drm_display_mode *mode;
6005 int htot = I915_READ(HTOTAL(pipe));
6006 int hsync = I915_READ(HSYNC(pipe));
6007 int vtot = I915_READ(VTOTAL(pipe));
6008 int vsync = I915_READ(VSYNC(pipe));
6009
6010 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6011 if (!mode)
6012 return NULL;
6013
6014 mode->clock = intel_crtc_clock_get(dev, crtc);
6015 mode->hdisplay = (htot & 0xffff) + 1;
6016 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6017 mode->hsync_start = (hsync & 0xffff) + 1;
6018 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6019 mode->vdisplay = (vtot & 0xffff) + 1;
6020 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6021 mode->vsync_start = (vsync & 0xffff) + 1;
6022 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6023
6024 drm_mode_set_name(mode);
6025
6026 return mode;
6027 }
6028
6029 static void intel_increase_pllclock(struct drm_crtc *crtc)
6030 {
6031 struct drm_device *dev = crtc->dev;
6032 drm_i915_private_t *dev_priv = dev->dev_private;
6033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6034 int pipe = intel_crtc->pipe;
6035 int dpll_reg = DPLL(pipe);
6036 int dpll;
6037
6038 if (HAS_PCH_SPLIT(dev))
6039 return;
6040
6041 if (!dev_priv->lvds_downclock_avail)
6042 return;
6043
6044 dpll = I915_READ(dpll_reg);
6045 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6046 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6047
6048 assert_panel_unlocked(dev_priv, pipe);
6049
6050 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6051 I915_WRITE(dpll_reg, dpll);
6052 intel_wait_for_vblank(dev, pipe);
6053
6054 dpll = I915_READ(dpll_reg);
6055 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6056 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6057 }
6058 }
6059
6060 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6061 {
6062 struct drm_device *dev = crtc->dev;
6063 drm_i915_private_t *dev_priv = dev->dev_private;
6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6065
6066 if (HAS_PCH_SPLIT(dev))
6067 return;
6068
6069 if (!dev_priv->lvds_downclock_avail)
6070 return;
6071
6072 /*
6073 * Since this is called by a timer, we should never get here in
6074 * the manual case.
6075 */
6076 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6077 int pipe = intel_crtc->pipe;
6078 int dpll_reg = DPLL(pipe);
6079 int dpll;
6080
6081 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6082
6083 assert_panel_unlocked(dev_priv, pipe);
6084
6085 dpll = I915_READ(dpll_reg);
6086 dpll |= DISPLAY_RATE_SELECT_FPA1;
6087 I915_WRITE(dpll_reg, dpll);
6088 intel_wait_for_vblank(dev, pipe);
6089 dpll = I915_READ(dpll_reg);
6090 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6091 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6092 }
6093
6094 }
6095
6096 void intel_mark_busy(struct drm_device *dev)
6097 {
6098 i915_update_gfx_val(dev->dev_private);
6099 }
6100
6101 void intel_mark_idle(struct drm_device *dev)
6102 {
6103 }
6104
6105 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6106 {
6107 struct drm_device *dev = obj->base.dev;
6108 struct drm_crtc *crtc;
6109
6110 if (!i915_powersave)
6111 return;
6112
6113 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6114 if (!crtc->fb)
6115 continue;
6116
6117 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6118 intel_increase_pllclock(crtc);
6119 }
6120 }
6121
6122 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6123 {
6124 struct drm_device *dev = obj->base.dev;
6125 struct drm_crtc *crtc;
6126
6127 if (!i915_powersave)
6128 return;
6129
6130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6131 if (!crtc->fb)
6132 continue;
6133
6134 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6135 intel_decrease_pllclock(crtc);
6136 }
6137 }
6138
6139 static void intel_crtc_destroy(struct drm_crtc *crtc)
6140 {
6141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6142 struct drm_device *dev = crtc->dev;
6143 struct intel_unpin_work *work;
6144 unsigned long flags;
6145
6146 spin_lock_irqsave(&dev->event_lock, flags);
6147 work = intel_crtc->unpin_work;
6148 intel_crtc->unpin_work = NULL;
6149 spin_unlock_irqrestore(&dev->event_lock, flags);
6150
6151 if (work) {
6152 cancel_work_sync(&work->work);
6153 kfree(work);
6154 }
6155
6156 drm_crtc_cleanup(crtc);
6157
6158 kfree(intel_crtc);
6159 }
6160
6161 static void intel_unpin_work_fn(struct work_struct *__work)
6162 {
6163 struct intel_unpin_work *work =
6164 container_of(__work, struct intel_unpin_work, work);
6165
6166 mutex_lock(&work->dev->struct_mutex);
6167 intel_unpin_fb_obj(work->old_fb_obj);
6168 drm_gem_object_unreference(&work->pending_flip_obj->base);
6169 drm_gem_object_unreference(&work->old_fb_obj->base);
6170
6171 intel_update_fbc(work->dev);
6172 mutex_unlock(&work->dev->struct_mutex);
6173 kfree(work);
6174 }
6175
6176 static void do_intel_finish_page_flip(struct drm_device *dev,
6177 struct drm_crtc *crtc)
6178 {
6179 drm_i915_private_t *dev_priv = dev->dev_private;
6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181 struct intel_unpin_work *work;
6182 struct drm_i915_gem_object *obj;
6183 struct drm_pending_vblank_event *e;
6184 struct timeval tvbl;
6185 unsigned long flags;
6186
6187 /* Ignore early vblank irqs */
6188 if (intel_crtc == NULL)
6189 return;
6190
6191 spin_lock_irqsave(&dev->event_lock, flags);
6192 work = intel_crtc->unpin_work;
6193 if (work == NULL || !work->pending) {
6194 spin_unlock_irqrestore(&dev->event_lock, flags);
6195 return;
6196 }
6197
6198 intel_crtc->unpin_work = NULL;
6199
6200 if (work->event) {
6201 e = work->event;
6202 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6203
6204 e->event.tv_sec = tvbl.tv_sec;
6205 e->event.tv_usec = tvbl.tv_usec;
6206
6207 list_add_tail(&e->base.link,
6208 &e->base.file_priv->event_list);
6209 wake_up_interruptible(&e->base.file_priv->event_wait);
6210 }
6211
6212 drm_vblank_put(dev, intel_crtc->pipe);
6213
6214 spin_unlock_irqrestore(&dev->event_lock, flags);
6215
6216 obj = work->old_fb_obj;
6217
6218 atomic_clear_mask(1 << intel_crtc->plane,
6219 &obj->pending_flip.counter);
6220
6221 wake_up(&dev_priv->pending_flip_queue);
6222 schedule_work(&work->work);
6223
6224 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6225 }
6226
6227 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6228 {
6229 drm_i915_private_t *dev_priv = dev->dev_private;
6230 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6231
6232 do_intel_finish_page_flip(dev, crtc);
6233 }
6234
6235 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6236 {
6237 drm_i915_private_t *dev_priv = dev->dev_private;
6238 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6239
6240 do_intel_finish_page_flip(dev, crtc);
6241 }
6242
6243 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6244 {
6245 drm_i915_private_t *dev_priv = dev->dev_private;
6246 struct intel_crtc *intel_crtc =
6247 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6248 unsigned long flags;
6249
6250 spin_lock_irqsave(&dev->event_lock, flags);
6251 if (intel_crtc->unpin_work) {
6252 if ((++intel_crtc->unpin_work->pending) > 1)
6253 DRM_ERROR("Prepared flip multiple times\n");
6254 } else {
6255 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6256 }
6257 spin_unlock_irqrestore(&dev->event_lock, flags);
6258 }
6259
6260 static int intel_gen2_queue_flip(struct drm_device *dev,
6261 struct drm_crtc *crtc,
6262 struct drm_framebuffer *fb,
6263 struct drm_i915_gem_object *obj)
6264 {
6265 struct drm_i915_private *dev_priv = dev->dev_private;
6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6267 u32 flip_mask;
6268 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6269 int ret;
6270
6271 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6272 if (ret)
6273 goto err;
6274
6275 ret = intel_ring_begin(ring, 6);
6276 if (ret)
6277 goto err_unpin;
6278
6279 /* Can't queue multiple flips, so wait for the previous
6280 * one to finish before executing the next.
6281 */
6282 if (intel_crtc->plane)
6283 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6284 else
6285 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6286 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6287 intel_ring_emit(ring, MI_NOOP);
6288 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6289 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6290 intel_ring_emit(ring, fb->pitches[0]);
6291 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6292 intel_ring_emit(ring, 0); /* aux display base address, unused */
6293 intel_ring_advance(ring);
6294 return 0;
6295
6296 err_unpin:
6297 intel_unpin_fb_obj(obj);
6298 err:
6299 return ret;
6300 }
6301
6302 static int intel_gen3_queue_flip(struct drm_device *dev,
6303 struct drm_crtc *crtc,
6304 struct drm_framebuffer *fb,
6305 struct drm_i915_gem_object *obj)
6306 {
6307 struct drm_i915_private *dev_priv = dev->dev_private;
6308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6309 u32 flip_mask;
6310 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6311 int ret;
6312
6313 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6314 if (ret)
6315 goto err;
6316
6317 ret = intel_ring_begin(ring, 6);
6318 if (ret)
6319 goto err_unpin;
6320
6321 if (intel_crtc->plane)
6322 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6323 else
6324 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6325 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6326 intel_ring_emit(ring, MI_NOOP);
6327 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6328 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6329 intel_ring_emit(ring, fb->pitches[0]);
6330 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6331 intel_ring_emit(ring, MI_NOOP);
6332
6333 intel_ring_advance(ring);
6334 return 0;
6335
6336 err_unpin:
6337 intel_unpin_fb_obj(obj);
6338 err:
6339 return ret;
6340 }
6341
6342 static int intel_gen4_queue_flip(struct drm_device *dev,
6343 struct drm_crtc *crtc,
6344 struct drm_framebuffer *fb,
6345 struct drm_i915_gem_object *obj)
6346 {
6347 struct drm_i915_private *dev_priv = dev->dev_private;
6348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6349 uint32_t pf, pipesrc;
6350 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6351 int ret;
6352
6353 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6354 if (ret)
6355 goto err;
6356
6357 ret = intel_ring_begin(ring, 4);
6358 if (ret)
6359 goto err_unpin;
6360
6361 /* i965+ uses the linear or tiled offsets from the
6362 * Display Registers (which do not change across a page-flip)
6363 * so we need only reprogram the base address.
6364 */
6365 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6366 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6367 intel_ring_emit(ring, fb->pitches[0]);
6368 intel_ring_emit(ring,
6369 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6370 obj->tiling_mode);
6371
6372 /* XXX Enabling the panel-fitter across page-flip is so far
6373 * untested on non-native modes, so ignore it for now.
6374 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6375 */
6376 pf = 0;
6377 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6378 intel_ring_emit(ring, pf | pipesrc);
6379 intel_ring_advance(ring);
6380 return 0;
6381
6382 err_unpin:
6383 intel_unpin_fb_obj(obj);
6384 err:
6385 return ret;
6386 }
6387
6388 static int intel_gen6_queue_flip(struct drm_device *dev,
6389 struct drm_crtc *crtc,
6390 struct drm_framebuffer *fb,
6391 struct drm_i915_gem_object *obj)
6392 {
6393 struct drm_i915_private *dev_priv = dev->dev_private;
6394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6395 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6396 uint32_t pf, pipesrc;
6397 int ret;
6398
6399 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6400 if (ret)
6401 goto err;
6402
6403 ret = intel_ring_begin(ring, 4);
6404 if (ret)
6405 goto err_unpin;
6406
6407 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6408 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6409 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6410 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6411
6412 /* Contrary to the suggestions in the documentation,
6413 * "Enable Panel Fitter" does not seem to be required when page
6414 * flipping with a non-native mode, and worse causes a normal
6415 * modeset to fail.
6416 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6417 */
6418 pf = 0;
6419 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6420 intel_ring_emit(ring, pf | pipesrc);
6421 intel_ring_advance(ring);
6422 return 0;
6423
6424 err_unpin:
6425 intel_unpin_fb_obj(obj);
6426 err:
6427 return ret;
6428 }
6429
6430 /*
6431 * On gen7 we currently use the blit ring because (in early silicon at least)
6432 * the render ring doesn't give us interrpts for page flip completion, which
6433 * means clients will hang after the first flip is queued. Fortunately the
6434 * blit ring generates interrupts properly, so use it instead.
6435 */
6436 static int intel_gen7_queue_flip(struct drm_device *dev,
6437 struct drm_crtc *crtc,
6438 struct drm_framebuffer *fb,
6439 struct drm_i915_gem_object *obj)
6440 {
6441 struct drm_i915_private *dev_priv = dev->dev_private;
6442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6443 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6444 uint32_t plane_bit = 0;
6445 int ret;
6446
6447 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6448 if (ret)
6449 goto err;
6450
6451 switch(intel_crtc->plane) {
6452 case PLANE_A:
6453 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6454 break;
6455 case PLANE_B:
6456 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6457 break;
6458 case PLANE_C:
6459 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6460 break;
6461 default:
6462 WARN_ONCE(1, "unknown plane in flip command\n");
6463 ret = -ENODEV;
6464 goto err_unpin;
6465 }
6466
6467 ret = intel_ring_begin(ring, 4);
6468 if (ret)
6469 goto err_unpin;
6470
6471 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6472 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6473 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6474 intel_ring_emit(ring, (MI_NOOP));
6475 intel_ring_advance(ring);
6476 return 0;
6477
6478 err_unpin:
6479 intel_unpin_fb_obj(obj);
6480 err:
6481 return ret;
6482 }
6483
6484 static int intel_default_queue_flip(struct drm_device *dev,
6485 struct drm_crtc *crtc,
6486 struct drm_framebuffer *fb,
6487 struct drm_i915_gem_object *obj)
6488 {
6489 return -ENODEV;
6490 }
6491
6492 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6493 struct drm_framebuffer *fb,
6494 struct drm_pending_vblank_event *event)
6495 {
6496 struct drm_device *dev = crtc->dev;
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498 struct intel_framebuffer *intel_fb;
6499 struct drm_i915_gem_object *obj;
6500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6501 struct intel_unpin_work *work;
6502 unsigned long flags;
6503 int ret;
6504
6505 /* Can't change pixel format via MI display flips. */
6506 if (fb->pixel_format != crtc->fb->pixel_format)
6507 return -EINVAL;
6508
6509 /*
6510 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6511 * Note that pitch changes could also affect these register.
6512 */
6513 if (INTEL_INFO(dev)->gen > 3 &&
6514 (fb->offsets[0] != crtc->fb->offsets[0] ||
6515 fb->pitches[0] != crtc->fb->pitches[0]))
6516 return -EINVAL;
6517
6518 work = kzalloc(sizeof *work, GFP_KERNEL);
6519 if (work == NULL)
6520 return -ENOMEM;
6521
6522 work->event = event;
6523 work->dev = crtc->dev;
6524 intel_fb = to_intel_framebuffer(crtc->fb);
6525 work->old_fb_obj = intel_fb->obj;
6526 INIT_WORK(&work->work, intel_unpin_work_fn);
6527
6528 ret = drm_vblank_get(dev, intel_crtc->pipe);
6529 if (ret)
6530 goto free_work;
6531
6532 /* We borrow the event spin lock for protecting unpin_work */
6533 spin_lock_irqsave(&dev->event_lock, flags);
6534 if (intel_crtc->unpin_work) {
6535 spin_unlock_irqrestore(&dev->event_lock, flags);
6536 kfree(work);
6537 drm_vblank_put(dev, intel_crtc->pipe);
6538
6539 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6540 return -EBUSY;
6541 }
6542 intel_crtc->unpin_work = work;
6543 spin_unlock_irqrestore(&dev->event_lock, flags);
6544
6545 intel_fb = to_intel_framebuffer(fb);
6546 obj = intel_fb->obj;
6547
6548 ret = i915_mutex_lock_interruptible(dev);
6549 if (ret)
6550 goto cleanup;
6551
6552 /* Reference the objects for the scheduled work. */
6553 drm_gem_object_reference(&work->old_fb_obj->base);
6554 drm_gem_object_reference(&obj->base);
6555
6556 crtc->fb = fb;
6557
6558 work->pending_flip_obj = obj;
6559
6560 work->enable_stall_check = true;
6561
6562 /* Block clients from rendering to the new back buffer until
6563 * the flip occurs and the object is no longer visible.
6564 */
6565 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6566
6567 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6568 if (ret)
6569 goto cleanup_pending;
6570
6571 intel_disable_fbc(dev);
6572 intel_mark_fb_busy(obj);
6573 mutex_unlock(&dev->struct_mutex);
6574
6575 trace_i915_flip_request(intel_crtc->plane, obj);
6576
6577 return 0;
6578
6579 cleanup_pending:
6580 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6581 drm_gem_object_unreference(&work->old_fb_obj->base);
6582 drm_gem_object_unreference(&obj->base);
6583 mutex_unlock(&dev->struct_mutex);
6584
6585 cleanup:
6586 spin_lock_irqsave(&dev->event_lock, flags);
6587 intel_crtc->unpin_work = NULL;
6588 spin_unlock_irqrestore(&dev->event_lock, flags);
6589
6590 drm_vblank_put(dev, intel_crtc->pipe);
6591 free_work:
6592 kfree(work);
6593
6594 return ret;
6595 }
6596
6597 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6598 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6599 .load_lut = intel_crtc_load_lut,
6600 .disable = intel_crtc_noop,
6601 };
6602
6603 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6604 {
6605 struct intel_encoder *other_encoder;
6606 struct drm_crtc *crtc = &encoder->new_crtc->base;
6607
6608 if (WARN_ON(!crtc))
6609 return false;
6610
6611 list_for_each_entry(other_encoder,
6612 &crtc->dev->mode_config.encoder_list,
6613 base.head) {
6614
6615 if (&other_encoder->new_crtc->base != crtc ||
6616 encoder == other_encoder)
6617 continue;
6618 else
6619 return true;
6620 }
6621
6622 return false;
6623 }
6624
6625 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6626 struct drm_crtc *crtc)
6627 {
6628 struct drm_device *dev;
6629 struct drm_crtc *tmp;
6630 int crtc_mask = 1;
6631
6632 WARN(!crtc, "checking null crtc?\n");
6633
6634 dev = crtc->dev;
6635
6636 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6637 if (tmp == crtc)
6638 break;
6639 crtc_mask <<= 1;
6640 }
6641
6642 if (encoder->possible_crtcs & crtc_mask)
6643 return true;
6644 return false;
6645 }
6646
6647 /**
6648 * intel_modeset_update_staged_output_state
6649 *
6650 * Updates the staged output configuration state, e.g. after we've read out the
6651 * current hw state.
6652 */
6653 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6654 {
6655 struct intel_encoder *encoder;
6656 struct intel_connector *connector;
6657
6658 list_for_each_entry(connector, &dev->mode_config.connector_list,
6659 base.head) {
6660 connector->new_encoder =
6661 to_intel_encoder(connector->base.encoder);
6662 }
6663
6664 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6665 base.head) {
6666 encoder->new_crtc =
6667 to_intel_crtc(encoder->base.crtc);
6668 }
6669 }
6670
6671 /**
6672 * intel_modeset_commit_output_state
6673 *
6674 * This function copies the stage display pipe configuration to the real one.
6675 */
6676 static void intel_modeset_commit_output_state(struct drm_device *dev)
6677 {
6678 struct intel_encoder *encoder;
6679 struct intel_connector *connector;
6680
6681 list_for_each_entry(connector, &dev->mode_config.connector_list,
6682 base.head) {
6683 connector->base.encoder = &connector->new_encoder->base;
6684 }
6685
6686 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6687 base.head) {
6688 encoder->base.crtc = &encoder->new_crtc->base;
6689 }
6690 }
6691
6692 static struct drm_display_mode *
6693 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6694 struct drm_display_mode *mode)
6695 {
6696 struct drm_device *dev = crtc->dev;
6697 struct drm_display_mode *adjusted_mode;
6698 struct drm_encoder_helper_funcs *encoder_funcs;
6699 struct intel_encoder *encoder;
6700
6701 adjusted_mode = drm_mode_duplicate(dev, mode);
6702 if (!adjusted_mode)
6703 return ERR_PTR(-ENOMEM);
6704
6705 /* Pass our mode to the connectors and the CRTC to give them a chance to
6706 * adjust it according to limitations or connector properties, and also
6707 * a chance to reject the mode entirely.
6708 */
6709 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6710 base.head) {
6711
6712 if (&encoder->new_crtc->base != crtc)
6713 continue;
6714 encoder_funcs = encoder->base.helper_private;
6715 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6716 adjusted_mode))) {
6717 DRM_DEBUG_KMS("Encoder fixup failed\n");
6718 goto fail;
6719 }
6720 }
6721
6722 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6723 DRM_DEBUG_KMS("CRTC fixup failed\n");
6724 goto fail;
6725 }
6726 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6727
6728 return adjusted_mode;
6729 fail:
6730 drm_mode_destroy(dev, adjusted_mode);
6731 return ERR_PTR(-EINVAL);
6732 }
6733
6734 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6735 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6736 static void
6737 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6738 unsigned *prepare_pipes, unsigned *disable_pipes)
6739 {
6740 struct intel_crtc *intel_crtc;
6741 struct drm_device *dev = crtc->dev;
6742 struct intel_encoder *encoder;
6743 struct intel_connector *connector;
6744 struct drm_crtc *tmp_crtc;
6745
6746 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
6747
6748 /* Check which crtcs have changed outputs connected to them, these need
6749 * to be part of the prepare_pipes mask. We don't (yet) support global
6750 * modeset across multiple crtcs, so modeset_pipes will only have one
6751 * bit set at most. */
6752 list_for_each_entry(connector, &dev->mode_config.connector_list,
6753 base.head) {
6754 if (connector->base.encoder == &connector->new_encoder->base)
6755 continue;
6756
6757 if (connector->base.encoder) {
6758 tmp_crtc = connector->base.encoder->crtc;
6759
6760 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6761 }
6762
6763 if (connector->new_encoder)
6764 *prepare_pipes |=
6765 1 << connector->new_encoder->new_crtc->pipe;
6766 }
6767
6768 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6769 base.head) {
6770 if (encoder->base.crtc == &encoder->new_crtc->base)
6771 continue;
6772
6773 if (encoder->base.crtc) {
6774 tmp_crtc = encoder->base.crtc;
6775
6776 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6777 }
6778
6779 if (encoder->new_crtc)
6780 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
6781 }
6782
6783 /* Check for any pipes that will be fully disabled ... */
6784 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6785 base.head) {
6786 bool used = false;
6787
6788 /* Don't try to disable disabled crtcs. */
6789 if (!intel_crtc->base.enabled)
6790 continue;
6791
6792 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6793 base.head) {
6794 if (encoder->new_crtc == intel_crtc)
6795 used = true;
6796 }
6797
6798 if (!used)
6799 *disable_pipes |= 1 << intel_crtc->pipe;
6800 }
6801
6802
6803 /* set_mode is also used to update properties on life display pipes. */
6804 intel_crtc = to_intel_crtc(crtc);
6805 if (crtc->enabled)
6806 *prepare_pipes |= 1 << intel_crtc->pipe;
6807
6808 /* We only support modeset on one single crtc, hence we need to do that
6809 * only for the passed in crtc iff we change anything else than just
6810 * disable crtcs.
6811 *
6812 * This is actually not true, to be fully compatible with the old crtc
6813 * helper we automatically disable _any_ output (i.e. doesn't need to be
6814 * connected to the crtc we're modesetting on) if it's disconnected.
6815 * Which is a rather nutty api (since changed the output configuration
6816 * without userspace's explicit request can lead to confusion), but
6817 * alas. Hence we currently need to modeset on all pipes we prepare. */
6818 if (*prepare_pipes)
6819 *modeset_pipes = *prepare_pipes;
6820
6821 /* ... and mask these out. */
6822 *modeset_pipes &= ~(*disable_pipes);
6823 *prepare_pipes &= ~(*disable_pipes);
6824 }
6825
6826 static bool intel_crtc_in_use(struct drm_crtc *crtc)
6827 {
6828 struct drm_encoder *encoder;
6829 struct drm_device *dev = crtc->dev;
6830
6831 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6832 if (encoder->crtc == crtc)
6833 return true;
6834
6835 return false;
6836 }
6837
6838 static void
6839 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6840 {
6841 struct intel_encoder *intel_encoder;
6842 struct intel_crtc *intel_crtc;
6843 struct drm_connector *connector;
6844
6845 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6846 base.head) {
6847 if (!intel_encoder->base.crtc)
6848 continue;
6849
6850 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6851
6852 if (prepare_pipes & (1 << intel_crtc->pipe))
6853 intel_encoder->connectors_active = false;
6854 }
6855
6856 intel_modeset_commit_output_state(dev);
6857
6858 /* Update computed state. */
6859 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6860 base.head) {
6861 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6862 }
6863
6864 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6865 if (!connector->encoder || !connector->encoder->crtc)
6866 continue;
6867
6868 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6869
6870 if (prepare_pipes & (1 << intel_crtc->pipe)) {
6871 struct drm_property *dpms_property =
6872 dev->mode_config.dpms_property;
6873
6874 connector->dpms = DRM_MODE_DPMS_ON;
6875 drm_connector_property_set_value(connector,
6876 dpms_property,
6877 DRM_MODE_DPMS_ON);
6878
6879 intel_encoder = to_intel_encoder(connector->encoder);
6880 intel_encoder->connectors_active = true;
6881 }
6882 }
6883
6884 }
6885
6886 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6887 list_for_each_entry((intel_crtc), \
6888 &(dev)->mode_config.crtc_list, \
6889 base.head) \
6890 if (mask & (1 <<(intel_crtc)->pipe)) \
6891
6892 void
6893 intel_modeset_check_state(struct drm_device *dev)
6894 {
6895 struct intel_crtc *crtc;
6896 struct intel_encoder *encoder;
6897 struct intel_connector *connector;
6898
6899 list_for_each_entry(connector, &dev->mode_config.connector_list,
6900 base.head) {
6901 /* This also checks the encoder/connector hw state with the
6902 * ->get_hw_state callbacks. */
6903 intel_connector_check_state(connector);
6904
6905 WARN(&connector->new_encoder->base != connector->base.encoder,
6906 "connector's staged encoder doesn't match current encoder\n");
6907 }
6908
6909 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6910 base.head) {
6911 bool enabled = false;
6912 bool active = false;
6913 enum pipe pipe, tracked_pipe;
6914
6915 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6916 encoder->base.base.id,
6917 drm_get_encoder_name(&encoder->base));
6918
6919 WARN(&encoder->new_crtc->base != encoder->base.crtc,
6920 "encoder's stage crtc doesn't match current crtc\n");
6921 WARN(encoder->connectors_active && !encoder->base.crtc,
6922 "encoder's active_connectors set, but no crtc\n");
6923
6924 list_for_each_entry(connector, &dev->mode_config.connector_list,
6925 base.head) {
6926 if (connector->base.encoder != &encoder->base)
6927 continue;
6928 enabled = true;
6929 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
6930 active = true;
6931 }
6932 WARN(!!encoder->base.crtc != enabled,
6933 "encoder's enabled state mismatch "
6934 "(expected %i, found %i)\n",
6935 !!encoder->base.crtc, enabled);
6936 WARN(active && !encoder->base.crtc,
6937 "active encoder with no crtc\n");
6938
6939 WARN(encoder->connectors_active != active,
6940 "encoder's computed active state doesn't match tracked active state "
6941 "(expected %i, found %i)\n", active, encoder->connectors_active);
6942
6943 active = encoder->get_hw_state(encoder, &pipe);
6944 WARN(active != encoder->connectors_active,
6945 "encoder's hw state doesn't match sw tracking "
6946 "(expected %i, found %i)\n",
6947 encoder->connectors_active, active);
6948
6949 if (!encoder->base.crtc)
6950 continue;
6951
6952 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
6953 WARN(active && pipe != tracked_pipe,
6954 "active encoder's pipe doesn't match"
6955 "(expected %i, found %i)\n",
6956 tracked_pipe, pipe);
6957
6958 }
6959
6960 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
6961 base.head) {
6962 bool enabled = false;
6963 bool active = false;
6964
6965 DRM_DEBUG_KMS("[CRTC:%d]\n",
6966 crtc->base.base.id);
6967
6968 WARN(crtc->active && !crtc->base.enabled,
6969 "active crtc, but not enabled in sw tracking\n");
6970
6971 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6972 base.head) {
6973 if (encoder->base.crtc != &crtc->base)
6974 continue;
6975 enabled = true;
6976 if (encoder->connectors_active)
6977 active = true;
6978 }
6979 WARN(active != crtc->active,
6980 "crtc's computed active state doesn't match tracked active state "
6981 "(expected %i, found %i)\n", active, crtc->active);
6982 WARN(enabled != crtc->base.enabled,
6983 "crtc's computed enabled state doesn't match tracked enabled state "
6984 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
6985
6986 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
6987 }
6988 }
6989
6990 bool intel_set_mode(struct drm_crtc *crtc,
6991 struct drm_display_mode *mode,
6992 int x, int y, struct drm_framebuffer *fb)
6993 {
6994 struct drm_device *dev = crtc->dev;
6995 drm_i915_private_t *dev_priv = dev->dev_private;
6996 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
6997 struct drm_encoder_helper_funcs *encoder_funcs;
6998 struct drm_encoder *encoder;
6999 struct intel_crtc *intel_crtc;
7000 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7001 bool ret = true;
7002
7003 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7004 &prepare_pipes, &disable_pipes);
7005
7006 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7007 modeset_pipes, prepare_pipes, disable_pipes);
7008
7009 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7010 intel_crtc_disable(&intel_crtc->base);
7011
7012 saved_hwmode = crtc->hwmode;
7013 saved_mode = crtc->mode;
7014
7015 /* Hack: Because we don't (yet) support global modeset on multiple
7016 * crtcs, we don't keep track of the new mode for more than one crtc.
7017 * Hence simply check whether any bit is set in modeset_pipes in all the
7018 * pieces of code that are not yet converted to deal with mutliple crtcs
7019 * changing their mode at the same time. */
7020 adjusted_mode = NULL;
7021 if (modeset_pipes) {
7022 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7023 if (IS_ERR(adjusted_mode)) {
7024 return false;
7025 }
7026 }
7027
7028 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7029 if (intel_crtc->base.enabled)
7030 dev_priv->display.crtc_disable(&intel_crtc->base);
7031 }
7032
7033 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7034 * to set it here already despite that we pass it down the callchain.
7035 */
7036 if (modeset_pipes)
7037 crtc->mode = *mode;
7038
7039 /* Only after disabling all output pipelines that will be changed can we
7040 * update the the output configuration. */
7041 intel_modeset_update_state(dev, prepare_pipes);
7042
7043 /* Set up the DPLL and any encoders state that needs to adjust or depend
7044 * on the DPLL.
7045 */
7046 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7047 ret = !intel_crtc_mode_set(&intel_crtc->base,
7048 mode, adjusted_mode,
7049 x, y, fb);
7050 if (!ret)
7051 goto done;
7052
7053 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7054
7055 if (encoder->crtc != &intel_crtc->base)
7056 continue;
7057
7058 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7059 encoder->base.id, drm_get_encoder_name(encoder),
7060 mode->base.id, mode->name);
7061 encoder_funcs = encoder->helper_private;
7062 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7063 }
7064 }
7065
7066 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7067 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7068 dev_priv->display.crtc_enable(&intel_crtc->base);
7069
7070 if (modeset_pipes) {
7071 /* Store real post-adjustment hardware mode. */
7072 crtc->hwmode = *adjusted_mode;
7073
7074 /* Calculate and store various constants which
7075 * are later needed by vblank and swap-completion
7076 * timestamping. They are derived from true hwmode.
7077 */
7078 drm_calc_timestamping_constants(crtc);
7079 }
7080
7081 /* FIXME: add subpixel order */
7082 done:
7083 drm_mode_destroy(dev, adjusted_mode);
7084 if (!ret && crtc->enabled) {
7085 crtc->hwmode = saved_hwmode;
7086 crtc->mode = saved_mode;
7087 } else {
7088 intel_modeset_check_state(dev);
7089 }
7090
7091 return ret;
7092 }
7093
7094 #undef for_each_intel_crtc_masked
7095
7096 static void intel_set_config_free(struct intel_set_config *config)
7097 {
7098 if (!config)
7099 return;
7100
7101 kfree(config->save_connector_encoders);
7102 kfree(config->save_encoder_crtcs);
7103 kfree(config);
7104 }
7105
7106 static int intel_set_config_save_state(struct drm_device *dev,
7107 struct intel_set_config *config)
7108 {
7109 struct drm_encoder *encoder;
7110 struct drm_connector *connector;
7111 int count;
7112
7113 config->save_encoder_crtcs =
7114 kcalloc(dev->mode_config.num_encoder,
7115 sizeof(struct drm_crtc *), GFP_KERNEL);
7116 if (!config->save_encoder_crtcs)
7117 return -ENOMEM;
7118
7119 config->save_connector_encoders =
7120 kcalloc(dev->mode_config.num_connector,
7121 sizeof(struct drm_encoder *), GFP_KERNEL);
7122 if (!config->save_connector_encoders)
7123 return -ENOMEM;
7124
7125 /* Copy data. Note that driver private data is not affected.
7126 * Should anything bad happen only the expected state is
7127 * restored, not the drivers personal bookkeeping.
7128 */
7129 count = 0;
7130 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7131 config->save_encoder_crtcs[count++] = encoder->crtc;
7132 }
7133
7134 count = 0;
7135 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7136 config->save_connector_encoders[count++] = connector->encoder;
7137 }
7138
7139 return 0;
7140 }
7141
7142 static void intel_set_config_restore_state(struct drm_device *dev,
7143 struct intel_set_config *config)
7144 {
7145 struct intel_encoder *encoder;
7146 struct intel_connector *connector;
7147 int count;
7148
7149 count = 0;
7150 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7151 encoder->new_crtc =
7152 to_intel_crtc(config->save_encoder_crtcs[count++]);
7153 }
7154
7155 count = 0;
7156 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7157 connector->new_encoder =
7158 to_intel_encoder(config->save_connector_encoders[count++]);
7159 }
7160 }
7161
7162 static void
7163 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7164 struct intel_set_config *config)
7165 {
7166
7167 /* We should be able to check here if the fb has the same properties
7168 * and then just flip_or_move it */
7169 if (set->crtc->fb != set->fb) {
7170 /* If we have no fb then treat it as a full mode set */
7171 if (set->crtc->fb == NULL) {
7172 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7173 config->mode_changed = true;
7174 } else if (set->fb == NULL) {
7175 config->mode_changed = true;
7176 } else if (set->fb->depth != set->crtc->fb->depth) {
7177 config->mode_changed = true;
7178 } else if (set->fb->bits_per_pixel !=
7179 set->crtc->fb->bits_per_pixel) {
7180 config->mode_changed = true;
7181 } else
7182 config->fb_changed = true;
7183 }
7184
7185 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7186 config->fb_changed = true;
7187
7188 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7189 DRM_DEBUG_KMS("modes are different, full mode set\n");
7190 drm_mode_debug_printmodeline(&set->crtc->mode);
7191 drm_mode_debug_printmodeline(set->mode);
7192 config->mode_changed = true;
7193 }
7194 }
7195
7196 static int
7197 intel_modeset_stage_output_state(struct drm_device *dev,
7198 struct drm_mode_set *set,
7199 struct intel_set_config *config)
7200 {
7201 struct drm_crtc *new_crtc;
7202 struct intel_connector *connector;
7203 struct intel_encoder *encoder;
7204 int count, ro;
7205
7206 /* The upper layers ensure that we either disabl a crtc or have a list
7207 * of connectors. For paranoia, double-check this. */
7208 WARN_ON(!set->fb && (set->num_connectors != 0));
7209 WARN_ON(set->fb && (set->num_connectors == 0));
7210
7211 count = 0;
7212 list_for_each_entry(connector, &dev->mode_config.connector_list,
7213 base.head) {
7214 /* Otherwise traverse passed in connector list and get encoders
7215 * for them. */
7216 for (ro = 0; ro < set->num_connectors; ro++) {
7217 if (set->connectors[ro] == &connector->base) {
7218 connector->new_encoder = connector->encoder;
7219 break;
7220 }
7221 }
7222
7223 /* If we disable the crtc, disable all its connectors. Also, if
7224 * the connector is on the changing crtc but not on the new
7225 * connector list, disable it. */
7226 if ((!set->fb || ro == set->num_connectors) &&
7227 connector->base.encoder &&
7228 connector->base.encoder->crtc == set->crtc) {
7229 connector->new_encoder = NULL;
7230
7231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7232 connector->base.base.id,
7233 drm_get_connector_name(&connector->base));
7234 }
7235
7236
7237 if (&connector->new_encoder->base != connector->base.encoder) {
7238 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7239 config->mode_changed = true;
7240 }
7241
7242 /* Disable all disconnected encoders. */
7243 if (connector->base.status == connector_status_disconnected)
7244 connector->new_encoder = NULL;
7245 }
7246 /* connector->new_encoder is now updated for all connectors. */
7247
7248 /* Update crtc of enabled connectors. */
7249 count = 0;
7250 list_for_each_entry(connector, &dev->mode_config.connector_list,
7251 base.head) {
7252 if (!connector->new_encoder)
7253 continue;
7254
7255 new_crtc = connector->new_encoder->base.crtc;
7256
7257 for (ro = 0; ro < set->num_connectors; ro++) {
7258 if (set->connectors[ro] == &connector->base)
7259 new_crtc = set->crtc;
7260 }
7261
7262 /* Make sure the new CRTC will work with the encoder */
7263 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7264 new_crtc)) {
7265 return -EINVAL;
7266 }
7267 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7268
7269 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7270 connector->base.base.id,
7271 drm_get_connector_name(&connector->base),
7272 new_crtc->base.id);
7273 }
7274
7275 /* Check for any encoders that needs to be disabled. */
7276 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7277 base.head) {
7278 list_for_each_entry(connector,
7279 &dev->mode_config.connector_list,
7280 base.head) {
7281 if (connector->new_encoder == encoder) {
7282 WARN_ON(!connector->new_encoder->new_crtc);
7283
7284 goto next_encoder;
7285 }
7286 }
7287 encoder->new_crtc = NULL;
7288 next_encoder:
7289 /* Only now check for crtc changes so we don't miss encoders
7290 * that will be disabled. */
7291 if (&encoder->new_crtc->base != encoder->base.crtc) {
7292 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7293 config->mode_changed = true;
7294 }
7295 }
7296 /* Now we've also updated encoder->new_crtc for all encoders. */
7297
7298 return 0;
7299 }
7300
7301 static int intel_crtc_set_config(struct drm_mode_set *set)
7302 {
7303 struct drm_device *dev;
7304 struct drm_mode_set save_set;
7305 struct intel_set_config *config;
7306 int ret;
7307
7308 BUG_ON(!set);
7309 BUG_ON(!set->crtc);
7310 BUG_ON(!set->crtc->helper_private);
7311
7312 if (!set->mode)
7313 set->fb = NULL;
7314
7315 /* The fb helper likes to play gross jokes with ->mode_set_config.
7316 * Unfortunately the crtc helper doesn't do much at all for this case,
7317 * so we have to cope with this madness until the fb helper is fixed up. */
7318 if (set->fb && set->num_connectors == 0)
7319 return 0;
7320
7321 if (set->fb) {
7322 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7323 set->crtc->base.id, set->fb->base.id,
7324 (int)set->num_connectors, set->x, set->y);
7325 } else {
7326 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7327 }
7328
7329 dev = set->crtc->dev;
7330
7331 ret = -ENOMEM;
7332 config = kzalloc(sizeof(*config), GFP_KERNEL);
7333 if (!config)
7334 goto out_config;
7335
7336 ret = intel_set_config_save_state(dev, config);
7337 if (ret)
7338 goto out_config;
7339
7340 save_set.crtc = set->crtc;
7341 save_set.mode = &set->crtc->mode;
7342 save_set.x = set->crtc->x;
7343 save_set.y = set->crtc->y;
7344 save_set.fb = set->crtc->fb;
7345
7346 /* Compute whether we need a full modeset, only an fb base update or no
7347 * change at all. In the future we might also check whether only the
7348 * mode changed, e.g. for LVDS where we only change the panel fitter in
7349 * such cases. */
7350 intel_set_config_compute_mode_changes(set, config);
7351
7352 ret = intel_modeset_stage_output_state(dev, set, config);
7353 if (ret)
7354 goto fail;
7355
7356 if (config->mode_changed) {
7357 if (set->mode) {
7358 DRM_DEBUG_KMS("attempting to set mode from"
7359 " userspace\n");
7360 drm_mode_debug_printmodeline(set->mode);
7361 }
7362
7363 if (!intel_set_mode(set->crtc, set->mode,
7364 set->x, set->y, set->fb)) {
7365 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7366 set->crtc->base.id);
7367 ret = -EINVAL;
7368 goto fail;
7369 }
7370 } else if (config->fb_changed) {
7371 ret = intel_pipe_set_base(set->crtc,
7372 set->x, set->y, set->fb);
7373 }
7374
7375 intel_set_config_free(config);
7376
7377 return 0;
7378
7379 fail:
7380 intel_set_config_restore_state(dev, config);
7381
7382 /* Try to restore the config */
7383 if (config->mode_changed &&
7384 !intel_set_mode(save_set.crtc, save_set.mode,
7385 save_set.x, save_set.y, save_set.fb))
7386 DRM_ERROR("failed to restore config after modeset failure\n");
7387
7388 out_config:
7389 intel_set_config_free(config);
7390 return ret;
7391 }
7392
7393 static const struct drm_crtc_funcs intel_crtc_funcs = {
7394 .cursor_set = intel_crtc_cursor_set,
7395 .cursor_move = intel_crtc_cursor_move,
7396 .gamma_set = intel_crtc_gamma_set,
7397 .set_config = intel_crtc_set_config,
7398 .destroy = intel_crtc_destroy,
7399 .page_flip = intel_crtc_page_flip,
7400 };
7401
7402 static void intel_pch_pll_init(struct drm_device *dev)
7403 {
7404 drm_i915_private_t *dev_priv = dev->dev_private;
7405 int i;
7406
7407 if (dev_priv->num_pch_pll == 0) {
7408 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7409 return;
7410 }
7411
7412 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7413 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7414 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7415 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7416 }
7417 }
7418
7419 static void intel_crtc_init(struct drm_device *dev, int pipe)
7420 {
7421 drm_i915_private_t *dev_priv = dev->dev_private;
7422 struct intel_crtc *intel_crtc;
7423 int i;
7424
7425 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7426 if (intel_crtc == NULL)
7427 return;
7428
7429 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7430
7431 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7432 for (i = 0; i < 256; i++) {
7433 intel_crtc->lut_r[i] = i;
7434 intel_crtc->lut_g[i] = i;
7435 intel_crtc->lut_b[i] = i;
7436 }
7437
7438 /* Swap pipes & planes for FBC on pre-965 */
7439 intel_crtc->pipe = pipe;
7440 intel_crtc->plane = pipe;
7441 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7442 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7443 intel_crtc->plane = !pipe;
7444 }
7445
7446 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7447 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7448 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7449 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7450
7451 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7452
7453 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7454 }
7455
7456 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7457 struct drm_file *file)
7458 {
7459 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7460 struct drm_mode_object *drmmode_obj;
7461 struct intel_crtc *crtc;
7462
7463 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7464 return -ENODEV;
7465
7466 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7467 DRM_MODE_OBJECT_CRTC);
7468
7469 if (!drmmode_obj) {
7470 DRM_ERROR("no such CRTC id\n");
7471 return -EINVAL;
7472 }
7473
7474 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7475 pipe_from_crtc_id->pipe = crtc->pipe;
7476
7477 return 0;
7478 }
7479
7480 static int intel_encoder_clones(struct intel_encoder *encoder)
7481 {
7482 struct drm_device *dev = encoder->base.dev;
7483 struct intel_encoder *source_encoder;
7484 int index_mask = 0;
7485 int entry = 0;
7486
7487 list_for_each_entry(source_encoder,
7488 &dev->mode_config.encoder_list, base.head) {
7489
7490 if (encoder == source_encoder)
7491 index_mask |= (1 << entry);
7492
7493 /* Intel hw has only one MUX where enocoders could be cloned. */
7494 if (encoder->cloneable && source_encoder->cloneable)
7495 index_mask |= (1 << entry);
7496
7497 entry++;
7498 }
7499
7500 return index_mask;
7501 }
7502
7503 static bool has_edp_a(struct drm_device *dev)
7504 {
7505 struct drm_i915_private *dev_priv = dev->dev_private;
7506
7507 if (!IS_MOBILE(dev))
7508 return false;
7509
7510 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7511 return false;
7512
7513 if (IS_GEN5(dev) &&
7514 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7515 return false;
7516
7517 return true;
7518 }
7519
7520 static void intel_setup_outputs(struct drm_device *dev)
7521 {
7522 struct drm_i915_private *dev_priv = dev->dev_private;
7523 struct intel_encoder *encoder;
7524 bool dpd_is_edp = false;
7525 bool has_lvds;
7526
7527 has_lvds = intel_lvds_init(dev);
7528 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7529 /* disable the panel fitter on everything but LVDS */
7530 I915_WRITE(PFIT_CONTROL, 0);
7531 }
7532
7533 if (HAS_PCH_SPLIT(dev)) {
7534 dpd_is_edp = intel_dpd_is_edp(dev);
7535
7536 if (has_edp_a(dev))
7537 intel_dp_init(dev, DP_A, PORT_A);
7538
7539 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7540 intel_dp_init(dev, PCH_DP_D, PORT_D);
7541 }
7542
7543 intel_crt_init(dev);
7544
7545 if (IS_HASWELL(dev)) {
7546 int found;
7547
7548 /* Haswell uses DDI functions to detect digital outputs */
7549 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7550 /* DDI A only supports eDP */
7551 if (found)
7552 intel_ddi_init(dev, PORT_A);
7553
7554 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7555 * register */
7556 found = I915_READ(SFUSE_STRAP);
7557
7558 if (found & SFUSE_STRAP_DDIB_DETECTED)
7559 intel_ddi_init(dev, PORT_B);
7560 if (found & SFUSE_STRAP_DDIC_DETECTED)
7561 intel_ddi_init(dev, PORT_C);
7562 if (found & SFUSE_STRAP_DDID_DETECTED)
7563 intel_ddi_init(dev, PORT_D);
7564 } else if (HAS_PCH_SPLIT(dev)) {
7565 int found;
7566
7567 if (I915_READ(HDMIB) & PORT_DETECTED) {
7568 /* PCH SDVOB multiplex with HDMIB */
7569 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7570 if (!found)
7571 intel_hdmi_init(dev, HDMIB, PORT_B);
7572 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7573 intel_dp_init(dev, PCH_DP_B, PORT_B);
7574 }
7575
7576 if (I915_READ(HDMIC) & PORT_DETECTED)
7577 intel_hdmi_init(dev, HDMIC, PORT_C);
7578
7579 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7580 intel_hdmi_init(dev, HDMID, PORT_D);
7581
7582 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7583 intel_dp_init(dev, PCH_DP_C, PORT_C);
7584
7585 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7586 intel_dp_init(dev, PCH_DP_D, PORT_D);
7587 } else if (IS_VALLEYVIEW(dev)) {
7588 int found;
7589
7590 if (I915_READ(SDVOB) & PORT_DETECTED) {
7591 /* SDVOB multiplex with HDMIB */
7592 found = intel_sdvo_init(dev, SDVOB, true);
7593 if (!found)
7594 intel_hdmi_init(dev, SDVOB, PORT_B);
7595 if (!found && (I915_READ(DP_B) & DP_DETECTED))
7596 intel_dp_init(dev, DP_B, PORT_B);
7597 }
7598
7599 if (I915_READ(SDVOC) & PORT_DETECTED)
7600 intel_hdmi_init(dev, SDVOC, PORT_C);
7601
7602 /* Shares lanes with HDMI on SDVOC */
7603 if (I915_READ(DP_C) & DP_DETECTED)
7604 intel_dp_init(dev, DP_C, PORT_C);
7605 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7606 bool found = false;
7607
7608 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7609 DRM_DEBUG_KMS("probing SDVOB\n");
7610 found = intel_sdvo_init(dev, SDVOB, true);
7611 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7612 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7613 intel_hdmi_init(dev, SDVOB, PORT_B);
7614 }
7615
7616 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7617 DRM_DEBUG_KMS("probing DP_B\n");
7618 intel_dp_init(dev, DP_B, PORT_B);
7619 }
7620 }
7621
7622 /* Before G4X SDVOC doesn't have its own detect register */
7623
7624 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7625 DRM_DEBUG_KMS("probing SDVOC\n");
7626 found = intel_sdvo_init(dev, SDVOC, false);
7627 }
7628
7629 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7630
7631 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7632 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7633 intel_hdmi_init(dev, SDVOC, PORT_C);
7634 }
7635 if (SUPPORTS_INTEGRATED_DP(dev)) {
7636 DRM_DEBUG_KMS("probing DP_C\n");
7637 intel_dp_init(dev, DP_C, PORT_C);
7638 }
7639 }
7640
7641 if (SUPPORTS_INTEGRATED_DP(dev) &&
7642 (I915_READ(DP_D) & DP_DETECTED)) {
7643 DRM_DEBUG_KMS("probing DP_D\n");
7644 intel_dp_init(dev, DP_D, PORT_D);
7645 }
7646 } else if (IS_GEN2(dev))
7647 intel_dvo_init(dev);
7648
7649 if (SUPPORTS_TV(dev))
7650 intel_tv_init(dev);
7651
7652 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7653 encoder->base.possible_crtcs = encoder->crtc_mask;
7654 encoder->base.possible_clones =
7655 intel_encoder_clones(encoder);
7656 }
7657
7658 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7659 ironlake_init_pch_refclk(dev);
7660 }
7661
7662 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7663 {
7664 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7665
7666 drm_framebuffer_cleanup(fb);
7667 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7668
7669 kfree(intel_fb);
7670 }
7671
7672 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7673 struct drm_file *file,
7674 unsigned int *handle)
7675 {
7676 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7677 struct drm_i915_gem_object *obj = intel_fb->obj;
7678
7679 return drm_gem_handle_create(file, &obj->base, handle);
7680 }
7681
7682 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7683 .destroy = intel_user_framebuffer_destroy,
7684 .create_handle = intel_user_framebuffer_create_handle,
7685 };
7686
7687 int intel_framebuffer_init(struct drm_device *dev,
7688 struct intel_framebuffer *intel_fb,
7689 struct drm_mode_fb_cmd2 *mode_cmd,
7690 struct drm_i915_gem_object *obj)
7691 {
7692 int ret;
7693
7694 if (obj->tiling_mode == I915_TILING_Y)
7695 return -EINVAL;
7696
7697 if (mode_cmd->pitches[0] & 63)
7698 return -EINVAL;
7699
7700 switch (mode_cmd->pixel_format) {
7701 case DRM_FORMAT_RGB332:
7702 case DRM_FORMAT_RGB565:
7703 case DRM_FORMAT_XRGB8888:
7704 case DRM_FORMAT_XBGR8888:
7705 case DRM_FORMAT_ARGB8888:
7706 case DRM_FORMAT_XRGB2101010:
7707 case DRM_FORMAT_ARGB2101010:
7708 /* RGB formats are common across chipsets */
7709 break;
7710 case DRM_FORMAT_YUYV:
7711 case DRM_FORMAT_UYVY:
7712 case DRM_FORMAT_YVYU:
7713 case DRM_FORMAT_VYUY:
7714 break;
7715 default:
7716 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7717 mode_cmd->pixel_format);
7718 return -EINVAL;
7719 }
7720
7721 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7722 if (ret) {
7723 DRM_ERROR("framebuffer init failed %d\n", ret);
7724 return ret;
7725 }
7726
7727 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7728 intel_fb->obj = obj;
7729 return 0;
7730 }
7731
7732 static struct drm_framebuffer *
7733 intel_user_framebuffer_create(struct drm_device *dev,
7734 struct drm_file *filp,
7735 struct drm_mode_fb_cmd2 *mode_cmd)
7736 {
7737 struct drm_i915_gem_object *obj;
7738
7739 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7740 mode_cmd->handles[0]));
7741 if (&obj->base == NULL)
7742 return ERR_PTR(-ENOENT);
7743
7744 return intel_framebuffer_create(dev, mode_cmd, obj);
7745 }
7746
7747 static const struct drm_mode_config_funcs intel_mode_funcs = {
7748 .fb_create = intel_user_framebuffer_create,
7749 .output_poll_changed = intel_fb_output_poll_changed,
7750 };
7751
7752 /* Set up chip specific display functions */
7753 static void intel_init_display(struct drm_device *dev)
7754 {
7755 struct drm_i915_private *dev_priv = dev->dev_private;
7756
7757 /* We always want a DPMS function */
7758 if (HAS_PCH_SPLIT(dev)) {
7759 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7760 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7761 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7762 dev_priv->display.off = ironlake_crtc_off;
7763 dev_priv->display.update_plane = ironlake_update_plane;
7764 } else {
7765 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7766 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7767 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7768 dev_priv->display.off = i9xx_crtc_off;
7769 dev_priv->display.update_plane = i9xx_update_plane;
7770 }
7771
7772 /* Returns the core display clock speed */
7773 if (IS_VALLEYVIEW(dev))
7774 dev_priv->display.get_display_clock_speed =
7775 valleyview_get_display_clock_speed;
7776 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7777 dev_priv->display.get_display_clock_speed =
7778 i945_get_display_clock_speed;
7779 else if (IS_I915G(dev))
7780 dev_priv->display.get_display_clock_speed =
7781 i915_get_display_clock_speed;
7782 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7783 dev_priv->display.get_display_clock_speed =
7784 i9xx_misc_get_display_clock_speed;
7785 else if (IS_I915GM(dev))
7786 dev_priv->display.get_display_clock_speed =
7787 i915gm_get_display_clock_speed;
7788 else if (IS_I865G(dev))
7789 dev_priv->display.get_display_clock_speed =
7790 i865_get_display_clock_speed;
7791 else if (IS_I85X(dev))
7792 dev_priv->display.get_display_clock_speed =
7793 i855_get_display_clock_speed;
7794 else /* 852, 830 */
7795 dev_priv->display.get_display_clock_speed =
7796 i830_get_display_clock_speed;
7797
7798 if (HAS_PCH_SPLIT(dev)) {
7799 if (IS_GEN5(dev)) {
7800 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7801 dev_priv->display.write_eld = ironlake_write_eld;
7802 } else if (IS_GEN6(dev)) {
7803 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7804 dev_priv->display.write_eld = ironlake_write_eld;
7805 } else if (IS_IVYBRIDGE(dev)) {
7806 /* FIXME: detect B0+ stepping and use auto training */
7807 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7808 dev_priv->display.write_eld = ironlake_write_eld;
7809 } else if (IS_HASWELL(dev)) {
7810 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7811 dev_priv->display.write_eld = haswell_write_eld;
7812 } else
7813 dev_priv->display.update_wm = NULL;
7814 } else if (IS_G4X(dev)) {
7815 dev_priv->display.write_eld = g4x_write_eld;
7816 }
7817
7818 /* Default just returns -ENODEV to indicate unsupported */
7819 dev_priv->display.queue_flip = intel_default_queue_flip;
7820
7821 switch (INTEL_INFO(dev)->gen) {
7822 case 2:
7823 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7824 break;
7825
7826 case 3:
7827 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7828 break;
7829
7830 case 4:
7831 case 5:
7832 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7833 break;
7834
7835 case 6:
7836 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7837 break;
7838 case 7:
7839 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7840 break;
7841 }
7842 }
7843
7844 /*
7845 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7846 * resume, or other times. This quirk makes sure that's the case for
7847 * affected systems.
7848 */
7849 static void quirk_pipea_force(struct drm_device *dev)
7850 {
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852
7853 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7854 DRM_INFO("applying pipe a force quirk\n");
7855 }
7856
7857 /*
7858 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7859 */
7860 static void quirk_ssc_force_disable(struct drm_device *dev)
7861 {
7862 struct drm_i915_private *dev_priv = dev->dev_private;
7863 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7864 DRM_INFO("applying lvds SSC disable quirk\n");
7865 }
7866
7867 /*
7868 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7869 * brightness value
7870 */
7871 static void quirk_invert_brightness(struct drm_device *dev)
7872 {
7873 struct drm_i915_private *dev_priv = dev->dev_private;
7874 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7875 DRM_INFO("applying inverted panel brightness quirk\n");
7876 }
7877
7878 struct intel_quirk {
7879 int device;
7880 int subsystem_vendor;
7881 int subsystem_device;
7882 void (*hook)(struct drm_device *dev);
7883 };
7884
7885 static struct intel_quirk intel_quirks[] = {
7886 /* HP Mini needs pipe A force quirk (LP: #322104) */
7887 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7888
7889 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7890 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7891
7892 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7893 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7894
7895 /* 855 & before need to leave pipe A & dpll A up */
7896 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7897 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7898 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7899
7900 /* Lenovo U160 cannot use SSC on LVDS */
7901 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7902
7903 /* Sony Vaio Y cannot use SSC on LVDS */
7904 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7905
7906 /* Acer Aspire 5734Z must invert backlight brightness */
7907 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7908 };
7909
7910 static void intel_init_quirks(struct drm_device *dev)
7911 {
7912 struct pci_dev *d = dev->pdev;
7913 int i;
7914
7915 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7916 struct intel_quirk *q = &intel_quirks[i];
7917
7918 if (d->device == q->device &&
7919 (d->subsystem_vendor == q->subsystem_vendor ||
7920 q->subsystem_vendor == PCI_ANY_ID) &&
7921 (d->subsystem_device == q->subsystem_device ||
7922 q->subsystem_device == PCI_ANY_ID))
7923 q->hook(dev);
7924 }
7925 }
7926
7927 /* Disable the VGA plane that we never use */
7928 static void i915_disable_vga(struct drm_device *dev)
7929 {
7930 struct drm_i915_private *dev_priv = dev->dev_private;
7931 u8 sr1;
7932 u32 vga_reg;
7933
7934 if (HAS_PCH_SPLIT(dev))
7935 vga_reg = CPU_VGACNTRL;
7936 else
7937 vga_reg = VGACNTRL;
7938
7939 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7940 outb(SR01, VGA_SR_INDEX);
7941 sr1 = inb(VGA_SR_DATA);
7942 outb(sr1 | 1<<5, VGA_SR_DATA);
7943 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7944 udelay(300);
7945
7946 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7947 POSTING_READ(vga_reg);
7948 }
7949
7950 void intel_modeset_init_hw(struct drm_device *dev)
7951 {
7952 /* We attempt to init the necessary power wells early in the initialization
7953 * time, so the subsystems that expect power to be enabled can work.
7954 */
7955 intel_init_power_wells(dev);
7956
7957 intel_prepare_ddi(dev);
7958
7959 intel_init_clock_gating(dev);
7960
7961 mutex_lock(&dev->struct_mutex);
7962 intel_enable_gt_powersave(dev);
7963 mutex_unlock(&dev->struct_mutex);
7964 }
7965
7966 void intel_modeset_init(struct drm_device *dev)
7967 {
7968 struct drm_i915_private *dev_priv = dev->dev_private;
7969 int i, ret;
7970
7971 drm_mode_config_init(dev);
7972
7973 dev->mode_config.min_width = 0;
7974 dev->mode_config.min_height = 0;
7975
7976 dev->mode_config.preferred_depth = 24;
7977 dev->mode_config.prefer_shadow = 1;
7978
7979 dev->mode_config.funcs = &intel_mode_funcs;
7980
7981 intel_init_quirks(dev);
7982
7983 intel_init_pm(dev);
7984
7985 intel_init_display(dev);
7986
7987 if (IS_GEN2(dev)) {
7988 dev->mode_config.max_width = 2048;
7989 dev->mode_config.max_height = 2048;
7990 } else if (IS_GEN3(dev)) {
7991 dev->mode_config.max_width = 4096;
7992 dev->mode_config.max_height = 4096;
7993 } else {
7994 dev->mode_config.max_width = 8192;
7995 dev->mode_config.max_height = 8192;
7996 }
7997 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7998
7999 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8000 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8001
8002 for (i = 0; i < dev_priv->num_pipe; i++) {
8003 intel_crtc_init(dev, i);
8004 ret = intel_plane_init(dev, i);
8005 if (ret)
8006 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8007 }
8008
8009 intel_pch_pll_init(dev);
8010
8011 /* Just disable it once at startup */
8012 i915_disable_vga(dev);
8013 intel_setup_outputs(dev);
8014 }
8015
8016 static void
8017 intel_connector_break_all_links(struct intel_connector *connector)
8018 {
8019 connector->base.dpms = DRM_MODE_DPMS_OFF;
8020 connector->base.encoder = NULL;
8021 connector->encoder->connectors_active = false;
8022 connector->encoder->base.crtc = NULL;
8023 }
8024
8025 static void intel_enable_pipe_a(struct drm_device *dev)
8026 {
8027 struct intel_connector *connector;
8028 struct drm_connector *crt = NULL;
8029 struct intel_load_detect_pipe load_detect_temp;
8030
8031 /* We can't just switch on the pipe A, we need to set things up with a
8032 * proper mode and output configuration. As a gross hack, enable pipe A
8033 * by enabling the load detect pipe once. */
8034 list_for_each_entry(connector,
8035 &dev->mode_config.connector_list,
8036 base.head) {
8037 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8038 crt = &connector->base;
8039 break;
8040 }
8041 }
8042
8043 if (!crt)
8044 return;
8045
8046 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8047 intel_release_load_detect_pipe(crt, &load_detect_temp);
8048
8049
8050 }
8051
8052 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8053 {
8054 struct drm_device *dev = crtc->base.dev;
8055 struct drm_i915_private *dev_priv = dev->dev_private;
8056 u32 reg, val;
8057
8058 /* Clear any frame start delays used for debugging left by the BIOS */
8059 reg = PIPECONF(crtc->pipe);
8060 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8061
8062 /* We need to sanitize the plane -> pipe mapping first because this will
8063 * disable the crtc (and hence change the state) if it is wrong. */
8064 if (!HAS_PCH_SPLIT(dev)) {
8065 struct intel_connector *connector;
8066 bool plane;
8067
8068 reg = DSPCNTR(crtc->plane);
8069 val = I915_READ(reg);
8070
8071 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8072 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8073 goto ok;
8074
8075 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8076 crtc->base.base.id);
8077
8078 /* Pipe has the wrong plane attached and the plane is active.
8079 * Temporarily change the plane mapping and disable everything
8080 * ... */
8081 plane = crtc->plane;
8082 crtc->plane = !plane;
8083 dev_priv->display.crtc_disable(&crtc->base);
8084 crtc->plane = plane;
8085
8086 /* ... and break all links. */
8087 list_for_each_entry(connector, &dev->mode_config.connector_list,
8088 base.head) {
8089 if (connector->encoder->base.crtc != &crtc->base)
8090 continue;
8091
8092 intel_connector_break_all_links(connector);
8093 }
8094
8095 WARN_ON(crtc->active);
8096 crtc->base.enabled = false;
8097 }
8098 ok:
8099
8100 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8101 crtc->pipe == PIPE_A && !crtc->active) {
8102 /* BIOS forgot to enable pipe A, this mostly happens after
8103 * resume. Force-enable the pipe to fix this, the update_dpms
8104 * call below we restore the pipe to the right state, but leave
8105 * the required bits on. */
8106 intel_enable_pipe_a(dev);
8107 }
8108
8109 /* Adjust the state of the output pipe according to whether we
8110 * have active connectors/encoders. */
8111 intel_crtc_update_dpms(&crtc->base);
8112
8113 if (crtc->active != crtc->base.enabled) {
8114 struct intel_encoder *encoder;
8115
8116 /* This can happen either due to bugs in the get_hw_state
8117 * functions or because the pipe is force-enabled due to the
8118 * pipe A quirk. */
8119 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8120 crtc->base.base.id,
8121 crtc->base.enabled ? "enabled" : "disabled",
8122 crtc->active ? "enabled" : "disabled");
8123
8124 crtc->base.enabled = crtc->active;
8125
8126 /* Because we only establish the connector -> encoder ->
8127 * crtc links if something is active, this means the
8128 * crtc is now deactivated. Break the links. connector
8129 * -> encoder links are only establish when things are
8130 * actually up, hence no need to break them. */
8131 WARN_ON(crtc->active);
8132
8133 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8134 WARN_ON(encoder->connectors_active);
8135 encoder->base.crtc = NULL;
8136 }
8137 }
8138 }
8139
8140 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8141 {
8142 struct intel_connector *connector;
8143 struct drm_device *dev = encoder->base.dev;
8144
8145 /* We need to check both for a crtc link (meaning that the
8146 * encoder is active and trying to read from a pipe) and the
8147 * pipe itself being active. */
8148 bool has_active_crtc = encoder->base.crtc &&
8149 to_intel_crtc(encoder->base.crtc)->active;
8150
8151 if (encoder->connectors_active && !has_active_crtc) {
8152 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8153 encoder->base.base.id,
8154 drm_get_encoder_name(&encoder->base));
8155
8156 /* Connector is active, but has no active pipe. This is
8157 * fallout from our resume register restoring. Disable
8158 * the encoder manually again. */
8159 if (encoder->base.crtc) {
8160 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8161 encoder->base.base.id,
8162 drm_get_encoder_name(&encoder->base));
8163 encoder->disable(encoder);
8164 }
8165
8166 /* Inconsistent output/port/pipe state happens presumably due to
8167 * a bug in one of the get_hw_state functions. Or someplace else
8168 * in our code, like the register restore mess on resume. Clamp
8169 * things to off as a safer default. */
8170 list_for_each_entry(connector,
8171 &dev->mode_config.connector_list,
8172 base.head) {
8173 if (connector->encoder != encoder)
8174 continue;
8175
8176 intel_connector_break_all_links(connector);
8177 }
8178 }
8179 /* Enabled encoders without active connectors will be fixed in
8180 * the crtc fixup. */
8181 }
8182
8183 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8184 * and i915 state tracking structures. */
8185 void intel_modeset_setup_hw_state(struct drm_device *dev)
8186 {
8187 struct drm_i915_private *dev_priv = dev->dev_private;
8188 enum pipe pipe;
8189 u32 tmp;
8190 struct intel_crtc *crtc;
8191 struct intel_encoder *encoder;
8192 struct intel_connector *connector;
8193
8194 for_each_pipe(pipe) {
8195 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8196
8197 tmp = I915_READ(PIPECONF(pipe));
8198 if (tmp & PIPECONF_ENABLE)
8199 crtc->active = true;
8200 else
8201 crtc->active = false;
8202
8203 crtc->base.enabled = crtc->active;
8204
8205 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8206 crtc->base.base.id,
8207 crtc->active ? "enabled" : "disabled");
8208 }
8209
8210 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8211 base.head) {
8212 pipe = 0;
8213
8214 if (encoder->get_hw_state(encoder, &pipe)) {
8215 encoder->base.crtc =
8216 dev_priv->pipe_to_crtc_mapping[pipe];
8217 } else {
8218 encoder->base.crtc = NULL;
8219 }
8220
8221 encoder->connectors_active = false;
8222 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8223 encoder->base.base.id,
8224 drm_get_encoder_name(&encoder->base),
8225 encoder->base.crtc ? "enabled" : "disabled",
8226 pipe);
8227 }
8228
8229 list_for_each_entry(connector, &dev->mode_config.connector_list,
8230 base.head) {
8231 if (connector->get_hw_state(connector)) {
8232 connector->base.dpms = DRM_MODE_DPMS_ON;
8233 connector->encoder->connectors_active = true;
8234 connector->base.encoder = &connector->encoder->base;
8235 } else {
8236 connector->base.dpms = DRM_MODE_DPMS_OFF;
8237 connector->base.encoder = NULL;
8238 }
8239 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8240 connector->base.base.id,
8241 drm_get_connector_name(&connector->base),
8242 connector->base.encoder ? "enabled" : "disabled");
8243 }
8244
8245 /* HW state is read out, now we need to sanitize this mess. */
8246 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8247 base.head) {
8248 intel_sanitize_encoder(encoder);
8249 }
8250
8251 for_each_pipe(pipe) {
8252 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8253 intel_sanitize_crtc(crtc);
8254 }
8255
8256 intel_modeset_update_staged_output_state(dev);
8257
8258 intel_modeset_check_state(dev);
8259 }
8260
8261 void intel_modeset_gem_init(struct drm_device *dev)
8262 {
8263 intel_modeset_init_hw(dev);
8264
8265 intel_setup_overlay(dev);
8266
8267 intel_modeset_setup_hw_state(dev);
8268 }
8269
8270 void intel_modeset_cleanup(struct drm_device *dev)
8271 {
8272 struct drm_i915_private *dev_priv = dev->dev_private;
8273 struct drm_crtc *crtc;
8274 struct intel_crtc *intel_crtc;
8275
8276 drm_kms_helper_poll_fini(dev);
8277 mutex_lock(&dev->struct_mutex);
8278
8279 intel_unregister_dsm_handler();
8280
8281
8282 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8283 /* Skip inactive CRTCs */
8284 if (!crtc->fb)
8285 continue;
8286
8287 intel_crtc = to_intel_crtc(crtc);
8288 intel_increase_pllclock(crtc);
8289 }
8290
8291 intel_disable_fbc(dev);
8292
8293 intel_disable_gt_powersave(dev);
8294
8295 ironlake_teardown_rc6(dev);
8296
8297 if (IS_VALLEYVIEW(dev))
8298 vlv_init_dpio(dev);
8299
8300 mutex_unlock(&dev->struct_mutex);
8301
8302 /* Disable the irq before mode object teardown, for the irq might
8303 * enqueue unpin/hotplug work. */
8304 drm_irq_uninstall(dev);
8305 cancel_work_sync(&dev_priv->hotplug_work);
8306 cancel_work_sync(&dev_priv->rps.work);
8307
8308 /* flush any delayed tasks or pending work */
8309 flush_scheduled_work();
8310
8311 drm_mode_config_cleanup(dev);
8312 }
8313
8314 /*
8315 * Return which encoder is currently attached for connector.
8316 */
8317 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8318 {
8319 return &intel_attached_encoder(connector)->base;
8320 }
8321
8322 void intel_connector_attach_encoder(struct intel_connector *connector,
8323 struct intel_encoder *encoder)
8324 {
8325 connector->encoder = encoder;
8326 drm_mode_connector_attach_encoder(&connector->base,
8327 &encoder->base);
8328 }
8329
8330 /*
8331 * set vga decode state - true == enable VGA decode
8332 */
8333 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8334 {
8335 struct drm_i915_private *dev_priv = dev->dev_private;
8336 u16 gmch_ctrl;
8337
8338 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8339 if (state)
8340 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8341 else
8342 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8343 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8344 return 0;
8345 }
8346
8347 #ifdef CONFIG_DEBUG_FS
8348 #include <linux/seq_file.h>
8349
8350 struct intel_display_error_state {
8351 struct intel_cursor_error_state {
8352 u32 control;
8353 u32 position;
8354 u32 base;
8355 u32 size;
8356 } cursor[I915_MAX_PIPES];
8357
8358 struct intel_pipe_error_state {
8359 u32 conf;
8360 u32 source;
8361
8362 u32 htotal;
8363 u32 hblank;
8364 u32 hsync;
8365 u32 vtotal;
8366 u32 vblank;
8367 u32 vsync;
8368 } pipe[I915_MAX_PIPES];
8369
8370 struct intel_plane_error_state {
8371 u32 control;
8372 u32 stride;
8373 u32 size;
8374 u32 pos;
8375 u32 addr;
8376 u32 surface;
8377 u32 tile_offset;
8378 } plane[I915_MAX_PIPES];
8379 };
8380
8381 struct intel_display_error_state *
8382 intel_display_capture_error_state(struct drm_device *dev)
8383 {
8384 drm_i915_private_t *dev_priv = dev->dev_private;
8385 struct intel_display_error_state *error;
8386 int i;
8387
8388 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8389 if (error == NULL)
8390 return NULL;
8391
8392 for_each_pipe(i) {
8393 error->cursor[i].control = I915_READ(CURCNTR(i));
8394 error->cursor[i].position = I915_READ(CURPOS(i));
8395 error->cursor[i].base = I915_READ(CURBASE(i));
8396
8397 error->plane[i].control = I915_READ(DSPCNTR(i));
8398 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8399 error->plane[i].size = I915_READ(DSPSIZE(i));
8400 error->plane[i].pos = I915_READ(DSPPOS(i));
8401 error->plane[i].addr = I915_READ(DSPADDR(i));
8402 if (INTEL_INFO(dev)->gen >= 4) {
8403 error->plane[i].surface = I915_READ(DSPSURF(i));
8404 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8405 }
8406
8407 error->pipe[i].conf = I915_READ(PIPECONF(i));
8408 error->pipe[i].source = I915_READ(PIPESRC(i));
8409 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8410 error->pipe[i].hblank = I915_READ(HBLANK(i));
8411 error->pipe[i].hsync = I915_READ(HSYNC(i));
8412 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8413 error->pipe[i].vblank = I915_READ(VBLANK(i));
8414 error->pipe[i].vsync = I915_READ(VSYNC(i));
8415 }
8416
8417 return error;
8418 }
8419
8420 void
8421 intel_display_print_error_state(struct seq_file *m,
8422 struct drm_device *dev,
8423 struct intel_display_error_state *error)
8424 {
8425 drm_i915_private_t *dev_priv = dev->dev_private;
8426 int i;
8427
8428 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8429 for_each_pipe(i) {
8430 seq_printf(m, "Pipe [%d]:\n", i);
8431 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8432 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8433 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8434 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8435 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8436 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8437 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8438 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8439
8440 seq_printf(m, "Plane [%d]:\n", i);
8441 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8442 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8443 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8444 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8445 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8446 if (INTEL_INFO(dev)->gen >= 4) {
8447 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8448 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8449 }
8450
8451 seq_printf(m, "Cursor [%d]:\n", i);
8452 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8453 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8454 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8455 }
8456 }
8457 #endif
Linux kernel - Deliverables
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