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drm/i915: Check locking in i915_gem_request_unreference
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
77
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
82
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
101
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103 {
104 if (!connector->mst_port)
105 return connector->encoder;
106 else
107 return &connector->mst_port->mst_encoders[pipe]->base;
108 }
109
110 typedef struct {
111 int min, max;
112 } intel_range_t;
113
114 typedef struct {
115 int dot_limit;
116 int p2_slow, p2_fast;
117 } intel_p2_t;
118
119 typedef struct intel_limit intel_limit_t;
120 struct intel_limit {
121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
122 intel_p2_t p2;
123 };
124
125 int
126 intel_pch_rawclk(struct drm_device *dev)
127 {
128 struct drm_i915_private *dev_priv = dev->dev_private;
129
130 WARN_ON(!HAS_PCH_SPLIT(dev));
131
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133 }
134
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
137 {
138 if (IS_GEN5(dev)) {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141 } else
142 return 27;
143 }
144
145 static const intel_limit_t intel_limits_i8xx_dac = {
146 .dot = { .min = 25000, .max = 350000 },
147 .vco = { .min = 908000, .max = 1512000 },
148 .n = { .min = 2, .max = 16 },
149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
156 };
157
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
182 };
183
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
208 };
209
210
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
221 .p2_slow = 10,
222 .p2_fast = 10
223 },
224 };
225
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
250 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
264 },
265 };
266
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
280 };
281
282 static const intel_limit_t intel_limits_pineview_lvds = {
283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
293 };
294
295 /* Ironlake / Sandybridge
296 *
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
299 */
300 static const intel_limit_t intel_limits_ironlake_dac = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
311 };
312
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
337 };
338
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
361 .p1 = { .min = 2, .max = 6 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
364 };
365
366 static const intel_limit_t intel_limits_vlv = {
367 /*
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
372 */
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374 .vco = { .min = 4000000, .max = 6000000 },
375 .n = { .min = 1, .max = 7 },
376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
378 .p1 = { .min = 2, .max = 3 },
379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
380 };
381
382 static const intel_limit_t intel_limits_chv = {
383 /*
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
388 */
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396 };
397
398 static void vlv_clock(int refclk, intel_clock_t *clock)
399 {
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
402 if (WARN_ON(clock->n == 0 || clock->p == 0))
403 return;
404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
406 }
407
408 /**
409 * Returns whether any output on the specified pipe is of the specified type
410 */
411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
412 {
413 struct drm_device *dev = crtc->base.dev;
414 struct intel_encoder *encoder;
415
416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
417 if (encoder->type == type)
418 return true;
419
420 return false;
421 }
422
423 /**
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427 * encoder->crtc.
428 */
429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
430 {
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
433
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
436 return true;
437
438 return false;
439 }
440
441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
442 int refclk)
443 {
444 struct drm_device *dev = crtc->base.dev;
445 const intel_limit_t *limit;
446
447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
448 if (intel_is_dual_link_lvds(dev)) {
449 if (refclk == 100000)
450 limit = &intel_limits_ironlake_dual_lvds_100m;
451 else
452 limit = &intel_limits_ironlake_dual_lvds;
453 } else {
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_single_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_single_lvds;
458 }
459 } else
460 limit = &intel_limits_ironlake_dac;
461
462 return limit;
463 }
464
465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
466 {
467 struct drm_device *dev = crtc->base.dev;
468 const intel_limit_t *limit;
469
470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
471 if (intel_is_dual_link_lvds(dev))
472 limit = &intel_limits_g4x_dual_channel_lvds;
473 else
474 limit = &intel_limits_g4x_single_channel_lvds;
475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
477 limit = &intel_limits_g4x_hdmi;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
479 limit = &intel_limits_g4x_sdvo;
480 } else /* The option is for other outputs */
481 limit = &intel_limits_i9xx_sdvo;
482
483 return limit;
484 }
485
486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
487 {
488 struct drm_device *dev = crtc->base.dev;
489 const intel_limit_t *limit;
490
491 if (HAS_PCH_SPLIT(dev))
492 limit = intel_ironlake_limit(crtc, refclk);
493 else if (IS_G4X(dev)) {
494 limit = intel_g4x_limit(crtc);
495 } else if (IS_PINEVIEW(dev)) {
496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
497 limit = &intel_limits_pineview_lvds;
498 else
499 limit = &intel_limits_pineview_sdvo;
500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
502 } else if (IS_VALLEYVIEW(dev)) {
503 limit = &intel_limits_vlv;
504 } else if (!IS_GEN2(dev)) {
505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
506 limit = &intel_limits_i9xx_lvds;
507 else
508 limit = &intel_limits_i9xx_sdvo;
509 } else {
510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
511 limit = &intel_limits_i8xx_lvds;
512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
513 limit = &intel_limits_i8xx_dvo;
514 else
515 limit = &intel_limits_i8xx_dac;
516 }
517 return limit;
518 }
519
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532 {
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534 }
535
536 static void i9xx_clock(int refclk, intel_clock_t *clock)
537 {
538 clock->m = i9xx_dpll_compute_m(clock);
539 clock->p = clock->p1 * clock->p2;
540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
541 return;
542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
544 }
545
546 static void chv_clock(int refclk, intel_clock_t *clock)
547 {
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
553 clock->n << 22);
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555 }
556
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
558 /**
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
561 */
562
563 static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
566 {
567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
574 INTELPllInvalid("m1 out of range\n");
575
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
579
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
585 }
586
587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
591 */
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
593 INTELPllInvalid("dot out of range\n");
594
595 return true;
596 }
597
598 static bool
599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
602 {
603 struct drm_device *dev = crtc->base.dev;
604 intel_clock_t clock;
605 int err = target;
606
607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
608 /*
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
612 */
613 if (intel_is_dual_link_lvds(dev))
614 clock.p2 = limit->p2.p2_fast;
615 else
616 clock.p2 = limit->p2.p2_slow;
617 } else {
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
620 else
621 clock.p2 = limit->p2.p2_fast;
622 }
623
624 memset(best_clock, 0, sizeof(*best_clock));
625
626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
627 clock.m1++) {
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
630 if (clock.m2 >= clock.m1)
631 break;
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
636 int this_err;
637
638 i9xx_clock(refclk, &clock);
639 if (!intel_PLL_is_valid(dev, limit,
640 &clock))
641 continue;
642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657 }
658
659 static bool
660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
663 {
664 struct drm_device *dev = crtc->base.dev;
665 intel_clock_t clock;
666 int err = target;
667
668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
669 /*
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
673 */
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
676 else
677 clock.p2 = limit->p2.p2_slow;
678 } else {
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
681 else
682 clock.p2 = limit->p2.p2_fast;
683 }
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pineview_clock(refclk, &clock);
698 if (!intel_PLL_is_valid(dev, limit,
699 &clock))
700 continue;
701 if (match_clock &&
702 clock.p != match_clock->p)
703 continue;
704
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
707 *best_clock = clock;
708 err = this_err;
709 }
710 }
711 }
712 }
713 }
714
715 return (err != target);
716 }
717
718 static bool
719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722 {
723 struct drm_device *dev = crtc->base.dev;
724 intel_clock_t clock;
725 int max_n;
726 bool found;
727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
729 found = false;
730
731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
732 if (intel_is_dual_link_lvds(dev))
733 clock.p2 = limit->p2.p2_fast;
734 else
735 clock.p2 = limit->p2.p2_slow;
736 } else {
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
739 else
740 clock.p2 = limit->p2.p2_fast;
741 }
742
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
754 int this_err;
755
756 i9xx_clock(refclk, &clock);
757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
759 continue;
760
761 this_err = abs(clock.dot - target);
762 if (this_err < err_most) {
763 *best_clock = clock;
764 err_most = this_err;
765 max_n = clock.n;
766 found = true;
767 }
768 }
769 }
770 }
771 }
772 return found;
773 }
774
775 static bool
776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779 {
780 struct drm_device *dev = crtc->base.dev;
781 intel_clock_t clock;
782 unsigned int bestppm = 1000000;
783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
785 bool found = false;
786
787 target *= 5; /* fast clock */
788
789 memset(best_clock, 0, sizeof(*best_clock));
790
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
796 clock.p = clock.p1 * clock.p2;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
799 unsigned int ppm, diff;
800
801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
802 refclk * clock.m1);
803
804 vlv_clock(refclk, &clock);
805
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
808 continue;
809
810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
812
813 if (ppm < 100 && clock.p > best_clock->p) {
814 bestppm = 0;
815 *best_clock = clock;
816 found = true;
817 }
818
819 if (bestppm >= 10 && ppm < bestppm - 10) {
820 bestppm = ppm;
821 *best_clock = clock;
822 found = true;
823 }
824 }
825 }
826 }
827 }
828
829 return found;
830 }
831
832 static bool
833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
836 {
837 struct drm_device *dev = crtc->base.dev;
838 intel_clock_t clock;
839 uint64_t m2;
840 int found = false;
841
842 memset(best_clock, 0, sizeof(*best_clock));
843
844 /*
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
848 */
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
851
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856
857 clock.p = clock.p1 * clock.p2;
858
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
861
862 if (m2 > INT_MAX/clock.m1)
863 continue;
864
865 clock.m2 = m2;
866
867 chv_clock(refclk, &clock);
868
869 if (!intel_PLL_is_valid(dev, limit, &clock))
870 continue;
871
872 /* based on hardware requirement, prefer bigger p
873 */
874 if (clock.p > best_clock->p) {
875 *best_clock = clock;
876 found = true;
877 }
878 }
879 }
880
881 return found;
882 }
883
884 bool intel_crtc_active(struct drm_crtc *crtc)
885 {
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
890 *
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
893 *
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
896 */
897 return intel_crtc->active && crtc->primary->fb &&
898 intel_crtc->config.adjusted_mode.crtc_clock;
899 }
900
901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902 enum pipe pipe)
903 {
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906
907 return intel_crtc->config.cpu_transcoder;
908 }
909
910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
911 {
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
914 u32 line1, line2;
915 u32 line_mask;
916
917 if (IS_GEN2(dev))
918 line_mask = DSL_LINEMASK_GEN2;
919 else
920 line_mask = DSL_LINEMASK_GEN3;
921
922 line1 = I915_READ(reg) & line_mask;
923 mdelay(5);
924 line2 = I915_READ(reg) & line_mask;
925
926 return line1 == line2;
927 }
928
929 /*
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
932 *
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
936 *
937 * On Gen4 and above:
938 * wait for the pipe register state bit to turn off
939 *
940 * Otherwise:
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
943 *
944 */
945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
946 {
947 struct drm_device *dev = crtc->base.dev;
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
951
952 if (INTEL_INFO(dev)->gen >= 4) {
953 int reg = PIPECONF(cpu_transcoder);
954
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
957 100))
958 WARN(1, "pipe_off wait timed out\n");
959 } else {
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
962 WARN(1, "pipe_off wait timed out\n");
963 }
964 }
965
966 /*
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
970 *
971 * Returns true if @port is connected, false otherwise.
972 */
973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
975 {
976 u32 bit;
977
978 if (HAS_PCH_IBX(dev_priv->dev)) {
979 switch (port->port) {
980 case PORT_B:
981 bit = SDE_PORTB_HOTPLUG;
982 break;
983 case PORT_C:
984 bit = SDE_PORTC_HOTPLUG;
985 break;
986 case PORT_D:
987 bit = SDE_PORTD_HOTPLUG;
988 break;
989 default:
990 return true;
991 }
992 } else {
993 switch (port->port) {
994 case PORT_B:
995 bit = SDE_PORTB_HOTPLUG_CPT;
996 break;
997 case PORT_C:
998 bit = SDE_PORTC_HOTPLUG_CPT;
999 break;
1000 case PORT_D:
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1002 break;
1003 default:
1004 return true;
1005 }
1006 }
1007
1008 return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013 return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
1019 {
1020 int reg;
1021 u32 val;
1022 bool cur_state;
1023
1024 reg = DPLL(pipe);
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035 u32 val;
1036 bool cur_state;
1037
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1041
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055 if (crtc->config.shared_dpll < 0)
1056 return NULL;
1057
1058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1064 bool state)
1065 {
1066 bool cur_state;
1067 struct intel_dpll_hw_state hw_state;
1068
1069 if (WARN (!pll,
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1071 return;
1072
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081 {
1082 int reg;
1083 u32 val;
1084 bool cur_state;
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
1087
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124 {
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130 return;
1131
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1134 return;
1135
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158 {
1159 struct drm_device *dev = dev_priv->dev;
1160 int pp_reg;
1161 u32 val;
1162 enum pipe panel_pipe = PIPE_A;
1163 bool locked = true;
1164
1165 if (WARN_ON(HAS_DDI(dev)))
1166 return;
1167
1168 if (HAS_PCH_SPLIT(dev)) {
1169 u32 port_sel;
1170
1171 pp_reg = PCH_PP_CONTROL;
1172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181 panel_pipe = pipe;
1182 } else {
1183 pp_reg = PP_CONTROL;
1184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
1186 }
1187
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
1190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191 locked = false;
1192
1193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
1195 pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200 {
1201 struct drm_device *dev = dev_priv->dev;
1202 bool cur_state;
1203
1204 if (IS_845G(dev) || IS_I865G(dev))
1205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206 else
1207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1218 {
1219 int reg;
1220 u32 val;
1221 bool cur_state;
1222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223 pipe);
1224
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228 state = true;
1229
1230 if (!intel_display_power_is_enabled(dev_priv,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1246 {
1247 int reg;
1248 u32 val;
1249 bool cur_state;
1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 struct drm_device *dev = dev_priv->dev;
1266 int reg, i;
1267 u32 val;
1268 int cur_pipe;
1269
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
1272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
1274 WARN(val & DISPLAY_PLANE_ENABLE,
1275 "plane %c assertion failure, should be disabled but not\n",
1276 plane_name(pipe));
1277 return;
1278 }
1279
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv, i) {
1282 reg = DSPCNTR(i);
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
1289 }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe)
1294 {
1295 struct drm_device *dev = dev_priv->dev;
1296 int reg, sprite;
1297 u32 val;
1298
1299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1305 }
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
1309 val = I915_READ(reg);
1310 WARN(val & SP_ENABLE,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe, sprite), pipe_name(pipe));
1313 }
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1315 reg = SPRCTL(pipe);
1316 val = I915_READ(reg);
1317 WARN(val & SPRITE_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
1323 WARN(val & DVS_ENABLE,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
1326 }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337 u32 val;
1338 bool enabled;
1339
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349 enum pipe pipe)
1350 {
1351 int reg;
1352 u32 val;
1353 bool enabled;
1354
1355 reg = PCH_TRANSCONF(pipe);
1356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
1358 WARN(enabled,
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360 pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366 if ((val & DP_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373 return false;
1374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376 return false;
1377 } else {
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379 return false;
1380 }
1381 return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1386 {
1387 if ((val & SDVO_ENABLE) == 0)
1388 return false;
1389
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
1391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392 return false;
1393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395 return false;
1396 } else {
1397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398 return false;
1399 }
1400 return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1405 {
1406 if ((val & LVDS_PORT_EN) == 0)
1407 return false;
1408
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411 return false;
1412 } else {
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414 return false;
1415 }
1416 return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421 {
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1423 return false;
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426 return false;
1427 } else {
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429 return false;
1430 }
1431 return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435 enum pipe pipe, int reg, u32 port_sel)
1436 {
1437 u32 val = I915_READ(reg);
1438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg, pipe_name(pipe));
1441
1442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
1444 "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1449 {
1450 u32 val = I915_READ(reg);
1451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg, pipe_name(pipe));
1454
1455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456 && (val & SDVO_PIPE_B_SELECT),
1457 "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe)
1462 {
1463 int reg;
1464 u32 val;
1465
1466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470 reg = PCH_ADPA;
1471 val = I915_READ(reg);
1472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1474 pipe_name(pipe));
1475
1476 reg = PCH_LVDS;
1477 val = I915_READ(reg);
1478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491 if (!IS_VALLEYVIEW(dev))
1492 return;
1493
1494 /*
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498 */
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502 } else {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504 }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
1509 {
1510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
1513 u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv->dev))
1522 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524 I915_WRITE(reg, dpll);
1525 POSTING_READ(reg);
1526 udelay(150);
1527
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532 POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534 /* We do this three times for luck */
1535 I915_WRITE(reg, dpll);
1536 POSTING_READ(reg);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
1548 {
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553 u32 tmp;
1554
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559 mutex_lock(&dev_priv->dpio_lock);
1560
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566 /*
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568 */
1569 udelay(1);
1570
1571 /* Enable PLL */
1572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580 POSTING_READ(DPLL_MD(pipe));
1581
1582 mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587 struct intel_crtc *crtc;
1588 int count = 0;
1589
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
1592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594 return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604 assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615 /*
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1620 */
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624 }
1625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
1641
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1668
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) &&
1671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677 }
1678
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682 return;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
1687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693 u32 val = 0;
1694
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1697
1698 /*
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1701 */
1702 if (pipe == PIPE_B)
1703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712 u32 val;
1713
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1716
1717 /* Set PLL en = 0 */
1718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719 if (pipe != PIPE_A)
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1723
1724 mutex_lock(&dev_priv->dpio_lock);
1725
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736 } else {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740 }
1741
1742 mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
1747 {
1748 u32 port_mask;
1749 int dpll_reg;
1750
1751 switch (dport->port) {
1752 case PORT_B:
1753 port_mask = DPLL_PORTB_READY_MASK;
1754 dpll_reg = DPLL(0);
1755 break;
1756 case PORT_C:
1757 port_mask = DPLL_PORTC_READY_MASK;
1758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_D:
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
1763 break;
1764 default:
1765 BUG();
1766 }
1767
1768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779 if (WARN_ON(pll == NULL))
1780 return;
1781
1782 WARN_ON(!pll->config.crtc_mask);
1783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785 WARN_ON(pll->on);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788 pll->mode_set(dev_priv, pll);
1789 }
1790 }
1791
1792 /**
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1796 *
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1799 */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806 if (WARN_ON(pll == NULL))
1807 return;
1808
1809 if (WARN_ON(pll->config.crtc_mask == 0))
1810 return;
1811
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1815
1816 if (pll->active++) {
1817 WARN_ON(!pll->on);
1818 assert_shared_dpll_enabled(dev_priv, pll);
1819 return;
1820 }
1821 WARN_ON(pll->on);
1822
1823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826 pll->enable(dev_priv, pll);
1827 pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev)->gen < 5);
1838 if (WARN_ON(pll == NULL))
1839 return;
1840
1841 if (WARN_ON(pll->config.crtc_mask == 0))
1842 return;
1843
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
1846 crtc->base.base.id);
1847
1848 if (WARN_ON(pll->active == 0)) {
1849 assert_shared_dpll_disabled(dev_priv, pll);
1850 return;
1851 }
1852
1853 assert_shared_dpll_enabled(dev_priv, pll);
1854 WARN_ON(!pll->on);
1855 if (--pll->active)
1856 return;
1857
1858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859 pll->disable(dev_priv, pll);
1860 pll->on = false;
1861
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
1867 {
1868 struct drm_device *dev = dev_priv->dev;
1869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871 uint32_t reg, val, pipeconf_val;
1872
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv,
1878 intel_crtc_to_shared_dpll(intel_crtc));
1879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
1891 }
1892
1893 reg = PCH_TRANSCONF(pipe);
1894 val = I915_READ(reg);
1895 pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1898 /*
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1901 */
1902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904 }
1905
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908 if (HAS_PCH_IBX(dev_priv->dev) &&
1909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910 val |= TRANS_LEGACY_INTERLACED_ILK;
1911 else
1912 val |= TRANS_INTERLACED;
1913 else
1914 val |= TRANS_PROGRESSIVE;
1915
1916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 enum transcoder cpu_transcoder)
1923 {
1924 u32 val, pipeconf_val;
1925
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
1935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936 I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938 val = TRANS_ENABLE;
1939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
1943 val |= TRANS_INTERLACED;
1944 else
1945 val |= TRANS_PROGRESSIVE;
1946
1947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 enum pipe pipe)
1954 {
1955 struct drm_device *dev = dev_priv->dev;
1956 uint32_t reg, val;
1957
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1964
1965 reg = PCH_TRANSCONF(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1979 }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984 u32 val;
1985
1986 val = I915_READ(LPT_TRANSCONF);
1987 val &= ~TRANS_ENABLE;
1988 I915_WRITE(LPT_TRANSCONF, val);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
1995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996 I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2002 *
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005 */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
2011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012 pipe);
2013 enum pipe pch_transcoder;
2014 int reg;
2015 u32 val;
2016
2017 assert_planes_disabled(dev_priv, pipe);
2018 assert_cursor_disabled(dev_priv, pipe);
2019 assert_sprites_disabled(dev_priv, pipe);
2020
2021 if (HAS_PCH_LPT(dev_priv->dev))
2022 pch_transcoder = TRANSCODER_A;
2023 else
2024 pch_transcoder = pipe;
2025
2026 /*
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2029 * need the check.
2030 */
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
2032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033 assert_dsi_pll_enabled(dev_priv);
2034 else
2035 assert_pll_enabled(dev_priv, pipe);
2036 else {
2037 if (crtc->config.has_pch_encoder) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
2042 }
2043 /* FIXME: assert CPU port conditions for SNB+ */
2044 }
2045
2046 reg = PIPECONF(cpu_transcoder);
2047 val = I915_READ(reg);
2048 if (val & PIPECONF_ENABLE) {
2049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051 return;
2052 }
2053
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
2055 POSTING_READ(reg);
2056 }
2057
2058 /**
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2061 *
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2065 *
2066 * Will wait until the pipe has shut down before returning.
2067 */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
2073 int reg;
2074 u32 val;
2075
2076 /*
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2079 */
2080 assert_planes_disabled(dev_priv, pipe);
2081 assert_cursor_disabled(dev_priv, pipe);
2082 assert_sprites_disabled(dev_priv, pipe);
2083
2084 reg = PIPECONF(cpu_transcoder);
2085 val = I915_READ(reg);
2086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
2089 /*
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2092 */
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099 val &= ~PIPECONF_ENABLE;
2100
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2109 */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane)
2112 {
2113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116 I915_WRITE(reg, I915_READ(reg));
2117 POSTING_READ(reg);
2118 }
2119
2120 /**
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2124 *
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2126 */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
2129 {
2130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137 if (intel_crtc->primary_enabled)
2138 return;
2139
2140 intel_crtc->primary_enabled = true;
2141
2142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2143 crtc->x, crtc->y);
2144
2145 /*
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2149 */
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2158 *
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2160 */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
2163 {
2164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170 if (!intel_crtc->primary_enabled)
2171 return;
2172
2173 intel_crtc->primary_enabled = false;
2174
2175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184 #endif
2185 return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190 int tile_height;
2191
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198 struct drm_framebuffer *fb,
2199 struct intel_engine_cs *pipelined)
2200 {
2201 struct drm_device *dev = fb->dev;
2202 struct drm_i915_private *dev_priv = dev->dev_private;
2203 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204 u32 alignment;
2205 int ret;
2206
2207 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209 switch (obj->tiling_mode) {
2210 case I915_TILING_NONE:
2211 if (INTEL_INFO(dev)->gen >= 9)
2212 alignment = 256 * 1024;
2213 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214 alignment = 128 * 1024;
2215 else if (INTEL_INFO(dev)->gen >= 4)
2216 alignment = 4 * 1024;
2217 else
2218 alignment = 64 * 1024;
2219 break;
2220 case I915_TILING_X:
2221 if (INTEL_INFO(dev)->gen >= 9)
2222 alignment = 256 * 1024;
2223 else {
2224 /* pin() will align the object as required by fence */
2225 alignment = 0;
2226 }
2227 break;
2228 case I915_TILING_Y:
2229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230 return -EINVAL;
2231 default:
2232 BUG();
2233 }
2234
2235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2238 * the VT-d warning.
2239 */
2240 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241 alignment = 256 * 1024;
2242
2243 /*
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2249 */
2250 intel_runtime_pm_get(dev_priv);
2251
2252 dev_priv->mm.interruptible = false;
2253 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254 if (ret)
2255 goto err_interruptible;
2256
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2261 */
2262 ret = i915_gem_object_get_fence(obj);
2263 if (ret)
2264 goto err_unpin;
2265
2266 i915_gem_object_pin_fence(obj);
2267
2268 dev_priv->mm.interruptible = true;
2269 intel_runtime_pm_put(dev_priv);
2270 return 0;
2271
2272 err_unpin:
2273 i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275 dev_priv->mm.interruptible = true;
2276 intel_runtime_pm_put(dev_priv);
2277 return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284 i915_gem_object_unpin_fence(obj);
2285 i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291 unsigned int tiling_mode,
2292 unsigned int cpp,
2293 unsigned int pitch)
2294 {
2295 if (tiling_mode != I915_TILING_NONE) {
2296 unsigned int tile_rows, tiles;
2297
2298 tile_rows = *y / 8;
2299 *y %= 8;
2300
2301 tiles = *x / (512/cpp);
2302 *x %= 512/cpp;
2303
2304 return tile_rows * pitch * 8 + tiles * 4096;
2305 } else {
2306 unsigned int offset;
2307
2308 offset = *y * pitch + *x * cpp;
2309 *y = 0;
2310 *x = (offset & 4095) / cpp;
2311 return offset & -4096;
2312 }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317 switch (format) {
2318 case DISPPLANE_8BPP:
2319 return DRM_FORMAT_C8;
2320 case DISPPLANE_BGRX555:
2321 return DRM_FORMAT_XRGB1555;
2322 case DISPPLANE_BGRX565:
2323 return DRM_FORMAT_RGB565;
2324 default:
2325 case DISPPLANE_BGRX888:
2326 return DRM_FORMAT_XRGB8888;
2327 case DISPPLANE_RGBX888:
2328 return DRM_FORMAT_XBGR8888;
2329 case DISPPLANE_BGRX101010:
2330 return DRM_FORMAT_XRGB2101010;
2331 case DISPPLANE_RGBX101010:
2332 return DRM_FORMAT_XBGR2101010;
2333 }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337 struct intel_plane_config *plane_config)
2338 {
2339 struct drm_device *dev = crtc->base.dev;
2340 struct drm_i915_gem_object *obj = NULL;
2341 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342 u32 base = plane_config->base;
2343
2344 if (plane_config->size == 0)
2345 return false;
2346
2347 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348 plane_config->size);
2349 if (!obj)
2350 return false;
2351
2352 if (plane_config->tiled) {
2353 obj->tiling_mode = I915_TILING_X;
2354 obj->stride = crtc->base.primary->fb->pitches[0];
2355 }
2356
2357 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358 mode_cmd.width = crtc->base.primary->fb->width;
2359 mode_cmd.height = crtc->base.primary->fb->height;
2360 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362 mutex_lock(&dev->struct_mutex);
2363
2364 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365 &mode_cmd, obj)) {
2366 DRM_DEBUG_KMS("intel fb init failed\n");
2367 goto out_unref_obj;
2368 }
2369
2370 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371 mutex_unlock(&dev->struct_mutex);
2372
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374 return true;
2375
2376 out_unref_obj:
2377 drm_gem_object_unreference(&obj->base);
2378 mutex_unlock(&dev->struct_mutex);
2379 return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383 struct intel_plane_config *plane_config)
2384 {
2385 struct drm_device *dev = intel_crtc->base.dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct drm_crtc *c;
2388 struct intel_crtc *i;
2389 struct drm_i915_gem_object *obj;
2390
2391 if (!intel_crtc->base.primary->fb)
2392 return;
2393
2394 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395 return;
2396
2397 kfree(intel_crtc->base.primary->fb);
2398 intel_crtc->base.primary->fb = NULL;
2399
2400 /*
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2403 */
2404 for_each_crtc(dev, c) {
2405 i = to_intel_crtc(c);
2406
2407 if (c == &intel_crtc->base)
2408 continue;
2409
2410 if (!i->active)
2411 continue;
2412
2413 obj = intel_fb_obj(c->primary->fb);
2414 if (obj == NULL)
2415 continue;
2416
2417 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418 if (obj->tiling_mode != I915_TILING_NONE)
2419 dev_priv->preserve_bios_swizzle = true;
2420
2421 drm_framebuffer_reference(c->primary->fb);
2422 intel_crtc->base.primary->fb = c->primary->fb;
2423 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424 break;
2425 }
2426 }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430 struct drm_framebuffer *fb,
2431 int x, int y)
2432 {
2433 struct drm_device *dev = crtc->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436 struct drm_i915_gem_object *obj;
2437 int plane = intel_crtc->plane;
2438 unsigned long linear_offset;
2439 u32 dspcntr;
2440 u32 reg = DSPCNTR(plane);
2441 int pixel_size;
2442
2443 if (!intel_crtc->primary_enabled) {
2444 I915_WRITE(reg, 0);
2445 if (INTEL_INFO(dev)->gen >= 4)
2446 I915_WRITE(DSPSURF(plane), 0);
2447 else
2448 I915_WRITE(DSPADDR(plane), 0);
2449 POSTING_READ(reg);
2450 return;
2451 }
2452
2453 obj = intel_fb_obj(fb);
2454 if (WARN_ON(obj == NULL))
2455 return;
2456
2457 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459 dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461 dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463 if (INTEL_INFO(dev)->gen < 4) {
2464 if (intel_crtc->pipe == PIPE_B)
2465 dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2469 */
2470 I915_WRITE(DSPSIZE(plane),
2471 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472 (intel_crtc->config.pipe_src_w - 1));
2473 I915_WRITE(DSPPOS(plane), 0);
2474 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475 I915_WRITE(PRIMSIZE(plane),
2476 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477 (intel_crtc->config.pipe_src_w - 1));
2478 I915_WRITE(PRIMPOS(plane), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480 }
2481
2482 switch (fb->pixel_format) {
2483 case DRM_FORMAT_C8:
2484 dspcntr |= DISPPLANE_8BPP;
2485 break;
2486 case DRM_FORMAT_XRGB1555:
2487 case DRM_FORMAT_ARGB1555:
2488 dspcntr |= DISPPLANE_BGRX555;
2489 break;
2490 case DRM_FORMAT_RGB565:
2491 dspcntr |= DISPPLANE_BGRX565;
2492 break;
2493 case DRM_FORMAT_XRGB8888:
2494 case DRM_FORMAT_ARGB8888:
2495 dspcntr |= DISPPLANE_BGRX888;
2496 break;
2497 case DRM_FORMAT_XBGR8888:
2498 case DRM_FORMAT_ABGR8888:
2499 dspcntr |= DISPPLANE_RGBX888;
2500 break;
2501 case DRM_FORMAT_XRGB2101010:
2502 case DRM_FORMAT_ARGB2101010:
2503 dspcntr |= DISPPLANE_BGRX101010;
2504 break;
2505 case DRM_FORMAT_XBGR2101010:
2506 case DRM_FORMAT_ABGR2101010:
2507 dspcntr |= DISPPLANE_RGBX101010;
2508 break;
2509 default:
2510 BUG();
2511 }
2512
2513 if (INTEL_INFO(dev)->gen >= 4 &&
2514 obj->tiling_mode != I915_TILING_NONE)
2515 dspcntr |= DISPPLANE_TILED;
2516
2517 if (IS_G4X(dev))
2518 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520 linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522 if (INTEL_INFO(dev)->gen >= 4) {
2523 intel_crtc->dspaddr_offset =
2524 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525 pixel_size,
2526 fb->pitches[0]);
2527 linear_offset -= intel_crtc->dspaddr_offset;
2528 } else {
2529 intel_crtc->dspaddr_offset = linear_offset;
2530 }
2531
2532 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535 x += (intel_crtc->config.pipe_src_w - 1);
2536 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2540 linear_offset +=
2541 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543 }
2544
2545 I915_WRITE(reg, dspcntr);
2546
2547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549 fb->pitches[0]);
2550 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551 if (INTEL_INFO(dev)->gen >= 4) {
2552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556 } else
2557 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558 POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562 struct drm_framebuffer *fb,
2563 int x, int y)
2564 {
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 struct drm_i915_gem_object *obj;
2569 int plane = intel_crtc->plane;
2570 unsigned long linear_offset;
2571 u32 dspcntr;
2572 u32 reg = DSPCNTR(plane);
2573 int pixel_size;
2574
2575 if (!intel_crtc->primary_enabled) {
2576 I915_WRITE(reg, 0);
2577 I915_WRITE(DSPSURF(plane), 0);
2578 POSTING_READ(reg);
2579 return;
2580 }
2581
2582 obj = intel_fb_obj(fb);
2583 if (WARN_ON(obj == NULL))
2584 return;
2585
2586 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588 dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590 dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595 switch (fb->pixel_format) {
2596 case DRM_FORMAT_C8:
2597 dspcntr |= DISPPLANE_8BPP;
2598 break;
2599 case DRM_FORMAT_RGB565:
2600 dspcntr |= DISPPLANE_BGRX565;
2601 break;
2602 case DRM_FORMAT_XRGB8888:
2603 case DRM_FORMAT_ARGB8888:
2604 dspcntr |= DISPPLANE_BGRX888;
2605 break;
2606 case DRM_FORMAT_XBGR8888:
2607 case DRM_FORMAT_ABGR8888:
2608 dspcntr |= DISPPLANE_RGBX888;
2609 break;
2610 case DRM_FORMAT_XRGB2101010:
2611 case DRM_FORMAT_ARGB2101010:
2612 dspcntr |= DISPPLANE_BGRX101010;
2613 break;
2614 case DRM_FORMAT_XBGR2101010:
2615 case DRM_FORMAT_ABGR2101010:
2616 dspcntr |= DISPPLANE_RGBX101010;
2617 break;
2618 default:
2619 BUG();
2620 }
2621
2622 if (obj->tiling_mode != I915_TILING_NONE)
2623 dspcntr |= DISPPLANE_TILED;
2624
2625 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628 linear_offset = y * fb->pitches[0] + x * pixel_size;
2629 intel_crtc->dspaddr_offset =
2630 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631 pixel_size,
2632 fb->pitches[0]);
2633 linear_offset -= intel_crtc->dspaddr_offset;
2634 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638 x += (intel_crtc->config.pipe_src_w - 1);
2639 y += (intel_crtc->config.pipe_src_h - 1);
2640
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2643 linear_offset +=
2644 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646 }
2647 }
2648
2649 I915_WRITE(reg, dspcntr);
2650
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653 fb->pitches[0]);
2654 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655 I915_WRITE(DSPSURF(plane),
2656 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659 } else {
2660 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662 }
2663 POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667 struct drm_framebuffer *fb,
2668 int x, int y)
2669 {
2670 struct drm_device *dev = crtc->dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673 struct intel_framebuffer *intel_fb;
2674 struct drm_i915_gem_object *obj;
2675 int pipe = intel_crtc->pipe;
2676 u32 plane_ctl, stride;
2677
2678 if (!intel_crtc->primary_enabled) {
2679 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe, 0));
2682 return;
2683 }
2684
2685 plane_ctl = PLANE_CTL_ENABLE |
2686 PLANE_CTL_PIPE_GAMMA_ENABLE |
2687 PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689 switch (fb->pixel_format) {
2690 case DRM_FORMAT_RGB565:
2691 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692 break;
2693 case DRM_FORMAT_XRGB8888:
2694 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695 break;
2696 case DRM_FORMAT_XBGR8888:
2697 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699 break;
2700 case DRM_FORMAT_XRGB2101010:
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702 break;
2703 case DRM_FORMAT_XBGR2101010:
2704 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706 break;
2707 default:
2708 BUG();
2709 }
2710
2711 intel_fb = to_intel_framebuffer(fb);
2712 obj = intel_fb->obj;
2713
2714 /*
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2717 */
2718 switch (obj->tiling_mode) {
2719 case I915_TILING_NONE:
2720 stride = fb->pitches[0] >> 6;
2721 break;
2722 case I915_TILING_X:
2723 plane_ctl |= PLANE_CTL_TILED_X;
2724 stride = fb->pitches[0] >> 9;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj),
2738 x, y, fb->width, fb->height,
2739 fb->pitches[0]);
2740
2741 I915_WRITE(PLANE_POS(pipe, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743 I915_WRITE(PLANE_SIZE(pipe, 0),
2744 (intel_crtc->config.pipe_src_h - 1) << 16 |
2745 (intel_crtc->config.pipe_src_w - 1));
2746 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749 POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755 int x, int y, enum mode_set_atomic state)
2756 {
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760 if (dev_priv->display.disable_fbc)
2761 dev_priv->display.disable_fbc(dev);
2762
2763 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765 return 0;
2766 }
2767
2768 static void intel_complete_page_flips(struct drm_device *dev)
2769 {
2770 struct drm_crtc *crtc;
2771
2772 for_each_crtc(dev, crtc) {
2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774 enum plane plane = intel_crtc->plane;
2775
2776 intel_prepare_page_flip(dev, plane);
2777 intel_finish_page_flip_plane(dev, plane);
2778 }
2779 }
2780
2781 static void intel_update_primary_planes(struct drm_device *dev)
2782 {
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct drm_crtc *crtc;
2785
2786 for_each_crtc(dev, crtc) {
2787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788
2789 drm_modeset_lock(&crtc->mutex, NULL);
2790 /*
2791 * FIXME: Once we have proper support for primary planes (and
2792 * disabling them without disabling the entire crtc) allow again
2793 * a NULL crtc->primary->fb.
2794 */
2795 if (intel_crtc->active && crtc->primary->fb)
2796 dev_priv->display.update_primary_plane(crtc,
2797 crtc->primary->fb,
2798 crtc->x,
2799 crtc->y);
2800 drm_modeset_unlock(&crtc->mutex);
2801 }
2802 }
2803
2804 void intel_prepare_reset(struct drm_device *dev)
2805 {
2806 struct drm_i915_private *dev_priv = to_i915(dev);
2807 struct intel_crtc *crtc;
2808
2809 /* no reset support for gen2 */
2810 if (IS_GEN2(dev))
2811 return;
2812
2813 /* reset doesn't touch the display */
2814 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2815 return;
2816
2817 drm_modeset_lock_all(dev);
2818
2819 /*
2820 * Disabling the crtcs gracefully seems nicer. Also the
2821 * g33 docs say we should at least disable all the planes.
2822 */
2823 for_each_intel_crtc(dev, crtc) {
2824 if (crtc->active)
2825 dev_priv->display.crtc_disable(&crtc->base);
2826 }
2827 }
2828
2829 void intel_finish_reset(struct drm_device *dev)
2830 {
2831 struct drm_i915_private *dev_priv = to_i915(dev);
2832
2833 /*
2834 * Flips in the rings will be nuked by the reset,
2835 * so complete all pending flips so that user space
2836 * will get its events and not get stuck.
2837 */
2838 intel_complete_page_flips(dev);
2839
2840 /* no reset support for gen2 */
2841 if (IS_GEN2(dev))
2842 return;
2843
2844 /* reset doesn't touch the display */
2845 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2846 /*
2847 * Flips in the rings have been nuked by the reset,
2848 * so update the base address of all primary
2849 * planes to the the last fb to make sure we're
2850 * showing the correct fb after a reset.
2851 */
2852 intel_update_primary_planes(dev);
2853 return;
2854 }
2855
2856 /*
2857 * The display has been reset as well,
2858 * so need a full re-initialization.
2859 */
2860 intel_runtime_pm_disable_interrupts(dev_priv);
2861 intel_runtime_pm_enable_interrupts(dev_priv);
2862
2863 intel_modeset_init_hw(dev);
2864
2865 spin_lock_irq(&dev_priv->irq_lock);
2866 if (dev_priv->display.hpd_irq_setup)
2867 dev_priv->display.hpd_irq_setup(dev);
2868 spin_unlock_irq(&dev_priv->irq_lock);
2869
2870 intel_modeset_setup_hw_state(dev, true);
2871
2872 intel_hpd_init(dev_priv);
2873
2874 drm_modeset_unlock_all(dev);
2875 }
2876
2877 static int
2878 intel_finish_fb(struct drm_framebuffer *old_fb)
2879 {
2880 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2881 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2882 bool was_interruptible = dev_priv->mm.interruptible;
2883 int ret;
2884
2885 /* Big Hammer, we also need to ensure that any pending
2886 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2887 * current scanout is retired before unpinning the old
2888 * framebuffer.
2889 *
2890 * This should only fail upon a hung GPU, in which case we
2891 * can safely continue.
2892 */
2893 dev_priv->mm.interruptible = false;
2894 ret = i915_gem_object_finish_gpu(obj);
2895 dev_priv->mm.interruptible = was_interruptible;
2896
2897 return ret;
2898 }
2899
2900 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2901 {
2902 struct drm_device *dev = crtc->dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905 bool pending;
2906
2907 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2908 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2909 return false;
2910
2911 spin_lock_irq(&dev->event_lock);
2912 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2913 spin_unlock_irq(&dev->event_lock);
2914
2915 return pending;
2916 }
2917
2918 static void intel_update_pipe_size(struct intel_crtc *crtc)
2919 {
2920 struct drm_device *dev = crtc->base.dev;
2921 struct drm_i915_private *dev_priv = dev->dev_private;
2922 const struct drm_display_mode *adjusted_mode;
2923
2924 if (!i915.fastboot)
2925 return;
2926
2927 /*
2928 * Update pipe size and adjust fitter if needed: the reason for this is
2929 * that in compute_mode_changes we check the native mode (not the pfit
2930 * mode) to see if we can flip rather than do a full mode set. In the
2931 * fastboot case, we'll flip, but if we don't update the pipesrc and
2932 * pfit state, we'll end up with a big fb scanned out into the wrong
2933 * sized surface.
2934 *
2935 * To fix this properly, we need to hoist the checks up into
2936 * compute_mode_changes (or above), check the actual pfit state and
2937 * whether the platform allows pfit disable with pipe active, and only
2938 * then update the pipesrc and pfit state, even on the flip path.
2939 */
2940
2941 adjusted_mode = &crtc->config.adjusted_mode;
2942
2943 I915_WRITE(PIPESRC(crtc->pipe),
2944 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2945 (adjusted_mode->crtc_vdisplay - 1));
2946 if (!crtc->config.pch_pfit.enabled &&
2947 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2948 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2949 I915_WRITE(PF_CTL(crtc->pipe), 0);
2950 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2951 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2952 }
2953 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2954 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2955 }
2956
2957 static int
2958 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2959 struct drm_framebuffer *fb)
2960 {
2961 struct drm_device *dev = crtc->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964 enum pipe pipe = intel_crtc->pipe;
2965 struct drm_framebuffer *old_fb = crtc->primary->fb;
2966 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2967 int ret;
2968
2969 if (intel_crtc_has_pending_flip(crtc)) {
2970 DRM_ERROR("pipe is still busy with an old pageflip\n");
2971 return -EBUSY;
2972 }
2973
2974 /* no fb bound */
2975 if (!fb) {
2976 DRM_ERROR("No FB bound\n");
2977 return 0;
2978 }
2979
2980 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2981 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2982 plane_name(intel_crtc->plane),
2983 INTEL_INFO(dev)->num_pipes);
2984 return -EINVAL;
2985 }
2986
2987 mutex_lock(&dev->struct_mutex);
2988 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2989 if (ret == 0)
2990 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2991 INTEL_FRONTBUFFER_PRIMARY(pipe));
2992 mutex_unlock(&dev->struct_mutex);
2993 if (ret != 0) {
2994 DRM_ERROR("pin & fence failed\n");
2995 return ret;
2996 }
2997
2998 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2999
3000 if (intel_crtc->active)
3001 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
3002
3003 crtc->primary->fb = fb;
3004 crtc->x = x;
3005 crtc->y = y;
3006
3007 if (old_fb) {
3008 if (intel_crtc->active && old_fb != fb)
3009 intel_wait_for_vblank(dev, intel_crtc->pipe);
3010 mutex_lock(&dev->struct_mutex);
3011 intel_unpin_fb_obj(old_obj);
3012 mutex_unlock(&dev->struct_mutex);
3013 }
3014
3015 mutex_lock(&dev->struct_mutex);
3016 intel_update_fbc(dev);
3017 mutex_unlock(&dev->struct_mutex);
3018
3019 return 0;
3020 }
3021
3022 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3023 {
3024 struct drm_device *dev = crtc->dev;
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027 int pipe = intel_crtc->pipe;
3028 u32 reg, temp;
3029
3030 /* enable normal train */
3031 reg = FDI_TX_CTL(pipe);
3032 temp = I915_READ(reg);
3033 if (IS_IVYBRIDGE(dev)) {
3034 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3035 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3036 } else {
3037 temp &= ~FDI_LINK_TRAIN_NONE;
3038 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3039 }
3040 I915_WRITE(reg, temp);
3041
3042 reg = FDI_RX_CTL(pipe);
3043 temp = I915_READ(reg);
3044 if (HAS_PCH_CPT(dev)) {
3045 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3046 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3047 } else {
3048 temp &= ~FDI_LINK_TRAIN_NONE;
3049 temp |= FDI_LINK_TRAIN_NONE;
3050 }
3051 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3052
3053 /* wait one idle pattern time */
3054 POSTING_READ(reg);
3055 udelay(1000);
3056
3057 /* IVB wants error correction enabled */
3058 if (IS_IVYBRIDGE(dev))
3059 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3060 FDI_FE_ERRC_ENABLE);
3061 }
3062
3063 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3064 {
3065 return crtc->base.enabled && crtc->active &&
3066 crtc->config.has_pch_encoder;
3067 }
3068
3069 static void ivb_modeset_global_resources(struct drm_device *dev)
3070 {
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct intel_crtc *pipe_B_crtc =
3073 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3074 struct intel_crtc *pipe_C_crtc =
3075 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3076 uint32_t temp;
3077
3078 /*
3079 * When everything is off disable fdi C so that we could enable fdi B
3080 * with all lanes. Note that we don't care about enabled pipes without
3081 * an enabled pch encoder.
3082 */
3083 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3084 !pipe_has_enabled_pch(pipe_C_crtc)) {
3085 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3086 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3087
3088 temp = I915_READ(SOUTH_CHICKEN1);
3089 temp &= ~FDI_BC_BIFURCATION_SELECT;
3090 DRM_DEBUG_KMS("disabling fdi C rx\n");
3091 I915_WRITE(SOUTH_CHICKEN1, temp);
3092 }
3093 }
3094
3095 /* The FDI link training functions for ILK/Ibexpeak. */
3096 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3097 {
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
3102 u32 reg, temp, tries;
3103
3104 /* FDI needs bits from pipe first */
3105 assert_pipe_enabled(dev_priv, pipe);
3106
3107 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3108 for train result */
3109 reg = FDI_RX_IMR(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_RX_SYMBOL_LOCK;
3112 temp &= ~FDI_RX_BIT_LOCK;
3113 I915_WRITE(reg, temp);
3114 I915_READ(reg);
3115 udelay(150);
3116
3117 /* enable CPU FDI TX and PCH FDI RX */
3118 reg = FDI_TX_CTL(pipe);
3119 temp = I915_READ(reg);
3120 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3121 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3122 temp &= ~FDI_LINK_TRAIN_NONE;
3123 temp |= FDI_LINK_TRAIN_PATTERN_1;
3124 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3125
3126 reg = FDI_RX_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~FDI_LINK_TRAIN_NONE;
3129 temp |= FDI_LINK_TRAIN_PATTERN_1;
3130 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3131
3132 POSTING_READ(reg);
3133 udelay(150);
3134
3135 /* Ironlake workaround, enable clock pointer after FDI enable*/
3136 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3137 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3138 FDI_RX_PHASE_SYNC_POINTER_EN);
3139
3140 reg = FDI_RX_IIR(pipe);
3141 for (tries = 0; tries < 5; tries++) {
3142 temp = I915_READ(reg);
3143 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3144
3145 if ((temp & FDI_RX_BIT_LOCK)) {
3146 DRM_DEBUG_KMS("FDI train 1 done.\n");
3147 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3148 break;
3149 }
3150 }
3151 if (tries == 5)
3152 DRM_ERROR("FDI train 1 fail!\n");
3153
3154 /* Train 2 */
3155 reg = FDI_TX_CTL(pipe);
3156 temp = I915_READ(reg);
3157 temp &= ~FDI_LINK_TRAIN_NONE;
3158 temp |= FDI_LINK_TRAIN_PATTERN_2;
3159 I915_WRITE(reg, temp);
3160
3161 reg = FDI_RX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 temp &= ~FDI_LINK_TRAIN_NONE;
3164 temp |= FDI_LINK_TRAIN_PATTERN_2;
3165 I915_WRITE(reg, temp);
3166
3167 POSTING_READ(reg);
3168 udelay(150);
3169
3170 reg = FDI_RX_IIR(pipe);
3171 for (tries = 0; tries < 5; tries++) {
3172 temp = I915_READ(reg);
3173 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3174
3175 if (temp & FDI_RX_SYMBOL_LOCK) {
3176 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3177 DRM_DEBUG_KMS("FDI train 2 done.\n");
3178 break;
3179 }
3180 }
3181 if (tries == 5)
3182 DRM_ERROR("FDI train 2 fail!\n");
3183
3184 DRM_DEBUG_KMS("FDI train done\n");
3185
3186 }
3187
3188 static const int snb_b_fdi_train_param[] = {
3189 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3190 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3191 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3192 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3193 };
3194
3195 /* The FDI link training functions for SNB/Cougarpoint. */
3196 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3197 {
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201 int pipe = intel_crtc->pipe;
3202 u32 reg, temp, i, retry;
3203
3204 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3205 for train result */
3206 reg = FDI_RX_IMR(pipe);
3207 temp = I915_READ(reg);
3208 temp &= ~FDI_RX_SYMBOL_LOCK;
3209 temp &= ~FDI_RX_BIT_LOCK;
3210 I915_WRITE(reg, temp);
3211
3212 POSTING_READ(reg);
3213 udelay(150);
3214
3215 /* enable CPU FDI TX and PCH FDI RX */
3216 reg = FDI_TX_CTL(pipe);
3217 temp = I915_READ(reg);
3218 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3219 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3220 temp &= ~FDI_LINK_TRAIN_NONE;
3221 temp |= FDI_LINK_TRAIN_PATTERN_1;
3222 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3223 /* SNB-B */
3224 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3225 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3226
3227 I915_WRITE(FDI_RX_MISC(pipe),
3228 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3229
3230 reg = FDI_RX_CTL(pipe);
3231 temp = I915_READ(reg);
3232 if (HAS_PCH_CPT(dev)) {
3233 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3234 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3235 } else {
3236 temp &= ~FDI_LINK_TRAIN_NONE;
3237 temp |= FDI_LINK_TRAIN_PATTERN_1;
3238 }
3239 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3240
3241 POSTING_READ(reg);
3242 udelay(150);
3243
3244 for (i = 0; i < 4; i++) {
3245 reg = FDI_TX_CTL(pipe);
3246 temp = I915_READ(reg);
3247 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3248 temp |= snb_b_fdi_train_param[i];
3249 I915_WRITE(reg, temp);
3250
3251 POSTING_READ(reg);
3252 udelay(500);
3253
3254 for (retry = 0; retry < 5; retry++) {
3255 reg = FDI_RX_IIR(pipe);
3256 temp = I915_READ(reg);
3257 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3258 if (temp & FDI_RX_BIT_LOCK) {
3259 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3260 DRM_DEBUG_KMS("FDI train 1 done.\n");
3261 break;
3262 }
3263 udelay(50);
3264 }
3265 if (retry < 5)
3266 break;
3267 }
3268 if (i == 4)
3269 DRM_ERROR("FDI train 1 fail!\n");
3270
3271 /* Train 2 */
3272 reg = FDI_TX_CTL(pipe);
3273 temp = I915_READ(reg);
3274 temp &= ~FDI_LINK_TRAIN_NONE;
3275 temp |= FDI_LINK_TRAIN_PATTERN_2;
3276 if (IS_GEN6(dev)) {
3277 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3278 /* SNB-B */
3279 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3280 }
3281 I915_WRITE(reg, temp);
3282
3283 reg = FDI_RX_CTL(pipe);
3284 temp = I915_READ(reg);
3285 if (HAS_PCH_CPT(dev)) {
3286 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3287 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3288 } else {
3289 temp &= ~FDI_LINK_TRAIN_NONE;
3290 temp |= FDI_LINK_TRAIN_PATTERN_2;
3291 }
3292 I915_WRITE(reg, temp);
3293
3294 POSTING_READ(reg);
3295 udelay(150);
3296
3297 for (i = 0; i < 4; i++) {
3298 reg = FDI_TX_CTL(pipe);
3299 temp = I915_READ(reg);
3300 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3301 temp |= snb_b_fdi_train_param[i];
3302 I915_WRITE(reg, temp);
3303
3304 POSTING_READ(reg);
3305 udelay(500);
3306
3307 for (retry = 0; retry < 5; retry++) {
3308 reg = FDI_RX_IIR(pipe);
3309 temp = I915_READ(reg);
3310 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3311 if (temp & FDI_RX_SYMBOL_LOCK) {
3312 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3313 DRM_DEBUG_KMS("FDI train 2 done.\n");
3314 break;
3315 }
3316 udelay(50);
3317 }
3318 if (retry < 5)
3319 break;
3320 }
3321 if (i == 4)
3322 DRM_ERROR("FDI train 2 fail!\n");
3323
3324 DRM_DEBUG_KMS("FDI train done.\n");
3325 }
3326
3327 /* Manual link training for Ivy Bridge A0 parts */
3328 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3329 {
3330 struct drm_device *dev = crtc->dev;
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333 int pipe = intel_crtc->pipe;
3334 u32 reg, temp, i, j;
3335
3336 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3337 for train result */
3338 reg = FDI_RX_IMR(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~FDI_RX_SYMBOL_LOCK;
3341 temp &= ~FDI_RX_BIT_LOCK;
3342 I915_WRITE(reg, temp);
3343
3344 POSTING_READ(reg);
3345 udelay(150);
3346
3347 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3348 I915_READ(FDI_RX_IIR(pipe)));
3349
3350 /* Try each vswing and preemphasis setting twice before moving on */
3351 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3352 /* disable first in case we need to retry */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3356 temp &= ~FDI_TX_ENABLE;
3357 I915_WRITE(reg, temp);
3358
3359 reg = FDI_RX_CTL(pipe);
3360 temp = I915_READ(reg);
3361 temp &= ~FDI_LINK_TRAIN_AUTO;
3362 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3363 temp &= ~FDI_RX_ENABLE;
3364 I915_WRITE(reg, temp);
3365
3366 /* enable CPU FDI TX and PCH FDI RX */
3367 reg = FDI_TX_CTL(pipe);
3368 temp = I915_READ(reg);
3369 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3370 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3371 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3372 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3373 temp |= snb_b_fdi_train_param[j/2];
3374 temp |= FDI_COMPOSITE_SYNC;
3375 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3376
3377 I915_WRITE(FDI_RX_MISC(pipe),
3378 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3379
3380 reg = FDI_RX_CTL(pipe);
3381 temp = I915_READ(reg);
3382 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3383 temp |= FDI_COMPOSITE_SYNC;
3384 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3385
3386 POSTING_READ(reg);
3387 udelay(1); /* should be 0.5us */
3388
3389 for (i = 0; i < 4; i++) {
3390 reg = FDI_RX_IIR(pipe);
3391 temp = I915_READ(reg);
3392 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3393
3394 if (temp & FDI_RX_BIT_LOCK ||
3395 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3396 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3397 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3398 i);
3399 break;
3400 }
3401 udelay(1); /* should be 0.5us */
3402 }
3403 if (i == 4) {
3404 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3405 continue;
3406 }
3407
3408 /* Train 2 */
3409 reg = FDI_TX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3413 I915_WRITE(reg, temp);
3414
3415 reg = FDI_RX_CTL(pipe);
3416 temp = I915_READ(reg);
3417 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3418 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3419 I915_WRITE(reg, temp);
3420
3421 POSTING_READ(reg);
3422 udelay(2); /* should be 1.5us */
3423
3424 for (i = 0; i < 4; i++) {
3425 reg = FDI_RX_IIR(pipe);
3426 temp = I915_READ(reg);
3427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3428
3429 if (temp & FDI_RX_SYMBOL_LOCK ||
3430 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3431 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3432 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3433 i);
3434 goto train_done;
3435 }
3436 udelay(2); /* should be 1.5us */
3437 }
3438 if (i == 4)
3439 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3440 }
3441
3442 train_done:
3443 DRM_DEBUG_KMS("FDI train done.\n");
3444 }
3445
3446 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3447 {
3448 struct drm_device *dev = intel_crtc->base.dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 int pipe = intel_crtc->pipe;
3451 u32 reg, temp;
3452
3453
3454 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3455 reg = FDI_RX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3459 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3460 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3461
3462 POSTING_READ(reg);
3463 udelay(200);
3464
3465 /* Switch from Rawclk to PCDclk */
3466 temp = I915_READ(reg);
3467 I915_WRITE(reg, temp | FDI_PCDCLK);
3468
3469 POSTING_READ(reg);
3470 udelay(200);
3471
3472 /* Enable CPU FDI TX PLL, always on for Ironlake */
3473 reg = FDI_TX_CTL(pipe);
3474 temp = I915_READ(reg);
3475 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3476 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3477
3478 POSTING_READ(reg);
3479 udelay(100);
3480 }
3481 }
3482
3483 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3484 {
3485 struct drm_device *dev = intel_crtc->base.dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 int pipe = intel_crtc->pipe;
3488 u32 reg, temp;
3489
3490 /* Switch from PCDclk to Rawclk */
3491 reg = FDI_RX_CTL(pipe);
3492 temp = I915_READ(reg);
3493 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3494
3495 /* Disable CPU FDI TX PLL */
3496 reg = FDI_TX_CTL(pipe);
3497 temp = I915_READ(reg);
3498 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3499
3500 POSTING_READ(reg);
3501 udelay(100);
3502
3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3506
3507 /* Wait for the clocks to turn off. */
3508 POSTING_READ(reg);
3509 udelay(100);
3510 }
3511
3512 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3513 {
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 int pipe = intel_crtc->pipe;
3518 u32 reg, temp;
3519
3520 /* disable CPU FDI tx and PCH FDI rx */
3521 reg = FDI_TX_CTL(pipe);
3522 temp = I915_READ(reg);
3523 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3524 POSTING_READ(reg);
3525
3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~(0x7 << 16);
3529 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3530 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3531
3532 POSTING_READ(reg);
3533 udelay(100);
3534
3535 /* Ironlake workaround, disable clock pointer after downing FDI */
3536 if (HAS_PCH_IBX(dev))
3537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3538
3539 /* still set train pattern 1 */
3540 reg = FDI_TX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_NONE;
3543 temp |= FDI_LINK_TRAIN_PATTERN_1;
3544 I915_WRITE(reg, temp);
3545
3546 reg = FDI_RX_CTL(pipe);
3547 temp = I915_READ(reg);
3548 if (HAS_PCH_CPT(dev)) {
3549 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3551 } else {
3552 temp &= ~FDI_LINK_TRAIN_NONE;
3553 temp |= FDI_LINK_TRAIN_PATTERN_1;
3554 }
3555 /* BPC in FDI rx is consistent with that in PIPECONF */
3556 temp &= ~(0x07 << 16);
3557 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3558 I915_WRITE(reg, temp);
3559
3560 POSTING_READ(reg);
3561 udelay(100);
3562 }
3563
3564 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3565 {
3566 struct intel_crtc *crtc;
3567
3568 /* Note that we don't need to be called with mode_config.lock here
3569 * as our list of CRTC objects is static for the lifetime of the
3570 * device and so cannot disappear as we iterate. Similarly, we can
3571 * happily treat the predicates as racy, atomic checks as userspace
3572 * cannot claim and pin a new fb without at least acquring the
3573 * struct_mutex and so serialising with us.
3574 */
3575 for_each_intel_crtc(dev, crtc) {
3576 if (atomic_read(&crtc->unpin_work_count) == 0)
3577 continue;
3578
3579 if (crtc->unpin_work)
3580 intel_wait_for_vblank(dev, crtc->pipe);
3581
3582 return true;
3583 }
3584
3585 return false;
3586 }
3587
3588 static void page_flip_completed(struct intel_crtc *intel_crtc)
3589 {
3590 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3591 struct intel_unpin_work *work = intel_crtc->unpin_work;
3592
3593 /* ensure that the unpin work is consistent wrt ->pending. */
3594 smp_rmb();
3595 intel_crtc->unpin_work = NULL;
3596
3597 if (work->event)
3598 drm_send_vblank_event(intel_crtc->base.dev,
3599 intel_crtc->pipe,
3600 work->event);
3601
3602 drm_crtc_vblank_put(&intel_crtc->base);
3603
3604 wake_up_all(&dev_priv->pending_flip_queue);
3605 queue_work(dev_priv->wq, &work->work);
3606
3607 trace_i915_flip_complete(intel_crtc->plane,
3608 work->pending_flip_obj);
3609 }
3610
3611 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3612 {
3613 struct drm_device *dev = crtc->dev;
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615
3616 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3617 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3618 !intel_crtc_has_pending_flip(crtc),
3619 60*HZ) == 0)) {
3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621
3622 spin_lock_irq(&dev->event_lock);
3623 if (intel_crtc->unpin_work) {
3624 WARN_ONCE(1, "Removing stuck page flip\n");
3625 page_flip_completed(intel_crtc);
3626 }
3627 spin_unlock_irq(&dev->event_lock);
3628 }
3629
3630 if (crtc->primary->fb) {
3631 mutex_lock(&dev->struct_mutex);
3632 intel_finish_fb(crtc->primary->fb);
3633 mutex_unlock(&dev->struct_mutex);
3634 }
3635 }
3636
3637 /* Program iCLKIP clock to the desired frequency */
3638 static void lpt_program_iclkip(struct drm_crtc *crtc)
3639 {
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3643 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3644 u32 temp;
3645
3646 mutex_lock(&dev_priv->dpio_lock);
3647
3648 /* It is necessary to ungate the pixclk gate prior to programming
3649 * the divisors, and gate it back when it is done.
3650 */
3651 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3652
3653 /* Disable SSCCTL */
3654 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3655 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3656 SBI_SSCCTL_DISABLE,
3657 SBI_ICLK);
3658
3659 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3660 if (clock == 20000) {
3661 auxdiv = 1;
3662 divsel = 0x41;
3663 phaseinc = 0x20;
3664 } else {
3665 /* The iCLK virtual clock root frequency is in MHz,
3666 * but the adjusted_mode->crtc_clock in in KHz. To get the
3667 * divisors, it is necessary to divide one by another, so we
3668 * convert the virtual clock precision to KHz here for higher
3669 * precision.
3670 */
3671 u32 iclk_virtual_root_freq = 172800 * 1000;
3672 u32 iclk_pi_range = 64;
3673 u32 desired_divisor, msb_divisor_value, pi_value;
3674
3675 desired_divisor = (iclk_virtual_root_freq / clock);
3676 msb_divisor_value = desired_divisor / iclk_pi_range;
3677 pi_value = desired_divisor % iclk_pi_range;
3678
3679 auxdiv = 0;
3680 divsel = msb_divisor_value - 2;
3681 phaseinc = pi_value;
3682 }
3683
3684 /* This should not happen with any sane values */
3685 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3686 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3687 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3688 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3689
3690 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3691 clock,
3692 auxdiv,
3693 divsel,
3694 phasedir,
3695 phaseinc);
3696
3697 /* Program SSCDIVINTPHASE6 */
3698 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3699 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3700 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3701 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3702 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3703 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3704 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3705 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3706
3707 /* Program SSCAUXDIV */
3708 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3709 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3710 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3711 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3712
3713 /* Enable modulator and associated divider */
3714 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3715 temp &= ~SBI_SSCCTL_DISABLE;
3716 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3717
3718 /* Wait for initialization time */
3719 udelay(24);
3720
3721 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3722
3723 mutex_unlock(&dev_priv->dpio_lock);
3724 }
3725
3726 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3727 enum pipe pch_transcoder)
3728 {
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3732
3733 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3734 I915_READ(HTOTAL(cpu_transcoder)));
3735 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3736 I915_READ(HBLANK(cpu_transcoder)));
3737 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3738 I915_READ(HSYNC(cpu_transcoder)));
3739
3740 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3741 I915_READ(VTOTAL(cpu_transcoder)));
3742 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3743 I915_READ(VBLANK(cpu_transcoder)));
3744 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3745 I915_READ(VSYNC(cpu_transcoder)));
3746 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3747 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3748 }
3749
3750 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3751 {
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753 uint32_t temp;
3754
3755 temp = I915_READ(SOUTH_CHICKEN1);
3756 if (temp & FDI_BC_BIFURCATION_SELECT)
3757 return;
3758
3759 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3760 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3761
3762 temp |= FDI_BC_BIFURCATION_SELECT;
3763 DRM_DEBUG_KMS("enabling fdi C rx\n");
3764 I915_WRITE(SOUTH_CHICKEN1, temp);
3765 POSTING_READ(SOUTH_CHICKEN1);
3766 }
3767
3768 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3769 {
3770 struct drm_device *dev = intel_crtc->base.dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772
3773 switch (intel_crtc->pipe) {
3774 case PIPE_A:
3775 break;
3776 case PIPE_B:
3777 if (intel_crtc->config.fdi_lanes > 2)
3778 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3779 else
3780 cpt_enable_fdi_bc_bifurcation(dev);
3781
3782 break;
3783 case PIPE_C:
3784 cpt_enable_fdi_bc_bifurcation(dev);
3785
3786 break;
3787 default:
3788 BUG();
3789 }
3790 }
3791
3792 /*
3793 * Enable PCH resources required for PCH ports:
3794 * - PCH PLLs
3795 * - FDI training & RX/TX
3796 * - update transcoder timings
3797 * - DP transcoding bits
3798 * - transcoder
3799 */
3800 static void ironlake_pch_enable(struct drm_crtc *crtc)
3801 {
3802 struct drm_device *dev = crtc->dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3805 int pipe = intel_crtc->pipe;
3806 u32 reg, temp;
3807
3808 assert_pch_transcoder_disabled(dev_priv, pipe);
3809
3810 if (IS_IVYBRIDGE(dev))
3811 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3812
3813 /* Write the TU size bits before fdi link training, so that error
3814 * detection works. */
3815 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3816 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3817
3818 /* For PCH output, training FDI link */
3819 dev_priv->display.fdi_link_train(crtc);
3820
3821 /* We need to program the right clock selection before writing the pixel
3822 * mutliplier into the DPLL. */
3823 if (HAS_PCH_CPT(dev)) {
3824 u32 sel;
3825
3826 temp = I915_READ(PCH_DPLL_SEL);
3827 temp |= TRANS_DPLL_ENABLE(pipe);
3828 sel = TRANS_DPLLB_SEL(pipe);
3829 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3830 temp |= sel;
3831 else
3832 temp &= ~sel;
3833 I915_WRITE(PCH_DPLL_SEL, temp);
3834 }
3835
3836 /* XXX: pch pll's can be enabled any time before we enable the PCH
3837 * transcoder, and we actually should do this to not upset any PCH
3838 * transcoder that already use the clock when we share it.
3839 *
3840 * Note that enable_shared_dpll tries to do the right thing, but
3841 * get_shared_dpll unconditionally resets the pll - we need that to have
3842 * the right LVDS enable sequence. */
3843 intel_enable_shared_dpll(intel_crtc);
3844
3845 /* set transcoder timing, panel must allow it */
3846 assert_panel_unlocked(dev_priv, pipe);
3847 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3848
3849 intel_fdi_normal_train(crtc);
3850
3851 /* For PCH DP, enable TRANS_DP_CTL */
3852 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3853 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3854 reg = TRANS_DP_CTL(pipe);
3855 temp = I915_READ(reg);
3856 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3857 TRANS_DP_SYNC_MASK |
3858 TRANS_DP_BPC_MASK);
3859 temp |= (TRANS_DP_OUTPUT_ENABLE |
3860 TRANS_DP_ENH_FRAMING);
3861 temp |= bpc << 9; /* same format but at 11:9 */
3862
3863 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3864 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3865 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3866 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3867
3868 switch (intel_trans_dp_port_sel(crtc)) {
3869 case PCH_DP_B:
3870 temp |= TRANS_DP_PORT_SEL_B;
3871 break;
3872 case PCH_DP_C:
3873 temp |= TRANS_DP_PORT_SEL_C;
3874 break;
3875 case PCH_DP_D:
3876 temp |= TRANS_DP_PORT_SEL_D;
3877 break;
3878 default:
3879 BUG();
3880 }
3881
3882 I915_WRITE(reg, temp);
3883 }
3884
3885 ironlake_enable_pch_transcoder(dev_priv, pipe);
3886 }
3887
3888 static void lpt_pch_enable(struct drm_crtc *crtc)
3889 {
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3894
3895 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3896
3897 lpt_program_iclkip(crtc);
3898
3899 /* Set transcoder timing. */
3900 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3901
3902 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3903 }
3904
3905 void intel_put_shared_dpll(struct intel_crtc *crtc)
3906 {
3907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3908
3909 if (pll == NULL)
3910 return;
3911
3912 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3913 WARN(1, "bad %s crtc mask\n", pll->name);
3914 return;
3915 }
3916
3917 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3918 if (pll->config.crtc_mask == 0) {
3919 WARN_ON(pll->on);
3920 WARN_ON(pll->active);
3921 }
3922
3923 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3924 }
3925
3926 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3927 {
3928 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3929 struct intel_shared_dpll *pll;
3930 enum intel_dpll_id i;
3931
3932 if (HAS_PCH_IBX(dev_priv->dev)) {
3933 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3934 i = (enum intel_dpll_id) crtc->pipe;
3935 pll = &dev_priv->shared_dplls[i];
3936
3937 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3938 crtc->base.base.id, pll->name);
3939
3940 WARN_ON(pll->new_config->crtc_mask);
3941
3942 goto found;
3943 }
3944
3945 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3946 pll = &dev_priv->shared_dplls[i];
3947
3948 /* Only want to check enabled timings first */
3949 if (pll->new_config->crtc_mask == 0)
3950 continue;
3951
3952 if (memcmp(&crtc->new_config->dpll_hw_state,
3953 &pll->new_config->hw_state,
3954 sizeof(pll->new_config->hw_state)) == 0) {
3955 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3956 crtc->base.base.id, pll->name,
3957 pll->new_config->crtc_mask,
3958 pll->active);
3959 goto found;
3960 }
3961 }
3962
3963 /* Ok no matching timings, maybe there's a free one? */
3964 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3965 pll = &dev_priv->shared_dplls[i];
3966 if (pll->new_config->crtc_mask == 0) {
3967 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3968 crtc->base.base.id, pll->name);
3969 goto found;
3970 }
3971 }
3972
3973 return NULL;
3974
3975 found:
3976 if (pll->new_config->crtc_mask == 0)
3977 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3978
3979 crtc->new_config->shared_dpll = i;
3980 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3981 pipe_name(crtc->pipe));
3982
3983 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3984
3985 return pll;
3986 }
3987
3988 /**
3989 * intel_shared_dpll_start_config - start a new PLL staged config
3990 * @dev_priv: DRM device
3991 * @clear_pipes: mask of pipes that will have their PLLs freed
3992 *
3993 * Starts a new PLL staged config, copying the current config but
3994 * releasing the references of pipes specified in clear_pipes.
3995 */
3996 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3997 unsigned clear_pipes)
3998 {
3999 struct intel_shared_dpll *pll;
4000 enum intel_dpll_id i;
4001
4002 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4003 pll = &dev_priv->shared_dplls[i];
4004
4005 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4006 GFP_KERNEL);
4007 if (!pll->new_config)
4008 goto cleanup;
4009
4010 pll->new_config->crtc_mask &= ~clear_pipes;
4011 }
4012
4013 return 0;
4014
4015 cleanup:
4016 while (--i >= 0) {
4017 pll = &dev_priv->shared_dplls[i];
4018 kfree(pll->new_config);
4019 pll->new_config = NULL;
4020 }
4021
4022 return -ENOMEM;
4023 }
4024
4025 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4026 {
4027 struct intel_shared_dpll *pll;
4028 enum intel_dpll_id i;
4029
4030 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4031 pll = &dev_priv->shared_dplls[i];
4032
4033 WARN_ON(pll->new_config == &pll->config);
4034
4035 pll->config = *pll->new_config;
4036 kfree(pll->new_config);
4037 pll->new_config = NULL;
4038 }
4039 }
4040
4041 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4042 {
4043 struct intel_shared_dpll *pll;
4044 enum intel_dpll_id i;
4045
4046 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4047 pll = &dev_priv->shared_dplls[i];
4048
4049 WARN_ON(pll->new_config == &pll->config);
4050
4051 kfree(pll->new_config);
4052 pll->new_config = NULL;
4053 }
4054 }
4055
4056 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4057 {
4058 struct drm_i915_private *dev_priv = dev->dev_private;
4059 int dslreg = PIPEDSL(pipe);
4060 u32 temp;
4061
4062 temp = I915_READ(dslreg);
4063 udelay(500);
4064 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4065 if (wait_for(I915_READ(dslreg) != temp, 5))
4066 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4067 }
4068 }
4069
4070 static void skylake_pfit_enable(struct intel_crtc *crtc)
4071 {
4072 struct drm_device *dev = crtc->base.dev;
4073 struct drm_i915_private *dev_priv = dev->dev_private;
4074 int pipe = crtc->pipe;
4075
4076 if (crtc->config.pch_pfit.enabled) {
4077 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4078 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4079 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4080 }
4081 }
4082
4083 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4084 {
4085 struct drm_device *dev = crtc->base.dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 int pipe = crtc->pipe;
4088
4089 if (crtc->config.pch_pfit.enabled) {
4090 /* Force use of hard-coded filter coefficients
4091 * as some pre-programmed values are broken,
4092 * e.g. x201.
4093 */
4094 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4095 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4096 PF_PIPE_SEL_IVB(pipe));
4097 else
4098 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4099 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4100 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4101 }
4102 }
4103
4104 static void intel_enable_planes(struct drm_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->dev;
4107 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4108 struct drm_plane *plane;
4109 struct intel_plane *intel_plane;
4110
4111 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4112 intel_plane = to_intel_plane(plane);
4113 if (intel_plane->pipe == pipe)
4114 intel_plane_restore(&intel_plane->base);
4115 }
4116 }
4117
4118 static void intel_disable_planes(struct drm_crtc *crtc)
4119 {
4120 struct drm_device *dev = crtc->dev;
4121 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4122 struct drm_plane *plane;
4123 struct intel_plane *intel_plane;
4124
4125 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4126 intel_plane = to_intel_plane(plane);
4127 if (intel_plane->pipe == pipe)
4128 intel_plane_disable(&intel_plane->base);
4129 }
4130 }
4131
4132 void hsw_enable_ips(struct intel_crtc *crtc)
4133 {
4134 struct drm_device *dev = crtc->base.dev;
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4136
4137 if (!crtc->config.ips_enabled)
4138 return;
4139
4140 /* We can only enable IPS after we enable a plane and wait for a vblank */
4141 intel_wait_for_vblank(dev, crtc->pipe);
4142
4143 assert_plane_enabled(dev_priv, crtc->plane);
4144 if (IS_BROADWELL(dev)) {
4145 mutex_lock(&dev_priv->rps.hw_lock);
4146 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4147 mutex_unlock(&dev_priv->rps.hw_lock);
4148 /* Quoting Art Runyan: "its not safe to expect any particular
4149 * value in IPS_CTL bit 31 after enabling IPS through the
4150 * mailbox." Moreover, the mailbox may return a bogus state,
4151 * so we need to just enable it and continue on.
4152 */
4153 } else {
4154 I915_WRITE(IPS_CTL, IPS_ENABLE);
4155 /* The bit only becomes 1 in the next vblank, so this wait here
4156 * is essentially intel_wait_for_vblank. If we don't have this
4157 * and don't wait for vblanks until the end of crtc_enable, then
4158 * the HW state readout code will complain that the expected
4159 * IPS_CTL value is not the one we read. */
4160 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4161 DRM_ERROR("Timed out waiting for IPS enable\n");
4162 }
4163 }
4164
4165 void hsw_disable_ips(struct intel_crtc *crtc)
4166 {
4167 struct drm_device *dev = crtc->base.dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169
4170 if (!crtc->config.ips_enabled)
4171 return;
4172
4173 assert_plane_enabled(dev_priv, crtc->plane);
4174 if (IS_BROADWELL(dev)) {
4175 mutex_lock(&dev_priv->rps.hw_lock);
4176 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4177 mutex_unlock(&dev_priv->rps.hw_lock);
4178 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4179 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4180 DRM_ERROR("Timed out waiting for IPS disable\n");
4181 } else {
4182 I915_WRITE(IPS_CTL, 0);
4183 POSTING_READ(IPS_CTL);
4184 }
4185
4186 /* We need to wait for a vblank before we can disable the plane. */
4187 intel_wait_for_vblank(dev, crtc->pipe);
4188 }
4189
4190 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4191 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4192 {
4193 struct drm_device *dev = crtc->dev;
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196 enum pipe pipe = intel_crtc->pipe;
4197 int palreg = PALETTE(pipe);
4198 int i;
4199 bool reenable_ips = false;
4200
4201 /* The clocks have to be on to load the palette. */
4202 if (!crtc->enabled || !intel_crtc->active)
4203 return;
4204
4205 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4206 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4207 assert_dsi_pll_enabled(dev_priv);
4208 else
4209 assert_pll_enabled(dev_priv, pipe);
4210 }
4211
4212 /* use legacy palette for Ironlake */
4213 if (!HAS_GMCH_DISPLAY(dev))
4214 palreg = LGC_PALETTE(pipe);
4215
4216 /* Workaround : Do not read or write the pipe palette/gamma data while
4217 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4218 */
4219 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4220 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4221 GAMMA_MODE_MODE_SPLIT)) {
4222 hsw_disable_ips(intel_crtc);
4223 reenable_ips = true;
4224 }
4225
4226 for (i = 0; i < 256; i++) {
4227 I915_WRITE(palreg + 4 * i,
4228 (intel_crtc->lut_r[i] << 16) |
4229 (intel_crtc->lut_g[i] << 8) |
4230 intel_crtc->lut_b[i]);
4231 }
4232
4233 if (reenable_ips)
4234 hsw_enable_ips(intel_crtc);
4235 }
4236
4237 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4238 {
4239 if (!enable && intel_crtc->overlay) {
4240 struct drm_device *dev = intel_crtc->base.dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242
4243 mutex_lock(&dev->struct_mutex);
4244 dev_priv->mm.interruptible = false;
4245 (void) intel_overlay_switch_off(intel_crtc->overlay);
4246 dev_priv->mm.interruptible = true;
4247 mutex_unlock(&dev->struct_mutex);
4248 }
4249
4250 /* Let userspace switch the overlay on again. In most cases userspace
4251 * has to recompute where to put it anyway.
4252 */
4253 }
4254
4255 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4256 {
4257 struct drm_device *dev = crtc->dev;
4258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4259 int pipe = intel_crtc->pipe;
4260
4261 intel_enable_primary_hw_plane(crtc->primary, crtc);
4262 intel_enable_planes(crtc);
4263 intel_crtc_update_cursor(crtc, true);
4264 intel_crtc_dpms_overlay(intel_crtc, true);
4265
4266 hsw_enable_ips(intel_crtc);
4267
4268 mutex_lock(&dev->struct_mutex);
4269 intel_update_fbc(dev);
4270 mutex_unlock(&dev->struct_mutex);
4271
4272 /*
4273 * FIXME: Once we grow proper nuclear flip support out of this we need
4274 * to compute the mask of flip planes precisely. For the time being
4275 * consider this a flip from a NULL plane.
4276 */
4277 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4278 }
4279
4280 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4281 {
4282 struct drm_device *dev = crtc->dev;
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285 int pipe = intel_crtc->pipe;
4286 int plane = intel_crtc->plane;
4287
4288 intel_crtc_wait_for_pending_flips(crtc);
4289
4290 if (dev_priv->fbc.plane == plane)
4291 intel_disable_fbc(dev);
4292
4293 hsw_disable_ips(intel_crtc);
4294
4295 intel_crtc_dpms_overlay(intel_crtc, false);
4296 intel_crtc_update_cursor(crtc, false);
4297 intel_disable_planes(crtc);
4298 intel_disable_primary_hw_plane(crtc->primary, crtc);
4299
4300 /*
4301 * FIXME: Once we grow proper nuclear flip support out of this we need
4302 * to compute the mask of flip planes precisely. For the time being
4303 * consider this a flip to a NULL plane.
4304 */
4305 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4306 }
4307
4308 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4309 {
4310 struct drm_device *dev = crtc->dev;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313 struct intel_encoder *encoder;
4314 int pipe = intel_crtc->pipe;
4315
4316 WARN_ON(!crtc->enabled);
4317
4318 if (intel_crtc->active)
4319 return;
4320
4321 if (intel_crtc->config.has_pch_encoder)
4322 intel_prepare_shared_dpll(intel_crtc);
4323
4324 if (intel_crtc->config.has_dp_encoder)
4325 intel_dp_set_m_n(intel_crtc);
4326
4327 intel_set_pipe_timings(intel_crtc);
4328
4329 if (intel_crtc->config.has_pch_encoder) {
4330 intel_cpu_transcoder_set_m_n(intel_crtc,
4331 &intel_crtc->config.fdi_m_n, NULL);
4332 }
4333
4334 ironlake_set_pipeconf(crtc);
4335
4336 intel_crtc->active = true;
4337
4338 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4339 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4340
4341 for_each_encoder_on_crtc(dev, crtc, encoder)
4342 if (encoder->pre_enable)
4343 encoder->pre_enable(encoder);
4344
4345 if (intel_crtc->config.has_pch_encoder) {
4346 /* Note: FDI PLL enabling _must_ be done before we enable the
4347 * cpu pipes, hence this is separate from all the other fdi/pch
4348 * enabling. */
4349 ironlake_fdi_pll_enable(intel_crtc);
4350 } else {
4351 assert_fdi_tx_disabled(dev_priv, pipe);
4352 assert_fdi_rx_disabled(dev_priv, pipe);
4353 }
4354
4355 ironlake_pfit_enable(intel_crtc);
4356
4357 /*
4358 * On ILK+ LUT must be loaded before the pipe is running but with
4359 * clocks enabled
4360 */
4361 intel_crtc_load_lut(crtc);
4362
4363 intel_update_watermarks(crtc);
4364 intel_enable_pipe(intel_crtc);
4365
4366 if (intel_crtc->config.has_pch_encoder)
4367 ironlake_pch_enable(crtc);
4368
4369 for_each_encoder_on_crtc(dev, crtc, encoder)
4370 encoder->enable(encoder);
4371
4372 if (HAS_PCH_CPT(dev))
4373 cpt_verify_modeset(dev, intel_crtc->pipe);
4374
4375 assert_vblank_disabled(crtc);
4376 drm_crtc_vblank_on(crtc);
4377
4378 intel_crtc_enable_planes(crtc);
4379 }
4380
4381 /* IPS only exists on ULT machines and is tied to pipe A. */
4382 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4383 {
4384 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4385 }
4386
4387 /*
4388 * This implements the workaround described in the "notes" section of the mode
4389 * set sequence documentation. When going from no pipes or single pipe to
4390 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4391 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4392 */
4393 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4394 {
4395 struct drm_device *dev = crtc->base.dev;
4396 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4397
4398 /* We want to get the other_active_crtc only if there's only 1 other
4399 * active crtc. */
4400 for_each_intel_crtc(dev, crtc_it) {
4401 if (!crtc_it->active || crtc_it == crtc)
4402 continue;
4403
4404 if (other_active_crtc)
4405 return;
4406
4407 other_active_crtc = crtc_it;
4408 }
4409 if (!other_active_crtc)
4410 return;
4411
4412 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4413 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4414 }
4415
4416 static void haswell_crtc_enable(struct drm_crtc *crtc)
4417 {
4418 struct drm_device *dev = crtc->dev;
4419 struct drm_i915_private *dev_priv = dev->dev_private;
4420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4421 struct intel_encoder *encoder;
4422 int pipe = intel_crtc->pipe;
4423
4424 WARN_ON(!crtc->enabled);
4425
4426 if (intel_crtc->active)
4427 return;
4428
4429 if (intel_crtc_to_shared_dpll(intel_crtc))
4430 intel_enable_shared_dpll(intel_crtc);
4431
4432 if (intel_crtc->config.has_dp_encoder)
4433 intel_dp_set_m_n(intel_crtc);
4434
4435 intel_set_pipe_timings(intel_crtc);
4436
4437 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4438 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4439 intel_crtc->config.pixel_multiplier - 1);
4440 }
4441
4442 if (intel_crtc->config.has_pch_encoder) {
4443 intel_cpu_transcoder_set_m_n(intel_crtc,
4444 &intel_crtc->config.fdi_m_n, NULL);
4445 }
4446
4447 haswell_set_pipeconf(crtc);
4448
4449 intel_set_pipe_csc(crtc);
4450
4451 intel_crtc->active = true;
4452
4453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4454 for_each_encoder_on_crtc(dev, crtc, encoder)
4455 if (encoder->pre_enable)
4456 encoder->pre_enable(encoder);
4457
4458 if (intel_crtc->config.has_pch_encoder) {
4459 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4460 true);
4461 dev_priv->display.fdi_link_train(crtc);
4462 }
4463
4464 intel_ddi_enable_pipe_clock(intel_crtc);
4465
4466 if (IS_SKYLAKE(dev))
4467 skylake_pfit_enable(intel_crtc);
4468 else
4469 ironlake_pfit_enable(intel_crtc);
4470
4471 /*
4472 * On ILK+ LUT must be loaded before the pipe is running but with
4473 * clocks enabled
4474 */
4475 intel_crtc_load_lut(crtc);
4476
4477 intel_ddi_set_pipe_settings(crtc);
4478 intel_ddi_enable_transcoder_func(crtc);
4479
4480 intel_update_watermarks(crtc);
4481 intel_enable_pipe(intel_crtc);
4482
4483 if (intel_crtc->config.has_pch_encoder)
4484 lpt_pch_enable(crtc);
4485
4486 if (intel_crtc->config.dp_encoder_is_mst)
4487 intel_ddi_set_vc_payload_alloc(crtc, true);
4488
4489 for_each_encoder_on_crtc(dev, crtc, encoder) {
4490 encoder->enable(encoder);
4491 intel_opregion_notify_encoder(encoder, true);
4492 }
4493
4494 assert_vblank_disabled(crtc);
4495 drm_crtc_vblank_on(crtc);
4496
4497 /* If we change the relative order between pipe/planes enabling, we need
4498 * to change the workaround. */
4499 haswell_mode_set_planes_workaround(intel_crtc);
4500 intel_crtc_enable_planes(crtc);
4501 }
4502
4503 static void skylake_pfit_disable(struct intel_crtc *crtc)
4504 {
4505 struct drm_device *dev = crtc->base.dev;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507 int pipe = crtc->pipe;
4508
4509 /* To avoid upsetting the power well on haswell only disable the pfit if
4510 * it's in use. The hw state code will make sure we get this right. */
4511 if (crtc->config.pch_pfit.enabled) {
4512 I915_WRITE(PS_CTL(pipe), 0);
4513 I915_WRITE(PS_WIN_POS(pipe), 0);
4514 I915_WRITE(PS_WIN_SZ(pipe), 0);
4515 }
4516 }
4517
4518 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4519 {
4520 struct drm_device *dev = crtc->base.dev;
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522 int pipe = crtc->pipe;
4523
4524 /* To avoid upsetting the power well on haswell only disable the pfit if
4525 * it's in use. The hw state code will make sure we get this right. */
4526 if (crtc->config.pch_pfit.enabled) {
4527 I915_WRITE(PF_CTL(pipe), 0);
4528 I915_WRITE(PF_WIN_POS(pipe), 0);
4529 I915_WRITE(PF_WIN_SZ(pipe), 0);
4530 }
4531 }
4532
4533 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4534 {
4535 struct drm_device *dev = crtc->dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538 struct intel_encoder *encoder;
4539 int pipe = intel_crtc->pipe;
4540 u32 reg, temp;
4541
4542 if (!intel_crtc->active)
4543 return;
4544
4545 intel_crtc_disable_planes(crtc);
4546
4547 drm_crtc_vblank_off(crtc);
4548 assert_vblank_disabled(crtc);
4549
4550 for_each_encoder_on_crtc(dev, crtc, encoder)
4551 encoder->disable(encoder);
4552
4553 if (intel_crtc->config.has_pch_encoder)
4554 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4555
4556 intel_disable_pipe(intel_crtc);
4557
4558 ironlake_pfit_disable(intel_crtc);
4559
4560 for_each_encoder_on_crtc(dev, crtc, encoder)
4561 if (encoder->post_disable)
4562 encoder->post_disable(encoder);
4563
4564 if (intel_crtc->config.has_pch_encoder) {
4565 ironlake_fdi_disable(crtc);
4566
4567 ironlake_disable_pch_transcoder(dev_priv, pipe);
4568 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4569
4570 if (HAS_PCH_CPT(dev)) {
4571 /* disable TRANS_DP_CTL */
4572 reg = TRANS_DP_CTL(pipe);
4573 temp = I915_READ(reg);
4574 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4575 TRANS_DP_PORT_SEL_MASK);
4576 temp |= TRANS_DP_PORT_SEL_NONE;
4577 I915_WRITE(reg, temp);
4578
4579 /* disable DPLL_SEL */
4580 temp = I915_READ(PCH_DPLL_SEL);
4581 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4582 I915_WRITE(PCH_DPLL_SEL, temp);
4583 }
4584
4585 /* disable PCH DPLL */
4586 intel_disable_shared_dpll(intel_crtc);
4587
4588 ironlake_fdi_pll_disable(intel_crtc);
4589 }
4590
4591 intel_crtc->active = false;
4592 intel_update_watermarks(crtc);
4593
4594 mutex_lock(&dev->struct_mutex);
4595 intel_update_fbc(dev);
4596 mutex_unlock(&dev->struct_mutex);
4597 }
4598
4599 static void haswell_crtc_disable(struct drm_crtc *crtc)
4600 {
4601 struct drm_device *dev = crtc->dev;
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4604 struct intel_encoder *encoder;
4605 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4606
4607 if (!intel_crtc->active)
4608 return;
4609
4610 intel_crtc_disable_planes(crtc);
4611
4612 drm_crtc_vblank_off(crtc);
4613 assert_vblank_disabled(crtc);
4614
4615 for_each_encoder_on_crtc(dev, crtc, encoder) {
4616 intel_opregion_notify_encoder(encoder, false);
4617 encoder->disable(encoder);
4618 }
4619
4620 if (intel_crtc->config.has_pch_encoder)
4621 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4622 false);
4623 intel_disable_pipe(intel_crtc);
4624
4625 if (intel_crtc->config.dp_encoder_is_mst)
4626 intel_ddi_set_vc_payload_alloc(crtc, false);
4627
4628 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4629
4630 if (IS_SKYLAKE(dev))
4631 skylake_pfit_disable(intel_crtc);
4632 else
4633 ironlake_pfit_disable(intel_crtc);
4634
4635 intel_ddi_disable_pipe_clock(intel_crtc);
4636
4637 if (intel_crtc->config.has_pch_encoder) {
4638 lpt_disable_pch_transcoder(dev_priv);
4639 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4640 true);
4641 intel_ddi_fdi_disable(crtc);
4642 }
4643
4644 for_each_encoder_on_crtc(dev, crtc, encoder)
4645 if (encoder->post_disable)
4646 encoder->post_disable(encoder);
4647
4648 intel_crtc->active = false;
4649 intel_update_watermarks(crtc);
4650
4651 mutex_lock(&dev->struct_mutex);
4652 intel_update_fbc(dev);
4653 mutex_unlock(&dev->struct_mutex);
4654
4655 if (intel_crtc_to_shared_dpll(intel_crtc))
4656 intel_disable_shared_dpll(intel_crtc);
4657 }
4658
4659 static void ironlake_crtc_off(struct drm_crtc *crtc)
4660 {
4661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4662 intel_put_shared_dpll(intel_crtc);
4663 }
4664
4665
4666 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4667 {
4668 struct drm_device *dev = crtc->base.dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670 struct intel_crtc_config *pipe_config = &crtc->config;
4671
4672 if (!crtc->config.gmch_pfit.control)
4673 return;
4674
4675 /*
4676 * The panel fitter should only be adjusted whilst the pipe is disabled,
4677 * according to register description and PRM.
4678 */
4679 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4680 assert_pipe_disabled(dev_priv, crtc->pipe);
4681
4682 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4683 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4684
4685 /* Border color in case we don't scale up to the full screen. Black by
4686 * default, change to something else for debugging. */
4687 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4688 }
4689
4690 static enum intel_display_power_domain port_to_power_domain(enum port port)
4691 {
4692 switch (port) {
4693 case PORT_A:
4694 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4695 case PORT_B:
4696 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4697 case PORT_C:
4698 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4699 case PORT_D:
4700 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4701 default:
4702 WARN_ON_ONCE(1);
4703 return POWER_DOMAIN_PORT_OTHER;
4704 }
4705 }
4706
4707 #define for_each_power_domain(domain, mask) \
4708 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4709 if ((1 << (domain)) & (mask))
4710
4711 enum intel_display_power_domain
4712 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4713 {
4714 struct drm_device *dev = intel_encoder->base.dev;
4715 struct intel_digital_port *intel_dig_port;
4716
4717 switch (intel_encoder->type) {
4718 case INTEL_OUTPUT_UNKNOWN:
4719 /* Only DDI platforms should ever use this output type */
4720 WARN_ON_ONCE(!HAS_DDI(dev));
4721 case INTEL_OUTPUT_DISPLAYPORT:
4722 case INTEL_OUTPUT_HDMI:
4723 case INTEL_OUTPUT_EDP:
4724 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4725 return port_to_power_domain(intel_dig_port->port);
4726 case INTEL_OUTPUT_DP_MST:
4727 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4728 return port_to_power_domain(intel_dig_port->port);
4729 case INTEL_OUTPUT_ANALOG:
4730 return POWER_DOMAIN_PORT_CRT;
4731 case INTEL_OUTPUT_DSI:
4732 return POWER_DOMAIN_PORT_DSI;
4733 default:
4734 return POWER_DOMAIN_PORT_OTHER;
4735 }
4736 }
4737
4738 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4739 {
4740 struct drm_device *dev = crtc->dev;
4741 struct intel_encoder *intel_encoder;
4742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4743 enum pipe pipe = intel_crtc->pipe;
4744 unsigned long mask;
4745 enum transcoder transcoder;
4746
4747 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4748
4749 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4750 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4751 if (intel_crtc->config.pch_pfit.enabled ||
4752 intel_crtc->config.pch_pfit.force_thru)
4753 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4754
4755 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4756 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4757
4758 return mask;
4759 }
4760
4761 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4762 {
4763 struct drm_i915_private *dev_priv = dev->dev_private;
4764 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4765 struct intel_crtc *crtc;
4766
4767 /*
4768 * First get all needed power domains, then put all unneeded, to avoid
4769 * any unnecessary toggling of the power wells.
4770 */
4771 for_each_intel_crtc(dev, crtc) {
4772 enum intel_display_power_domain domain;
4773
4774 if (!crtc->base.enabled)
4775 continue;
4776
4777 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4778
4779 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4780 intel_display_power_get(dev_priv, domain);
4781 }
4782
4783 if (dev_priv->display.modeset_global_resources)
4784 dev_priv->display.modeset_global_resources(dev);
4785
4786 for_each_intel_crtc(dev, crtc) {
4787 enum intel_display_power_domain domain;
4788
4789 for_each_power_domain(domain, crtc->enabled_power_domains)
4790 intel_display_power_put(dev_priv, domain);
4791
4792 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4793 }
4794
4795 intel_display_set_init_power(dev_priv, false);
4796 }
4797
4798 /* returns HPLL frequency in kHz */
4799 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4800 {
4801 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4802
4803 /* Obtain SKU information */
4804 mutex_lock(&dev_priv->dpio_lock);
4805 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4806 CCK_FUSE_HPLL_FREQ_MASK;
4807 mutex_unlock(&dev_priv->dpio_lock);
4808
4809 return vco_freq[hpll_freq] * 1000;
4810 }
4811
4812 static void vlv_update_cdclk(struct drm_device *dev)
4813 {
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815
4816 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4817 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4818 dev_priv->vlv_cdclk_freq);
4819
4820 /*
4821 * Program the gmbus_freq based on the cdclk frequency.
4822 * BSpec erroneously claims we should aim for 4MHz, but
4823 * in fact 1MHz is the correct frequency.
4824 */
4825 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4826 }
4827
4828 /* Adjust CDclk dividers to allow high res or save power if possible */
4829 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4830 {
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 u32 val, cmd;
4833
4834 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4835
4836 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4837 cmd = 2;
4838 else if (cdclk == 266667)
4839 cmd = 1;
4840 else
4841 cmd = 0;
4842
4843 mutex_lock(&dev_priv->rps.hw_lock);
4844 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4845 val &= ~DSPFREQGUAR_MASK;
4846 val |= (cmd << DSPFREQGUAR_SHIFT);
4847 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4848 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4849 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4850 50)) {
4851 DRM_ERROR("timed out waiting for CDclk change\n");
4852 }
4853 mutex_unlock(&dev_priv->rps.hw_lock);
4854
4855 if (cdclk == 400000) {
4856 u32 divider;
4857
4858 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4859
4860 mutex_lock(&dev_priv->dpio_lock);
4861 /* adjust cdclk divider */
4862 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4863 val &= ~DISPLAY_FREQUENCY_VALUES;
4864 val |= divider;
4865 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4866
4867 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4868 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4869 50))
4870 DRM_ERROR("timed out waiting for CDclk change\n");
4871 mutex_unlock(&dev_priv->dpio_lock);
4872 }
4873
4874 mutex_lock(&dev_priv->dpio_lock);
4875 /* adjust self-refresh exit latency value */
4876 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4877 val &= ~0x7f;
4878
4879 /*
4880 * For high bandwidth configs, we set a higher latency in the bunit
4881 * so that the core display fetch happens in time to avoid underruns.
4882 */
4883 if (cdclk == 400000)
4884 val |= 4500 / 250; /* 4.5 usec */
4885 else
4886 val |= 3000 / 250; /* 3.0 usec */
4887 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4888 mutex_unlock(&dev_priv->dpio_lock);
4889
4890 vlv_update_cdclk(dev);
4891 }
4892
4893 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4894 {
4895 struct drm_i915_private *dev_priv = dev->dev_private;
4896 u32 val, cmd;
4897
4898 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4899
4900 switch (cdclk) {
4901 case 400000:
4902 cmd = 3;
4903 break;
4904 case 333333:
4905 case 320000:
4906 cmd = 2;
4907 break;
4908 case 266667:
4909 cmd = 1;
4910 break;
4911 case 200000:
4912 cmd = 0;
4913 break;
4914 default:
4915 WARN_ON(1);
4916 return;
4917 }
4918
4919 mutex_lock(&dev_priv->rps.hw_lock);
4920 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4921 val &= ~DSPFREQGUAR_MASK_CHV;
4922 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4923 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4924 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4925 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4926 50)) {
4927 DRM_ERROR("timed out waiting for CDclk change\n");
4928 }
4929 mutex_unlock(&dev_priv->rps.hw_lock);
4930
4931 vlv_update_cdclk(dev);
4932 }
4933
4934 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4935 int max_pixclk)
4936 {
4937 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4938
4939 /* FIXME: Punit isn't quite ready yet */
4940 if (IS_CHERRYVIEW(dev_priv->dev))
4941 return 400000;
4942
4943 /*
4944 * Really only a few cases to deal with, as only 4 CDclks are supported:
4945 * 200MHz
4946 * 267MHz
4947 * 320/333MHz (depends on HPLL freq)
4948 * 400MHz
4949 * So we check to see whether we're above 90% of the lower bin and
4950 * adjust if needed.
4951 *
4952 * We seem to get an unstable or solid color picture at 200MHz.
4953 * Not sure what's wrong. For now use 200MHz only when all pipes
4954 * are off.
4955 */
4956 if (max_pixclk > freq_320*9/10)
4957 return 400000;
4958 else if (max_pixclk > 266667*9/10)
4959 return freq_320;
4960 else if (max_pixclk > 0)
4961 return 266667;
4962 else
4963 return 200000;
4964 }
4965
4966 /* compute the max pixel clock for new configuration */
4967 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4968 {
4969 struct drm_device *dev = dev_priv->dev;
4970 struct intel_crtc *intel_crtc;
4971 int max_pixclk = 0;
4972
4973 for_each_intel_crtc(dev, intel_crtc) {
4974 if (intel_crtc->new_enabled)
4975 max_pixclk = max(max_pixclk,
4976 intel_crtc->new_config->adjusted_mode.crtc_clock);
4977 }
4978
4979 return max_pixclk;
4980 }
4981
4982 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4983 unsigned *prepare_pipes)
4984 {
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 struct intel_crtc *intel_crtc;
4987 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4988
4989 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4990 dev_priv->vlv_cdclk_freq)
4991 return;
4992
4993 /* disable/enable all currently active pipes while we change cdclk */
4994 for_each_intel_crtc(dev, intel_crtc)
4995 if (intel_crtc->base.enabled)
4996 *prepare_pipes |= (1 << intel_crtc->pipe);
4997 }
4998
4999 static void valleyview_modeset_global_resources(struct drm_device *dev)
5000 {
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5003 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5004
5005 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5006 /*
5007 * FIXME: We can end up here with all power domains off, yet
5008 * with a CDCLK frequency other than the minimum. To account
5009 * for this take the PIPE-A power domain, which covers the HW
5010 * blocks needed for the following programming. This can be
5011 * removed once it's guaranteed that we get here either with
5012 * the minimum CDCLK set, or the required power domains
5013 * enabled.
5014 */
5015 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5016
5017 if (IS_CHERRYVIEW(dev))
5018 cherryview_set_cdclk(dev, req_cdclk);
5019 else
5020 valleyview_set_cdclk(dev, req_cdclk);
5021
5022 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5023 }
5024 }
5025
5026 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5027 {
5028 struct drm_device *dev = crtc->dev;
5029 struct drm_i915_private *dev_priv = to_i915(dev);
5030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031 struct intel_encoder *encoder;
5032 int pipe = intel_crtc->pipe;
5033 bool is_dsi;
5034
5035 WARN_ON(!crtc->enabled);
5036
5037 if (intel_crtc->active)
5038 return;
5039
5040 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5041
5042 if (!is_dsi) {
5043 if (IS_CHERRYVIEW(dev))
5044 chv_prepare_pll(intel_crtc, &intel_crtc->config);
5045 else
5046 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
5047 }
5048
5049 if (intel_crtc->config.has_dp_encoder)
5050 intel_dp_set_m_n(intel_crtc);
5051
5052 intel_set_pipe_timings(intel_crtc);
5053
5054 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5055 struct drm_i915_private *dev_priv = dev->dev_private;
5056
5057 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5058 I915_WRITE(CHV_CANVAS(pipe), 0);
5059 }
5060
5061 i9xx_set_pipeconf(intel_crtc);
5062
5063 intel_crtc->active = true;
5064
5065 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5066
5067 for_each_encoder_on_crtc(dev, crtc, encoder)
5068 if (encoder->pre_pll_enable)
5069 encoder->pre_pll_enable(encoder);
5070
5071 if (!is_dsi) {
5072 if (IS_CHERRYVIEW(dev))
5073 chv_enable_pll(intel_crtc, &intel_crtc->config);
5074 else
5075 vlv_enable_pll(intel_crtc, &intel_crtc->config);
5076 }
5077
5078 for_each_encoder_on_crtc(dev, crtc, encoder)
5079 if (encoder->pre_enable)
5080 encoder->pre_enable(encoder);
5081
5082 i9xx_pfit_enable(intel_crtc);
5083
5084 intel_crtc_load_lut(crtc);
5085
5086 intel_update_watermarks(crtc);
5087 intel_enable_pipe(intel_crtc);
5088
5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 encoder->enable(encoder);
5091
5092 assert_vblank_disabled(crtc);
5093 drm_crtc_vblank_on(crtc);
5094
5095 intel_crtc_enable_planes(crtc);
5096
5097 /* Underruns don't raise interrupts, so check manually. */
5098 i9xx_check_fifo_underruns(dev_priv);
5099 }
5100
5101 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5102 {
5103 struct drm_device *dev = crtc->base.dev;
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5105
5106 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
5107 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5108 }
5109
5110 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5111 {
5112 struct drm_device *dev = crtc->dev;
5113 struct drm_i915_private *dev_priv = to_i915(dev);
5114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115 struct intel_encoder *encoder;
5116 int pipe = intel_crtc->pipe;
5117
5118 WARN_ON(!crtc->enabled);
5119
5120 if (intel_crtc->active)
5121 return;
5122
5123 i9xx_set_pll_dividers(intel_crtc);
5124
5125 if (intel_crtc->config.has_dp_encoder)
5126 intel_dp_set_m_n(intel_crtc);
5127
5128 intel_set_pipe_timings(intel_crtc);
5129
5130 i9xx_set_pipeconf(intel_crtc);
5131
5132 intel_crtc->active = true;
5133
5134 if (!IS_GEN2(dev))
5135 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5136
5137 for_each_encoder_on_crtc(dev, crtc, encoder)
5138 if (encoder->pre_enable)
5139 encoder->pre_enable(encoder);
5140
5141 i9xx_enable_pll(intel_crtc);
5142
5143 i9xx_pfit_enable(intel_crtc);
5144
5145 intel_crtc_load_lut(crtc);
5146
5147 intel_update_watermarks(crtc);
5148 intel_enable_pipe(intel_crtc);
5149
5150 for_each_encoder_on_crtc(dev, crtc, encoder)
5151 encoder->enable(encoder);
5152
5153 assert_vblank_disabled(crtc);
5154 drm_crtc_vblank_on(crtc);
5155
5156 intel_crtc_enable_planes(crtc);
5157
5158 /*
5159 * Gen2 reports pipe underruns whenever all planes are disabled.
5160 * So don't enable underrun reporting before at least some planes
5161 * are enabled.
5162 * FIXME: Need to fix the logic to work when we turn off all planes
5163 * but leave the pipe running.
5164 */
5165 if (IS_GEN2(dev))
5166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5167
5168 /* Underruns don't raise interrupts, so check manually. */
5169 i9xx_check_fifo_underruns(dev_priv);
5170 }
5171
5172 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5173 {
5174 struct drm_device *dev = crtc->base.dev;
5175 struct drm_i915_private *dev_priv = dev->dev_private;
5176
5177 if (!crtc->config.gmch_pfit.control)
5178 return;
5179
5180 assert_pipe_disabled(dev_priv, crtc->pipe);
5181
5182 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5183 I915_READ(PFIT_CONTROL));
5184 I915_WRITE(PFIT_CONTROL, 0);
5185 }
5186
5187 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5188 {
5189 struct drm_device *dev = crtc->dev;
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5192 struct intel_encoder *encoder;
5193 int pipe = intel_crtc->pipe;
5194
5195 if (!intel_crtc->active)
5196 return;
5197
5198 /*
5199 * Gen2 reports pipe underruns whenever all planes are disabled.
5200 * So diasble underrun reporting before all the planes get disabled.
5201 * FIXME: Need to fix the logic to work when we turn off all planes
5202 * but leave the pipe running.
5203 */
5204 if (IS_GEN2(dev))
5205 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5206
5207 /*
5208 * Vblank time updates from the shadow to live plane control register
5209 * are blocked if the memory self-refresh mode is active at that
5210 * moment. So to make sure the plane gets truly disabled, disable
5211 * first the self-refresh mode. The self-refresh enable bit in turn
5212 * will be checked/applied by the HW only at the next frame start
5213 * event which is after the vblank start event, so we need to have a
5214 * wait-for-vblank between disabling the plane and the pipe.
5215 */
5216 intel_set_memory_cxsr(dev_priv, false);
5217 intel_crtc_disable_planes(crtc);
5218
5219 /*
5220 * On gen2 planes are double buffered but the pipe isn't, so we must
5221 * wait for planes to fully turn off before disabling the pipe.
5222 * We also need to wait on all gmch platforms because of the
5223 * self-refresh mode constraint explained above.
5224 */
5225 intel_wait_for_vblank(dev, pipe);
5226
5227 drm_crtc_vblank_off(crtc);
5228 assert_vblank_disabled(crtc);
5229
5230 for_each_encoder_on_crtc(dev, crtc, encoder)
5231 encoder->disable(encoder);
5232
5233 intel_disable_pipe(intel_crtc);
5234
5235 i9xx_pfit_disable(intel_crtc);
5236
5237 for_each_encoder_on_crtc(dev, crtc, encoder)
5238 if (encoder->post_disable)
5239 encoder->post_disable(encoder);
5240
5241 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5242 if (IS_CHERRYVIEW(dev))
5243 chv_disable_pll(dev_priv, pipe);
5244 else if (IS_VALLEYVIEW(dev))
5245 vlv_disable_pll(dev_priv, pipe);
5246 else
5247 i9xx_disable_pll(intel_crtc);
5248 }
5249
5250 if (!IS_GEN2(dev))
5251 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5252
5253 intel_crtc->active = false;
5254 intel_update_watermarks(crtc);
5255
5256 mutex_lock(&dev->struct_mutex);
5257 intel_update_fbc(dev);
5258 mutex_unlock(&dev->struct_mutex);
5259 }
5260
5261 static void i9xx_crtc_off(struct drm_crtc *crtc)
5262 {
5263 }
5264
5265 /* Master function to enable/disable CRTC and corresponding power wells */
5266 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5267 {
5268 struct drm_device *dev = crtc->dev;
5269 struct drm_i915_private *dev_priv = dev->dev_private;
5270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5271 enum intel_display_power_domain domain;
5272 unsigned long domains;
5273
5274 if (enable) {
5275 if (!intel_crtc->active) {
5276 domains = get_crtc_power_domains(crtc);
5277 for_each_power_domain(domain, domains)
5278 intel_display_power_get(dev_priv, domain);
5279 intel_crtc->enabled_power_domains = domains;
5280
5281 dev_priv->display.crtc_enable(crtc);
5282 }
5283 } else {
5284 if (intel_crtc->active) {
5285 dev_priv->display.crtc_disable(crtc);
5286
5287 domains = intel_crtc->enabled_power_domains;
5288 for_each_power_domain(domain, domains)
5289 intel_display_power_put(dev_priv, domain);
5290 intel_crtc->enabled_power_domains = 0;
5291 }
5292 }
5293 }
5294
5295 /**
5296 * Sets the power management mode of the pipe and plane.
5297 */
5298 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5299 {
5300 struct drm_device *dev = crtc->dev;
5301 struct intel_encoder *intel_encoder;
5302 bool enable = false;
5303
5304 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5305 enable |= intel_encoder->connectors_active;
5306
5307 intel_crtc_control(crtc, enable);
5308 }
5309
5310 static void intel_crtc_disable(struct drm_crtc *crtc)
5311 {
5312 struct drm_device *dev = crtc->dev;
5313 struct drm_connector *connector;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5316 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5317
5318 /* crtc should still be enabled when we disable it. */
5319 WARN_ON(!crtc->enabled);
5320
5321 dev_priv->display.crtc_disable(crtc);
5322 dev_priv->display.off(crtc);
5323
5324 if (crtc->primary->fb) {
5325 mutex_lock(&dev->struct_mutex);
5326 intel_unpin_fb_obj(old_obj);
5327 i915_gem_track_fb(old_obj, NULL,
5328 INTEL_FRONTBUFFER_PRIMARY(pipe));
5329 mutex_unlock(&dev->struct_mutex);
5330 crtc->primary->fb = NULL;
5331 }
5332
5333 /* Update computed state. */
5334 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5335 if (!connector->encoder || !connector->encoder->crtc)
5336 continue;
5337
5338 if (connector->encoder->crtc != crtc)
5339 continue;
5340
5341 connector->dpms = DRM_MODE_DPMS_OFF;
5342 to_intel_encoder(connector->encoder)->connectors_active = false;
5343 }
5344 }
5345
5346 void intel_encoder_destroy(struct drm_encoder *encoder)
5347 {
5348 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5349
5350 drm_encoder_cleanup(encoder);
5351 kfree(intel_encoder);
5352 }
5353
5354 /* Simple dpms helper for encoders with just one connector, no cloning and only
5355 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5356 * state of the entire output pipe. */
5357 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5358 {
5359 if (mode == DRM_MODE_DPMS_ON) {
5360 encoder->connectors_active = true;
5361
5362 intel_crtc_update_dpms(encoder->base.crtc);
5363 } else {
5364 encoder->connectors_active = false;
5365
5366 intel_crtc_update_dpms(encoder->base.crtc);
5367 }
5368 }
5369
5370 /* Cross check the actual hw state with our own modeset state tracking (and it's
5371 * internal consistency). */
5372 static void intel_connector_check_state(struct intel_connector *connector)
5373 {
5374 if (connector->get_hw_state(connector)) {
5375 struct intel_encoder *encoder = connector->encoder;
5376 struct drm_crtc *crtc;
5377 bool encoder_enabled;
5378 enum pipe pipe;
5379
5380 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5381 connector->base.base.id,
5382 connector->base.name);
5383
5384 /* there is no real hw state for MST connectors */
5385 if (connector->mst_port)
5386 return;
5387
5388 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5389 "wrong connector dpms state\n");
5390 WARN(connector->base.encoder != &encoder->base,
5391 "active connector not linked to encoder\n");
5392
5393 if (encoder) {
5394 WARN(!encoder->connectors_active,
5395 "encoder->connectors_active not set\n");
5396
5397 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5398 WARN(!encoder_enabled, "encoder not enabled\n");
5399 if (WARN_ON(!encoder->base.crtc))
5400 return;
5401
5402 crtc = encoder->base.crtc;
5403
5404 WARN(!crtc->enabled, "crtc not enabled\n");
5405 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5406 WARN(pipe != to_intel_crtc(crtc)->pipe,
5407 "encoder active on the wrong pipe\n");
5408 }
5409 }
5410 }
5411
5412 /* Even simpler default implementation, if there's really no special case to
5413 * consider. */
5414 void intel_connector_dpms(struct drm_connector *connector, int mode)
5415 {
5416 /* All the simple cases only support two dpms states. */
5417 if (mode != DRM_MODE_DPMS_ON)
5418 mode = DRM_MODE_DPMS_OFF;
5419
5420 if (mode == connector->dpms)
5421 return;
5422
5423 connector->dpms = mode;
5424
5425 /* Only need to change hw state when actually enabled */
5426 if (connector->encoder)
5427 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5428
5429 intel_modeset_check_state(connector->dev);
5430 }
5431
5432 /* Simple connector->get_hw_state implementation for encoders that support only
5433 * one connector and no cloning and hence the encoder state determines the state
5434 * of the connector. */
5435 bool intel_connector_get_hw_state(struct intel_connector *connector)
5436 {
5437 enum pipe pipe = 0;
5438 struct intel_encoder *encoder = connector->encoder;
5439
5440 return encoder->get_hw_state(encoder, &pipe);
5441 }
5442
5443 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5444 struct intel_crtc_config *pipe_config)
5445 {
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447 struct intel_crtc *pipe_B_crtc =
5448 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5449
5450 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5451 pipe_name(pipe), pipe_config->fdi_lanes);
5452 if (pipe_config->fdi_lanes > 4) {
5453 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5454 pipe_name(pipe), pipe_config->fdi_lanes);
5455 return false;
5456 }
5457
5458 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5459 if (pipe_config->fdi_lanes > 2) {
5460 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5461 pipe_config->fdi_lanes);
5462 return false;
5463 } else {
5464 return true;
5465 }
5466 }
5467
5468 if (INTEL_INFO(dev)->num_pipes == 2)
5469 return true;
5470
5471 /* Ivybridge 3 pipe is really complicated */
5472 switch (pipe) {
5473 case PIPE_A:
5474 return true;
5475 case PIPE_B:
5476 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5477 pipe_config->fdi_lanes > 2) {
5478 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5479 pipe_name(pipe), pipe_config->fdi_lanes);
5480 return false;
5481 }
5482 return true;
5483 case PIPE_C:
5484 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5485 pipe_B_crtc->config.fdi_lanes <= 2) {
5486 if (pipe_config->fdi_lanes > 2) {
5487 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5488 pipe_name(pipe), pipe_config->fdi_lanes);
5489 return false;
5490 }
5491 } else {
5492 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5493 return false;
5494 }
5495 return true;
5496 default:
5497 BUG();
5498 }
5499 }
5500
5501 #define RETRY 1
5502 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5503 struct intel_crtc_config *pipe_config)
5504 {
5505 struct drm_device *dev = intel_crtc->base.dev;
5506 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5507 int lane, link_bw, fdi_dotclock;
5508 bool setup_ok, needs_recompute = false;
5509
5510 retry:
5511 /* FDI is a binary signal running at ~2.7GHz, encoding
5512 * each output octet as 10 bits. The actual frequency
5513 * is stored as a divider into a 100MHz clock, and the
5514 * mode pixel clock is stored in units of 1KHz.
5515 * Hence the bw of each lane in terms of the mode signal
5516 * is:
5517 */
5518 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5519
5520 fdi_dotclock = adjusted_mode->crtc_clock;
5521
5522 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5523 pipe_config->pipe_bpp);
5524
5525 pipe_config->fdi_lanes = lane;
5526
5527 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5528 link_bw, &pipe_config->fdi_m_n);
5529
5530 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5531 intel_crtc->pipe, pipe_config);
5532 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5533 pipe_config->pipe_bpp -= 2*3;
5534 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5535 pipe_config->pipe_bpp);
5536 needs_recompute = true;
5537 pipe_config->bw_constrained = true;
5538
5539 goto retry;
5540 }
5541
5542 if (needs_recompute)
5543 return RETRY;
5544
5545 return setup_ok ? 0 : -EINVAL;
5546 }
5547
5548 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5549 struct intel_crtc_config *pipe_config)
5550 {
5551 pipe_config->ips_enabled = i915.enable_ips &&
5552 hsw_crtc_supports_ips(crtc) &&
5553 pipe_config->pipe_bpp <= 24;
5554 }
5555
5556 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5557 struct intel_crtc_config *pipe_config)
5558 {
5559 struct drm_device *dev = crtc->base.dev;
5560 struct drm_i915_private *dev_priv = dev->dev_private;
5561 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5562
5563 /* FIXME should check pixel clock limits on all platforms */
5564 if (INTEL_INFO(dev)->gen < 4) {
5565 int clock_limit =
5566 dev_priv->display.get_display_clock_speed(dev);
5567
5568 /*
5569 * Enable pixel doubling when the dot clock
5570 * is > 90% of the (display) core speed.
5571 *
5572 * GDG double wide on either pipe,
5573 * otherwise pipe A only.
5574 */
5575 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5576 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5577 clock_limit *= 2;
5578 pipe_config->double_wide = true;
5579 }
5580
5581 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5582 return -EINVAL;
5583 }
5584
5585 /*
5586 * Pipe horizontal size must be even in:
5587 * - DVO ganged mode
5588 * - LVDS dual channel mode
5589 * - Double wide pipe
5590 */
5591 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5592 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5593 pipe_config->pipe_src_w &= ~1;
5594
5595 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5596 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5597 */
5598 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5599 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5600 return -EINVAL;
5601
5602 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5603 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5604 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5605 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5606 * for lvds. */
5607 pipe_config->pipe_bpp = 8*3;
5608 }
5609
5610 if (HAS_IPS(dev))
5611 hsw_compute_ips_config(crtc, pipe_config);
5612
5613 if (pipe_config->has_pch_encoder)
5614 return ironlake_fdi_compute_config(crtc, pipe_config);
5615
5616 return 0;
5617 }
5618
5619 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5620 {
5621 struct drm_i915_private *dev_priv = dev->dev_private;
5622 u32 val;
5623 int divider;
5624
5625 /* FIXME: Punit isn't quite ready yet */
5626 if (IS_CHERRYVIEW(dev))
5627 return 400000;
5628
5629 if (dev_priv->hpll_freq == 0)
5630 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5631
5632 mutex_lock(&dev_priv->dpio_lock);
5633 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5634 mutex_unlock(&dev_priv->dpio_lock);
5635
5636 divider = val & DISPLAY_FREQUENCY_VALUES;
5637
5638 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5639 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5640 "cdclk change in progress\n");
5641
5642 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5643 }
5644
5645 static int i945_get_display_clock_speed(struct drm_device *dev)
5646 {
5647 return 400000;
5648 }
5649
5650 static int i915_get_display_clock_speed(struct drm_device *dev)
5651 {
5652 return 333000;
5653 }
5654
5655 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5656 {
5657 return 200000;
5658 }
5659
5660 static int pnv_get_display_clock_speed(struct drm_device *dev)
5661 {
5662 u16 gcfgc = 0;
5663
5664 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5665
5666 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5667 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5668 return 267000;
5669 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5670 return 333000;
5671 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5672 return 444000;
5673 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5674 return 200000;
5675 default:
5676 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5677 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5678 return 133000;
5679 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5680 return 167000;
5681 }
5682 }
5683
5684 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5685 {
5686 u16 gcfgc = 0;
5687
5688 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5689
5690 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5691 return 133000;
5692 else {
5693 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5694 case GC_DISPLAY_CLOCK_333_MHZ:
5695 return 333000;
5696 default:
5697 case GC_DISPLAY_CLOCK_190_200_MHZ:
5698 return 190000;
5699 }
5700 }
5701 }
5702
5703 static int i865_get_display_clock_speed(struct drm_device *dev)
5704 {
5705 return 266000;
5706 }
5707
5708 static int i855_get_display_clock_speed(struct drm_device *dev)
5709 {
5710 u16 hpllcc = 0;
5711 /* Assume that the hardware is in the high speed state. This
5712 * should be the default.
5713 */
5714 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5715 case GC_CLOCK_133_200:
5716 case GC_CLOCK_100_200:
5717 return 200000;
5718 case GC_CLOCK_166_250:
5719 return 250000;
5720 case GC_CLOCK_100_133:
5721 return 133000;
5722 }
5723
5724 /* Shouldn't happen */
5725 return 0;
5726 }
5727
5728 static int i830_get_display_clock_speed(struct drm_device *dev)
5729 {
5730 return 133000;
5731 }
5732
5733 static void
5734 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5735 {
5736 while (*num > DATA_LINK_M_N_MASK ||
5737 *den > DATA_LINK_M_N_MASK) {
5738 *num >>= 1;
5739 *den >>= 1;
5740 }
5741 }
5742
5743 static void compute_m_n(unsigned int m, unsigned int n,
5744 uint32_t *ret_m, uint32_t *ret_n)
5745 {
5746 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5747 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5748 intel_reduce_m_n_ratio(ret_m, ret_n);
5749 }
5750
5751 void
5752 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5753 int pixel_clock, int link_clock,
5754 struct intel_link_m_n *m_n)
5755 {
5756 m_n->tu = 64;
5757
5758 compute_m_n(bits_per_pixel * pixel_clock,
5759 link_clock * nlanes * 8,
5760 &m_n->gmch_m, &m_n->gmch_n);
5761
5762 compute_m_n(pixel_clock, link_clock,
5763 &m_n->link_m, &m_n->link_n);
5764 }
5765
5766 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5767 {
5768 if (i915.panel_use_ssc >= 0)
5769 return i915.panel_use_ssc != 0;
5770 return dev_priv->vbt.lvds_use_ssc
5771 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5772 }
5773
5774 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5775 {
5776 struct drm_device *dev = crtc->base.dev;
5777 struct drm_i915_private *dev_priv = dev->dev_private;
5778 int refclk;
5779
5780 if (IS_VALLEYVIEW(dev)) {
5781 refclk = 100000;
5782 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5783 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5784 refclk = dev_priv->vbt.lvds_ssc_freq;
5785 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5786 } else if (!IS_GEN2(dev)) {
5787 refclk = 96000;
5788 } else {
5789 refclk = 48000;
5790 }
5791
5792 return refclk;
5793 }
5794
5795 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5796 {
5797 return (1 << dpll->n) << 16 | dpll->m2;
5798 }
5799
5800 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5801 {
5802 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5803 }
5804
5805 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5806 intel_clock_t *reduced_clock)
5807 {
5808 struct drm_device *dev = crtc->base.dev;
5809 u32 fp, fp2 = 0;
5810
5811 if (IS_PINEVIEW(dev)) {
5812 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5813 if (reduced_clock)
5814 fp2 = pnv_dpll_compute_fp(reduced_clock);
5815 } else {
5816 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5817 if (reduced_clock)
5818 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5819 }
5820
5821 crtc->new_config->dpll_hw_state.fp0 = fp;
5822
5823 crtc->lowfreq_avail = false;
5824 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5825 reduced_clock && i915.powersave) {
5826 crtc->new_config->dpll_hw_state.fp1 = fp2;
5827 crtc->lowfreq_avail = true;
5828 } else {
5829 crtc->new_config->dpll_hw_state.fp1 = fp;
5830 }
5831 }
5832
5833 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5834 pipe)
5835 {
5836 u32 reg_val;
5837
5838 /*
5839 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5840 * and set it to a reasonable value instead.
5841 */
5842 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5843 reg_val &= 0xffffff00;
5844 reg_val |= 0x00000030;
5845 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5846
5847 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5848 reg_val &= 0x8cffffff;
5849 reg_val = 0x8c000000;
5850 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5851
5852 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5853 reg_val &= 0xffffff00;
5854 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5855
5856 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5857 reg_val &= 0x00ffffff;
5858 reg_val |= 0xb0000000;
5859 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5860 }
5861
5862 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5863 struct intel_link_m_n *m_n)
5864 {
5865 struct drm_device *dev = crtc->base.dev;
5866 struct drm_i915_private *dev_priv = dev->dev_private;
5867 int pipe = crtc->pipe;
5868
5869 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5870 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5871 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5872 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5873 }
5874
5875 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5876 struct intel_link_m_n *m_n,
5877 struct intel_link_m_n *m2_n2)
5878 {
5879 struct drm_device *dev = crtc->base.dev;
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 int pipe = crtc->pipe;
5882 enum transcoder transcoder = crtc->config.cpu_transcoder;
5883
5884 if (INTEL_INFO(dev)->gen >= 5) {
5885 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5886 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5887 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5888 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5889 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5890 * for gen < 8) and if DRRS is supported (to make sure the
5891 * registers are not unnecessarily accessed).
5892 */
5893 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5894 crtc->config.has_drrs) {
5895 I915_WRITE(PIPE_DATA_M2(transcoder),
5896 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5897 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5898 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5899 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5900 }
5901 } else {
5902 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5903 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5904 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5905 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5906 }
5907 }
5908
5909 void intel_dp_set_m_n(struct intel_crtc *crtc)
5910 {
5911 if (crtc->config.has_pch_encoder)
5912 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5913 else
5914 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5915 &crtc->config.dp_m2_n2);
5916 }
5917
5918 static void vlv_update_pll(struct intel_crtc *crtc,
5919 struct intel_crtc_config *pipe_config)
5920 {
5921 u32 dpll, dpll_md;
5922
5923 /*
5924 * Enable DPIO clock input. We should never disable the reference
5925 * clock for pipe B, since VGA hotplug / manual detection depends
5926 * on it.
5927 */
5928 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5929 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5930 /* We should never disable this, set it here for state tracking */
5931 if (crtc->pipe == PIPE_B)
5932 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5933 dpll |= DPLL_VCO_ENABLE;
5934 pipe_config->dpll_hw_state.dpll = dpll;
5935
5936 dpll_md = (pipe_config->pixel_multiplier - 1)
5937 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5938 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5939 }
5940
5941 static void vlv_prepare_pll(struct intel_crtc *crtc,
5942 const struct intel_crtc_config *pipe_config)
5943 {
5944 struct drm_device *dev = crtc->base.dev;
5945 struct drm_i915_private *dev_priv = dev->dev_private;
5946 int pipe = crtc->pipe;
5947 u32 mdiv;
5948 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5949 u32 coreclk, reg_val;
5950
5951 mutex_lock(&dev_priv->dpio_lock);
5952
5953 bestn = pipe_config->dpll.n;
5954 bestm1 = pipe_config->dpll.m1;
5955 bestm2 = pipe_config->dpll.m2;
5956 bestp1 = pipe_config->dpll.p1;
5957 bestp2 = pipe_config->dpll.p2;
5958
5959 /* See eDP HDMI DPIO driver vbios notes doc */
5960
5961 /* PLL B needs special handling */
5962 if (pipe == PIPE_B)
5963 vlv_pllb_recal_opamp(dev_priv, pipe);
5964
5965 /* Set up Tx target for periodic Rcomp update */
5966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5967
5968 /* Disable target IRef on PLL */
5969 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5970 reg_val &= 0x00ffffff;
5971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5972
5973 /* Disable fast lock */
5974 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5975
5976 /* Set idtafcrecal before PLL is enabled */
5977 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5978 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5979 mdiv |= ((bestn << DPIO_N_SHIFT));
5980 mdiv |= (1 << DPIO_K_SHIFT);
5981
5982 /*
5983 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5984 * but we don't support that).
5985 * Note: don't use the DAC post divider as it seems unstable.
5986 */
5987 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5988 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5989
5990 mdiv |= DPIO_ENABLE_CALIBRATION;
5991 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5992
5993 /* Set HBR and RBR LPF coefficients */
5994 if (pipe_config->port_clock == 162000 ||
5995 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5996 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5997 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5998 0x009f0003);
5999 else
6000 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6001 0x00d0000f);
6002
6003 if (crtc->config.has_dp_encoder) {
6004 /* Use SSC source */
6005 if (pipe == PIPE_A)
6006 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6007 0x0df40000);
6008 else
6009 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6010 0x0df70000);
6011 } else { /* HDMI or VGA */
6012 /* Use bend source */
6013 if (pipe == PIPE_A)
6014 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6015 0x0df70000);
6016 else
6017 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6018 0x0df40000);
6019 }
6020
6021 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6022 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6023 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6024 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6025 coreclk |= 0x01000000;
6026 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6027
6028 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6029 mutex_unlock(&dev_priv->dpio_lock);
6030 }
6031
6032 static void chv_update_pll(struct intel_crtc *crtc,
6033 struct intel_crtc_config *pipe_config)
6034 {
6035 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6036 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6037 DPLL_VCO_ENABLE;
6038 if (crtc->pipe != PIPE_A)
6039 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6040
6041 pipe_config->dpll_hw_state.dpll_md =
6042 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6043 }
6044
6045 static void chv_prepare_pll(struct intel_crtc *crtc,
6046 const struct intel_crtc_config *pipe_config)
6047 {
6048 struct drm_device *dev = crtc->base.dev;
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050 int pipe = crtc->pipe;
6051 int dpll_reg = DPLL(crtc->pipe);
6052 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6053 u32 loopfilter, intcoeff;
6054 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6055 int refclk;
6056
6057 bestn = pipe_config->dpll.n;
6058 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6059 bestm1 = pipe_config->dpll.m1;
6060 bestm2 = pipe_config->dpll.m2 >> 22;
6061 bestp1 = pipe_config->dpll.p1;
6062 bestp2 = pipe_config->dpll.p2;
6063
6064 /*
6065 * Enable Refclk and SSC
6066 */
6067 I915_WRITE(dpll_reg,
6068 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6069
6070 mutex_lock(&dev_priv->dpio_lock);
6071
6072 /* p1 and p2 divider */
6073 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6074 5 << DPIO_CHV_S1_DIV_SHIFT |
6075 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6076 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6077 1 << DPIO_CHV_K_DIV_SHIFT);
6078
6079 /* Feedback post-divider - m2 */
6080 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6081
6082 /* Feedback refclk divider - n and m1 */
6083 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6084 DPIO_CHV_M1_DIV_BY_2 |
6085 1 << DPIO_CHV_N_DIV_SHIFT);
6086
6087 /* M2 fraction division */
6088 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6089
6090 /* M2 fraction division enable */
6091 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6092 DPIO_CHV_FRAC_DIV_EN |
6093 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6094
6095 /* Loop filter */
6096 refclk = i9xx_get_refclk(crtc, 0);
6097 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6098 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6099 if (refclk == 100000)
6100 intcoeff = 11;
6101 else if (refclk == 38400)
6102 intcoeff = 10;
6103 else
6104 intcoeff = 9;
6105 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6106 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6107
6108 /* AFC Recal */
6109 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6110 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6111 DPIO_AFC_RECAL);
6112
6113 mutex_unlock(&dev_priv->dpio_lock);
6114 }
6115
6116 /**
6117 * vlv_force_pll_on - forcibly enable just the PLL
6118 * @dev_priv: i915 private structure
6119 * @pipe: pipe PLL to enable
6120 * @dpll: PLL configuration
6121 *
6122 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6123 * in cases where we need the PLL enabled even when @pipe is not going to
6124 * be enabled.
6125 */
6126 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6127 const struct dpll *dpll)
6128 {
6129 struct intel_crtc *crtc =
6130 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6131 struct intel_crtc_config pipe_config = {
6132 .pixel_multiplier = 1,
6133 .dpll = *dpll,
6134 };
6135
6136 if (IS_CHERRYVIEW(dev)) {
6137 chv_update_pll(crtc, &pipe_config);
6138 chv_prepare_pll(crtc, &pipe_config);
6139 chv_enable_pll(crtc, &pipe_config);
6140 } else {
6141 vlv_update_pll(crtc, &pipe_config);
6142 vlv_prepare_pll(crtc, &pipe_config);
6143 vlv_enable_pll(crtc, &pipe_config);
6144 }
6145 }
6146
6147 /**
6148 * vlv_force_pll_off - forcibly disable just the PLL
6149 * @dev_priv: i915 private structure
6150 * @pipe: pipe PLL to disable
6151 *
6152 * Disable the PLL for @pipe. To be used in cases where we need
6153 * the PLL enabled even when @pipe is not going to be enabled.
6154 */
6155 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6156 {
6157 if (IS_CHERRYVIEW(dev))
6158 chv_disable_pll(to_i915(dev), pipe);
6159 else
6160 vlv_disable_pll(to_i915(dev), pipe);
6161 }
6162
6163 static void i9xx_update_pll(struct intel_crtc *crtc,
6164 intel_clock_t *reduced_clock,
6165 int num_connectors)
6166 {
6167 struct drm_device *dev = crtc->base.dev;
6168 struct drm_i915_private *dev_priv = dev->dev_private;
6169 u32 dpll;
6170 bool is_sdvo;
6171 struct dpll *clock = &crtc->new_config->dpll;
6172
6173 i9xx_update_pll_dividers(crtc, reduced_clock);
6174
6175 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6176 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6177
6178 dpll = DPLL_VGA_MODE_DIS;
6179
6180 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6181 dpll |= DPLLB_MODE_LVDS;
6182 else
6183 dpll |= DPLLB_MODE_DAC_SERIAL;
6184
6185 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6186 dpll |= (crtc->new_config->pixel_multiplier - 1)
6187 << SDVO_MULTIPLIER_SHIFT_HIRES;
6188 }
6189
6190 if (is_sdvo)
6191 dpll |= DPLL_SDVO_HIGH_SPEED;
6192
6193 if (crtc->new_config->has_dp_encoder)
6194 dpll |= DPLL_SDVO_HIGH_SPEED;
6195
6196 /* compute bitmask from p1 value */
6197 if (IS_PINEVIEW(dev))
6198 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6199 else {
6200 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6201 if (IS_G4X(dev) && reduced_clock)
6202 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6203 }
6204 switch (clock->p2) {
6205 case 5:
6206 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6207 break;
6208 case 7:
6209 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6210 break;
6211 case 10:
6212 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6213 break;
6214 case 14:
6215 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6216 break;
6217 }
6218 if (INTEL_INFO(dev)->gen >= 4)
6219 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6220
6221 if (crtc->new_config->sdvo_tv_clock)
6222 dpll |= PLL_REF_INPUT_TVCLKINBC;
6223 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6224 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6225 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6226 else
6227 dpll |= PLL_REF_INPUT_DREFCLK;
6228
6229 dpll |= DPLL_VCO_ENABLE;
6230 crtc->new_config->dpll_hw_state.dpll = dpll;
6231
6232 if (INTEL_INFO(dev)->gen >= 4) {
6233 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6234 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6235 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6236 }
6237 }
6238
6239 static void i8xx_update_pll(struct intel_crtc *crtc,
6240 intel_clock_t *reduced_clock,
6241 int num_connectors)
6242 {
6243 struct drm_device *dev = crtc->base.dev;
6244 struct drm_i915_private *dev_priv = dev->dev_private;
6245 u32 dpll;
6246 struct dpll *clock = &crtc->new_config->dpll;
6247
6248 i9xx_update_pll_dividers(crtc, reduced_clock);
6249
6250 dpll = DPLL_VGA_MODE_DIS;
6251
6252 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6253 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6254 } else {
6255 if (clock->p1 == 2)
6256 dpll |= PLL_P1_DIVIDE_BY_TWO;
6257 else
6258 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6259 if (clock->p2 == 4)
6260 dpll |= PLL_P2_DIVIDE_BY_4;
6261 }
6262
6263 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6264 dpll |= DPLL_DVO_2X_MODE;
6265
6266 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6267 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6268 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6269 else
6270 dpll |= PLL_REF_INPUT_DREFCLK;
6271
6272 dpll |= DPLL_VCO_ENABLE;
6273 crtc->new_config->dpll_hw_state.dpll = dpll;
6274 }
6275
6276 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6277 {
6278 struct drm_device *dev = intel_crtc->base.dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280 enum pipe pipe = intel_crtc->pipe;
6281 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6282 struct drm_display_mode *adjusted_mode =
6283 &intel_crtc->config.adjusted_mode;
6284 uint32_t crtc_vtotal, crtc_vblank_end;
6285 int vsyncshift = 0;
6286
6287 /* We need to be careful not to changed the adjusted mode, for otherwise
6288 * the hw state checker will get angry at the mismatch. */
6289 crtc_vtotal = adjusted_mode->crtc_vtotal;
6290 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6291
6292 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6293 /* the chip adds 2 halflines automatically */
6294 crtc_vtotal -= 1;
6295 crtc_vblank_end -= 1;
6296
6297 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6298 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6299 else
6300 vsyncshift = adjusted_mode->crtc_hsync_start -
6301 adjusted_mode->crtc_htotal / 2;
6302 if (vsyncshift < 0)
6303 vsyncshift += adjusted_mode->crtc_htotal;
6304 }
6305
6306 if (INTEL_INFO(dev)->gen > 3)
6307 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6308
6309 I915_WRITE(HTOTAL(cpu_transcoder),
6310 (adjusted_mode->crtc_hdisplay - 1) |
6311 ((adjusted_mode->crtc_htotal - 1) << 16));
6312 I915_WRITE(HBLANK(cpu_transcoder),
6313 (adjusted_mode->crtc_hblank_start - 1) |
6314 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6315 I915_WRITE(HSYNC(cpu_transcoder),
6316 (adjusted_mode->crtc_hsync_start - 1) |
6317 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6318
6319 I915_WRITE(VTOTAL(cpu_transcoder),
6320 (adjusted_mode->crtc_vdisplay - 1) |
6321 ((crtc_vtotal - 1) << 16));
6322 I915_WRITE(VBLANK(cpu_transcoder),
6323 (adjusted_mode->crtc_vblank_start - 1) |
6324 ((crtc_vblank_end - 1) << 16));
6325 I915_WRITE(VSYNC(cpu_transcoder),
6326 (adjusted_mode->crtc_vsync_start - 1) |
6327 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6328
6329 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6330 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6331 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6332 * bits. */
6333 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6334 (pipe == PIPE_B || pipe == PIPE_C))
6335 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6336
6337 /* pipesrc controls the size that is scaled from, which should
6338 * always be the user's requested size.
6339 */
6340 I915_WRITE(PIPESRC(pipe),
6341 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6342 (intel_crtc->config.pipe_src_h - 1));
6343 }
6344
6345 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6346 struct intel_crtc_config *pipe_config)
6347 {
6348 struct drm_device *dev = crtc->base.dev;
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6351 uint32_t tmp;
6352
6353 tmp = I915_READ(HTOTAL(cpu_transcoder));
6354 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6355 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6356 tmp = I915_READ(HBLANK(cpu_transcoder));
6357 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6358 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6359 tmp = I915_READ(HSYNC(cpu_transcoder));
6360 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6361 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6362
6363 tmp = I915_READ(VTOTAL(cpu_transcoder));
6364 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6365 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6366 tmp = I915_READ(VBLANK(cpu_transcoder));
6367 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6368 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6369 tmp = I915_READ(VSYNC(cpu_transcoder));
6370 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6371 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6372
6373 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6374 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6375 pipe_config->adjusted_mode.crtc_vtotal += 1;
6376 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6377 }
6378
6379 tmp = I915_READ(PIPESRC(crtc->pipe));
6380 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6381 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6382
6383 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6384 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6385 }
6386
6387 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6388 struct intel_crtc_config *pipe_config)
6389 {
6390 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6391 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6392 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6393 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6394
6395 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6396 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6397 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6398 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6399
6400 mode->flags = pipe_config->adjusted_mode.flags;
6401
6402 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6403 mode->flags |= pipe_config->adjusted_mode.flags;
6404 }
6405
6406 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6407 {
6408 struct drm_device *dev = intel_crtc->base.dev;
6409 struct drm_i915_private *dev_priv = dev->dev_private;
6410 uint32_t pipeconf;
6411
6412 pipeconf = 0;
6413
6414 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6415 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6416 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6417
6418 if (intel_crtc->config.double_wide)
6419 pipeconf |= PIPECONF_DOUBLE_WIDE;
6420
6421 /* only g4x and later have fancy bpc/dither controls */
6422 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6423 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6424 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6425 pipeconf |= PIPECONF_DITHER_EN |
6426 PIPECONF_DITHER_TYPE_SP;
6427
6428 switch (intel_crtc->config.pipe_bpp) {
6429 case 18:
6430 pipeconf |= PIPECONF_6BPC;
6431 break;
6432 case 24:
6433 pipeconf |= PIPECONF_8BPC;
6434 break;
6435 case 30:
6436 pipeconf |= PIPECONF_10BPC;
6437 break;
6438 default:
6439 /* Case prevented by intel_choose_pipe_bpp_dither. */
6440 BUG();
6441 }
6442 }
6443
6444 if (HAS_PIPE_CXSR(dev)) {
6445 if (intel_crtc->lowfreq_avail) {
6446 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6447 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6448 } else {
6449 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6450 }
6451 }
6452
6453 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6454 if (INTEL_INFO(dev)->gen < 4 ||
6455 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6456 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6457 else
6458 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6459 } else
6460 pipeconf |= PIPECONF_PROGRESSIVE;
6461
6462 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6463 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6464
6465 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6466 POSTING_READ(PIPECONF(intel_crtc->pipe));
6467 }
6468
6469 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6470 {
6471 struct drm_device *dev = crtc->base.dev;
6472 struct drm_i915_private *dev_priv = dev->dev_private;
6473 int refclk, num_connectors = 0;
6474 intel_clock_t clock, reduced_clock;
6475 bool ok, has_reduced_clock = false;
6476 bool is_lvds = false, is_dsi = false;
6477 struct intel_encoder *encoder;
6478 const intel_limit_t *limit;
6479
6480 for_each_intel_encoder(dev, encoder) {
6481 if (encoder->new_crtc != crtc)
6482 continue;
6483
6484 switch (encoder->type) {
6485 case INTEL_OUTPUT_LVDS:
6486 is_lvds = true;
6487 break;
6488 case INTEL_OUTPUT_DSI:
6489 is_dsi = true;
6490 break;
6491 default:
6492 break;
6493 }
6494
6495 num_connectors++;
6496 }
6497
6498 if (is_dsi)
6499 return 0;
6500
6501 if (!crtc->new_config->clock_set) {
6502 refclk = i9xx_get_refclk(crtc, num_connectors);
6503
6504 /*
6505 * Returns a set of divisors for the desired target clock with
6506 * the given refclk, or FALSE. The returned values represent
6507 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6508 * 2) / p1 / p2.
6509 */
6510 limit = intel_limit(crtc, refclk);
6511 ok = dev_priv->display.find_dpll(limit, crtc,
6512 crtc->new_config->port_clock,
6513 refclk, NULL, &clock);
6514 if (!ok) {
6515 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6516 return -EINVAL;
6517 }
6518
6519 if (is_lvds && dev_priv->lvds_downclock_avail) {
6520 /*
6521 * Ensure we match the reduced clock's P to the target
6522 * clock. If the clocks don't match, we can't switch
6523 * the display clock by using the FP0/FP1. In such case
6524 * we will disable the LVDS downclock feature.
6525 */
6526 has_reduced_clock =
6527 dev_priv->display.find_dpll(limit, crtc,
6528 dev_priv->lvds_downclock,
6529 refclk, &clock,
6530 &reduced_clock);
6531 }
6532 /* Compat-code for transition, will disappear. */
6533 crtc->new_config->dpll.n = clock.n;
6534 crtc->new_config->dpll.m1 = clock.m1;
6535 crtc->new_config->dpll.m2 = clock.m2;
6536 crtc->new_config->dpll.p1 = clock.p1;
6537 crtc->new_config->dpll.p2 = clock.p2;
6538 }
6539
6540 if (IS_GEN2(dev)) {
6541 i8xx_update_pll(crtc,
6542 has_reduced_clock ? &reduced_clock : NULL,
6543 num_connectors);
6544 } else if (IS_CHERRYVIEW(dev)) {
6545 chv_update_pll(crtc, crtc->new_config);
6546 } else if (IS_VALLEYVIEW(dev)) {
6547 vlv_update_pll(crtc, crtc->new_config);
6548 } else {
6549 i9xx_update_pll(crtc,
6550 has_reduced_clock ? &reduced_clock : NULL,
6551 num_connectors);
6552 }
6553
6554 return 0;
6555 }
6556
6557 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6558 struct intel_crtc_config *pipe_config)
6559 {
6560 struct drm_device *dev = crtc->base.dev;
6561 struct drm_i915_private *dev_priv = dev->dev_private;
6562 uint32_t tmp;
6563
6564 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6565 return;
6566
6567 tmp = I915_READ(PFIT_CONTROL);
6568 if (!(tmp & PFIT_ENABLE))
6569 return;
6570
6571 /* Check whether the pfit is attached to our pipe. */
6572 if (INTEL_INFO(dev)->gen < 4) {
6573 if (crtc->pipe != PIPE_B)
6574 return;
6575 } else {
6576 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6577 return;
6578 }
6579
6580 pipe_config->gmch_pfit.control = tmp;
6581 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6582 if (INTEL_INFO(dev)->gen < 5)
6583 pipe_config->gmch_pfit.lvds_border_bits =
6584 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6585 }
6586
6587 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6588 struct intel_crtc_config *pipe_config)
6589 {
6590 struct drm_device *dev = crtc->base.dev;
6591 struct drm_i915_private *dev_priv = dev->dev_private;
6592 int pipe = pipe_config->cpu_transcoder;
6593 intel_clock_t clock;
6594 u32 mdiv;
6595 int refclk = 100000;
6596
6597 /* In case of MIPI DPLL will not even be used */
6598 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6599 return;
6600
6601 mutex_lock(&dev_priv->dpio_lock);
6602 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6603 mutex_unlock(&dev_priv->dpio_lock);
6604
6605 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6606 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6607 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6608 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6609 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6610
6611 vlv_clock(refclk, &clock);
6612
6613 /* clock.dot is the fast clock */
6614 pipe_config->port_clock = clock.dot / 5;
6615 }
6616
6617 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6618 struct intel_plane_config *plane_config)
6619 {
6620 struct drm_device *dev = crtc->base.dev;
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622 u32 val, base, offset;
6623 int pipe = crtc->pipe, plane = crtc->plane;
6624 int fourcc, pixel_format;
6625 int aligned_height;
6626
6627 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6628 if (!crtc->base.primary->fb) {
6629 DRM_DEBUG_KMS("failed to alloc fb\n");
6630 return;
6631 }
6632
6633 val = I915_READ(DSPCNTR(plane));
6634
6635 if (INTEL_INFO(dev)->gen >= 4)
6636 if (val & DISPPLANE_TILED)
6637 plane_config->tiled = true;
6638
6639 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6640 fourcc = intel_format_to_fourcc(pixel_format);
6641 crtc->base.primary->fb->pixel_format = fourcc;
6642 crtc->base.primary->fb->bits_per_pixel =
6643 drm_format_plane_cpp(fourcc, 0) * 8;
6644
6645 if (INTEL_INFO(dev)->gen >= 4) {
6646 if (plane_config->tiled)
6647 offset = I915_READ(DSPTILEOFF(plane));
6648 else
6649 offset = I915_READ(DSPLINOFF(plane));
6650 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6651 } else {
6652 base = I915_READ(DSPADDR(plane));
6653 }
6654 plane_config->base = base;
6655
6656 val = I915_READ(PIPESRC(pipe));
6657 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6658 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6659
6660 val = I915_READ(DSPSTRIDE(pipe));
6661 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6662
6663 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6664 plane_config->tiled);
6665
6666 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6667 aligned_height);
6668
6669 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6670 pipe, plane, crtc->base.primary->fb->width,
6671 crtc->base.primary->fb->height,
6672 crtc->base.primary->fb->bits_per_pixel, base,
6673 crtc->base.primary->fb->pitches[0],
6674 plane_config->size);
6675
6676 }
6677
6678 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6679 struct intel_crtc_config *pipe_config)
6680 {
6681 struct drm_device *dev = crtc->base.dev;
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 int pipe = pipe_config->cpu_transcoder;
6684 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6685 intel_clock_t clock;
6686 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6687 int refclk = 100000;
6688
6689 mutex_lock(&dev_priv->dpio_lock);
6690 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6691 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6692 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6693 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6694 mutex_unlock(&dev_priv->dpio_lock);
6695
6696 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6697 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6698 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6699 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6700 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6701
6702 chv_clock(refclk, &clock);
6703
6704 /* clock.dot is the fast clock */
6705 pipe_config->port_clock = clock.dot / 5;
6706 }
6707
6708 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6709 struct intel_crtc_config *pipe_config)
6710 {
6711 struct drm_device *dev = crtc->base.dev;
6712 struct drm_i915_private *dev_priv = dev->dev_private;
6713 uint32_t tmp;
6714
6715 if (!intel_display_power_is_enabled(dev_priv,
6716 POWER_DOMAIN_PIPE(crtc->pipe)))
6717 return false;
6718
6719 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6720 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6721
6722 tmp = I915_READ(PIPECONF(crtc->pipe));
6723 if (!(tmp & PIPECONF_ENABLE))
6724 return false;
6725
6726 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6727 switch (tmp & PIPECONF_BPC_MASK) {
6728 case PIPECONF_6BPC:
6729 pipe_config->pipe_bpp = 18;
6730 break;
6731 case PIPECONF_8BPC:
6732 pipe_config->pipe_bpp = 24;
6733 break;
6734 case PIPECONF_10BPC:
6735 pipe_config->pipe_bpp = 30;
6736 break;
6737 default:
6738 break;
6739 }
6740 }
6741
6742 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6743 pipe_config->limited_color_range = true;
6744
6745 if (INTEL_INFO(dev)->gen < 4)
6746 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6747
6748 intel_get_pipe_timings(crtc, pipe_config);
6749
6750 i9xx_get_pfit_config(crtc, pipe_config);
6751
6752 if (INTEL_INFO(dev)->gen >= 4) {
6753 tmp = I915_READ(DPLL_MD(crtc->pipe));
6754 pipe_config->pixel_multiplier =
6755 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6756 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6757 pipe_config->dpll_hw_state.dpll_md = tmp;
6758 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6759 tmp = I915_READ(DPLL(crtc->pipe));
6760 pipe_config->pixel_multiplier =
6761 ((tmp & SDVO_MULTIPLIER_MASK)
6762 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6763 } else {
6764 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6765 * port and will be fixed up in the encoder->get_config
6766 * function. */
6767 pipe_config->pixel_multiplier = 1;
6768 }
6769 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6770 if (!IS_VALLEYVIEW(dev)) {
6771 /*
6772 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6773 * on 830. Filter it out here so that we don't
6774 * report errors due to that.
6775 */
6776 if (IS_I830(dev))
6777 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6778
6779 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6780 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6781 } else {
6782 /* Mask out read-only status bits. */
6783 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6784 DPLL_PORTC_READY_MASK |
6785 DPLL_PORTB_READY_MASK);
6786 }
6787
6788 if (IS_CHERRYVIEW(dev))
6789 chv_crtc_clock_get(crtc, pipe_config);
6790 else if (IS_VALLEYVIEW(dev))
6791 vlv_crtc_clock_get(crtc, pipe_config);
6792 else
6793 i9xx_crtc_clock_get(crtc, pipe_config);
6794
6795 return true;
6796 }
6797
6798 static void ironlake_init_pch_refclk(struct drm_device *dev)
6799 {
6800 struct drm_i915_private *dev_priv = dev->dev_private;
6801 struct intel_encoder *encoder;
6802 u32 val, final;
6803 bool has_lvds = false;
6804 bool has_cpu_edp = false;
6805 bool has_panel = false;
6806 bool has_ck505 = false;
6807 bool can_ssc = false;
6808
6809 /* We need to take the global config into account */
6810 for_each_intel_encoder(dev, encoder) {
6811 switch (encoder->type) {
6812 case INTEL_OUTPUT_LVDS:
6813 has_panel = true;
6814 has_lvds = true;
6815 break;
6816 case INTEL_OUTPUT_EDP:
6817 has_panel = true;
6818 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6819 has_cpu_edp = true;
6820 break;
6821 default:
6822 break;
6823 }
6824 }
6825
6826 if (HAS_PCH_IBX(dev)) {
6827 has_ck505 = dev_priv->vbt.display_clock_mode;
6828 can_ssc = has_ck505;
6829 } else {
6830 has_ck505 = false;
6831 can_ssc = true;
6832 }
6833
6834 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6835 has_panel, has_lvds, has_ck505);
6836
6837 /* Ironlake: try to setup display ref clock before DPLL
6838 * enabling. This is only under driver's control after
6839 * PCH B stepping, previous chipset stepping should be
6840 * ignoring this setting.
6841 */
6842 val = I915_READ(PCH_DREF_CONTROL);
6843
6844 /* As we must carefully and slowly disable/enable each source in turn,
6845 * compute the final state we want first and check if we need to
6846 * make any changes at all.
6847 */
6848 final = val;
6849 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6850 if (has_ck505)
6851 final |= DREF_NONSPREAD_CK505_ENABLE;
6852 else
6853 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6854
6855 final &= ~DREF_SSC_SOURCE_MASK;
6856 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6857 final &= ~DREF_SSC1_ENABLE;
6858
6859 if (has_panel) {
6860 final |= DREF_SSC_SOURCE_ENABLE;
6861
6862 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6863 final |= DREF_SSC1_ENABLE;
6864
6865 if (has_cpu_edp) {
6866 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6867 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6868 else
6869 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6870 } else
6871 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6872 } else {
6873 final |= DREF_SSC_SOURCE_DISABLE;
6874 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6875 }
6876
6877 if (final == val)
6878 return;
6879
6880 /* Always enable nonspread source */
6881 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6882
6883 if (has_ck505)
6884 val |= DREF_NONSPREAD_CK505_ENABLE;
6885 else
6886 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6887
6888 if (has_panel) {
6889 val &= ~DREF_SSC_SOURCE_MASK;
6890 val |= DREF_SSC_SOURCE_ENABLE;
6891
6892 /* SSC must be turned on before enabling the CPU output */
6893 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6894 DRM_DEBUG_KMS("Using SSC on panel\n");
6895 val |= DREF_SSC1_ENABLE;
6896 } else
6897 val &= ~DREF_SSC1_ENABLE;
6898
6899 /* Get SSC going before enabling the outputs */
6900 I915_WRITE(PCH_DREF_CONTROL, val);
6901 POSTING_READ(PCH_DREF_CONTROL);
6902 udelay(200);
6903
6904 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6905
6906 /* Enable CPU source on CPU attached eDP */
6907 if (has_cpu_edp) {
6908 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6909 DRM_DEBUG_KMS("Using SSC on eDP\n");
6910 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6911 } else
6912 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6913 } else
6914 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6915
6916 I915_WRITE(PCH_DREF_CONTROL, val);
6917 POSTING_READ(PCH_DREF_CONTROL);
6918 udelay(200);
6919 } else {
6920 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6921
6922 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6923
6924 /* Turn off CPU output */
6925 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6926
6927 I915_WRITE(PCH_DREF_CONTROL, val);
6928 POSTING_READ(PCH_DREF_CONTROL);
6929 udelay(200);
6930
6931 /* Turn off the SSC source */
6932 val &= ~DREF_SSC_SOURCE_MASK;
6933 val |= DREF_SSC_SOURCE_DISABLE;
6934
6935 /* Turn off SSC1 */
6936 val &= ~DREF_SSC1_ENABLE;
6937
6938 I915_WRITE(PCH_DREF_CONTROL, val);
6939 POSTING_READ(PCH_DREF_CONTROL);
6940 udelay(200);
6941 }
6942
6943 BUG_ON(val != final);
6944 }
6945
6946 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6947 {
6948 uint32_t tmp;
6949
6950 tmp = I915_READ(SOUTH_CHICKEN2);
6951 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6952 I915_WRITE(SOUTH_CHICKEN2, tmp);
6953
6954 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6955 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6956 DRM_ERROR("FDI mPHY reset assert timeout\n");
6957
6958 tmp = I915_READ(SOUTH_CHICKEN2);
6959 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6960 I915_WRITE(SOUTH_CHICKEN2, tmp);
6961
6962 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6963 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6964 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6965 }
6966
6967 /* WaMPhyProgramming:hsw */
6968 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6969 {
6970 uint32_t tmp;
6971
6972 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6973 tmp &= ~(0xFF << 24);
6974 tmp |= (0x12 << 24);
6975 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6976
6977 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6978 tmp |= (1 << 11);
6979 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6980
6981 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6982 tmp |= (1 << 11);
6983 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6984
6985 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6986 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6987 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6988
6989 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6990 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6991 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6992
6993 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6994 tmp &= ~(7 << 13);
6995 tmp |= (5 << 13);
6996 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6997
6998 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6999 tmp &= ~(7 << 13);
7000 tmp |= (5 << 13);
7001 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7002
7003 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7004 tmp &= ~0xFF;
7005 tmp |= 0x1C;
7006 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7007
7008 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7009 tmp &= ~0xFF;
7010 tmp |= 0x1C;
7011 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7012
7013 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7014 tmp &= ~(0xFF << 16);
7015 tmp |= (0x1C << 16);
7016 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7017
7018 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7019 tmp &= ~(0xFF << 16);
7020 tmp |= (0x1C << 16);
7021 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7022
7023 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7024 tmp |= (1 << 27);
7025 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7026
7027 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7028 tmp |= (1 << 27);
7029 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7030
7031 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7032 tmp &= ~(0xF << 28);
7033 tmp |= (4 << 28);
7034 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7035
7036 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7037 tmp &= ~(0xF << 28);
7038 tmp |= (4 << 28);
7039 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7040 }
7041
7042 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7043 * Programming" based on the parameters passed:
7044 * - Sequence to enable CLKOUT_DP
7045 * - Sequence to enable CLKOUT_DP without spread
7046 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7047 */
7048 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7049 bool with_fdi)
7050 {
7051 struct drm_i915_private *dev_priv = dev->dev_private;
7052 uint32_t reg, tmp;
7053
7054 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7055 with_spread = true;
7056 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7057 with_fdi, "LP PCH doesn't have FDI\n"))
7058 with_fdi = false;
7059
7060 mutex_lock(&dev_priv->dpio_lock);
7061
7062 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7063 tmp &= ~SBI_SSCCTL_DISABLE;
7064 tmp |= SBI_SSCCTL_PATHALT;
7065 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7066
7067 udelay(24);
7068
7069 if (with_spread) {
7070 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7071 tmp &= ~SBI_SSCCTL_PATHALT;
7072 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7073
7074 if (with_fdi) {
7075 lpt_reset_fdi_mphy(dev_priv);
7076 lpt_program_fdi_mphy(dev_priv);
7077 }
7078 }
7079
7080 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7081 SBI_GEN0 : SBI_DBUFF0;
7082 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7083 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7084 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7085
7086 mutex_unlock(&dev_priv->dpio_lock);
7087 }
7088
7089 /* Sequence to disable CLKOUT_DP */
7090 static void lpt_disable_clkout_dp(struct drm_device *dev)
7091 {
7092 struct drm_i915_private *dev_priv = dev->dev_private;
7093 uint32_t reg, tmp;
7094
7095 mutex_lock(&dev_priv->dpio_lock);
7096
7097 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7098 SBI_GEN0 : SBI_DBUFF0;
7099 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7100 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7101 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7102
7103 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7104 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7105 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7106 tmp |= SBI_SSCCTL_PATHALT;
7107 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7108 udelay(32);
7109 }
7110 tmp |= SBI_SSCCTL_DISABLE;
7111 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7112 }
7113
7114 mutex_unlock(&dev_priv->dpio_lock);
7115 }
7116
7117 static void lpt_init_pch_refclk(struct drm_device *dev)
7118 {
7119 struct intel_encoder *encoder;
7120 bool has_vga = false;
7121
7122 for_each_intel_encoder(dev, encoder) {
7123 switch (encoder->type) {
7124 case INTEL_OUTPUT_ANALOG:
7125 has_vga = true;
7126 break;
7127 default:
7128 break;
7129 }
7130 }
7131
7132 if (has_vga)
7133 lpt_enable_clkout_dp(dev, true, true);
7134 else
7135 lpt_disable_clkout_dp(dev);
7136 }
7137
7138 /*
7139 * Initialize reference clocks when the driver loads
7140 */
7141 void intel_init_pch_refclk(struct drm_device *dev)
7142 {
7143 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7144 ironlake_init_pch_refclk(dev);
7145 else if (HAS_PCH_LPT(dev))
7146 lpt_init_pch_refclk(dev);
7147 }
7148
7149 static int ironlake_get_refclk(struct drm_crtc *crtc)
7150 {
7151 struct drm_device *dev = crtc->dev;
7152 struct drm_i915_private *dev_priv = dev->dev_private;
7153 struct intel_encoder *encoder;
7154 int num_connectors = 0;
7155 bool is_lvds = false;
7156
7157 for_each_intel_encoder(dev, encoder) {
7158 if (encoder->new_crtc != to_intel_crtc(crtc))
7159 continue;
7160
7161 switch (encoder->type) {
7162 case INTEL_OUTPUT_LVDS:
7163 is_lvds = true;
7164 break;
7165 default:
7166 break;
7167 }
7168 num_connectors++;
7169 }
7170
7171 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7172 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7173 dev_priv->vbt.lvds_ssc_freq);
7174 return dev_priv->vbt.lvds_ssc_freq;
7175 }
7176
7177 return 120000;
7178 }
7179
7180 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7181 {
7182 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7184 int pipe = intel_crtc->pipe;
7185 uint32_t val;
7186
7187 val = 0;
7188
7189 switch (intel_crtc->config.pipe_bpp) {
7190 case 18:
7191 val |= PIPECONF_6BPC;
7192 break;
7193 case 24:
7194 val |= PIPECONF_8BPC;
7195 break;
7196 case 30:
7197 val |= PIPECONF_10BPC;
7198 break;
7199 case 36:
7200 val |= PIPECONF_12BPC;
7201 break;
7202 default:
7203 /* Case prevented by intel_choose_pipe_bpp_dither. */
7204 BUG();
7205 }
7206
7207 if (intel_crtc->config.dither)
7208 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7209
7210 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7211 val |= PIPECONF_INTERLACED_ILK;
7212 else
7213 val |= PIPECONF_PROGRESSIVE;
7214
7215 if (intel_crtc->config.limited_color_range)
7216 val |= PIPECONF_COLOR_RANGE_SELECT;
7217
7218 I915_WRITE(PIPECONF(pipe), val);
7219 POSTING_READ(PIPECONF(pipe));
7220 }
7221
7222 /*
7223 * Set up the pipe CSC unit.
7224 *
7225 * Currently only full range RGB to limited range RGB conversion
7226 * is supported, but eventually this should handle various
7227 * RGB<->YCbCr scenarios as well.
7228 */
7229 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7230 {
7231 struct drm_device *dev = crtc->dev;
7232 struct drm_i915_private *dev_priv = dev->dev_private;
7233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7234 int pipe = intel_crtc->pipe;
7235 uint16_t coeff = 0x7800; /* 1.0 */
7236
7237 /*
7238 * TODO: Check what kind of values actually come out of the pipe
7239 * with these coeff/postoff values and adjust to get the best
7240 * accuracy. Perhaps we even need to take the bpc value into
7241 * consideration.
7242 */
7243
7244 if (intel_crtc->config.limited_color_range)
7245 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7246
7247 /*
7248 * GY/GU and RY/RU should be the other way around according
7249 * to BSpec, but reality doesn't agree. Just set them up in
7250 * a way that results in the correct picture.
7251 */
7252 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7253 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7254
7255 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7256 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7257
7258 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7259 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7260
7261 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7262 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7263 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7264
7265 if (INTEL_INFO(dev)->gen > 6) {
7266 uint16_t postoff = 0;
7267
7268 if (intel_crtc->config.limited_color_range)
7269 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7270
7271 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7272 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7273 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7274
7275 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7276 } else {
7277 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7278
7279 if (intel_crtc->config.limited_color_range)
7280 mode |= CSC_BLACK_SCREEN_OFFSET;
7281
7282 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7283 }
7284 }
7285
7286 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7287 {
7288 struct drm_device *dev = crtc->dev;
7289 struct drm_i915_private *dev_priv = dev->dev_private;
7290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291 enum pipe pipe = intel_crtc->pipe;
7292 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7293 uint32_t val;
7294
7295 val = 0;
7296
7297 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7298 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7299
7300 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7301 val |= PIPECONF_INTERLACED_ILK;
7302 else
7303 val |= PIPECONF_PROGRESSIVE;
7304
7305 I915_WRITE(PIPECONF(cpu_transcoder), val);
7306 POSTING_READ(PIPECONF(cpu_transcoder));
7307
7308 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7309 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7310
7311 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7312 val = 0;
7313
7314 switch (intel_crtc->config.pipe_bpp) {
7315 case 18:
7316 val |= PIPEMISC_DITHER_6_BPC;
7317 break;
7318 case 24:
7319 val |= PIPEMISC_DITHER_8_BPC;
7320 break;
7321 case 30:
7322 val |= PIPEMISC_DITHER_10_BPC;
7323 break;
7324 case 36:
7325 val |= PIPEMISC_DITHER_12_BPC;
7326 break;
7327 default:
7328 /* Case prevented by pipe_config_set_bpp. */
7329 BUG();
7330 }
7331
7332 if (intel_crtc->config.dither)
7333 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7334
7335 I915_WRITE(PIPEMISC(pipe), val);
7336 }
7337 }
7338
7339 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7340 intel_clock_t *clock,
7341 bool *has_reduced_clock,
7342 intel_clock_t *reduced_clock)
7343 {
7344 struct drm_device *dev = crtc->dev;
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7347 int refclk;
7348 const intel_limit_t *limit;
7349 bool ret, is_lvds = false;
7350
7351 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7352
7353 refclk = ironlake_get_refclk(crtc);
7354
7355 /*
7356 * Returns a set of divisors for the desired target clock with the given
7357 * refclk, or FALSE. The returned values represent the clock equation:
7358 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7359 */
7360 limit = intel_limit(intel_crtc, refclk);
7361 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7362 intel_crtc->new_config->port_clock,
7363 refclk, NULL, clock);
7364 if (!ret)
7365 return false;
7366
7367 if (is_lvds && dev_priv->lvds_downclock_avail) {
7368 /*
7369 * Ensure we match the reduced clock's P to the target clock.
7370 * If the clocks don't match, we can't switch the display clock
7371 * by using the FP0/FP1. In such case we will disable the LVDS
7372 * downclock feature.
7373 */
7374 *has_reduced_clock =
7375 dev_priv->display.find_dpll(limit, intel_crtc,
7376 dev_priv->lvds_downclock,
7377 refclk, clock,
7378 reduced_clock);
7379 }
7380
7381 return true;
7382 }
7383
7384 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7385 {
7386 /*
7387 * Account for spread spectrum to avoid
7388 * oversubscribing the link. Max center spread
7389 * is 2.5%; use 5% for safety's sake.
7390 */
7391 u32 bps = target_clock * bpp * 21 / 20;
7392 return DIV_ROUND_UP(bps, link_bw * 8);
7393 }
7394
7395 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7396 {
7397 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7398 }
7399
7400 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7401 u32 *fp,
7402 intel_clock_t *reduced_clock, u32 *fp2)
7403 {
7404 struct drm_crtc *crtc = &intel_crtc->base;
7405 struct drm_device *dev = crtc->dev;
7406 struct drm_i915_private *dev_priv = dev->dev_private;
7407 struct intel_encoder *intel_encoder;
7408 uint32_t dpll;
7409 int factor, num_connectors = 0;
7410 bool is_lvds = false, is_sdvo = false;
7411
7412 for_each_intel_encoder(dev, intel_encoder) {
7413 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7414 continue;
7415
7416 switch (intel_encoder->type) {
7417 case INTEL_OUTPUT_LVDS:
7418 is_lvds = true;
7419 break;
7420 case INTEL_OUTPUT_SDVO:
7421 case INTEL_OUTPUT_HDMI:
7422 is_sdvo = true;
7423 break;
7424 default:
7425 break;
7426 }
7427
7428 num_connectors++;
7429 }
7430
7431 /* Enable autotuning of the PLL clock (if permissible) */
7432 factor = 21;
7433 if (is_lvds) {
7434 if ((intel_panel_use_ssc(dev_priv) &&
7435 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7436 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7437 factor = 25;
7438 } else if (intel_crtc->new_config->sdvo_tv_clock)
7439 factor = 20;
7440
7441 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7442 *fp |= FP_CB_TUNE;
7443
7444 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7445 *fp2 |= FP_CB_TUNE;
7446
7447 dpll = 0;
7448
7449 if (is_lvds)
7450 dpll |= DPLLB_MODE_LVDS;
7451 else
7452 dpll |= DPLLB_MODE_DAC_SERIAL;
7453
7454 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7455 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7456
7457 if (is_sdvo)
7458 dpll |= DPLL_SDVO_HIGH_SPEED;
7459 if (intel_crtc->new_config->has_dp_encoder)
7460 dpll |= DPLL_SDVO_HIGH_SPEED;
7461
7462 /* compute bitmask from p1 value */
7463 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7464 /* also FPA1 */
7465 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7466
7467 switch (intel_crtc->new_config->dpll.p2) {
7468 case 5:
7469 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7470 break;
7471 case 7:
7472 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7473 break;
7474 case 10:
7475 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7476 break;
7477 case 14:
7478 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7479 break;
7480 }
7481
7482 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7483 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7484 else
7485 dpll |= PLL_REF_INPUT_DREFCLK;
7486
7487 return dpll | DPLL_VCO_ENABLE;
7488 }
7489
7490 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7491 {
7492 struct drm_device *dev = crtc->base.dev;
7493 intel_clock_t clock, reduced_clock;
7494 u32 dpll = 0, fp = 0, fp2 = 0;
7495 bool ok, has_reduced_clock = false;
7496 bool is_lvds = false;
7497 struct intel_shared_dpll *pll;
7498
7499 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7500
7501 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7502 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7503
7504 ok = ironlake_compute_clocks(&crtc->base, &clock,
7505 &has_reduced_clock, &reduced_clock);
7506 if (!ok && !crtc->new_config->clock_set) {
7507 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7508 return -EINVAL;
7509 }
7510 /* Compat-code for transition, will disappear. */
7511 if (!crtc->new_config->clock_set) {
7512 crtc->new_config->dpll.n = clock.n;
7513 crtc->new_config->dpll.m1 = clock.m1;
7514 crtc->new_config->dpll.m2 = clock.m2;
7515 crtc->new_config->dpll.p1 = clock.p1;
7516 crtc->new_config->dpll.p2 = clock.p2;
7517 }
7518
7519 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7520 if (crtc->new_config->has_pch_encoder) {
7521 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7522 if (has_reduced_clock)
7523 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7524
7525 dpll = ironlake_compute_dpll(crtc,
7526 &fp, &reduced_clock,
7527 has_reduced_clock ? &fp2 : NULL);
7528
7529 crtc->new_config->dpll_hw_state.dpll = dpll;
7530 crtc->new_config->dpll_hw_state.fp0 = fp;
7531 if (has_reduced_clock)
7532 crtc->new_config->dpll_hw_state.fp1 = fp2;
7533 else
7534 crtc->new_config->dpll_hw_state.fp1 = fp;
7535
7536 pll = intel_get_shared_dpll(crtc);
7537 if (pll == NULL) {
7538 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7539 pipe_name(crtc->pipe));
7540 return -EINVAL;
7541 }
7542 }
7543
7544 if (is_lvds && has_reduced_clock && i915.powersave)
7545 crtc->lowfreq_avail = true;
7546 else
7547 crtc->lowfreq_avail = false;
7548
7549 return 0;
7550 }
7551
7552 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7553 struct intel_link_m_n *m_n)
7554 {
7555 struct drm_device *dev = crtc->base.dev;
7556 struct drm_i915_private *dev_priv = dev->dev_private;
7557 enum pipe pipe = crtc->pipe;
7558
7559 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7560 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7561 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7562 & ~TU_SIZE_MASK;
7563 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7564 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7565 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7566 }
7567
7568 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7569 enum transcoder transcoder,
7570 struct intel_link_m_n *m_n,
7571 struct intel_link_m_n *m2_n2)
7572 {
7573 struct drm_device *dev = crtc->base.dev;
7574 struct drm_i915_private *dev_priv = dev->dev_private;
7575 enum pipe pipe = crtc->pipe;
7576
7577 if (INTEL_INFO(dev)->gen >= 5) {
7578 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7579 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7580 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7581 & ~TU_SIZE_MASK;
7582 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7583 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7584 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7585 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7586 * gen < 8) and if DRRS is supported (to make sure the
7587 * registers are not unnecessarily read).
7588 */
7589 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7590 crtc->config.has_drrs) {
7591 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7592 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7593 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7594 & ~TU_SIZE_MASK;
7595 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7596 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7597 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7598 }
7599 } else {
7600 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7601 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7602 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7603 & ~TU_SIZE_MASK;
7604 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7605 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7606 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7607 }
7608 }
7609
7610 void intel_dp_get_m_n(struct intel_crtc *crtc,
7611 struct intel_crtc_config *pipe_config)
7612 {
7613 if (crtc->config.has_pch_encoder)
7614 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7615 else
7616 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7617 &pipe_config->dp_m_n,
7618 &pipe_config->dp_m2_n2);
7619 }
7620
7621 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7622 struct intel_crtc_config *pipe_config)
7623 {
7624 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7625 &pipe_config->fdi_m_n, NULL);
7626 }
7627
7628 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7629 struct intel_crtc_config *pipe_config)
7630 {
7631 struct drm_device *dev = crtc->base.dev;
7632 struct drm_i915_private *dev_priv = dev->dev_private;
7633 uint32_t tmp;
7634
7635 tmp = I915_READ(PS_CTL(crtc->pipe));
7636
7637 if (tmp & PS_ENABLE) {
7638 pipe_config->pch_pfit.enabled = true;
7639 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7640 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7641 }
7642 }
7643
7644 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7645 struct intel_crtc_config *pipe_config)
7646 {
7647 struct drm_device *dev = crtc->base.dev;
7648 struct drm_i915_private *dev_priv = dev->dev_private;
7649 uint32_t tmp;
7650
7651 tmp = I915_READ(PF_CTL(crtc->pipe));
7652
7653 if (tmp & PF_ENABLE) {
7654 pipe_config->pch_pfit.enabled = true;
7655 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7656 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7657
7658 /* We currently do not free assignements of panel fitters on
7659 * ivb/hsw (since we don't use the higher upscaling modes which
7660 * differentiates them) so just WARN about this case for now. */
7661 if (IS_GEN7(dev)) {
7662 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7663 PF_PIPE_SEL_IVB(crtc->pipe));
7664 }
7665 }
7666 }
7667
7668 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7669 struct intel_plane_config *plane_config)
7670 {
7671 struct drm_device *dev = crtc->base.dev;
7672 struct drm_i915_private *dev_priv = dev->dev_private;
7673 u32 val, base, offset;
7674 int pipe = crtc->pipe, plane = crtc->plane;
7675 int fourcc, pixel_format;
7676 int aligned_height;
7677
7678 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7679 if (!crtc->base.primary->fb) {
7680 DRM_DEBUG_KMS("failed to alloc fb\n");
7681 return;
7682 }
7683
7684 val = I915_READ(DSPCNTR(plane));
7685
7686 if (INTEL_INFO(dev)->gen >= 4)
7687 if (val & DISPPLANE_TILED)
7688 plane_config->tiled = true;
7689
7690 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7691 fourcc = intel_format_to_fourcc(pixel_format);
7692 crtc->base.primary->fb->pixel_format = fourcc;
7693 crtc->base.primary->fb->bits_per_pixel =
7694 drm_format_plane_cpp(fourcc, 0) * 8;
7695
7696 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7697 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7698 offset = I915_READ(DSPOFFSET(plane));
7699 } else {
7700 if (plane_config->tiled)
7701 offset = I915_READ(DSPTILEOFF(plane));
7702 else
7703 offset = I915_READ(DSPLINOFF(plane));
7704 }
7705 plane_config->base = base;
7706
7707 val = I915_READ(PIPESRC(pipe));
7708 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7709 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7710
7711 val = I915_READ(DSPSTRIDE(pipe));
7712 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7713
7714 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7715 plane_config->tiled);
7716
7717 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7718 aligned_height);
7719
7720 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7721 pipe, plane, crtc->base.primary->fb->width,
7722 crtc->base.primary->fb->height,
7723 crtc->base.primary->fb->bits_per_pixel, base,
7724 crtc->base.primary->fb->pitches[0],
7725 plane_config->size);
7726 }
7727
7728 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7729 struct intel_crtc_config *pipe_config)
7730 {
7731 struct drm_device *dev = crtc->base.dev;
7732 struct drm_i915_private *dev_priv = dev->dev_private;
7733 uint32_t tmp;
7734
7735 if (!intel_display_power_is_enabled(dev_priv,
7736 POWER_DOMAIN_PIPE(crtc->pipe)))
7737 return false;
7738
7739 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7740 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7741
7742 tmp = I915_READ(PIPECONF(crtc->pipe));
7743 if (!(tmp & PIPECONF_ENABLE))
7744 return false;
7745
7746 switch (tmp & PIPECONF_BPC_MASK) {
7747 case PIPECONF_6BPC:
7748 pipe_config->pipe_bpp = 18;
7749 break;
7750 case PIPECONF_8BPC:
7751 pipe_config->pipe_bpp = 24;
7752 break;
7753 case PIPECONF_10BPC:
7754 pipe_config->pipe_bpp = 30;
7755 break;
7756 case PIPECONF_12BPC:
7757 pipe_config->pipe_bpp = 36;
7758 break;
7759 default:
7760 break;
7761 }
7762
7763 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7764 pipe_config->limited_color_range = true;
7765
7766 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7767 struct intel_shared_dpll *pll;
7768
7769 pipe_config->has_pch_encoder = true;
7770
7771 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7772 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7773 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7774
7775 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7776
7777 if (HAS_PCH_IBX(dev_priv->dev)) {
7778 pipe_config->shared_dpll =
7779 (enum intel_dpll_id) crtc->pipe;
7780 } else {
7781 tmp = I915_READ(PCH_DPLL_SEL);
7782 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7783 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7784 else
7785 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7786 }
7787
7788 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7789
7790 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7791 &pipe_config->dpll_hw_state));
7792
7793 tmp = pipe_config->dpll_hw_state.dpll;
7794 pipe_config->pixel_multiplier =
7795 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7796 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7797
7798 ironlake_pch_clock_get(crtc, pipe_config);
7799 } else {
7800 pipe_config->pixel_multiplier = 1;
7801 }
7802
7803 intel_get_pipe_timings(crtc, pipe_config);
7804
7805 ironlake_get_pfit_config(crtc, pipe_config);
7806
7807 return true;
7808 }
7809
7810 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7811 {
7812 struct drm_device *dev = dev_priv->dev;
7813 struct intel_crtc *crtc;
7814
7815 for_each_intel_crtc(dev, crtc)
7816 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7817 pipe_name(crtc->pipe));
7818
7819 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7820 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7821 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7822 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7823 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7824 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7825 "CPU PWM1 enabled\n");
7826 if (IS_HASWELL(dev))
7827 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7828 "CPU PWM2 enabled\n");
7829 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7830 "PCH PWM1 enabled\n");
7831 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7832 "Utility pin enabled\n");
7833 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7834
7835 /*
7836 * In theory we can still leave IRQs enabled, as long as only the HPD
7837 * interrupts remain enabled. We used to check for that, but since it's
7838 * gen-specific and since we only disable LCPLL after we fully disable
7839 * the interrupts, the check below should be enough.
7840 */
7841 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7842 }
7843
7844 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7845 {
7846 struct drm_device *dev = dev_priv->dev;
7847
7848 if (IS_HASWELL(dev))
7849 return I915_READ(D_COMP_HSW);
7850 else
7851 return I915_READ(D_COMP_BDW);
7852 }
7853
7854 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7855 {
7856 struct drm_device *dev = dev_priv->dev;
7857
7858 if (IS_HASWELL(dev)) {
7859 mutex_lock(&dev_priv->rps.hw_lock);
7860 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7861 val))
7862 DRM_ERROR("Failed to write to D_COMP\n");
7863 mutex_unlock(&dev_priv->rps.hw_lock);
7864 } else {
7865 I915_WRITE(D_COMP_BDW, val);
7866 POSTING_READ(D_COMP_BDW);
7867 }
7868 }
7869
7870 /*
7871 * This function implements pieces of two sequences from BSpec:
7872 * - Sequence for display software to disable LCPLL
7873 * - Sequence for display software to allow package C8+
7874 * The steps implemented here are just the steps that actually touch the LCPLL
7875 * register. Callers should take care of disabling all the display engine
7876 * functions, doing the mode unset, fixing interrupts, etc.
7877 */
7878 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7879 bool switch_to_fclk, bool allow_power_down)
7880 {
7881 uint32_t val;
7882
7883 assert_can_disable_lcpll(dev_priv);
7884
7885 val = I915_READ(LCPLL_CTL);
7886
7887 if (switch_to_fclk) {
7888 val |= LCPLL_CD_SOURCE_FCLK;
7889 I915_WRITE(LCPLL_CTL, val);
7890
7891 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7892 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7893 DRM_ERROR("Switching to FCLK failed\n");
7894
7895 val = I915_READ(LCPLL_CTL);
7896 }
7897
7898 val |= LCPLL_PLL_DISABLE;
7899 I915_WRITE(LCPLL_CTL, val);
7900 POSTING_READ(LCPLL_CTL);
7901
7902 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7903 DRM_ERROR("LCPLL still locked\n");
7904
7905 val = hsw_read_dcomp(dev_priv);
7906 val |= D_COMP_COMP_DISABLE;
7907 hsw_write_dcomp(dev_priv, val);
7908 ndelay(100);
7909
7910 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7911 1))
7912 DRM_ERROR("D_COMP RCOMP still in progress\n");
7913
7914 if (allow_power_down) {
7915 val = I915_READ(LCPLL_CTL);
7916 val |= LCPLL_POWER_DOWN_ALLOW;
7917 I915_WRITE(LCPLL_CTL, val);
7918 POSTING_READ(LCPLL_CTL);
7919 }
7920 }
7921
7922 /*
7923 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7924 * source.
7925 */
7926 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7927 {
7928 uint32_t val;
7929
7930 val = I915_READ(LCPLL_CTL);
7931
7932 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7933 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7934 return;
7935
7936 /*
7937 * Make sure we're not on PC8 state before disabling PC8, otherwise
7938 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7939 *
7940 * The other problem is that hsw_restore_lcpll() is called as part of
7941 * the runtime PM resume sequence, so we can't just call
7942 * gen6_gt_force_wake_get() because that function calls
7943 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7944 * while we are on the resume sequence. So to solve this problem we have
7945 * to call special forcewake code that doesn't touch runtime PM and
7946 * doesn't enable the forcewake delayed work.
7947 */
7948 spin_lock_irq(&dev_priv->uncore.lock);
7949 if (dev_priv->uncore.forcewake_count++ == 0)
7950 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7951 spin_unlock_irq(&dev_priv->uncore.lock);
7952
7953 if (val & LCPLL_POWER_DOWN_ALLOW) {
7954 val &= ~LCPLL_POWER_DOWN_ALLOW;
7955 I915_WRITE(LCPLL_CTL, val);
7956 POSTING_READ(LCPLL_CTL);
7957 }
7958
7959 val = hsw_read_dcomp(dev_priv);
7960 val |= D_COMP_COMP_FORCE;
7961 val &= ~D_COMP_COMP_DISABLE;
7962 hsw_write_dcomp(dev_priv, val);
7963
7964 val = I915_READ(LCPLL_CTL);
7965 val &= ~LCPLL_PLL_DISABLE;
7966 I915_WRITE(LCPLL_CTL, val);
7967
7968 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7969 DRM_ERROR("LCPLL not locked yet\n");
7970
7971 if (val & LCPLL_CD_SOURCE_FCLK) {
7972 val = I915_READ(LCPLL_CTL);
7973 val &= ~LCPLL_CD_SOURCE_FCLK;
7974 I915_WRITE(LCPLL_CTL, val);
7975
7976 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7977 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7978 DRM_ERROR("Switching back to LCPLL failed\n");
7979 }
7980
7981 /* See the big comment above. */
7982 spin_lock_irq(&dev_priv->uncore.lock);
7983 if (--dev_priv->uncore.forcewake_count == 0)
7984 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7985 spin_unlock_irq(&dev_priv->uncore.lock);
7986 }
7987
7988 /*
7989 * Package states C8 and deeper are really deep PC states that can only be
7990 * reached when all the devices on the system allow it, so even if the graphics
7991 * device allows PC8+, it doesn't mean the system will actually get to these
7992 * states. Our driver only allows PC8+ when going into runtime PM.
7993 *
7994 * The requirements for PC8+ are that all the outputs are disabled, the power
7995 * well is disabled and most interrupts are disabled, and these are also
7996 * requirements for runtime PM. When these conditions are met, we manually do
7997 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7998 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7999 * hang the machine.
8000 *
8001 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8002 * the state of some registers, so when we come back from PC8+ we need to
8003 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8004 * need to take care of the registers kept by RC6. Notice that this happens even
8005 * if we don't put the device in PCI D3 state (which is what currently happens
8006 * because of the runtime PM support).
8007 *
8008 * For more, read "Display Sequences for Package C8" on the hardware
8009 * documentation.
8010 */
8011 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8012 {
8013 struct drm_device *dev = dev_priv->dev;
8014 uint32_t val;
8015
8016 DRM_DEBUG_KMS("Enabling package C8+\n");
8017
8018 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8019 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8020 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8021 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8022 }
8023
8024 lpt_disable_clkout_dp(dev);
8025 hsw_disable_lcpll(dev_priv, true, true);
8026 }
8027
8028 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8029 {
8030 struct drm_device *dev = dev_priv->dev;
8031 uint32_t val;
8032
8033 DRM_DEBUG_KMS("Disabling package C8+\n");
8034
8035 hsw_restore_lcpll(dev_priv);
8036 lpt_init_pch_refclk(dev);
8037
8038 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8039 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8040 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8041 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8042 }
8043
8044 intel_prepare_ddi(dev);
8045 }
8046
8047 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
8048 {
8049 if (!intel_ddi_pll_select(crtc))
8050 return -EINVAL;
8051
8052 crtc->lowfreq_avail = false;
8053
8054 return 0;
8055 }
8056
8057 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8058 enum port port,
8059 struct intel_crtc_config *pipe_config)
8060 {
8061 u32 temp, dpll_ctl1;
8062
8063 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8064 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8065
8066 switch (pipe_config->ddi_pll_sel) {
8067 case SKL_DPLL0:
8068 /*
8069 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8070 * of the shared DPLL framework and thus needs to be read out
8071 * separately
8072 */
8073 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8074 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8075 break;
8076 case SKL_DPLL1:
8077 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8078 break;
8079 case SKL_DPLL2:
8080 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8081 break;
8082 case SKL_DPLL3:
8083 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8084 break;
8085 }
8086 }
8087
8088 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8089 enum port port,
8090 struct intel_crtc_config *pipe_config)
8091 {
8092 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8093
8094 switch (pipe_config->ddi_pll_sel) {
8095 case PORT_CLK_SEL_WRPLL1:
8096 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8097 break;
8098 case PORT_CLK_SEL_WRPLL2:
8099 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8100 break;
8101 }
8102 }
8103
8104 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8105 struct intel_crtc_config *pipe_config)
8106 {
8107 struct drm_device *dev = crtc->base.dev;
8108 struct drm_i915_private *dev_priv = dev->dev_private;
8109 struct intel_shared_dpll *pll;
8110 enum port port;
8111 uint32_t tmp;
8112
8113 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8114
8115 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8116
8117 if (IS_SKYLAKE(dev))
8118 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8119 else
8120 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8121
8122 if (pipe_config->shared_dpll >= 0) {
8123 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8124
8125 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8126 &pipe_config->dpll_hw_state));
8127 }
8128
8129 /*
8130 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8131 * DDI E. So just check whether this pipe is wired to DDI E and whether
8132 * the PCH transcoder is on.
8133 */
8134 if (INTEL_INFO(dev)->gen < 9 &&
8135 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8136 pipe_config->has_pch_encoder = true;
8137
8138 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8139 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8140 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8141
8142 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8143 }
8144 }
8145
8146 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8147 struct intel_crtc_config *pipe_config)
8148 {
8149 struct drm_device *dev = crtc->base.dev;
8150 struct drm_i915_private *dev_priv = dev->dev_private;
8151 enum intel_display_power_domain pfit_domain;
8152 uint32_t tmp;
8153
8154 if (!intel_display_power_is_enabled(dev_priv,
8155 POWER_DOMAIN_PIPE(crtc->pipe)))
8156 return false;
8157
8158 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8159 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8160
8161 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8162 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8163 enum pipe trans_edp_pipe;
8164 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8165 default:
8166 WARN(1, "unknown pipe linked to edp transcoder\n");
8167 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8168 case TRANS_DDI_EDP_INPUT_A_ON:
8169 trans_edp_pipe = PIPE_A;
8170 break;
8171 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8172 trans_edp_pipe = PIPE_B;
8173 break;
8174 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8175 trans_edp_pipe = PIPE_C;
8176 break;
8177 }
8178
8179 if (trans_edp_pipe == crtc->pipe)
8180 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8181 }
8182
8183 if (!intel_display_power_is_enabled(dev_priv,
8184 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8185 return false;
8186
8187 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8188 if (!(tmp & PIPECONF_ENABLE))
8189 return false;
8190
8191 haswell_get_ddi_port_state(crtc, pipe_config);
8192
8193 intel_get_pipe_timings(crtc, pipe_config);
8194
8195 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8196 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8197 if (IS_SKYLAKE(dev))
8198 skylake_get_pfit_config(crtc, pipe_config);
8199 else
8200 ironlake_get_pfit_config(crtc, pipe_config);
8201 }
8202
8203 if (IS_HASWELL(dev))
8204 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8205 (I915_READ(IPS_CTL) & IPS_ENABLE);
8206
8207 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8208 pipe_config->pixel_multiplier =
8209 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8210 } else {
8211 pipe_config->pixel_multiplier = 1;
8212 }
8213
8214 return true;
8215 }
8216
8217 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8218 {
8219 struct drm_device *dev = crtc->dev;
8220 struct drm_i915_private *dev_priv = dev->dev_private;
8221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8222 uint32_t cntl = 0, size = 0;
8223
8224 if (base) {
8225 unsigned int width = intel_crtc->cursor_width;
8226 unsigned int height = intel_crtc->cursor_height;
8227 unsigned int stride = roundup_pow_of_two(width) * 4;
8228
8229 switch (stride) {
8230 default:
8231 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8232 width, stride);
8233 stride = 256;
8234 /* fallthrough */
8235 case 256:
8236 case 512:
8237 case 1024:
8238 case 2048:
8239 break;
8240 }
8241
8242 cntl |= CURSOR_ENABLE |
8243 CURSOR_GAMMA_ENABLE |
8244 CURSOR_FORMAT_ARGB |
8245 CURSOR_STRIDE(stride);
8246
8247 size = (height << 12) | width;
8248 }
8249
8250 if (intel_crtc->cursor_cntl != 0 &&
8251 (intel_crtc->cursor_base != base ||
8252 intel_crtc->cursor_size != size ||
8253 intel_crtc->cursor_cntl != cntl)) {
8254 /* On these chipsets we can only modify the base/size/stride
8255 * whilst the cursor is disabled.
8256 */
8257 I915_WRITE(_CURACNTR, 0);
8258 POSTING_READ(_CURACNTR);
8259 intel_crtc->cursor_cntl = 0;
8260 }
8261
8262 if (intel_crtc->cursor_base != base) {
8263 I915_WRITE(_CURABASE, base);
8264 intel_crtc->cursor_base = base;
8265 }
8266
8267 if (intel_crtc->cursor_size != size) {
8268 I915_WRITE(CURSIZE, size);
8269 intel_crtc->cursor_size = size;
8270 }
8271
8272 if (intel_crtc->cursor_cntl != cntl) {
8273 I915_WRITE(_CURACNTR, cntl);
8274 POSTING_READ(_CURACNTR);
8275 intel_crtc->cursor_cntl = cntl;
8276 }
8277 }
8278
8279 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8280 {
8281 struct drm_device *dev = crtc->dev;
8282 struct drm_i915_private *dev_priv = dev->dev_private;
8283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8284 int pipe = intel_crtc->pipe;
8285 uint32_t cntl;
8286
8287 cntl = 0;
8288 if (base) {
8289 cntl = MCURSOR_GAMMA_ENABLE;
8290 switch (intel_crtc->cursor_width) {
8291 case 64:
8292 cntl |= CURSOR_MODE_64_ARGB_AX;
8293 break;
8294 case 128:
8295 cntl |= CURSOR_MODE_128_ARGB_AX;
8296 break;
8297 case 256:
8298 cntl |= CURSOR_MODE_256_ARGB_AX;
8299 break;
8300 default:
8301 WARN_ON(1);
8302 return;
8303 }
8304 cntl |= pipe << 28; /* Connect to correct pipe */
8305
8306 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8307 cntl |= CURSOR_PIPE_CSC_ENABLE;
8308 }
8309
8310 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8311 cntl |= CURSOR_ROTATE_180;
8312
8313 if (intel_crtc->cursor_cntl != cntl) {
8314 I915_WRITE(CURCNTR(pipe), cntl);
8315 POSTING_READ(CURCNTR(pipe));
8316 intel_crtc->cursor_cntl = cntl;
8317 }
8318
8319 /* and commit changes on next vblank */
8320 I915_WRITE(CURBASE(pipe), base);
8321 POSTING_READ(CURBASE(pipe));
8322
8323 intel_crtc->cursor_base = base;
8324 }
8325
8326 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8327 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8328 bool on)
8329 {
8330 struct drm_device *dev = crtc->dev;
8331 struct drm_i915_private *dev_priv = dev->dev_private;
8332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8333 int pipe = intel_crtc->pipe;
8334 int x = crtc->cursor_x;
8335 int y = crtc->cursor_y;
8336 u32 base = 0, pos = 0;
8337
8338 if (on)
8339 base = intel_crtc->cursor_addr;
8340
8341 if (x >= intel_crtc->config.pipe_src_w)
8342 base = 0;
8343
8344 if (y >= intel_crtc->config.pipe_src_h)
8345 base = 0;
8346
8347 if (x < 0) {
8348 if (x + intel_crtc->cursor_width <= 0)
8349 base = 0;
8350
8351 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8352 x = -x;
8353 }
8354 pos |= x << CURSOR_X_SHIFT;
8355
8356 if (y < 0) {
8357 if (y + intel_crtc->cursor_height <= 0)
8358 base = 0;
8359
8360 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8361 y = -y;
8362 }
8363 pos |= y << CURSOR_Y_SHIFT;
8364
8365 if (base == 0 && intel_crtc->cursor_base == 0)
8366 return;
8367
8368 I915_WRITE(CURPOS(pipe), pos);
8369
8370 /* ILK+ do this automagically */
8371 if (HAS_GMCH_DISPLAY(dev) &&
8372 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8373 base += (intel_crtc->cursor_height *
8374 intel_crtc->cursor_width - 1) * 4;
8375 }
8376
8377 if (IS_845G(dev) || IS_I865G(dev))
8378 i845_update_cursor(crtc, base);
8379 else
8380 i9xx_update_cursor(crtc, base);
8381 }
8382
8383 static bool cursor_size_ok(struct drm_device *dev,
8384 uint32_t width, uint32_t height)
8385 {
8386 if (width == 0 || height == 0)
8387 return false;
8388
8389 /*
8390 * 845g/865g are special in that they are only limited by
8391 * the width of their cursors, the height is arbitrary up to
8392 * the precision of the register. Everything else requires
8393 * square cursors, limited to a few power-of-two sizes.
8394 */
8395 if (IS_845G(dev) || IS_I865G(dev)) {
8396 if ((width & 63) != 0)
8397 return false;
8398
8399 if (width > (IS_845G(dev) ? 64 : 512))
8400 return false;
8401
8402 if (height > 1023)
8403 return false;
8404 } else {
8405 switch (width | height) {
8406 case 256:
8407 case 128:
8408 if (IS_GEN2(dev))
8409 return false;
8410 case 64:
8411 break;
8412 default:
8413 return false;
8414 }
8415 }
8416
8417 return true;
8418 }
8419
8420 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8421 struct drm_i915_gem_object *obj,
8422 uint32_t width, uint32_t height)
8423 {
8424 struct drm_device *dev = crtc->dev;
8425 struct drm_i915_private *dev_priv = to_i915(dev);
8426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8427 enum pipe pipe = intel_crtc->pipe;
8428 unsigned old_width;
8429 uint32_t addr;
8430 int ret;
8431
8432 /* if we want to turn off the cursor ignore width and height */
8433 if (!obj) {
8434 DRM_DEBUG_KMS("cursor off\n");
8435 addr = 0;
8436 mutex_lock(&dev->struct_mutex);
8437 goto finish;
8438 }
8439
8440 /* we only need to pin inside GTT if cursor is non-phy */
8441 mutex_lock(&dev->struct_mutex);
8442 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8443 unsigned alignment;
8444
8445 /*
8446 * Global gtt pte registers are special registers which actually
8447 * forward writes to a chunk of system memory. Which means that
8448 * there is no risk that the register values disappear as soon
8449 * as we call intel_runtime_pm_put(), so it is correct to wrap
8450 * only the pin/unpin/fence and not more.
8451 */
8452 intel_runtime_pm_get(dev_priv);
8453
8454 /* Note that the w/a also requires 2 PTE of padding following
8455 * the bo. We currently fill all unused PTE with the shadow
8456 * page and so we should always have valid PTE following the
8457 * cursor preventing the VT-d warning.
8458 */
8459 alignment = 0;
8460 if (need_vtd_wa(dev))
8461 alignment = 64*1024;
8462
8463 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8464 if (ret) {
8465 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8466 intel_runtime_pm_put(dev_priv);
8467 goto fail_locked;
8468 }
8469
8470 ret = i915_gem_object_put_fence(obj);
8471 if (ret) {
8472 DRM_DEBUG_KMS("failed to release fence for cursor");
8473 intel_runtime_pm_put(dev_priv);
8474 goto fail_unpin;
8475 }
8476
8477 addr = i915_gem_obj_ggtt_offset(obj);
8478
8479 intel_runtime_pm_put(dev_priv);
8480 } else {
8481 int align = IS_I830(dev) ? 16 * 1024 : 256;
8482 ret = i915_gem_object_attach_phys(obj, align);
8483 if (ret) {
8484 DRM_DEBUG_KMS("failed to attach phys object\n");
8485 goto fail_locked;
8486 }
8487 addr = obj->phys_handle->busaddr;
8488 }
8489
8490 finish:
8491 if (intel_crtc->cursor_bo) {
8492 if (!INTEL_INFO(dev)->cursor_needs_physical)
8493 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8494 }
8495
8496 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8497 INTEL_FRONTBUFFER_CURSOR(pipe));
8498 mutex_unlock(&dev->struct_mutex);
8499
8500 old_width = intel_crtc->cursor_width;
8501
8502 intel_crtc->cursor_addr = addr;
8503 intel_crtc->cursor_bo = obj;
8504 intel_crtc->cursor_width = width;
8505 intel_crtc->cursor_height = height;
8506
8507 if (intel_crtc->active) {
8508 if (old_width != width)
8509 intel_update_watermarks(crtc);
8510 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8511
8512 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8513 }
8514
8515 return 0;
8516 fail_unpin:
8517 i915_gem_object_unpin_from_display_plane(obj);
8518 fail_locked:
8519 mutex_unlock(&dev->struct_mutex);
8520 return ret;
8521 }
8522
8523 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8524 u16 *blue, uint32_t start, uint32_t size)
8525 {
8526 int end = (start + size > 256) ? 256 : start + size, i;
8527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8528
8529 for (i = start; i < end; i++) {
8530 intel_crtc->lut_r[i] = red[i] >> 8;
8531 intel_crtc->lut_g[i] = green[i] >> 8;
8532 intel_crtc->lut_b[i] = blue[i] >> 8;
8533 }
8534
8535 intel_crtc_load_lut(crtc);
8536 }
8537
8538 /* VESA 640x480x72Hz mode to set on the pipe */
8539 static struct drm_display_mode load_detect_mode = {
8540 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8541 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8542 };
8543
8544 struct drm_framebuffer *
8545 __intel_framebuffer_create(struct drm_device *dev,
8546 struct drm_mode_fb_cmd2 *mode_cmd,
8547 struct drm_i915_gem_object *obj)
8548 {
8549 struct intel_framebuffer *intel_fb;
8550 int ret;
8551
8552 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8553 if (!intel_fb) {
8554 drm_gem_object_unreference(&obj->base);
8555 return ERR_PTR(-ENOMEM);
8556 }
8557
8558 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8559 if (ret)
8560 goto err;
8561
8562 return &intel_fb->base;
8563 err:
8564 drm_gem_object_unreference(&obj->base);
8565 kfree(intel_fb);
8566
8567 return ERR_PTR(ret);
8568 }
8569
8570 static struct drm_framebuffer *
8571 intel_framebuffer_create(struct drm_device *dev,
8572 struct drm_mode_fb_cmd2 *mode_cmd,
8573 struct drm_i915_gem_object *obj)
8574 {
8575 struct drm_framebuffer *fb;
8576 int ret;
8577
8578 ret = i915_mutex_lock_interruptible(dev);
8579 if (ret)
8580 return ERR_PTR(ret);
8581 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8582 mutex_unlock(&dev->struct_mutex);
8583
8584 return fb;
8585 }
8586
8587 static u32
8588 intel_framebuffer_pitch_for_width(int width, int bpp)
8589 {
8590 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8591 return ALIGN(pitch, 64);
8592 }
8593
8594 static u32
8595 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8596 {
8597 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8598 return PAGE_ALIGN(pitch * mode->vdisplay);
8599 }
8600
8601 static struct drm_framebuffer *
8602 intel_framebuffer_create_for_mode(struct drm_device *dev,
8603 struct drm_display_mode *mode,
8604 int depth, int bpp)
8605 {
8606 struct drm_i915_gem_object *obj;
8607 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8608
8609 obj = i915_gem_alloc_object(dev,
8610 intel_framebuffer_size_for_mode(mode, bpp));
8611 if (obj == NULL)
8612 return ERR_PTR(-ENOMEM);
8613
8614 mode_cmd.width = mode->hdisplay;
8615 mode_cmd.height = mode->vdisplay;
8616 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8617 bpp);
8618 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8619
8620 return intel_framebuffer_create(dev, &mode_cmd, obj);
8621 }
8622
8623 static struct drm_framebuffer *
8624 mode_fits_in_fbdev(struct drm_device *dev,
8625 struct drm_display_mode *mode)
8626 {
8627 #ifdef CONFIG_DRM_I915_FBDEV
8628 struct drm_i915_private *dev_priv = dev->dev_private;
8629 struct drm_i915_gem_object *obj;
8630 struct drm_framebuffer *fb;
8631
8632 if (!dev_priv->fbdev)
8633 return NULL;
8634
8635 if (!dev_priv->fbdev->fb)
8636 return NULL;
8637
8638 obj = dev_priv->fbdev->fb->obj;
8639 BUG_ON(!obj);
8640
8641 fb = &dev_priv->fbdev->fb->base;
8642 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8643 fb->bits_per_pixel))
8644 return NULL;
8645
8646 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8647 return NULL;
8648
8649 return fb;
8650 #else
8651 return NULL;
8652 #endif
8653 }
8654
8655 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8656 struct drm_display_mode *mode,
8657 struct intel_load_detect_pipe *old,
8658 struct drm_modeset_acquire_ctx *ctx)
8659 {
8660 struct intel_crtc *intel_crtc;
8661 struct intel_encoder *intel_encoder =
8662 intel_attached_encoder(connector);
8663 struct drm_crtc *possible_crtc;
8664 struct drm_encoder *encoder = &intel_encoder->base;
8665 struct drm_crtc *crtc = NULL;
8666 struct drm_device *dev = encoder->dev;
8667 struct drm_framebuffer *fb;
8668 struct drm_mode_config *config = &dev->mode_config;
8669 int ret, i = -1;
8670
8671 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8672 connector->base.id, connector->name,
8673 encoder->base.id, encoder->name);
8674
8675 retry:
8676 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8677 if (ret)
8678 goto fail_unlock;
8679
8680 /*
8681 * Algorithm gets a little messy:
8682 *
8683 * - if the connector already has an assigned crtc, use it (but make
8684 * sure it's on first)
8685 *
8686 * - try to find the first unused crtc that can drive this connector,
8687 * and use that if we find one
8688 */
8689
8690 /* See if we already have a CRTC for this connector */
8691 if (encoder->crtc) {
8692 crtc = encoder->crtc;
8693
8694 ret = drm_modeset_lock(&crtc->mutex, ctx);
8695 if (ret)
8696 goto fail_unlock;
8697 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8698 if (ret)
8699 goto fail_unlock;
8700
8701 old->dpms_mode = connector->dpms;
8702 old->load_detect_temp = false;
8703
8704 /* Make sure the crtc and connector are running */
8705 if (connector->dpms != DRM_MODE_DPMS_ON)
8706 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8707
8708 return true;
8709 }
8710
8711 /* Find an unused one (if possible) */
8712 for_each_crtc(dev, possible_crtc) {
8713 i++;
8714 if (!(encoder->possible_crtcs & (1 << i)))
8715 continue;
8716 if (possible_crtc->enabled)
8717 continue;
8718 /* This can occur when applying the pipe A quirk on resume. */
8719 if (to_intel_crtc(possible_crtc)->new_enabled)
8720 continue;
8721
8722 crtc = possible_crtc;
8723 break;
8724 }
8725
8726 /*
8727 * If we didn't find an unused CRTC, don't use any.
8728 */
8729 if (!crtc) {
8730 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8731 goto fail_unlock;
8732 }
8733
8734 ret = drm_modeset_lock(&crtc->mutex, ctx);
8735 if (ret)
8736 goto fail_unlock;
8737 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8738 if (ret)
8739 goto fail_unlock;
8740 intel_encoder->new_crtc = to_intel_crtc(crtc);
8741 to_intel_connector(connector)->new_encoder = intel_encoder;
8742
8743 intel_crtc = to_intel_crtc(crtc);
8744 intel_crtc->new_enabled = true;
8745 intel_crtc->new_config = &intel_crtc->config;
8746 old->dpms_mode = connector->dpms;
8747 old->load_detect_temp = true;
8748 old->release_fb = NULL;
8749
8750 if (!mode)
8751 mode = &load_detect_mode;
8752
8753 /* We need a framebuffer large enough to accommodate all accesses
8754 * that the plane may generate whilst we perform load detection.
8755 * We can not rely on the fbcon either being present (we get called
8756 * during its initialisation to detect all boot displays, or it may
8757 * not even exist) or that it is large enough to satisfy the
8758 * requested mode.
8759 */
8760 fb = mode_fits_in_fbdev(dev, mode);
8761 if (fb == NULL) {
8762 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8763 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8764 old->release_fb = fb;
8765 } else
8766 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8767 if (IS_ERR(fb)) {
8768 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8769 goto fail;
8770 }
8771
8772 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8773 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8774 if (old->release_fb)
8775 old->release_fb->funcs->destroy(old->release_fb);
8776 goto fail;
8777 }
8778
8779 /* let the connector get through one full cycle before testing */
8780 intel_wait_for_vblank(dev, intel_crtc->pipe);
8781 return true;
8782
8783 fail:
8784 intel_crtc->new_enabled = crtc->enabled;
8785 if (intel_crtc->new_enabled)
8786 intel_crtc->new_config = &intel_crtc->config;
8787 else
8788 intel_crtc->new_config = NULL;
8789 fail_unlock:
8790 if (ret == -EDEADLK) {
8791 drm_modeset_backoff(ctx);
8792 goto retry;
8793 }
8794
8795 return false;
8796 }
8797
8798 void intel_release_load_detect_pipe(struct drm_connector *connector,
8799 struct intel_load_detect_pipe *old)
8800 {
8801 struct intel_encoder *intel_encoder =
8802 intel_attached_encoder(connector);
8803 struct drm_encoder *encoder = &intel_encoder->base;
8804 struct drm_crtc *crtc = encoder->crtc;
8805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8806
8807 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8808 connector->base.id, connector->name,
8809 encoder->base.id, encoder->name);
8810
8811 if (old->load_detect_temp) {
8812 to_intel_connector(connector)->new_encoder = NULL;
8813 intel_encoder->new_crtc = NULL;
8814 intel_crtc->new_enabled = false;
8815 intel_crtc->new_config = NULL;
8816 intel_set_mode(crtc, NULL, 0, 0, NULL);
8817
8818 if (old->release_fb) {
8819 drm_framebuffer_unregister_private(old->release_fb);
8820 drm_framebuffer_unreference(old->release_fb);
8821 }
8822
8823 return;
8824 }
8825
8826 /* Switch crtc and encoder back off if necessary */
8827 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8828 connector->funcs->dpms(connector, old->dpms_mode);
8829 }
8830
8831 static int i9xx_pll_refclk(struct drm_device *dev,
8832 const struct intel_crtc_config *pipe_config)
8833 {
8834 struct drm_i915_private *dev_priv = dev->dev_private;
8835 u32 dpll = pipe_config->dpll_hw_state.dpll;
8836
8837 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8838 return dev_priv->vbt.lvds_ssc_freq;
8839 else if (HAS_PCH_SPLIT(dev))
8840 return 120000;
8841 else if (!IS_GEN2(dev))
8842 return 96000;
8843 else
8844 return 48000;
8845 }
8846
8847 /* Returns the clock of the currently programmed mode of the given pipe. */
8848 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8849 struct intel_crtc_config *pipe_config)
8850 {
8851 struct drm_device *dev = crtc->base.dev;
8852 struct drm_i915_private *dev_priv = dev->dev_private;
8853 int pipe = pipe_config->cpu_transcoder;
8854 u32 dpll = pipe_config->dpll_hw_state.dpll;
8855 u32 fp;
8856 intel_clock_t clock;
8857 int refclk = i9xx_pll_refclk(dev, pipe_config);
8858
8859 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8860 fp = pipe_config->dpll_hw_state.fp0;
8861 else
8862 fp = pipe_config->dpll_hw_state.fp1;
8863
8864 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8865 if (IS_PINEVIEW(dev)) {
8866 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8867 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8868 } else {
8869 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8870 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8871 }
8872
8873 if (!IS_GEN2(dev)) {
8874 if (IS_PINEVIEW(dev))
8875 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8876 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8877 else
8878 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8879 DPLL_FPA01_P1_POST_DIV_SHIFT);
8880
8881 switch (dpll & DPLL_MODE_MASK) {
8882 case DPLLB_MODE_DAC_SERIAL:
8883 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8884 5 : 10;
8885 break;
8886 case DPLLB_MODE_LVDS:
8887 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8888 7 : 14;
8889 break;
8890 default:
8891 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8892 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8893 return;
8894 }
8895
8896 if (IS_PINEVIEW(dev))
8897 pineview_clock(refclk, &clock);
8898 else
8899 i9xx_clock(refclk, &clock);
8900 } else {
8901 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8902 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8903
8904 if (is_lvds) {
8905 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8906 DPLL_FPA01_P1_POST_DIV_SHIFT);
8907
8908 if (lvds & LVDS_CLKB_POWER_UP)
8909 clock.p2 = 7;
8910 else
8911 clock.p2 = 14;
8912 } else {
8913 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8914 clock.p1 = 2;
8915 else {
8916 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8917 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8918 }
8919 if (dpll & PLL_P2_DIVIDE_BY_4)
8920 clock.p2 = 4;
8921 else
8922 clock.p2 = 2;
8923 }
8924
8925 i9xx_clock(refclk, &clock);
8926 }
8927
8928 /*
8929 * This value includes pixel_multiplier. We will use
8930 * port_clock to compute adjusted_mode.crtc_clock in the
8931 * encoder's get_config() function.
8932 */
8933 pipe_config->port_clock = clock.dot;
8934 }
8935
8936 int intel_dotclock_calculate(int link_freq,
8937 const struct intel_link_m_n *m_n)
8938 {
8939 /*
8940 * The calculation for the data clock is:
8941 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8942 * But we want to avoid losing precison if possible, so:
8943 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8944 *
8945 * and the link clock is simpler:
8946 * link_clock = (m * link_clock) / n
8947 */
8948
8949 if (!m_n->link_n)
8950 return 0;
8951
8952 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8953 }
8954
8955 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8956 struct intel_crtc_config *pipe_config)
8957 {
8958 struct drm_device *dev = crtc->base.dev;
8959
8960 /* read out port_clock from the DPLL */
8961 i9xx_crtc_clock_get(crtc, pipe_config);
8962
8963 /*
8964 * This value does not include pixel_multiplier.
8965 * We will check that port_clock and adjusted_mode.crtc_clock
8966 * agree once we know their relationship in the encoder's
8967 * get_config() function.
8968 */
8969 pipe_config->adjusted_mode.crtc_clock =
8970 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8971 &pipe_config->fdi_m_n);
8972 }
8973
8974 /** Returns the currently programmed mode of the given pipe. */
8975 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8976 struct drm_crtc *crtc)
8977 {
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8980 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8981 struct drm_display_mode *mode;
8982 struct intel_crtc_config pipe_config;
8983 int htot = I915_READ(HTOTAL(cpu_transcoder));
8984 int hsync = I915_READ(HSYNC(cpu_transcoder));
8985 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8986 int vsync = I915_READ(VSYNC(cpu_transcoder));
8987 enum pipe pipe = intel_crtc->pipe;
8988
8989 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8990 if (!mode)
8991 return NULL;
8992
8993 /*
8994 * Construct a pipe_config sufficient for getting the clock info
8995 * back out of crtc_clock_get.
8996 *
8997 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8998 * to use a real value here instead.
8999 */
9000 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9001 pipe_config.pixel_multiplier = 1;
9002 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9003 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9004 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9005 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9006
9007 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9008 mode->hdisplay = (htot & 0xffff) + 1;
9009 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9010 mode->hsync_start = (hsync & 0xffff) + 1;
9011 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9012 mode->vdisplay = (vtot & 0xffff) + 1;
9013 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9014 mode->vsync_start = (vsync & 0xffff) + 1;
9015 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9016
9017 drm_mode_set_name(mode);
9018
9019 return mode;
9020 }
9021
9022 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9023 {
9024 struct drm_device *dev = crtc->dev;
9025 struct drm_i915_private *dev_priv = dev->dev_private;
9026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9027
9028 if (!HAS_GMCH_DISPLAY(dev))
9029 return;
9030
9031 if (!dev_priv->lvds_downclock_avail)
9032 return;
9033
9034 /*
9035 * Since this is called by a timer, we should never get here in
9036 * the manual case.
9037 */
9038 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9039 int pipe = intel_crtc->pipe;
9040 int dpll_reg = DPLL(pipe);
9041 int dpll;
9042
9043 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9044
9045 assert_panel_unlocked(dev_priv, pipe);
9046
9047 dpll = I915_READ(dpll_reg);
9048 dpll |= DISPLAY_RATE_SELECT_FPA1;
9049 I915_WRITE(dpll_reg, dpll);
9050 intel_wait_for_vblank(dev, pipe);
9051 dpll = I915_READ(dpll_reg);
9052 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9053 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9054 }
9055
9056 }
9057
9058 void intel_mark_busy(struct drm_device *dev)
9059 {
9060 struct drm_i915_private *dev_priv = dev->dev_private;
9061
9062 if (dev_priv->mm.busy)
9063 return;
9064
9065 intel_runtime_pm_get(dev_priv);
9066 i915_update_gfx_val(dev_priv);
9067 dev_priv->mm.busy = true;
9068 }
9069
9070 void intel_mark_idle(struct drm_device *dev)
9071 {
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073 struct drm_crtc *crtc;
9074
9075 if (!dev_priv->mm.busy)
9076 return;
9077
9078 dev_priv->mm.busy = false;
9079
9080 if (!i915.powersave)
9081 goto out;
9082
9083 for_each_crtc(dev, crtc) {
9084 if (!crtc->primary->fb)
9085 continue;
9086
9087 intel_decrease_pllclock(crtc);
9088 }
9089
9090 if (INTEL_INFO(dev)->gen >= 6)
9091 gen6_rps_idle(dev->dev_private);
9092
9093 out:
9094 intel_runtime_pm_put(dev_priv);
9095 }
9096
9097 static void intel_crtc_destroy(struct drm_crtc *crtc)
9098 {
9099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9100 struct drm_device *dev = crtc->dev;
9101 struct intel_unpin_work *work;
9102
9103 spin_lock_irq(&dev->event_lock);
9104 work = intel_crtc->unpin_work;
9105 intel_crtc->unpin_work = NULL;
9106 spin_unlock_irq(&dev->event_lock);
9107
9108 if (work) {
9109 cancel_work_sync(&work->work);
9110 kfree(work);
9111 }
9112
9113 drm_crtc_cleanup(crtc);
9114
9115 kfree(intel_crtc);
9116 }
9117
9118 static void intel_unpin_work_fn(struct work_struct *__work)
9119 {
9120 struct intel_unpin_work *work =
9121 container_of(__work, struct intel_unpin_work, work);
9122 struct drm_device *dev = work->crtc->dev;
9123 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9124
9125 mutex_lock(&dev->struct_mutex);
9126 intel_unpin_fb_obj(work->old_fb_obj);
9127 drm_gem_object_unreference(&work->pending_flip_obj->base);
9128 drm_gem_object_unreference(&work->old_fb_obj->base);
9129
9130 intel_update_fbc(dev);
9131 mutex_unlock(&dev->struct_mutex);
9132
9133 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9134
9135 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9136 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9137
9138 kfree(work);
9139 }
9140
9141 static void do_intel_finish_page_flip(struct drm_device *dev,
9142 struct drm_crtc *crtc)
9143 {
9144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9145 struct intel_unpin_work *work;
9146 unsigned long flags;
9147
9148 /* Ignore early vblank irqs */
9149 if (intel_crtc == NULL)
9150 return;
9151
9152 /*
9153 * This is called both by irq handlers and the reset code (to complete
9154 * lost pageflips) so needs the full irqsave spinlocks.
9155 */
9156 spin_lock_irqsave(&dev->event_lock, flags);
9157 work = intel_crtc->unpin_work;
9158
9159 /* Ensure we don't miss a work->pending update ... */
9160 smp_rmb();
9161
9162 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9163 spin_unlock_irqrestore(&dev->event_lock, flags);
9164 return;
9165 }
9166
9167 page_flip_completed(intel_crtc);
9168
9169 spin_unlock_irqrestore(&dev->event_lock, flags);
9170 }
9171
9172 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9173 {
9174 struct drm_i915_private *dev_priv = dev->dev_private;
9175 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9176
9177 do_intel_finish_page_flip(dev, crtc);
9178 }
9179
9180 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9181 {
9182 struct drm_i915_private *dev_priv = dev->dev_private;
9183 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9184
9185 do_intel_finish_page_flip(dev, crtc);
9186 }
9187
9188 /* Is 'a' after or equal to 'b'? */
9189 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9190 {
9191 return !((a - b) & 0x80000000);
9192 }
9193
9194 static bool page_flip_finished(struct intel_crtc *crtc)
9195 {
9196 struct drm_device *dev = crtc->base.dev;
9197 struct drm_i915_private *dev_priv = dev->dev_private;
9198
9199 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9200 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9201 return true;
9202
9203 /*
9204 * The relevant registers doen't exist on pre-ctg.
9205 * As the flip done interrupt doesn't trigger for mmio
9206 * flips on gmch platforms, a flip count check isn't
9207 * really needed there. But since ctg has the registers,
9208 * include it in the check anyway.
9209 */
9210 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9211 return true;
9212
9213 /*
9214 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9215 * used the same base address. In that case the mmio flip might
9216 * have completed, but the CS hasn't even executed the flip yet.
9217 *
9218 * A flip count check isn't enough as the CS might have updated
9219 * the base address just after start of vblank, but before we
9220 * managed to process the interrupt. This means we'd complete the
9221 * CS flip too soon.
9222 *
9223 * Combining both checks should get us a good enough result. It may
9224 * still happen that the CS flip has been executed, but has not
9225 * yet actually completed. But in case the base address is the same
9226 * anyway, we don't really care.
9227 */
9228 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9229 crtc->unpin_work->gtt_offset &&
9230 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9231 crtc->unpin_work->flip_count);
9232 }
9233
9234 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9235 {
9236 struct drm_i915_private *dev_priv = dev->dev_private;
9237 struct intel_crtc *intel_crtc =
9238 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9239 unsigned long flags;
9240
9241
9242 /*
9243 * This is called both by irq handlers and the reset code (to complete
9244 * lost pageflips) so needs the full irqsave spinlocks.
9245 *
9246 * NB: An MMIO update of the plane base pointer will also
9247 * generate a page-flip completion irq, i.e. every modeset
9248 * is also accompanied by a spurious intel_prepare_page_flip().
9249 */
9250 spin_lock_irqsave(&dev->event_lock, flags);
9251 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9252 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9253 spin_unlock_irqrestore(&dev->event_lock, flags);
9254 }
9255
9256 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9257 {
9258 /* Ensure that the work item is consistent when activating it ... */
9259 smp_wmb();
9260 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9261 /* and that it is marked active as soon as the irq could fire. */
9262 smp_wmb();
9263 }
9264
9265 static int intel_gen2_queue_flip(struct drm_device *dev,
9266 struct drm_crtc *crtc,
9267 struct drm_framebuffer *fb,
9268 struct drm_i915_gem_object *obj,
9269 struct intel_engine_cs *ring,
9270 uint32_t flags)
9271 {
9272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9273 u32 flip_mask;
9274 int ret;
9275
9276 ret = intel_ring_begin(ring, 6);
9277 if (ret)
9278 return ret;
9279
9280 /* Can't queue multiple flips, so wait for the previous
9281 * one to finish before executing the next.
9282 */
9283 if (intel_crtc->plane)
9284 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9285 else
9286 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9287 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9288 intel_ring_emit(ring, MI_NOOP);
9289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9291 intel_ring_emit(ring, fb->pitches[0]);
9292 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9293 intel_ring_emit(ring, 0); /* aux display base address, unused */
9294
9295 intel_mark_page_flip_active(intel_crtc);
9296 __intel_ring_advance(ring);
9297 return 0;
9298 }
9299
9300 static int intel_gen3_queue_flip(struct drm_device *dev,
9301 struct drm_crtc *crtc,
9302 struct drm_framebuffer *fb,
9303 struct drm_i915_gem_object *obj,
9304 struct intel_engine_cs *ring,
9305 uint32_t flags)
9306 {
9307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9308 u32 flip_mask;
9309 int ret;
9310
9311 ret = intel_ring_begin(ring, 6);
9312 if (ret)
9313 return ret;
9314
9315 if (intel_crtc->plane)
9316 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9317 else
9318 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9319 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9320 intel_ring_emit(ring, MI_NOOP);
9321 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9322 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9323 intel_ring_emit(ring, fb->pitches[0]);
9324 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9325 intel_ring_emit(ring, MI_NOOP);
9326
9327 intel_mark_page_flip_active(intel_crtc);
9328 __intel_ring_advance(ring);
9329 return 0;
9330 }
9331
9332 static int intel_gen4_queue_flip(struct drm_device *dev,
9333 struct drm_crtc *crtc,
9334 struct drm_framebuffer *fb,
9335 struct drm_i915_gem_object *obj,
9336 struct intel_engine_cs *ring,
9337 uint32_t flags)
9338 {
9339 struct drm_i915_private *dev_priv = dev->dev_private;
9340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9341 uint32_t pf, pipesrc;
9342 int ret;
9343
9344 ret = intel_ring_begin(ring, 4);
9345 if (ret)
9346 return ret;
9347
9348 /* i965+ uses the linear or tiled offsets from the
9349 * Display Registers (which do not change across a page-flip)
9350 * so we need only reprogram the base address.
9351 */
9352 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9353 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9354 intel_ring_emit(ring, fb->pitches[0]);
9355 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9356 obj->tiling_mode);
9357
9358 /* XXX Enabling the panel-fitter across page-flip is so far
9359 * untested on non-native modes, so ignore it for now.
9360 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9361 */
9362 pf = 0;
9363 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9364 intel_ring_emit(ring, pf | pipesrc);
9365
9366 intel_mark_page_flip_active(intel_crtc);
9367 __intel_ring_advance(ring);
9368 return 0;
9369 }
9370
9371 static int intel_gen6_queue_flip(struct drm_device *dev,
9372 struct drm_crtc *crtc,
9373 struct drm_framebuffer *fb,
9374 struct drm_i915_gem_object *obj,
9375 struct intel_engine_cs *ring,
9376 uint32_t flags)
9377 {
9378 struct drm_i915_private *dev_priv = dev->dev_private;
9379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9380 uint32_t pf, pipesrc;
9381 int ret;
9382
9383 ret = intel_ring_begin(ring, 4);
9384 if (ret)
9385 return ret;
9386
9387 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9388 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9389 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9390 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9391
9392 /* Contrary to the suggestions in the documentation,
9393 * "Enable Panel Fitter" does not seem to be required when page
9394 * flipping with a non-native mode, and worse causes a normal
9395 * modeset to fail.
9396 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9397 */
9398 pf = 0;
9399 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9400 intel_ring_emit(ring, pf | pipesrc);
9401
9402 intel_mark_page_flip_active(intel_crtc);
9403 __intel_ring_advance(ring);
9404 return 0;
9405 }
9406
9407 static int intel_gen7_queue_flip(struct drm_device *dev,
9408 struct drm_crtc *crtc,
9409 struct drm_framebuffer *fb,
9410 struct drm_i915_gem_object *obj,
9411 struct intel_engine_cs *ring,
9412 uint32_t flags)
9413 {
9414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9415 uint32_t plane_bit = 0;
9416 int len, ret;
9417
9418 switch (intel_crtc->plane) {
9419 case PLANE_A:
9420 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9421 break;
9422 case PLANE_B:
9423 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9424 break;
9425 case PLANE_C:
9426 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9427 break;
9428 default:
9429 WARN_ONCE(1, "unknown plane in flip command\n");
9430 return -ENODEV;
9431 }
9432
9433 len = 4;
9434 if (ring->id == RCS) {
9435 len += 6;
9436 /*
9437 * On Gen 8, SRM is now taking an extra dword to accommodate
9438 * 48bits addresses, and we need a NOOP for the batch size to
9439 * stay even.
9440 */
9441 if (IS_GEN8(dev))
9442 len += 2;
9443 }
9444
9445 /*
9446 * BSpec MI_DISPLAY_FLIP for IVB:
9447 * "The full packet must be contained within the same cache line."
9448 *
9449 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9450 * cacheline, if we ever start emitting more commands before
9451 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9452 * then do the cacheline alignment, and finally emit the
9453 * MI_DISPLAY_FLIP.
9454 */
9455 ret = intel_ring_cacheline_align(ring);
9456 if (ret)
9457 return ret;
9458
9459 ret = intel_ring_begin(ring, len);
9460 if (ret)
9461 return ret;
9462
9463 /* Unmask the flip-done completion message. Note that the bspec says that
9464 * we should do this for both the BCS and RCS, and that we must not unmask
9465 * more than one flip event at any time (or ensure that one flip message
9466 * can be sent by waiting for flip-done prior to queueing new flips).
9467 * Experimentation says that BCS works despite DERRMR masking all
9468 * flip-done completion events and that unmasking all planes at once
9469 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9470 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9471 */
9472 if (ring->id == RCS) {
9473 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9474 intel_ring_emit(ring, DERRMR);
9475 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9476 DERRMR_PIPEB_PRI_FLIP_DONE |
9477 DERRMR_PIPEC_PRI_FLIP_DONE));
9478 if (IS_GEN8(dev))
9479 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9480 MI_SRM_LRM_GLOBAL_GTT);
9481 else
9482 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9483 MI_SRM_LRM_GLOBAL_GTT);
9484 intel_ring_emit(ring, DERRMR);
9485 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9486 if (IS_GEN8(dev)) {
9487 intel_ring_emit(ring, 0);
9488 intel_ring_emit(ring, MI_NOOP);
9489 }
9490 }
9491
9492 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9493 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9494 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9495 intel_ring_emit(ring, (MI_NOOP));
9496
9497 intel_mark_page_flip_active(intel_crtc);
9498 __intel_ring_advance(ring);
9499 return 0;
9500 }
9501
9502 static bool use_mmio_flip(struct intel_engine_cs *ring,
9503 struct drm_i915_gem_object *obj)
9504 {
9505 /*
9506 * This is not being used for older platforms, because
9507 * non-availability of flip done interrupt forces us to use
9508 * CS flips. Older platforms derive flip done using some clever
9509 * tricks involving the flip_pending status bits and vblank irqs.
9510 * So using MMIO flips there would disrupt this mechanism.
9511 */
9512
9513 if (ring == NULL)
9514 return true;
9515
9516 if (INTEL_INFO(ring->dev)->gen < 5)
9517 return false;
9518
9519 if (i915.use_mmio_flip < 0)
9520 return false;
9521 else if (i915.use_mmio_flip > 0)
9522 return true;
9523 else if (i915.enable_execlists)
9524 return true;
9525 else
9526 return ring != obj->ring;
9527 }
9528
9529 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9530 {
9531 struct drm_device *dev = intel_crtc->base.dev;
9532 struct drm_i915_private *dev_priv = dev->dev_private;
9533 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9534 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9535 struct drm_i915_gem_object *obj = intel_fb->obj;
9536 const enum pipe pipe = intel_crtc->pipe;
9537 u32 ctl, stride;
9538
9539 ctl = I915_READ(PLANE_CTL(pipe, 0));
9540 ctl &= ~PLANE_CTL_TILED_MASK;
9541 if (obj->tiling_mode == I915_TILING_X)
9542 ctl |= PLANE_CTL_TILED_X;
9543
9544 /*
9545 * The stride is either expressed as a multiple of 64 bytes chunks for
9546 * linear buffers or in number of tiles for tiled buffers.
9547 */
9548 stride = fb->pitches[0] >> 6;
9549 if (obj->tiling_mode == I915_TILING_X)
9550 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9551
9552 /*
9553 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9554 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9555 */
9556 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9557 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9558
9559 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9560 POSTING_READ(PLANE_SURF(pipe, 0));
9561 }
9562
9563 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9564 {
9565 struct drm_device *dev = intel_crtc->base.dev;
9566 struct drm_i915_private *dev_priv = dev->dev_private;
9567 struct intel_framebuffer *intel_fb =
9568 to_intel_framebuffer(intel_crtc->base.primary->fb);
9569 struct drm_i915_gem_object *obj = intel_fb->obj;
9570 u32 dspcntr;
9571 u32 reg;
9572
9573 reg = DSPCNTR(intel_crtc->plane);
9574 dspcntr = I915_READ(reg);
9575
9576 if (obj->tiling_mode != I915_TILING_NONE)
9577 dspcntr |= DISPPLANE_TILED;
9578 else
9579 dspcntr &= ~DISPPLANE_TILED;
9580
9581 I915_WRITE(reg, dspcntr);
9582
9583 I915_WRITE(DSPSURF(intel_crtc->plane),
9584 intel_crtc->unpin_work->gtt_offset);
9585 POSTING_READ(DSPSURF(intel_crtc->plane));
9586
9587 }
9588
9589 /*
9590 * XXX: This is the temporary way to update the plane registers until we get
9591 * around to using the usual plane update functions for MMIO flips
9592 */
9593 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9594 {
9595 struct drm_device *dev = intel_crtc->base.dev;
9596 bool atomic_update;
9597 u32 start_vbl_count;
9598
9599 intel_mark_page_flip_active(intel_crtc);
9600
9601 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9602
9603 if (INTEL_INFO(dev)->gen >= 9)
9604 skl_do_mmio_flip(intel_crtc);
9605 else
9606 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9607 ilk_do_mmio_flip(intel_crtc);
9608
9609 if (atomic_update)
9610 intel_pipe_update_end(intel_crtc, start_vbl_count);
9611 }
9612
9613 static void intel_mmio_flip_work_func(struct work_struct *work)
9614 {
9615 struct intel_crtc *intel_crtc =
9616 container_of(work, struct intel_crtc, mmio_flip.work);
9617 struct intel_engine_cs *ring;
9618 uint32_t seqno;
9619
9620 seqno = intel_crtc->mmio_flip.seqno;
9621 ring = intel_crtc->mmio_flip.ring;
9622
9623 if (seqno)
9624 WARN_ON(__i915_wait_seqno(ring, seqno,
9625 intel_crtc->reset_counter,
9626 false, NULL, NULL) != 0);
9627
9628 intel_do_mmio_flip(intel_crtc);
9629 }
9630
9631 static int intel_queue_mmio_flip(struct drm_device *dev,
9632 struct drm_crtc *crtc,
9633 struct drm_framebuffer *fb,
9634 struct drm_i915_gem_object *obj,
9635 struct intel_engine_cs *ring,
9636 uint32_t flags)
9637 {
9638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9639
9640 intel_crtc->mmio_flip.seqno =
9641 i915_gem_request_get_seqno(obj->last_write_req);
9642 intel_crtc->mmio_flip.ring = obj->ring;
9643
9644 schedule_work(&intel_crtc->mmio_flip.work);
9645
9646 return 0;
9647 }
9648
9649 static int intel_gen9_queue_flip(struct drm_device *dev,
9650 struct drm_crtc *crtc,
9651 struct drm_framebuffer *fb,
9652 struct drm_i915_gem_object *obj,
9653 struct intel_engine_cs *ring,
9654 uint32_t flags)
9655 {
9656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9657 uint32_t plane = 0, stride;
9658 int ret;
9659
9660 switch(intel_crtc->pipe) {
9661 case PIPE_A:
9662 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9663 break;
9664 case PIPE_B:
9665 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9666 break;
9667 case PIPE_C:
9668 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9669 break;
9670 default:
9671 WARN_ONCE(1, "unknown plane in flip command\n");
9672 return -ENODEV;
9673 }
9674
9675 switch (obj->tiling_mode) {
9676 case I915_TILING_NONE:
9677 stride = fb->pitches[0] >> 6;
9678 break;
9679 case I915_TILING_X:
9680 stride = fb->pitches[0] >> 9;
9681 break;
9682 default:
9683 WARN_ONCE(1, "unknown tiling in flip command\n");
9684 return -ENODEV;
9685 }
9686
9687 ret = intel_ring_begin(ring, 10);
9688 if (ret)
9689 return ret;
9690
9691 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9692 intel_ring_emit(ring, DERRMR);
9693 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9694 DERRMR_PIPEB_PRI_FLIP_DONE |
9695 DERRMR_PIPEC_PRI_FLIP_DONE));
9696 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9697 MI_SRM_LRM_GLOBAL_GTT);
9698 intel_ring_emit(ring, DERRMR);
9699 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9700 intel_ring_emit(ring, 0);
9701
9702 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9703 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9704 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9705
9706 intel_mark_page_flip_active(intel_crtc);
9707 __intel_ring_advance(ring);
9708
9709 return 0;
9710 }
9711
9712 static int intel_default_queue_flip(struct drm_device *dev,
9713 struct drm_crtc *crtc,
9714 struct drm_framebuffer *fb,
9715 struct drm_i915_gem_object *obj,
9716 struct intel_engine_cs *ring,
9717 uint32_t flags)
9718 {
9719 return -ENODEV;
9720 }
9721
9722 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9723 struct drm_crtc *crtc)
9724 {
9725 struct drm_i915_private *dev_priv = dev->dev_private;
9726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9727 struct intel_unpin_work *work = intel_crtc->unpin_work;
9728 u32 addr;
9729
9730 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9731 return true;
9732
9733 if (!work->enable_stall_check)
9734 return false;
9735
9736 if (work->flip_ready_vblank == 0) {
9737 if (work->flip_queued_ring &&
9738 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9739 work->flip_queued_seqno))
9740 return false;
9741
9742 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9743 }
9744
9745 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9746 return false;
9747
9748 /* Potential stall - if we see that the flip has happened,
9749 * assume a missed interrupt. */
9750 if (INTEL_INFO(dev)->gen >= 4)
9751 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9752 else
9753 addr = I915_READ(DSPADDR(intel_crtc->plane));
9754
9755 /* There is a potential issue here with a false positive after a flip
9756 * to the same address. We could address this by checking for a
9757 * non-incrementing frame counter.
9758 */
9759 return addr == work->gtt_offset;
9760 }
9761
9762 void intel_check_page_flip(struct drm_device *dev, int pipe)
9763 {
9764 struct drm_i915_private *dev_priv = dev->dev_private;
9765 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9767
9768 WARN_ON(!in_irq());
9769
9770 if (crtc == NULL)
9771 return;
9772
9773 spin_lock(&dev->event_lock);
9774 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9775 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9776 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9777 page_flip_completed(intel_crtc);
9778 }
9779 spin_unlock(&dev->event_lock);
9780 }
9781
9782 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9783 struct drm_framebuffer *fb,
9784 struct drm_pending_vblank_event *event,
9785 uint32_t page_flip_flags)
9786 {
9787 struct drm_device *dev = crtc->dev;
9788 struct drm_i915_private *dev_priv = dev->dev_private;
9789 struct drm_framebuffer *old_fb = crtc->primary->fb;
9790 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9792 enum pipe pipe = intel_crtc->pipe;
9793 struct intel_unpin_work *work;
9794 struct intel_engine_cs *ring;
9795 int ret;
9796
9797 /*
9798 * drm_mode_page_flip_ioctl() should already catch this, but double
9799 * check to be safe. In the future we may enable pageflipping from
9800 * a disabled primary plane.
9801 */
9802 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9803 return -EBUSY;
9804
9805 /* Can't change pixel format via MI display flips. */
9806 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9807 return -EINVAL;
9808
9809 /*
9810 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9811 * Note that pitch changes could also affect these register.
9812 */
9813 if (INTEL_INFO(dev)->gen > 3 &&
9814 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9815 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9816 return -EINVAL;
9817
9818 if (i915_terminally_wedged(&dev_priv->gpu_error))
9819 goto out_hang;
9820
9821 work = kzalloc(sizeof(*work), GFP_KERNEL);
9822 if (work == NULL)
9823 return -ENOMEM;
9824
9825 work->event = event;
9826 work->crtc = crtc;
9827 work->old_fb_obj = intel_fb_obj(old_fb);
9828 INIT_WORK(&work->work, intel_unpin_work_fn);
9829
9830 ret = drm_crtc_vblank_get(crtc);
9831 if (ret)
9832 goto free_work;
9833
9834 /* We borrow the event spin lock for protecting unpin_work */
9835 spin_lock_irq(&dev->event_lock);
9836 if (intel_crtc->unpin_work) {
9837 /* Before declaring the flip queue wedged, check if
9838 * the hardware completed the operation behind our backs.
9839 */
9840 if (__intel_pageflip_stall_check(dev, crtc)) {
9841 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9842 page_flip_completed(intel_crtc);
9843 } else {
9844 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9845 spin_unlock_irq(&dev->event_lock);
9846
9847 drm_crtc_vblank_put(crtc);
9848 kfree(work);
9849 return -EBUSY;
9850 }
9851 }
9852 intel_crtc->unpin_work = work;
9853 spin_unlock_irq(&dev->event_lock);
9854
9855 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9856 flush_workqueue(dev_priv->wq);
9857
9858 ret = i915_mutex_lock_interruptible(dev);
9859 if (ret)
9860 goto cleanup;
9861
9862 /* Reference the objects for the scheduled work. */
9863 drm_gem_object_reference(&work->old_fb_obj->base);
9864 drm_gem_object_reference(&obj->base);
9865
9866 crtc->primary->fb = fb;
9867
9868 work->pending_flip_obj = obj;
9869
9870 atomic_inc(&intel_crtc->unpin_work_count);
9871 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9872
9873 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9874 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9875
9876 if (IS_VALLEYVIEW(dev)) {
9877 ring = &dev_priv->ring[BCS];
9878 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9879 /* vlv: DISPLAY_FLIP fails to change tiling */
9880 ring = NULL;
9881 } else if (IS_IVYBRIDGE(dev)) {
9882 ring = &dev_priv->ring[BCS];
9883 } else if (INTEL_INFO(dev)->gen >= 7) {
9884 ring = obj->ring;
9885 if (ring == NULL || ring->id != RCS)
9886 ring = &dev_priv->ring[BCS];
9887 } else {
9888 ring = &dev_priv->ring[RCS];
9889 }
9890
9891 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9892 if (ret)
9893 goto cleanup_pending;
9894
9895 work->gtt_offset =
9896 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9897
9898 if (use_mmio_flip(ring, obj)) {
9899 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9900 page_flip_flags);
9901 if (ret)
9902 goto cleanup_unpin;
9903
9904 work->flip_queued_seqno =
9905 i915_gem_request_get_seqno(obj->last_write_req);
9906 work->flip_queued_ring = obj->ring;
9907 } else {
9908 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9909 page_flip_flags);
9910 if (ret)
9911 goto cleanup_unpin;
9912
9913 work->flip_queued_seqno =
9914 i915_gem_request_get_seqno(intel_ring_get_request(ring));
9915 work->flip_queued_ring = ring;
9916 }
9917
9918 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9919 work->enable_stall_check = true;
9920
9921 i915_gem_track_fb(work->old_fb_obj, obj,
9922 INTEL_FRONTBUFFER_PRIMARY(pipe));
9923
9924 intel_disable_fbc(dev);
9925 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9926 mutex_unlock(&dev->struct_mutex);
9927
9928 trace_i915_flip_request(intel_crtc->plane, obj);
9929
9930 return 0;
9931
9932 cleanup_unpin:
9933 intel_unpin_fb_obj(obj);
9934 cleanup_pending:
9935 atomic_dec(&intel_crtc->unpin_work_count);
9936 crtc->primary->fb = old_fb;
9937 drm_gem_object_unreference(&work->old_fb_obj->base);
9938 drm_gem_object_unreference(&obj->base);
9939 mutex_unlock(&dev->struct_mutex);
9940
9941 cleanup:
9942 spin_lock_irq(&dev->event_lock);
9943 intel_crtc->unpin_work = NULL;
9944 spin_unlock_irq(&dev->event_lock);
9945
9946 drm_crtc_vblank_put(crtc);
9947 free_work:
9948 kfree(work);
9949
9950 if (ret == -EIO) {
9951 out_hang:
9952 intel_crtc_wait_for_pending_flips(crtc);
9953 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9954 if (ret == 0 && event) {
9955 spin_lock_irq(&dev->event_lock);
9956 drm_send_vblank_event(dev, pipe, event);
9957 spin_unlock_irq(&dev->event_lock);
9958 }
9959 }
9960 return ret;
9961 }
9962
9963 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9964 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9965 .load_lut = intel_crtc_load_lut,
9966 };
9967
9968 /**
9969 * intel_modeset_update_staged_output_state
9970 *
9971 * Updates the staged output configuration state, e.g. after we've read out the
9972 * current hw state.
9973 */
9974 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9975 {
9976 struct intel_crtc *crtc;
9977 struct intel_encoder *encoder;
9978 struct intel_connector *connector;
9979
9980 list_for_each_entry(connector, &dev->mode_config.connector_list,
9981 base.head) {
9982 connector->new_encoder =
9983 to_intel_encoder(connector->base.encoder);
9984 }
9985
9986 for_each_intel_encoder(dev, encoder) {
9987 encoder->new_crtc =
9988 to_intel_crtc(encoder->base.crtc);
9989 }
9990
9991 for_each_intel_crtc(dev, crtc) {
9992 crtc->new_enabled = crtc->base.enabled;
9993
9994 if (crtc->new_enabled)
9995 crtc->new_config = &crtc->config;
9996 else
9997 crtc->new_config = NULL;
9998 }
9999 }
10000
10001 /**
10002 * intel_modeset_commit_output_state
10003 *
10004 * This function copies the stage display pipe configuration to the real one.
10005 */
10006 static void intel_modeset_commit_output_state(struct drm_device *dev)
10007 {
10008 struct intel_crtc *crtc;
10009 struct intel_encoder *encoder;
10010 struct intel_connector *connector;
10011
10012 list_for_each_entry(connector, &dev->mode_config.connector_list,
10013 base.head) {
10014 connector->base.encoder = &connector->new_encoder->base;
10015 }
10016
10017 for_each_intel_encoder(dev, encoder) {
10018 encoder->base.crtc = &encoder->new_crtc->base;
10019 }
10020
10021 for_each_intel_crtc(dev, crtc) {
10022 crtc->base.enabled = crtc->new_enabled;
10023 }
10024 }
10025
10026 static void
10027 connected_sink_compute_bpp(struct intel_connector *connector,
10028 struct intel_crtc_config *pipe_config)
10029 {
10030 int bpp = pipe_config->pipe_bpp;
10031
10032 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10033 connector->base.base.id,
10034 connector->base.name);
10035
10036 /* Don't use an invalid EDID bpc value */
10037 if (connector->base.display_info.bpc &&
10038 connector->base.display_info.bpc * 3 < bpp) {
10039 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10040 bpp, connector->base.display_info.bpc*3);
10041 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10042 }
10043
10044 /* Clamp bpp to 8 on screens without EDID 1.4 */
10045 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10046 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10047 bpp);
10048 pipe_config->pipe_bpp = 24;
10049 }
10050 }
10051
10052 static int
10053 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10054 struct drm_framebuffer *fb,
10055 struct intel_crtc_config *pipe_config)
10056 {
10057 struct drm_device *dev = crtc->base.dev;
10058 struct intel_connector *connector;
10059 int bpp;
10060
10061 switch (fb->pixel_format) {
10062 case DRM_FORMAT_C8:
10063 bpp = 8*3; /* since we go through a colormap */
10064 break;
10065 case DRM_FORMAT_XRGB1555:
10066 case DRM_FORMAT_ARGB1555:
10067 /* checked in intel_framebuffer_init already */
10068 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10069 return -EINVAL;
10070 case DRM_FORMAT_RGB565:
10071 bpp = 6*3; /* min is 18bpp */
10072 break;
10073 case DRM_FORMAT_XBGR8888:
10074 case DRM_FORMAT_ABGR8888:
10075 /* checked in intel_framebuffer_init already */
10076 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10077 return -EINVAL;
10078 case DRM_FORMAT_XRGB8888:
10079 case DRM_FORMAT_ARGB8888:
10080 bpp = 8*3;
10081 break;
10082 case DRM_FORMAT_XRGB2101010:
10083 case DRM_FORMAT_ARGB2101010:
10084 case DRM_FORMAT_XBGR2101010:
10085 case DRM_FORMAT_ABGR2101010:
10086 /* checked in intel_framebuffer_init already */
10087 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10088 return -EINVAL;
10089 bpp = 10*3;
10090 break;
10091 /* TODO: gen4+ supports 16 bpc floating point, too. */
10092 default:
10093 DRM_DEBUG_KMS("unsupported depth\n");
10094 return -EINVAL;
10095 }
10096
10097 pipe_config->pipe_bpp = bpp;
10098
10099 /* Clamp display bpp to EDID value */
10100 list_for_each_entry(connector, &dev->mode_config.connector_list,
10101 base.head) {
10102 if (!connector->new_encoder ||
10103 connector->new_encoder->new_crtc != crtc)
10104 continue;
10105
10106 connected_sink_compute_bpp(connector, pipe_config);
10107 }
10108
10109 return bpp;
10110 }
10111
10112 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10113 {
10114 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10115 "type: 0x%x flags: 0x%x\n",
10116 mode->crtc_clock,
10117 mode->crtc_hdisplay, mode->crtc_hsync_start,
10118 mode->crtc_hsync_end, mode->crtc_htotal,
10119 mode->crtc_vdisplay, mode->crtc_vsync_start,
10120 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10121 }
10122
10123 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10124 struct intel_crtc_config *pipe_config,
10125 const char *context)
10126 {
10127 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10128 context, pipe_name(crtc->pipe));
10129
10130 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10131 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10132 pipe_config->pipe_bpp, pipe_config->dither);
10133 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10134 pipe_config->has_pch_encoder,
10135 pipe_config->fdi_lanes,
10136 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10137 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10138 pipe_config->fdi_m_n.tu);
10139 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10140 pipe_config->has_dp_encoder,
10141 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10142 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10143 pipe_config->dp_m_n.tu);
10144
10145 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10146 pipe_config->has_dp_encoder,
10147 pipe_config->dp_m2_n2.gmch_m,
10148 pipe_config->dp_m2_n2.gmch_n,
10149 pipe_config->dp_m2_n2.link_m,
10150 pipe_config->dp_m2_n2.link_n,
10151 pipe_config->dp_m2_n2.tu);
10152
10153 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10154 pipe_config->has_audio,
10155 pipe_config->has_infoframe);
10156
10157 DRM_DEBUG_KMS("requested mode:\n");
10158 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10159 DRM_DEBUG_KMS("adjusted mode:\n");
10160 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10161 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10162 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10163 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10164 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10165 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10166 pipe_config->gmch_pfit.control,
10167 pipe_config->gmch_pfit.pgm_ratios,
10168 pipe_config->gmch_pfit.lvds_border_bits);
10169 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10170 pipe_config->pch_pfit.pos,
10171 pipe_config->pch_pfit.size,
10172 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10173 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10174 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10175 }
10176
10177 static bool encoders_cloneable(const struct intel_encoder *a,
10178 const struct intel_encoder *b)
10179 {
10180 /* masks could be asymmetric, so check both ways */
10181 return a == b || (a->cloneable & (1 << b->type) &&
10182 b->cloneable & (1 << a->type));
10183 }
10184
10185 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10186 struct intel_encoder *encoder)
10187 {
10188 struct drm_device *dev = crtc->base.dev;
10189 struct intel_encoder *source_encoder;
10190
10191 for_each_intel_encoder(dev, source_encoder) {
10192 if (source_encoder->new_crtc != crtc)
10193 continue;
10194
10195 if (!encoders_cloneable(encoder, source_encoder))
10196 return false;
10197 }
10198
10199 return true;
10200 }
10201
10202 static bool check_encoder_cloning(struct intel_crtc *crtc)
10203 {
10204 struct drm_device *dev = crtc->base.dev;
10205 struct intel_encoder *encoder;
10206
10207 for_each_intel_encoder(dev, encoder) {
10208 if (encoder->new_crtc != crtc)
10209 continue;
10210
10211 if (!check_single_encoder_cloning(crtc, encoder))
10212 return false;
10213 }
10214
10215 return true;
10216 }
10217
10218 static bool check_digital_port_conflicts(struct drm_device *dev)
10219 {
10220 struct intel_connector *connector;
10221 unsigned int used_ports = 0;
10222
10223 /*
10224 * Walk the connector list instead of the encoder
10225 * list to detect the problem on ddi platforms
10226 * where there's just one encoder per digital port.
10227 */
10228 list_for_each_entry(connector,
10229 &dev->mode_config.connector_list, base.head) {
10230 struct intel_encoder *encoder = connector->new_encoder;
10231
10232 if (!encoder)
10233 continue;
10234
10235 WARN_ON(!encoder->new_crtc);
10236
10237 switch (encoder->type) {
10238 unsigned int port_mask;
10239 case INTEL_OUTPUT_UNKNOWN:
10240 if (WARN_ON(!HAS_DDI(dev)))
10241 break;
10242 case INTEL_OUTPUT_DISPLAYPORT:
10243 case INTEL_OUTPUT_HDMI:
10244 case INTEL_OUTPUT_EDP:
10245 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10246
10247 /* the same port mustn't appear more than once */
10248 if (used_ports & port_mask)
10249 return false;
10250
10251 used_ports |= port_mask;
10252 default:
10253 break;
10254 }
10255 }
10256
10257 return true;
10258 }
10259
10260 static struct intel_crtc_config *
10261 intel_modeset_pipe_config(struct drm_crtc *crtc,
10262 struct drm_framebuffer *fb,
10263 struct drm_display_mode *mode)
10264 {
10265 struct drm_device *dev = crtc->dev;
10266 struct intel_encoder *encoder;
10267 struct intel_crtc_config *pipe_config;
10268 int plane_bpp, ret = -EINVAL;
10269 bool retry = true;
10270
10271 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10272 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10273 return ERR_PTR(-EINVAL);
10274 }
10275
10276 if (!check_digital_port_conflicts(dev)) {
10277 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10278 return ERR_PTR(-EINVAL);
10279 }
10280
10281 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10282 if (!pipe_config)
10283 return ERR_PTR(-ENOMEM);
10284
10285 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10286 drm_mode_copy(&pipe_config->requested_mode, mode);
10287
10288 pipe_config->cpu_transcoder =
10289 (enum transcoder) to_intel_crtc(crtc)->pipe;
10290 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10291
10292 /*
10293 * Sanitize sync polarity flags based on requested ones. If neither
10294 * positive or negative polarity is requested, treat this as meaning
10295 * negative polarity.
10296 */
10297 if (!(pipe_config->adjusted_mode.flags &
10298 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10299 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10300
10301 if (!(pipe_config->adjusted_mode.flags &
10302 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10303 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10304
10305 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10306 * plane pixel format and any sink constraints into account. Returns the
10307 * source plane bpp so that dithering can be selected on mismatches
10308 * after encoders and crtc also have had their say. */
10309 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10310 fb, pipe_config);
10311 if (plane_bpp < 0)
10312 goto fail;
10313
10314 /*
10315 * Determine the real pipe dimensions. Note that stereo modes can
10316 * increase the actual pipe size due to the frame doubling and
10317 * insertion of additional space for blanks between the frame. This
10318 * is stored in the crtc timings. We use the requested mode to do this
10319 * computation to clearly distinguish it from the adjusted mode, which
10320 * can be changed by the connectors in the below retry loop.
10321 */
10322 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10323 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10324 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10325
10326 encoder_retry:
10327 /* Ensure the port clock defaults are reset when retrying. */
10328 pipe_config->port_clock = 0;
10329 pipe_config->pixel_multiplier = 1;
10330
10331 /* Fill in default crtc timings, allow encoders to overwrite them. */
10332 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10333
10334 /* Pass our mode to the connectors and the CRTC to give them a chance to
10335 * adjust it according to limitations or connector properties, and also
10336 * a chance to reject the mode entirely.
10337 */
10338 for_each_intel_encoder(dev, encoder) {
10339
10340 if (&encoder->new_crtc->base != crtc)
10341 continue;
10342
10343 if (!(encoder->compute_config(encoder, pipe_config))) {
10344 DRM_DEBUG_KMS("Encoder config failure\n");
10345 goto fail;
10346 }
10347 }
10348
10349 /* Set default port clock if not overwritten by the encoder. Needs to be
10350 * done afterwards in case the encoder adjusts the mode. */
10351 if (!pipe_config->port_clock)
10352 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10353 * pipe_config->pixel_multiplier;
10354
10355 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10356 if (ret < 0) {
10357 DRM_DEBUG_KMS("CRTC fixup failed\n");
10358 goto fail;
10359 }
10360
10361 if (ret == RETRY) {
10362 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10363 ret = -EINVAL;
10364 goto fail;
10365 }
10366
10367 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10368 retry = false;
10369 goto encoder_retry;
10370 }
10371
10372 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10373 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10374 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10375
10376 return pipe_config;
10377 fail:
10378 kfree(pipe_config);
10379 return ERR_PTR(ret);
10380 }
10381
10382 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10383 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10384 static void
10385 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10386 unsigned *prepare_pipes, unsigned *disable_pipes)
10387 {
10388 struct intel_crtc *intel_crtc;
10389 struct drm_device *dev = crtc->dev;
10390 struct intel_encoder *encoder;
10391 struct intel_connector *connector;
10392 struct drm_crtc *tmp_crtc;
10393
10394 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10395
10396 /* Check which crtcs have changed outputs connected to them, these need
10397 * to be part of the prepare_pipes mask. We don't (yet) support global
10398 * modeset across multiple crtcs, so modeset_pipes will only have one
10399 * bit set at most. */
10400 list_for_each_entry(connector, &dev->mode_config.connector_list,
10401 base.head) {
10402 if (connector->base.encoder == &connector->new_encoder->base)
10403 continue;
10404
10405 if (connector->base.encoder) {
10406 tmp_crtc = connector->base.encoder->crtc;
10407
10408 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10409 }
10410
10411 if (connector->new_encoder)
10412 *prepare_pipes |=
10413 1 << connector->new_encoder->new_crtc->pipe;
10414 }
10415
10416 for_each_intel_encoder(dev, encoder) {
10417 if (encoder->base.crtc == &encoder->new_crtc->base)
10418 continue;
10419
10420 if (encoder->base.crtc) {
10421 tmp_crtc = encoder->base.crtc;
10422
10423 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10424 }
10425
10426 if (encoder->new_crtc)
10427 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10428 }
10429
10430 /* Check for pipes that will be enabled/disabled ... */
10431 for_each_intel_crtc(dev, intel_crtc) {
10432 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10433 continue;
10434
10435 if (!intel_crtc->new_enabled)
10436 *disable_pipes |= 1 << intel_crtc->pipe;
10437 else
10438 *prepare_pipes |= 1 << intel_crtc->pipe;
10439 }
10440
10441
10442 /* set_mode is also used to update properties on life display pipes. */
10443 intel_crtc = to_intel_crtc(crtc);
10444 if (intel_crtc->new_enabled)
10445 *prepare_pipes |= 1 << intel_crtc->pipe;
10446
10447 /*
10448 * For simplicity do a full modeset on any pipe where the output routing
10449 * changed. We could be more clever, but that would require us to be
10450 * more careful with calling the relevant encoder->mode_set functions.
10451 */
10452 if (*prepare_pipes)
10453 *modeset_pipes = *prepare_pipes;
10454
10455 /* ... and mask these out. */
10456 *modeset_pipes &= ~(*disable_pipes);
10457 *prepare_pipes &= ~(*disable_pipes);
10458
10459 /*
10460 * HACK: We don't (yet) fully support global modesets. intel_set_config
10461 * obies this rule, but the modeset restore mode of
10462 * intel_modeset_setup_hw_state does not.
10463 */
10464 *modeset_pipes &= 1 << intel_crtc->pipe;
10465 *prepare_pipes &= 1 << intel_crtc->pipe;
10466
10467 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10468 *modeset_pipes, *prepare_pipes, *disable_pipes);
10469 }
10470
10471 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10472 {
10473 struct drm_encoder *encoder;
10474 struct drm_device *dev = crtc->dev;
10475
10476 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10477 if (encoder->crtc == crtc)
10478 return true;
10479
10480 return false;
10481 }
10482
10483 static void
10484 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10485 {
10486 struct drm_i915_private *dev_priv = dev->dev_private;
10487 struct intel_encoder *intel_encoder;
10488 struct intel_crtc *intel_crtc;
10489 struct drm_connector *connector;
10490
10491 intel_shared_dpll_commit(dev_priv);
10492
10493 for_each_intel_encoder(dev, intel_encoder) {
10494 if (!intel_encoder->base.crtc)
10495 continue;
10496
10497 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10498
10499 if (prepare_pipes & (1 << intel_crtc->pipe))
10500 intel_encoder->connectors_active = false;
10501 }
10502
10503 intel_modeset_commit_output_state(dev);
10504
10505 /* Double check state. */
10506 for_each_intel_crtc(dev, intel_crtc) {
10507 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10508 WARN_ON(intel_crtc->new_config &&
10509 intel_crtc->new_config != &intel_crtc->config);
10510 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10511 }
10512
10513 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10514 if (!connector->encoder || !connector->encoder->crtc)
10515 continue;
10516
10517 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10518
10519 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10520 struct drm_property *dpms_property =
10521 dev->mode_config.dpms_property;
10522
10523 connector->dpms = DRM_MODE_DPMS_ON;
10524 drm_object_property_set_value(&connector->base,
10525 dpms_property,
10526 DRM_MODE_DPMS_ON);
10527
10528 intel_encoder = to_intel_encoder(connector->encoder);
10529 intel_encoder->connectors_active = true;
10530 }
10531 }
10532
10533 }
10534
10535 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10536 {
10537 int diff;
10538
10539 if (clock1 == clock2)
10540 return true;
10541
10542 if (!clock1 || !clock2)
10543 return false;
10544
10545 diff = abs(clock1 - clock2);
10546
10547 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10548 return true;
10549
10550 return false;
10551 }
10552
10553 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10554 list_for_each_entry((intel_crtc), \
10555 &(dev)->mode_config.crtc_list, \
10556 base.head) \
10557 if (mask & (1 <<(intel_crtc)->pipe))
10558
10559 static bool
10560 intel_pipe_config_compare(struct drm_device *dev,
10561 struct intel_crtc_config *current_config,
10562 struct intel_crtc_config *pipe_config)
10563 {
10564 #define PIPE_CONF_CHECK_X(name) \
10565 if (current_config->name != pipe_config->name) { \
10566 DRM_ERROR("mismatch in " #name " " \
10567 "(expected 0x%08x, found 0x%08x)\n", \
10568 current_config->name, \
10569 pipe_config->name); \
10570 return false; \
10571 }
10572
10573 #define PIPE_CONF_CHECK_I(name) \
10574 if (current_config->name != pipe_config->name) { \
10575 DRM_ERROR("mismatch in " #name " " \
10576 "(expected %i, found %i)\n", \
10577 current_config->name, \
10578 pipe_config->name); \
10579 return false; \
10580 }
10581
10582 /* This is required for BDW+ where there is only one set of registers for
10583 * switching between high and low RR.
10584 * This macro can be used whenever a comparison has to be made between one
10585 * hw state and multiple sw state variables.
10586 */
10587 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10588 if ((current_config->name != pipe_config->name) && \
10589 (current_config->alt_name != pipe_config->name)) { \
10590 DRM_ERROR("mismatch in " #name " " \
10591 "(expected %i or %i, found %i)\n", \
10592 current_config->name, \
10593 current_config->alt_name, \
10594 pipe_config->name); \
10595 return false; \
10596 }
10597
10598 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10599 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10600 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10601 "(expected %i, found %i)\n", \
10602 current_config->name & (mask), \
10603 pipe_config->name & (mask)); \
10604 return false; \
10605 }
10606
10607 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10608 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10609 DRM_ERROR("mismatch in " #name " " \
10610 "(expected %i, found %i)\n", \
10611 current_config->name, \
10612 pipe_config->name); \
10613 return false; \
10614 }
10615
10616 #define PIPE_CONF_QUIRK(quirk) \
10617 ((current_config->quirks | pipe_config->quirks) & (quirk))
10618
10619 PIPE_CONF_CHECK_I(cpu_transcoder);
10620
10621 PIPE_CONF_CHECK_I(has_pch_encoder);
10622 PIPE_CONF_CHECK_I(fdi_lanes);
10623 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10624 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10625 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10626 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10627 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10628
10629 PIPE_CONF_CHECK_I(has_dp_encoder);
10630
10631 if (INTEL_INFO(dev)->gen < 8) {
10632 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10633 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10634 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10635 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10636 PIPE_CONF_CHECK_I(dp_m_n.tu);
10637
10638 if (current_config->has_drrs) {
10639 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10640 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10641 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10642 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10643 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10644 }
10645 } else {
10646 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10647 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10648 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10649 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10650 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10651 }
10652
10653 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10654 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10655 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10656 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10657 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10658 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10659
10660 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10661 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10662 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10663 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10664 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10665 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10666
10667 PIPE_CONF_CHECK_I(pixel_multiplier);
10668 PIPE_CONF_CHECK_I(has_hdmi_sink);
10669 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10670 IS_VALLEYVIEW(dev))
10671 PIPE_CONF_CHECK_I(limited_color_range);
10672 PIPE_CONF_CHECK_I(has_infoframe);
10673
10674 PIPE_CONF_CHECK_I(has_audio);
10675
10676 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10677 DRM_MODE_FLAG_INTERLACE);
10678
10679 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10680 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10681 DRM_MODE_FLAG_PHSYNC);
10682 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10683 DRM_MODE_FLAG_NHSYNC);
10684 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10685 DRM_MODE_FLAG_PVSYNC);
10686 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10687 DRM_MODE_FLAG_NVSYNC);
10688 }
10689
10690 PIPE_CONF_CHECK_I(pipe_src_w);
10691 PIPE_CONF_CHECK_I(pipe_src_h);
10692
10693 /*
10694 * FIXME: BIOS likes to set up a cloned config with lvds+external
10695 * screen. Since we don't yet re-compute the pipe config when moving
10696 * just the lvds port away to another pipe the sw tracking won't match.
10697 *
10698 * Proper atomic modesets with recomputed global state will fix this.
10699 * Until then just don't check gmch state for inherited modes.
10700 */
10701 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10702 PIPE_CONF_CHECK_I(gmch_pfit.control);
10703 /* pfit ratios are autocomputed by the hw on gen4+ */
10704 if (INTEL_INFO(dev)->gen < 4)
10705 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10706 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10707 }
10708
10709 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10710 if (current_config->pch_pfit.enabled) {
10711 PIPE_CONF_CHECK_I(pch_pfit.pos);
10712 PIPE_CONF_CHECK_I(pch_pfit.size);
10713 }
10714
10715 /* BDW+ don't expose a synchronous way to read the state */
10716 if (IS_HASWELL(dev))
10717 PIPE_CONF_CHECK_I(ips_enabled);
10718
10719 PIPE_CONF_CHECK_I(double_wide);
10720
10721 PIPE_CONF_CHECK_X(ddi_pll_sel);
10722
10723 PIPE_CONF_CHECK_I(shared_dpll);
10724 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10725 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10726 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10727 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10728 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10729 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10730 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10731 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10732
10733 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10734 PIPE_CONF_CHECK_I(pipe_bpp);
10735
10736 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10737 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10738
10739 #undef PIPE_CONF_CHECK_X
10740 #undef PIPE_CONF_CHECK_I
10741 #undef PIPE_CONF_CHECK_I_ALT
10742 #undef PIPE_CONF_CHECK_FLAGS
10743 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10744 #undef PIPE_CONF_QUIRK
10745
10746 return true;
10747 }
10748
10749 static void check_wm_state(struct drm_device *dev)
10750 {
10751 struct drm_i915_private *dev_priv = dev->dev_private;
10752 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10753 struct intel_crtc *intel_crtc;
10754 int plane;
10755
10756 if (INTEL_INFO(dev)->gen < 9)
10757 return;
10758
10759 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10760 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10761
10762 for_each_intel_crtc(dev, intel_crtc) {
10763 struct skl_ddb_entry *hw_entry, *sw_entry;
10764 const enum pipe pipe = intel_crtc->pipe;
10765
10766 if (!intel_crtc->active)
10767 continue;
10768
10769 /* planes */
10770 for_each_plane(pipe, plane) {
10771 hw_entry = &hw_ddb.plane[pipe][plane];
10772 sw_entry = &sw_ddb->plane[pipe][plane];
10773
10774 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10775 continue;
10776
10777 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10778 "(expected (%u,%u), found (%u,%u))\n",
10779 pipe_name(pipe), plane + 1,
10780 sw_entry->start, sw_entry->end,
10781 hw_entry->start, hw_entry->end);
10782 }
10783
10784 /* cursor */
10785 hw_entry = &hw_ddb.cursor[pipe];
10786 sw_entry = &sw_ddb->cursor[pipe];
10787
10788 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10789 continue;
10790
10791 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10792 "(expected (%u,%u), found (%u,%u))\n",
10793 pipe_name(pipe),
10794 sw_entry->start, sw_entry->end,
10795 hw_entry->start, hw_entry->end);
10796 }
10797 }
10798
10799 static void
10800 check_connector_state(struct drm_device *dev)
10801 {
10802 struct intel_connector *connector;
10803
10804 list_for_each_entry(connector, &dev->mode_config.connector_list,
10805 base.head) {
10806 /* This also checks the encoder/connector hw state with the
10807 * ->get_hw_state callbacks. */
10808 intel_connector_check_state(connector);
10809
10810 WARN(&connector->new_encoder->base != connector->base.encoder,
10811 "connector's staged encoder doesn't match current encoder\n");
10812 }
10813 }
10814
10815 static void
10816 check_encoder_state(struct drm_device *dev)
10817 {
10818 struct intel_encoder *encoder;
10819 struct intel_connector *connector;
10820
10821 for_each_intel_encoder(dev, encoder) {
10822 bool enabled = false;
10823 bool active = false;
10824 enum pipe pipe, tracked_pipe;
10825
10826 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10827 encoder->base.base.id,
10828 encoder->base.name);
10829
10830 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10831 "encoder's stage crtc doesn't match current crtc\n");
10832 WARN(encoder->connectors_active && !encoder->base.crtc,
10833 "encoder's active_connectors set, but no crtc\n");
10834
10835 list_for_each_entry(connector, &dev->mode_config.connector_list,
10836 base.head) {
10837 if (connector->base.encoder != &encoder->base)
10838 continue;
10839 enabled = true;
10840 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10841 active = true;
10842 }
10843 /*
10844 * for MST connectors if we unplug the connector is gone
10845 * away but the encoder is still connected to a crtc
10846 * until a modeset happens in response to the hotplug.
10847 */
10848 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10849 continue;
10850
10851 WARN(!!encoder->base.crtc != enabled,
10852 "encoder's enabled state mismatch "
10853 "(expected %i, found %i)\n",
10854 !!encoder->base.crtc, enabled);
10855 WARN(active && !encoder->base.crtc,
10856 "active encoder with no crtc\n");
10857
10858 WARN(encoder->connectors_active != active,
10859 "encoder's computed active state doesn't match tracked active state "
10860 "(expected %i, found %i)\n", active, encoder->connectors_active);
10861
10862 active = encoder->get_hw_state(encoder, &pipe);
10863 WARN(active != encoder->connectors_active,
10864 "encoder's hw state doesn't match sw tracking "
10865 "(expected %i, found %i)\n",
10866 encoder->connectors_active, active);
10867
10868 if (!encoder->base.crtc)
10869 continue;
10870
10871 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10872 WARN(active && pipe != tracked_pipe,
10873 "active encoder's pipe doesn't match"
10874 "(expected %i, found %i)\n",
10875 tracked_pipe, pipe);
10876
10877 }
10878 }
10879
10880 static void
10881 check_crtc_state(struct drm_device *dev)
10882 {
10883 struct drm_i915_private *dev_priv = dev->dev_private;
10884 struct intel_crtc *crtc;
10885 struct intel_encoder *encoder;
10886 struct intel_crtc_config pipe_config;
10887
10888 for_each_intel_crtc(dev, crtc) {
10889 bool enabled = false;
10890 bool active = false;
10891
10892 memset(&pipe_config, 0, sizeof(pipe_config));
10893
10894 DRM_DEBUG_KMS("[CRTC:%d]\n",
10895 crtc->base.base.id);
10896
10897 WARN(crtc->active && !crtc->base.enabled,
10898 "active crtc, but not enabled in sw tracking\n");
10899
10900 for_each_intel_encoder(dev, encoder) {
10901 if (encoder->base.crtc != &crtc->base)
10902 continue;
10903 enabled = true;
10904 if (encoder->connectors_active)
10905 active = true;
10906 }
10907
10908 WARN(active != crtc->active,
10909 "crtc's computed active state doesn't match tracked active state "
10910 "(expected %i, found %i)\n", active, crtc->active);
10911 WARN(enabled != crtc->base.enabled,
10912 "crtc's computed enabled state doesn't match tracked enabled state "
10913 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10914
10915 active = dev_priv->display.get_pipe_config(crtc,
10916 &pipe_config);
10917
10918 /* hw state is inconsistent with the pipe quirk */
10919 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10920 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10921 active = crtc->active;
10922
10923 for_each_intel_encoder(dev, encoder) {
10924 enum pipe pipe;
10925 if (encoder->base.crtc != &crtc->base)
10926 continue;
10927 if (encoder->get_hw_state(encoder, &pipe))
10928 encoder->get_config(encoder, &pipe_config);
10929 }
10930
10931 WARN(crtc->active != active,
10932 "crtc active state doesn't match with hw state "
10933 "(expected %i, found %i)\n", crtc->active, active);
10934
10935 if (active &&
10936 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10937 WARN(1, "pipe state doesn't match!\n");
10938 intel_dump_pipe_config(crtc, &pipe_config,
10939 "[hw state]");
10940 intel_dump_pipe_config(crtc, &crtc->config,
10941 "[sw state]");
10942 }
10943 }
10944 }
10945
10946 static void
10947 check_shared_dpll_state(struct drm_device *dev)
10948 {
10949 struct drm_i915_private *dev_priv = dev->dev_private;
10950 struct intel_crtc *crtc;
10951 struct intel_dpll_hw_state dpll_hw_state;
10952 int i;
10953
10954 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10955 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10956 int enabled_crtcs = 0, active_crtcs = 0;
10957 bool active;
10958
10959 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10960
10961 DRM_DEBUG_KMS("%s\n", pll->name);
10962
10963 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10964
10965 WARN(pll->active > hweight32(pll->config.crtc_mask),
10966 "more active pll users than references: %i vs %i\n",
10967 pll->active, hweight32(pll->config.crtc_mask));
10968 WARN(pll->active && !pll->on,
10969 "pll in active use but not on in sw tracking\n");
10970 WARN(pll->on && !pll->active,
10971 "pll in on but not on in use in sw tracking\n");
10972 WARN(pll->on != active,
10973 "pll on state mismatch (expected %i, found %i)\n",
10974 pll->on, active);
10975
10976 for_each_intel_crtc(dev, crtc) {
10977 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10978 enabled_crtcs++;
10979 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10980 active_crtcs++;
10981 }
10982 WARN(pll->active != active_crtcs,
10983 "pll active crtcs mismatch (expected %i, found %i)\n",
10984 pll->active, active_crtcs);
10985 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10986 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10987 hweight32(pll->config.crtc_mask), enabled_crtcs);
10988
10989 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10990 sizeof(dpll_hw_state)),
10991 "pll hw state mismatch\n");
10992 }
10993 }
10994
10995 void
10996 intel_modeset_check_state(struct drm_device *dev)
10997 {
10998 check_wm_state(dev);
10999 check_connector_state(dev);
11000 check_encoder_state(dev);
11001 check_crtc_state(dev);
11002 check_shared_dpll_state(dev);
11003 }
11004
11005 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11006 int dotclock)
11007 {
11008 /*
11009 * FDI already provided one idea for the dotclock.
11010 * Yell if the encoder disagrees.
11011 */
11012 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11013 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11014 pipe_config->adjusted_mode.crtc_clock, dotclock);
11015 }
11016
11017 static void update_scanline_offset(struct intel_crtc *crtc)
11018 {
11019 struct drm_device *dev = crtc->base.dev;
11020
11021 /*
11022 * The scanline counter increments at the leading edge of hsync.
11023 *
11024 * On most platforms it starts counting from vtotal-1 on the
11025 * first active line. That means the scanline counter value is
11026 * always one less than what we would expect. Ie. just after
11027 * start of vblank, which also occurs at start of hsync (on the
11028 * last active line), the scanline counter will read vblank_start-1.
11029 *
11030 * On gen2 the scanline counter starts counting from 1 instead
11031 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11032 * to keep the value positive), instead of adding one.
11033 *
11034 * On HSW+ the behaviour of the scanline counter depends on the output
11035 * type. For DP ports it behaves like most other platforms, but on HDMI
11036 * there's an extra 1 line difference. So we need to add two instead of
11037 * one to the value.
11038 */
11039 if (IS_GEN2(dev)) {
11040 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11041 int vtotal;
11042
11043 vtotal = mode->crtc_vtotal;
11044 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11045 vtotal /= 2;
11046
11047 crtc->scanline_offset = vtotal - 1;
11048 } else if (HAS_DDI(dev) &&
11049 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11050 crtc->scanline_offset = 2;
11051 } else
11052 crtc->scanline_offset = 1;
11053 }
11054
11055 static struct intel_crtc_config *
11056 intel_modeset_compute_config(struct drm_crtc *crtc,
11057 struct drm_display_mode *mode,
11058 struct drm_framebuffer *fb,
11059 unsigned *modeset_pipes,
11060 unsigned *prepare_pipes,
11061 unsigned *disable_pipes)
11062 {
11063 struct intel_crtc_config *pipe_config = NULL;
11064
11065 intel_modeset_affected_pipes(crtc, modeset_pipes,
11066 prepare_pipes, disable_pipes);
11067
11068 if ((*modeset_pipes) == 0)
11069 goto out;
11070
11071 /*
11072 * Note this needs changes when we start tracking multiple modes
11073 * and crtcs. At that point we'll need to compute the whole config
11074 * (i.e. one pipe_config for each crtc) rather than just the one
11075 * for this crtc.
11076 */
11077 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11078 if (IS_ERR(pipe_config)) {
11079 goto out;
11080 }
11081 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11082 "[modeset]");
11083
11084 out:
11085 return pipe_config;
11086 }
11087
11088 static int __intel_set_mode(struct drm_crtc *crtc,
11089 struct drm_display_mode *mode,
11090 int x, int y, struct drm_framebuffer *fb,
11091 struct intel_crtc_config *pipe_config,
11092 unsigned modeset_pipes,
11093 unsigned prepare_pipes,
11094 unsigned disable_pipes)
11095 {
11096 struct drm_device *dev = crtc->dev;
11097 struct drm_i915_private *dev_priv = dev->dev_private;
11098 struct drm_display_mode *saved_mode;
11099 struct intel_crtc *intel_crtc;
11100 int ret = 0;
11101
11102 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11103 if (!saved_mode)
11104 return -ENOMEM;
11105
11106 *saved_mode = crtc->mode;
11107
11108 if (modeset_pipes)
11109 to_intel_crtc(crtc)->new_config = pipe_config;
11110
11111 /*
11112 * See if the config requires any additional preparation, e.g.
11113 * to adjust global state with pipes off. We need to do this
11114 * here so we can get the modeset_pipe updated config for the new
11115 * mode set on this crtc. For other crtcs we need to use the
11116 * adjusted_mode bits in the crtc directly.
11117 */
11118 if (IS_VALLEYVIEW(dev)) {
11119 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11120
11121 /* may have added more to prepare_pipes than we should */
11122 prepare_pipes &= ~disable_pipes;
11123 }
11124
11125 if (dev_priv->display.crtc_compute_clock) {
11126 unsigned clear_pipes = modeset_pipes | disable_pipes;
11127
11128 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11129 if (ret)
11130 goto done;
11131
11132 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11133 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
11134 if (ret) {
11135 intel_shared_dpll_abort_config(dev_priv);
11136 goto done;
11137 }
11138 }
11139 }
11140
11141 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11142 intel_crtc_disable(&intel_crtc->base);
11143
11144 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11145 if (intel_crtc->base.enabled)
11146 dev_priv->display.crtc_disable(&intel_crtc->base);
11147 }
11148
11149 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11150 * to set it here already despite that we pass it down the callchain.
11151 *
11152 * Note we'll need to fix this up when we start tracking multiple
11153 * pipes; here we assume a single modeset_pipe and only track the
11154 * single crtc and mode.
11155 */
11156 if (modeset_pipes) {
11157 crtc->mode = *mode;
11158 /* mode_set/enable/disable functions rely on a correct pipe
11159 * config. */
11160 to_intel_crtc(crtc)->config = *pipe_config;
11161 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11162
11163 /*
11164 * Calculate and store various constants which
11165 * are later needed by vblank and swap-completion
11166 * timestamping. They are derived from true hwmode.
11167 */
11168 drm_calc_timestamping_constants(crtc,
11169 &pipe_config->adjusted_mode);
11170 }
11171
11172 /* Only after disabling all output pipelines that will be changed can we
11173 * update the the output configuration. */
11174 intel_modeset_update_state(dev, prepare_pipes);
11175
11176 modeset_update_crtc_power_domains(dev);
11177
11178 /* Set up the DPLL and any encoders state that needs to adjust or depend
11179 * on the DPLL.
11180 */
11181 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11182 struct drm_framebuffer *old_fb = crtc->primary->fb;
11183 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11184 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11185
11186 mutex_lock(&dev->struct_mutex);
11187 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
11188 if (ret != 0) {
11189 DRM_ERROR("pin & fence failed\n");
11190 mutex_unlock(&dev->struct_mutex);
11191 goto done;
11192 }
11193 if (old_fb)
11194 intel_unpin_fb_obj(old_obj);
11195 i915_gem_track_fb(old_obj, obj,
11196 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11197 mutex_unlock(&dev->struct_mutex);
11198
11199 crtc->primary->fb = fb;
11200 crtc->x = x;
11201 crtc->y = y;
11202 }
11203
11204 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11205 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11206 update_scanline_offset(intel_crtc);
11207
11208 dev_priv->display.crtc_enable(&intel_crtc->base);
11209 }
11210
11211 /* FIXME: add subpixel order */
11212 done:
11213 if (ret && crtc->enabled)
11214 crtc->mode = *saved_mode;
11215
11216 kfree(pipe_config);
11217 kfree(saved_mode);
11218 return ret;
11219 }
11220
11221 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11222 struct drm_display_mode *mode,
11223 int x, int y, struct drm_framebuffer *fb,
11224 struct intel_crtc_config *pipe_config,
11225 unsigned modeset_pipes,
11226 unsigned prepare_pipes,
11227 unsigned disable_pipes)
11228 {
11229 int ret;
11230
11231 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11232 prepare_pipes, disable_pipes);
11233
11234 if (ret == 0)
11235 intel_modeset_check_state(crtc->dev);
11236
11237 return ret;
11238 }
11239
11240 static int intel_set_mode(struct drm_crtc *crtc,
11241 struct drm_display_mode *mode,
11242 int x, int y, struct drm_framebuffer *fb)
11243 {
11244 struct intel_crtc_config *pipe_config;
11245 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11246
11247 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11248 &modeset_pipes,
11249 &prepare_pipes,
11250 &disable_pipes);
11251
11252 if (IS_ERR(pipe_config))
11253 return PTR_ERR(pipe_config);
11254
11255 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11256 modeset_pipes, prepare_pipes,
11257 disable_pipes);
11258 }
11259
11260 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11261 {
11262 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11263 }
11264
11265 #undef for_each_intel_crtc_masked
11266
11267 static void intel_set_config_free(struct intel_set_config *config)
11268 {
11269 if (!config)
11270 return;
11271
11272 kfree(config->save_connector_encoders);
11273 kfree(config->save_encoder_crtcs);
11274 kfree(config->save_crtc_enabled);
11275 kfree(config);
11276 }
11277
11278 static int intel_set_config_save_state(struct drm_device *dev,
11279 struct intel_set_config *config)
11280 {
11281 struct drm_crtc *crtc;
11282 struct drm_encoder *encoder;
11283 struct drm_connector *connector;
11284 int count;
11285
11286 config->save_crtc_enabled =
11287 kcalloc(dev->mode_config.num_crtc,
11288 sizeof(bool), GFP_KERNEL);
11289 if (!config->save_crtc_enabled)
11290 return -ENOMEM;
11291
11292 config->save_encoder_crtcs =
11293 kcalloc(dev->mode_config.num_encoder,
11294 sizeof(struct drm_crtc *), GFP_KERNEL);
11295 if (!config->save_encoder_crtcs)
11296 return -ENOMEM;
11297
11298 config->save_connector_encoders =
11299 kcalloc(dev->mode_config.num_connector,
11300 sizeof(struct drm_encoder *), GFP_KERNEL);
11301 if (!config->save_connector_encoders)
11302 return -ENOMEM;
11303
11304 /* Copy data. Note that driver private data is not affected.
11305 * Should anything bad happen only the expected state is
11306 * restored, not the drivers personal bookkeeping.
11307 */
11308 count = 0;
11309 for_each_crtc(dev, crtc) {
11310 config->save_crtc_enabled[count++] = crtc->enabled;
11311 }
11312
11313 count = 0;
11314 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11315 config->save_encoder_crtcs[count++] = encoder->crtc;
11316 }
11317
11318 count = 0;
11319 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11320 config->save_connector_encoders[count++] = connector->encoder;
11321 }
11322
11323 return 0;
11324 }
11325
11326 static void intel_set_config_restore_state(struct drm_device *dev,
11327 struct intel_set_config *config)
11328 {
11329 struct intel_crtc *crtc;
11330 struct intel_encoder *encoder;
11331 struct intel_connector *connector;
11332 int count;
11333
11334 count = 0;
11335 for_each_intel_crtc(dev, crtc) {
11336 crtc->new_enabled = config->save_crtc_enabled[count++];
11337
11338 if (crtc->new_enabled)
11339 crtc->new_config = &crtc->config;
11340 else
11341 crtc->new_config = NULL;
11342 }
11343
11344 count = 0;
11345 for_each_intel_encoder(dev, encoder) {
11346 encoder->new_crtc =
11347 to_intel_crtc(config->save_encoder_crtcs[count++]);
11348 }
11349
11350 count = 0;
11351 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11352 connector->new_encoder =
11353 to_intel_encoder(config->save_connector_encoders[count++]);
11354 }
11355 }
11356
11357 static bool
11358 is_crtc_connector_off(struct drm_mode_set *set)
11359 {
11360 int i;
11361
11362 if (set->num_connectors == 0)
11363 return false;
11364
11365 if (WARN_ON(set->connectors == NULL))
11366 return false;
11367
11368 for (i = 0; i < set->num_connectors; i++)
11369 if (set->connectors[i]->encoder &&
11370 set->connectors[i]->encoder->crtc == set->crtc &&
11371 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11372 return true;
11373
11374 return false;
11375 }
11376
11377 static void
11378 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11379 struct intel_set_config *config)
11380 {
11381
11382 /* We should be able to check here if the fb has the same properties
11383 * and then just flip_or_move it */
11384 if (is_crtc_connector_off(set)) {
11385 config->mode_changed = true;
11386 } else if (set->crtc->primary->fb != set->fb) {
11387 /*
11388 * If we have no fb, we can only flip as long as the crtc is
11389 * active, otherwise we need a full mode set. The crtc may
11390 * be active if we've only disabled the primary plane, or
11391 * in fastboot situations.
11392 */
11393 if (set->crtc->primary->fb == NULL) {
11394 struct intel_crtc *intel_crtc =
11395 to_intel_crtc(set->crtc);
11396
11397 if (intel_crtc->active) {
11398 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11399 config->fb_changed = true;
11400 } else {
11401 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11402 config->mode_changed = true;
11403 }
11404 } else if (set->fb == NULL) {
11405 config->mode_changed = true;
11406 } else if (set->fb->pixel_format !=
11407 set->crtc->primary->fb->pixel_format) {
11408 config->mode_changed = true;
11409 } else {
11410 config->fb_changed = true;
11411 }
11412 }
11413
11414 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11415 config->fb_changed = true;
11416
11417 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11418 DRM_DEBUG_KMS("modes are different, full mode set\n");
11419 drm_mode_debug_printmodeline(&set->crtc->mode);
11420 drm_mode_debug_printmodeline(set->mode);
11421 config->mode_changed = true;
11422 }
11423
11424 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11425 set->crtc->base.id, config->mode_changed, config->fb_changed);
11426 }
11427
11428 static int
11429 intel_modeset_stage_output_state(struct drm_device *dev,
11430 struct drm_mode_set *set,
11431 struct intel_set_config *config)
11432 {
11433 struct intel_connector *connector;
11434 struct intel_encoder *encoder;
11435 struct intel_crtc *crtc;
11436 int ro;
11437
11438 /* The upper layers ensure that we either disable a crtc or have a list
11439 * of connectors. For paranoia, double-check this. */
11440 WARN_ON(!set->fb && (set->num_connectors != 0));
11441 WARN_ON(set->fb && (set->num_connectors == 0));
11442
11443 list_for_each_entry(connector, &dev->mode_config.connector_list,
11444 base.head) {
11445 /* Otherwise traverse passed in connector list and get encoders
11446 * for them. */
11447 for (ro = 0; ro < set->num_connectors; ro++) {
11448 if (set->connectors[ro] == &connector->base) {
11449 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11450 break;
11451 }
11452 }
11453
11454 /* If we disable the crtc, disable all its connectors. Also, if
11455 * the connector is on the changing crtc but not on the new
11456 * connector list, disable it. */
11457 if ((!set->fb || ro == set->num_connectors) &&
11458 connector->base.encoder &&
11459 connector->base.encoder->crtc == set->crtc) {
11460 connector->new_encoder = NULL;
11461
11462 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11463 connector->base.base.id,
11464 connector->base.name);
11465 }
11466
11467
11468 if (&connector->new_encoder->base != connector->base.encoder) {
11469 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11470 config->mode_changed = true;
11471 }
11472 }
11473 /* connector->new_encoder is now updated for all connectors. */
11474
11475 /* Update crtc of enabled connectors. */
11476 list_for_each_entry(connector, &dev->mode_config.connector_list,
11477 base.head) {
11478 struct drm_crtc *new_crtc;
11479
11480 if (!connector->new_encoder)
11481 continue;
11482
11483 new_crtc = connector->new_encoder->base.crtc;
11484
11485 for (ro = 0; ro < set->num_connectors; ro++) {
11486 if (set->connectors[ro] == &connector->base)
11487 new_crtc = set->crtc;
11488 }
11489
11490 /* Make sure the new CRTC will work with the encoder */
11491 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11492 new_crtc)) {
11493 return -EINVAL;
11494 }
11495 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11496
11497 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11498 connector->base.base.id,
11499 connector->base.name,
11500 new_crtc->base.id);
11501 }
11502
11503 /* Check for any encoders that needs to be disabled. */
11504 for_each_intel_encoder(dev, encoder) {
11505 int num_connectors = 0;
11506 list_for_each_entry(connector,
11507 &dev->mode_config.connector_list,
11508 base.head) {
11509 if (connector->new_encoder == encoder) {
11510 WARN_ON(!connector->new_encoder->new_crtc);
11511 num_connectors++;
11512 }
11513 }
11514
11515 if (num_connectors == 0)
11516 encoder->new_crtc = NULL;
11517 else if (num_connectors > 1)
11518 return -EINVAL;
11519
11520 /* Only now check for crtc changes so we don't miss encoders
11521 * that will be disabled. */
11522 if (&encoder->new_crtc->base != encoder->base.crtc) {
11523 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11524 config->mode_changed = true;
11525 }
11526 }
11527 /* Now we've also updated encoder->new_crtc for all encoders. */
11528 list_for_each_entry(connector, &dev->mode_config.connector_list,
11529 base.head) {
11530 if (connector->new_encoder)
11531 if (connector->new_encoder != connector->encoder)
11532 connector->encoder = connector->new_encoder;
11533 }
11534 for_each_intel_crtc(dev, crtc) {
11535 crtc->new_enabled = false;
11536
11537 for_each_intel_encoder(dev, encoder) {
11538 if (encoder->new_crtc == crtc) {
11539 crtc->new_enabled = true;
11540 break;
11541 }
11542 }
11543
11544 if (crtc->new_enabled != crtc->base.enabled) {
11545 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11546 crtc->new_enabled ? "en" : "dis");
11547 config->mode_changed = true;
11548 }
11549
11550 if (crtc->new_enabled)
11551 crtc->new_config = &crtc->config;
11552 else
11553 crtc->new_config = NULL;
11554 }
11555
11556 return 0;
11557 }
11558
11559 static void disable_crtc_nofb(struct intel_crtc *crtc)
11560 {
11561 struct drm_device *dev = crtc->base.dev;
11562 struct intel_encoder *encoder;
11563 struct intel_connector *connector;
11564
11565 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11566 pipe_name(crtc->pipe));
11567
11568 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11569 if (connector->new_encoder &&
11570 connector->new_encoder->new_crtc == crtc)
11571 connector->new_encoder = NULL;
11572 }
11573
11574 for_each_intel_encoder(dev, encoder) {
11575 if (encoder->new_crtc == crtc)
11576 encoder->new_crtc = NULL;
11577 }
11578
11579 crtc->new_enabled = false;
11580 crtc->new_config = NULL;
11581 }
11582
11583 static int intel_crtc_set_config(struct drm_mode_set *set)
11584 {
11585 struct drm_device *dev;
11586 struct drm_mode_set save_set;
11587 struct intel_set_config *config;
11588 struct intel_crtc_config *pipe_config;
11589 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11590 int ret;
11591
11592 BUG_ON(!set);
11593 BUG_ON(!set->crtc);
11594 BUG_ON(!set->crtc->helper_private);
11595
11596 /* Enforce sane interface api - has been abused by the fb helper. */
11597 BUG_ON(!set->mode && set->fb);
11598 BUG_ON(set->fb && set->num_connectors == 0);
11599
11600 if (set->fb) {
11601 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11602 set->crtc->base.id, set->fb->base.id,
11603 (int)set->num_connectors, set->x, set->y);
11604 } else {
11605 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11606 }
11607
11608 dev = set->crtc->dev;
11609
11610 ret = -ENOMEM;
11611 config = kzalloc(sizeof(*config), GFP_KERNEL);
11612 if (!config)
11613 goto out_config;
11614
11615 ret = intel_set_config_save_state(dev, config);
11616 if (ret)
11617 goto out_config;
11618
11619 save_set.crtc = set->crtc;
11620 save_set.mode = &set->crtc->mode;
11621 save_set.x = set->crtc->x;
11622 save_set.y = set->crtc->y;
11623 save_set.fb = set->crtc->primary->fb;
11624
11625 /* Compute whether we need a full modeset, only an fb base update or no
11626 * change at all. In the future we might also check whether only the
11627 * mode changed, e.g. for LVDS where we only change the panel fitter in
11628 * such cases. */
11629 intel_set_config_compute_mode_changes(set, config);
11630
11631 ret = intel_modeset_stage_output_state(dev, set, config);
11632 if (ret)
11633 goto fail;
11634
11635 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11636 set->fb,
11637 &modeset_pipes,
11638 &prepare_pipes,
11639 &disable_pipes);
11640 if (IS_ERR(pipe_config)) {
11641 ret = PTR_ERR(pipe_config);
11642 goto fail;
11643 } else if (pipe_config) {
11644 if (pipe_config->has_audio !=
11645 to_intel_crtc(set->crtc)->config.has_audio)
11646 config->mode_changed = true;
11647
11648 /* Force mode sets for any infoframe stuff */
11649 if (pipe_config->has_infoframe ||
11650 to_intel_crtc(set->crtc)->config.has_infoframe)
11651 config->mode_changed = true;
11652 }
11653
11654 /* set_mode will free it in the mode_changed case */
11655 if (!config->mode_changed)
11656 kfree(pipe_config);
11657
11658 intel_update_pipe_size(to_intel_crtc(set->crtc));
11659
11660 if (config->mode_changed) {
11661 ret = intel_set_mode_pipes(set->crtc, set->mode,
11662 set->x, set->y, set->fb, pipe_config,
11663 modeset_pipes, prepare_pipes,
11664 disable_pipes);
11665 } else if (config->fb_changed) {
11666 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11667
11668 intel_crtc_wait_for_pending_flips(set->crtc);
11669
11670 ret = intel_pipe_set_base(set->crtc,
11671 set->x, set->y, set->fb);
11672
11673 /*
11674 * We need to make sure the primary plane is re-enabled if it
11675 * has previously been turned off.
11676 */
11677 if (!intel_crtc->primary_enabled && ret == 0) {
11678 WARN_ON(!intel_crtc->active);
11679 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11680 }
11681
11682 /*
11683 * In the fastboot case this may be our only check of the
11684 * state after boot. It would be better to only do it on
11685 * the first update, but we don't have a nice way of doing that
11686 * (and really, set_config isn't used much for high freq page
11687 * flipping, so increasing its cost here shouldn't be a big
11688 * deal).
11689 */
11690 if (i915.fastboot && ret == 0)
11691 intel_modeset_check_state(set->crtc->dev);
11692 }
11693
11694 if (ret) {
11695 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11696 set->crtc->base.id, ret);
11697 fail:
11698 intel_set_config_restore_state(dev, config);
11699
11700 /*
11701 * HACK: if the pipe was on, but we didn't have a framebuffer,
11702 * force the pipe off to avoid oopsing in the modeset code
11703 * due to fb==NULL. This should only happen during boot since
11704 * we don't yet reconstruct the FB from the hardware state.
11705 */
11706 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11707 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11708
11709 /* Try to restore the config */
11710 if (config->mode_changed &&
11711 intel_set_mode(save_set.crtc, save_set.mode,
11712 save_set.x, save_set.y, save_set.fb))
11713 DRM_ERROR("failed to restore config after modeset failure\n");
11714 }
11715
11716 out_config:
11717 intel_set_config_free(config);
11718 return ret;
11719 }
11720
11721 static const struct drm_crtc_funcs intel_crtc_funcs = {
11722 .gamma_set = intel_crtc_gamma_set,
11723 .set_config = intel_crtc_set_config,
11724 .destroy = intel_crtc_destroy,
11725 .page_flip = intel_crtc_page_flip,
11726 };
11727
11728 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11729 struct intel_shared_dpll *pll,
11730 struct intel_dpll_hw_state *hw_state)
11731 {
11732 uint32_t val;
11733
11734 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11735 return false;
11736
11737 val = I915_READ(PCH_DPLL(pll->id));
11738 hw_state->dpll = val;
11739 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11740 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11741
11742 return val & DPLL_VCO_ENABLE;
11743 }
11744
11745 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11746 struct intel_shared_dpll *pll)
11747 {
11748 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11749 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11750 }
11751
11752 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11753 struct intel_shared_dpll *pll)
11754 {
11755 /* PCH refclock must be enabled first */
11756 ibx_assert_pch_refclk_enabled(dev_priv);
11757
11758 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11759
11760 /* Wait for the clocks to stabilize. */
11761 POSTING_READ(PCH_DPLL(pll->id));
11762 udelay(150);
11763
11764 /* The pixel multiplier can only be updated once the
11765 * DPLL is enabled and the clocks are stable.
11766 *
11767 * So write it again.
11768 */
11769 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11770 POSTING_READ(PCH_DPLL(pll->id));
11771 udelay(200);
11772 }
11773
11774 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11775 struct intel_shared_dpll *pll)
11776 {
11777 struct drm_device *dev = dev_priv->dev;
11778 struct intel_crtc *crtc;
11779
11780 /* Make sure no transcoder isn't still depending on us. */
11781 for_each_intel_crtc(dev, crtc) {
11782 if (intel_crtc_to_shared_dpll(crtc) == pll)
11783 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11784 }
11785
11786 I915_WRITE(PCH_DPLL(pll->id), 0);
11787 POSTING_READ(PCH_DPLL(pll->id));
11788 udelay(200);
11789 }
11790
11791 static char *ibx_pch_dpll_names[] = {
11792 "PCH DPLL A",
11793 "PCH DPLL B",
11794 };
11795
11796 static void ibx_pch_dpll_init(struct drm_device *dev)
11797 {
11798 struct drm_i915_private *dev_priv = dev->dev_private;
11799 int i;
11800
11801 dev_priv->num_shared_dpll = 2;
11802
11803 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11804 dev_priv->shared_dplls[i].id = i;
11805 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11806 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11807 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11808 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11809 dev_priv->shared_dplls[i].get_hw_state =
11810 ibx_pch_dpll_get_hw_state;
11811 }
11812 }
11813
11814 static void intel_shared_dpll_init(struct drm_device *dev)
11815 {
11816 struct drm_i915_private *dev_priv = dev->dev_private;
11817
11818 if (HAS_DDI(dev))
11819 intel_ddi_pll_init(dev);
11820 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11821 ibx_pch_dpll_init(dev);
11822 else
11823 dev_priv->num_shared_dpll = 0;
11824
11825 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11826 }
11827
11828 static int
11829 intel_primary_plane_disable(struct drm_plane *plane)
11830 {
11831 struct drm_device *dev = plane->dev;
11832 struct intel_crtc *intel_crtc;
11833
11834 if (!plane->fb)
11835 return 0;
11836
11837 BUG_ON(!plane->crtc);
11838
11839 intel_crtc = to_intel_crtc(plane->crtc);
11840
11841 /*
11842 * Even though we checked plane->fb above, it's still possible that
11843 * the primary plane has been implicitly disabled because the crtc
11844 * coordinates given weren't visible, or because we detected
11845 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11846 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11847 * In either case, we need to unpin the FB and let the fb pointer get
11848 * updated, but otherwise we don't need to touch the hardware.
11849 */
11850 if (!intel_crtc->primary_enabled)
11851 goto disable_unpin;
11852
11853 intel_crtc_wait_for_pending_flips(plane->crtc);
11854 intel_disable_primary_hw_plane(plane, plane->crtc);
11855
11856 disable_unpin:
11857 mutex_lock(&dev->struct_mutex);
11858 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11859 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11860 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11861 mutex_unlock(&dev->struct_mutex);
11862 plane->fb = NULL;
11863
11864 return 0;
11865 }
11866
11867 static int
11868 intel_check_primary_plane(struct drm_plane *plane,
11869 struct intel_plane_state *state)
11870 {
11871 struct drm_crtc *crtc = state->crtc;
11872 struct drm_framebuffer *fb = state->fb;
11873 struct drm_rect *dest = &state->dst;
11874 struct drm_rect *src = &state->src;
11875 const struct drm_rect *clip = &state->clip;
11876
11877 return drm_plane_helper_check_update(plane, crtc, fb,
11878 src, dest, clip,
11879 DRM_PLANE_HELPER_NO_SCALING,
11880 DRM_PLANE_HELPER_NO_SCALING,
11881 false, true, &state->visible);
11882 }
11883
11884 static int
11885 intel_prepare_primary_plane(struct drm_plane *plane,
11886 struct intel_plane_state *state)
11887 {
11888 struct drm_crtc *crtc = state->crtc;
11889 struct drm_framebuffer *fb = state->fb;
11890 struct drm_device *dev = crtc->dev;
11891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11892 enum pipe pipe = intel_crtc->pipe;
11893 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11894 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11895 int ret;
11896
11897 intel_crtc_wait_for_pending_flips(crtc);
11898
11899 if (intel_crtc_has_pending_flip(crtc)) {
11900 DRM_ERROR("pipe is still busy with an old pageflip\n");
11901 return -EBUSY;
11902 }
11903
11904 if (old_obj != obj) {
11905 mutex_lock(&dev->struct_mutex);
11906 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11907 if (ret == 0)
11908 i915_gem_track_fb(old_obj, obj,
11909 INTEL_FRONTBUFFER_PRIMARY(pipe));
11910 mutex_unlock(&dev->struct_mutex);
11911 if (ret != 0) {
11912 DRM_DEBUG_KMS("pin & fence failed\n");
11913 return ret;
11914 }
11915 }
11916
11917 return 0;
11918 }
11919
11920 static void
11921 intel_commit_primary_plane(struct drm_plane *plane,
11922 struct intel_plane_state *state)
11923 {
11924 struct drm_crtc *crtc = state->crtc;
11925 struct drm_framebuffer *fb = state->fb;
11926 struct drm_device *dev = crtc->dev;
11927 struct drm_i915_private *dev_priv = dev->dev_private;
11928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11929 enum pipe pipe = intel_crtc->pipe;
11930 struct drm_framebuffer *old_fb = plane->fb;
11931 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11932 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11933 struct intel_plane *intel_plane = to_intel_plane(plane);
11934 struct drm_rect *src = &state->src;
11935
11936 crtc->primary->fb = fb;
11937 crtc->x = src->x1 >> 16;
11938 crtc->y = src->y1 >> 16;
11939
11940 intel_plane->crtc_x = state->orig_dst.x1;
11941 intel_plane->crtc_y = state->orig_dst.y1;
11942 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11943 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11944 intel_plane->src_x = state->orig_src.x1;
11945 intel_plane->src_y = state->orig_src.y1;
11946 intel_plane->src_w = drm_rect_width(&state->orig_src);
11947 intel_plane->src_h = drm_rect_height(&state->orig_src);
11948 intel_plane->obj = obj;
11949
11950 if (intel_crtc->active) {
11951 /*
11952 * FBC does not work on some platforms for rotated
11953 * planes, so disable it when rotation is not 0 and
11954 * update it when rotation is set back to 0.
11955 *
11956 * FIXME: This is redundant with the fbc update done in
11957 * the primary plane enable function except that that
11958 * one is done too late. We eventually need to unify
11959 * this.
11960 */
11961 if (intel_crtc->primary_enabled &&
11962 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11963 dev_priv->fbc.plane == intel_crtc->plane &&
11964 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11965 intel_disable_fbc(dev);
11966 }
11967
11968 if (state->visible) {
11969 bool was_enabled = intel_crtc->primary_enabled;
11970
11971 /* FIXME: kill this fastboot hack */
11972 intel_update_pipe_size(intel_crtc);
11973
11974 intel_crtc->primary_enabled = true;
11975
11976 dev_priv->display.update_primary_plane(crtc, plane->fb,
11977 crtc->x, crtc->y);
11978
11979 /*
11980 * BDW signals flip done immediately if the plane
11981 * is disabled, even if the plane enable is already
11982 * armed to occur at the next vblank :(
11983 */
11984 if (IS_BROADWELL(dev) && !was_enabled)
11985 intel_wait_for_vblank(dev, intel_crtc->pipe);
11986 } else {
11987 /*
11988 * If clipping results in a non-visible primary plane,
11989 * we'll disable the primary plane. Note that this is
11990 * a bit different than what happens if userspace
11991 * explicitly disables the plane by passing fb=0
11992 * because plane->fb still gets set and pinned.
11993 */
11994 intel_disable_primary_hw_plane(plane, crtc);
11995 }
11996
11997 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11998
11999 mutex_lock(&dev->struct_mutex);
12000 intel_update_fbc(dev);
12001 mutex_unlock(&dev->struct_mutex);
12002 }
12003
12004 if (old_fb && old_fb != fb) {
12005 if (intel_crtc->active)
12006 intel_wait_for_vblank(dev, intel_crtc->pipe);
12007
12008 mutex_lock(&dev->struct_mutex);
12009 intel_unpin_fb_obj(old_obj);
12010 mutex_unlock(&dev->struct_mutex);
12011 }
12012 }
12013
12014 static int
12015 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
12016 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12017 unsigned int crtc_w, unsigned int crtc_h,
12018 uint32_t src_x, uint32_t src_y,
12019 uint32_t src_w, uint32_t src_h)
12020 {
12021 struct intel_plane_state state;
12022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12023 int ret;
12024
12025 state.crtc = crtc;
12026 state.fb = fb;
12027
12028 /* sample coordinates in 16.16 fixed point */
12029 state.src.x1 = src_x;
12030 state.src.x2 = src_x + src_w;
12031 state.src.y1 = src_y;
12032 state.src.y2 = src_y + src_h;
12033
12034 /* integer pixels */
12035 state.dst.x1 = crtc_x;
12036 state.dst.x2 = crtc_x + crtc_w;
12037 state.dst.y1 = crtc_y;
12038 state.dst.y2 = crtc_y + crtc_h;
12039
12040 state.clip.x1 = 0;
12041 state.clip.y1 = 0;
12042 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12043 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12044
12045 state.orig_src = state.src;
12046 state.orig_dst = state.dst;
12047
12048 ret = intel_check_primary_plane(plane, &state);
12049 if (ret)
12050 return ret;
12051
12052 ret = intel_prepare_primary_plane(plane, &state);
12053 if (ret)
12054 return ret;
12055
12056 intel_commit_primary_plane(plane, &state);
12057
12058 return 0;
12059 }
12060
12061 /* Common destruction function for both primary and cursor planes */
12062 static void intel_plane_destroy(struct drm_plane *plane)
12063 {
12064 struct intel_plane *intel_plane = to_intel_plane(plane);
12065 drm_plane_cleanup(plane);
12066 kfree(intel_plane);
12067 }
12068
12069 static const struct drm_plane_funcs intel_primary_plane_funcs = {
12070 .update_plane = intel_primary_plane_setplane,
12071 .disable_plane = intel_primary_plane_disable,
12072 .destroy = intel_plane_destroy,
12073 .set_property = intel_plane_set_property
12074 };
12075
12076 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12077 int pipe)
12078 {
12079 struct intel_plane *primary;
12080 const uint32_t *intel_primary_formats;
12081 int num_formats;
12082
12083 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12084 if (primary == NULL)
12085 return NULL;
12086
12087 primary->can_scale = false;
12088 primary->max_downscale = 1;
12089 primary->pipe = pipe;
12090 primary->plane = pipe;
12091 primary->rotation = BIT(DRM_ROTATE_0);
12092 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12093 primary->plane = !pipe;
12094
12095 if (INTEL_INFO(dev)->gen <= 3) {
12096 intel_primary_formats = intel_primary_formats_gen2;
12097 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12098 } else {
12099 intel_primary_formats = intel_primary_formats_gen4;
12100 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12101 }
12102
12103 drm_universal_plane_init(dev, &primary->base, 0,
12104 &intel_primary_plane_funcs,
12105 intel_primary_formats, num_formats,
12106 DRM_PLANE_TYPE_PRIMARY);
12107
12108 if (INTEL_INFO(dev)->gen >= 4) {
12109 if (!dev->mode_config.rotation_property)
12110 dev->mode_config.rotation_property =
12111 drm_mode_create_rotation_property(dev,
12112 BIT(DRM_ROTATE_0) |
12113 BIT(DRM_ROTATE_180));
12114 if (dev->mode_config.rotation_property)
12115 drm_object_attach_property(&primary->base.base,
12116 dev->mode_config.rotation_property,
12117 primary->rotation);
12118 }
12119
12120 return &primary->base;
12121 }
12122
12123 static int
12124 intel_cursor_plane_disable(struct drm_plane *plane)
12125 {
12126 if (!plane->fb)
12127 return 0;
12128
12129 BUG_ON(!plane->crtc);
12130
12131 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12132 }
12133
12134 static int
12135 intel_check_cursor_plane(struct drm_plane *plane,
12136 struct intel_plane_state *state)
12137 {
12138 struct drm_crtc *crtc = state->crtc;
12139 struct drm_device *dev = crtc->dev;
12140 struct drm_framebuffer *fb = state->fb;
12141 struct drm_rect *dest = &state->dst;
12142 struct drm_rect *src = &state->src;
12143 const struct drm_rect *clip = &state->clip;
12144 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12145 int crtc_w, crtc_h;
12146 unsigned stride;
12147 int ret;
12148
12149 ret = drm_plane_helper_check_update(plane, crtc, fb,
12150 src, dest, clip,
12151 DRM_PLANE_HELPER_NO_SCALING,
12152 DRM_PLANE_HELPER_NO_SCALING,
12153 true, true, &state->visible);
12154 if (ret)
12155 return ret;
12156
12157
12158 /* if we want to turn off the cursor ignore width and height */
12159 if (!obj)
12160 return 0;
12161
12162 /* Check for which cursor types we support */
12163 crtc_w = drm_rect_width(&state->orig_dst);
12164 crtc_h = drm_rect_height(&state->orig_dst);
12165 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
12166 DRM_DEBUG("Cursor dimension not supported\n");
12167 return -EINVAL;
12168 }
12169
12170 stride = roundup_pow_of_two(crtc_w) * 4;
12171 if (obj->base.size < stride * crtc_h) {
12172 DRM_DEBUG_KMS("buffer is too small\n");
12173 return -ENOMEM;
12174 }
12175
12176 if (fb == crtc->cursor->fb)
12177 return 0;
12178
12179 /* we only need to pin inside GTT if cursor is non-phy */
12180 mutex_lock(&dev->struct_mutex);
12181 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12182 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12183 ret = -EINVAL;
12184 }
12185 mutex_unlock(&dev->struct_mutex);
12186
12187 return ret;
12188 }
12189
12190 static int
12191 intel_commit_cursor_plane(struct drm_plane *plane,
12192 struct intel_plane_state *state)
12193 {
12194 struct drm_crtc *crtc = state->crtc;
12195 struct drm_framebuffer *fb = state->fb;
12196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12197 struct intel_plane *intel_plane = to_intel_plane(plane);
12198 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12199 struct drm_i915_gem_object *obj = intel_fb->obj;
12200 int crtc_w, crtc_h;
12201
12202 crtc->cursor_x = state->orig_dst.x1;
12203 crtc->cursor_y = state->orig_dst.y1;
12204
12205 intel_plane->crtc_x = state->orig_dst.x1;
12206 intel_plane->crtc_y = state->orig_dst.y1;
12207 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
12208 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
12209 intel_plane->src_x = state->orig_src.x1;
12210 intel_plane->src_y = state->orig_src.y1;
12211 intel_plane->src_w = drm_rect_width(&state->orig_src);
12212 intel_plane->src_h = drm_rect_height(&state->orig_src);
12213 intel_plane->obj = obj;
12214
12215 if (fb != crtc->cursor->fb) {
12216 crtc_w = drm_rect_width(&state->orig_dst);
12217 crtc_h = drm_rect_height(&state->orig_dst);
12218 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12219 } else {
12220 intel_crtc_update_cursor(crtc, state->visible);
12221
12222 intel_frontbuffer_flip(crtc->dev,
12223 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12224
12225 return 0;
12226 }
12227 }
12228
12229 static int
12230 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12231 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12232 unsigned int crtc_w, unsigned int crtc_h,
12233 uint32_t src_x, uint32_t src_y,
12234 uint32_t src_w, uint32_t src_h)
12235 {
12236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12237 struct intel_plane_state state;
12238 int ret;
12239
12240 state.crtc = crtc;
12241 state.fb = fb;
12242
12243 /* sample coordinates in 16.16 fixed point */
12244 state.src.x1 = src_x;
12245 state.src.x2 = src_x + src_w;
12246 state.src.y1 = src_y;
12247 state.src.y2 = src_y + src_h;
12248
12249 /* integer pixels */
12250 state.dst.x1 = crtc_x;
12251 state.dst.x2 = crtc_x + crtc_w;
12252 state.dst.y1 = crtc_y;
12253 state.dst.y2 = crtc_y + crtc_h;
12254
12255 state.clip.x1 = 0;
12256 state.clip.y1 = 0;
12257 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12258 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12259
12260 state.orig_src = state.src;
12261 state.orig_dst = state.dst;
12262
12263 ret = intel_check_cursor_plane(plane, &state);
12264 if (ret)
12265 return ret;
12266
12267 return intel_commit_cursor_plane(plane, &state);
12268 }
12269
12270 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12271 .update_plane = intel_cursor_plane_update,
12272 .disable_plane = intel_cursor_plane_disable,
12273 .destroy = intel_plane_destroy,
12274 .set_property = intel_plane_set_property,
12275 };
12276
12277 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12278 int pipe)
12279 {
12280 struct intel_plane *cursor;
12281
12282 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12283 if (cursor == NULL)
12284 return NULL;
12285
12286 cursor->can_scale = false;
12287 cursor->max_downscale = 1;
12288 cursor->pipe = pipe;
12289 cursor->plane = pipe;
12290 cursor->rotation = BIT(DRM_ROTATE_0);
12291
12292 drm_universal_plane_init(dev, &cursor->base, 0,
12293 &intel_cursor_plane_funcs,
12294 intel_cursor_formats,
12295 ARRAY_SIZE(intel_cursor_formats),
12296 DRM_PLANE_TYPE_CURSOR);
12297
12298 if (INTEL_INFO(dev)->gen >= 4) {
12299 if (!dev->mode_config.rotation_property)
12300 dev->mode_config.rotation_property =
12301 drm_mode_create_rotation_property(dev,
12302 BIT(DRM_ROTATE_0) |
12303 BIT(DRM_ROTATE_180));
12304 if (dev->mode_config.rotation_property)
12305 drm_object_attach_property(&cursor->base.base,
12306 dev->mode_config.rotation_property,
12307 cursor->rotation);
12308 }
12309
12310 return &cursor->base;
12311 }
12312
12313 static void intel_crtc_init(struct drm_device *dev, int pipe)
12314 {
12315 struct drm_i915_private *dev_priv = dev->dev_private;
12316 struct intel_crtc *intel_crtc;
12317 struct drm_plane *primary = NULL;
12318 struct drm_plane *cursor = NULL;
12319 int i, ret;
12320
12321 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12322 if (intel_crtc == NULL)
12323 return;
12324
12325 primary = intel_primary_plane_create(dev, pipe);
12326 if (!primary)
12327 goto fail;
12328
12329 cursor = intel_cursor_plane_create(dev, pipe);
12330 if (!cursor)
12331 goto fail;
12332
12333 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12334 cursor, &intel_crtc_funcs);
12335 if (ret)
12336 goto fail;
12337
12338 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12339 for (i = 0; i < 256; i++) {
12340 intel_crtc->lut_r[i] = i;
12341 intel_crtc->lut_g[i] = i;
12342 intel_crtc->lut_b[i] = i;
12343 }
12344
12345 /*
12346 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12347 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12348 */
12349 intel_crtc->pipe = pipe;
12350 intel_crtc->plane = pipe;
12351 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12352 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12353 intel_crtc->plane = !pipe;
12354 }
12355
12356 intel_crtc->cursor_base = ~0;
12357 intel_crtc->cursor_cntl = ~0;
12358 intel_crtc->cursor_size = ~0;
12359
12360 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12361 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12362 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12363 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12364
12365 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12366
12367 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12368
12369 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12370 return;
12371
12372 fail:
12373 if (primary)
12374 drm_plane_cleanup(primary);
12375 if (cursor)
12376 drm_plane_cleanup(cursor);
12377 kfree(intel_crtc);
12378 }
12379
12380 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12381 {
12382 struct drm_encoder *encoder = connector->base.encoder;
12383 struct drm_device *dev = connector->base.dev;
12384
12385 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12386
12387 if (!encoder || WARN_ON(!encoder->crtc))
12388 return INVALID_PIPE;
12389
12390 return to_intel_crtc(encoder->crtc)->pipe;
12391 }
12392
12393 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12394 struct drm_file *file)
12395 {
12396 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12397 struct drm_crtc *drmmode_crtc;
12398 struct intel_crtc *crtc;
12399
12400 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12401 return -ENODEV;
12402
12403 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12404
12405 if (!drmmode_crtc) {
12406 DRM_ERROR("no such CRTC id\n");
12407 return -ENOENT;
12408 }
12409
12410 crtc = to_intel_crtc(drmmode_crtc);
12411 pipe_from_crtc_id->pipe = crtc->pipe;
12412
12413 return 0;
12414 }
12415
12416 static int intel_encoder_clones(struct intel_encoder *encoder)
12417 {
12418 struct drm_device *dev = encoder->base.dev;
12419 struct intel_encoder *source_encoder;
12420 int index_mask = 0;
12421 int entry = 0;
12422
12423 for_each_intel_encoder(dev, source_encoder) {
12424 if (encoders_cloneable(encoder, source_encoder))
12425 index_mask |= (1 << entry);
12426
12427 entry++;
12428 }
12429
12430 return index_mask;
12431 }
12432
12433 static bool has_edp_a(struct drm_device *dev)
12434 {
12435 struct drm_i915_private *dev_priv = dev->dev_private;
12436
12437 if (!IS_MOBILE(dev))
12438 return false;
12439
12440 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12441 return false;
12442
12443 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12444 return false;
12445
12446 return true;
12447 }
12448
12449 const char *intel_output_name(int output)
12450 {
12451 static const char *names[] = {
12452 [INTEL_OUTPUT_UNUSED] = "Unused",
12453 [INTEL_OUTPUT_ANALOG] = "Analog",
12454 [INTEL_OUTPUT_DVO] = "DVO",
12455 [INTEL_OUTPUT_SDVO] = "SDVO",
12456 [INTEL_OUTPUT_LVDS] = "LVDS",
12457 [INTEL_OUTPUT_TVOUT] = "TV",
12458 [INTEL_OUTPUT_HDMI] = "HDMI",
12459 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12460 [INTEL_OUTPUT_EDP] = "eDP",
12461 [INTEL_OUTPUT_DSI] = "DSI",
12462 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12463 };
12464
12465 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12466 return "Invalid";
12467
12468 return names[output];
12469 }
12470
12471 static bool intel_crt_present(struct drm_device *dev)
12472 {
12473 struct drm_i915_private *dev_priv = dev->dev_private;
12474
12475 if (INTEL_INFO(dev)->gen >= 9)
12476 return false;
12477
12478 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12479 return false;
12480
12481 if (IS_CHERRYVIEW(dev))
12482 return false;
12483
12484 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12485 return false;
12486
12487 return true;
12488 }
12489
12490 static void intel_setup_outputs(struct drm_device *dev)
12491 {
12492 struct drm_i915_private *dev_priv = dev->dev_private;
12493 struct intel_encoder *encoder;
12494 bool dpd_is_edp = false;
12495
12496 intel_lvds_init(dev);
12497
12498 if (intel_crt_present(dev))
12499 intel_crt_init(dev);
12500
12501 if (HAS_DDI(dev)) {
12502 int found;
12503
12504 /* Haswell uses DDI functions to detect digital outputs */
12505 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12506 /* DDI A only supports eDP */
12507 if (found)
12508 intel_ddi_init(dev, PORT_A);
12509
12510 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12511 * register */
12512 found = I915_READ(SFUSE_STRAP);
12513
12514 if (found & SFUSE_STRAP_DDIB_DETECTED)
12515 intel_ddi_init(dev, PORT_B);
12516 if (found & SFUSE_STRAP_DDIC_DETECTED)
12517 intel_ddi_init(dev, PORT_C);
12518 if (found & SFUSE_STRAP_DDID_DETECTED)
12519 intel_ddi_init(dev, PORT_D);
12520 } else if (HAS_PCH_SPLIT(dev)) {
12521 int found;
12522 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12523
12524 if (has_edp_a(dev))
12525 intel_dp_init(dev, DP_A, PORT_A);
12526
12527 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12528 /* PCH SDVOB multiplex with HDMIB */
12529 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12530 if (!found)
12531 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12532 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12533 intel_dp_init(dev, PCH_DP_B, PORT_B);
12534 }
12535
12536 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12537 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12538
12539 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12540 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12541
12542 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12543 intel_dp_init(dev, PCH_DP_C, PORT_C);
12544
12545 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12546 intel_dp_init(dev, PCH_DP_D, PORT_D);
12547 } else if (IS_VALLEYVIEW(dev)) {
12548 /*
12549 * The DP_DETECTED bit is the latched state of the DDC
12550 * SDA pin at boot. However since eDP doesn't require DDC
12551 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12552 * eDP ports may have been muxed to an alternate function.
12553 * Thus we can't rely on the DP_DETECTED bit alone to detect
12554 * eDP ports. Consult the VBT as well as DP_DETECTED to
12555 * detect eDP ports.
12556 */
12557 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12558 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12559 PORT_B);
12560 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12561 intel_dp_is_edp(dev, PORT_B))
12562 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12563
12564 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12565 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12566 PORT_C);
12567 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12568 intel_dp_is_edp(dev, PORT_C))
12569 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12570
12571 if (IS_CHERRYVIEW(dev)) {
12572 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12573 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12574 PORT_D);
12575 /* eDP not supported on port D, so don't check VBT */
12576 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12577 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12578 }
12579
12580 intel_dsi_init(dev);
12581 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12582 bool found = false;
12583
12584 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12585 DRM_DEBUG_KMS("probing SDVOB\n");
12586 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12587 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12588 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12589 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12590 }
12591
12592 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12593 intel_dp_init(dev, DP_B, PORT_B);
12594 }
12595
12596 /* Before G4X SDVOC doesn't have its own detect register */
12597
12598 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12599 DRM_DEBUG_KMS("probing SDVOC\n");
12600 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12601 }
12602
12603 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12604
12605 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12606 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12607 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12608 }
12609 if (SUPPORTS_INTEGRATED_DP(dev))
12610 intel_dp_init(dev, DP_C, PORT_C);
12611 }
12612
12613 if (SUPPORTS_INTEGRATED_DP(dev) &&
12614 (I915_READ(DP_D) & DP_DETECTED))
12615 intel_dp_init(dev, DP_D, PORT_D);
12616 } else if (IS_GEN2(dev))
12617 intel_dvo_init(dev);
12618
12619 if (SUPPORTS_TV(dev))
12620 intel_tv_init(dev);
12621
12622 intel_psr_init(dev);
12623
12624 for_each_intel_encoder(dev, encoder) {
12625 encoder->base.possible_crtcs = encoder->crtc_mask;
12626 encoder->base.possible_clones =
12627 intel_encoder_clones(encoder);
12628 }
12629
12630 intel_init_pch_refclk(dev);
12631
12632 drm_helper_move_panel_connectors_to_head(dev);
12633 }
12634
12635 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12636 {
12637 struct drm_device *dev = fb->dev;
12638 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12639
12640 drm_framebuffer_cleanup(fb);
12641 mutex_lock(&dev->struct_mutex);
12642 WARN_ON(!intel_fb->obj->framebuffer_references--);
12643 drm_gem_object_unreference(&intel_fb->obj->base);
12644 mutex_unlock(&dev->struct_mutex);
12645 kfree(intel_fb);
12646 }
12647
12648 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12649 struct drm_file *file,
12650 unsigned int *handle)
12651 {
12652 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12653 struct drm_i915_gem_object *obj = intel_fb->obj;
12654
12655 return drm_gem_handle_create(file, &obj->base, handle);
12656 }
12657
12658 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12659 .destroy = intel_user_framebuffer_destroy,
12660 .create_handle = intel_user_framebuffer_create_handle,
12661 };
12662
12663 static int intel_framebuffer_init(struct drm_device *dev,
12664 struct intel_framebuffer *intel_fb,
12665 struct drm_mode_fb_cmd2 *mode_cmd,
12666 struct drm_i915_gem_object *obj)
12667 {
12668 int aligned_height;
12669 int pitch_limit;
12670 int ret;
12671
12672 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12673
12674 if (obj->tiling_mode == I915_TILING_Y) {
12675 DRM_DEBUG("hardware does not support tiling Y\n");
12676 return -EINVAL;
12677 }
12678
12679 if (mode_cmd->pitches[0] & 63) {
12680 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12681 mode_cmd->pitches[0]);
12682 return -EINVAL;
12683 }
12684
12685 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12686 pitch_limit = 32*1024;
12687 } else if (INTEL_INFO(dev)->gen >= 4) {
12688 if (obj->tiling_mode)
12689 pitch_limit = 16*1024;
12690 else
12691 pitch_limit = 32*1024;
12692 } else if (INTEL_INFO(dev)->gen >= 3) {
12693 if (obj->tiling_mode)
12694 pitch_limit = 8*1024;
12695 else
12696 pitch_limit = 16*1024;
12697 } else
12698 /* XXX DSPC is limited to 4k tiled */
12699 pitch_limit = 8*1024;
12700
12701 if (mode_cmd->pitches[0] > pitch_limit) {
12702 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12703 obj->tiling_mode ? "tiled" : "linear",
12704 mode_cmd->pitches[0], pitch_limit);
12705 return -EINVAL;
12706 }
12707
12708 if (obj->tiling_mode != I915_TILING_NONE &&
12709 mode_cmd->pitches[0] != obj->stride) {
12710 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12711 mode_cmd->pitches[0], obj->stride);
12712 return -EINVAL;
12713 }
12714
12715 /* Reject formats not supported by any plane early. */
12716 switch (mode_cmd->pixel_format) {
12717 case DRM_FORMAT_C8:
12718 case DRM_FORMAT_RGB565:
12719 case DRM_FORMAT_XRGB8888:
12720 case DRM_FORMAT_ARGB8888:
12721 break;
12722 case DRM_FORMAT_XRGB1555:
12723 case DRM_FORMAT_ARGB1555:
12724 if (INTEL_INFO(dev)->gen > 3) {
12725 DRM_DEBUG("unsupported pixel format: %s\n",
12726 drm_get_format_name(mode_cmd->pixel_format));
12727 return -EINVAL;
12728 }
12729 break;
12730 case DRM_FORMAT_XBGR8888:
12731 case DRM_FORMAT_ABGR8888:
12732 case DRM_FORMAT_XRGB2101010:
12733 case DRM_FORMAT_ARGB2101010:
12734 case DRM_FORMAT_XBGR2101010:
12735 case DRM_FORMAT_ABGR2101010:
12736 if (INTEL_INFO(dev)->gen < 4) {
12737 DRM_DEBUG("unsupported pixel format: %s\n",
12738 drm_get_format_name(mode_cmd->pixel_format));
12739 return -EINVAL;
12740 }
12741 break;
12742 case DRM_FORMAT_YUYV:
12743 case DRM_FORMAT_UYVY:
12744 case DRM_FORMAT_YVYU:
12745 case DRM_FORMAT_VYUY:
12746 if (INTEL_INFO(dev)->gen < 5) {
12747 DRM_DEBUG("unsupported pixel format: %s\n",
12748 drm_get_format_name(mode_cmd->pixel_format));
12749 return -EINVAL;
12750 }
12751 break;
12752 default:
12753 DRM_DEBUG("unsupported pixel format: %s\n",
12754 drm_get_format_name(mode_cmd->pixel_format));
12755 return -EINVAL;
12756 }
12757
12758 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12759 if (mode_cmd->offsets[0] != 0)
12760 return -EINVAL;
12761
12762 aligned_height = intel_align_height(dev, mode_cmd->height,
12763 obj->tiling_mode);
12764 /* FIXME drm helper for size checks (especially planar formats)? */
12765 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12766 return -EINVAL;
12767
12768 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12769 intel_fb->obj = obj;
12770 intel_fb->obj->framebuffer_references++;
12771
12772 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12773 if (ret) {
12774 DRM_ERROR("framebuffer init failed %d\n", ret);
12775 return ret;
12776 }
12777
12778 return 0;
12779 }
12780
12781 static struct drm_framebuffer *
12782 intel_user_framebuffer_create(struct drm_device *dev,
12783 struct drm_file *filp,
12784 struct drm_mode_fb_cmd2 *mode_cmd)
12785 {
12786 struct drm_i915_gem_object *obj;
12787
12788 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12789 mode_cmd->handles[0]));
12790 if (&obj->base == NULL)
12791 return ERR_PTR(-ENOENT);
12792
12793 return intel_framebuffer_create(dev, mode_cmd, obj);
12794 }
12795
12796 #ifndef CONFIG_DRM_I915_FBDEV
12797 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12798 {
12799 }
12800 #endif
12801
12802 static const struct drm_mode_config_funcs intel_mode_funcs = {
12803 .fb_create = intel_user_framebuffer_create,
12804 .output_poll_changed = intel_fbdev_output_poll_changed,
12805 };
12806
12807 /* Set up chip specific display functions */
12808 static void intel_init_display(struct drm_device *dev)
12809 {
12810 struct drm_i915_private *dev_priv = dev->dev_private;
12811
12812 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12813 dev_priv->display.find_dpll = g4x_find_best_dpll;
12814 else if (IS_CHERRYVIEW(dev))
12815 dev_priv->display.find_dpll = chv_find_best_dpll;
12816 else if (IS_VALLEYVIEW(dev))
12817 dev_priv->display.find_dpll = vlv_find_best_dpll;
12818 else if (IS_PINEVIEW(dev))
12819 dev_priv->display.find_dpll = pnv_find_best_dpll;
12820 else
12821 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12822
12823 if (HAS_DDI(dev)) {
12824 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12825 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12826 dev_priv->display.crtc_compute_clock =
12827 haswell_crtc_compute_clock;
12828 dev_priv->display.crtc_enable = haswell_crtc_enable;
12829 dev_priv->display.crtc_disable = haswell_crtc_disable;
12830 dev_priv->display.off = ironlake_crtc_off;
12831 if (INTEL_INFO(dev)->gen >= 9)
12832 dev_priv->display.update_primary_plane =
12833 skylake_update_primary_plane;
12834 else
12835 dev_priv->display.update_primary_plane =
12836 ironlake_update_primary_plane;
12837 } else if (HAS_PCH_SPLIT(dev)) {
12838 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12839 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12840 dev_priv->display.crtc_compute_clock =
12841 ironlake_crtc_compute_clock;
12842 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12843 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12844 dev_priv->display.off = ironlake_crtc_off;
12845 dev_priv->display.update_primary_plane =
12846 ironlake_update_primary_plane;
12847 } else if (IS_VALLEYVIEW(dev)) {
12848 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12849 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12850 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12851 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12852 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12853 dev_priv->display.off = i9xx_crtc_off;
12854 dev_priv->display.update_primary_plane =
12855 i9xx_update_primary_plane;
12856 } else {
12857 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12858 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12859 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12860 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12861 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12862 dev_priv->display.off = i9xx_crtc_off;
12863 dev_priv->display.update_primary_plane =
12864 i9xx_update_primary_plane;
12865 }
12866
12867 /* Returns the core display clock speed */
12868 if (IS_VALLEYVIEW(dev))
12869 dev_priv->display.get_display_clock_speed =
12870 valleyview_get_display_clock_speed;
12871 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12872 dev_priv->display.get_display_clock_speed =
12873 i945_get_display_clock_speed;
12874 else if (IS_I915G(dev))
12875 dev_priv->display.get_display_clock_speed =
12876 i915_get_display_clock_speed;
12877 else if (IS_I945GM(dev) || IS_845G(dev))
12878 dev_priv->display.get_display_clock_speed =
12879 i9xx_misc_get_display_clock_speed;
12880 else if (IS_PINEVIEW(dev))
12881 dev_priv->display.get_display_clock_speed =
12882 pnv_get_display_clock_speed;
12883 else if (IS_I915GM(dev))
12884 dev_priv->display.get_display_clock_speed =
12885 i915gm_get_display_clock_speed;
12886 else if (IS_I865G(dev))
12887 dev_priv->display.get_display_clock_speed =
12888 i865_get_display_clock_speed;
12889 else if (IS_I85X(dev))
12890 dev_priv->display.get_display_clock_speed =
12891 i855_get_display_clock_speed;
12892 else /* 852, 830 */
12893 dev_priv->display.get_display_clock_speed =
12894 i830_get_display_clock_speed;
12895
12896 if (IS_GEN5(dev)) {
12897 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12898 } else if (IS_GEN6(dev)) {
12899 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12900 } else if (IS_IVYBRIDGE(dev)) {
12901 /* FIXME: detect B0+ stepping and use auto training */
12902 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12903 dev_priv->display.modeset_global_resources =
12904 ivb_modeset_global_resources;
12905 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12906 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12907 } else if (IS_VALLEYVIEW(dev)) {
12908 dev_priv->display.modeset_global_resources =
12909 valleyview_modeset_global_resources;
12910 }
12911
12912 /* Default just returns -ENODEV to indicate unsupported */
12913 dev_priv->display.queue_flip = intel_default_queue_flip;
12914
12915 switch (INTEL_INFO(dev)->gen) {
12916 case 2:
12917 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12918 break;
12919
12920 case 3:
12921 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12922 break;
12923
12924 case 4:
12925 case 5:
12926 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12927 break;
12928
12929 case 6:
12930 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12931 break;
12932 case 7:
12933 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12934 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12935 break;
12936 case 9:
12937 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12938 break;
12939 }
12940
12941 intel_panel_init_backlight_funcs(dev);
12942
12943 mutex_init(&dev_priv->pps_mutex);
12944 }
12945
12946 /*
12947 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12948 * resume, or other times. This quirk makes sure that's the case for
12949 * affected systems.
12950 */
12951 static void quirk_pipea_force(struct drm_device *dev)
12952 {
12953 struct drm_i915_private *dev_priv = dev->dev_private;
12954
12955 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12956 DRM_INFO("applying pipe a force quirk\n");
12957 }
12958
12959 static void quirk_pipeb_force(struct drm_device *dev)
12960 {
12961 struct drm_i915_private *dev_priv = dev->dev_private;
12962
12963 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12964 DRM_INFO("applying pipe b force quirk\n");
12965 }
12966
12967 /*
12968 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12969 */
12970 static void quirk_ssc_force_disable(struct drm_device *dev)
12971 {
12972 struct drm_i915_private *dev_priv = dev->dev_private;
12973 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12974 DRM_INFO("applying lvds SSC disable quirk\n");
12975 }
12976
12977 /*
12978 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12979 * brightness value
12980 */
12981 static void quirk_invert_brightness(struct drm_device *dev)
12982 {
12983 struct drm_i915_private *dev_priv = dev->dev_private;
12984 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12985 DRM_INFO("applying inverted panel brightness quirk\n");
12986 }
12987
12988 /* Some VBT's incorrectly indicate no backlight is present */
12989 static void quirk_backlight_present(struct drm_device *dev)
12990 {
12991 struct drm_i915_private *dev_priv = dev->dev_private;
12992 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12993 DRM_INFO("applying backlight present quirk\n");
12994 }
12995
12996 struct intel_quirk {
12997 int device;
12998 int subsystem_vendor;
12999 int subsystem_device;
13000 void (*hook)(struct drm_device *dev);
13001 };
13002
13003 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13004 struct intel_dmi_quirk {
13005 void (*hook)(struct drm_device *dev);
13006 const struct dmi_system_id (*dmi_id_list)[];
13007 };
13008
13009 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13010 {
13011 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13012 return 1;
13013 }
13014
13015 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13016 {
13017 .dmi_id_list = &(const struct dmi_system_id[]) {
13018 {
13019 .callback = intel_dmi_reverse_brightness,
13020 .ident = "NCR Corporation",
13021 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13022 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13023 },
13024 },
13025 { } /* terminating entry */
13026 },
13027 .hook = quirk_invert_brightness,
13028 },
13029 };
13030
13031 static struct intel_quirk intel_quirks[] = {
13032 /* HP Mini needs pipe A force quirk (LP: #322104) */
13033 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13034
13035 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13036 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13037
13038 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13039 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13040
13041 /* 830 needs to leave pipe A & dpll A up */
13042 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13043
13044 /* 830 needs to leave pipe B & dpll B up */
13045 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13046
13047 /* Lenovo U160 cannot use SSC on LVDS */
13048 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13049
13050 /* Sony Vaio Y cannot use SSC on LVDS */
13051 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13052
13053 /* Acer Aspire 5734Z must invert backlight brightness */
13054 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13055
13056 /* Acer/eMachines G725 */
13057 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13058
13059 /* Acer/eMachines e725 */
13060 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13061
13062 /* Acer/Packard Bell NCL20 */
13063 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13064
13065 /* Acer Aspire 4736Z */
13066 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13067
13068 /* Acer Aspire 5336 */
13069 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13070
13071 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13072 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13073
13074 /* Acer C720 Chromebook (Core i3 4005U) */
13075 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13076
13077 /* Apple Macbook 2,1 (Core 2 T7400) */
13078 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13079
13080 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13081 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13082
13083 /* HP Chromebook 14 (Celeron 2955U) */
13084 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13085 };
13086
13087 static void intel_init_quirks(struct drm_device *dev)
13088 {
13089 struct pci_dev *d = dev->pdev;
13090 int i;
13091
13092 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13093 struct intel_quirk *q = &intel_quirks[i];
13094
13095 if (d->device == q->device &&
13096 (d->subsystem_vendor == q->subsystem_vendor ||
13097 q->subsystem_vendor == PCI_ANY_ID) &&
13098 (d->subsystem_device == q->subsystem_device ||
13099 q->subsystem_device == PCI_ANY_ID))
13100 q->hook(dev);
13101 }
13102 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13103 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13104 intel_dmi_quirks[i].hook(dev);
13105 }
13106 }
13107
13108 /* Disable the VGA plane that we never use */
13109 static void i915_disable_vga(struct drm_device *dev)
13110 {
13111 struct drm_i915_private *dev_priv = dev->dev_private;
13112 u8 sr1;
13113 u32 vga_reg = i915_vgacntrl_reg(dev);
13114
13115 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13116 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13117 outb(SR01, VGA_SR_INDEX);
13118 sr1 = inb(VGA_SR_DATA);
13119 outb(sr1 | 1<<5, VGA_SR_DATA);
13120 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13121 udelay(300);
13122
13123 /*
13124 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
13125 * from S3 without preserving (some of?) the other bits.
13126 */
13127 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
13128 POSTING_READ(vga_reg);
13129 }
13130
13131 void intel_modeset_init_hw(struct drm_device *dev)
13132 {
13133 intel_prepare_ddi(dev);
13134
13135 if (IS_VALLEYVIEW(dev))
13136 vlv_update_cdclk(dev);
13137
13138 intel_init_clock_gating(dev);
13139
13140 intel_enable_gt_powersave(dev);
13141 }
13142
13143 void intel_modeset_init(struct drm_device *dev)
13144 {
13145 struct drm_i915_private *dev_priv = dev->dev_private;
13146 int sprite, ret;
13147 enum pipe pipe;
13148 struct intel_crtc *crtc;
13149
13150 drm_mode_config_init(dev);
13151
13152 dev->mode_config.min_width = 0;
13153 dev->mode_config.min_height = 0;
13154
13155 dev->mode_config.preferred_depth = 24;
13156 dev->mode_config.prefer_shadow = 1;
13157
13158 dev->mode_config.funcs = &intel_mode_funcs;
13159
13160 intel_init_quirks(dev);
13161
13162 intel_init_pm(dev);
13163
13164 if (INTEL_INFO(dev)->num_pipes == 0)
13165 return;
13166
13167 intel_init_display(dev);
13168 intel_init_audio(dev);
13169
13170 if (IS_GEN2(dev)) {
13171 dev->mode_config.max_width = 2048;
13172 dev->mode_config.max_height = 2048;
13173 } else if (IS_GEN3(dev)) {
13174 dev->mode_config.max_width = 4096;
13175 dev->mode_config.max_height = 4096;
13176 } else {
13177 dev->mode_config.max_width = 8192;
13178 dev->mode_config.max_height = 8192;
13179 }
13180
13181 if (IS_845G(dev) || IS_I865G(dev)) {
13182 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13183 dev->mode_config.cursor_height = 1023;
13184 } else if (IS_GEN2(dev)) {
13185 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13186 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13187 } else {
13188 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13189 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13190 }
13191
13192 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13193
13194 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13195 INTEL_INFO(dev)->num_pipes,
13196 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13197
13198 for_each_pipe(dev_priv, pipe) {
13199 intel_crtc_init(dev, pipe);
13200 for_each_sprite(pipe, sprite) {
13201 ret = intel_plane_init(dev, pipe, sprite);
13202 if (ret)
13203 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13204 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13205 }
13206 }
13207
13208 intel_init_dpio(dev);
13209
13210 intel_shared_dpll_init(dev);
13211
13212 /* save the BIOS value before clobbering it */
13213 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13214 /* Just disable it once at startup */
13215 i915_disable_vga(dev);
13216 intel_setup_outputs(dev);
13217
13218 /* Just in case the BIOS is doing something questionable. */
13219 intel_disable_fbc(dev);
13220
13221 drm_modeset_lock_all(dev);
13222 intel_modeset_setup_hw_state(dev, false);
13223 drm_modeset_unlock_all(dev);
13224
13225 for_each_intel_crtc(dev, crtc) {
13226 if (!crtc->active)
13227 continue;
13228
13229 /*
13230 * Note that reserving the BIOS fb up front prevents us
13231 * from stuffing other stolen allocations like the ring
13232 * on top. This prevents some ugliness at boot time, and
13233 * can even allow for smooth boot transitions if the BIOS
13234 * fb is large enough for the active pipe configuration.
13235 */
13236 if (dev_priv->display.get_plane_config) {
13237 dev_priv->display.get_plane_config(crtc,
13238 &crtc->plane_config);
13239 /*
13240 * If the fb is shared between multiple heads, we'll
13241 * just get the first one.
13242 */
13243 intel_find_plane_obj(crtc, &crtc->plane_config);
13244 }
13245 }
13246 }
13247
13248 static void intel_enable_pipe_a(struct drm_device *dev)
13249 {
13250 struct intel_connector *connector;
13251 struct drm_connector *crt = NULL;
13252 struct intel_load_detect_pipe load_detect_temp;
13253 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13254
13255 /* We can't just switch on the pipe A, we need to set things up with a
13256 * proper mode and output configuration. As a gross hack, enable pipe A
13257 * by enabling the load detect pipe once. */
13258 list_for_each_entry(connector,
13259 &dev->mode_config.connector_list,
13260 base.head) {
13261 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13262 crt = &connector->base;
13263 break;
13264 }
13265 }
13266
13267 if (!crt)
13268 return;
13269
13270 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13271 intel_release_load_detect_pipe(crt, &load_detect_temp);
13272 }
13273
13274 static bool
13275 intel_check_plane_mapping(struct intel_crtc *crtc)
13276 {
13277 struct drm_device *dev = crtc->base.dev;
13278 struct drm_i915_private *dev_priv = dev->dev_private;
13279 u32 reg, val;
13280
13281 if (INTEL_INFO(dev)->num_pipes == 1)
13282 return true;
13283
13284 reg = DSPCNTR(!crtc->plane);
13285 val = I915_READ(reg);
13286
13287 if ((val & DISPLAY_PLANE_ENABLE) &&
13288 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13289 return false;
13290
13291 return true;
13292 }
13293
13294 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13295 {
13296 struct drm_device *dev = crtc->base.dev;
13297 struct drm_i915_private *dev_priv = dev->dev_private;
13298 u32 reg;
13299
13300 /* Clear any frame start delays used for debugging left by the BIOS */
13301 reg = PIPECONF(crtc->config.cpu_transcoder);
13302 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13303
13304 /* restore vblank interrupts to correct state */
13305 if (crtc->active) {
13306 update_scanline_offset(crtc);
13307 drm_vblank_on(dev, crtc->pipe);
13308 } else
13309 drm_vblank_off(dev, crtc->pipe);
13310
13311 /* We need to sanitize the plane -> pipe mapping first because this will
13312 * disable the crtc (and hence change the state) if it is wrong. Note
13313 * that gen4+ has a fixed plane -> pipe mapping. */
13314 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13315 struct intel_connector *connector;
13316 bool plane;
13317
13318 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13319 crtc->base.base.id);
13320
13321 /* Pipe has the wrong plane attached and the plane is active.
13322 * Temporarily change the plane mapping and disable everything
13323 * ... */
13324 plane = crtc->plane;
13325 crtc->plane = !plane;
13326 crtc->primary_enabled = true;
13327 dev_priv->display.crtc_disable(&crtc->base);
13328 crtc->plane = plane;
13329
13330 /* ... and break all links. */
13331 list_for_each_entry(connector, &dev->mode_config.connector_list,
13332 base.head) {
13333 if (connector->encoder->base.crtc != &crtc->base)
13334 continue;
13335
13336 connector->base.dpms = DRM_MODE_DPMS_OFF;
13337 connector->base.encoder = NULL;
13338 }
13339 /* multiple connectors may have the same encoder:
13340 * handle them and break crtc link separately */
13341 list_for_each_entry(connector, &dev->mode_config.connector_list,
13342 base.head)
13343 if (connector->encoder->base.crtc == &crtc->base) {
13344 connector->encoder->base.crtc = NULL;
13345 connector->encoder->connectors_active = false;
13346 }
13347
13348 WARN_ON(crtc->active);
13349 crtc->base.enabled = false;
13350 }
13351
13352 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13353 crtc->pipe == PIPE_A && !crtc->active) {
13354 /* BIOS forgot to enable pipe A, this mostly happens after
13355 * resume. Force-enable the pipe to fix this, the update_dpms
13356 * call below we restore the pipe to the right state, but leave
13357 * the required bits on. */
13358 intel_enable_pipe_a(dev);
13359 }
13360
13361 /* Adjust the state of the output pipe according to whether we
13362 * have active connectors/encoders. */
13363 intel_crtc_update_dpms(&crtc->base);
13364
13365 if (crtc->active != crtc->base.enabled) {
13366 struct intel_encoder *encoder;
13367
13368 /* This can happen either due to bugs in the get_hw_state
13369 * functions or because the pipe is force-enabled due to the
13370 * pipe A quirk. */
13371 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13372 crtc->base.base.id,
13373 crtc->base.enabled ? "enabled" : "disabled",
13374 crtc->active ? "enabled" : "disabled");
13375
13376 crtc->base.enabled = crtc->active;
13377
13378 /* Because we only establish the connector -> encoder ->
13379 * crtc links if something is active, this means the
13380 * crtc is now deactivated. Break the links. connector
13381 * -> encoder links are only establish when things are
13382 * actually up, hence no need to break them. */
13383 WARN_ON(crtc->active);
13384
13385 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13386 WARN_ON(encoder->connectors_active);
13387 encoder->base.crtc = NULL;
13388 }
13389 }
13390
13391 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13392 /*
13393 * We start out with underrun reporting disabled to avoid races.
13394 * For correct bookkeeping mark this on active crtcs.
13395 *
13396 * Also on gmch platforms we dont have any hardware bits to
13397 * disable the underrun reporting. Which means we need to start
13398 * out with underrun reporting disabled also on inactive pipes,
13399 * since otherwise we'll complain about the garbage we read when
13400 * e.g. coming up after runtime pm.
13401 *
13402 * No protection against concurrent access is required - at
13403 * worst a fifo underrun happens which also sets this to false.
13404 */
13405 crtc->cpu_fifo_underrun_disabled = true;
13406 crtc->pch_fifo_underrun_disabled = true;
13407 }
13408 }
13409
13410 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13411 {
13412 struct intel_connector *connector;
13413 struct drm_device *dev = encoder->base.dev;
13414
13415 /* We need to check both for a crtc link (meaning that the
13416 * encoder is active and trying to read from a pipe) and the
13417 * pipe itself being active. */
13418 bool has_active_crtc = encoder->base.crtc &&
13419 to_intel_crtc(encoder->base.crtc)->active;
13420
13421 if (encoder->connectors_active && !has_active_crtc) {
13422 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13423 encoder->base.base.id,
13424 encoder->base.name);
13425
13426 /* Connector is active, but has no active pipe. This is
13427 * fallout from our resume register restoring. Disable
13428 * the encoder manually again. */
13429 if (encoder->base.crtc) {
13430 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13431 encoder->base.base.id,
13432 encoder->base.name);
13433 encoder->disable(encoder);
13434 if (encoder->post_disable)
13435 encoder->post_disable(encoder);
13436 }
13437 encoder->base.crtc = NULL;
13438 encoder->connectors_active = false;
13439
13440 /* Inconsistent output/port/pipe state happens presumably due to
13441 * a bug in one of the get_hw_state functions. Or someplace else
13442 * in our code, like the register restore mess on resume. Clamp
13443 * things to off as a safer default. */
13444 list_for_each_entry(connector,
13445 &dev->mode_config.connector_list,
13446 base.head) {
13447 if (connector->encoder != encoder)
13448 continue;
13449 connector->base.dpms = DRM_MODE_DPMS_OFF;
13450 connector->base.encoder = NULL;
13451 }
13452 }
13453 /* Enabled encoders without active connectors will be fixed in
13454 * the crtc fixup. */
13455 }
13456
13457 void i915_redisable_vga_power_on(struct drm_device *dev)
13458 {
13459 struct drm_i915_private *dev_priv = dev->dev_private;
13460 u32 vga_reg = i915_vgacntrl_reg(dev);
13461
13462 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13463 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13464 i915_disable_vga(dev);
13465 }
13466 }
13467
13468 void i915_redisable_vga(struct drm_device *dev)
13469 {
13470 struct drm_i915_private *dev_priv = dev->dev_private;
13471
13472 /* This function can be called both from intel_modeset_setup_hw_state or
13473 * at a very early point in our resume sequence, where the power well
13474 * structures are not yet restored. Since this function is at a very
13475 * paranoid "someone might have enabled VGA while we were not looking"
13476 * level, just check if the power well is enabled instead of trying to
13477 * follow the "don't touch the power well if we don't need it" policy
13478 * the rest of the driver uses. */
13479 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13480 return;
13481
13482 i915_redisable_vga_power_on(dev);
13483 }
13484
13485 static bool primary_get_hw_state(struct intel_crtc *crtc)
13486 {
13487 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13488
13489 if (!crtc->active)
13490 return false;
13491
13492 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13493 }
13494
13495 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13496 {
13497 struct drm_i915_private *dev_priv = dev->dev_private;
13498 enum pipe pipe;
13499 struct intel_crtc *crtc;
13500 struct intel_encoder *encoder;
13501 struct intel_connector *connector;
13502 int i;
13503
13504 for_each_intel_crtc(dev, crtc) {
13505 memset(&crtc->config, 0, sizeof(crtc->config));
13506
13507 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13508
13509 crtc->active = dev_priv->display.get_pipe_config(crtc,
13510 &crtc->config);
13511
13512 crtc->base.enabled = crtc->active;
13513 crtc->primary_enabled = primary_get_hw_state(crtc);
13514
13515 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13516 crtc->base.base.id,
13517 crtc->active ? "enabled" : "disabled");
13518 }
13519
13520 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13521 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13522
13523 pll->on = pll->get_hw_state(dev_priv, pll,
13524 &pll->config.hw_state);
13525 pll->active = 0;
13526 pll->config.crtc_mask = 0;
13527 for_each_intel_crtc(dev, crtc) {
13528 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13529 pll->active++;
13530 pll->config.crtc_mask |= 1 << crtc->pipe;
13531 }
13532 }
13533
13534 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13535 pll->name, pll->config.crtc_mask, pll->on);
13536
13537 if (pll->config.crtc_mask)
13538 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13539 }
13540
13541 for_each_intel_encoder(dev, encoder) {
13542 pipe = 0;
13543
13544 if (encoder->get_hw_state(encoder, &pipe)) {
13545 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13546 encoder->base.crtc = &crtc->base;
13547 encoder->get_config(encoder, &crtc->config);
13548 } else {
13549 encoder->base.crtc = NULL;
13550 }
13551
13552 encoder->connectors_active = false;
13553 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13554 encoder->base.base.id,
13555 encoder->base.name,
13556 encoder->base.crtc ? "enabled" : "disabled",
13557 pipe_name(pipe));
13558 }
13559
13560 list_for_each_entry(connector, &dev->mode_config.connector_list,
13561 base.head) {
13562 if (connector->get_hw_state(connector)) {
13563 connector->base.dpms = DRM_MODE_DPMS_ON;
13564 connector->encoder->connectors_active = true;
13565 connector->base.encoder = &connector->encoder->base;
13566 } else {
13567 connector->base.dpms = DRM_MODE_DPMS_OFF;
13568 connector->base.encoder = NULL;
13569 }
13570 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13571 connector->base.base.id,
13572 connector->base.name,
13573 connector->base.encoder ? "enabled" : "disabled");
13574 }
13575 }
13576
13577 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13578 * and i915 state tracking structures. */
13579 void intel_modeset_setup_hw_state(struct drm_device *dev,
13580 bool force_restore)
13581 {
13582 struct drm_i915_private *dev_priv = dev->dev_private;
13583 enum pipe pipe;
13584 struct intel_crtc *crtc;
13585 struct intel_encoder *encoder;
13586 int i;
13587
13588 intel_modeset_readout_hw_state(dev);
13589
13590 /*
13591 * Now that we have the config, copy it to each CRTC struct
13592 * Note that this could go away if we move to using crtc_config
13593 * checking everywhere.
13594 */
13595 for_each_intel_crtc(dev, crtc) {
13596 if (crtc->active && i915.fastboot) {
13597 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13598 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13599 crtc->base.base.id);
13600 drm_mode_debug_printmodeline(&crtc->base.mode);
13601 }
13602 }
13603
13604 /* HW state is read out, now we need to sanitize this mess. */
13605 for_each_intel_encoder(dev, encoder) {
13606 intel_sanitize_encoder(encoder);
13607 }
13608
13609 for_each_pipe(dev_priv, pipe) {
13610 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13611 intel_sanitize_crtc(crtc);
13612 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13613 }
13614
13615 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13616 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13617
13618 if (!pll->on || pll->active)
13619 continue;
13620
13621 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13622
13623 pll->disable(dev_priv, pll);
13624 pll->on = false;
13625 }
13626
13627 if (IS_GEN9(dev))
13628 skl_wm_get_hw_state(dev);
13629 else if (HAS_PCH_SPLIT(dev))
13630 ilk_wm_get_hw_state(dev);
13631
13632 if (force_restore) {
13633 i915_redisable_vga(dev);
13634
13635 /*
13636 * We need to use raw interfaces for restoring state to avoid
13637 * checking (bogus) intermediate states.
13638 */
13639 for_each_pipe(dev_priv, pipe) {
13640 struct drm_crtc *crtc =
13641 dev_priv->pipe_to_crtc_mapping[pipe];
13642
13643 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13644 crtc->primary->fb);
13645 }
13646 } else {
13647 intel_modeset_update_staged_output_state(dev);
13648 }
13649
13650 intel_modeset_check_state(dev);
13651 }
13652
13653 void intel_modeset_gem_init(struct drm_device *dev)
13654 {
13655 struct drm_i915_private *dev_priv = dev->dev_private;
13656 struct drm_crtc *c;
13657 struct drm_i915_gem_object *obj;
13658
13659 mutex_lock(&dev->struct_mutex);
13660 intel_init_gt_powersave(dev);
13661 mutex_unlock(&dev->struct_mutex);
13662
13663 /*
13664 * There may be no VBT; and if the BIOS enabled SSC we can
13665 * just keep using it to avoid unnecessary flicker. Whereas if the
13666 * BIOS isn't using it, don't assume it will work even if the VBT
13667 * indicates as much.
13668 */
13669 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13670 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13671 DREF_SSC1_ENABLE);
13672
13673 intel_modeset_init_hw(dev);
13674
13675 intel_setup_overlay(dev);
13676
13677 /*
13678 * Make sure any fbs we allocated at startup are properly
13679 * pinned & fenced. When we do the allocation it's too early
13680 * for this.
13681 */
13682 mutex_lock(&dev->struct_mutex);
13683 for_each_crtc(dev, c) {
13684 obj = intel_fb_obj(c->primary->fb);
13685 if (obj == NULL)
13686 continue;
13687
13688 if (intel_pin_and_fence_fb_obj(c->primary,
13689 c->primary->fb,
13690 NULL)) {
13691 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13692 to_intel_crtc(c)->pipe);
13693 drm_framebuffer_unreference(c->primary->fb);
13694 c->primary->fb = NULL;
13695 }
13696 }
13697 mutex_unlock(&dev->struct_mutex);
13698
13699 intel_backlight_register(dev);
13700 }
13701
13702 void intel_connector_unregister(struct intel_connector *intel_connector)
13703 {
13704 struct drm_connector *connector = &intel_connector->base;
13705
13706 intel_panel_destroy_backlight(connector);
13707 drm_connector_unregister(connector);
13708 }
13709
13710 void intel_modeset_cleanup(struct drm_device *dev)
13711 {
13712 struct drm_i915_private *dev_priv = dev->dev_private;
13713 struct drm_connector *connector;
13714
13715 intel_disable_gt_powersave(dev);
13716
13717 intel_backlight_unregister(dev);
13718
13719 /*
13720 * Interrupts and polling as the first thing to avoid creating havoc.
13721 * Too much stuff here (turning of connectors, ...) would
13722 * experience fancy races otherwise.
13723 */
13724 intel_irq_uninstall(dev_priv);
13725
13726 /*
13727 * Due to the hpd irq storm handling the hotplug work can re-arm the
13728 * poll handlers. Hence disable polling after hpd handling is shut down.
13729 */
13730 drm_kms_helper_poll_fini(dev);
13731
13732 mutex_lock(&dev->struct_mutex);
13733
13734 intel_unregister_dsm_handler();
13735
13736 intel_disable_fbc(dev);
13737
13738 ironlake_teardown_rc6(dev);
13739
13740 mutex_unlock(&dev->struct_mutex);
13741
13742 /* flush any delayed tasks or pending work */
13743 flush_scheduled_work();
13744
13745 /* destroy the backlight and sysfs files before encoders/connectors */
13746 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13747 struct intel_connector *intel_connector;
13748
13749 intel_connector = to_intel_connector(connector);
13750 intel_connector->unregister(intel_connector);
13751 }
13752
13753 drm_mode_config_cleanup(dev);
13754
13755 intel_cleanup_overlay(dev);
13756
13757 mutex_lock(&dev->struct_mutex);
13758 intel_cleanup_gt_powersave(dev);
13759 mutex_unlock(&dev->struct_mutex);
13760 }
13761
13762 /*
13763 * Return which encoder is currently attached for connector.
13764 */
13765 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13766 {
13767 return &intel_attached_encoder(connector)->base;
13768 }
13769
13770 void intel_connector_attach_encoder(struct intel_connector *connector,
13771 struct intel_encoder *encoder)
13772 {
13773 connector->encoder = encoder;
13774 drm_mode_connector_attach_encoder(&connector->base,
13775 &encoder->base);
13776 }
13777
13778 /*
13779 * set vga decode state - true == enable VGA decode
13780 */
13781 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13782 {
13783 struct drm_i915_private *dev_priv = dev->dev_private;
13784 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13785 u16 gmch_ctrl;
13786
13787 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13788 DRM_ERROR("failed to read control word\n");
13789 return -EIO;
13790 }
13791
13792 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13793 return 0;
13794
13795 if (state)
13796 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13797 else
13798 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13799
13800 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13801 DRM_ERROR("failed to write control word\n");
13802 return -EIO;
13803 }
13804
13805 return 0;
13806 }
13807
13808 struct intel_display_error_state {
13809
13810 u32 power_well_driver;
13811
13812 int num_transcoders;
13813
13814 struct intel_cursor_error_state {
13815 u32 control;
13816 u32 position;
13817 u32 base;
13818 u32 size;
13819 } cursor[I915_MAX_PIPES];
13820
13821 struct intel_pipe_error_state {
13822 bool power_domain_on;
13823 u32 source;
13824 u32 stat;
13825 } pipe[I915_MAX_PIPES];
13826
13827 struct intel_plane_error_state {
13828 u32 control;
13829 u32 stride;
13830 u32 size;
13831 u32 pos;
13832 u32 addr;
13833 u32 surface;
13834 u32 tile_offset;
13835 } plane[I915_MAX_PIPES];
13836
13837 struct intel_transcoder_error_state {
13838 bool power_domain_on;
13839 enum transcoder cpu_transcoder;
13840
13841 u32 conf;
13842
13843 u32 htotal;
13844 u32 hblank;
13845 u32 hsync;
13846 u32 vtotal;
13847 u32 vblank;
13848 u32 vsync;
13849 } transcoder[4];
13850 };
13851
13852 struct intel_display_error_state *
13853 intel_display_capture_error_state(struct drm_device *dev)
13854 {
13855 struct drm_i915_private *dev_priv = dev->dev_private;
13856 struct intel_display_error_state *error;
13857 int transcoders[] = {
13858 TRANSCODER_A,
13859 TRANSCODER_B,
13860 TRANSCODER_C,
13861 TRANSCODER_EDP,
13862 };
13863 int i;
13864
13865 if (INTEL_INFO(dev)->num_pipes == 0)
13866 return NULL;
13867
13868 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13869 if (error == NULL)
13870 return NULL;
13871
13872 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13873 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13874
13875 for_each_pipe(dev_priv, i) {
13876 error->pipe[i].power_domain_on =
13877 __intel_display_power_is_enabled(dev_priv,
13878 POWER_DOMAIN_PIPE(i));
13879 if (!error->pipe[i].power_domain_on)
13880 continue;
13881
13882 error->cursor[i].control = I915_READ(CURCNTR(i));
13883 error->cursor[i].position = I915_READ(CURPOS(i));
13884 error->cursor[i].base = I915_READ(CURBASE(i));
13885
13886 error->plane[i].control = I915_READ(DSPCNTR(i));
13887 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13888 if (INTEL_INFO(dev)->gen <= 3) {
13889 error->plane[i].size = I915_READ(DSPSIZE(i));
13890 error->plane[i].pos = I915_READ(DSPPOS(i));
13891 }
13892 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13893 error->plane[i].addr = I915_READ(DSPADDR(i));
13894 if (INTEL_INFO(dev)->gen >= 4) {
13895 error->plane[i].surface = I915_READ(DSPSURF(i));
13896 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13897 }
13898
13899 error->pipe[i].source = I915_READ(PIPESRC(i));
13900
13901 if (HAS_GMCH_DISPLAY(dev))
13902 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13903 }
13904
13905 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13906 if (HAS_DDI(dev_priv->dev))
13907 error->num_transcoders++; /* Account for eDP. */
13908
13909 for (i = 0; i < error->num_transcoders; i++) {
13910 enum transcoder cpu_transcoder = transcoders[i];
13911
13912 error->transcoder[i].power_domain_on =
13913 __intel_display_power_is_enabled(dev_priv,
13914 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13915 if (!error->transcoder[i].power_domain_on)
13916 continue;
13917
13918 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13919
13920 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13921 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13922 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13923 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13924 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13925 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13926 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13927 }
13928
13929 return error;
13930 }
13931
13932 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13933
13934 void
13935 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13936 struct drm_device *dev,
13937 struct intel_display_error_state *error)
13938 {
13939 struct drm_i915_private *dev_priv = dev->dev_private;
13940 int i;
13941
13942 if (!error)
13943 return;
13944
13945 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13946 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13947 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13948 error->power_well_driver);
13949 for_each_pipe(dev_priv, i) {
13950 err_printf(m, "Pipe [%d]:\n", i);
13951 err_printf(m, " Power: %s\n",
13952 error->pipe[i].power_domain_on ? "on" : "off");
13953 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13954 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13955
13956 err_printf(m, "Plane [%d]:\n", i);
13957 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13958 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13959 if (INTEL_INFO(dev)->gen <= 3) {
13960 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13961 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13962 }
13963 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13964 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13965 if (INTEL_INFO(dev)->gen >= 4) {
13966 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13967 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13968 }
13969
13970 err_printf(m, "Cursor [%d]:\n", i);
13971 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13972 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13973 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13974 }
13975
13976 for (i = 0; i < error->num_transcoders; i++) {
13977 err_printf(m, "CPU transcoder: %c\n",
13978 transcoder_name(error->transcoder[i].cpu_transcoder));
13979 err_printf(m, " Power: %s\n",
13980 error->transcoder[i].power_domain_on ? "on" : "off");
13981 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13982 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13983 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13984 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13985 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13986 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13987 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13988 }
13989 }
13990
13991 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13992 {
13993 struct intel_crtc *crtc;
13994
13995 for_each_intel_crtc(dev, crtc) {
13996 struct intel_unpin_work *work;
13997
13998 spin_lock_irq(&dev->event_lock);
13999
14000 work = crtc->unpin_work;
14001
14002 if (work && work->event &&
14003 work->event->base.file_priv == file) {
14004 kfree(work->event);
14005 work->event = NULL;
14006 }
14007
14008 spin_unlock_irq(&dev->event_lock);
14009 }
14010 }
Linux kernel - Deliverables
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