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drm/i915: Fix VLV DP RBR/HDMI/DAC PLL LPF coefficients
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
56 {
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
60 }
61
62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63 {
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
65 }
66
67 static void intel_dp_link_down(struct intel_dp *intel_dp);
68
69 static int
70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
71 {
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 default:
79 max_link_bw = DP_LINK_BW_1_62;
80 break;
81 }
82 return max_link_bw;
83 }
84
85 /*
86 * The units on the numbers in the next two are... bizarre. Examples will
87 * make it clearer; this one parallels an example in the eDP spec.
88 *
89 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
90 *
91 * 270000 * 1 * 8 / 10 == 216000
92 *
93 * The actual data capacity of that configuration is 2.16Gbit/s, so the
94 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
95 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
96 * 119000. At 18bpp that's 2142000 kilobits per second.
97 *
98 * Thus the strange-looking division by 10 in intel_dp_link_required, to
99 * get the result in decakilobits instead of kilobits.
100 */
101
102 static int
103 intel_dp_link_required(int pixel_clock, int bpp)
104 {
105 return (pixel_clock * bpp + 9) / 10;
106 }
107
108 static int
109 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
110 {
111 return (max_link_clock * max_lanes * 8) / 10;
112 }
113
114 static int
115 intel_dp_mode_valid(struct drm_connector *connector,
116 struct drm_display_mode *mode)
117 {
118 struct intel_dp *intel_dp = intel_attached_dp(connector);
119 struct intel_connector *intel_connector = to_intel_connector(connector);
120 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
121 int target_clock = mode->clock;
122 int max_rate, mode_rate, max_lanes, max_link_clock;
123
124 if (is_edp(intel_dp) && fixed_mode) {
125 if (mode->hdisplay > fixed_mode->hdisplay)
126 return MODE_PANEL;
127
128 if (mode->vdisplay > fixed_mode->vdisplay)
129 return MODE_PANEL;
130
131 target_clock = fixed_mode->clock;
132 }
133
134 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
135 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
136
137 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
138 mode_rate = intel_dp_link_required(target_clock, 18);
139
140 if (mode_rate > max_rate)
141 return MODE_CLOCK_HIGH;
142
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
145
146 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
147 return MODE_H_ILLEGAL;
148
149 return MODE_OK;
150 }
151
152 static uint32_t
153 pack_aux(uint8_t *src, int src_bytes)
154 {
155 int i;
156 uint32_t v = 0;
157
158 if (src_bytes > 4)
159 src_bytes = 4;
160 for (i = 0; i < src_bytes; i++)
161 v |= ((uint32_t) src[i]) << ((3-i) * 8);
162 return v;
163 }
164
165 static void
166 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
167 {
168 int i;
169 if (dst_bytes > 4)
170 dst_bytes = 4;
171 for (i = 0; i < dst_bytes; i++)
172 dst[i] = src >> ((3-i) * 8);
173 }
174
175 /* hrawclock is 1/4 the FSB frequency */
176 static int
177 intel_hrawclk(struct drm_device *dev)
178 {
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 uint32_t clkcfg;
181
182 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
183 if (IS_VALLEYVIEW(dev))
184 return 200;
185
186 clkcfg = I915_READ(CLKCFG);
187 switch (clkcfg & CLKCFG_FSB_MASK) {
188 case CLKCFG_FSB_400:
189 return 100;
190 case CLKCFG_FSB_533:
191 return 133;
192 case CLKCFG_FSB_667:
193 return 166;
194 case CLKCFG_FSB_800:
195 return 200;
196 case CLKCFG_FSB_1067:
197 return 266;
198 case CLKCFG_FSB_1333:
199 return 333;
200 /* these two are just a guess; one of them might be right */
201 case CLKCFG_FSB_1600:
202 case CLKCFG_FSB_1600_ALT:
203 return 400;
204 default:
205 return 133;
206 }
207 }
208
209 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
210 {
211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
212 struct drm_i915_private *dev_priv = dev->dev_private;
213 u32 pp_stat_reg;
214
215 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
216 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
217 }
218
219 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
220 {
221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 u32 pp_ctrl_reg;
224
225 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
226 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
227 }
228
229 static void
230 intel_dp_check_edp(struct intel_dp *intel_dp)
231 {
232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
233 struct drm_i915_private *dev_priv = dev->dev_private;
234 u32 pp_stat_reg, pp_ctrl_reg;
235
236 if (!is_edp(intel_dp))
237 return;
238
239 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
240 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
241
242 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
243 WARN(1, "eDP powered off while attempting aux channel communication.\n");
244 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
245 I915_READ(pp_stat_reg),
246 I915_READ(pp_ctrl_reg));
247 }
248 }
249
250 static uint32_t
251 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
252 {
253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
257 uint32_t status;
258 bool done;
259
260 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
261 if (has_aux_irq)
262 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
263 msecs_to_jiffies_timeout(10));
264 else
265 done = wait_for_atomic(C, 10) == 0;
266 if (!done)
267 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
268 has_aux_irq);
269 #undef C
270
271 return status;
272 }
273
274 static int
275 intel_dp_aux_ch(struct intel_dp *intel_dp,
276 uint8_t *send, int send_bytes,
277 uint8_t *recv, int recv_size)
278 {
279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
280 struct drm_device *dev = intel_dig_port->base.base.dev;
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
283 uint32_t ch_data = ch_ctl + 4;
284 int i, ret, recv_bytes;
285 uint32_t status;
286 uint32_t aux_clock_divider;
287 int try, precharge;
288 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
289
290 /* dp aux is extremely sensitive to irq latency, hence request the
291 * lowest possible wakeup latency and so prevent the cpu from going into
292 * deep sleep states.
293 */
294 pm_qos_update_request(&dev_priv->pm_qos, 0);
295
296 intel_dp_check_edp(intel_dp);
297 /* The clock divider is based off the hrawclk,
298 * and would like to run at 2MHz. So, take the
299 * hrawclk value and divide by 2 and use that
300 *
301 * Note that PCH attached eDP panels should use a 125MHz input
302 * clock divider.
303 */
304 if (IS_VALLEYVIEW(dev)) {
305 aux_clock_divider = 100;
306 } else if (intel_dig_port->port == PORT_A) {
307 if (HAS_DDI(dev))
308 aux_clock_divider = DIV_ROUND_CLOSEST(
309 intel_ddi_get_cdclk_freq(dev_priv), 2000);
310 else if (IS_GEN6(dev) || IS_GEN7(dev))
311 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
312 else
313 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
314 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
315 /* Workaround for non-ULT HSW */
316 aux_clock_divider = 74;
317 } else if (HAS_PCH_SPLIT(dev)) {
318 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
319 } else {
320 aux_clock_divider = intel_hrawclk(dev) / 2;
321 }
322
323 if (IS_GEN6(dev))
324 precharge = 3;
325 else
326 precharge = 5;
327
328 /* Try to wait for any previous AUX channel activity */
329 for (try = 0; try < 3; try++) {
330 status = I915_READ_NOTRACE(ch_ctl);
331 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
332 break;
333 msleep(1);
334 }
335
336 if (try == 3) {
337 WARN(1, "dp_aux_ch not started status 0x%08x\n",
338 I915_READ(ch_ctl));
339 ret = -EBUSY;
340 goto out;
341 }
342
343 /* Must try at least 3 times according to DP spec */
344 for (try = 0; try < 5; try++) {
345 /* Load the send data into the aux channel data registers */
346 for (i = 0; i < send_bytes; i += 4)
347 I915_WRITE(ch_data + i,
348 pack_aux(send + i, send_bytes - i));
349
350 /* Send the command and wait for it to complete */
351 I915_WRITE(ch_ctl,
352 DP_AUX_CH_CTL_SEND_BUSY |
353 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
354 DP_AUX_CH_CTL_TIME_OUT_400us |
355 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
356 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
357 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
358 DP_AUX_CH_CTL_DONE |
359 DP_AUX_CH_CTL_TIME_OUT_ERROR |
360 DP_AUX_CH_CTL_RECEIVE_ERROR);
361
362 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
363
364 /* Clear done status and any errors */
365 I915_WRITE(ch_ctl,
366 status |
367 DP_AUX_CH_CTL_DONE |
368 DP_AUX_CH_CTL_TIME_OUT_ERROR |
369 DP_AUX_CH_CTL_RECEIVE_ERROR);
370
371 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
372 DP_AUX_CH_CTL_RECEIVE_ERROR))
373 continue;
374 if (status & DP_AUX_CH_CTL_DONE)
375 break;
376 }
377
378 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
379 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
380 ret = -EBUSY;
381 goto out;
382 }
383
384 /* Check for timeout or receive error.
385 * Timeouts occur when the sink is not connected
386 */
387 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
388 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
389 ret = -EIO;
390 goto out;
391 }
392
393 /* Timeouts occur when the device isn't connected, so they're
394 * "normal" -- don't fill the kernel log with these */
395 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
396 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
397 ret = -ETIMEDOUT;
398 goto out;
399 }
400
401 /* Unload any bytes sent back from the other side */
402 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
403 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
404 if (recv_bytes > recv_size)
405 recv_bytes = recv_size;
406
407 for (i = 0; i < recv_bytes; i += 4)
408 unpack_aux(I915_READ(ch_data + i),
409 recv + i, recv_bytes - i);
410
411 ret = recv_bytes;
412 out:
413 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
414
415 return ret;
416 }
417
418 /* Write data to the aux channel in native mode */
419 static int
420 intel_dp_aux_native_write(struct intel_dp *intel_dp,
421 uint16_t address, uint8_t *send, int send_bytes)
422 {
423 int ret;
424 uint8_t msg[20];
425 int msg_bytes;
426 uint8_t ack;
427
428 intel_dp_check_edp(intel_dp);
429 if (send_bytes > 16)
430 return -1;
431 msg[0] = AUX_NATIVE_WRITE << 4;
432 msg[1] = address >> 8;
433 msg[2] = address & 0xff;
434 msg[3] = send_bytes - 1;
435 memcpy(&msg[4], send, send_bytes);
436 msg_bytes = send_bytes + 4;
437 for (;;) {
438 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
439 if (ret < 0)
440 return ret;
441 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
442 break;
443 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
444 udelay(100);
445 else
446 return -EIO;
447 }
448 return send_bytes;
449 }
450
451 /* Write a single byte to the aux channel in native mode */
452 static int
453 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
454 uint16_t address, uint8_t byte)
455 {
456 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
457 }
458
459 /* read bytes from a native aux channel */
460 static int
461 intel_dp_aux_native_read(struct intel_dp *intel_dp,
462 uint16_t address, uint8_t *recv, int recv_bytes)
463 {
464 uint8_t msg[4];
465 int msg_bytes;
466 uint8_t reply[20];
467 int reply_bytes;
468 uint8_t ack;
469 int ret;
470
471 intel_dp_check_edp(intel_dp);
472 msg[0] = AUX_NATIVE_READ << 4;
473 msg[1] = address >> 8;
474 msg[2] = address & 0xff;
475 msg[3] = recv_bytes - 1;
476
477 msg_bytes = 4;
478 reply_bytes = recv_bytes + 1;
479
480 for (;;) {
481 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
482 reply, reply_bytes);
483 if (ret == 0)
484 return -EPROTO;
485 if (ret < 0)
486 return ret;
487 ack = reply[0];
488 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
489 memcpy(recv, reply + 1, ret - 1);
490 return ret - 1;
491 }
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 udelay(100);
494 else
495 return -EIO;
496 }
497 }
498
499 static int
500 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
501 uint8_t write_byte, uint8_t *read_byte)
502 {
503 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
504 struct intel_dp *intel_dp = container_of(adapter,
505 struct intel_dp,
506 adapter);
507 uint16_t address = algo_data->address;
508 uint8_t msg[5];
509 uint8_t reply[2];
510 unsigned retry;
511 int msg_bytes;
512 int reply_bytes;
513 int ret;
514
515 intel_dp_check_edp(intel_dp);
516 /* Set up the command byte */
517 if (mode & MODE_I2C_READ)
518 msg[0] = AUX_I2C_READ << 4;
519 else
520 msg[0] = AUX_I2C_WRITE << 4;
521
522 if (!(mode & MODE_I2C_STOP))
523 msg[0] |= AUX_I2C_MOT << 4;
524
525 msg[1] = address >> 8;
526 msg[2] = address;
527
528 switch (mode) {
529 case MODE_I2C_WRITE:
530 msg[3] = 0;
531 msg[4] = write_byte;
532 msg_bytes = 5;
533 reply_bytes = 1;
534 break;
535 case MODE_I2C_READ:
536 msg[3] = 0;
537 msg_bytes = 4;
538 reply_bytes = 2;
539 break;
540 default:
541 msg_bytes = 3;
542 reply_bytes = 1;
543 break;
544 }
545
546 for (retry = 0; retry < 5; retry++) {
547 ret = intel_dp_aux_ch(intel_dp,
548 msg, msg_bytes,
549 reply, reply_bytes);
550 if (ret < 0) {
551 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
552 return ret;
553 }
554
555 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
556 case AUX_NATIVE_REPLY_ACK:
557 /* I2C-over-AUX Reply field is only valid
558 * when paired with AUX ACK.
559 */
560 break;
561 case AUX_NATIVE_REPLY_NACK:
562 DRM_DEBUG_KMS("aux_ch native nack\n");
563 return -EREMOTEIO;
564 case AUX_NATIVE_REPLY_DEFER:
565 udelay(100);
566 continue;
567 default:
568 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
569 reply[0]);
570 return -EREMOTEIO;
571 }
572
573 switch (reply[0] & AUX_I2C_REPLY_MASK) {
574 case AUX_I2C_REPLY_ACK:
575 if (mode == MODE_I2C_READ) {
576 *read_byte = reply[1];
577 }
578 return reply_bytes - 1;
579 case AUX_I2C_REPLY_NACK:
580 DRM_DEBUG_KMS("aux_i2c nack\n");
581 return -EREMOTEIO;
582 case AUX_I2C_REPLY_DEFER:
583 DRM_DEBUG_KMS("aux_i2c defer\n");
584 udelay(100);
585 break;
586 default:
587 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
588 return -EREMOTEIO;
589 }
590 }
591
592 DRM_ERROR("too many retries, giving up\n");
593 return -EREMOTEIO;
594 }
595
596 static int
597 intel_dp_i2c_init(struct intel_dp *intel_dp,
598 struct intel_connector *intel_connector, const char *name)
599 {
600 int ret;
601
602 DRM_DEBUG_KMS("i2c_init %s\n", name);
603 intel_dp->algo.running = false;
604 intel_dp->algo.address = 0;
605 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
606
607 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
608 intel_dp->adapter.owner = THIS_MODULE;
609 intel_dp->adapter.class = I2C_CLASS_DDC;
610 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
611 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
612 intel_dp->adapter.algo_data = &intel_dp->algo;
613 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
614
615 ironlake_edp_panel_vdd_on(intel_dp);
616 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
617 ironlake_edp_panel_vdd_off(intel_dp, false);
618 return ret;
619 }
620
621 static void
622 intel_dp_set_clock(struct intel_encoder *encoder,
623 struct intel_crtc_config *pipe_config, int link_bw)
624 {
625 struct drm_device *dev = encoder->base.dev;
626
627 if (IS_G4X(dev)) {
628 if (link_bw == DP_LINK_BW_1_62) {
629 pipe_config->dpll.p1 = 2;
630 pipe_config->dpll.p2 = 10;
631 pipe_config->dpll.n = 2;
632 pipe_config->dpll.m1 = 23;
633 pipe_config->dpll.m2 = 8;
634 } else {
635 pipe_config->dpll.p1 = 1;
636 pipe_config->dpll.p2 = 10;
637 pipe_config->dpll.n = 1;
638 pipe_config->dpll.m1 = 14;
639 pipe_config->dpll.m2 = 2;
640 }
641 pipe_config->clock_set = true;
642 } else if (IS_HASWELL(dev)) {
643 /* Haswell has special-purpose DP DDI clocks. */
644 } else if (HAS_PCH_SPLIT(dev)) {
645 if (link_bw == DP_LINK_BW_1_62) {
646 pipe_config->dpll.n = 1;
647 pipe_config->dpll.p1 = 2;
648 pipe_config->dpll.p2 = 10;
649 pipe_config->dpll.m1 = 12;
650 pipe_config->dpll.m2 = 9;
651 } else {
652 pipe_config->dpll.n = 2;
653 pipe_config->dpll.p1 = 1;
654 pipe_config->dpll.p2 = 10;
655 pipe_config->dpll.m1 = 14;
656 pipe_config->dpll.m2 = 8;
657 }
658 pipe_config->clock_set = true;
659 } else if (IS_VALLEYVIEW(dev)) {
660 /* FIXME: Need to figure out optimized DP clocks for vlv. */
661 }
662 }
663
664 bool
665 intel_dp_compute_config(struct intel_encoder *encoder,
666 struct intel_crtc_config *pipe_config)
667 {
668 struct drm_device *dev = encoder->base.dev;
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
672 enum port port = dp_to_dig_port(intel_dp)->port;
673 struct intel_crtc *intel_crtc = encoder->new_crtc;
674 struct intel_connector *intel_connector = intel_dp->attached_connector;
675 int lane_count, clock;
676 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
677 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
678 int bpp, mode_rate;
679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
680 int link_avail, link_clock;
681
682 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
683 pipe_config->has_pch_encoder = true;
684
685 pipe_config->has_dp_encoder = true;
686
687 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
688 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
689 adjusted_mode);
690 if (!HAS_PCH_SPLIT(dev))
691 intel_gmch_panel_fitting(intel_crtc, pipe_config,
692 intel_connector->panel.fitting_mode);
693 else
694 intel_pch_panel_fitting(intel_crtc, pipe_config,
695 intel_connector->panel.fitting_mode);
696 }
697
698 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
699 return false;
700
701 DRM_DEBUG_KMS("DP link computation with max lane count %i "
702 "max bw %02x pixel clock %iKHz\n",
703 max_lane_count, bws[max_clock], adjusted_mode->clock);
704
705 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
706 * bpc in between. */
707 bpp = pipe_config->pipe_bpp;
708 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
709 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
710
711 for (; bpp >= 6*3; bpp -= 2*3) {
712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
713
714 for (clock = 0; clock <= max_clock; clock++) {
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
716 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
717 link_avail = intel_dp_max_data_rate(link_clock,
718 lane_count);
719
720 if (mode_rate <= link_avail) {
721 goto found;
722 }
723 }
724 }
725 }
726
727 return false;
728
729 found:
730 if (intel_dp->color_range_auto) {
731 /*
732 * See:
733 * CEA-861-E - 5.1 Default Encoding Parameters
734 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
735 */
736 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
737 intel_dp->color_range = DP_COLOR_RANGE_16_235;
738 else
739 intel_dp->color_range = 0;
740 }
741
742 if (intel_dp->color_range)
743 pipe_config->limited_color_range = true;
744
745 intel_dp->link_bw = bws[clock];
746 intel_dp->lane_count = lane_count;
747 pipe_config->pipe_bpp = bpp;
748 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
749
750 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
751 intel_dp->link_bw, intel_dp->lane_count,
752 pipe_config->port_clock, bpp);
753 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
754 mode_rate, link_avail);
755
756 intel_link_compute_m_n(bpp, lane_count,
757 adjusted_mode->clock, pipe_config->port_clock,
758 &pipe_config->dp_m_n);
759
760 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
761
762 return true;
763 }
764
765 void intel_dp_init_link_config(struct intel_dp *intel_dp)
766 {
767 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
768 intel_dp->link_configuration[0] = intel_dp->link_bw;
769 intel_dp->link_configuration[1] = intel_dp->lane_count;
770 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
771 /*
772 * Check for DPCD version > 1.1 and enhanced framing support
773 */
774 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
775 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
776 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
777 }
778 }
779
780 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
781 {
782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
783 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
784 struct drm_device *dev = crtc->base.dev;
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 u32 dpa_ctl;
787
788 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
789 dpa_ctl = I915_READ(DP_A);
790 dpa_ctl &= ~DP_PLL_FREQ_MASK;
791
792 if (crtc->config.port_clock == 162000) {
793 /* For a long time we've carried around a ILK-DevA w/a for the
794 * 160MHz clock. If we're really unlucky, it's still required.
795 */
796 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
797 dpa_ctl |= DP_PLL_FREQ_160MHZ;
798 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
799 } else {
800 dpa_ctl |= DP_PLL_FREQ_270MHZ;
801 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
802 }
803
804 I915_WRITE(DP_A, dpa_ctl);
805
806 POSTING_READ(DP_A);
807 udelay(500);
808 }
809
810 static void
811 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode)
813 {
814 struct drm_device *dev = encoder->dev;
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
817 enum port port = dp_to_dig_port(intel_dp)->port;
818 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
819
820 /*
821 * There are four kinds of DP registers:
822 *
823 * IBX PCH
824 * SNB CPU
825 * IVB CPU
826 * CPT PCH
827 *
828 * IBX PCH and CPU are the same for almost everything,
829 * except that the CPU DP PLL is configured in this
830 * register
831 *
832 * CPT PCH is quite different, having many bits moved
833 * to the TRANS_DP_CTL register instead. That
834 * configuration happens (oddly) in ironlake_pch_enable
835 */
836
837 /* Preserve the BIOS-computed detected bit. This is
838 * supposed to be read-only.
839 */
840 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
841
842 /* Handle DP bits in common between all three register formats */
843 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
844 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
845
846 if (intel_dp->has_audio) {
847 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
848 pipe_name(crtc->pipe));
849 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
850 intel_write_eld(encoder, adjusted_mode);
851 }
852
853 intel_dp_init_link_config(intel_dp);
854
855 /* Split out the IBX/CPU vs CPT settings */
856
857 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
858 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
859 intel_dp->DP |= DP_SYNC_HS_HIGH;
860 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
861 intel_dp->DP |= DP_SYNC_VS_HIGH;
862 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
863
864 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
865 intel_dp->DP |= DP_ENHANCED_FRAMING;
866
867 intel_dp->DP |= crtc->pipe << 29;
868 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
869 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
870 intel_dp->DP |= intel_dp->color_range;
871
872 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
873 intel_dp->DP |= DP_SYNC_HS_HIGH;
874 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
875 intel_dp->DP |= DP_SYNC_VS_HIGH;
876 intel_dp->DP |= DP_LINK_TRAIN_OFF;
877
878 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
879 intel_dp->DP |= DP_ENHANCED_FRAMING;
880
881 if (crtc->pipe == 1)
882 intel_dp->DP |= DP_PIPEB_SELECT;
883 } else {
884 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
885 }
886
887 if (port == PORT_A && !IS_VALLEYVIEW(dev))
888 ironlake_set_pll_cpu_edp(intel_dp);
889 }
890
891 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
892 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
893
894 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
895 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
896
897 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
898 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
899
900 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
901 u32 mask,
902 u32 value)
903 {
904 struct drm_device *dev = intel_dp_to_dev(intel_dp);
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 u32 pp_stat_reg, pp_ctrl_reg;
907
908 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
909 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
910
911 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
912 mask, value,
913 I915_READ(pp_stat_reg),
914 I915_READ(pp_ctrl_reg));
915
916 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
917 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
918 I915_READ(pp_stat_reg),
919 I915_READ(pp_ctrl_reg));
920 }
921 }
922
923 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
924 {
925 DRM_DEBUG_KMS("Wait for panel power on\n");
926 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
927 }
928
929 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
930 {
931 DRM_DEBUG_KMS("Wait for panel power off time\n");
932 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
933 }
934
935 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
936 {
937 DRM_DEBUG_KMS("Wait for panel power cycle\n");
938 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
939 }
940
941
942 /* Read the current pp_control value, unlocking the register if it
943 * is locked
944 */
945
946 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
947 {
948 struct drm_device *dev = intel_dp_to_dev(intel_dp);
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 control;
951 u32 pp_ctrl_reg;
952
953 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
954 control = I915_READ(pp_ctrl_reg);
955
956 control &= ~PANEL_UNLOCK_MASK;
957 control |= PANEL_UNLOCK_REGS;
958 return control;
959 }
960
961 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
962 {
963 struct drm_device *dev = intel_dp_to_dev(intel_dp);
964 struct drm_i915_private *dev_priv = dev->dev_private;
965 u32 pp;
966 u32 pp_stat_reg, pp_ctrl_reg;
967
968 if (!is_edp(intel_dp))
969 return;
970 DRM_DEBUG_KMS("Turn eDP VDD on\n");
971
972 WARN(intel_dp->want_panel_vdd,
973 "eDP VDD already requested on\n");
974
975 intel_dp->want_panel_vdd = true;
976
977 if (ironlake_edp_have_panel_vdd(intel_dp)) {
978 DRM_DEBUG_KMS("eDP VDD already on\n");
979 return;
980 }
981
982 if (!ironlake_edp_have_panel_power(intel_dp))
983 ironlake_wait_panel_power_cycle(intel_dp);
984
985 pp = ironlake_get_pp_control(intel_dp);
986 pp |= EDP_FORCE_VDD;
987
988 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
989 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
990
991 I915_WRITE(pp_ctrl_reg, pp);
992 POSTING_READ(pp_ctrl_reg);
993 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
994 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
995 /*
996 * If the panel wasn't on, delay before accessing aux channel
997 */
998 if (!ironlake_edp_have_panel_power(intel_dp)) {
999 DRM_DEBUG_KMS("eDP was not running\n");
1000 msleep(intel_dp->panel_power_up_delay);
1001 }
1002 }
1003
1004 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1005 {
1006 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 u32 pp;
1009 u32 pp_stat_reg, pp_ctrl_reg;
1010
1011 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1012
1013 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1014 pp = ironlake_get_pp_control(intel_dp);
1015 pp &= ~EDP_FORCE_VDD;
1016
1017 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1018 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1019
1020 I915_WRITE(pp_ctrl_reg, pp);
1021 POSTING_READ(pp_ctrl_reg);
1022
1023 /* Make sure sequencer is idle before allowing subsequent activity */
1024 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1025 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1026 msleep(intel_dp->panel_power_down_delay);
1027 }
1028 }
1029
1030 static void ironlake_panel_vdd_work(struct work_struct *__work)
1031 {
1032 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1033 struct intel_dp, panel_vdd_work);
1034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1035
1036 mutex_lock(&dev->mode_config.mutex);
1037 ironlake_panel_vdd_off_sync(intel_dp);
1038 mutex_unlock(&dev->mode_config.mutex);
1039 }
1040
1041 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1042 {
1043 if (!is_edp(intel_dp))
1044 return;
1045
1046 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1047 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1048
1049 intel_dp->want_panel_vdd = false;
1050
1051 if (sync) {
1052 ironlake_panel_vdd_off_sync(intel_dp);
1053 } else {
1054 /*
1055 * Queue the timer to fire a long
1056 * time from now (relative to the power down delay)
1057 * to keep the panel power up across a sequence of operations
1058 */
1059 schedule_delayed_work(&intel_dp->panel_vdd_work,
1060 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1061 }
1062 }
1063
1064 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1065 {
1066 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1068 u32 pp;
1069 u32 pp_ctrl_reg;
1070
1071 if (!is_edp(intel_dp))
1072 return;
1073
1074 DRM_DEBUG_KMS("Turn eDP power on\n");
1075
1076 if (ironlake_edp_have_panel_power(intel_dp)) {
1077 DRM_DEBUG_KMS("eDP power already on\n");
1078 return;
1079 }
1080
1081 ironlake_wait_panel_power_cycle(intel_dp);
1082
1083 pp = ironlake_get_pp_control(intel_dp);
1084 if (IS_GEN5(dev)) {
1085 /* ILK workaround: disable reset around power sequence */
1086 pp &= ~PANEL_POWER_RESET;
1087 I915_WRITE(PCH_PP_CONTROL, pp);
1088 POSTING_READ(PCH_PP_CONTROL);
1089 }
1090
1091 pp |= POWER_TARGET_ON;
1092 if (!IS_GEN5(dev))
1093 pp |= PANEL_POWER_RESET;
1094
1095 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1096
1097 I915_WRITE(pp_ctrl_reg, pp);
1098 POSTING_READ(pp_ctrl_reg);
1099
1100 ironlake_wait_panel_on(intel_dp);
1101
1102 if (IS_GEN5(dev)) {
1103 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1104 I915_WRITE(PCH_PP_CONTROL, pp);
1105 POSTING_READ(PCH_PP_CONTROL);
1106 }
1107 }
1108
1109 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1110 {
1111 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1113 u32 pp;
1114 u32 pp_ctrl_reg;
1115
1116 if (!is_edp(intel_dp))
1117 return;
1118
1119 DRM_DEBUG_KMS("Turn eDP power off\n");
1120
1121 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1122
1123 pp = ironlake_get_pp_control(intel_dp);
1124 /* We need to switch off panel power _and_ force vdd, for otherwise some
1125 * panels get very unhappy and cease to work. */
1126 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1127
1128 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1129
1130 I915_WRITE(pp_ctrl_reg, pp);
1131 POSTING_READ(pp_ctrl_reg);
1132
1133 intel_dp->want_panel_vdd = false;
1134
1135 ironlake_wait_panel_off(intel_dp);
1136 }
1137
1138 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1139 {
1140 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1141 struct drm_device *dev = intel_dig_port->base.base.dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1144 u32 pp;
1145 u32 pp_ctrl_reg;
1146
1147 if (!is_edp(intel_dp))
1148 return;
1149
1150 DRM_DEBUG_KMS("\n");
1151 /*
1152 * If we enable the backlight right away following a panel power
1153 * on, we may see slight flicker as the panel syncs with the eDP
1154 * link. So delay a bit to make sure the image is solid before
1155 * allowing it to appear.
1156 */
1157 msleep(intel_dp->backlight_on_delay);
1158 pp = ironlake_get_pp_control(intel_dp);
1159 pp |= EDP_BLC_ENABLE;
1160
1161 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1162
1163 I915_WRITE(pp_ctrl_reg, pp);
1164 POSTING_READ(pp_ctrl_reg);
1165
1166 intel_panel_enable_backlight(dev, pipe);
1167 }
1168
1169 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1170 {
1171 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 pp;
1174 u32 pp_ctrl_reg;
1175
1176 if (!is_edp(intel_dp))
1177 return;
1178
1179 intel_panel_disable_backlight(dev);
1180
1181 DRM_DEBUG_KMS("\n");
1182 pp = ironlake_get_pp_control(intel_dp);
1183 pp &= ~EDP_BLC_ENABLE;
1184
1185 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1186
1187 I915_WRITE(pp_ctrl_reg, pp);
1188 POSTING_READ(pp_ctrl_reg);
1189 msleep(intel_dp->backlight_off_delay);
1190 }
1191
1192 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1193 {
1194 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1195 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1196 struct drm_device *dev = crtc->dev;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 u32 dpa_ctl;
1199
1200 assert_pipe_disabled(dev_priv,
1201 to_intel_crtc(crtc)->pipe);
1202
1203 DRM_DEBUG_KMS("\n");
1204 dpa_ctl = I915_READ(DP_A);
1205 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1206 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1207
1208 /* We don't adjust intel_dp->DP while tearing down the link, to
1209 * facilitate link retraining (e.g. after hotplug). Hence clear all
1210 * enable bits here to ensure that we don't enable too much. */
1211 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1212 intel_dp->DP |= DP_PLL_ENABLE;
1213 I915_WRITE(DP_A, intel_dp->DP);
1214 POSTING_READ(DP_A);
1215 udelay(200);
1216 }
1217
1218 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1219 {
1220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222 struct drm_device *dev = crtc->dev;
1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 u32 dpa_ctl;
1225
1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1228
1229 dpa_ctl = I915_READ(DP_A);
1230 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1231 "dp pll off, should be on\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234 /* We can't rely on the value tracked for the DP register in
1235 * intel_dp->DP because link_down must not change that (otherwise link
1236 * re-training will fail. */
1237 dpa_ctl &= ~DP_PLL_ENABLE;
1238 I915_WRITE(DP_A, dpa_ctl);
1239 POSTING_READ(DP_A);
1240 udelay(200);
1241 }
1242
1243 /* If the sink supports it, try to set the power state appropriately */
1244 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1245 {
1246 int ret, i;
1247
1248 /* Should have a valid DPCD by this point */
1249 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1250 return;
1251
1252 if (mode != DRM_MODE_DPMS_ON) {
1253 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1254 DP_SET_POWER_D3);
1255 if (ret != 1)
1256 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1257 } else {
1258 /*
1259 * When turning on, we need to retry for 1ms to give the sink
1260 * time to wake up.
1261 */
1262 for (i = 0; i < 3; i++) {
1263 ret = intel_dp_aux_native_write_1(intel_dp,
1264 DP_SET_POWER,
1265 DP_SET_POWER_D0);
1266 if (ret == 1)
1267 break;
1268 msleep(1);
1269 }
1270 }
1271 }
1272
1273 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1274 enum pipe *pipe)
1275 {
1276 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1277 enum port port = dp_to_dig_port(intel_dp)->port;
1278 struct drm_device *dev = encoder->base.dev;
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 u32 tmp = I915_READ(intel_dp->output_reg);
1281
1282 if (!(tmp & DP_PORT_EN))
1283 return false;
1284
1285 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1286 *pipe = PORT_TO_PIPE_CPT(tmp);
1287 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1288 *pipe = PORT_TO_PIPE(tmp);
1289 } else {
1290 u32 trans_sel;
1291 u32 trans_dp;
1292 int i;
1293
1294 switch (intel_dp->output_reg) {
1295 case PCH_DP_B:
1296 trans_sel = TRANS_DP_PORT_SEL_B;
1297 break;
1298 case PCH_DP_C:
1299 trans_sel = TRANS_DP_PORT_SEL_C;
1300 break;
1301 case PCH_DP_D:
1302 trans_sel = TRANS_DP_PORT_SEL_D;
1303 break;
1304 default:
1305 return true;
1306 }
1307
1308 for_each_pipe(i) {
1309 trans_dp = I915_READ(TRANS_DP_CTL(i));
1310 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1311 *pipe = i;
1312 return true;
1313 }
1314 }
1315
1316 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1317 intel_dp->output_reg);
1318 }
1319
1320 return true;
1321 }
1322
1323 static void intel_dp_get_config(struct intel_encoder *encoder,
1324 struct intel_crtc_config *pipe_config)
1325 {
1326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1327 u32 tmp, flags = 0;
1328 struct drm_device *dev = encoder->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 enum port port = dp_to_dig_port(intel_dp)->port;
1331 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1332
1333 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1334 tmp = I915_READ(intel_dp->output_reg);
1335 if (tmp & DP_SYNC_HS_HIGH)
1336 flags |= DRM_MODE_FLAG_PHSYNC;
1337 else
1338 flags |= DRM_MODE_FLAG_NHSYNC;
1339
1340 if (tmp & DP_SYNC_VS_HIGH)
1341 flags |= DRM_MODE_FLAG_PVSYNC;
1342 else
1343 flags |= DRM_MODE_FLAG_NVSYNC;
1344 } else {
1345 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1346 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1347 flags |= DRM_MODE_FLAG_PHSYNC;
1348 else
1349 flags |= DRM_MODE_FLAG_NHSYNC;
1350
1351 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1352 flags |= DRM_MODE_FLAG_PVSYNC;
1353 else
1354 flags |= DRM_MODE_FLAG_NVSYNC;
1355 }
1356
1357 pipe_config->adjusted_mode.flags |= flags;
1358
1359 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1360 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1361 pipe_config->port_clock = 162000;
1362 else
1363 pipe_config->port_clock = 270000;
1364 }
1365 }
1366
1367 static void intel_disable_dp(struct intel_encoder *encoder)
1368 {
1369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1370 enum port port = dp_to_dig_port(intel_dp)->port;
1371 struct drm_device *dev = encoder->base.dev;
1372
1373 /* Make sure the panel is off before trying to change the mode. But also
1374 * ensure that we have vdd while we switch off the panel. */
1375 ironlake_edp_panel_vdd_on(intel_dp);
1376 ironlake_edp_backlight_off(intel_dp);
1377 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1378 ironlake_edp_panel_off(intel_dp);
1379
1380 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1381 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1382 intel_dp_link_down(intel_dp);
1383 }
1384
1385 static void intel_post_disable_dp(struct intel_encoder *encoder)
1386 {
1387 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1388 enum port port = dp_to_dig_port(intel_dp)->port;
1389 struct drm_device *dev = encoder->base.dev;
1390
1391 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1392 intel_dp_link_down(intel_dp);
1393 if (!IS_VALLEYVIEW(dev))
1394 ironlake_edp_pll_off(intel_dp);
1395 }
1396 }
1397
1398 static void intel_enable_dp(struct intel_encoder *encoder)
1399 {
1400 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1401 struct drm_device *dev = encoder->base.dev;
1402 struct drm_i915_private *dev_priv = dev->dev_private;
1403 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1404
1405 if (WARN_ON(dp_reg & DP_PORT_EN))
1406 return;
1407
1408 ironlake_edp_panel_vdd_on(intel_dp);
1409 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1410 intel_dp_start_link_train(intel_dp);
1411 ironlake_edp_panel_on(intel_dp);
1412 ironlake_edp_panel_vdd_off(intel_dp, true);
1413 intel_dp_complete_link_train(intel_dp);
1414 intel_dp_stop_link_train(intel_dp);
1415 ironlake_edp_backlight_on(intel_dp);
1416
1417 if (IS_VALLEYVIEW(dev)) {
1418 struct intel_digital_port *dport =
1419 enc_to_dig_port(&encoder->base);
1420 int channel = vlv_dport_to_channel(dport);
1421
1422 vlv_wait_port_ready(dev_priv, channel);
1423 }
1424 }
1425
1426 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1427 {
1428 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1429 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1430 struct drm_device *dev = encoder->base.dev;
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432
1433 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1434 ironlake_edp_pll_on(intel_dp);
1435
1436 if (IS_VALLEYVIEW(dev)) {
1437 struct intel_crtc *intel_crtc =
1438 to_intel_crtc(encoder->base.crtc);
1439 int port = vlv_dport_to_channel(dport);
1440 int pipe = intel_crtc->pipe;
1441 u32 val;
1442
1443 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1444 val = 0;
1445 if (pipe)
1446 val |= (1<<21);
1447 else
1448 val &= ~(1<<21);
1449 val |= 0x001000c4;
1450 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1451
1452 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1453 0x00760018);
1454 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1455 0x00400888);
1456 }
1457 }
1458
1459 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1460 {
1461 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1462 struct drm_device *dev = encoder->base.dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 int port = vlv_dport_to_channel(dport);
1465
1466 if (!IS_VALLEYVIEW(dev))
1467 return;
1468
1469 /* Program Tx lane resets to default */
1470 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1471 DPIO_PCS_TX_LANE2_RESET |
1472 DPIO_PCS_TX_LANE1_RESET);
1473 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1474 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1475 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1476 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1477 DPIO_PCS_CLK_SOFT_RESET);
1478
1479 /* Fix up inter-pair skew failure */
1480 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1481 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1482 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1483 }
1484
1485 /*
1486 * Native read with retry for link status and receiver capability reads for
1487 * cases where the sink may still be asleep.
1488 */
1489 static bool
1490 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1491 uint8_t *recv, int recv_bytes)
1492 {
1493 int ret, i;
1494
1495 /*
1496 * Sinks are *supposed* to come up within 1ms from an off state,
1497 * but we're also supposed to retry 3 times per the spec.
1498 */
1499 for (i = 0; i < 3; i++) {
1500 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1501 recv_bytes);
1502 if (ret == recv_bytes)
1503 return true;
1504 msleep(1);
1505 }
1506
1507 return false;
1508 }
1509
1510 /*
1511 * Fetch AUX CH registers 0x202 - 0x207 which contain
1512 * link status information
1513 */
1514 static bool
1515 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1516 {
1517 return intel_dp_aux_native_read_retry(intel_dp,
1518 DP_LANE0_1_STATUS,
1519 link_status,
1520 DP_LINK_STATUS_SIZE);
1521 }
1522
1523 #if 0
1524 static char *voltage_names[] = {
1525 "0.4V", "0.6V", "0.8V", "1.2V"
1526 };
1527 static char *pre_emph_names[] = {
1528 "0dB", "3.5dB", "6dB", "9.5dB"
1529 };
1530 static char *link_train_names[] = {
1531 "pattern 1", "pattern 2", "idle", "off"
1532 };
1533 #endif
1534
1535 /*
1536 * These are source-specific values; current Intel hardware supports
1537 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1538 */
1539
1540 static uint8_t
1541 intel_dp_voltage_max(struct intel_dp *intel_dp)
1542 {
1543 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1544 enum port port = dp_to_dig_port(intel_dp)->port;
1545
1546 if (IS_VALLEYVIEW(dev))
1547 return DP_TRAIN_VOLTAGE_SWING_1200;
1548 else if (IS_GEN7(dev) && port == PORT_A)
1549 return DP_TRAIN_VOLTAGE_SWING_800;
1550 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1551 return DP_TRAIN_VOLTAGE_SWING_1200;
1552 else
1553 return DP_TRAIN_VOLTAGE_SWING_800;
1554 }
1555
1556 static uint8_t
1557 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1558 {
1559 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1560 enum port port = dp_to_dig_port(intel_dp)->port;
1561
1562 if (HAS_DDI(dev)) {
1563 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1564 case DP_TRAIN_VOLTAGE_SWING_400:
1565 return DP_TRAIN_PRE_EMPHASIS_9_5;
1566 case DP_TRAIN_VOLTAGE_SWING_600:
1567 return DP_TRAIN_PRE_EMPHASIS_6;
1568 case DP_TRAIN_VOLTAGE_SWING_800:
1569 return DP_TRAIN_PRE_EMPHASIS_3_5;
1570 case DP_TRAIN_VOLTAGE_SWING_1200:
1571 default:
1572 return DP_TRAIN_PRE_EMPHASIS_0;
1573 }
1574 } else if (IS_VALLEYVIEW(dev)) {
1575 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576 case DP_TRAIN_VOLTAGE_SWING_400:
1577 return DP_TRAIN_PRE_EMPHASIS_9_5;
1578 case DP_TRAIN_VOLTAGE_SWING_600:
1579 return DP_TRAIN_PRE_EMPHASIS_6;
1580 case DP_TRAIN_VOLTAGE_SWING_800:
1581 return DP_TRAIN_PRE_EMPHASIS_3_5;
1582 case DP_TRAIN_VOLTAGE_SWING_1200:
1583 default:
1584 return DP_TRAIN_PRE_EMPHASIS_0;
1585 }
1586 } else if (IS_GEN7(dev) && port == PORT_A) {
1587 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1588 case DP_TRAIN_VOLTAGE_SWING_400:
1589 return DP_TRAIN_PRE_EMPHASIS_6;
1590 case DP_TRAIN_VOLTAGE_SWING_600:
1591 case DP_TRAIN_VOLTAGE_SWING_800:
1592 return DP_TRAIN_PRE_EMPHASIS_3_5;
1593 default:
1594 return DP_TRAIN_PRE_EMPHASIS_0;
1595 }
1596 } else {
1597 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1598 case DP_TRAIN_VOLTAGE_SWING_400:
1599 return DP_TRAIN_PRE_EMPHASIS_6;
1600 case DP_TRAIN_VOLTAGE_SWING_600:
1601 return DP_TRAIN_PRE_EMPHASIS_6;
1602 case DP_TRAIN_VOLTAGE_SWING_800:
1603 return DP_TRAIN_PRE_EMPHASIS_3_5;
1604 case DP_TRAIN_VOLTAGE_SWING_1200:
1605 default:
1606 return DP_TRAIN_PRE_EMPHASIS_0;
1607 }
1608 }
1609 }
1610
1611 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1612 {
1613 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1616 unsigned long demph_reg_value, preemph_reg_value,
1617 uniqtranscale_reg_value;
1618 uint8_t train_set = intel_dp->train_set[0];
1619 int port = vlv_dport_to_channel(dport);
1620
1621 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1622 case DP_TRAIN_PRE_EMPHASIS_0:
1623 preemph_reg_value = 0x0004000;
1624 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1625 case DP_TRAIN_VOLTAGE_SWING_400:
1626 demph_reg_value = 0x2B405555;
1627 uniqtranscale_reg_value = 0x552AB83A;
1628 break;
1629 case DP_TRAIN_VOLTAGE_SWING_600:
1630 demph_reg_value = 0x2B404040;
1631 uniqtranscale_reg_value = 0x5548B83A;
1632 break;
1633 case DP_TRAIN_VOLTAGE_SWING_800:
1634 demph_reg_value = 0x2B245555;
1635 uniqtranscale_reg_value = 0x5560B83A;
1636 break;
1637 case DP_TRAIN_VOLTAGE_SWING_1200:
1638 demph_reg_value = 0x2B405555;
1639 uniqtranscale_reg_value = 0x5598DA3A;
1640 break;
1641 default:
1642 return 0;
1643 }
1644 break;
1645 case DP_TRAIN_PRE_EMPHASIS_3_5:
1646 preemph_reg_value = 0x0002000;
1647 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1648 case DP_TRAIN_VOLTAGE_SWING_400:
1649 demph_reg_value = 0x2B404040;
1650 uniqtranscale_reg_value = 0x5552B83A;
1651 break;
1652 case DP_TRAIN_VOLTAGE_SWING_600:
1653 demph_reg_value = 0x2B404848;
1654 uniqtranscale_reg_value = 0x5580B83A;
1655 break;
1656 case DP_TRAIN_VOLTAGE_SWING_800:
1657 demph_reg_value = 0x2B404040;
1658 uniqtranscale_reg_value = 0x55ADDA3A;
1659 break;
1660 default:
1661 return 0;
1662 }
1663 break;
1664 case DP_TRAIN_PRE_EMPHASIS_6:
1665 preemph_reg_value = 0x0000000;
1666 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1667 case DP_TRAIN_VOLTAGE_SWING_400:
1668 demph_reg_value = 0x2B305555;
1669 uniqtranscale_reg_value = 0x5570B83A;
1670 break;
1671 case DP_TRAIN_VOLTAGE_SWING_600:
1672 demph_reg_value = 0x2B2B4040;
1673 uniqtranscale_reg_value = 0x55ADDA3A;
1674 break;
1675 default:
1676 return 0;
1677 }
1678 break;
1679 case DP_TRAIN_PRE_EMPHASIS_9_5:
1680 preemph_reg_value = 0x0006000;
1681 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1682 case DP_TRAIN_VOLTAGE_SWING_400:
1683 demph_reg_value = 0x1B405555;
1684 uniqtranscale_reg_value = 0x55ADDA3A;
1685 break;
1686 default:
1687 return 0;
1688 }
1689 break;
1690 default:
1691 return 0;
1692 }
1693
1694 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1695 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1696 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1697 uniqtranscale_reg_value);
1698 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1699 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1700 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1701 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1702
1703 return 0;
1704 }
1705
1706 static void
1707 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1708 {
1709 uint8_t v = 0;
1710 uint8_t p = 0;
1711 int lane;
1712 uint8_t voltage_max;
1713 uint8_t preemph_max;
1714
1715 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1716 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1717 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1718
1719 if (this_v > v)
1720 v = this_v;
1721 if (this_p > p)
1722 p = this_p;
1723 }
1724
1725 voltage_max = intel_dp_voltage_max(intel_dp);
1726 if (v >= voltage_max)
1727 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1728
1729 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1730 if (p >= preemph_max)
1731 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1732
1733 for (lane = 0; lane < 4; lane++)
1734 intel_dp->train_set[lane] = v | p;
1735 }
1736
1737 static uint32_t
1738 intel_gen4_signal_levels(uint8_t train_set)
1739 {
1740 uint32_t signal_levels = 0;
1741
1742 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1743 case DP_TRAIN_VOLTAGE_SWING_400:
1744 default:
1745 signal_levels |= DP_VOLTAGE_0_4;
1746 break;
1747 case DP_TRAIN_VOLTAGE_SWING_600:
1748 signal_levels |= DP_VOLTAGE_0_6;
1749 break;
1750 case DP_TRAIN_VOLTAGE_SWING_800:
1751 signal_levels |= DP_VOLTAGE_0_8;
1752 break;
1753 case DP_TRAIN_VOLTAGE_SWING_1200:
1754 signal_levels |= DP_VOLTAGE_1_2;
1755 break;
1756 }
1757 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1758 case DP_TRAIN_PRE_EMPHASIS_0:
1759 default:
1760 signal_levels |= DP_PRE_EMPHASIS_0;
1761 break;
1762 case DP_TRAIN_PRE_EMPHASIS_3_5:
1763 signal_levels |= DP_PRE_EMPHASIS_3_5;
1764 break;
1765 case DP_TRAIN_PRE_EMPHASIS_6:
1766 signal_levels |= DP_PRE_EMPHASIS_6;
1767 break;
1768 case DP_TRAIN_PRE_EMPHASIS_9_5:
1769 signal_levels |= DP_PRE_EMPHASIS_9_5;
1770 break;
1771 }
1772 return signal_levels;
1773 }
1774
1775 /* Gen6's DP voltage swing and pre-emphasis control */
1776 static uint32_t
1777 intel_gen6_edp_signal_levels(uint8_t train_set)
1778 {
1779 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1780 DP_TRAIN_PRE_EMPHASIS_MASK);
1781 switch (signal_levels) {
1782 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1783 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1784 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1785 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1786 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1787 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1788 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1789 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1790 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1791 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1792 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1793 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1794 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1795 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1796 default:
1797 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1798 "0x%x\n", signal_levels);
1799 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1800 }
1801 }
1802
1803 /* Gen7's DP voltage swing and pre-emphasis control */
1804 static uint32_t
1805 intel_gen7_edp_signal_levels(uint8_t train_set)
1806 {
1807 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1808 DP_TRAIN_PRE_EMPHASIS_MASK);
1809 switch (signal_levels) {
1810 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1811 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1812 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1813 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1814 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1815 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1816
1817 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1818 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1819 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1820 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1821
1822 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1823 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1824 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1825 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1826
1827 default:
1828 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1829 "0x%x\n", signal_levels);
1830 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1831 }
1832 }
1833
1834 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1835 static uint32_t
1836 intel_hsw_signal_levels(uint8_t train_set)
1837 {
1838 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1839 DP_TRAIN_PRE_EMPHASIS_MASK);
1840 switch (signal_levels) {
1841 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1842 return DDI_BUF_EMP_400MV_0DB_HSW;
1843 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1844 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1845 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1846 return DDI_BUF_EMP_400MV_6DB_HSW;
1847 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1848 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1849
1850 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1851 return DDI_BUF_EMP_600MV_0DB_HSW;
1852 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1853 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1854 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1855 return DDI_BUF_EMP_600MV_6DB_HSW;
1856
1857 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1858 return DDI_BUF_EMP_800MV_0DB_HSW;
1859 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1860 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1861 default:
1862 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1863 "0x%x\n", signal_levels);
1864 return DDI_BUF_EMP_400MV_0DB_HSW;
1865 }
1866 }
1867
1868 /* Properly updates "DP" with the correct signal levels. */
1869 static void
1870 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1871 {
1872 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1873 enum port port = intel_dig_port->port;
1874 struct drm_device *dev = intel_dig_port->base.base.dev;
1875 uint32_t signal_levels, mask;
1876 uint8_t train_set = intel_dp->train_set[0];
1877
1878 if (HAS_DDI(dev)) {
1879 signal_levels = intel_hsw_signal_levels(train_set);
1880 mask = DDI_BUF_EMP_MASK;
1881 } else if (IS_VALLEYVIEW(dev)) {
1882 signal_levels = intel_vlv_signal_levels(intel_dp);
1883 mask = 0;
1884 } else if (IS_GEN7(dev) && port == PORT_A) {
1885 signal_levels = intel_gen7_edp_signal_levels(train_set);
1886 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1887 } else if (IS_GEN6(dev) && port == PORT_A) {
1888 signal_levels = intel_gen6_edp_signal_levels(train_set);
1889 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1890 } else {
1891 signal_levels = intel_gen4_signal_levels(train_set);
1892 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1893 }
1894
1895 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1896
1897 *DP = (*DP & ~mask) | signal_levels;
1898 }
1899
1900 static bool
1901 intel_dp_set_link_train(struct intel_dp *intel_dp,
1902 uint32_t dp_reg_value,
1903 uint8_t dp_train_pat)
1904 {
1905 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1906 struct drm_device *dev = intel_dig_port->base.base.dev;
1907 struct drm_i915_private *dev_priv = dev->dev_private;
1908 enum port port = intel_dig_port->port;
1909 int ret;
1910
1911 if (HAS_DDI(dev)) {
1912 uint32_t temp = I915_READ(DP_TP_CTL(port));
1913
1914 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1915 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1916 else
1917 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1918
1919 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1920 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1921 case DP_TRAINING_PATTERN_DISABLE:
1922 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1923
1924 break;
1925 case DP_TRAINING_PATTERN_1:
1926 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1927 break;
1928 case DP_TRAINING_PATTERN_2:
1929 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1930 break;
1931 case DP_TRAINING_PATTERN_3:
1932 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1933 break;
1934 }
1935 I915_WRITE(DP_TP_CTL(port), temp);
1936
1937 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
1938 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1939
1940 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1941 case DP_TRAINING_PATTERN_DISABLE:
1942 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1943 break;
1944 case DP_TRAINING_PATTERN_1:
1945 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1946 break;
1947 case DP_TRAINING_PATTERN_2:
1948 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1949 break;
1950 case DP_TRAINING_PATTERN_3:
1951 DRM_ERROR("DP training pattern 3 not supported\n");
1952 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1953 break;
1954 }
1955
1956 } else {
1957 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1958
1959 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1960 case DP_TRAINING_PATTERN_DISABLE:
1961 dp_reg_value |= DP_LINK_TRAIN_OFF;
1962 break;
1963 case DP_TRAINING_PATTERN_1:
1964 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1965 break;
1966 case DP_TRAINING_PATTERN_2:
1967 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1968 break;
1969 case DP_TRAINING_PATTERN_3:
1970 DRM_ERROR("DP training pattern 3 not supported\n");
1971 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1972 break;
1973 }
1974 }
1975
1976 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1977 POSTING_READ(intel_dp->output_reg);
1978
1979 intel_dp_aux_native_write_1(intel_dp,
1980 DP_TRAINING_PATTERN_SET,
1981 dp_train_pat);
1982
1983 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1984 DP_TRAINING_PATTERN_DISABLE) {
1985 ret = intel_dp_aux_native_write(intel_dp,
1986 DP_TRAINING_LANE0_SET,
1987 intel_dp->train_set,
1988 intel_dp->lane_count);
1989 if (ret != intel_dp->lane_count)
1990 return false;
1991 }
1992
1993 return true;
1994 }
1995
1996 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1997 {
1998 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1999 struct drm_device *dev = intel_dig_port->base.base.dev;
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 enum port port = intel_dig_port->port;
2002 uint32_t val;
2003
2004 if (!HAS_DDI(dev))
2005 return;
2006
2007 val = I915_READ(DP_TP_CTL(port));
2008 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2009 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2010 I915_WRITE(DP_TP_CTL(port), val);
2011
2012 /*
2013 * On PORT_A we can have only eDP in SST mode. There the only reason
2014 * we need to set idle transmission mode is to work around a HW issue
2015 * where we enable the pipe while not in idle link-training mode.
2016 * In this case there is requirement to wait for a minimum number of
2017 * idle patterns to be sent.
2018 */
2019 if (port == PORT_A)
2020 return;
2021
2022 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2023 1))
2024 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2025 }
2026
2027 /* Enable corresponding port and start training pattern 1 */
2028 void
2029 intel_dp_start_link_train(struct intel_dp *intel_dp)
2030 {
2031 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2032 struct drm_device *dev = encoder->dev;
2033 int i;
2034 uint8_t voltage;
2035 bool clock_recovery = false;
2036 int voltage_tries, loop_tries;
2037 uint32_t DP = intel_dp->DP;
2038
2039 if (HAS_DDI(dev))
2040 intel_ddi_prepare_link_retrain(encoder);
2041
2042 /* Write the link configuration data */
2043 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2044 intel_dp->link_configuration,
2045 DP_LINK_CONFIGURATION_SIZE);
2046
2047 DP |= DP_PORT_EN;
2048
2049 memset(intel_dp->train_set, 0, 4);
2050 voltage = 0xff;
2051 voltage_tries = 0;
2052 loop_tries = 0;
2053 clock_recovery = false;
2054 for (;;) {
2055 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2056 uint8_t link_status[DP_LINK_STATUS_SIZE];
2057
2058 intel_dp_set_signal_levels(intel_dp, &DP);
2059
2060 /* Set training pattern 1 */
2061 if (!intel_dp_set_link_train(intel_dp, DP,
2062 DP_TRAINING_PATTERN_1 |
2063 DP_LINK_SCRAMBLING_DISABLE))
2064 break;
2065
2066 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2067 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2068 DRM_ERROR("failed to get link status\n");
2069 break;
2070 }
2071
2072 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2073 DRM_DEBUG_KMS("clock recovery OK\n");
2074 clock_recovery = true;
2075 break;
2076 }
2077
2078 /* Check to see if we've tried the max voltage */
2079 for (i = 0; i < intel_dp->lane_count; i++)
2080 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2081 break;
2082 if (i == intel_dp->lane_count) {
2083 ++loop_tries;
2084 if (loop_tries == 5) {
2085 DRM_DEBUG_KMS("too many full retries, give up\n");
2086 break;
2087 }
2088 memset(intel_dp->train_set, 0, 4);
2089 voltage_tries = 0;
2090 continue;
2091 }
2092
2093 /* Check to see if we've tried the same voltage 5 times */
2094 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2095 ++voltage_tries;
2096 if (voltage_tries == 5) {
2097 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2098 break;
2099 }
2100 } else
2101 voltage_tries = 0;
2102 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2103
2104 /* Compute new intel_dp->train_set as requested by target */
2105 intel_get_adjust_train(intel_dp, link_status);
2106 }
2107
2108 intel_dp->DP = DP;
2109 }
2110
2111 void
2112 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2113 {
2114 bool channel_eq = false;
2115 int tries, cr_tries;
2116 uint32_t DP = intel_dp->DP;
2117
2118 /* channel equalization */
2119 tries = 0;
2120 cr_tries = 0;
2121 channel_eq = false;
2122 for (;;) {
2123 uint8_t link_status[DP_LINK_STATUS_SIZE];
2124
2125 if (cr_tries > 5) {
2126 DRM_ERROR("failed to train DP, aborting\n");
2127 intel_dp_link_down(intel_dp);
2128 break;
2129 }
2130
2131 intel_dp_set_signal_levels(intel_dp, &DP);
2132
2133 /* channel eq pattern */
2134 if (!intel_dp_set_link_train(intel_dp, DP,
2135 DP_TRAINING_PATTERN_2 |
2136 DP_LINK_SCRAMBLING_DISABLE))
2137 break;
2138
2139 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2140 if (!intel_dp_get_link_status(intel_dp, link_status))
2141 break;
2142
2143 /* Make sure clock is still ok */
2144 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2145 intel_dp_start_link_train(intel_dp);
2146 cr_tries++;
2147 continue;
2148 }
2149
2150 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2151 channel_eq = true;
2152 break;
2153 }
2154
2155 /* Try 5 times, then try clock recovery if that fails */
2156 if (tries > 5) {
2157 intel_dp_link_down(intel_dp);
2158 intel_dp_start_link_train(intel_dp);
2159 tries = 0;
2160 cr_tries++;
2161 continue;
2162 }
2163
2164 /* Compute new intel_dp->train_set as requested by target */
2165 intel_get_adjust_train(intel_dp, link_status);
2166 ++tries;
2167 }
2168
2169 intel_dp_set_idle_link_train(intel_dp);
2170
2171 intel_dp->DP = DP;
2172
2173 if (channel_eq)
2174 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2175
2176 }
2177
2178 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2179 {
2180 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2181 DP_TRAINING_PATTERN_DISABLE);
2182 }
2183
2184 static void
2185 intel_dp_link_down(struct intel_dp *intel_dp)
2186 {
2187 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2188 enum port port = intel_dig_port->port;
2189 struct drm_device *dev = intel_dig_port->base.base.dev;
2190 struct drm_i915_private *dev_priv = dev->dev_private;
2191 struct intel_crtc *intel_crtc =
2192 to_intel_crtc(intel_dig_port->base.base.crtc);
2193 uint32_t DP = intel_dp->DP;
2194
2195 /*
2196 * DDI code has a strict mode set sequence and we should try to respect
2197 * it, otherwise we might hang the machine in many different ways. So we
2198 * really should be disabling the port only on a complete crtc_disable
2199 * sequence. This function is just called under two conditions on DDI
2200 * code:
2201 * - Link train failed while doing crtc_enable, and on this case we
2202 * really should respect the mode set sequence and wait for a
2203 * crtc_disable.
2204 * - Someone turned the monitor off and intel_dp_check_link_status
2205 * called us. We don't need to disable the whole port on this case, so
2206 * when someone turns the monitor on again,
2207 * intel_ddi_prepare_link_retrain will take care of redoing the link
2208 * train.
2209 */
2210 if (HAS_DDI(dev))
2211 return;
2212
2213 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2214 return;
2215
2216 DRM_DEBUG_KMS("\n");
2217
2218 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2219 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2220 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2221 } else {
2222 DP &= ~DP_LINK_TRAIN_MASK;
2223 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2224 }
2225 POSTING_READ(intel_dp->output_reg);
2226
2227 /* We don't really know why we're doing this */
2228 intel_wait_for_vblank(dev, intel_crtc->pipe);
2229
2230 if (HAS_PCH_IBX(dev) &&
2231 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2232 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2233
2234 /* Hardware workaround: leaving our transcoder select
2235 * set to transcoder B while it's off will prevent the
2236 * corresponding HDMI output on transcoder A.
2237 *
2238 * Combine this with another hardware workaround:
2239 * transcoder select bit can only be cleared while the
2240 * port is enabled.
2241 */
2242 DP &= ~DP_PIPEB_SELECT;
2243 I915_WRITE(intel_dp->output_reg, DP);
2244
2245 /* Changes to enable or select take place the vblank
2246 * after being written.
2247 */
2248 if (WARN_ON(crtc == NULL)) {
2249 /* We should never try to disable a port without a crtc
2250 * attached. For paranoia keep the code around for a
2251 * bit. */
2252 POSTING_READ(intel_dp->output_reg);
2253 msleep(50);
2254 } else
2255 intel_wait_for_vblank(dev, intel_crtc->pipe);
2256 }
2257
2258 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2259 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2260 POSTING_READ(intel_dp->output_reg);
2261 msleep(intel_dp->panel_power_down_delay);
2262 }
2263
2264 static bool
2265 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2266 {
2267 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2268
2269 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2270 sizeof(intel_dp->dpcd)) == 0)
2271 return false; /* aux transfer failed */
2272
2273 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2274 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2275 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2276
2277 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2278 return false; /* DPCD not present */
2279
2280 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2281 DP_DWN_STRM_PORT_PRESENT))
2282 return true; /* native DP sink */
2283
2284 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2285 return true; /* no per-port downstream info */
2286
2287 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2288 intel_dp->downstream_ports,
2289 DP_MAX_DOWNSTREAM_PORTS) == 0)
2290 return false; /* downstream port status fetch failed */
2291
2292 return true;
2293 }
2294
2295 static void
2296 intel_dp_probe_oui(struct intel_dp *intel_dp)
2297 {
2298 u8 buf[3];
2299
2300 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2301 return;
2302
2303 ironlake_edp_panel_vdd_on(intel_dp);
2304
2305 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2306 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2307 buf[0], buf[1], buf[2]);
2308
2309 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2310 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2311 buf[0], buf[1], buf[2]);
2312
2313 ironlake_edp_panel_vdd_off(intel_dp, false);
2314 }
2315
2316 static bool
2317 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2318 {
2319 int ret;
2320
2321 ret = intel_dp_aux_native_read_retry(intel_dp,
2322 DP_DEVICE_SERVICE_IRQ_VECTOR,
2323 sink_irq_vector, 1);
2324 if (!ret)
2325 return false;
2326
2327 return true;
2328 }
2329
2330 static void
2331 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2332 {
2333 /* NAK by default */
2334 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2335 }
2336
2337 /*
2338 * According to DP spec
2339 * 5.1.2:
2340 * 1. Read DPCD
2341 * 2. Configure link according to Receiver Capabilities
2342 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2343 * 4. Check link status on receipt of hot-plug interrupt
2344 */
2345
2346 void
2347 intel_dp_check_link_status(struct intel_dp *intel_dp)
2348 {
2349 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2350 u8 sink_irq_vector;
2351 u8 link_status[DP_LINK_STATUS_SIZE];
2352
2353 if (!intel_encoder->connectors_active)
2354 return;
2355
2356 if (WARN_ON(!intel_encoder->base.crtc))
2357 return;
2358
2359 /* Try to read receiver status if the link appears to be up */
2360 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2361 intel_dp_link_down(intel_dp);
2362 return;
2363 }
2364
2365 /* Now read the DPCD to see if it's actually running */
2366 if (!intel_dp_get_dpcd(intel_dp)) {
2367 intel_dp_link_down(intel_dp);
2368 return;
2369 }
2370
2371 /* Try to read the source of the interrupt */
2372 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2373 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2374 /* Clear interrupt source */
2375 intel_dp_aux_native_write_1(intel_dp,
2376 DP_DEVICE_SERVICE_IRQ_VECTOR,
2377 sink_irq_vector);
2378
2379 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2380 intel_dp_handle_test_request(intel_dp);
2381 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2382 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2383 }
2384
2385 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2386 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2387 drm_get_encoder_name(&intel_encoder->base));
2388 intel_dp_start_link_train(intel_dp);
2389 intel_dp_complete_link_train(intel_dp);
2390 intel_dp_stop_link_train(intel_dp);
2391 }
2392 }
2393
2394 /* XXX this is probably wrong for multiple downstream ports */
2395 static enum drm_connector_status
2396 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2397 {
2398 uint8_t *dpcd = intel_dp->dpcd;
2399 bool hpd;
2400 uint8_t type;
2401
2402 if (!intel_dp_get_dpcd(intel_dp))
2403 return connector_status_disconnected;
2404
2405 /* if there's no downstream port, we're done */
2406 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2407 return connector_status_connected;
2408
2409 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2410 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2411 if (hpd) {
2412 uint8_t reg;
2413 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2414 &reg, 1))
2415 return connector_status_unknown;
2416 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2417 : connector_status_disconnected;
2418 }
2419
2420 /* If no HPD, poke DDC gently */
2421 if (drm_probe_ddc(&intel_dp->adapter))
2422 return connector_status_connected;
2423
2424 /* Well we tried, say unknown for unreliable port types */
2425 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2426 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2427 return connector_status_unknown;
2428
2429 /* Anything else is out of spec, warn and ignore */
2430 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2431 return connector_status_disconnected;
2432 }
2433
2434 static enum drm_connector_status
2435 ironlake_dp_detect(struct intel_dp *intel_dp)
2436 {
2437 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2438 struct drm_i915_private *dev_priv = dev->dev_private;
2439 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2440 enum drm_connector_status status;
2441
2442 /* Can't disconnect eDP, but you can close the lid... */
2443 if (is_edp(intel_dp)) {
2444 status = intel_panel_detect(dev);
2445 if (status == connector_status_unknown)
2446 status = connector_status_connected;
2447 return status;
2448 }
2449
2450 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2451 return connector_status_disconnected;
2452
2453 return intel_dp_detect_dpcd(intel_dp);
2454 }
2455
2456 static enum drm_connector_status
2457 g4x_dp_detect(struct intel_dp *intel_dp)
2458 {
2459 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2462 uint32_t bit;
2463
2464 /* Can't disconnect eDP, but you can close the lid... */
2465 if (is_edp(intel_dp)) {
2466 enum drm_connector_status status;
2467
2468 status = intel_panel_detect(dev);
2469 if (status == connector_status_unknown)
2470 status = connector_status_connected;
2471 return status;
2472 }
2473
2474 switch (intel_dig_port->port) {
2475 case PORT_B:
2476 bit = PORTB_HOTPLUG_LIVE_STATUS;
2477 break;
2478 case PORT_C:
2479 bit = PORTC_HOTPLUG_LIVE_STATUS;
2480 break;
2481 case PORT_D:
2482 bit = PORTD_HOTPLUG_LIVE_STATUS;
2483 break;
2484 default:
2485 return connector_status_unknown;
2486 }
2487
2488 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2489 return connector_status_disconnected;
2490
2491 return intel_dp_detect_dpcd(intel_dp);
2492 }
2493
2494 static struct edid *
2495 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2496 {
2497 struct intel_connector *intel_connector = to_intel_connector(connector);
2498
2499 /* use cached edid if we have one */
2500 if (intel_connector->edid) {
2501 struct edid *edid;
2502 int size;
2503
2504 /* invalid edid */
2505 if (IS_ERR(intel_connector->edid))
2506 return NULL;
2507
2508 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2509 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2510 if (!edid)
2511 return NULL;
2512
2513 return edid;
2514 }
2515
2516 return drm_get_edid(connector, adapter);
2517 }
2518
2519 static int
2520 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2521 {
2522 struct intel_connector *intel_connector = to_intel_connector(connector);
2523
2524 /* use cached edid if we have one */
2525 if (intel_connector->edid) {
2526 /* invalid edid */
2527 if (IS_ERR(intel_connector->edid))
2528 return 0;
2529
2530 return intel_connector_update_modes(connector,
2531 intel_connector->edid);
2532 }
2533
2534 return intel_ddc_get_modes(connector, adapter);
2535 }
2536
2537 static enum drm_connector_status
2538 intel_dp_detect(struct drm_connector *connector, bool force)
2539 {
2540 struct intel_dp *intel_dp = intel_attached_dp(connector);
2541 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2542 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2543 struct drm_device *dev = connector->dev;
2544 enum drm_connector_status status;
2545 struct edid *edid = NULL;
2546
2547 intel_dp->has_audio = false;
2548
2549 if (HAS_PCH_SPLIT(dev))
2550 status = ironlake_dp_detect(intel_dp);
2551 else
2552 status = g4x_dp_detect(intel_dp);
2553
2554 if (status != connector_status_connected)
2555 return status;
2556
2557 intel_dp_probe_oui(intel_dp);
2558
2559 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2560 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2561 } else {
2562 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2563 if (edid) {
2564 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2565 kfree(edid);
2566 }
2567 }
2568
2569 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2570 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2571 return connector_status_connected;
2572 }
2573
2574 static int intel_dp_get_modes(struct drm_connector *connector)
2575 {
2576 struct intel_dp *intel_dp = intel_attached_dp(connector);
2577 struct intel_connector *intel_connector = to_intel_connector(connector);
2578 struct drm_device *dev = connector->dev;
2579 int ret;
2580
2581 /* We should parse the EDID data and find out if it has an audio sink
2582 */
2583
2584 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2585 if (ret)
2586 return ret;
2587
2588 /* if eDP has no EDID, fall back to fixed mode */
2589 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2590 struct drm_display_mode *mode;
2591 mode = drm_mode_duplicate(dev,
2592 intel_connector->panel.fixed_mode);
2593 if (mode) {
2594 drm_mode_probed_add(connector, mode);
2595 return 1;
2596 }
2597 }
2598 return 0;
2599 }
2600
2601 static bool
2602 intel_dp_detect_audio(struct drm_connector *connector)
2603 {
2604 struct intel_dp *intel_dp = intel_attached_dp(connector);
2605 struct edid *edid;
2606 bool has_audio = false;
2607
2608 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2609 if (edid) {
2610 has_audio = drm_detect_monitor_audio(edid);
2611 kfree(edid);
2612 }
2613
2614 return has_audio;
2615 }
2616
2617 static int
2618 intel_dp_set_property(struct drm_connector *connector,
2619 struct drm_property *property,
2620 uint64_t val)
2621 {
2622 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2623 struct intel_connector *intel_connector = to_intel_connector(connector);
2624 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2625 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2626 int ret;
2627
2628 ret = drm_object_property_set_value(&connector->base, property, val);
2629 if (ret)
2630 return ret;
2631
2632 if (property == dev_priv->force_audio_property) {
2633 int i = val;
2634 bool has_audio;
2635
2636 if (i == intel_dp->force_audio)
2637 return 0;
2638
2639 intel_dp->force_audio = i;
2640
2641 if (i == HDMI_AUDIO_AUTO)
2642 has_audio = intel_dp_detect_audio(connector);
2643 else
2644 has_audio = (i == HDMI_AUDIO_ON);
2645
2646 if (has_audio == intel_dp->has_audio)
2647 return 0;
2648
2649 intel_dp->has_audio = has_audio;
2650 goto done;
2651 }
2652
2653 if (property == dev_priv->broadcast_rgb_property) {
2654 bool old_auto = intel_dp->color_range_auto;
2655 uint32_t old_range = intel_dp->color_range;
2656
2657 switch (val) {
2658 case INTEL_BROADCAST_RGB_AUTO:
2659 intel_dp->color_range_auto = true;
2660 break;
2661 case INTEL_BROADCAST_RGB_FULL:
2662 intel_dp->color_range_auto = false;
2663 intel_dp->color_range = 0;
2664 break;
2665 case INTEL_BROADCAST_RGB_LIMITED:
2666 intel_dp->color_range_auto = false;
2667 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2668 break;
2669 default:
2670 return -EINVAL;
2671 }
2672
2673 if (old_auto == intel_dp->color_range_auto &&
2674 old_range == intel_dp->color_range)
2675 return 0;
2676
2677 goto done;
2678 }
2679
2680 if (is_edp(intel_dp) &&
2681 property == connector->dev->mode_config.scaling_mode_property) {
2682 if (val == DRM_MODE_SCALE_NONE) {
2683 DRM_DEBUG_KMS("no scaling not supported\n");
2684 return -EINVAL;
2685 }
2686
2687 if (intel_connector->panel.fitting_mode == val) {
2688 /* the eDP scaling property is not changed */
2689 return 0;
2690 }
2691 intel_connector->panel.fitting_mode = val;
2692
2693 goto done;
2694 }
2695
2696 return -EINVAL;
2697
2698 done:
2699 if (intel_encoder->base.crtc)
2700 intel_crtc_restore_mode(intel_encoder->base.crtc);
2701
2702 return 0;
2703 }
2704
2705 static void
2706 intel_dp_connector_destroy(struct drm_connector *connector)
2707 {
2708 struct intel_connector *intel_connector = to_intel_connector(connector);
2709
2710 if (!IS_ERR_OR_NULL(intel_connector->edid))
2711 kfree(intel_connector->edid);
2712
2713 /* Can't call is_edp() since the encoder may have been destroyed
2714 * already. */
2715 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2716 intel_panel_fini(&intel_connector->panel);
2717
2718 drm_sysfs_connector_remove(connector);
2719 drm_connector_cleanup(connector);
2720 kfree(connector);
2721 }
2722
2723 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2724 {
2725 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2726 struct intel_dp *intel_dp = &intel_dig_port->dp;
2727 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2728
2729 i2c_del_adapter(&intel_dp->adapter);
2730 drm_encoder_cleanup(encoder);
2731 if (is_edp(intel_dp)) {
2732 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2733 mutex_lock(&dev->mode_config.mutex);
2734 ironlake_panel_vdd_off_sync(intel_dp);
2735 mutex_unlock(&dev->mode_config.mutex);
2736 }
2737 kfree(intel_dig_port);
2738 }
2739
2740 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2741 .mode_set = intel_dp_mode_set,
2742 };
2743
2744 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2745 .dpms = intel_connector_dpms,
2746 .detect = intel_dp_detect,
2747 .fill_modes = drm_helper_probe_single_connector_modes,
2748 .set_property = intel_dp_set_property,
2749 .destroy = intel_dp_connector_destroy,
2750 };
2751
2752 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2753 .get_modes = intel_dp_get_modes,
2754 .mode_valid = intel_dp_mode_valid,
2755 .best_encoder = intel_best_encoder,
2756 };
2757
2758 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2759 .destroy = intel_dp_encoder_destroy,
2760 };
2761
2762 static void
2763 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2764 {
2765 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2766
2767 intel_dp_check_link_status(intel_dp);
2768 }
2769
2770 /* Return which DP Port should be selected for Transcoder DP control */
2771 int
2772 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2773 {
2774 struct drm_device *dev = crtc->dev;
2775 struct intel_encoder *intel_encoder;
2776 struct intel_dp *intel_dp;
2777
2778 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2779 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2780
2781 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2782 intel_encoder->type == INTEL_OUTPUT_EDP)
2783 return intel_dp->output_reg;
2784 }
2785
2786 return -1;
2787 }
2788
2789 /* check the VBT to see whether the eDP is on DP-D port */
2790 bool intel_dpd_is_edp(struct drm_device *dev)
2791 {
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 struct child_device_config *p_child;
2794 int i;
2795
2796 if (!dev_priv->vbt.child_dev_num)
2797 return false;
2798
2799 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2800 p_child = dev_priv->vbt.child_dev + i;
2801
2802 if (p_child->dvo_port == PORT_IDPD &&
2803 p_child->device_type == DEVICE_TYPE_eDP)
2804 return true;
2805 }
2806 return false;
2807 }
2808
2809 static void
2810 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2811 {
2812 struct intel_connector *intel_connector = to_intel_connector(connector);
2813
2814 intel_attach_force_audio_property(connector);
2815 intel_attach_broadcast_rgb_property(connector);
2816 intel_dp->color_range_auto = true;
2817
2818 if (is_edp(intel_dp)) {
2819 drm_mode_create_scaling_mode_property(connector->dev);
2820 drm_object_attach_property(
2821 &connector->base,
2822 connector->dev->mode_config.scaling_mode_property,
2823 DRM_MODE_SCALE_ASPECT);
2824 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2825 }
2826 }
2827
2828 static void
2829 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2830 struct intel_dp *intel_dp,
2831 struct edp_power_seq *out)
2832 {
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834 struct edp_power_seq cur, vbt, spec, final;
2835 u32 pp_on, pp_off, pp_div, pp;
2836 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2837
2838 if (HAS_PCH_SPLIT(dev)) {
2839 pp_control_reg = PCH_PP_CONTROL;
2840 pp_on_reg = PCH_PP_ON_DELAYS;
2841 pp_off_reg = PCH_PP_OFF_DELAYS;
2842 pp_div_reg = PCH_PP_DIVISOR;
2843 } else {
2844 pp_control_reg = PIPEA_PP_CONTROL;
2845 pp_on_reg = PIPEA_PP_ON_DELAYS;
2846 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2847 pp_div_reg = PIPEA_PP_DIVISOR;
2848 }
2849
2850 /* Workaround: Need to write PP_CONTROL with the unlock key as
2851 * the very first thing. */
2852 pp = ironlake_get_pp_control(intel_dp);
2853 I915_WRITE(pp_control_reg, pp);
2854
2855 pp_on = I915_READ(pp_on_reg);
2856 pp_off = I915_READ(pp_off_reg);
2857 pp_div = I915_READ(pp_div_reg);
2858
2859 /* Pull timing values out of registers */
2860 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2861 PANEL_POWER_UP_DELAY_SHIFT;
2862
2863 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2864 PANEL_LIGHT_ON_DELAY_SHIFT;
2865
2866 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2867 PANEL_LIGHT_OFF_DELAY_SHIFT;
2868
2869 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2870 PANEL_POWER_DOWN_DELAY_SHIFT;
2871
2872 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2873 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2874
2875 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2876 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2877
2878 vbt = dev_priv->vbt.edp_pps;
2879
2880 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2881 * our hw here, which are all in 100usec. */
2882 spec.t1_t3 = 210 * 10;
2883 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2884 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2885 spec.t10 = 500 * 10;
2886 /* This one is special and actually in units of 100ms, but zero
2887 * based in the hw (so we need to add 100 ms). But the sw vbt
2888 * table multiplies it with 1000 to make it in units of 100usec,
2889 * too. */
2890 spec.t11_t12 = (510 + 100) * 10;
2891
2892 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2893 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2894
2895 /* Use the max of the register settings and vbt. If both are
2896 * unset, fall back to the spec limits. */
2897 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2898 spec.field : \
2899 max(cur.field, vbt.field))
2900 assign_final(t1_t3);
2901 assign_final(t8);
2902 assign_final(t9);
2903 assign_final(t10);
2904 assign_final(t11_t12);
2905 #undef assign_final
2906
2907 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2908 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2909 intel_dp->backlight_on_delay = get_delay(t8);
2910 intel_dp->backlight_off_delay = get_delay(t9);
2911 intel_dp->panel_power_down_delay = get_delay(t10);
2912 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2913 #undef get_delay
2914
2915 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2916 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2917 intel_dp->panel_power_cycle_delay);
2918
2919 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2920 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2921
2922 if (out)
2923 *out = final;
2924 }
2925
2926 static void
2927 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2928 struct intel_dp *intel_dp,
2929 struct edp_power_seq *seq)
2930 {
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 u32 pp_on, pp_off, pp_div, port_sel = 0;
2933 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2934 int pp_on_reg, pp_off_reg, pp_div_reg;
2935
2936 if (HAS_PCH_SPLIT(dev)) {
2937 pp_on_reg = PCH_PP_ON_DELAYS;
2938 pp_off_reg = PCH_PP_OFF_DELAYS;
2939 pp_div_reg = PCH_PP_DIVISOR;
2940 } else {
2941 pp_on_reg = PIPEA_PP_ON_DELAYS;
2942 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2943 pp_div_reg = PIPEA_PP_DIVISOR;
2944 }
2945
2946 /* And finally store the new values in the power sequencer. */
2947 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2948 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2949 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2950 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2951 /* Compute the divisor for the pp clock, simply match the Bspec
2952 * formula. */
2953 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2954 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2955 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2956
2957 /* Haswell doesn't have any port selection bits for the panel
2958 * power sequencer any more. */
2959 if (IS_VALLEYVIEW(dev)) {
2960 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2961 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2962 if (dp_to_dig_port(intel_dp)->port == PORT_A)
2963 port_sel = PANEL_POWER_PORT_DP_A;
2964 else
2965 port_sel = PANEL_POWER_PORT_DP_D;
2966 }
2967
2968 pp_on |= port_sel;
2969
2970 I915_WRITE(pp_on_reg, pp_on);
2971 I915_WRITE(pp_off_reg, pp_off);
2972 I915_WRITE(pp_div_reg, pp_div);
2973
2974 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2975 I915_READ(pp_on_reg),
2976 I915_READ(pp_off_reg),
2977 I915_READ(pp_div_reg));
2978 }
2979
2980 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
2981 struct intel_connector *intel_connector)
2982 {
2983 struct drm_connector *connector = &intel_connector->base;
2984 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2985 struct drm_device *dev = intel_dig_port->base.base.dev;
2986 struct drm_i915_private *dev_priv = dev->dev_private;
2987 struct drm_display_mode *fixed_mode = NULL;
2988 struct edp_power_seq power_seq = { 0 };
2989 bool has_dpcd;
2990 struct drm_display_mode *scan;
2991 struct edid *edid;
2992
2993 if (!is_edp(intel_dp))
2994 return true;
2995
2996 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2997
2998 /* Cache DPCD and EDID for edp. */
2999 ironlake_edp_panel_vdd_on(intel_dp);
3000 has_dpcd = intel_dp_get_dpcd(intel_dp);
3001 ironlake_edp_panel_vdd_off(intel_dp, false);
3002
3003 if (has_dpcd) {
3004 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3005 dev_priv->no_aux_handshake =
3006 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3007 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3008 } else {
3009 /* if this fails, presume the device is a ghost */
3010 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3011 return false;
3012 }
3013
3014 /* We now know it's not a ghost, init power sequence regs. */
3015 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3016 &power_seq);
3017
3018 ironlake_edp_panel_vdd_on(intel_dp);
3019 edid = drm_get_edid(connector, &intel_dp->adapter);
3020 if (edid) {
3021 if (drm_add_edid_modes(connector, edid)) {
3022 drm_mode_connector_update_edid_property(connector,
3023 edid);
3024 drm_edid_to_eld(connector, edid);
3025 } else {
3026 kfree(edid);
3027 edid = ERR_PTR(-EINVAL);
3028 }
3029 } else {
3030 edid = ERR_PTR(-ENOENT);
3031 }
3032 intel_connector->edid = edid;
3033
3034 /* prefer fixed mode from EDID if available */
3035 list_for_each_entry(scan, &connector->probed_modes, head) {
3036 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3037 fixed_mode = drm_mode_duplicate(dev, scan);
3038 break;
3039 }
3040 }
3041
3042 /* fallback to VBT if available for eDP */
3043 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3044 fixed_mode = drm_mode_duplicate(dev,
3045 dev_priv->vbt.lfp_lvds_vbt_mode);
3046 if (fixed_mode)
3047 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3048 }
3049
3050 ironlake_edp_panel_vdd_off(intel_dp, false);
3051
3052 intel_panel_init(&intel_connector->panel, fixed_mode);
3053 intel_panel_setup_backlight(connector);
3054
3055 return true;
3056 }
3057
3058 bool
3059 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3060 struct intel_connector *intel_connector)
3061 {
3062 struct drm_connector *connector = &intel_connector->base;
3063 struct intel_dp *intel_dp = &intel_dig_port->dp;
3064 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3065 struct drm_device *dev = intel_encoder->base.dev;
3066 struct drm_i915_private *dev_priv = dev->dev_private;
3067 enum port port = intel_dig_port->port;
3068 const char *name = NULL;
3069 int type, error;
3070
3071 /* Preserve the current hw state. */
3072 intel_dp->DP = I915_READ(intel_dp->output_reg);
3073 intel_dp->attached_connector = intel_connector;
3074
3075 type = DRM_MODE_CONNECTOR_DisplayPort;
3076 /*
3077 * FIXME : We need to initialize built-in panels before external panels.
3078 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3079 */
3080 switch (port) {
3081 case PORT_A:
3082 type = DRM_MODE_CONNECTOR_eDP;
3083 break;
3084 case PORT_C:
3085 if (IS_VALLEYVIEW(dev))
3086 type = DRM_MODE_CONNECTOR_eDP;
3087 break;
3088 case PORT_D:
3089 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3090 type = DRM_MODE_CONNECTOR_eDP;
3091 break;
3092 default: /* silence GCC warning */
3093 break;
3094 }
3095
3096 /*
3097 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3098 * for DP the encoder type can be set by the caller to
3099 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3100 */
3101 if (type == DRM_MODE_CONNECTOR_eDP)
3102 intel_encoder->type = INTEL_OUTPUT_EDP;
3103
3104 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3105 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3106 port_name(port));
3107
3108 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3109 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3110
3111 connector->interlace_allowed = true;
3112 connector->doublescan_allowed = 0;
3113
3114 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3115 ironlake_panel_vdd_work);
3116
3117 intel_connector_attach_encoder(intel_connector, intel_encoder);
3118 drm_sysfs_connector_add(connector);
3119
3120 if (HAS_DDI(dev))
3121 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3122 else
3123 intel_connector->get_hw_state = intel_connector_get_hw_state;
3124
3125 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3126 if (HAS_DDI(dev)) {
3127 switch (intel_dig_port->port) {
3128 case PORT_A:
3129 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3130 break;
3131 case PORT_B:
3132 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3133 break;
3134 case PORT_C:
3135 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3136 break;
3137 case PORT_D:
3138 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3139 break;
3140 default:
3141 BUG();
3142 }
3143 }
3144
3145 /* Set up the DDC bus. */
3146 switch (port) {
3147 case PORT_A:
3148 intel_encoder->hpd_pin = HPD_PORT_A;
3149 name = "DPDDC-A";
3150 break;
3151 case PORT_B:
3152 intel_encoder->hpd_pin = HPD_PORT_B;
3153 name = "DPDDC-B";
3154 break;
3155 case PORT_C:
3156 intel_encoder->hpd_pin = HPD_PORT_C;
3157 name = "DPDDC-C";
3158 break;
3159 case PORT_D:
3160 intel_encoder->hpd_pin = HPD_PORT_D;
3161 name = "DPDDC-D";
3162 break;
3163 default:
3164 BUG();
3165 }
3166
3167 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3168 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3169 error, port_name(port));
3170
3171 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3172 i2c_del_adapter(&intel_dp->adapter);
3173 if (is_edp(intel_dp)) {
3174 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3175 mutex_lock(&dev->mode_config.mutex);
3176 ironlake_panel_vdd_off_sync(intel_dp);
3177 mutex_unlock(&dev->mode_config.mutex);
3178 }
3179 drm_sysfs_connector_remove(connector);
3180 drm_connector_cleanup(connector);
3181 return false;
3182 }
3183
3184 intel_dp_add_properties(intel_dp, connector);
3185
3186 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3187 * 0xd. Failure to do so will result in spurious interrupts being
3188 * generated on the port when a cable is not attached.
3189 */
3190 if (IS_G4X(dev) && !IS_GM45(dev)) {
3191 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3192 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3193 }
3194
3195 return true;
3196 }
3197
3198 void
3199 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3200 {
3201 struct intel_digital_port *intel_dig_port;
3202 struct intel_encoder *intel_encoder;
3203 struct drm_encoder *encoder;
3204 struct intel_connector *intel_connector;
3205
3206 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3207 if (!intel_dig_port)
3208 return;
3209
3210 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3211 if (!intel_connector) {
3212 kfree(intel_dig_port);
3213 return;
3214 }
3215
3216 intel_encoder = &intel_dig_port->base;
3217 encoder = &intel_encoder->base;
3218
3219 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3220 DRM_MODE_ENCODER_TMDS);
3221 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3222
3223 intel_encoder->compute_config = intel_dp_compute_config;
3224 intel_encoder->enable = intel_enable_dp;
3225 intel_encoder->pre_enable = intel_pre_enable_dp;
3226 intel_encoder->disable = intel_disable_dp;
3227 intel_encoder->post_disable = intel_post_disable_dp;
3228 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3229 intel_encoder->get_config = intel_dp_get_config;
3230 if (IS_VALLEYVIEW(dev))
3231 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3232
3233 intel_dig_port->port = port;
3234 intel_dig_port->dp.output_reg = output_reg;
3235
3236 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3237 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3238 intel_encoder->cloneable = false;
3239 intel_encoder->hot_plug = intel_dp_hot_plug;
3240
3241 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3242 drm_encoder_cleanup(encoder);
3243 kfree(intel_dig_port);
3244 kfree(intel_connector);
3245 }
3246 }
Linux kernel - Deliverables
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