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drm/i915: Rename edp vdd funcs for consistency
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46 };
47
48 static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 };
54
55 static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 };
61
62 static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67 };
68
69 /*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73 static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85 };
86
87 /**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94 static bool is_edp(struct intel_dp *intel_dp)
95 {
96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
99 }
100
101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
102 {
103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
106 }
107
108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109 {
110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
111 }
112
113 static void intel_dp_link_down(struct intel_dp *intel_dp);
114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
116
117 int
118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
119 {
120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
134 break;
135 default:
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142 }
143
144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145 {
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158 }
159
160 /*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
177 static int
178 intel_dp_link_required(int pixel_clock, int bpp)
179 {
180 return (pixel_clock * bpp + 9) / 10;
181 }
182
183 static int
184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185 {
186 return (max_link_clock * max_lanes * 8) / 10;
187 }
188
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192 {
193 struct intel_dp *intel_dp = intel_attached_dp(connector);
194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
198
199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
201 return MODE_PANEL;
202
203 if (mode->vdisplay > fixed_mode->vdisplay)
204 return MODE_PANEL;
205
206 target_clock = fixed_mode->clock;
207 }
208
209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
210 max_lanes = intel_dp_max_lane_count(intel_dp);
211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
216 return MODE_CLOCK_HIGH;
217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
224 return MODE_OK;
225 }
226
227 static uint32_t
228 pack_aux(uint8_t *src, int src_bytes)
229 {
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238 }
239
240 static void
241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242 {
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248 }
249
250 /* hrawclock is 1/4 the FSB frequency */
251 static int
252 intel_hrawclk(struct drm_device *dev)
253 {
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282 }
283
284 static void
285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288 static void
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293 static enum pipe
294 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295 {
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
311 if (port_sel == PANEL_PORT_SELECT_VLV(port))
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317 }
318
319 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320 {
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327 }
328
329 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330 {
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337 }
338
339 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
342 void *unused)
343 {
344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
345 edp_notifier);
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 u32 pp_div;
349 u32 pp_ctrl_reg, pp_div_reg;
350 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
351
352 if (!is_edp(intel_dp) || code != SYS_RESTART)
353 return 0;
354
355 if (IS_VALLEYVIEW(dev)) {
356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358 pp_div = I915_READ(pp_div_reg);
359 pp_div &= PP_REFERENCE_DIVIDER_MASK;
360
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg, pp_div | 0x1F);
363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364 msleep(intel_dp->panel_power_cycle_delay);
365 }
366
367 return 0;
368 }
369
370 static bool edp_have_panel_power(struct intel_dp *intel_dp)
371 {
372 struct drm_device *dev = intel_dp_to_dev(intel_dp);
373 struct drm_i915_private *dev_priv = dev->dev_private;
374
375 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
376 }
377
378 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
379 {
380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
381 struct drm_i915_private *dev_priv = dev->dev_private;
382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
383 struct intel_encoder *intel_encoder = &intel_dig_port->base;
384 enum intel_display_power_domain power_domain;
385
386 power_domain = intel_display_port_power_domain(intel_encoder);
387 return intel_display_power_enabled(dev_priv, power_domain) &&
388 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
389 }
390
391 static void
392 intel_dp_check_edp(struct intel_dp *intel_dp)
393 {
394 struct drm_device *dev = intel_dp_to_dev(intel_dp);
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (!is_edp(intel_dp))
398 return;
399
400 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
403 I915_READ(_pp_stat_reg(intel_dp)),
404 I915_READ(_pp_ctrl_reg(intel_dp)));
405 }
406 }
407
408 static uint32_t
409 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
410 {
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
415 uint32_t status;
416 bool done;
417
418 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
419 if (has_aux_irq)
420 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
421 msecs_to_jiffies_timeout(10));
422 else
423 done = wait_for_atomic(C, 10) == 0;
424 if (!done)
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
426 has_aux_irq);
427 #undef C
428
429 return status;
430 }
431
432 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
433 {
434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
436
437 /*
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
440 */
441 return index ? 0 : intel_hrawclk(dev) / 2;
442 }
443
444 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
445 {
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448
449 if (index)
450 return 0;
451
452 if (intel_dig_port->port == PORT_A) {
453 if (IS_GEN6(dev) || IS_GEN7(dev))
454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
455 else
456 return 225; /* eDP input clock at 450Mhz */
457 } else {
458 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
459 }
460 }
461
462 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
463 {
464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
465 struct drm_device *dev = intel_dig_port->base.base.dev;
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 if (intel_dig_port->port == PORT_A) {
469 if (index)
470 return 0;
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
472 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
473 /* Workaround for non-ULT HSW */
474 switch (index) {
475 case 0: return 63;
476 case 1: return 72;
477 default: return 0;
478 }
479 } else {
480 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
481 }
482 }
483
484 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
485 {
486 return index ? 0 : 100;
487 }
488
489 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
490 bool has_aux_irq,
491 int send_bytes,
492 uint32_t aux_clock_divider)
493 {
494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
495 struct drm_device *dev = intel_dig_port->base.base.dev;
496 uint32_t precharge, timeout;
497
498 if (IS_GEN6(dev))
499 precharge = 3;
500 else
501 precharge = 5;
502
503 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
504 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
505 else
506 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
507
508 return DP_AUX_CH_CTL_SEND_BUSY |
509 DP_AUX_CH_CTL_DONE |
510 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
511 DP_AUX_CH_CTL_TIME_OUT_ERROR |
512 timeout |
513 DP_AUX_CH_CTL_RECEIVE_ERROR |
514 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
515 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
516 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
517 }
518
519 static int
520 intel_dp_aux_ch(struct intel_dp *intel_dp,
521 uint8_t *send, int send_bytes,
522 uint8_t *recv, int recv_size)
523 {
524 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
525 struct drm_device *dev = intel_dig_port->base.base.dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
528 uint32_t ch_data = ch_ctl + 4;
529 uint32_t aux_clock_divider;
530 int i, ret, recv_bytes;
531 uint32_t status;
532 int try, clock = 0;
533 bool has_aux_irq = HAS_AUX_IRQ(dev);
534 bool vdd;
535
536 vdd = edp_panel_vdd_on(intel_dp);
537
538 /* dp aux is extremely sensitive to irq latency, hence request the
539 * lowest possible wakeup latency and so prevent the cpu from going into
540 * deep sleep states.
541 */
542 pm_qos_update_request(&dev_priv->pm_qos, 0);
543
544 intel_dp_check_edp(intel_dp);
545
546 intel_aux_display_runtime_get(dev_priv);
547
548 /* Try to wait for any previous AUX channel activity */
549 for (try = 0; try < 3; try++) {
550 status = I915_READ_NOTRACE(ch_ctl);
551 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
552 break;
553 msleep(1);
554 }
555
556 if (try == 3) {
557 WARN(1, "dp_aux_ch not started status 0x%08x\n",
558 I915_READ(ch_ctl));
559 ret = -EBUSY;
560 goto out;
561 }
562
563 /* Only 5 data registers! */
564 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
565 ret = -E2BIG;
566 goto out;
567 }
568
569 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
570 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
571 has_aux_irq,
572 send_bytes,
573 aux_clock_divider);
574
575 /* Must try at least 3 times according to DP spec */
576 for (try = 0; try < 5; try++) {
577 /* Load the send data into the aux channel data registers */
578 for (i = 0; i < send_bytes; i += 4)
579 I915_WRITE(ch_data + i,
580 pack_aux(send + i, send_bytes - i));
581
582 /* Send the command and wait for it to complete */
583 I915_WRITE(ch_ctl, send_ctl);
584
585 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
586
587 /* Clear done status and any errors */
588 I915_WRITE(ch_ctl,
589 status |
590 DP_AUX_CH_CTL_DONE |
591 DP_AUX_CH_CTL_TIME_OUT_ERROR |
592 DP_AUX_CH_CTL_RECEIVE_ERROR);
593
594 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
595 DP_AUX_CH_CTL_RECEIVE_ERROR))
596 continue;
597 if (status & DP_AUX_CH_CTL_DONE)
598 break;
599 }
600 if (status & DP_AUX_CH_CTL_DONE)
601 break;
602 }
603
604 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
605 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
606 ret = -EBUSY;
607 goto out;
608 }
609
610 /* Check for timeout or receive error.
611 * Timeouts occur when the sink is not connected
612 */
613 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
614 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
615 ret = -EIO;
616 goto out;
617 }
618
619 /* Timeouts occur when the device isn't connected, so they're
620 * "normal" -- don't fill the kernel log with these */
621 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
622 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
623 ret = -ETIMEDOUT;
624 goto out;
625 }
626
627 /* Unload any bytes sent back from the other side */
628 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
629 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
630 if (recv_bytes > recv_size)
631 recv_bytes = recv_size;
632
633 for (i = 0; i < recv_bytes; i += 4)
634 unpack_aux(I915_READ(ch_data + i),
635 recv + i, recv_bytes - i);
636
637 ret = recv_bytes;
638 out:
639 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
640 intel_aux_display_runtime_put(dev_priv);
641
642 if (vdd)
643 edp_panel_vdd_off(intel_dp, false);
644
645 return ret;
646 }
647
648 #define BARE_ADDRESS_SIZE 3
649 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
650 static ssize_t
651 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
652 {
653 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
654 uint8_t txbuf[20], rxbuf[20];
655 size_t txsize, rxsize;
656 int ret;
657
658 txbuf[0] = msg->request << 4;
659 txbuf[1] = msg->address >> 8;
660 txbuf[2] = msg->address & 0xff;
661 txbuf[3] = msg->size - 1;
662
663 switch (msg->request & ~DP_AUX_I2C_MOT) {
664 case DP_AUX_NATIVE_WRITE:
665 case DP_AUX_I2C_WRITE:
666 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
667 rxsize = 1;
668
669 if (WARN_ON(txsize > 20))
670 return -E2BIG;
671
672 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
673
674 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
675 if (ret > 0) {
676 msg->reply = rxbuf[0] >> 4;
677
678 /* Return payload size. */
679 ret = msg->size;
680 }
681 break;
682
683 case DP_AUX_NATIVE_READ:
684 case DP_AUX_I2C_READ:
685 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
686 rxsize = msg->size + 1;
687
688 if (WARN_ON(rxsize > 20))
689 return -E2BIG;
690
691 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
692 if (ret > 0) {
693 msg->reply = rxbuf[0] >> 4;
694 /*
695 * Assume happy day, and copy the data. The caller is
696 * expected to check msg->reply before touching it.
697 *
698 * Return payload size.
699 */
700 ret--;
701 memcpy(msg->buffer, rxbuf + 1, ret);
702 }
703 break;
704
705 default:
706 ret = -EINVAL;
707 break;
708 }
709
710 return ret;
711 }
712
713 static void
714 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
715 {
716 struct drm_device *dev = intel_dp_to_dev(intel_dp);
717 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
718 enum port port = intel_dig_port->port;
719 const char *name = NULL;
720 int ret;
721
722 switch (port) {
723 case PORT_A:
724 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
725 name = "DPDDC-A";
726 break;
727 case PORT_B:
728 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
729 name = "DPDDC-B";
730 break;
731 case PORT_C:
732 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
733 name = "DPDDC-C";
734 break;
735 case PORT_D:
736 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
737 name = "DPDDC-D";
738 break;
739 default:
740 BUG();
741 }
742
743 if (!HAS_DDI(dev))
744 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
745
746 intel_dp->aux.name = name;
747 intel_dp->aux.dev = dev->dev;
748 intel_dp->aux.transfer = intel_dp_aux_transfer;
749
750 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
751 connector->base.kdev->kobj.name);
752
753 ret = drm_dp_aux_register(&intel_dp->aux);
754 if (ret < 0) {
755 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
756 name, ret);
757 return;
758 }
759
760 ret = sysfs_create_link(&connector->base.kdev->kobj,
761 &intel_dp->aux.ddc.dev.kobj,
762 intel_dp->aux.ddc.dev.kobj.name);
763 if (ret < 0) {
764 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
765 drm_dp_aux_unregister(&intel_dp->aux);
766 }
767 }
768
769 static void
770 intel_dp_connector_unregister(struct intel_connector *intel_connector)
771 {
772 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
773
774 if (!intel_connector->mst_port)
775 sysfs_remove_link(&intel_connector->base.kdev->kobj,
776 intel_dp->aux.ddc.dev.kobj.name);
777 intel_connector_unregister(intel_connector);
778 }
779
780 static void
781 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
782 {
783 switch (link_bw) {
784 case DP_LINK_BW_1_62:
785 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
786 break;
787 case DP_LINK_BW_2_7:
788 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
789 break;
790 case DP_LINK_BW_5_4:
791 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
792 break;
793 }
794 }
795
796 static void
797 intel_dp_set_clock(struct intel_encoder *encoder,
798 struct intel_crtc_config *pipe_config, int link_bw)
799 {
800 struct drm_device *dev = encoder->base.dev;
801 const struct dp_link_dpll *divisor = NULL;
802 int i, count = 0;
803
804 if (IS_G4X(dev)) {
805 divisor = gen4_dpll;
806 count = ARRAY_SIZE(gen4_dpll);
807 } else if (HAS_PCH_SPLIT(dev)) {
808 divisor = pch_dpll;
809 count = ARRAY_SIZE(pch_dpll);
810 } else if (IS_CHERRYVIEW(dev)) {
811 divisor = chv_dpll;
812 count = ARRAY_SIZE(chv_dpll);
813 } else if (IS_VALLEYVIEW(dev)) {
814 divisor = vlv_dpll;
815 count = ARRAY_SIZE(vlv_dpll);
816 }
817
818 if (divisor && count) {
819 for (i = 0; i < count; i++) {
820 if (link_bw == divisor[i].link_bw) {
821 pipe_config->dpll = divisor[i].dpll;
822 pipe_config->clock_set = true;
823 break;
824 }
825 }
826 }
827 }
828
829 bool
830 intel_dp_compute_config(struct intel_encoder *encoder,
831 struct intel_crtc_config *pipe_config)
832 {
833 struct drm_device *dev = encoder->base.dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
836 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
837 enum port port = dp_to_dig_port(intel_dp)->port;
838 struct intel_crtc *intel_crtc = encoder->new_crtc;
839 struct intel_connector *intel_connector = intel_dp->attached_connector;
840 int lane_count, clock;
841 int min_lane_count = 1;
842 int max_lane_count = intel_dp_max_lane_count(intel_dp);
843 /* Conveniently, the link BW constants become indices with a shift...*/
844 int min_clock = 0;
845 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
846 int bpp, mode_rate;
847 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
848 int link_avail, link_clock;
849
850 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
851 pipe_config->has_pch_encoder = true;
852
853 pipe_config->has_dp_encoder = true;
854 pipe_config->has_drrs = false;
855 pipe_config->has_audio = intel_dp->has_audio;
856
857 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
858 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
859 adjusted_mode);
860 if (!HAS_PCH_SPLIT(dev))
861 intel_gmch_panel_fitting(intel_crtc, pipe_config,
862 intel_connector->panel.fitting_mode);
863 else
864 intel_pch_panel_fitting(intel_crtc, pipe_config,
865 intel_connector->panel.fitting_mode);
866 }
867
868 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
869 return false;
870
871 DRM_DEBUG_KMS("DP link computation with max lane count %i "
872 "max bw %02x pixel clock %iKHz\n",
873 max_lane_count, bws[max_clock],
874 adjusted_mode->crtc_clock);
875
876 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
877 * bpc in between. */
878 bpp = pipe_config->pipe_bpp;
879 if (is_edp(intel_dp)) {
880 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
881 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
882 dev_priv->vbt.edp_bpp);
883 bpp = dev_priv->vbt.edp_bpp;
884 }
885
886 if (IS_BROADWELL(dev)) {
887 /* Yes, it's an ugly hack. */
888 min_lane_count = max_lane_count;
889 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
890 min_lane_count);
891 } else if (dev_priv->vbt.edp_lanes) {
892 min_lane_count = min(dev_priv->vbt.edp_lanes,
893 max_lane_count);
894 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
895 min_lane_count);
896 }
897
898 if (dev_priv->vbt.edp_rate) {
899 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
900 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
901 bws[min_clock]);
902 }
903 }
904
905 for (; bpp >= 6*3; bpp -= 2*3) {
906 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
907 bpp);
908
909 for (clock = min_clock; clock <= max_clock; clock++) {
910 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
911 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
912 link_avail = intel_dp_max_data_rate(link_clock,
913 lane_count);
914
915 if (mode_rate <= link_avail) {
916 goto found;
917 }
918 }
919 }
920 }
921
922 return false;
923
924 found:
925 if (intel_dp->color_range_auto) {
926 /*
927 * See:
928 * CEA-861-E - 5.1 Default Encoding Parameters
929 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
930 */
931 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
932 intel_dp->color_range = DP_COLOR_RANGE_16_235;
933 else
934 intel_dp->color_range = 0;
935 }
936
937 if (intel_dp->color_range)
938 pipe_config->limited_color_range = true;
939
940 intel_dp->link_bw = bws[clock];
941 intel_dp->lane_count = lane_count;
942 pipe_config->pipe_bpp = bpp;
943 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
944
945 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
946 intel_dp->link_bw, intel_dp->lane_count,
947 pipe_config->port_clock, bpp);
948 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
949 mode_rate, link_avail);
950
951 intel_link_compute_m_n(bpp, lane_count,
952 adjusted_mode->crtc_clock,
953 pipe_config->port_clock,
954 &pipe_config->dp_m_n);
955
956 if (intel_connector->panel.downclock_mode != NULL &&
957 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
958 pipe_config->has_drrs = true;
959 intel_link_compute_m_n(bpp, lane_count,
960 intel_connector->panel.downclock_mode->clock,
961 pipe_config->port_clock,
962 &pipe_config->dp_m2_n2);
963 }
964
965 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
966 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
967 else
968 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
969
970 return true;
971 }
972
973 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
974 {
975 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
976 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
977 struct drm_device *dev = crtc->base.dev;
978 struct drm_i915_private *dev_priv = dev->dev_private;
979 u32 dpa_ctl;
980
981 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
982 dpa_ctl = I915_READ(DP_A);
983 dpa_ctl &= ~DP_PLL_FREQ_MASK;
984
985 if (crtc->config.port_clock == 162000) {
986 /* For a long time we've carried around a ILK-DevA w/a for the
987 * 160MHz clock. If we're really unlucky, it's still required.
988 */
989 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
990 dpa_ctl |= DP_PLL_FREQ_160MHZ;
991 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
992 } else {
993 dpa_ctl |= DP_PLL_FREQ_270MHZ;
994 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
995 }
996
997 I915_WRITE(DP_A, dpa_ctl);
998
999 POSTING_READ(DP_A);
1000 udelay(500);
1001 }
1002
1003 static void intel_dp_prepare(struct intel_encoder *encoder)
1004 {
1005 struct drm_device *dev = encoder->base.dev;
1006 struct drm_i915_private *dev_priv = dev->dev_private;
1007 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1008 enum port port = dp_to_dig_port(intel_dp)->port;
1009 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1010 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1011
1012 /*
1013 * There are four kinds of DP registers:
1014 *
1015 * IBX PCH
1016 * SNB CPU
1017 * IVB CPU
1018 * CPT PCH
1019 *
1020 * IBX PCH and CPU are the same for almost everything,
1021 * except that the CPU DP PLL is configured in this
1022 * register
1023 *
1024 * CPT PCH is quite different, having many bits moved
1025 * to the TRANS_DP_CTL register instead. That
1026 * configuration happens (oddly) in ironlake_pch_enable
1027 */
1028
1029 /* Preserve the BIOS-computed detected bit. This is
1030 * supposed to be read-only.
1031 */
1032 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1033
1034 /* Handle DP bits in common between all three register formats */
1035 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1036 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1037
1038 if (crtc->config.has_audio) {
1039 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1040 pipe_name(crtc->pipe));
1041 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1042 intel_write_eld(&encoder->base, adjusted_mode);
1043 }
1044
1045 /* Split out the IBX/CPU vs CPT settings */
1046
1047 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1048 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1049 intel_dp->DP |= DP_SYNC_HS_HIGH;
1050 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1051 intel_dp->DP |= DP_SYNC_VS_HIGH;
1052 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1053
1054 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1055 intel_dp->DP |= DP_ENHANCED_FRAMING;
1056
1057 intel_dp->DP |= crtc->pipe << 29;
1058 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1059 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1060 intel_dp->DP |= intel_dp->color_range;
1061
1062 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1063 intel_dp->DP |= DP_SYNC_HS_HIGH;
1064 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1065 intel_dp->DP |= DP_SYNC_VS_HIGH;
1066 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1067
1068 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1069 intel_dp->DP |= DP_ENHANCED_FRAMING;
1070
1071 if (!IS_CHERRYVIEW(dev)) {
1072 if (crtc->pipe == 1)
1073 intel_dp->DP |= DP_PIPEB_SELECT;
1074 } else {
1075 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1076 }
1077 } else {
1078 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1079 }
1080 }
1081
1082 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1083 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1084
1085 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1086 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1087
1088 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1089 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1090
1091 static void wait_panel_status(struct intel_dp *intel_dp,
1092 u32 mask,
1093 u32 value)
1094 {
1095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 u32 pp_stat_reg, pp_ctrl_reg;
1098
1099 pp_stat_reg = _pp_stat_reg(intel_dp);
1100 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1101
1102 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1103 mask, value,
1104 I915_READ(pp_stat_reg),
1105 I915_READ(pp_ctrl_reg));
1106
1107 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1108 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1109 I915_READ(pp_stat_reg),
1110 I915_READ(pp_ctrl_reg));
1111 }
1112
1113 DRM_DEBUG_KMS("Wait complete\n");
1114 }
1115
1116 static void wait_panel_on(struct intel_dp *intel_dp)
1117 {
1118 DRM_DEBUG_KMS("Wait for panel power on\n");
1119 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1120 }
1121
1122 static void wait_panel_off(struct intel_dp *intel_dp)
1123 {
1124 DRM_DEBUG_KMS("Wait for panel power off time\n");
1125 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1126 }
1127
1128 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1129 {
1130 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1131
1132 /* When we disable the VDD override bit last we have to do the manual
1133 * wait. */
1134 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1135 intel_dp->panel_power_cycle_delay);
1136
1137 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1138 }
1139
1140 static void wait_backlight_on(struct intel_dp *intel_dp)
1141 {
1142 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1143 intel_dp->backlight_on_delay);
1144 }
1145
1146 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1147 {
1148 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1149 intel_dp->backlight_off_delay);
1150 }
1151
1152 /* Read the current pp_control value, unlocking the register if it
1153 * is locked
1154 */
1155
1156 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1157 {
1158 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1159 struct drm_i915_private *dev_priv = dev->dev_private;
1160 u32 control;
1161
1162 control = I915_READ(_pp_ctrl_reg(intel_dp));
1163 control &= ~PANEL_UNLOCK_MASK;
1164 control |= PANEL_UNLOCK_REGS;
1165 return control;
1166 }
1167
1168 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1169 {
1170 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1171 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1172 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 enum intel_display_power_domain power_domain;
1175 u32 pp;
1176 u32 pp_stat_reg, pp_ctrl_reg;
1177 bool need_to_disable = !intel_dp->want_panel_vdd;
1178
1179 if (!is_edp(intel_dp))
1180 return false;
1181
1182 intel_dp->want_panel_vdd = true;
1183
1184 if (edp_have_panel_vdd(intel_dp))
1185 return need_to_disable;
1186
1187 power_domain = intel_display_port_power_domain(intel_encoder);
1188 intel_display_power_get(dev_priv, power_domain);
1189
1190 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1191
1192 if (!edp_have_panel_power(intel_dp))
1193 wait_panel_power_cycle(intel_dp);
1194
1195 pp = ironlake_get_pp_control(intel_dp);
1196 pp |= EDP_FORCE_VDD;
1197
1198 pp_stat_reg = _pp_stat_reg(intel_dp);
1199 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1200
1201 I915_WRITE(pp_ctrl_reg, pp);
1202 POSTING_READ(pp_ctrl_reg);
1203 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1204 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1205 /*
1206 * If the panel wasn't on, delay before accessing aux channel
1207 */
1208 if (!edp_have_panel_power(intel_dp)) {
1209 DRM_DEBUG_KMS("eDP was not running\n");
1210 msleep(intel_dp->panel_power_up_delay);
1211 }
1212
1213 return need_to_disable;
1214 }
1215
1216 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1217 {
1218 if (is_edp(intel_dp)) {
1219 bool vdd = edp_panel_vdd_on(intel_dp);
1220
1221 WARN(!vdd, "eDP VDD already requested on\n");
1222 }
1223 }
1224
1225 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1226 {
1227 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1228 struct drm_i915_private *dev_priv = dev->dev_private;
1229 u32 pp;
1230 u32 pp_stat_reg, pp_ctrl_reg;
1231
1232 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1233
1234 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1235 struct intel_digital_port *intel_dig_port =
1236 dp_to_dig_port(intel_dp);
1237 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1238 enum intel_display_power_domain power_domain;
1239
1240 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1241
1242 pp = ironlake_get_pp_control(intel_dp);
1243 pp &= ~EDP_FORCE_VDD;
1244
1245 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1246 pp_stat_reg = _pp_stat_reg(intel_dp);
1247
1248 I915_WRITE(pp_ctrl_reg, pp);
1249 POSTING_READ(pp_ctrl_reg);
1250
1251 /* Make sure sequencer is idle before allowing subsequent activity */
1252 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1253 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1254
1255 if ((pp & POWER_TARGET_ON) == 0)
1256 intel_dp->last_power_cycle = jiffies;
1257
1258 power_domain = intel_display_port_power_domain(intel_encoder);
1259 intel_display_power_put(dev_priv, power_domain);
1260 }
1261 }
1262
1263 static void edp_panel_vdd_work(struct work_struct *__work)
1264 {
1265 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1266 struct intel_dp, panel_vdd_work);
1267 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1268
1269 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1270 edp_panel_vdd_off_sync(intel_dp);
1271 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1272 }
1273
1274 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1275 {
1276 unsigned long delay;
1277
1278 /*
1279 * Queue the timer to fire a long time from now (relative to the power
1280 * down delay) to keep the panel power up across a sequence of
1281 * operations.
1282 */
1283 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1284 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1285 }
1286
1287 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1288 {
1289 if (!is_edp(intel_dp))
1290 return;
1291
1292 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1293
1294 intel_dp->want_panel_vdd = false;
1295
1296 if (sync)
1297 edp_panel_vdd_off_sync(intel_dp);
1298 else
1299 edp_panel_vdd_schedule_off(intel_dp);
1300 }
1301
1302 static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1303 {
1304 edp_panel_vdd_off(intel_dp, sync);
1305 }
1306
1307 void intel_edp_panel_on(struct intel_dp *intel_dp)
1308 {
1309 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 u32 pp;
1312 u32 pp_ctrl_reg;
1313
1314 if (!is_edp(intel_dp))
1315 return;
1316
1317 DRM_DEBUG_KMS("Turn eDP power on\n");
1318
1319 if (edp_have_panel_power(intel_dp)) {
1320 DRM_DEBUG_KMS("eDP power already on\n");
1321 return;
1322 }
1323
1324 wait_panel_power_cycle(intel_dp);
1325
1326 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1327 pp = ironlake_get_pp_control(intel_dp);
1328 if (IS_GEN5(dev)) {
1329 /* ILK workaround: disable reset around power sequence */
1330 pp &= ~PANEL_POWER_RESET;
1331 I915_WRITE(pp_ctrl_reg, pp);
1332 POSTING_READ(pp_ctrl_reg);
1333 }
1334
1335 pp |= POWER_TARGET_ON;
1336 if (!IS_GEN5(dev))
1337 pp |= PANEL_POWER_RESET;
1338
1339 I915_WRITE(pp_ctrl_reg, pp);
1340 POSTING_READ(pp_ctrl_reg);
1341
1342 wait_panel_on(intel_dp);
1343 intel_dp->last_power_on = jiffies;
1344
1345 if (IS_GEN5(dev)) {
1346 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1347 I915_WRITE(pp_ctrl_reg, pp);
1348 POSTING_READ(pp_ctrl_reg);
1349 }
1350 }
1351
1352 void intel_edp_panel_off(struct intel_dp *intel_dp)
1353 {
1354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1355 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1356 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1357 struct drm_i915_private *dev_priv = dev->dev_private;
1358 enum intel_display_power_domain power_domain;
1359 u32 pp;
1360 u32 pp_ctrl_reg;
1361
1362 if (!is_edp(intel_dp))
1363 return;
1364
1365 DRM_DEBUG_KMS("Turn eDP power off\n");
1366
1367 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1368
1369 pp = ironlake_get_pp_control(intel_dp);
1370 /* We need to switch off panel power _and_ force vdd, for otherwise some
1371 * panels get very unhappy and cease to work. */
1372 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1373 EDP_BLC_ENABLE);
1374
1375 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1376
1377 intel_dp->want_panel_vdd = false;
1378
1379 I915_WRITE(pp_ctrl_reg, pp);
1380 POSTING_READ(pp_ctrl_reg);
1381
1382 intel_dp->last_power_cycle = jiffies;
1383 wait_panel_off(intel_dp);
1384
1385 /* We got a reference when we enabled the VDD. */
1386 power_domain = intel_display_port_power_domain(intel_encoder);
1387 intel_display_power_put(dev_priv, power_domain);
1388 }
1389
1390 /* Enable backlight in the panel power control. */
1391 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1392 {
1393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1394 struct drm_device *dev = intel_dig_port->base.base.dev;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 u32 pp;
1397 u32 pp_ctrl_reg;
1398
1399 /*
1400 * If we enable the backlight right away following a panel power
1401 * on, we may see slight flicker as the panel syncs with the eDP
1402 * link. So delay a bit to make sure the image is solid before
1403 * allowing it to appear.
1404 */
1405 wait_backlight_on(intel_dp);
1406 pp = ironlake_get_pp_control(intel_dp);
1407 pp |= EDP_BLC_ENABLE;
1408
1409 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1410
1411 I915_WRITE(pp_ctrl_reg, pp);
1412 POSTING_READ(pp_ctrl_reg);
1413 }
1414
1415 /* Enable backlight PWM and backlight PP control. */
1416 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1417 {
1418 if (!is_edp(intel_dp))
1419 return;
1420
1421 DRM_DEBUG_KMS("\n");
1422
1423 intel_panel_enable_backlight(intel_dp->attached_connector);
1424 _intel_edp_backlight_on(intel_dp);
1425 }
1426
1427 /* Disable backlight in the panel power control. */
1428 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1429 {
1430 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 u32 pp;
1433 u32 pp_ctrl_reg;
1434
1435 pp = ironlake_get_pp_control(intel_dp);
1436 pp &= ~EDP_BLC_ENABLE;
1437
1438 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1439
1440 I915_WRITE(pp_ctrl_reg, pp);
1441 POSTING_READ(pp_ctrl_reg);
1442 intel_dp->last_backlight_off = jiffies;
1443
1444 edp_wait_backlight_off(intel_dp);
1445 }
1446
1447 /* Disable backlight PP control and backlight PWM. */
1448 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1449 {
1450 if (!is_edp(intel_dp))
1451 return;
1452
1453 DRM_DEBUG_KMS("\n");
1454
1455 _intel_edp_backlight_off(intel_dp);
1456 intel_panel_disable_backlight(intel_dp->attached_connector);
1457 }
1458
1459 /*
1460 * Hook for controlling the panel power control backlight through the bl_power
1461 * sysfs attribute. Take care to handle multiple calls.
1462 */
1463 static void intel_edp_backlight_power(struct intel_connector *connector,
1464 bool enable)
1465 {
1466 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1467 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1468
1469 if (is_enabled == enable)
1470 return;
1471
1472 DRM_DEBUG_KMS("\n");
1473
1474 if (enable)
1475 _intel_edp_backlight_on(intel_dp);
1476 else
1477 _intel_edp_backlight_off(intel_dp);
1478 }
1479
1480 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1481 {
1482 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1483 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1484 struct drm_device *dev = crtc->dev;
1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 u32 dpa_ctl;
1487
1488 assert_pipe_disabled(dev_priv,
1489 to_intel_crtc(crtc)->pipe);
1490
1491 DRM_DEBUG_KMS("\n");
1492 dpa_ctl = I915_READ(DP_A);
1493 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1494 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1495
1496 /* We don't adjust intel_dp->DP while tearing down the link, to
1497 * facilitate link retraining (e.g. after hotplug). Hence clear all
1498 * enable bits here to ensure that we don't enable too much. */
1499 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1500 intel_dp->DP |= DP_PLL_ENABLE;
1501 I915_WRITE(DP_A, intel_dp->DP);
1502 POSTING_READ(DP_A);
1503 udelay(200);
1504 }
1505
1506 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1507 {
1508 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1509 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1510 struct drm_device *dev = crtc->dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 u32 dpa_ctl;
1513
1514 assert_pipe_disabled(dev_priv,
1515 to_intel_crtc(crtc)->pipe);
1516
1517 dpa_ctl = I915_READ(DP_A);
1518 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1519 "dp pll off, should be on\n");
1520 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1521
1522 /* We can't rely on the value tracked for the DP register in
1523 * intel_dp->DP because link_down must not change that (otherwise link
1524 * re-training will fail. */
1525 dpa_ctl &= ~DP_PLL_ENABLE;
1526 I915_WRITE(DP_A, dpa_ctl);
1527 POSTING_READ(DP_A);
1528 udelay(200);
1529 }
1530
1531 /* If the sink supports it, try to set the power state appropriately */
1532 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1533 {
1534 int ret, i;
1535
1536 /* Should have a valid DPCD by this point */
1537 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1538 return;
1539
1540 if (mode != DRM_MODE_DPMS_ON) {
1541 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1542 DP_SET_POWER_D3);
1543 if (ret != 1)
1544 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1545 } else {
1546 /*
1547 * When turning on, we need to retry for 1ms to give the sink
1548 * time to wake up.
1549 */
1550 for (i = 0; i < 3; i++) {
1551 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1552 DP_SET_POWER_D0);
1553 if (ret == 1)
1554 break;
1555 msleep(1);
1556 }
1557 }
1558 }
1559
1560 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1561 enum pipe *pipe)
1562 {
1563 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1564 enum port port = dp_to_dig_port(intel_dp)->port;
1565 struct drm_device *dev = encoder->base.dev;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 enum intel_display_power_domain power_domain;
1568 u32 tmp;
1569
1570 power_domain = intel_display_port_power_domain(encoder);
1571 if (!intel_display_power_enabled(dev_priv, power_domain))
1572 return false;
1573
1574 tmp = I915_READ(intel_dp->output_reg);
1575
1576 if (!(tmp & DP_PORT_EN))
1577 return false;
1578
1579 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1580 *pipe = PORT_TO_PIPE_CPT(tmp);
1581 } else if (IS_CHERRYVIEW(dev)) {
1582 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1583 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1584 *pipe = PORT_TO_PIPE(tmp);
1585 } else {
1586 u32 trans_sel;
1587 u32 trans_dp;
1588 int i;
1589
1590 switch (intel_dp->output_reg) {
1591 case PCH_DP_B:
1592 trans_sel = TRANS_DP_PORT_SEL_B;
1593 break;
1594 case PCH_DP_C:
1595 trans_sel = TRANS_DP_PORT_SEL_C;
1596 break;
1597 case PCH_DP_D:
1598 trans_sel = TRANS_DP_PORT_SEL_D;
1599 break;
1600 default:
1601 return true;
1602 }
1603
1604 for_each_pipe(dev_priv, i) {
1605 trans_dp = I915_READ(TRANS_DP_CTL(i));
1606 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1607 *pipe = i;
1608 return true;
1609 }
1610 }
1611
1612 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1613 intel_dp->output_reg);
1614 }
1615
1616 return true;
1617 }
1618
1619 static void intel_dp_get_config(struct intel_encoder *encoder,
1620 struct intel_crtc_config *pipe_config)
1621 {
1622 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1623 u32 tmp, flags = 0;
1624 struct drm_device *dev = encoder->base.dev;
1625 struct drm_i915_private *dev_priv = dev->dev_private;
1626 enum port port = dp_to_dig_port(intel_dp)->port;
1627 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1628 int dotclock;
1629
1630 tmp = I915_READ(intel_dp->output_reg);
1631 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1632 pipe_config->has_audio = true;
1633
1634 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1635 if (tmp & DP_SYNC_HS_HIGH)
1636 flags |= DRM_MODE_FLAG_PHSYNC;
1637 else
1638 flags |= DRM_MODE_FLAG_NHSYNC;
1639
1640 if (tmp & DP_SYNC_VS_HIGH)
1641 flags |= DRM_MODE_FLAG_PVSYNC;
1642 else
1643 flags |= DRM_MODE_FLAG_NVSYNC;
1644 } else {
1645 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1646 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1647 flags |= DRM_MODE_FLAG_PHSYNC;
1648 else
1649 flags |= DRM_MODE_FLAG_NHSYNC;
1650
1651 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1652 flags |= DRM_MODE_FLAG_PVSYNC;
1653 else
1654 flags |= DRM_MODE_FLAG_NVSYNC;
1655 }
1656
1657 pipe_config->adjusted_mode.flags |= flags;
1658
1659 pipe_config->has_dp_encoder = true;
1660
1661 intel_dp_get_m_n(crtc, pipe_config);
1662
1663 if (port == PORT_A) {
1664 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1665 pipe_config->port_clock = 162000;
1666 else
1667 pipe_config->port_clock = 270000;
1668 }
1669
1670 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1671 &pipe_config->dp_m_n);
1672
1673 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1674 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1675
1676 pipe_config->adjusted_mode.crtc_clock = dotclock;
1677
1678 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1679 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1680 /*
1681 * This is a big fat ugly hack.
1682 *
1683 * Some machines in UEFI boot mode provide us a VBT that has 18
1684 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1685 * unknown we fail to light up. Yet the same BIOS boots up with
1686 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1687 * max, not what it tells us to use.
1688 *
1689 * Note: This will still be broken if the eDP panel is not lit
1690 * up by the BIOS, and thus we can't get the mode at module
1691 * load.
1692 */
1693 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1694 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1695 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1696 }
1697 }
1698
1699 static bool is_edp_psr(struct intel_dp *intel_dp)
1700 {
1701 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1702 }
1703
1704 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1705 {
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707
1708 if (!HAS_PSR(dev))
1709 return false;
1710
1711 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1712 }
1713
1714 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1715 struct edp_vsc_psr *vsc_psr)
1716 {
1717 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1718 struct drm_device *dev = dig_port->base.base.dev;
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1721 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1722 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1723 uint32_t *data = (uint32_t *) vsc_psr;
1724 unsigned int i;
1725
1726 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1727 the video DIP being updated before program video DIP data buffer
1728 registers for DIP being updated. */
1729 I915_WRITE(ctl_reg, 0);
1730 POSTING_READ(ctl_reg);
1731
1732 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1733 if (i < sizeof(struct edp_vsc_psr))
1734 I915_WRITE(data_reg + i, *data++);
1735 else
1736 I915_WRITE(data_reg + i, 0);
1737 }
1738
1739 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1740 POSTING_READ(ctl_reg);
1741 }
1742
1743 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1744 {
1745 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 struct edp_vsc_psr psr_vsc;
1748
1749 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1750 memset(&psr_vsc, 0, sizeof(psr_vsc));
1751 psr_vsc.sdp_header.HB0 = 0;
1752 psr_vsc.sdp_header.HB1 = 0x7;
1753 psr_vsc.sdp_header.HB2 = 0x2;
1754 psr_vsc.sdp_header.HB3 = 0x8;
1755 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1756
1757 /* Avoid continuous PSR exit by masking memup and hpd */
1758 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1759 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1760 }
1761
1762 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1763 {
1764 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1765 struct drm_device *dev = dig_port->base.base.dev;
1766 struct drm_i915_private *dev_priv = dev->dev_private;
1767 uint32_t aux_clock_divider;
1768 int precharge = 0x3;
1769 int msg_size = 5; /* Header(4) + Message(1) */
1770 bool only_standby = false;
1771
1772 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1773
1774 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1775 only_standby = true;
1776
1777 /* Enable PSR in sink */
1778 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1779 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1780 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1781 else
1782 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1783 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1784
1785 /* Setup AUX registers */
1786 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1787 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1788 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1789 DP_AUX_CH_CTL_TIME_OUT_400us |
1790 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1791 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1792 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1793 }
1794
1795 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1796 {
1797 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1798 struct drm_device *dev = dig_port->base.base.dev;
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1800 uint32_t max_sleep_time = 0x1f;
1801 uint32_t idle_frames = 1;
1802 uint32_t val = 0x0;
1803 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1804 bool only_standby = false;
1805
1806 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1807 only_standby = true;
1808
1809 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1810 val |= EDP_PSR_LINK_STANDBY;
1811 val |= EDP_PSR_TP2_TP3_TIME_0us;
1812 val |= EDP_PSR_TP1_TIME_0us;
1813 val |= EDP_PSR_SKIP_AUX_EXIT;
1814 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1815 } else
1816 val |= EDP_PSR_LINK_DISABLE;
1817
1818 I915_WRITE(EDP_PSR_CTL(dev), val |
1819 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1820 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1821 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1822 EDP_PSR_ENABLE);
1823 }
1824
1825 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1826 {
1827 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1828 struct drm_device *dev = dig_port->base.base.dev;
1829 struct drm_i915_private *dev_priv = dev->dev_private;
1830 struct drm_crtc *crtc = dig_port->base.base.crtc;
1831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1832
1833 lockdep_assert_held(&dev_priv->psr.lock);
1834 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1835 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1836
1837 dev_priv->psr.source_ok = false;
1838
1839 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1840 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1841 return false;
1842 }
1843
1844 if (!i915.enable_psr) {
1845 DRM_DEBUG_KMS("PSR disable by flag\n");
1846 return false;
1847 }
1848
1849 /* Below limitations aren't valid for Broadwell */
1850 if (IS_BROADWELL(dev))
1851 goto out;
1852
1853 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1854 S3D_ENABLE) {
1855 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1856 return false;
1857 }
1858
1859 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1860 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1861 return false;
1862 }
1863
1864 out:
1865 dev_priv->psr.source_ok = true;
1866 return true;
1867 }
1868
1869 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1870 {
1871 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1872 struct drm_device *dev = intel_dig_port->base.base.dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874
1875 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1876 WARN_ON(dev_priv->psr.active);
1877 lockdep_assert_held(&dev_priv->psr.lock);
1878
1879 /* Enable PSR on the panel */
1880 intel_edp_psr_enable_sink(intel_dp);
1881
1882 /* Enable PSR on the host */
1883 intel_edp_psr_enable_source(intel_dp);
1884
1885 dev_priv->psr.active = true;
1886 }
1887
1888 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1889 {
1890 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1891 struct drm_i915_private *dev_priv = dev->dev_private;
1892
1893 if (!HAS_PSR(dev)) {
1894 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1895 return;
1896 }
1897
1898 if (!is_edp_psr(intel_dp)) {
1899 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1900 return;
1901 }
1902
1903 mutex_lock(&dev_priv->psr.lock);
1904 if (dev_priv->psr.enabled) {
1905 DRM_DEBUG_KMS("PSR already in use\n");
1906 mutex_unlock(&dev_priv->psr.lock);
1907 return;
1908 }
1909
1910 dev_priv->psr.busy_frontbuffer_bits = 0;
1911
1912 /* Setup PSR once */
1913 intel_edp_psr_setup(intel_dp);
1914
1915 if (intel_edp_psr_match_conditions(intel_dp))
1916 dev_priv->psr.enabled = intel_dp;
1917 mutex_unlock(&dev_priv->psr.lock);
1918 }
1919
1920 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1921 {
1922 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1923 struct drm_i915_private *dev_priv = dev->dev_private;
1924
1925 mutex_lock(&dev_priv->psr.lock);
1926 if (!dev_priv->psr.enabled) {
1927 mutex_unlock(&dev_priv->psr.lock);
1928 return;
1929 }
1930
1931 if (dev_priv->psr.active) {
1932 I915_WRITE(EDP_PSR_CTL(dev),
1933 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1934
1935 /* Wait till PSR is idle */
1936 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1937 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1938 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1939
1940 dev_priv->psr.active = false;
1941 } else {
1942 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1943 }
1944
1945 dev_priv->psr.enabled = NULL;
1946 mutex_unlock(&dev_priv->psr.lock);
1947
1948 cancel_delayed_work_sync(&dev_priv->psr.work);
1949 }
1950
1951 static void intel_edp_psr_work(struct work_struct *work)
1952 {
1953 struct drm_i915_private *dev_priv =
1954 container_of(work, typeof(*dev_priv), psr.work.work);
1955 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1956
1957 mutex_lock(&dev_priv->psr.lock);
1958 intel_dp = dev_priv->psr.enabled;
1959
1960 if (!intel_dp)
1961 goto unlock;
1962
1963 /*
1964 * The delayed work can race with an invalidate hence we need to
1965 * recheck. Since psr_flush first clears this and then reschedules we
1966 * won't ever miss a flush when bailing out here.
1967 */
1968 if (dev_priv->psr.busy_frontbuffer_bits)
1969 goto unlock;
1970
1971 intel_edp_psr_do_enable(intel_dp);
1972 unlock:
1973 mutex_unlock(&dev_priv->psr.lock);
1974 }
1975
1976 static void intel_edp_psr_do_exit(struct drm_device *dev)
1977 {
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979
1980 if (dev_priv->psr.active) {
1981 u32 val = I915_READ(EDP_PSR_CTL(dev));
1982
1983 WARN_ON(!(val & EDP_PSR_ENABLE));
1984
1985 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1986
1987 dev_priv->psr.active = false;
1988 }
1989
1990 }
1991
1992 void intel_edp_psr_invalidate(struct drm_device *dev,
1993 unsigned frontbuffer_bits)
1994 {
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct drm_crtc *crtc;
1997 enum pipe pipe;
1998
1999 mutex_lock(&dev_priv->psr.lock);
2000 if (!dev_priv->psr.enabled) {
2001 mutex_unlock(&dev_priv->psr.lock);
2002 return;
2003 }
2004
2005 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2006 pipe = to_intel_crtc(crtc)->pipe;
2007
2008 intel_edp_psr_do_exit(dev);
2009
2010 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2011
2012 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2013 mutex_unlock(&dev_priv->psr.lock);
2014 }
2015
2016 void intel_edp_psr_flush(struct drm_device *dev,
2017 unsigned frontbuffer_bits)
2018 {
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2020 struct drm_crtc *crtc;
2021 enum pipe pipe;
2022
2023 mutex_lock(&dev_priv->psr.lock);
2024 if (!dev_priv->psr.enabled) {
2025 mutex_unlock(&dev_priv->psr.lock);
2026 return;
2027 }
2028
2029 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2030 pipe = to_intel_crtc(crtc)->pipe;
2031 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2032
2033 /*
2034 * On Haswell sprite plane updates don't result in a psr invalidating
2035 * signal in the hardware. Which means we need to manually fake this in
2036 * software for all flushes, not just when we've seen a preceding
2037 * invalidation through frontbuffer rendering.
2038 */
2039 if (IS_HASWELL(dev) &&
2040 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2041 intel_edp_psr_do_exit(dev);
2042
2043 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2044 schedule_delayed_work(&dev_priv->psr.work,
2045 msecs_to_jiffies(100));
2046 mutex_unlock(&dev_priv->psr.lock);
2047 }
2048
2049 void intel_edp_psr_init(struct drm_device *dev)
2050 {
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052
2053 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2054 mutex_init(&dev_priv->psr.lock);
2055 }
2056
2057 static void intel_disable_dp(struct intel_encoder *encoder)
2058 {
2059 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2060 enum port port = dp_to_dig_port(intel_dp)->port;
2061 struct drm_device *dev = encoder->base.dev;
2062
2063 /* Make sure the panel is off before trying to change the mode. But also
2064 * ensure that we have vdd while we switch off the panel. */
2065 intel_edp_panel_vdd_on(intel_dp);
2066 intel_edp_backlight_off(intel_dp);
2067 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2068 intel_edp_panel_off(intel_dp);
2069
2070 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2071 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2072 intel_dp_link_down(intel_dp);
2073 }
2074
2075 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2076 {
2077 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2078 enum port port = dp_to_dig_port(intel_dp)->port;
2079
2080 if (port != PORT_A)
2081 return;
2082
2083 intel_dp_link_down(intel_dp);
2084 ironlake_edp_pll_off(intel_dp);
2085 }
2086
2087 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2088 {
2089 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2090
2091 intel_dp_link_down(intel_dp);
2092 }
2093
2094 static void chv_post_disable_dp(struct intel_encoder *encoder)
2095 {
2096 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2097 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2098 struct drm_device *dev = encoder->base.dev;
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2100 struct intel_crtc *intel_crtc =
2101 to_intel_crtc(encoder->base.crtc);
2102 enum dpio_channel ch = vlv_dport_to_channel(dport);
2103 enum pipe pipe = intel_crtc->pipe;
2104 u32 val;
2105
2106 intel_dp_link_down(intel_dp);
2107
2108 mutex_lock(&dev_priv->dpio_lock);
2109
2110 /* Propagate soft reset to data lane reset */
2111 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2112 val |= CHV_PCS_REQ_SOFTRESET_EN;
2113 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2114
2115 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2116 val |= CHV_PCS_REQ_SOFTRESET_EN;
2117 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2118
2119 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2120 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2121 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2122
2123 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2124 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2125 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2126
2127 mutex_unlock(&dev_priv->dpio_lock);
2128 }
2129
2130 static void intel_enable_dp(struct intel_encoder *encoder)
2131 {
2132 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2133 struct drm_device *dev = encoder->base.dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2136
2137 if (WARN_ON(dp_reg & DP_PORT_EN))
2138 return;
2139
2140 intel_edp_panel_vdd_on(intel_dp);
2141 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2142 intel_dp_start_link_train(intel_dp);
2143 intel_edp_panel_on(intel_dp);
2144 intel_edp_panel_vdd_off(intel_dp, true);
2145 intel_dp_complete_link_train(intel_dp);
2146 intel_dp_stop_link_train(intel_dp);
2147 }
2148
2149 static void g4x_enable_dp(struct intel_encoder *encoder)
2150 {
2151 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2152
2153 intel_enable_dp(encoder);
2154 intel_edp_backlight_on(intel_dp);
2155 }
2156
2157 static void vlv_enable_dp(struct intel_encoder *encoder)
2158 {
2159 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2160
2161 intel_edp_backlight_on(intel_dp);
2162 }
2163
2164 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2165 {
2166 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2167 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2168
2169 intel_dp_prepare(encoder);
2170
2171 /* Only ilk+ has port A */
2172 if (dport->port == PORT_A) {
2173 ironlake_set_pll_cpu_edp(intel_dp);
2174 ironlake_edp_pll_on(intel_dp);
2175 }
2176 }
2177
2178 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2179 {
2180 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2181 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2182 struct drm_device *dev = encoder->base.dev;
2183 struct drm_i915_private *dev_priv = dev->dev_private;
2184 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2185 enum dpio_channel port = vlv_dport_to_channel(dport);
2186 int pipe = intel_crtc->pipe;
2187 struct edp_power_seq power_seq;
2188 u32 val;
2189
2190 mutex_lock(&dev_priv->dpio_lock);
2191
2192 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2193 val = 0;
2194 if (pipe)
2195 val |= (1<<21);
2196 else
2197 val &= ~(1<<21);
2198 val |= 0x001000c4;
2199 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2200 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2201 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2202
2203 mutex_unlock(&dev_priv->dpio_lock);
2204
2205 if (is_edp(intel_dp)) {
2206 /* init power sequencer on this pipe and port */
2207 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2208 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2209 &power_seq);
2210 }
2211
2212 intel_enable_dp(encoder);
2213
2214 vlv_wait_port_ready(dev_priv, dport);
2215 }
2216
2217 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2218 {
2219 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2220 struct drm_device *dev = encoder->base.dev;
2221 struct drm_i915_private *dev_priv = dev->dev_private;
2222 struct intel_crtc *intel_crtc =
2223 to_intel_crtc(encoder->base.crtc);
2224 enum dpio_channel port = vlv_dport_to_channel(dport);
2225 int pipe = intel_crtc->pipe;
2226
2227 intel_dp_prepare(encoder);
2228
2229 /* Program Tx lane resets to default */
2230 mutex_lock(&dev_priv->dpio_lock);
2231 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2232 DPIO_PCS_TX_LANE2_RESET |
2233 DPIO_PCS_TX_LANE1_RESET);
2234 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2235 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2236 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2237 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2238 DPIO_PCS_CLK_SOFT_RESET);
2239
2240 /* Fix up inter-pair skew failure */
2241 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2242 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2243 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2244 mutex_unlock(&dev_priv->dpio_lock);
2245 }
2246
2247 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2248 {
2249 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2250 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2251 struct drm_device *dev = encoder->base.dev;
2252 struct drm_i915_private *dev_priv = dev->dev_private;
2253 struct edp_power_seq power_seq;
2254 struct intel_crtc *intel_crtc =
2255 to_intel_crtc(encoder->base.crtc);
2256 enum dpio_channel ch = vlv_dport_to_channel(dport);
2257 int pipe = intel_crtc->pipe;
2258 int data, i;
2259 u32 val;
2260
2261 mutex_lock(&dev_priv->dpio_lock);
2262
2263 /* Deassert soft data lane reset*/
2264 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2265 val |= CHV_PCS_REQ_SOFTRESET_EN;
2266 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2267
2268 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2269 val |= CHV_PCS_REQ_SOFTRESET_EN;
2270 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2271
2272 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2273 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2274 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2275
2276 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2277 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2278 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2279
2280 /* Program Tx lane latency optimal setting*/
2281 for (i = 0; i < 4; i++) {
2282 /* Set the latency optimal bit */
2283 data = (i == 1) ? 0x0 : 0x6;
2284 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2285 data << DPIO_FRC_LATENCY_SHFIT);
2286
2287 /* Set the upar bit */
2288 data = (i == 1) ? 0x0 : 0x1;
2289 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2290 data << DPIO_UPAR_SHIFT);
2291 }
2292
2293 /* Data lane stagger programming */
2294 /* FIXME: Fix up value only after power analysis */
2295
2296 mutex_unlock(&dev_priv->dpio_lock);
2297
2298 if (is_edp(intel_dp)) {
2299 /* init power sequencer on this pipe and port */
2300 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2301 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2302 &power_seq);
2303 }
2304
2305 intel_enable_dp(encoder);
2306
2307 vlv_wait_port_ready(dev_priv, dport);
2308 }
2309
2310 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2311 {
2312 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2313 struct drm_device *dev = encoder->base.dev;
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct intel_crtc *intel_crtc =
2316 to_intel_crtc(encoder->base.crtc);
2317 enum dpio_channel ch = vlv_dport_to_channel(dport);
2318 enum pipe pipe = intel_crtc->pipe;
2319 u32 val;
2320
2321 intel_dp_prepare(encoder);
2322
2323 mutex_lock(&dev_priv->dpio_lock);
2324
2325 /* program left/right clock distribution */
2326 if (pipe != PIPE_B) {
2327 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2328 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2329 if (ch == DPIO_CH0)
2330 val |= CHV_BUFLEFTENA1_FORCE;
2331 if (ch == DPIO_CH1)
2332 val |= CHV_BUFRIGHTENA1_FORCE;
2333 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2334 } else {
2335 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2336 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2337 if (ch == DPIO_CH0)
2338 val |= CHV_BUFLEFTENA2_FORCE;
2339 if (ch == DPIO_CH1)
2340 val |= CHV_BUFRIGHTENA2_FORCE;
2341 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2342 }
2343
2344 /* program clock channel usage */
2345 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2346 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2347 if (pipe != PIPE_B)
2348 val &= ~CHV_PCS_USEDCLKCHANNEL;
2349 else
2350 val |= CHV_PCS_USEDCLKCHANNEL;
2351 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2352
2353 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2354 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2355 if (pipe != PIPE_B)
2356 val &= ~CHV_PCS_USEDCLKCHANNEL;
2357 else
2358 val |= CHV_PCS_USEDCLKCHANNEL;
2359 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2360
2361 /*
2362 * This a a bit weird since generally CL
2363 * matches the pipe, but here we need to
2364 * pick the CL based on the port.
2365 */
2366 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2367 if (pipe != PIPE_B)
2368 val &= ~CHV_CMN_USEDCLKCHANNEL;
2369 else
2370 val |= CHV_CMN_USEDCLKCHANNEL;
2371 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2372
2373 mutex_unlock(&dev_priv->dpio_lock);
2374 }
2375
2376 /*
2377 * Native read with retry for link status and receiver capability reads for
2378 * cases where the sink may still be asleep.
2379 *
2380 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2381 * supposed to retry 3 times per the spec.
2382 */
2383 static ssize_t
2384 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2385 void *buffer, size_t size)
2386 {
2387 ssize_t ret;
2388 int i;
2389
2390 for (i = 0; i < 3; i++) {
2391 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2392 if (ret == size)
2393 return ret;
2394 msleep(1);
2395 }
2396
2397 return ret;
2398 }
2399
2400 /*
2401 * Fetch AUX CH registers 0x202 - 0x207 which contain
2402 * link status information
2403 */
2404 static bool
2405 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2406 {
2407 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2408 DP_LANE0_1_STATUS,
2409 link_status,
2410 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2411 }
2412
2413 /* These are source-specific values. */
2414 static uint8_t
2415 intel_dp_voltage_max(struct intel_dp *intel_dp)
2416 {
2417 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2418 enum port port = dp_to_dig_port(intel_dp)->port;
2419
2420 if (IS_VALLEYVIEW(dev))
2421 return DP_TRAIN_VOLTAGE_SWING_1200;
2422 else if (IS_GEN7(dev) && port == PORT_A)
2423 return DP_TRAIN_VOLTAGE_SWING_800;
2424 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2425 return DP_TRAIN_VOLTAGE_SWING_1200;
2426 else
2427 return DP_TRAIN_VOLTAGE_SWING_800;
2428 }
2429
2430 static uint8_t
2431 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2432 {
2433 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2434 enum port port = dp_to_dig_port(intel_dp)->port;
2435
2436 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2437 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2438 case DP_TRAIN_VOLTAGE_SWING_400:
2439 return DP_TRAIN_PRE_EMPHASIS_9_5;
2440 case DP_TRAIN_VOLTAGE_SWING_600:
2441 return DP_TRAIN_PRE_EMPHASIS_6;
2442 case DP_TRAIN_VOLTAGE_SWING_800:
2443 return DP_TRAIN_PRE_EMPHASIS_3_5;
2444 case DP_TRAIN_VOLTAGE_SWING_1200:
2445 default:
2446 return DP_TRAIN_PRE_EMPHASIS_0;
2447 }
2448 } else if (IS_VALLEYVIEW(dev)) {
2449 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2450 case DP_TRAIN_VOLTAGE_SWING_400:
2451 return DP_TRAIN_PRE_EMPHASIS_9_5;
2452 case DP_TRAIN_VOLTAGE_SWING_600:
2453 return DP_TRAIN_PRE_EMPHASIS_6;
2454 case DP_TRAIN_VOLTAGE_SWING_800:
2455 return DP_TRAIN_PRE_EMPHASIS_3_5;
2456 case DP_TRAIN_VOLTAGE_SWING_1200:
2457 default:
2458 return DP_TRAIN_PRE_EMPHASIS_0;
2459 }
2460 } else if (IS_GEN7(dev) && port == PORT_A) {
2461 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2462 case DP_TRAIN_VOLTAGE_SWING_400:
2463 return DP_TRAIN_PRE_EMPHASIS_6;
2464 case DP_TRAIN_VOLTAGE_SWING_600:
2465 case DP_TRAIN_VOLTAGE_SWING_800:
2466 return DP_TRAIN_PRE_EMPHASIS_3_5;
2467 default:
2468 return DP_TRAIN_PRE_EMPHASIS_0;
2469 }
2470 } else {
2471 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2472 case DP_TRAIN_VOLTAGE_SWING_400:
2473 return DP_TRAIN_PRE_EMPHASIS_6;
2474 case DP_TRAIN_VOLTAGE_SWING_600:
2475 return DP_TRAIN_PRE_EMPHASIS_6;
2476 case DP_TRAIN_VOLTAGE_SWING_800:
2477 return DP_TRAIN_PRE_EMPHASIS_3_5;
2478 case DP_TRAIN_VOLTAGE_SWING_1200:
2479 default:
2480 return DP_TRAIN_PRE_EMPHASIS_0;
2481 }
2482 }
2483 }
2484
2485 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2486 {
2487 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2489 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2490 struct intel_crtc *intel_crtc =
2491 to_intel_crtc(dport->base.base.crtc);
2492 unsigned long demph_reg_value, preemph_reg_value,
2493 uniqtranscale_reg_value;
2494 uint8_t train_set = intel_dp->train_set[0];
2495 enum dpio_channel port = vlv_dport_to_channel(dport);
2496 int pipe = intel_crtc->pipe;
2497
2498 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2499 case DP_TRAIN_PRE_EMPHASIS_0:
2500 preemph_reg_value = 0x0004000;
2501 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2502 case DP_TRAIN_VOLTAGE_SWING_400:
2503 demph_reg_value = 0x2B405555;
2504 uniqtranscale_reg_value = 0x552AB83A;
2505 break;
2506 case DP_TRAIN_VOLTAGE_SWING_600:
2507 demph_reg_value = 0x2B404040;
2508 uniqtranscale_reg_value = 0x5548B83A;
2509 break;
2510 case DP_TRAIN_VOLTAGE_SWING_800:
2511 demph_reg_value = 0x2B245555;
2512 uniqtranscale_reg_value = 0x5560B83A;
2513 break;
2514 case DP_TRAIN_VOLTAGE_SWING_1200:
2515 demph_reg_value = 0x2B405555;
2516 uniqtranscale_reg_value = 0x5598DA3A;
2517 break;
2518 default:
2519 return 0;
2520 }
2521 break;
2522 case DP_TRAIN_PRE_EMPHASIS_3_5:
2523 preemph_reg_value = 0x0002000;
2524 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2525 case DP_TRAIN_VOLTAGE_SWING_400:
2526 demph_reg_value = 0x2B404040;
2527 uniqtranscale_reg_value = 0x5552B83A;
2528 break;
2529 case DP_TRAIN_VOLTAGE_SWING_600:
2530 demph_reg_value = 0x2B404848;
2531 uniqtranscale_reg_value = 0x5580B83A;
2532 break;
2533 case DP_TRAIN_VOLTAGE_SWING_800:
2534 demph_reg_value = 0x2B404040;
2535 uniqtranscale_reg_value = 0x55ADDA3A;
2536 break;
2537 default:
2538 return 0;
2539 }
2540 break;
2541 case DP_TRAIN_PRE_EMPHASIS_6:
2542 preemph_reg_value = 0x0000000;
2543 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2544 case DP_TRAIN_VOLTAGE_SWING_400:
2545 demph_reg_value = 0x2B305555;
2546 uniqtranscale_reg_value = 0x5570B83A;
2547 break;
2548 case DP_TRAIN_VOLTAGE_SWING_600:
2549 demph_reg_value = 0x2B2B4040;
2550 uniqtranscale_reg_value = 0x55ADDA3A;
2551 break;
2552 default:
2553 return 0;
2554 }
2555 break;
2556 case DP_TRAIN_PRE_EMPHASIS_9_5:
2557 preemph_reg_value = 0x0006000;
2558 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2559 case DP_TRAIN_VOLTAGE_SWING_400:
2560 demph_reg_value = 0x1B405555;
2561 uniqtranscale_reg_value = 0x55ADDA3A;
2562 break;
2563 default:
2564 return 0;
2565 }
2566 break;
2567 default:
2568 return 0;
2569 }
2570
2571 mutex_lock(&dev_priv->dpio_lock);
2572 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2573 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2574 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2575 uniqtranscale_reg_value);
2576 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2577 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2578 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2579 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2580 mutex_unlock(&dev_priv->dpio_lock);
2581
2582 return 0;
2583 }
2584
2585 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2586 {
2587 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2590 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2591 u32 deemph_reg_value, margin_reg_value, val;
2592 uint8_t train_set = intel_dp->train_set[0];
2593 enum dpio_channel ch = vlv_dport_to_channel(dport);
2594 enum pipe pipe = intel_crtc->pipe;
2595 int i;
2596
2597 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2598 case DP_TRAIN_PRE_EMPHASIS_0:
2599 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2600 case DP_TRAIN_VOLTAGE_SWING_400:
2601 deemph_reg_value = 128;
2602 margin_reg_value = 52;
2603 break;
2604 case DP_TRAIN_VOLTAGE_SWING_600:
2605 deemph_reg_value = 128;
2606 margin_reg_value = 77;
2607 break;
2608 case DP_TRAIN_VOLTAGE_SWING_800:
2609 deemph_reg_value = 128;
2610 margin_reg_value = 102;
2611 break;
2612 case DP_TRAIN_VOLTAGE_SWING_1200:
2613 deemph_reg_value = 128;
2614 margin_reg_value = 154;
2615 /* FIXME extra to set for 1200 */
2616 break;
2617 default:
2618 return 0;
2619 }
2620 break;
2621 case DP_TRAIN_PRE_EMPHASIS_3_5:
2622 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2623 case DP_TRAIN_VOLTAGE_SWING_400:
2624 deemph_reg_value = 85;
2625 margin_reg_value = 78;
2626 break;
2627 case DP_TRAIN_VOLTAGE_SWING_600:
2628 deemph_reg_value = 85;
2629 margin_reg_value = 116;
2630 break;
2631 case DP_TRAIN_VOLTAGE_SWING_800:
2632 deemph_reg_value = 85;
2633 margin_reg_value = 154;
2634 break;
2635 default:
2636 return 0;
2637 }
2638 break;
2639 case DP_TRAIN_PRE_EMPHASIS_6:
2640 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2641 case DP_TRAIN_VOLTAGE_SWING_400:
2642 deemph_reg_value = 64;
2643 margin_reg_value = 104;
2644 break;
2645 case DP_TRAIN_VOLTAGE_SWING_600:
2646 deemph_reg_value = 64;
2647 margin_reg_value = 154;
2648 break;
2649 default:
2650 return 0;
2651 }
2652 break;
2653 case DP_TRAIN_PRE_EMPHASIS_9_5:
2654 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2655 case DP_TRAIN_VOLTAGE_SWING_400:
2656 deemph_reg_value = 43;
2657 margin_reg_value = 154;
2658 break;
2659 default:
2660 return 0;
2661 }
2662 break;
2663 default:
2664 return 0;
2665 }
2666
2667 mutex_lock(&dev_priv->dpio_lock);
2668
2669 /* Clear calc init */
2670 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2671 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2672 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2673
2674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2675 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2676 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2677
2678 /* Program swing deemph */
2679 for (i = 0; i < 4; i++) {
2680 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2681 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2682 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2683 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2684 }
2685
2686 /* Program swing margin */
2687 for (i = 0; i < 4; i++) {
2688 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2689 val &= ~DPIO_SWING_MARGIN000_MASK;
2690 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2691 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2692 }
2693
2694 /* Disable unique transition scale */
2695 for (i = 0; i < 4; i++) {
2696 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2697 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2698 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2699 }
2700
2701 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2702 == DP_TRAIN_PRE_EMPHASIS_0) &&
2703 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2704 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2705
2706 /*
2707 * The document said it needs to set bit 27 for ch0 and bit 26
2708 * for ch1. Might be a typo in the doc.
2709 * For now, for this unique transition scale selection, set bit
2710 * 27 for ch0 and ch1.
2711 */
2712 for (i = 0; i < 4; i++) {
2713 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2714 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2715 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2716 }
2717
2718 for (i = 0; i < 4; i++) {
2719 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2720 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2721 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2722 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2723 }
2724 }
2725
2726 /* Start swing calculation */
2727 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2728 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2729 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2730
2731 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2732 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2733 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2734
2735 /* LRC Bypass */
2736 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2737 val |= DPIO_LRC_BYPASS;
2738 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2739
2740 mutex_unlock(&dev_priv->dpio_lock);
2741
2742 return 0;
2743 }
2744
2745 static void
2746 intel_get_adjust_train(struct intel_dp *intel_dp,
2747 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2748 {
2749 uint8_t v = 0;
2750 uint8_t p = 0;
2751 int lane;
2752 uint8_t voltage_max;
2753 uint8_t preemph_max;
2754
2755 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2756 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2757 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2758
2759 if (this_v > v)
2760 v = this_v;
2761 if (this_p > p)
2762 p = this_p;
2763 }
2764
2765 voltage_max = intel_dp_voltage_max(intel_dp);
2766 if (v >= voltage_max)
2767 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2768
2769 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2770 if (p >= preemph_max)
2771 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2772
2773 for (lane = 0; lane < 4; lane++)
2774 intel_dp->train_set[lane] = v | p;
2775 }
2776
2777 static uint32_t
2778 intel_gen4_signal_levels(uint8_t train_set)
2779 {
2780 uint32_t signal_levels = 0;
2781
2782 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2783 case DP_TRAIN_VOLTAGE_SWING_400:
2784 default:
2785 signal_levels |= DP_VOLTAGE_0_4;
2786 break;
2787 case DP_TRAIN_VOLTAGE_SWING_600:
2788 signal_levels |= DP_VOLTAGE_0_6;
2789 break;
2790 case DP_TRAIN_VOLTAGE_SWING_800:
2791 signal_levels |= DP_VOLTAGE_0_8;
2792 break;
2793 case DP_TRAIN_VOLTAGE_SWING_1200:
2794 signal_levels |= DP_VOLTAGE_1_2;
2795 break;
2796 }
2797 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2798 case DP_TRAIN_PRE_EMPHASIS_0:
2799 default:
2800 signal_levels |= DP_PRE_EMPHASIS_0;
2801 break;
2802 case DP_TRAIN_PRE_EMPHASIS_3_5:
2803 signal_levels |= DP_PRE_EMPHASIS_3_5;
2804 break;
2805 case DP_TRAIN_PRE_EMPHASIS_6:
2806 signal_levels |= DP_PRE_EMPHASIS_6;
2807 break;
2808 case DP_TRAIN_PRE_EMPHASIS_9_5:
2809 signal_levels |= DP_PRE_EMPHASIS_9_5;
2810 break;
2811 }
2812 return signal_levels;
2813 }
2814
2815 /* Gen6's DP voltage swing and pre-emphasis control */
2816 static uint32_t
2817 intel_gen6_edp_signal_levels(uint8_t train_set)
2818 {
2819 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2820 DP_TRAIN_PRE_EMPHASIS_MASK);
2821 switch (signal_levels) {
2822 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2823 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2824 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2825 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2826 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2827 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2828 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2829 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2830 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2831 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2832 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2833 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2834 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2835 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2836 default:
2837 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2838 "0x%x\n", signal_levels);
2839 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2840 }
2841 }
2842
2843 /* Gen7's DP voltage swing and pre-emphasis control */
2844 static uint32_t
2845 intel_gen7_edp_signal_levels(uint8_t train_set)
2846 {
2847 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2848 DP_TRAIN_PRE_EMPHASIS_MASK);
2849 switch (signal_levels) {
2850 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2851 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2852 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2853 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2854 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2855 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2856
2857 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2858 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2859 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2860 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2861
2862 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2863 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2864 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2865 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2866
2867 default:
2868 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2869 "0x%x\n", signal_levels);
2870 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2871 }
2872 }
2873
2874 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2875 static uint32_t
2876 intel_hsw_signal_levels(uint8_t train_set)
2877 {
2878 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2879 DP_TRAIN_PRE_EMPHASIS_MASK);
2880 switch (signal_levels) {
2881 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2882 return DDI_BUF_EMP_400MV_0DB_HSW;
2883 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2884 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2885 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2886 return DDI_BUF_EMP_400MV_6DB_HSW;
2887 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2888 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2889
2890 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2891 return DDI_BUF_EMP_600MV_0DB_HSW;
2892 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2893 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2894 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2895 return DDI_BUF_EMP_600MV_6DB_HSW;
2896
2897 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2898 return DDI_BUF_EMP_800MV_0DB_HSW;
2899 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2900 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2901 default:
2902 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2903 "0x%x\n", signal_levels);
2904 return DDI_BUF_EMP_400MV_0DB_HSW;
2905 }
2906 }
2907
2908 /* Properly updates "DP" with the correct signal levels. */
2909 static void
2910 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2911 {
2912 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2913 enum port port = intel_dig_port->port;
2914 struct drm_device *dev = intel_dig_port->base.base.dev;
2915 uint32_t signal_levels, mask;
2916 uint8_t train_set = intel_dp->train_set[0];
2917
2918 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2919 signal_levels = intel_hsw_signal_levels(train_set);
2920 mask = DDI_BUF_EMP_MASK;
2921 } else if (IS_CHERRYVIEW(dev)) {
2922 signal_levels = intel_chv_signal_levels(intel_dp);
2923 mask = 0;
2924 } else if (IS_VALLEYVIEW(dev)) {
2925 signal_levels = intel_vlv_signal_levels(intel_dp);
2926 mask = 0;
2927 } else if (IS_GEN7(dev) && port == PORT_A) {
2928 signal_levels = intel_gen7_edp_signal_levels(train_set);
2929 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2930 } else if (IS_GEN6(dev) && port == PORT_A) {
2931 signal_levels = intel_gen6_edp_signal_levels(train_set);
2932 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2933 } else {
2934 signal_levels = intel_gen4_signal_levels(train_set);
2935 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2936 }
2937
2938 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2939
2940 *DP = (*DP & ~mask) | signal_levels;
2941 }
2942
2943 static bool
2944 intel_dp_set_link_train(struct intel_dp *intel_dp,
2945 uint32_t *DP,
2946 uint8_t dp_train_pat)
2947 {
2948 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2949 struct drm_device *dev = intel_dig_port->base.base.dev;
2950 struct drm_i915_private *dev_priv = dev->dev_private;
2951 enum port port = intel_dig_port->port;
2952 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2953 int ret, len;
2954
2955 if (HAS_DDI(dev)) {
2956 uint32_t temp = I915_READ(DP_TP_CTL(port));
2957
2958 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2959 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2960 else
2961 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2962
2963 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2964 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2965 case DP_TRAINING_PATTERN_DISABLE:
2966 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2967
2968 break;
2969 case DP_TRAINING_PATTERN_1:
2970 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2971 break;
2972 case DP_TRAINING_PATTERN_2:
2973 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2974 break;
2975 case DP_TRAINING_PATTERN_3:
2976 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2977 break;
2978 }
2979 I915_WRITE(DP_TP_CTL(port), temp);
2980
2981 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2982 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2983
2984 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2985 case DP_TRAINING_PATTERN_DISABLE:
2986 *DP |= DP_LINK_TRAIN_OFF_CPT;
2987 break;
2988 case DP_TRAINING_PATTERN_1:
2989 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2990 break;
2991 case DP_TRAINING_PATTERN_2:
2992 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2993 break;
2994 case DP_TRAINING_PATTERN_3:
2995 DRM_ERROR("DP training pattern 3 not supported\n");
2996 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2997 break;
2998 }
2999
3000 } else {
3001 if (IS_CHERRYVIEW(dev))
3002 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3003 else
3004 *DP &= ~DP_LINK_TRAIN_MASK;
3005
3006 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3007 case DP_TRAINING_PATTERN_DISABLE:
3008 *DP |= DP_LINK_TRAIN_OFF;
3009 break;
3010 case DP_TRAINING_PATTERN_1:
3011 *DP |= DP_LINK_TRAIN_PAT_1;
3012 break;
3013 case DP_TRAINING_PATTERN_2:
3014 *DP |= DP_LINK_TRAIN_PAT_2;
3015 break;
3016 case DP_TRAINING_PATTERN_3:
3017 if (IS_CHERRYVIEW(dev)) {
3018 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3019 } else {
3020 DRM_ERROR("DP training pattern 3 not supported\n");
3021 *DP |= DP_LINK_TRAIN_PAT_2;
3022 }
3023 break;
3024 }
3025 }
3026
3027 I915_WRITE(intel_dp->output_reg, *DP);
3028 POSTING_READ(intel_dp->output_reg);
3029
3030 buf[0] = dp_train_pat;
3031 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3032 DP_TRAINING_PATTERN_DISABLE) {
3033 /* don't write DP_TRAINING_LANEx_SET on disable */
3034 len = 1;
3035 } else {
3036 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3037 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3038 len = intel_dp->lane_count + 1;
3039 }
3040
3041 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3042 buf, len);
3043
3044 return ret == len;
3045 }
3046
3047 static bool
3048 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3049 uint8_t dp_train_pat)
3050 {
3051 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3052 intel_dp_set_signal_levels(intel_dp, DP);
3053 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3054 }
3055
3056 static bool
3057 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3058 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3059 {
3060 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3061 struct drm_device *dev = intel_dig_port->base.base.dev;
3062 struct drm_i915_private *dev_priv = dev->dev_private;
3063 int ret;
3064
3065 intel_get_adjust_train(intel_dp, link_status);
3066 intel_dp_set_signal_levels(intel_dp, DP);
3067
3068 I915_WRITE(intel_dp->output_reg, *DP);
3069 POSTING_READ(intel_dp->output_reg);
3070
3071 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3072 intel_dp->train_set, intel_dp->lane_count);
3073
3074 return ret == intel_dp->lane_count;
3075 }
3076
3077 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3078 {
3079 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3080 struct drm_device *dev = intel_dig_port->base.base.dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 enum port port = intel_dig_port->port;
3083 uint32_t val;
3084
3085 if (!HAS_DDI(dev))
3086 return;
3087
3088 val = I915_READ(DP_TP_CTL(port));
3089 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3090 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3091 I915_WRITE(DP_TP_CTL(port), val);
3092
3093 /*
3094 * On PORT_A we can have only eDP in SST mode. There the only reason
3095 * we need to set idle transmission mode is to work around a HW issue
3096 * where we enable the pipe while not in idle link-training mode.
3097 * In this case there is requirement to wait for a minimum number of
3098 * idle patterns to be sent.
3099 */
3100 if (port == PORT_A)
3101 return;
3102
3103 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3104 1))
3105 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3106 }
3107
3108 /* Enable corresponding port and start training pattern 1 */
3109 void
3110 intel_dp_start_link_train(struct intel_dp *intel_dp)
3111 {
3112 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3113 struct drm_device *dev = encoder->dev;
3114 int i;
3115 uint8_t voltage;
3116 int voltage_tries, loop_tries;
3117 uint32_t DP = intel_dp->DP;
3118 uint8_t link_config[2];
3119
3120 if (HAS_DDI(dev))
3121 intel_ddi_prepare_link_retrain(encoder);
3122
3123 /* Write the link configuration data */
3124 link_config[0] = intel_dp->link_bw;
3125 link_config[1] = intel_dp->lane_count;
3126 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3127 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3128 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3129
3130 link_config[0] = 0;
3131 link_config[1] = DP_SET_ANSI_8B10B;
3132 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3133
3134 DP |= DP_PORT_EN;
3135
3136 /* clock recovery */
3137 if (!intel_dp_reset_link_train(intel_dp, &DP,
3138 DP_TRAINING_PATTERN_1 |
3139 DP_LINK_SCRAMBLING_DISABLE)) {
3140 DRM_ERROR("failed to enable link training\n");
3141 return;
3142 }
3143
3144 voltage = 0xff;
3145 voltage_tries = 0;
3146 loop_tries = 0;
3147 for (;;) {
3148 uint8_t link_status[DP_LINK_STATUS_SIZE];
3149
3150 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3151 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3152 DRM_ERROR("failed to get link status\n");
3153 break;
3154 }
3155
3156 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3157 DRM_DEBUG_KMS("clock recovery OK\n");
3158 break;
3159 }
3160
3161 /* Check to see if we've tried the max voltage */
3162 for (i = 0; i < intel_dp->lane_count; i++)
3163 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3164 break;
3165 if (i == intel_dp->lane_count) {
3166 ++loop_tries;
3167 if (loop_tries == 5) {
3168 DRM_ERROR("too many full retries, give up\n");
3169 break;
3170 }
3171 intel_dp_reset_link_train(intel_dp, &DP,
3172 DP_TRAINING_PATTERN_1 |
3173 DP_LINK_SCRAMBLING_DISABLE);
3174 voltage_tries = 0;
3175 continue;
3176 }
3177
3178 /* Check to see if we've tried the same voltage 5 times */
3179 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3180 ++voltage_tries;
3181 if (voltage_tries == 5) {
3182 DRM_ERROR("too many voltage retries, give up\n");
3183 break;
3184 }
3185 } else
3186 voltage_tries = 0;
3187 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3188
3189 /* Update training set as requested by target */
3190 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3191 DRM_ERROR("failed to update link training\n");
3192 break;
3193 }
3194 }
3195
3196 intel_dp->DP = DP;
3197 }
3198
3199 void
3200 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3201 {
3202 bool channel_eq = false;
3203 int tries, cr_tries;
3204 uint32_t DP = intel_dp->DP;
3205 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3206
3207 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3208 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3209 training_pattern = DP_TRAINING_PATTERN_3;
3210
3211 /* channel equalization */
3212 if (!intel_dp_set_link_train(intel_dp, &DP,
3213 training_pattern |
3214 DP_LINK_SCRAMBLING_DISABLE)) {
3215 DRM_ERROR("failed to start channel equalization\n");
3216 return;
3217 }
3218
3219 tries = 0;
3220 cr_tries = 0;
3221 channel_eq = false;
3222 for (;;) {
3223 uint8_t link_status[DP_LINK_STATUS_SIZE];
3224
3225 if (cr_tries > 5) {
3226 DRM_ERROR("failed to train DP, aborting\n");
3227 break;
3228 }
3229
3230 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3231 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3232 DRM_ERROR("failed to get link status\n");
3233 break;
3234 }
3235
3236 /* Make sure clock is still ok */
3237 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3238 intel_dp_start_link_train(intel_dp);
3239 intel_dp_set_link_train(intel_dp, &DP,
3240 training_pattern |
3241 DP_LINK_SCRAMBLING_DISABLE);
3242 cr_tries++;
3243 continue;
3244 }
3245
3246 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3247 channel_eq = true;
3248 break;
3249 }
3250
3251 /* Try 5 times, then try clock recovery if that fails */
3252 if (tries > 5) {
3253 intel_dp_link_down(intel_dp);
3254 intel_dp_start_link_train(intel_dp);
3255 intel_dp_set_link_train(intel_dp, &DP,
3256 training_pattern |
3257 DP_LINK_SCRAMBLING_DISABLE);
3258 tries = 0;
3259 cr_tries++;
3260 continue;
3261 }
3262
3263 /* Update training set as requested by target */
3264 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3265 DRM_ERROR("failed to update link training\n");
3266 break;
3267 }
3268 ++tries;
3269 }
3270
3271 intel_dp_set_idle_link_train(intel_dp);
3272
3273 intel_dp->DP = DP;
3274
3275 if (channel_eq)
3276 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3277
3278 }
3279
3280 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3281 {
3282 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3283 DP_TRAINING_PATTERN_DISABLE);
3284 }
3285
3286 static void
3287 intel_dp_link_down(struct intel_dp *intel_dp)
3288 {
3289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3290 enum port port = intel_dig_port->port;
3291 struct drm_device *dev = intel_dig_port->base.base.dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *intel_crtc =
3294 to_intel_crtc(intel_dig_port->base.base.crtc);
3295 uint32_t DP = intel_dp->DP;
3296
3297 if (WARN_ON(HAS_DDI(dev)))
3298 return;
3299
3300 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3301 return;
3302
3303 DRM_DEBUG_KMS("\n");
3304
3305 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3306 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3307 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3308 } else {
3309 if (IS_CHERRYVIEW(dev))
3310 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3311 else
3312 DP &= ~DP_LINK_TRAIN_MASK;
3313 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3314 }
3315 POSTING_READ(intel_dp->output_reg);
3316
3317 if (HAS_PCH_IBX(dev) &&
3318 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3319 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3320
3321 /* Hardware workaround: leaving our transcoder select
3322 * set to transcoder B while it's off will prevent the
3323 * corresponding HDMI output on transcoder A.
3324 *
3325 * Combine this with another hardware workaround:
3326 * transcoder select bit can only be cleared while the
3327 * port is enabled.
3328 */
3329 DP &= ~DP_PIPEB_SELECT;
3330 I915_WRITE(intel_dp->output_reg, DP);
3331
3332 /* Changes to enable or select take place the vblank
3333 * after being written.
3334 */
3335 if (WARN_ON(crtc == NULL)) {
3336 /* We should never try to disable a port without a crtc
3337 * attached. For paranoia keep the code around for a
3338 * bit. */
3339 POSTING_READ(intel_dp->output_reg);
3340 msleep(50);
3341 } else
3342 intel_wait_for_vblank(dev, intel_crtc->pipe);
3343 }
3344
3345 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3346 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3347 POSTING_READ(intel_dp->output_reg);
3348 msleep(intel_dp->panel_power_down_delay);
3349 }
3350
3351 static bool
3352 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3353 {
3354 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3355 struct drm_device *dev = dig_port->base.base.dev;
3356 struct drm_i915_private *dev_priv = dev->dev_private;
3357
3358 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3359
3360 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3361 sizeof(intel_dp->dpcd)) < 0)
3362 return false; /* aux transfer failed */
3363
3364 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3365 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3366 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3367
3368 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3369 return false; /* DPCD not present */
3370
3371 /* Check if the panel supports PSR */
3372 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3373 if (is_edp(intel_dp)) {
3374 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3375 intel_dp->psr_dpcd,
3376 sizeof(intel_dp->psr_dpcd));
3377 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3378 dev_priv->psr.sink_support = true;
3379 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3380 }
3381 }
3382
3383 /* Training Pattern 3 support */
3384 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3385 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3386 intel_dp->use_tps3 = true;
3387 DRM_DEBUG_KMS("Displayport TPS3 supported");
3388 } else
3389 intel_dp->use_tps3 = false;
3390
3391 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3392 DP_DWN_STRM_PORT_PRESENT))
3393 return true; /* native DP sink */
3394
3395 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3396 return true; /* no per-port downstream info */
3397
3398 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3399 intel_dp->downstream_ports,
3400 DP_MAX_DOWNSTREAM_PORTS) < 0)
3401 return false; /* downstream port status fetch failed */
3402
3403 return true;
3404 }
3405
3406 static void
3407 intel_dp_probe_oui(struct intel_dp *intel_dp)
3408 {
3409 u8 buf[3];
3410
3411 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3412 return;
3413
3414 intel_edp_panel_vdd_on(intel_dp);
3415
3416 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3417 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3418 buf[0], buf[1], buf[2]);
3419
3420 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3421 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3422 buf[0], buf[1], buf[2]);
3423
3424 intel_edp_panel_vdd_off(intel_dp, false);
3425 }
3426
3427 static bool
3428 intel_dp_probe_mst(struct intel_dp *intel_dp)
3429 {
3430 u8 buf[1];
3431
3432 if (!intel_dp->can_mst)
3433 return false;
3434
3435 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3436 return false;
3437
3438 intel_edp_panel_vdd_on(intel_dp);
3439 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3440 if (buf[0] & DP_MST_CAP) {
3441 DRM_DEBUG_KMS("Sink is MST capable\n");
3442 intel_dp->is_mst = true;
3443 } else {
3444 DRM_DEBUG_KMS("Sink is not MST capable\n");
3445 intel_dp->is_mst = false;
3446 }
3447 }
3448 intel_edp_panel_vdd_off(intel_dp, false);
3449
3450 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3451 return intel_dp->is_mst;
3452 }
3453
3454 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3455 {
3456 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3457 struct drm_device *dev = intel_dig_port->base.base.dev;
3458 struct intel_crtc *intel_crtc =
3459 to_intel_crtc(intel_dig_port->base.base.crtc);
3460 u8 buf[1];
3461
3462 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3463 return -EAGAIN;
3464
3465 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3466 return -ENOTTY;
3467
3468 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3469 DP_TEST_SINK_START) < 0)
3470 return -EAGAIN;
3471
3472 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3473 intel_wait_for_vblank(dev, intel_crtc->pipe);
3474 intel_wait_for_vblank(dev, intel_crtc->pipe);
3475
3476 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3477 return -EAGAIN;
3478
3479 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3480 return 0;
3481 }
3482
3483 static bool
3484 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3485 {
3486 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3487 DP_DEVICE_SERVICE_IRQ_VECTOR,
3488 sink_irq_vector, 1) == 1;
3489 }
3490
3491 static bool
3492 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3493 {
3494 int ret;
3495
3496 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3497 DP_SINK_COUNT_ESI,
3498 sink_irq_vector, 14);
3499 if (ret != 14)
3500 return false;
3501
3502 return true;
3503 }
3504
3505 static void
3506 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3507 {
3508 /* NAK by default */
3509 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3510 }
3511
3512 static int
3513 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3514 {
3515 bool bret;
3516
3517 if (intel_dp->is_mst) {
3518 u8 esi[16] = { 0 };
3519 int ret = 0;
3520 int retry;
3521 bool handled;
3522 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3523 go_again:
3524 if (bret == true) {
3525
3526 /* check link status - esi[10] = 0x200c */
3527 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3528 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3529 intel_dp_start_link_train(intel_dp);
3530 intel_dp_complete_link_train(intel_dp);
3531 intel_dp_stop_link_train(intel_dp);
3532 }
3533
3534 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3535 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3536
3537 if (handled) {
3538 for (retry = 0; retry < 3; retry++) {
3539 int wret;
3540 wret = drm_dp_dpcd_write(&intel_dp->aux,
3541 DP_SINK_COUNT_ESI+1,
3542 &esi[1], 3);
3543 if (wret == 3) {
3544 break;
3545 }
3546 }
3547
3548 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3549 if (bret == true) {
3550 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3551 goto go_again;
3552 }
3553 } else
3554 ret = 0;
3555
3556 return ret;
3557 } else {
3558 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3559 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3560 intel_dp->is_mst = false;
3561 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3562 /* send a hotplug event */
3563 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3564 }
3565 }
3566 return -EINVAL;
3567 }
3568
3569 /*
3570 * According to DP spec
3571 * 5.1.2:
3572 * 1. Read DPCD
3573 * 2. Configure link according to Receiver Capabilities
3574 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3575 * 4. Check link status on receipt of hot-plug interrupt
3576 */
3577 void
3578 intel_dp_check_link_status(struct intel_dp *intel_dp)
3579 {
3580 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3581 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3582 u8 sink_irq_vector;
3583 u8 link_status[DP_LINK_STATUS_SIZE];
3584
3585 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3586
3587 if (!intel_encoder->connectors_active)
3588 return;
3589
3590 if (WARN_ON(!intel_encoder->base.crtc))
3591 return;
3592
3593 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3594 return;
3595
3596 /* Try to read receiver status if the link appears to be up */
3597 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3598 return;
3599 }
3600
3601 /* Now read the DPCD to see if it's actually running */
3602 if (!intel_dp_get_dpcd(intel_dp)) {
3603 return;
3604 }
3605
3606 /* Try to read the source of the interrupt */
3607 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3608 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3609 /* Clear interrupt source */
3610 drm_dp_dpcd_writeb(&intel_dp->aux,
3611 DP_DEVICE_SERVICE_IRQ_VECTOR,
3612 sink_irq_vector);
3613
3614 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3615 intel_dp_handle_test_request(intel_dp);
3616 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3617 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3618 }
3619
3620 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3621 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3622 intel_encoder->base.name);
3623 intel_dp_start_link_train(intel_dp);
3624 intel_dp_complete_link_train(intel_dp);
3625 intel_dp_stop_link_train(intel_dp);
3626 }
3627 }
3628
3629 /* XXX this is probably wrong for multiple downstream ports */
3630 static enum drm_connector_status
3631 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3632 {
3633 uint8_t *dpcd = intel_dp->dpcd;
3634 uint8_t type;
3635
3636 if (!intel_dp_get_dpcd(intel_dp))
3637 return connector_status_disconnected;
3638
3639 /* if there's no downstream port, we're done */
3640 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3641 return connector_status_connected;
3642
3643 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3644 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3645 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3646 uint8_t reg;
3647
3648 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3649 &reg, 1) < 0)
3650 return connector_status_unknown;
3651
3652 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3653 : connector_status_disconnected;
3654 }
3655
3656 /* If no HPD, poke DDC gently */
3657 if (drm_probe_ddc(&intel_dp->aux.ddc))
3658 return connector_status_connected;
3659
3660 /* Well we tried, say unknown for unreliable port types */
3661 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3662 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3663 if (type == DP_DS_PORT_TYPE_VGA ||
3664 type == DP_DS_PORT_TYPE_NON_EDID)
3665 return connector_status_unknown;
3666 } else {
3667 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3668 DP_DWN_STRM_PORT_TYPE_MASK;
3669 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3670 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3671 return connector_status_unknown;
3672 }
3673
3674 /* Anything else is out of spec, warn and ignore */
3675 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3676 return connector_status_disconnected;
3677 }
3678
3679 static enum drm_connector_status
3680 ironlake_dp_detect(struct intel_dp *intel_dp)
3681 {
3682 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3683 struct drm_i915_private *dev_priv = dev->dev_private;
3684 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3685 enum drm_connector_status status;
3686
3687 /* Can't disconnect eDP, but you can close the lid... */
3688 if (is_edp(intel_dp)) {
3689 status = intel_panel_detect(dev);
3690 if (status == connector_status_unknown)
3691 status = connector_status_connected;
3692 return status;
3693 }
3694
3695 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3696 return connector_status_disconnected;
3697
3698 return intel_dp_detect_dpcd(intel_dp);
3699 }
3700
3701 static enum drm_connector_status
3702 g4x_dp_detect(struct intel_dp *intel_dp)
3703 {
3704 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3705 struct drm_i915_private *dev_priv = dev->dev_private;
3706 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3707 uint32_t bit;
3708
3709 /* Can't disconnect eDP, but you can close the lid... */
3710 if (is_edp(intel_dp)) {
3711 enum drm_connector_status status;
3712
3713 status = intel_panel_detect(dev);
3714 if (status == connector_status_unknown)
3715 status = connector_status_connected;
3716 return status;
3717 }
3718
3719 if (IS_VALLEYVIEW(dev)) {
3720 switch (intel_dig_port->port) {
3721 case PORT_B:
3722 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3723 break;
3724 case PORT_C:
3725 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3726 break;
3727 case PORT_D:
3728 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3729 break;
3730 default:
3731 return connector_status_unknown;
3732 }
3733 } else {
3734 switch (intel_dig_port->port) {
3735 case PORT_B:
3736 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3737 break;
3738 case PORT_C:
3739 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3740 break;
3741 case PORT_D:
3742 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3743 break;
3744 default:
3745 return connector_status_unknown;
3746 }
3747 }
3748
3749 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3750 return connector_status_disconnected;
3751
3752 return intel_dp_detect_dpcd(intel_dp);
3753 }
3754
3755 static struct edid *
3756 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3757 {
3758 struct intel_connector *intel_connector = to_intel_connector(connector);
3759
3760 /* use cached edid if we have one */
3761 if (intel_connector->edid) {
3762 /* invalid edid */
3763 if (IS_ERR(intel_connector->edid))
3764 return NULL;
3765
3766 return drm_edid_duplicate(intel_connector->edid);
3767 }
3768
3769 return drm_get_edid(connector, adapter);
3770 }
3771
3772 static int
3773 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3774 {
3775 struct intel_connector *intel_connector = to_intel_connector(connector);
3776
3777 /* use cached edid if we have one */
3778 if (intel_connector->edid) {
3779 /* invalid edid */
3780 if (IS_ERR(intel_connector->edid))
3781 return 0;
3782
3783 return intel_connector_update_modes(connector,
3784 intel_connector->edid);
3785 }
3786
3787 return intel_ddc_get_modes(connector, adapter);
3788 }
3789
3790 static enum drm_connector_status
3791 intel_dp_detect(struct drm_connector *connector, bool force)
3792 {
3793 struct intel_dp *intel_dp = intel_attached_dp(connector);
3794 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3795 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3796 struct drm_device *dev = connector->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 enum drm_connector_status status;
3799 enum intel_display_power_domain power_domain;
3800 struct edid *edid = NULL;
3801 bool ret;
3802
3803 power_domain = intel_display_port_power_domain(intel_encoder);
3804 intel_display_power_get(dev_priv, power_domain);
3805
3806 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3807 connector->base.id, connector->name);
3808
3809 if (intel_dp->is_mst) {
3810 /* MST devices are disconnected from a monitor POV */
3811 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3812 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3813 status = connector_status_disconnected;
3814 goto out;
3815 }
3816
3817 intel_dp->has_audio = false;
3818
3819 if (HAS_PCH_SPLIT(dev))
3820 status = ironlake_dp_detect(intel_dp);
3821 else
3822 status = g4x_dp_detect(intel_dp);
3823
3824 if (status != connector_status_connected)
3825 goto out;
3826
3827 intel_dp_probe_oui(intel_dp);
3828
3829 ret = intel_dp_probe_mst(intel_dp);
3830 if (ret) {
3831 /* if we are in MST mode then this connector
3832 won't appear connected or have anything with EDID on it */
3833 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3834 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3835 status = connector_status_disconnected;
3836 goto out;
3837 }
3838
3839 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3840 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3841 } else {
3842 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3843 if (edid) {
3844 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3845 kfree(edid);
3846 }
3847 }
3848
3849 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3850 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3851 status = connector_status_connected;
3852
3853 out:
3854 intel_display_power_put(dev_priv, power_domain);
3855 return status;
3856 }
3857
3858 static int intel_dp_get_modes(struct drm_connector *connector)
3859 {
3860 struct intel_dp *intel_dp = intel_attached_dp(connector);
3861 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3862 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3863 struct intel_connector *intel_connector = to_intel_connector(connector);
3864 struct drm_device *dev = connector->dev;
3865 struct drm_i915_private *dev_priv = dev->dev_private;
3866 enum intel_display_power_domain power_domain;
3867 int ret;
3868
3869 /* We should parse the EDID data and find out if it has an audio sink
3870 */
3871
3872 power_domain = intel_display_port_power_domain(intel_encoder);
3873 intel_display_power_get(dev_priv, power_domain);
3874
3875 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3876 intel_display_power_put(dev_priv, power_domain);
3877 if (ret)
3878 return ret;
3879
3880 /* if eDP has no EDID, fall back to fixed mode */
3881 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3882 struct drm_display_mode *mode;
3883 mode = drm_mode_duplicate(dev,
3884 intel_connector->panel.fixed_mode);
3885 if (mode) {
3886 drm_mode_probed_add(connector, mode);
3887 return 1;
3888 }
3889 }
3890 return 0;
3891 }
3892
3893 static bool
3894 intel_dp_detect_audio(struct drm_connector *connector)
3895 {
3896 struct intel_dp *intel_dp = intel_attached_dp(connector);
3897 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3898 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3899 struct drm_device *dev = connector->dev;
3900 struct drm_i915_private *dev_priv = dev->dev_private;
3901 enum intel_display_power_domain power_domain;
3902 struct edid *edid;
3903 bool has_audio = false;
3904
3905 power_domain = intel_display_port_power_domain(intel_encoder);
3906 intel_display_power_get(dev_priv, power_domain);
3907
3908 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3909 if (edid) {
3910 has_audio = drm_detect_monitor_audio(edid);
3911 kfree(edid);
3912 }
3913
3914 intel_display_power_put(dev_priv, power_domain);
3915
3916 return has_audio;
3917 }
3918
3919 static int
3920 intel_dp_set_property(struct drm_connector *connector,
3921 struct drm_property *property,
3922 uint64_t val)
3923 {
3924 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3925 struct intel_connector *intel_connector = to_intel_connector(connector);
3926 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3927 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3928 int ret;
3929
3930 ret = drm_object_property_set_value(&connector->base, property, val);
3931 if (ret)
3932 return ret;
3933
3934 if (property == dev_priv->force_audio_property) {
3935 int i = val;
3936 bool has_audio;
3937
3938 if (i == intel_dp->force_audio)
3939 return 0;
3940
3941 intel_dp->force_audio = i;
3942
3943 if (i == HDMI_AUDIO_AUTO)
3944 has_audio = intel_dp_detect_audio(connector);
3945 else
3946 has_audio = (i == HDMI_AUDIO_ON);
3947
3948 if (has_audio == intel_dp->has_audio)
3949 return 0;
3950
3951 intel_dp->has_audio = has_audio;
3952 goto done;
3953 }
3954
3955 if (property == dev_priv->broadcast_rgb_property) {
3956 bool old_auto = intel_dp->color_range_auto;
3957 uint32_t old_range = intel_dp->color_range;
3958
3959 switch (val) {
3960 case INTEL_BROADCAST_RGB_AUTO:
3961 intel_dp->color_range_auto = true;
3962 break;
3963 case INTEL_BROADCAST_RGB_FULL:
3964 intel_dp->color_range_auto = false;
3965 intel_dp->color_range = 0;
3966 break;
3967 case INTEL_BROADCAST_RGB_LIMITED:
3968 intel_dp->color_range_auto = false;
3969 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3970 break;
3971 default:
3972 return -EINVAL;
3973 }
3974
3975 if (old_auto == intel_dp->color_range_auto &&
3976 old_range == intel_dp->color_range)
3977 return 0;
3978
3979 goto done;
3980 }
3981
3982 if (is_edp(intel_dp) &&
3983 property == connector->dev->mode_config.scaling_mode_property) {
3984 if (val == DRM_MODE_SCALE_NONE) {
3985 DRM_DEBUG_KMS("no scaling not supported\n");
3986 return -EINVAL;
3987 }
3988
3989 if (intel_connector->panel.fitting_mode == val) {
3990 /* the eDP scaling property is not changed */
3991 return 0;
3992 }
3993 intel_connector->panel.fitting_mode = val;
3994
3995 goto done;
3996 }
3997
3998 return -EINVAL;
3999
4000 done:
4001 if (intel_encoder->base.crtc)
4002 intel_crtc_restore_mode(intel_encoder->base.crtc);
4003
4004 return 0;
4005 }
4006
4007 static void
4008 intel_dp_connector_destroy(struct drm_connector *connector)
4009 {
4010 struct intel_connector *intel_connector = to_intel_connector(connector);
4011
4012 if (!IS_ERR_OR_NULL(intel_connector->edid))
4013 kfree(intel_connector->edid);
4014
4015 /* Can't call is_edp() since the encoder may have been destroyed
4016 * already. */
4017 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4018 intel_panel_fini(&intel_connector->panel);
4019
4020 drm_connector_cleanup(connector);
4021 kfree(connector);
4022 }
4023
4024 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4025 {
4026 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4027 struct intel_dp *intel_dp = &intel_dig_port->dp;
4028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4029
4030 drm_dp_aux_unregister(&intel_dp->aux);
4031 intel_dp_mst_encoder_cleanup(intel_dig_port);
4032 drm_encoder_cleanup(encoder);
4033 if (is_edp(intel_dp)) {
4034 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4035 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4036 edp_panel_vdd_off_sync(intel_dp);
4037 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4038 if (intel_dp->edp_notifier.notifier_call) {
4039 unregister_reboot_notifier(&intel_dp->edp_notifier);
4040 intel_dp->edp_notifier.notifier_call = NULL;
4041 }
4042 }
4043 kfree(intel_dig_port);
4044 }
4045
4046 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4047 {
4048 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4049
4050 if (!is_edp(intel_dp))
4051 return;
4052
4053 edp_panel_vdd_off_sync(intel_dp);
4054 }
4055
4056 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4057 {
4058 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4059 }
4060
4061 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4062 .dpms = intel_connector_dpms,
4063 .detect = intel_dp_detect,
4064 .fill_modes = drm_helper_probe_single_connector_modes,
4065 .set_property = intel_dp_set_property,
4066 .destroy = intel_dp_connector_destroy,
4067 };
4068
4069 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4070 .get_modes = intel_dp_get_modes,
4071 .mode_valid = intel_dp_mode_valid,
4072 .best_encoder = intel_best_encoder,
4073 };
4074
4075 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4076 .reset = intel_dp_encoder_reset,
4077 .destroy = intel_dp_encoder_destroy,
4078 };
4079
4080 void
4081 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4082 {
4083 return;
4084 }
4085
4086 bool
4087 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4088 {
4089 struct intel_dp *intel_dp = &intel_dig_port->dp;
4090 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4091 struct drm_device *dev = intel_dig_port->base.base.dev;
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4093 enum intel_display_power_domain power_domain;
4094 bool ret = true;
4095
4096 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4097 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4098
4099 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4100 port_name(intel_dig_port->port),
4101 long_hpd ? "long" : "short");
4102
4103 power_domain = intel_display_port_power_domain(intel_encoder);
4104 intel_display_power_get(dev_priv, power_domain);
4105
4106 if (long_hpd) {
4107 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4108 goto mst_fail;
4109
4110 if (!intel_dp_get_dpcd(intel_dp)) {
4111 goto mst_fail;
4112 }
4113
4114 intel_dp_probe_oui(intel_dp);
4115
4116 if (!intel_dp_probe_mst(intel_dp))
4117 goto mst_fail;
4118
4119 } else {
4120 if (intel_dp->is_mst) {
4121 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4122 goto mst_fail;
4123 }
4124
4125 if (!intel_dp->is_mst) {
4126 /*
4127 * we'll check the link status via the normal hot plug path later -
4128 * but for short hpds we should check it now
4129 */
4130 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4131 intel_dp_check_link_status(intel_dp);
4132 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4133 }
4134 }
4135 ret = false;
4136 goto put_power;
4137 mst_fail:
4138 /* if we were in MST mode, and device is not there get out of MST mode */
4139 if (intel_dp->is_mst) {
4140 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4141 intel_dp->is_mst = false;
4142 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4143 }
4144 put_power:
4145 intel_display_power_put(dev_priv, power_domain);
4146
4147 return ret;
4148 }
4149
4150 /* Return which DP Port should be selected for Transcoder DP control */
4151 int
4152 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4153 {
4154 struct drm_device *dev = crtc->dev;
4155 struct intel_encoder *intel_encoder;
4156 struct intel_dp *intel_dp;
4157
4158 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4159 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4160
4161 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4162 intel_encoder->type == INTEL_OUTPUT_EDP)
4163 return intel_dp->output_reg;
4164 }
4165
4166 return -1;
4167 }
4168
4169 /* check the VBT to see whether the eDP is on DP-D port */
4170 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4171 {
4172 struct drm_i915_private *dev_priv = dev->dev_private;
4173 union child_device_config *p_child;
4174 int i;
4175 static const short port_mapping[] = {
4176 [PORT_B] = PORT_IDPB,
4177 [PORT_C] = PORT_IDPC,
4178 [PORT_D] = PORT_IDPD,
4179 };
4180
4181 if (port == PORT_A)
4182 return true;
4183
4184 if (!dev_priv->vbt.child_dev_num)
4185 return false;
4186
4187 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4188 p_child = dev_priv->vbt.child_dev + i;
4189
4190 if (p_child->common.dvo_port == port_mapping[port] &&
4191 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4192 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4193 return true;
4194 }
4195 return false;
4196 }
4197
4198 void
4199 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4200 {
4201 struct intel_connector *intel_connector = to_intel_connector(connector);
4202
4203 intel_attach_force_audio_property(connector);
4204 intel_attach_broadcast_rgb_property(connector);
4205 intel_dp->color_range_auto = true;
4206
4207 if (is_edp(intel_dp)) {
4208 drm_mode_create_scaling_mode_property(connector->dev);
4209 drm_object_attach_property(
4210 &connector->base,
4211 connector->dev->mode_config.scaling_mode_property,
4212 DRM_MODE_SCALE_ASPECT);
4213 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4214 }
4215 }
4216
4217 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4218 {
4219 intel_dp->last_power_cycle = jiffies;
4220 intel_dp->last_power_on = jiffies;
4221 intel_dp->last_backlight_off = jiffies;
4222 }
4223
4224 static void
4225 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4226 struct intel_dp *intel_dp,
4227 struct edp_power_seq *out)
4228 {
4229 struct drm_i915_private *dev_priv = dev->dev_private;
4230 struct edp_power_seq cur, vbt, spec, final;
4231 u32 pp_on, pp_off, pp_div, pp;
4232 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4233
4234 if (HAS_PCH_SPLIT(dev)) {
4235 pp_ctrl_reg = PCH_PP_CONTROL;
4236 pp_on_reg = PCH_PP_ON_DELAYS;
4237 pp_off_reg = PCH_PP_OFF_DELAYS;
4238 pp_div_reg = PCH_PP_DIVISOR;
4239 } else {
4240 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4241
4242 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4243 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4244 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4245 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4246 }
4247
4248 /* Workaround: Need to write PP_CONTROL with the unlock key as
4249 * the very first thing. */
4250 pp = ironlake_get_pp_control(intel_dp);
4251 I915_WRITE(pp_ctrl_reg, pp);
4252
4253 pp_on = I915_READ(pp_on_reg);
4254 pp_off = I915_READ(pp_off_reg);
4255 pp_div = I915_READ(pp_div_reg);
4256
4257 /* Pull timing values out of registers */
4258 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4259 PANEL_POWER_UP_DELAY_SHIFT;
4260
4261 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4262 PANEL_LIGHT_ON_DELAY_SHIFT;
4263
4264 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4265 PANEL_LIGHT_OFF_DELAY_SHIFT;
4266
4267 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4268 PANEL_POWER_DOWN_DELAY_SHIFT;
4269
4270 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4271 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4272
4273 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4274 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4275
4276 vbt = dev_priv->vbt.edp_pps;
4277
4278 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4279 * our hw here, which are all in 100usec. */
4280 spec.t1_t3 = 210 * 10;
4281 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4282 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4283 spec.t10 = 500 * 10;
4284 /* This one is special and actually in units of 100ms, but zero
4285 * based in the hw (so we need to add 100 ms). But the sw vbt
4286 * table multiplies it with 1000 to make it in units of 100usec,
4287 * too. */
4288 spec.t11_t12 = (510 + 100) * 10;
4289
4290 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4291 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4292
4293 /* Use the max of the register settings and vbt. If both are
4294 * unset, fall back to the spec limits. */
4295 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4296 spec.field : \
4297 max(cur.field, vbt.field))
4298 assign_final(t1_t3);
4299 assign_final(t8);
4300 assign_final(t9);
4301 assign_final(t10);
4302 assign_final(t11_t12);
4303 #undef assign_final
4304
4305 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4306 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4307 intel_dp->backlight_on_delay = get_delay(t8);
4308 intel_dp->backlight_off_delay = get_delay(t9);
4309 intel_dp->panel_power_down_delay = get_delay(t10);
4310 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4311 #undef get_delay
4312
4313 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4314 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4315 intel_dp->panel_power_cycle_delay);
4316
4317 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4318 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4319
4320 if (out)
4321 *out = final;
4322 }
4323
4324 static void
4325 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4326 struct intel_dp *intel_dp,
4327 struct edp_power_seq *seq)
4328 {
4329 struct drm_i915_private *dev_priv = dev->dev_private;
4330 u32 pp_on, pp_off, pp_div, port_sel = 0;
4331 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4332 int pp_on_reg, pp_off_reg, pp_div_reg;
4333 enum port port = dp_to_dig_port(intel_dp)->port;
4334
4335 if (HAS_PCH_SPLIT(dev)) {
4336 pp_on_reg = PCH_PP_ON_DELAYS;
4337 pp_off_reg = PCH_PP_OFF_DELAYS;
4338 pp_div_reg = PCH_PP_DIVISOR;
4339 } else {
4340 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4341
4342 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4343 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4344 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4345 }
4346
4347 /*
4348 * And finally store the new values in the power sequencer. The
4349 * backlight delays are set to 1 because we do manual waits on them. For
4350 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4351 * we'll end up waiting for the backlight off delay twice: once when we
4352 * do the manual sleep, and once when we disable the panel and wait for
4353 * the PP_STATUS bit to become zero.
4354 */
4355 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4356 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4357 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4358 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4359 /* Compute the divisor for the pp clock, simply match the Bspec
4360 * formula. */
4361 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4362 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4363 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4364
4365 /* Haswell doesn't have any port selection bits for the panel
4366 * power sequencer any more. */
4367 if (IS_VALLEYVIEW(dev)) {
4368 port_sel = PANEL_PORT_SELECT_VLV(port);
4369 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4370 if (port == PORT_A)
4371 port_sel = PANEL_PORT_SELECT_DPA;
4372 else
4373 port_sel = PANEL_PORT_SELECT_DPD;
4374 }
4375
4376 pp_on |= port_sel;
4377
4378 I915_WRITE(pp_on_reg, pp_on);
4379 I915_WRITE(pp_off_reg, pp_off);
4380 I915_WRITE(pp_div_reg, pp_div);
4381
4382 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4383 I915_READ(pp_on_reg),
4384 I915_READ(pp_off_reg),
4385 I915_READ(pp_div_reg));
4386 }
4387
4388 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4389 {
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 struct intel_encoder *encoder;
4392 struct intel_dp *intel_dp = NULL;
4393 struct intel_crtc_config *config = NULL;
4394 struct intel_crtc *intel_crtc = NULL;
4395 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4396 u32 reg, val;
4397 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4398
4399 if (refresh_rate <= 0) {
4400 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4401 return;
4402 }
4403
4404 if (intel_connector == NULL) {
4405 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4406 return;
4407 }
4408
4409 /*
4410 * FIXME: This needs proper synchronization with psr state. But really
4411 * hard to tell without seeing the user of this function of this code.
4412 * Check locking and ordering once that lands.
4413 */
4414 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4415 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4416 return;
4417 }
4418
4419 encoder = intel_attached_encoder(&intel_connector->base);
4420 intel_dp = enc_to_intel_dp(&encoder->base);
4421 intel_crtc = encoder->new_crtc;
4422
4423 if (!intel_crtc) {
4424 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4425 return;
4426 }
4427
4428 config = &intel_crtc->config;
4429
4430 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4431 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4432 return;
4433 }
4434
4435 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4436 index = DRRS_LOW_RR;
4437
4438 if (index == intel_dp->drrs_state.refresh_rate_type) {
4439 DRM_DEBUG_KMS(
4440 "DRRS requested for previously set RR...ignoring\n");
4441 return;
4442 }
4443
4444 if (!intel_crtc->active) {
4445 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4446 return;
4447 }
4448
4449 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4450 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4451 val = I915_READ(reg);
4452 if (index > DRRS_HIGH_RR) {
4453 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4454 intel_dp_set_m_n(intel_crtc);
4455 } else {
4456 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4457 }
4458 I915_WRITE(reg, val);
4459 }
4460
4461 /*
4462 * mutex taken to ensure that there is no race between differnt
4463 * drrs calls trying to update refresh rate. This scenario may occur
4464 * in future when idleness detection based DRRS in kernel and
4465 * possible calls from user space to set differnt RR are made.
4466 */
4467
4468 mutex_lock(&intel_dp->drrs_state.mutex);
4469
4470 intel_dp->drrs_state.refresh_rate_type = index;
4471
4472 mutex_unlock(&intel_dp->drrs_state.mutex);
4473
4474 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4475 }
4476
4477 static struct drm_display_mode *
4478 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4479 struct intel_connector *intel_connector,
4480 struct drm_display_mode *fixed_mode)
4481 {
4482 struct drm_connector *connector = &intel_connector->base;
4483 struct intel_dp *intel_dp = &intel_dig_port->dp;
4484 struct drm_device *dev = intel_dig_port->base.base.dev;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 struct drm_display_mode *downclock_mode = NULL;
4487
4488 if (INTEL_INFO(dev)->gen <= 6) {
4489 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4490 return NULL;
4491 }
4492
4493 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4494 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4495 return NULL;
4496 }
4497
4498 downclock_mode = intel_find_panel_downclock
4499 (dev, fixed_mode, connector);
4500
4501 if (!downclock_mode) {
4502 DRM_DEBUG_KMS("DRRS not supported\n");
4503 return NULL;
4504 }
4505
4506 dev_priv->drrs.connector = intel_connector;
4507
4508 mutex_init(&intel_dp->drrs_state.mutex);
4509
4510 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4511
4512 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4513 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4514 return downclock_mode;
4515 }
4516
4517 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4518 {
4519 struct drm_device *dev = intel_encoder->base.dev;
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 struct intel_dp *intel_dp;
4522 enum intel_display_power_domain power_domain;
4523
4524 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4525 return;
4526
4527 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4528 if (!edp_have_panel_vdd(intel_dp))
4529 return;
4530 /*
4531 * The VDD bit needs a power domain reference, so if the bit is
4532 * already enabled when we boot or resume, grab this reference and
4533 * schedule a vdd off, so we don't hold on to the reference
4534 * indefinitely.
4535 */
4536 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4537 power_domain = intel_display_port_power_domain(intel_encoder);
4538 intel_display_power_get(dev_priv, power_domain);
4539
4540 edp_panel_vdd_schedule_off(intel_dp);
4541 }
4542
4543 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4544 struct intel_connector *intel_connector,
4545 struct edp_power_seq *power_seq)
4546 {
4547 struct drm_connector *connector = &intel_connector->base;
4548 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4549 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4550 struct drm_device *dev = intel_encoder->base.dev;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552 struct drm_display_mode *fixed_mode = NULL;
4553 struct drm_display_mode *downclock_mode = NULL;
4554 bool has_dpcd;
4555 struct drm_display_mode *scan;
4556 struct edid *edid;
4557
4558 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4559
4560 if (!is_edp(intel_dp))
4561 return true;
4562
4563 intel_edp_panel_vdd_sanitize(intel_encoder);
4564
4565 /* Cache DPCD and EDID for edp. */
4566 intel_edp_panel_vdd_on(intel_dp);
4567 has_dpcd = intel_dp_get_dpcd(intel_dp);
4568 intel_edp_panel_vdd_off(intel_dp, false);
4569
4570 if (has_dpcd) {
4571 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4572 dev_priv->no_aux_handshake =
4573 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4574 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4575 } else {
4576 /* if this fails, presume the device is a ghost */
4577 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4578 return false;
4579 }
4580
4581 /* We now know it's not a ghost, init power sequence regs. */
4582 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4583
4584 mutex_lock(&dev->mode_config.mutex);
4585 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4586 if (edid) {
4587 if (drm_add_edid_modes(connector, edid)) {
4588 drm_mode_connector_update_edid_property(connector,
4589 edid);
4590 drm_edid_to_eld(connector, edid);
4591 } else {
4592 kfree(edid);
4593 edid = ERR_PTR(-EINVAL);
4594 }
4595 } else {
4596 edid = ERR_PTR(-ENOENT);
4597 }
4598 intel_connector->edid = edid;
4599
4600 /* prefer fixed mode from EDID if available */
4601 list_for_each_entry(scan, &connector->probed_modes, head) {
4602 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4603 fixed_mode = drm_mode_duplicate(dev, scan);
4604 downclock_mode = intel_dp_drrs_init(
4605 intel_dig_port,
4606 intel_connector, fixed_mode);
4607 break;
4608 }
4609 }
4610
4611 /* fallback to VBT if available for eDP */
4612 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4613 fixed_mode = drm_mode_duplicate(dev,
4614 dev_priv->vbt.lfp_lvds_vbt_mode);
4615 if (fixed_mode)
4616 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4617 }
4618 mutex_unlock(&dev->mode_config.mutex);
4619
4620 if (IS_VALLEYVIEW(dev)) {
4621 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4622 register_reboot_notifier(&intel_dp->edp_notifier);
4623 }
4624
4625 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4626 intel_connector->panel.backlight_power = intel_edp_backlight_power;
4627 intel_panel_setup_backlight(connector);
4628
4629 return true;
4630 }
4631
4632 bool
4633 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4634 struct intel_connector *intel_connector)
4635 {
4636 struct drm_connector *connector = &intel_connector->base;
4637 struct intel_dp *intel_dp = &intel_dig_port->dp;
4638 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4639 struct drm_device *dev = intel_encoder->base.dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 enum port port = intel_dig_port->port;
4642 struct edp_power_seq power_seq = { 0 };
4643 int type;
4644
4645 /* intel_dp vfuncs */
4646 if (IS_VALLEYVIEW(dev))
4647 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4648 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4649 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4650 else if (HAS_PCH_SPLIT(dev))
4651 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4652 else
4653 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4654
4655 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4656
4657 /* Preserve the current hw state. */
4658 intel_dp->DP = I915_READ(intel_dp->output_reg);
4659 intel_dp->attached_connector = intel_connector;
4660
4661 if (intel_dp_is_edp(dev, port))
4662 type = DRM_MODE_CONNECTOR_eDP;
4663 else
4664 type = DRM_MODE_CONNECTOR_DisplayPort;
4665
4666 /*
4667 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4668 * for DP the encoder type can be set by the caller to
4669 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4670 */
4671 if (type == DRM_MODE_CONNECTOR_eDP)
4672 intel_encoder->type = INTEL_OUTPUT_EDP;
4673
4674 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4675 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4676 port_name(port));
4677
4678 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4679 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4680
4681 connector->interlace_allowed = true;
4682 connector->doublescan_allowed = 0;
4683
4684 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4685 edp_panel_vdd_work);
4686
4687 intel_connector_attach_encoder(intel_connector, intel_encoder);
4688 drm_connector_register(connector);
4689
4690 if (HAS_DDI(dev))
4691 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4692 else
4693 intel_connector->get_hw_state = intel_connector_get_hw_state;
4694 intel_connector->unregister = intel_dp_connector_unregister;
4695
4696 /* Set up the hotplug pin. */
4697 switch (port) {
4698 case PORT_A:
4699 intel_encoder->hpd_pin = HPD_PORT_A;
4700 break;
4701 case PORT_B:
4702 intel_encoder->hpd_pin = HPD_PORT_B;
4703 break;
4704 case PORT_C:
4705 intel_encoder->hpd_pin = HPD_PORT_C;
4706 break;
4707 case PORT_D:
4708 intel_encoder->hpd_pin = HPD_PORT_D;
4709 break;
4710 default:
4711 BUG();
4712 }
4713
4714 if (is_edp(intel_dp)) {
4715 intel_dp_init_panel_power_timestamps(intel_dp);
4716 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4717 }
4718
4719 intel_dp_aux_init(intel_dp, intel_connector);
4720
4721 /* init MST on ports that can support it */
4722 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4723 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4724 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4725 }
4726 }
4727
4728 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4729 drm_dp_aux_unregister(&intel_dp->aux);
4730 if (is_edp(intel_dp)) {
4731 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4732 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4733 edp_panel_vdd_off_sync(intel_dp);
4734 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4735 }
4736 drm_connector_unregister(connector);
4737 drm_connector_cleanup(connector);
4738 return false;
4739 }
4740
4741 intel_dp_add_properties(intel_dp, connector);
4742
4743 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4744 * 0xd. Failure to do so will result in spurious interrupts being
4745 * generated on the port when a cable is not attached.
4746 */
4747 if (IS_G4X(dev) && !IS_GM45(dev)) {
4748 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4749 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4750 }
4751
4752 return true;
4753 }
4754
4755 void
4756 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4757 {
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4759 struct intel_digital_port *intel_dig_port;
4760 struct intel_encoder *intel_encoder;
4761 struct drm_encoder *encoder;
4762 struct intel_connector *intel_connector;
4763
4764 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4765 if (!intel_dig_port)
4766 return;
4767
4768 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4769 if (!intel_connector) {
4770 kfree(intel_dig_port);
4771 return;
4772 }
4773
4774 intel_encoder = &intel_dig_port->base;
4775 encoder = &intel_encoder->base;
4776
4777 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4778 DRM_MODE_ENCODER_TMDS);
4779
4780 intel_encoder->compute_config = intel_dp_compute_config;
4781 intel_encoder->disable = intel_disable_dp;
4782 intel_encoder->get_hw_state = intel_dp_get_hw_state;
4783 intel_encoder->get_config = intel_dp_get_config;
4784 intel_encoder->suspend = intel_dp_encoder_suspend;
4785 if (IS_CHERRYVIEW(dev)) {
4786 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4787 intel_encoder->pre_enable = chv_pre_enable_dp;
4788 intel_encoder->enable = vlv_enable_dp;
4789 intel_encoder->post_disable = chv_post_disable_dp;
4790 } else if (IS_VALLEYVIEW(dev)) {
4791 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4792 intel_encoder->pre_enable = vlv_pre_enable_dp;
4793 intel_encoder->enable = vlv_enable_dp;
4794 intel_encoder->post_disable = vlv_post_disable_dp;
4795 } else {
4796 intel_encoder->pre_enable = g4x_pre_enable_dp;
4797 intel_encoder->enable = g4x_enable_dp;
4798 intel_encoder->post_disable = g4x_post_disable_dp;
4799 }
4800
4801 intel_dig_port->port = port;
4802 intel_dig_port->dp.output_reg = output_reg;
4803
4804 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4805 if (IS_CHERRYVIEW(dev)) {
4806 if (port == PORT_D)
4807 intel_encoder->crtc_mask = 1 << 2;
4808 else
4809 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4810 } else {
4811 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4812 }
4813 intel_encoder->cloneable = 0;
4814 intel_encoder->hot_plug = intel_dp_hot_plug;
4815
4816 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4817 dev_priv->hpd_irq_port[port] = intel_dig_port;
4818
4819 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4820 drm_encoder_cleanup(encoder);
4821 kfree(intel_dig_port);
4822 kfree(intel_connector);
4823 }
4824 }
4825
4826 void intel_dp_mst_suspend(struct drm_device *dev)
4827 {
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 int i;
4830
4831 /* disable MST */
4832 for (i = 0; i < I915_MAX_PORTS; i++) {
4833 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4834 if (!intel_dig_port)
4835 continue;
4836
4837 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4838 if (!intel_dig_port->dp.can_mst)
4839 continue;
4840 if (intel_dig_port->dp.is_mst)
4841 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4842 }
4843 }
4844 }
4845
4846 void intel_dp_mst_resume(struct drm_device *dev)
4847 {
4848 struct drm_i915_private *dev_priv = dev->dev_private;
4849 int i;
4850
4851 for (i = 0; i < I915_MAX_PORTS; i++) {
4852 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4853 if (!intel_dig_port)
4854 continue;
4855 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4856 int ret;
4857
4858 if (!intel_dig_port->dp.can_mst)
4859 continue;
4860
4861 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4862 if (ret != 0) {
4863 intel_dp_check_mst_status(&intel_dig_port->dp);
4864 }
4865 }
4866 }
4867 }
Linux kernel - Deliverables
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