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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
56 {
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
60 }
61
62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63 {
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
65 }
66
67 static void intel_dp_link_down(struct intel_dp *intel_dp);
68
69 static int
70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
71 {
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
80 break;
81 default:
82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
83 max_link_bw);
84 max_link_bw = DP_LINK_BW_1_62;
85 break;
86 }
87 return max_link_bw;
88 }
89
90 /*
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
93 *
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
95 *
96 * 270000 * 1 * 8 / 10 == 216000
97 *
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
102 *
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
105 */
106
107 static int
108 intel_dp_link_required(int pixel_clock, int bpp)
109 {
110 return (pixel_clock * bpp + 9) / 10;
111 }
112
113 static int
114 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
115 {
116 return (max_link_clock * max_lanes * 8) / 10;
117 }
118
119 static int
120 intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
122 {
123 struct intel_dp *intel_dp = intel_attached_dp(connector);
124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
128
129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
131 return MODE_PANEL;
132
133 if (mode->vdisplay > fixed_mode->vdisplay)
134 return MODE_PANEL;
135
136 target_clock = fixed_mode->clock;
137 }
138
139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
141
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
144
145 if (mode_rate > max_rate)
146 return MODE_CLOCK_HIGH;
147
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
150
151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
153
154 return MODE_OK;
155 }
156
157 static uint32_t
158 pack_aux(uint8_t *src, int src_bytes)
159 {
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168 }
169
170 static void
171 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172 {
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178 }
179
180 /* hrawclock is 1/4 the FSB frequency */
181 static int
182 intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
215 {
216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 u32 pp_stat_reg;
219
220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
222 }
223
224 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
225 {
226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 u32 pp_ctrl_reg;
229
230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
232 }
233
234 static void
235 intel_dp_check_edp(struct intel_dp *intel_dp)
236 {
237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 u32 pp_stat_reg, pp_ctrl_reg;
240
241 if (!is_edp(intel_dp))
242 return;
243
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
246
247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
252 }
253 }
254
255 static uint32_t
256 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
257 {
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
262 uint32_t status;
263 bool done;
264
265 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
266 if (has_aux_irq)
267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
268 msecs_to_jiffies_timeout(10));
269 else
270 done = wait_for_atomic(C, 10) == 0;
271 if (!done)
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
273 has_aux_irq);
274 #undef C
275
276 return status;
277 }
278
279 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
280 int index)
281 {
282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct drm_device *dev = intel_dig_port->base.base.dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
285
286 /* The clock divider is based off the hrawclk,
287 * and would like to run at 2MHz. So, take the
288 * hrawclk value and divide by 2 and use that
289 *
290 * Note that PCH attached eDP panels should use a 125MHz input
291 * clock divider.
292 */
293 if (IS_VALLEYVIEW(dev)) {
294 return index ? 0 : 100;
295 } else if (intel_dig_port->port == PORT_A) {
296 if (index)
297 return 0;
298 if (HAS_DDI(dev))
299 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
300 else if (IS_GEN6(dev) || IS_GEN7(dev))
301 return 200; /* SNB & IVB eDP input clock at 400Mhz */
302 else
303 return 225; /* eDP input clock at 450Mhz */
304 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
305 /* Workaround for non-ULT HSW */
306 switch (index) {
307 case 0: return 63;
308 case 1: return 72;
309 default: return 0;
310 }
311 } else if (HAS_PCH_SPLIT(dev)) {
312 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
313 } else {
314 return index ? 0 :intel_hrawclk(dev) / 2;
315 }
316 }
317
318 static int
319 intel_dp_aux_ch(struct intel_dp *intel_dp,
320 uint8_t *send, int send_bytes,
321 uint8_t *recv, int recv_size)
322 {
323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
324 struct drm_device *dev = intel_dig_port->base.base.dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
327 uint32_t ch_data = ch_ctl + 4;
328 uint32_t aux_clock_divider;
329 int i, ret, recv_bytes;
330 uint32_t status;
331 int try, precharge, clock = 0;
332 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
333
334 /* dp aux is extremely sensitive to irq latency, hence request the
335 * lowest possible wakeup latency and so prevent the cpu from going into
336 * deep sleep states.
337 */
338 pm_qos_update_request(&dev_priv->pm_qos, 0);
339
340 intel_dp_check_edp(intel_dp);
341
342 if (IS_GEN6(dev))
343 precharge = 3;
344 else
345 precharge = 5;
346
347 intel_aux_display_runtime_get(dev_priv);
348
349 /* Try to wait for any previous AUX channel activity */
350 for (try = 0; try < 3; try++) {
351 status = I915_READ_NOTRACE(ch_ctl);
352 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
353 break;
354 msleep(1);
355 }
356
357 if (try == 3) {
358 WARN(1, "dp_aux_ch not started status 0x%08x\n",
359 I915_READ(ch_ctl));
360 ret = -EBUSY;
361 goto out;
362 }
363
364 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
365 /* Must try at least 3 times according to DP spec */
366 for (try = 0; try < 5; try++) {
367 /* Load the send data into the aux channel data registers */
368 for (i = 0; i < send_bytes; i += 4)
369 I915_WRITE(ch_data + i,
370 pack_aux(send + i, send_bytes - i));
371
372 /* Send the command and wait for it to complete */
373 I915_WRITE(ch_ctl,
374 DP_AUX_CH_CTL_SEND_BUSY |
375 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
376 DP_AUX_CH_CTL_TIME_OUT_400us |
377 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
378 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
379 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
380 DP_AUX_CH_CTL_DONE |
381 DP_AUX_CH_CTL_TIME_OUT_ERROR |
382 DP_AUX_CH_CTL_RECEIVE_ERROR);
383
384 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
385
386 /* Clear done status and any errors */
387 I915_WRITE(ch_ctl,
388 status |
389 DP_AUX_CH_CTL_DONE |
390 DP_AUX_CH_CTL_TIME_OUT_ERROR |
391 DP_AUX_CH_CTL_RECEIVE_ERROR);
392
393 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
394 DP_AUX_CH_CTL_RECEIVE_ERROR))
395 continue;
396 if (status & DP_AUX_CH_CTL_DONE)
397 break;
398 }
399 if (status & DP_AUX_CH_CTL_DONE)
400 break;
401 }
402
403 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
404 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
405 ret = -EBUSY;
406 goto out;
407 }
408
409 /* Check for timeout or receive error.
410 * Timeouts occur when the sink is not connected
411 */
412 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
413 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
414 ret = -EIO;
415 goto out;
416 }
417
418 /* Timeouts occur when the device isn't connected, so they're
419 * "normal" -- don't fill the kernel log with these */
420 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
421 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
422 ret = -ETIMEDOUT;
423 goto out;
424 }
425
426 /* Unload any bytes sent back from the other side */
427 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
428 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
429 if (recv_bytes > recv_size)
430 recv_bytes = recv_size;
431
432 for (i = 0; i < recv_bytes; i += 4)
433 unpack_aux(I915_READ(ch_data + i),
434 recv + i, recv_bytes - i);
435
436 ret = recv_bytes;
437 out:
438 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
439 intel_aux_display_runtime_put(dev_priv);
440
441 return ret;
442 }
443
444 /* Write data to the aux channel in native mode */
445 static int
446 intel_dp_aux_native_write(struct intel_dp *intel_dp,
447 uint16_t address, uint8_t *send, int send_bytes)
448 {
449 int ret;
450 uint8_t msg[20];
451 int msg_bytes;
452 uint8_t ack;
453
454 intel_dp_check_edp(intel_dp);
455 if (send_bytes > 16)
456 return -1;
457 msg[0] = AUX_NATIVE_WRITE << 4;
458 msg[1] = address >> 8;
459 msg[2] = address & 0xff;
460 msg[3] = send_bytes - 1;
461 memcpy(&msg[4], send, send_bytes);
462 msg_bytes = send_bytes + 4;
463 for (;;) {
464 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
465 if (ret < 0)
466 return ret;
467 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
468 break;
469 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
470 udelay(100);
471 else
472 return -EIO;
473 }
474 return send_bytes;
475 }
476
477 /* Write a single byte to the aux channel in native mode */
478 static int
479 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
480 uint16_t address, uint8_t byte)
481 {
482 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
483 }
484
485 /* read bytes from a native aux channel */
486 static int
487 intel_dp_aux_native_read(struct intel_dp *intel_dp,
488 uint16_t address, uint8_t *recv, int recv_bytes)
489 {
490 uint8_t msg[4];
491 int msg_bytes;
492 uint8_t reply[20];
493 int reply_bytes;
494 uint8_t ack;
495 int ret;
496
497 intel_dp_check_edp(intel_dp);
498 msg[0] = AUX_NATIVE_READ << 4;
499 msg[1] = address >> 8;
500 msg[2] = address & 0xff;
501 msg[3] = recv_bytes - 1;
502
503 msg_bytes = 4;
504 reply_bytes = recv_bytes + 1;
505
506 for (;;) {
507 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
508 reply, reply_bytes);
509 if (ret == 0)
510 return -EPROTO;
511 if (ret < 0)
512 return ret;
513 ack = reply[0];
514 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
515 memcpy(recv, reply + 1, ret - 1);
516 return ret - 1;
517 }
518 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
519 udelay(100);
520 else
521 return -EIO;
522 }
523 }
524
525 static int
526 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
527 uint8_t write_byte, uint8_t *read_byte)
528 {
529 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
530 struct intel_dp *intel_dp = container_of(adapter,
531 struct intel_dp,
532 adapter);
533 uint16_t address = algo_data->address;
534 uint8_t msg[5];
535 uint8_t reply[2];
536 unsigned retry;
537 int msg_bytes;
538 int reply_bytes;
539 int ret;
540
541 intel_dp_check_edp(intel_dp);
542 /* Set up the command byte */
543 if (mode & MODE_I2C_READ)
544 msg[0] = AUX_I2C_READ << 4;
545 else
546 msg[0] = AUX_I2C_WRITE << 4;
547
548 if (!(mode & MODE_I2C_STOP))
549 msg[0] |= AUX_I2C_MOT << 4;
550
551 msg[1] = address >> 8;
552 msg[2] = address;
553
554 switch (mode) {
555 case MODE_I2C_WRITE:
556 msg[3] = 0;
557 msg[4] = write_byte;
558 msg_bytes = 5;
559 reply_bytes = 1;
560 break;
561 case MODE_I2C_READ:
562 msg[3] = 0;
563 msg_bytes = 4;
564 reply_bytes = 2;
565 break;
566 default:
567 msg_bytes = 3;
568 reply_bytes = 1;
569 break;
570 }
571
572 for (retry = 0; retry < 5; retry++) {
573 ret = intel_dp_aux_ch(intel_dp,
574 msg, msg_bytes,
575 reply, reply_bytes);
576 if (ret < 0) {
577 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
578 return ret;
579 }
580
581 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
582 case AUX_NATIVE_REPLY_ACK:
583 /* I2C-over-AUX Reply field is only valid
584 * when paired with AUX ACK.
585 */
586 break;
587 case AUX_NATIVE_REPLY_NACK:
588 DRM_DEBUG_KMS("aux_ch native nack\n");
589 return -EREMOTEIO;
590 case AUX_NATIVE_REPLY_DEFER:
591 udelay(100);
592 continue;
593 default:
594 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
595 reply[0]);
596 return -EREMOTEIO;
597 }
598
599 switch (reply[0] & AUX_I2C_REPLY_MASK) {
600 case AUX_I2C_REPLY_ACK:
601 if (mode == MODE_I2C_READ) {
602 *read_byte = reply[1];
603 }
604 return reply_bytes - 1;
605 case AUX_I2C_REPLY_NACK:
606 DRM_DEBUG_KMS("aux_i2c nack\n");
607 return -EREMOTEIO;
608 case AUX_I2C_REPLY_DEFER:
609 DRM_DEBUG_KMS("aux_i2c defer\n");
610 udelay(100);
611 break;
612 default:
613 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
614 return -EREMOTEIO;
615 }
616 }
617
618 DRM_ERROR("too many retries, giving up\n");
619 return -EREMOTEIO;
620 }
621
622 static int
623 intel_dp_i2c_init(struct intel_dp *intel_dp,
624 struct intel_connector *intel_connector, const char *name)
625 {
626 int ret;
627
628 DRM_DEBUG_KMS("i2c_init %s\n", name);
629 intel_dp->algo.running = false;
630 intel_dp->algo.address = 0;
631 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
632
633 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
634 intel_dp->adapter.owner = THIS_MODULE;
635 intel_dp->adapter.class = I2C_CLASS_DDC;
636 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
637 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
638 intel_dp->adapter.algo_data = &intel_dp->algo;
639 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
640
641 ironlake_edp_panel_vdd_on(intel_dp);
642 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
643 ironlake_edp_panel_vdd_off(intel_dp, false);
644 return ret;
645 }
646
647 static void
648 intel_dp_set_clock(struct intel_encoder *encoder,
649 struct intel_crtc_config *pipe_config, int link_bw)
650 {
651 struct drm_device *dev = encoder->base.dev;
652
653 if (IS_G4X(dev)) {
654 if (link_bw == DP_LINK_BW_1_62) {
655 pipe_config->dpll.p1 = 2;
656 pipe_config->dpll.p2 = 10;
657 pipe_config->dpll.n = 2;
658 pipe_config->dpll.m1 = 23;
659 pipe_config->dpll.m2 = 8;
660 } else {
661 pipe_config->dpll.p1 = 1;
662 pipe_config->dpll.p2 = 10;
663 pipe_config->dpll.n = 1;
664 pipe_config->dpll.m1 = 14;
665 pipe_config->dpll.m2 = 2;
666 }
667 pipe_config->clock_set = true;
668 } else if (IS_HASWELL(dev)) {
669 /* Haswell has special-purpose DP DDI clocks. */
670 } else if (HAS_PCH_SPLIT(dev)) {
671 if (link_bw == DP_LINK_BW_1_62) {
672 pipe_config->dpll.n = 1;
673 pipe_config->dpll.p1 = 2;
674 pipe_config->dpll.p2 = 10;
675 pipe_config->dpll.m1 = 12;
676 pipe_config->dpll.m2 = 9;
677 } else {
678 pipe_config->dpll.n = 2;
679 pipe_config->dpll.p1 = 1;
680 pipe_config->dpll.p2 = 10;
681 pipe_config->dpll.m1 = 14;
682 pipe_config->dpll.m2 = 8;
683 }
684 pipe_config->clock_set = true;
685 } else if (IS_VALLEYVIEW(dev)) {
686 /* FIXME: Need to figure out optimized DP clocks for vlv. */
687 }
688 }
689
690 bool
691 intel_dp_compute_config(struct intel_encoder *encoder,
692 struct intel_crtc_config *pipe_config)
693 {
694 struct drm_device *dev = encoder->base.dev;
695 struct drm_i915_private *dev_priv = dev->dev_private;
696 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
697 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
698 enum port port = dp_to_dig_port(intel_dp)->port;
699 struct intel_crtc *intel_crtc = encoder->new_crtc;
700 struct intel_connector *intel_connector = intel_dp->attached_connector;
701 int lane_count, clock;
702 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
703 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
704 int bpp, mode_rate;
705 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
706 int link_avail, link_clock;
707
708 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
709 pipe_config->has_pch_encoder = true;
710
711 pipe_config->has_dp_encoder = true;
712
713 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
714 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
715 adjusted_mode);
716 if (!HAS_PCH_SPLIT(dev))
717 intel_gmch_panel_fitting(intel_crtc, pipe_config,
718 intel_connector->panel.fitting_mode);
719 else
720 intel_pch_panel_fitting(intel_crtc, pipe_config,
721 intel_connector->panel.fitting_mode);
722 }
723
724 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
725 return false;
726
727 DRM_DEBUG_KMS("DP link computation with max lane count %i "
728 "max bw %02x pixel clock %iKHz\n",
729 max_lane_count, bws[max_clock], adjusted_mode->clock);
730
731 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
732 * bpc in between. */
733 bpp = pipe_config->pipe_bpp;
734 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
735 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
736 dev_priv->vbt.edp_bpp);
737 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
738 }
739
740 for (; bpp >= 6*3; bpp -= 2*3) {
741 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
742
743 for (clock = 0; clock <= max_clock; clock++) {
744 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
745 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
746 link_avail = intel_dp_max_data_rate(link_clock,
747 lane_count);
748
749 if (mode_rate <= link_avail) {
750 goto found;
751 }
752 }
753 }
754 }
755
756 return false;
757
758 found:
759 if (intel_dp->color_range_auto) {
760 /*
761 * See:
762 * CEA-861-E - 5.1 Default Encoding Parameters
763 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
764 */
765 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
766 intel_dp->color_range = DP_COLOR_RANGE_16_235;
767 else
768 intel_dp->color_range = 0;
769 }
770
771 if (intel_dp->color_range)
772 pipe_config->limited_color_range = true;
773
774 intel_dp->link_bw = bws[clock];
775 intel_dp->lane_count = lane_count;
776 pipe_config->pipe_bpp = bpp;
777 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
778
779 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
780 intel_dp->link_bw, intel_dp->lane_count,
781 pipe_config->port_clock, bpp);
782 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
783 mode_rate, link_avail);
784
785 intel_link_compute_m_n(bpp, lane_count,
786 adjusted_mode->clock, pipe_config->port_clock,
787 &pipe_config->dp_m_n);
788
789 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
790
791 return true;
792 }
793
794 void intel_dp_init_link_config(struct intel_dp *intel_dp)
795 {
796 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
797 intel_dp->link_configuration[0] = intel_dp->link_bw;
798 intel_dp->link_configuration[1] = intel_dp->lane_count;
799 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
800 /*
801 * Check for DPCD version > 1.1 and enhanced framing support
802 */
803 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
804 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
805 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
806 }
807 }
808
809 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
810 {
811 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
812 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
813 struct drm_device *dev = crtc->base.dev;
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 u32 dpa_ctl;
816
817 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
818 dpa_ctl = I915_READ(DP_A);
819 dpa_ctl &= ~DP_PLL_FREQ_MASK;
820
821 if (crtc->config.port_clock == 162000) {
822 /* For a long time we've carried around a ILK-DevA w/a for the
823 * 160MHz clock. If we're really unlucky, it's still required.
824 */
825 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
826 dpa_ctl |= DP_PLL_FREQ_160MHZ;
827 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
828 } else {
829 dpa_ctl |= DP_PLL_FREQ_270MHZ;
830 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
831 }
832
833 I915_WRITE(DP_A, dpa_ctl);
834
835 POSTING_READ(DP_A);
836 udelay(500);
837 }
838
839 static void intel_dp_mode_set(struct intel_encoder *encoder)
840 {
841 struct drm_device *dev = encoder->base.dev;
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
844 enum port port = dp_to_dig_port(intel_dp)->port;
845 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
846 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
847
848 /*
849 * There are four kinds of DP registers:
850 *
851 * IBX PCH
852 * SNB CPU
853 * IVB CPU
854 * CPT PCH
855 *
856 * IBX PCH and CPU are the same for almost everything,
857 * except that the CPU DP PLL is configured in this
858 * register
859 *
860 * CPT PCH is quite different, having many bits moved
861 * to the TRANS_DP_CTL register instead. That
862 * configuration happens (oddly) in ironlake_pch_enable
863 */
864
865 /* Preserve the BIOS-computed detected bit. This is
866 * supposed to be read-only.
867 */
868 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
869
870 /* Handle DP bits in common between all three register formats */
871 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
872 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
873
874 if (intel_dp->has_audio) {
875 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
876 pipe_name(crtc->pipe));
877 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
878 intel_write_eld(&encoder->base, adjusted_mode);
879 }
880
881 intel_dp_init_link_config(intel_dp);
882
883 /* Split out the IBX/CPU vs CPT settings */
884
885 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
886 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
887 intel_dp->DP |= DP_SYNC_HS_HIGH;
888 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
889 intel_dp->DP |= DP_SYNC_VS_HIGH;
890 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
891
892 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
893 intel_dp->DP |= DP_ENHANCED_FRAMING;
894
895 intel_dp->DP |= crtc->pipe << 29;
896 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
897 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
898 intel_dp->DP |= intel_dp->color_range;
899
900 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
901 intel_dp->DP |= DP_SYNC_HS_HIGH;
902 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
903 intel_dp->DP |= DP_SYNC_VS_HIGH;
904 intel_dp->DP |= DP_LINK_TRAIN_OFF;
905
906 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
907 intel_dp->DP |= DP_ENHANCED_FRAMING;
908
909 if (crtc->pipe == 1)
910 intel_dp->DP |= DP_PIPEB_SELECT;
911 } else {
912 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
913 }
914
915 if (port == PORT_A && !IS_VALLEYVIEW(dev))
916 ironlake_set_pll_cpu_edp(intel_dp);
917 }
918
919 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
920 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
921
922 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
923 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
924
925 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
926 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
927
928 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
929 u32 mask,
930 u32 value)
931 {
932 struct drm_device *dev = intel_dp_to_dev(intel_dp);
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 u32 pp_stat_reg, pp_ctrl_reg;
935
936 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
937 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
938
939 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
940 mask, value,
941 I915_READ(pp_stat_reg),
942 I915_READ(pp_ctrl_reg));
943
944 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
945 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
946 I915_READ(pp_stat_reg),
947 I915_READ(pp_ctrl_reg));
948 }
949 }
950
951 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
952 {
953 DRM_DEBUG_KMS("Wait for panel power on\n");
954 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
955 }
956
957 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
958 {
959 DRM_DEBUG_KMS("Wait for panel power off time\n");
960 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
961 }
962
963 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
964 {
965 DRM_DEBUG_KMS("Wait for panel power cycle\n");
966 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
967 }
968
969
970 /* Read the current pp_control value, unlocking the register if it
971 * is locked
972 */
973
974 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
975 {
976 struct drm_device *dev = intel_dp_to_dev(intel_dp);
977 struct drm_i915_private *dev_priv = dev->dev_private;
978 u32 control;
979 u32 pp_ctrl_reg;
980
981 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
982 control = I915_READ(pp_ctrl_reg);
983
984 control &= ~PANEL_UNLOCK_MASK;
985 control |= PANEL_UNLOCK_REGS;
986 return control;
987 }
988
989 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
990 {
991 struct drm_device *dev = intel_dp_to_dev(intel_dp);
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 u32 pp;
994 u32 pp_stat_reg, pp_ctrl_reg;
995
996 if (!is_edp(intel_dp))
997 return;
998 DRM_DEBUG_KMS("Turn eDP VDD on\n");
999
1000 WARN(intel_dp->want_panel_vdd,
1001 "eDP VDD already requested on\n");
1002
1003 intel_dp->want_panel_vdd = true;
1004
1005 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1006 DRM_DEBUG_KMS("eDP VDD already on\n");
1007 return;
1008 }
1009
1010 if (!ironlake_edp_have_panel_power(intel_dp))
1011 ironlake_wait_panel_power_cycle(intel_dp);
1012
1013 pp = ironlake_get_pp_control(intel_dp);
1014 pp |= EDP_FORCE_VDD;
1015
1016 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1017 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1018
1019 I915_WRITE(pp_ctrl_reg, pp);
1020 POSTING_READ(pp_ctrl_reg);
1021 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1022 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1023 /*
1024 * If the panel wasn't on, delay before accessing aux channel
1025 */
1026 if (!ironlake_edp_have_panel_power(intel_dp)) {
1027 DRM_DEBUG_KMS("eDP was not running\n");
1028 msleep(intel_dp->panel_power_up_delay);
1029 }
1030 }
1031
1032 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1033 {
1034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036 u32 pp;
1037 u32 pp_stat_reg, pp_ctrl_reg;
1038
1039 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1040
1041 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1042 pp = ironlake_get_pp_control(intel_dp);
1043 pp &= ~EDP_FORCE_VDD;
1044
1045 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1046 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1047
1048 I915_WRITE(pp_ctrl_reg, pp);
1049 POSTING_READ(pp_ctrl_reg);
1050
1051 /* Make sure sequencer is idle before allowing subsequent activity */
1052 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1053 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1054 msleep(intel_dp->panel_power_down_delay);
1055 }
1056 }
1057
1058 static void ironlake_panel_vdd_work(struct work_struct *__work)
1059 {
1060 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1061 struct intel_dp, panel_vdd_work);
1062 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1063
1064 mutex_lock(&dev->mode_config.mutex);
1065 ironlake_panel_vdd_off_sync(intel_dp);
1066 mutex_unlock(&dev->mode_config.mutex);
1067 }
1068
1069 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1070 {
1071 if (!is_edp(intel_dp))
1072 return;
1073
1074 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1075 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1076
1077 intel_dp->want_panel_vdd = false;
1078
1079 if (sync) {
1080 ironlake_panel_vdd_off_sync(intel_dp);
1081 } else {
1082 /*
1083 * Queue the timer to fire a long
1084 * time from now (relative to the power down delay)
1085 * to keep the panel power up across a sequence of operations
1086 */
1087 schedule_delayed_work(&intel_dp->panel_vdd_work,
1088 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1089 }
1090 }
1091
1092 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1093 {
1094 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 u32 pp;
1097 u32 pp_ctrl_reg;
1098
1099 if (!is_edp(intel_dp))
1100 return;
1101
1102 DRM_DEBUG_KMS("Turn eDP power on\n");
1103
1104 if (ironlake_edp_have_panel_power(intel_dp)) {
1105 DRM_DEBUG_KMS("eDP power already on\n");
1106 return;
1107 }
1108
1109 ironlake_wait_panel_power_cycle(intel_dp);
1110
1111 pp = ironlake_get_pp_control(intel_dp);
1112 if (IS_GEN5(dev)) {
1113 /* ILK workaround: disable reset around power sequence */
1114 pp &= ~PANEL_POWER_RESET;
1115 I915_WRITE(PCH_PP_CONTROL, pp);
1116 POSTING_READ(PCH_PP_CONTROL);
1117 }
1118
1119 pp |= POWER_TARGET_ON;
1120 if (!IS_GEN5(dev))
1121 pp |= PANEL_POWER_RESET;
1122
1123 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1124
1125 I915_WRITE(pp_ctrl_reg, pp);
1126 POSTING_READ(pp_ctrl_reg);
1127
1128 ironlake_wait_panel_on(intel_dp);
1129
1130 if (IS_GEN5(dev)) {
1131 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1132 I915_WRITE(PCH_PP_CONTROL, pp);
1133 POSTING_READ(PCH_PP_CONTROL);
1134 }
1135 }
1136
1137 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1138 {
1139 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 u32 pp;
1142 u32 pp_ctrl_reg;
1143
1144 if (!is_edp(intel_dp))
1145 return;
1146
1147 DRM_DEBUG_KMS("Turn eDP power off\n");
1148
1149 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1150
1151 pp = ironlake_get_pp_control(intel_dp);
1152 /* We need to switch off panel power _and_ force vdd, for otherwise some
1153 * panels get very unhappy and cease to work. */
1154 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1155
1156 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1157
1158 I915_WRITE(pp_ctrl_reg, pp);
1159 POSTING_READ(pp_ctrl_reg);
1160
1161 intel_dp->want_panel_vdd = false;
1162
1163 ironlake_wait_panel_off(intel_dp);
1164 }
1165
1166 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1167 {
1168 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1169 struct drm_device *dev = intel_dig_port->base.base.dev;
1170 struct drm_i915_private *dev_priv = dev->dev_private;
1171 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1172 u32 pp;
1173 u32 pp_ctrl_reg;
1174
1175 if (!is_edp(intel_dp))
1176 return;
1177
1178 DRM_DEBUG_KMS("\n");
1179 /*
1180 * If we enable the backlight right away following a panel power
1181 * on, we may see slight flicker as the panel syncs with the eDP
1182 * link. So delay a bit to make sure the image is solid before
1183 * allowing it to appear.
1184 */
1185 msleep(intel_dp->backlight_on_delay);
1186 pp = ironlake_get_pp_control(intel_dp);
1187 pp |= EDP_BLC_ENABLE;
1188
1189 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1190
1191 I915_WRITE(pp_ctrl_reg, pp);
1192 POSTING_READ(pp_ctrl_reg);
1193
1194 intel_panel_enable_backlight(dev, pipe);
1195 }
1196
1197 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1198 {
1199 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1200 struct drm_i915_private *dev_priv = dev->dev_private;
1201 u32 pp;
1202 u32 pp_ctrl_reg;
1203
1204 if (!is_edp(intel_dp))
1205 return;
1206
1207 intel_panel_disable_backlight(dev);
1208
1209 DRM_DEBUG_KMS("\n");
1210 pp = ironlake_get_pp_control(intel_dp);
1211 pp &= ~EDP_BLC_ENABLE;
1212
1213 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1214
1215 I915_WRITE(pp_ctrl_reg, pp);
1216 POSTING_READ(pp_ctrl_reg);
1217 msleep(intel_dp->backlight_off_delay);
1218 }
1219
1220 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1221 {
1222 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1223 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1224 struct drm_device *dev = crtc->dev;
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 u32 dpa_ctl;
1227
1228 assert_pipe_disabled(dev_priv,
1229 to_intel_crtc(crtc)->pipe);
1230
1231 DRM_DEBUG_KMS("\n");
1232 dpa_ctl = I915_READ(DP_A);
1233 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1234 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1235
1236 /* We don't adjust intel_dp->DP while tearing down the link, to
1237 * facilitate link retraining (e.g. after hotplug). Hence clear all
1238 * enable bits here to ensure that we don't enable too much. */
1239 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1240 intel_dp->DP |= DP_PLL_ENABLE;
1241 I915_WRITE(DP_A, intel_dp->DP);
1242 POSTING_READ(DP_A);
1243 udelay(200);
1244 }
1245
1246 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1247 {
1248 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1249 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1250 struct drm_device *dev = crtc->dev;
1251 struct drm_i915_private *dev_priv = dev->dev_private;
1252 u32 dpa_ctl;
1253
1254 assert_pipe_disabled(dev_priv,
1255 to_intel_crtc(crtc)->pipe);
1256
1257 dpa_ctl = I915_READ(DP_A);
1258 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1259 "dp pll off, should be on\n");
1260 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1261
1262 /* We can't rely on the value tracked for the DP register in
1263 * intel_dp->DP because link_down must not change that (otherwise link
1264 * re-training will fail. */
1265 dpa_ctl &= ~DP_PLL_ENABLE;
1266 I915_WRITE(DP_A, dpa_ctl);
1267 POSTING_READ(DP_A);
1268 udelay(200);
1269 }
1270
1271 /* If the sink supports it, try to set the power state appropriately */
1272 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1273 {
1274 int ret, i;
1275
1276 /* Should have a valid DPCD by this point */
1277 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1278 return;
1279
1280 if (mode != DRM_MODE_DPMS_ON) {
1281 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1282 DP_SET_POWER_D3);
1283 if (ret != 1)
1284 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1285 } else {
1286 /*
1287 * When turning on, we need to retry for 1ms to give the sink
1288 * time to wake up.
1289 */
1290 for (i = 0; i < 3; i++) {
1291 ret = intel_dp_aux_native_write_1(intel_dp,
1292 DP_SET_POWER,
1293 DP_SET_POWER_D0);
1294 if (ret == 1)
1295 break;
1296 msleep(1);
1297 }
1298 }
1299 }
1300
1301 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1302 enum pipe *pipe)
1303 {
1304 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1305 enum port port = dp_to_dig_port(intel_dp)->port;
1306 struct drm_device *dev = encoder->base.dev;
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 u32 tmp = I915_READ(intel_dp->output_reg);
1309
1310 if (!(tmp & DP_PORT_EN))
1311 return false;
1312
1313 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1314 *pipe = PORT_TO_PIPE_CPT(tmp);
1315 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1316 *pipe = PORT_TO_PIPE(tmp);
1317 } else {
1318 u32 trans_sel;
1319 u32 trans_dp;
1320 int i;
1321
1322 switch (intel_dp->output_reg) {
1323 case PCH_DP_B:
1324 trans_sel = TRANS_DP_PORT_SEL_B;
1325 break;
1326 case PCH_DP_C:
1327 trans_sel = TRANS_DP_PORT_SEL_C;
1328 break;
1329 case PCH_DP_D:
1330 trans_sel = TRANS_DP_PORT_SEL_D;
1331 break;
1332 default:
1333 return true;
1334 }
1335
1336 for_each_pipe(i) {
1337 trans_dp = I915_READ(TRANS_DP_CTL(i));
1338 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1339 *pipe = i;
1340 return true;
1341 }
1342 }
1343
1344 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1345 intel_dp->output_reg);
1346 }
1347
1348 return true;
1349 }
1350
1351 static void intel_dp_get_config(struct intel_encoder *encoder,
1352 struct intel_crtc_config *pipe_config)
1353 {
1354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1355 u32 tmp, flags = 0;
1356 struct drm_device *dev = encoder->base.dev;
1357 struct drm_i915_private *dev_priv = dev->dev_private;
1358 enum port port = dp_to_dig_port(intel_dp)->port;
1359 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1360
1361 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1362 tmp = I915_READ(intel_dp->output_reg);
1363 if (tmp & DP_SYNC_HS_HIGH)
1364 flags |= DRM_MODE_FLAG_PHSYNC;
1365 else
1366 flags |= DRM_MODE_FLAG_NHSYNC;
1367
1368 if (tmp & DP_SYNC_VS_HIGH)
1369 flags |= DRM_MODE_FLAG_PVSYNC;
1370 else
1371 flags |= DRM_MODE_FLAG_NVSYNC;
1372 } else {
1373 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1374 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1375 flags |= DRM_MODE_FLAG_PHSYNC;
1376 else
1377 flags |= DRM_MODE_FLAG_NHSYNC;
1378
1379 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1380 flags |= DRM_MODE_FLAG_PVSYNC;
1381 else
1382 flags |= DRM_MODE_FLAG_NVSYNC;
1383 }
1384
1385 pipe_config->adjusted_mode.flags |= flags;
1386
1387 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1388 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1389 pipe_config->port_clock = 162000;
1390 else
1391 pipe_config->port_clock = 270000;
1392 }
1393 }
1394
1395 static bool is_edp_psr(struct intel_dp *intel_dp)
1396 {
1397 return is_edp(intel_dp) &&
1398 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1399 }
1400
1401 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1402 {
1403 struct drm_i915_private *dev_priv = dev->dev_private;
1404
1405 if (!IS_HASWELL(dev))
1406 return false;
1407
1408 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1409 }
1410
1411 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1412 struct edp_vsc_psr *vsc_psr)
1413 {
1414 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1415 struct drm_device *dev = dig_port->base.base.dev;
1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1418 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1419 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1420 uint32_t *data = (uint32_t *) vsc_psr;
1421 unsigned int i;
1422
1423 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1424 the video DIP being updated before program video DIP data buffer
1425 registers for DIP being updated. */
1426 I915_WRITE(ctl_reg, 0);
1427 POSTING_READ(ctl_reg);
1428
1429 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1430 if (i < sizeof(struct edp_vsc_psr))
1431 I915_WRITE(data_reg + i, *data++);
1432 else
1433 I915_WRITE(data_reg + i, 0);
1434 }
1435
1436 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1437 POSTING_READ(ctl_reg);
1438 }
1439
1440 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1441 {
1442 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 struct edp_vsc_psr psr_vsc;
1445
1446 if (intel_dp->psr_setup_done)
1447 return;
1448
1449 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1450 memset(&psr_vsc, 0, sizeof(psr_vsc));
1451 psr_vsc.sdp_header.HB0 = 0;
1452 psr_vsc.sdp_header.HB1 = 0x7;
1453 psr_vsc.sdp_header.HB2 = 0x2;
1454 psr_vsc.sdp_header.HB3 = 0x8;
1455 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1456
1457 /* Avoid continuous PSR exit by masking memup and hpd */
1458 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1459 EDP_PSR_DEBUG_MASK_HPD);
1460
1461 intel_dp->psr_setup_done = true;
1462 }
1463
1464 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1465 {
1466 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1468 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1469 int precharge = 0x3;
1470 int msg_size = 5; /* Header(4) + Message(1) */
1471
1472 /* Enable PSR in sink */
1473 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1474 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1475 DP_PSR_ENABLE &
1476 ~DP_PSR_MAIN_LINK_ACTIVE);
1477 else
1478 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1479 DP_PSR_ENABLE |
1480 DP_PSR_MAIN_LINK_ACTIVE);
1481
1482 /* Setup AUX registers */
1483 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1484 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1485 I915_WRITE(EDP_PSR_AUX_CTL,
1486 DP_AUX_CH_CTL_TIME_OUT_400us |
1487 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1488 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1489 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1490 }
1491
1492 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1493 {
1494 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 uint32_t max_sleep_time = 0x1f;
1497 uint32_t idle_frames = 1;
1498 uint32_t val = 0x0;
1499
1500 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1501 val |= EDP_PSR_LINK_STANDBY;
1502 val |= EDP_PSR_TP2_TP3_TIME_0us;
1503 val |= EDP_PSR_TP1_TIME_0us;
1504 val |= EDP_PSR_SKIP_AUX_EXIT;
1505 } else
1506 val |= EDP_PSR_LINK_DISABLE;
1507
1508 I915_WRITE(EDP_PSR_CTL, val |
1509 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1510 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1511 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1512 EDP_PSR_ENABLE);
1513 }
1514
1515 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1516 {
1517 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1518 struct drm_device *dev = dig_port->base.base.dev;
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 struct drm_crtc *crtc = dig_port->base.base.crtc;
1521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1522 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1523 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1524
1525 if (!IS_HASWELL(dev)) {
1526 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1527 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1528 return false;
1529 }
1530
1531 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1532 (dig_port->port != PORT_A)) {
1533 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1534 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1535 return false;
1536 }
1537
1538 if (!is_edp_psr(intel_dp)) {
1539 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1540 dev_priv->no_psr_reason = PSR_NO_SINK;
1541 return false;
1542 }
1543
1544 if (!i915_enable_psr) {
1545 DRM_DEBUG_KMS("PSR disable by flag\n");
1546 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1547 return false;
1548 }
1549
1550 crtc = dig_port->base.base.crtc;
1551 if (crtc == NULL) {
1552 DRM_DEBUG_KMS("crtc not active for PSR\n");
1553 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1554 return false;
1555 }
1556
1557 intel_crtc = to_intel_crtc(crtc);
1558 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1559 DRM_DEBUG_KMS("crtc not active for PSR\n");
1560 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1561 return false;
1562 }
1563
1564 obj = to_intel_framebuffer(crtc->fb)->obj;
1565 if (obj->tiling_mode != I915_TILING_X ||
1566 obj->fence_reg == I915_FENCE_REG_NONE) {
1567 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1568 dev_priv->no_psr_reason = PSR_NOT_TILED;
1569 return false;
1570 }
1571
1572 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1573 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1574 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1575 return false;
1576 }
1577
1578 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1579 S3D_ENABLE) {
1580 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1581 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1582 return false;
1583 }
1584
1585 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1586 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1587 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1588 return false;
1589 }
1590
1591 return true;
1592 }
1593
1594 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1595 {
1596 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1597
1598 if (!intel_edp_psr_match_conditions(intel_dp) ||
1599 intel_edp_is_psr_enabled(dev))
1600 return;
1601
1602 /* Setup PSR once */
1603 intel_edp_psr_setup(intel_dp);
1604
1605 /* Enable PSR on the panel */
1606 intel_edp_psr_enable_sink(intel_dp);
1607
1608 /* Enable PSR on the host */
1609 intel_edp_psr_enable_source(intel_dp);
1610 }
1611
1612 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1613 {
1614 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1615
1616 if (intel_edp_psr_match_conditions(intel_dp) &&
1617 !intel_edp_is_psr_enabled(dev))
1618 intel_edp_psr_do_enable(intel_dp);
1619 }
1620
1621 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1622 {
1623 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625
1626 if (!intel_edp_is_psr_enabled(dev))
1627 return;
1628
1629 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1630
1631 /* Wait till PSR is idle */
1632 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1633 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1634 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1635 }
1636
1637 void intel_edp_psr_update(struct drm_device *dev)
1638 {
1639 struct intel_encoder *encoder;
1640 struct intel_dp *intel_dp = NULL;
1641
1642 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1643 if (encoder->type == INTEL_OUTPUT_EDP) {
1644 intel_dp = enc_to_intel_dp(&encoder->base);
1645
1646 if (!is_edp_psr(intel_dp))
1647 return;
1648
1649 if (!intel_edp_psr_match_conditions(intel_dp))
1650 intel_edp_psr_disable(intel_dp);
1651 else
1652 if (!intel_edp_is_psr_enabled(dev))
1653 intel_edp_psr_do_enable(intel_dp);
1654 }
1655 }
1656
1657 static void intel_disable_dp(struct intel_encoder *encoder)
1658 {
1659 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1660 enum port port = dp_to_dig_port(intel_dp)->port;
1661 struct drm_device *dev = encoder->base.dev;
1662
1663 /* Make sure the panel is off before trying to change the mode. But also
1664 * ensure that we have vdd while we switch off the panel. */
1665 ironlake_edp_panel_vdd_on(intel_dp);
1666 ironlake_edp_backlight_off(intel_dp);
1667 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1668 ironlake_edp_panel_off(intel_dp);
1669
1670 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1671 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1672 intel_dp_link_down(intel_dp);
1673 }
1674
1675 static void intel_post_disable_dp(struct intel_encoder *encoder)
1676 {
1677 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1678 enum port port = dp_to_dig_port(intel_dp)->port;
1679 struct drm_device *dev = encoder->base.dev;
1680
1681 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1682 intel_dp_link_down(intel_dp);
1683 if (!IS_VALLEYVIEW(dev))
1684 ironlake_edp_pll_off(intel_dp);
1685 }
1686 }
1687
1688 static void intel_enable_dp(struct intel_encoder *encoder)
1689 {
1690 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1691 struct drm_device *dev = encoder->base.dev;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1694
1695 if (WARN_ON(dp_reg & DP_PORT_EN))
1696 return;
1697
1698 ironlake_edp_panel_vdd_on(intel_dp);
1699 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1700 intel_dp_start_link_train(intel_dp);
1701 ironlake_edp_panel_on(intel_dp);
1702 ironlake_edp_panel_vdd_off(intel_dp, true);
1703 intel_dp_complete_link_train(intel_dp);
1704 intel_dp_stop_link_train(intel_dp);
1705 ironlake_edp_backlight_on(intel_dp);
1706 }
1707
1708 static void vlv_enable_dp(struct intel_encoder *encoder)
1709 {
1710 }
1711
1712 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1713 {
1714 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1715 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1716
1717 if (dport->port == PORT_A)
1718 ironlake_edp_pll_on(intel_dp);
1719 }
1720
1721 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1722 {
1723 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1724 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1725 struct drm_device *dev = encoder->base.dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1728 int port = vlv_dport_to_channel(dport);
1729 int pipe = intel_crtc->pipe;
1730 u32 val;
1731
1732 mutex_lock(&dev_priv->dpio_lock);
1733
1734 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1735 val = 0;
1736 if (pipe)
1737 val |= (1<<21);
1738 else
1739 val &= ~(1<<21);
1740 val |= 0x001000c4;
1741 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1742 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1743 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1744
1745 mutex_unlock(&dev_priv->dpio_lock);
1746
1747 intel_enable_dp(encoder);
1748
1749 vlv_wait_port_ready(dev_priv, port);
1750 }
1751
1752 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1753 {
1754 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1755 struct drm_device *dev = encoder->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 int port = vlv_dport_to_channel(dport);
1758
1759 if (!IS_VALLEYVIEW(dev))
1760 return;
1761
1762 /* Program Tx lane resets to default */
1763 mutex_lock(&dev_priv->dpio_lock);
1764 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1765 DPIO_PCS_TX_LANE2_RESET |
1766 DPIO_PCS_TX_LANE1_RESET);
1767 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1768 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1769 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1770 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1771 DPIO_PCS_CLK_SOFT_RESET);
1772
1773 /* Fix up inter-pair skew failure */
1774 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1775 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1776 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1777 mutex_unlock(&dev_priv->dpio_lock);
1778 }
1779
1780 /*
1781 * Native read with retry for link status and receiver capability reads for
1782 * cases where the sink may still be asleep.
1783 */
1784 static bool
1785 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1786 uint8_t *recv, int recv_bytes)
1787 {
1788 int ret, i;
1789
1790 /*
1791 * Sinks are *supposed* to come up within 1ms from an off state,
1792 * but we're also supposed to retry 3 times per the spec.
1793 */
1794 for (i = 0; i < 3; i++) {
1795 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1796 recv_bytes);
1797 if (ret == recv_bytes)
1798 return true;
1799 msleep(1);
1800 }
1801
1802 return false;
1803 }
1804
1805 /*
1806 * Fetch AUX CH registers 0x202 - 0x207 which contain
1807 * link status information
1808 */
1809 static bool
1810 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1811 {
1812 return intel_dp_aux_native_read_retry(intel_dp,
1813 DP_LANE0_1_STATUS,
1814 link_status,
1815 DP_LINK_STATUS_SIZE);
1816 }
1817
1818 #if 0
1819 static char *voltage_names[] = {
1820 "0.4V", "0.6V", "0.8V", "1.2V"
1821 };
1822 static char *pre_emph_names[] = {
1823 "0dB", "3.5dB", "6dB", "9.5dB"
1824 };
1825 static char *link_train_names[] = {
1826 "pattern 1", "pattern 2", "idle", "off"
1827 };
1828 #endif
1829
1830 /*
1831 * These are source-specific values; current Intel hardware supports
1832 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1833 */
1834
1835 static uint8_t
1836 intel_dp_voltage_max(struct intel_dp *intel_dp)
1837 {
1838 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1839 enum port port = dp_to_dig_port(intel_dp)->port;
1840
1841 if (IS_VALLEYVIEW(dev))
1842 return DP_TRAIN_VOLTAGE_SWING_1200;
1843 else if (IS_GEN7(dev) && port == PORT_A)
1844 return DP_TRAIN_VOLTAGE_SWING_800;
1845 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1846 return DP_TRAIN_VOLTAGE_SWING_1200;
1847 else
1848 return DP_TRAIN_VOLTAGE_SWING_800;
1849 }
1850
1851 static uint8_t
1852 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1853 {
1854 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1855 enum port port = dp_to_dig_port(intel_dp)->port;
1856
1857 if (HAS_DDI(dev)) {
1858 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1859 case DP_TRAIN_VOLTAGE_SWING_400:
1860 return DP_TRAIN_PRE_EMPHASIS_9_5;
1861 case DP_TRAIN_VOLTAGE_SWING_600:
1862 return DP_TRAIN_PRE_EMPHASIS_6;
1863 case DP_TRAIN_VOLTAGE_SWING_800:
1864 return DP_TRAIN_PRE_EMPHASIS_3_5;
1865 case DP_TRAIN_VOLTAGE_SWING_1200:
1866 default:
1867 return DP_TRAIN_PRE_EMPHASIS_0;
1868 }
1869 } else if (IS_VALLEYVIEW(dev)) {
1870 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1871 case DP_TRAIN_VOLTAGE_SWING_400:
1872 return DP_TRAIN_PRE_EMPHASIS_9_5;
1873 case DP_TRAIN_VOLTAGE_SWING_600:
1874 return DP_TRAIN_PRE_EMPHASIS_6;
1875 case DP_TRAIN_VOLTAGE_SWING_800:
1876 return DP_TRAIN_PRE_EMPHASIS_3_5;
1877 case DP_TRAIN_VOLTAGE_SWING_1200:
1878 default:
1879 return DP_TRAIN_PRE_EMPHASIS_0;
1880 }
1881 } else if (IS_GEN7(dev) && port == PORT_A) {
1882 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1883 case DP_TRAIN_VOLTAGE_SWING_400:
1884 return DP_TRAIN_PRE_EMPHASIS_6;
1885 case DP_TRAIN_VOLTAGE_SWING_600:
1886 case DP_TRAIN_VOLTAGE_SWING_800:
1887 return DP_TRAIN_PRE_EMPHASIS_3_5;
1888 default:
1889 return DP_TRAIN_PRE_EMPHASIS_0;
1890 }
1891 } else {
1892 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1893 case DP_TRAIN_VOLTAGE_SWING_400:
1894 return DP_TRAIN_PRE_EMPHASIS_6;
1895 case DP_TRAIN_VOLTAGE_SWING_600:
1896 return DP_TRAIN_PRE_EMPHASIS_6;
1897 case DP_TRAIN_VOLTAGE_SWING_800:
1898 return DP_TRAIN_PRE_EMPHASIS_3_5;
1899 case DP_TRAIN_VOLTAGE_SWING_1200:
1900 default:
1901 return DP_TRAIN_PRE_EMPHASIS_0;
1902 }
1903 }
1904 }
1905
1906 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1907 {
1908 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1911 unsigned long demph_reg_value, preemph_reg_value,
1912 uniqtranscale_reg_value;
1913 uint8_t train_set = intel_dp->train_set[0];
1914 int port = vlv_dport_to_channel(dport);
1915
1916 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1917 case DP_TRAIN_PRE_EMPHASIS_0:
1918 preemph_reg_value = 0x0004000;
1919 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1920 case DP_TRAIN_VOLTAGE_SWING_400:
1921 demph_reg_value = 0x2B405555;
1922 uniqtranscale_reg_value = 0x552AB83A;
1923 break;
1924 case DP_TRAIN_VOLTAGE_SWING_600:
1925 demph_reg_value = 0x2B404040;
1926 uniqtranscale_reg_value = 0x5548B83A;
1927 break;
1928 case DP_TRAIN_VOLTAGE_SWING_800:
1929 demph_reg_value = 0x2B245555;
1930 uniqtranscale_reg_value = 0x5560B83A;
1931 break;
1932 case DP_TRAIN_VOLTAGE_SWING_1200:
1933 demph_reg_value = 0x2B405555;
1934 uniqtranscale_reg_value = 0x5598DA3A;
1935 break;
1936 default:
1937 return 0;
1938 }
1939 break;
1940 case DP_TRAIN_PRE_EMPHASIS_3_5:
1941 preemph_reg_value = 0x0002000;
1942 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1943 case DP_TRAIN_VOLTAGE_SWING_400:
1944 demph_reg_value = 0x2B404040;
1945 uniqtranscale_reg_value = 0x5552B83A;
1946 break;
1947 case DP_TRAIN_VOLTAGE_SWING_600:
1948 demph_reg_value = 0x2B404848;
1949 uniqtranscale_reg_value = 0x5580B83A;
1950 break;
1951 case DP_TRAIN_VOLTAGE_SWING_800:
1952 demph_reg_value = 0x2B404040;
1953 uniqtranscale_reg_value = 0x55ADDA3A;
1954 break;
1955 default:
1956 return 0;
1957 }
1958 break;
1959 case DP_TRAIN_PRE_EMPHASIS_6:
1960 preemph_reg_value = 0x0000000;
1961 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1962 case DP_TRAIN_VOLTAGE_SWING_400:
1963 demph_reg_value = 0x2B305555;
1964 uniqtranscale_reg_value = 0x5570B83A;
1965 break;
1966 case DP_TRAIN_VOLTAGE_SWING_600:
1967 demph_reg_value = 0x2B2B4040;
1968 uniqtranscale_reg_value = 0x55ADDA3A;
1969 break;
1970 default:
1971 return 0;
1972 }
1973 break;
1974 case DP_TRAIN_PRE_EMPHASIS_9_5:
1975 preemph_reg_value = 0x0006000;
1976 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1977 case DP_TRAIN_VOLTAGE_SWING_400:
1978 demph_reg_value = 0x1B405555;
1979 uniqtranscale_reg_value = 0x55ADDA3A;
1980 break;
1981 default:
1982 return 0;
1983 }
1984 break;
1985 default:
1986 return 0;
1987 }
1988
1989 mutex_lock(&dev_priv->dpio_lock);
1990 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1991 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1992 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1993 uniqtranscale_reg_value);
1994 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1995 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1996 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1997 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1998 mutex_unlock(&dev_priv->dpio_lock);
1999
2000 return 0;
2001 }
2002
2003 static void
2004 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2005 {
2006 uint8_t v = 0;
2007 uint8_t p = 0;
2008 int lane;
2009 uint8_t voltage_max;
2010 uint8_t preemph_max;
2011
2012 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2013 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2014 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2015
2016 if (this_v > v)
2017 v = this_v;
2018 if (this_p > p)
2019 p = this_p;
2020 }
2021
2022 voltage_max = intel_dp_voltage_max(intel_dp);
2023 if (v >= voltage_max)
2024 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2025
2026 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2027 if (p >= preemph_max)
2028 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2029
2030 for (lane = 0; lane < 4; lane++)
2031 intel_dp->train_set[lane] = v | p;
2032 }
2033
2034 static uint32_t
2035 intel_gen4_signal_levels(uint8_t train_set)
2036 {
2037 uint32_t signal_levels = 0;
2038
2039 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2040 case DP_TRAIN_VOLTAGE_SWING_400:
2041 default:
2042 signal_levels |= DP_VOLTAGE_0_4;
2043 break;
2044 case DP_TRAIN_VOLTAGE_SWING_600:
2045 signal_levels |= DP_VOLTAGE_0_6;
2046 break;
2047 case DP_TRAIN_VOLTAGE_SWING_800:
2048 signal_levels |= DP_VOLTAGE_0_8;
2049 break;
2050 case DP_TRAIN_VOLTAGE_SWING_1200:
2051 signal_levels |= DP_VOLTAGE_1_2;
2052 break;
2053 }
2054 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2055 case DP_TRAIN_PRE_EMPHASIS_0:
2056 default:
2057 signal_levels |= DP_PRE_EMPHASIS_0;
2058 break;
2059 case DP_TRAIN_PRE_EMPHASIS_3_5:
2060 signal_levels |= DP_PRE_EMPHASIS_3_5;
2061 break;
2062 case DP_TRAIN_PRE_EMPHASIS_6:
2063 signal_levels |= DP_PRE_EMPHASIS_6;
2064 break;
2065 case DP_TRAIN_PRE_EMPHASIS_9_5:
2066 signal_levels |= DP_PRE_EMPHASIS_9_5;
2067 break;
2068 }
2069 return signal_levels;
2070 }
2071
2072 /* Gen6's DP voltage swing and pre-emphasis control */
2073 static uint32_t
2074 intel_gen6_edp_signal_levels(uint8_t train_set)
2075 {
2076 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2077 DP_TRAIN_PRE_EMPHASIS_MASK);
2078 switch (signal_levels) {
2079 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2080 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2081 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2082 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2083 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2084 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2085 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2086 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2087 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2088 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2089 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2090 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2091 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2092 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2093 default:
2094 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2095 "0x%x\n", signal_levels);
2096 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2097 }
2098 }
2099
2100 /* Gen7's DP voltage swing and pre-emphasis control */
2101 static uint32_t
2102 intel_gen7_edp_signal_levels(uint8_t train_set)
2103 {
2104 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2105 DP_TRAIN_PRE_EMPHASIS_MASK);
2106 switch (signal_levels) {
2107 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2108 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2109 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2110 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2111 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2112 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2113
2114 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2115 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2116 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2117 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2118
2119 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2120 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2121 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2122 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2123
2124 default:
2125 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2126 "0x%x\n", signal_levels);
2127 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2128 }
2129 }
2130
2131 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2132 static uint32_t
2133 intel_hsw_signal_levels(uint8_t train_set)
2134 {
2135 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2136 DP_TRAIN_PRE_EMPHASIS_MASK);
2137 switch (signal_levels) {
2138 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2139 return DDI_BUF_EMP_400MV_0DB_HSW;
2140 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2141 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2142 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2143 return DDI_BUF_EMP_400MV_6DB_HSW;
2144 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2145 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2146
2147 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2148 return DDI_BUF_EMP_600MV_0DB_HSW;
2149 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2150 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2151 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2152 return DDI_BUF_EMP_600MV_6DB_HSW;
2153
2154 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2155 return DDI_BUF_EMP_800MV_0DB_HSW;
2156 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2157 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2158 default:
2159 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2160 "0x%x\n", signal_levels);
2161 return DDI_BUF_EMP_400MV_0DB_HSW;
2162 }
2163 }
2164
2165 /* Properly updates "DP" with the correct signal levels. */
2166 static void
2167 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2168 {
2169 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2170 enum port port = intel_dig_port->port;
2171 struct drm_device *dev = intel_dig_port->base.base.dev;
2172 uint32_t signal_levels, mask;
2173 uint8_t train_set = intel_dp->train_set[0];
2174
2175 if (HAS_DDI(dev)) {
2176 signal_levels = intel_hsw_signal_levels(train_set);
2177 mask = DDI_BUF_EMP_MASK;
2178 } else if (IS_VALLEYVIEW(dev)) {
2179 signal_levels = intel_vlv_signal_levels(intel_dp);
2180 mask = 0;
2181 } else if (IS_GEN7(dev) && port == PORT_A) {
2182 signal_levels = intel_gen7_edp_signal_levels(train_set);
2183 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2184 } else if (IS_GEN6(dev) && port == PORT_A) {
2185 signal_levels = intel_gen6_edp_signal_levels(train_set);
2186 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2187 } else {
2188 signal_levels = intel_gen4_signal_levels(train_set);
2189 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2190 }
2191
2192 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2193
2194 *DP = (*DP & ~mask) | signal_levels;
2195 }
2196
2197 static bool
2198 intel_dp_set_link_train(struct intel_dp *intel_dp,
2199 uint32_t dp_reg_value,
2200 uint8_t dp_train_pat)
2201 {
2202 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2203 struct drm_device *dev = intel_dig_port->base.base.dev;
2204 struct drm_i915_private *dev_priv = dev->dev_private;
2205 enum port port = intel_dig_port->port;
2206 int ret;
2207
2208 if (HAS_DDI(dev)) {
2209 uint32_t temp = I915_READ(DP_TP_CTL(port));
2210
2211 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2212 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2213 else
2214 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2215
2216 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2217 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2218 case DP_TRAINING_PATTERN_DISABLE:
2219 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2220
2221 break;
2222 case DP_TRAINING_PATTERN_1:
2223 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2224 break;
2225 case DP_TRAINING_PATTERN_2:
2226 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2227 break;
2228 case DP_TRAINING_PATTERN_3:
2229 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2230 break;
2231 }
2232 I915_WRITE(DP_TP_CTL(port), temp);
2233
2234 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2235 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2236
2237 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2238 case DP_TRAINING_PATTERN_DISABLE:
2239 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2240 break;
2241 case DP_TRAINING_PATTERN_1:
2242 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2243 break;
2244 case DP_TRAINING_PATTERN_2:
2245 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2246 break;
2247 case DP_TRAINING_PATTERN_3:
2248 DRM_ERROR("DP training pattern 3 not supported\n");
2249 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2250 break;
2251 }
2252
2253 } else {
2254 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2255
2256 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2257 case DP_TRAINING_PATTERN_DISABLE:
2258 dp_reg_value |= DP_LINK_TRAIN_OFF;
2259 break;
2260 case DP_TRAINING_PATTERN_1:
2261 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2262 break;
2263 case DP_TRAINING_PATTERN_2:
2264 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2265 break;
2266 case DP_TRAINING_PATTERN_3:
2267 DRM_ERROR("DP training pattern 3 not supported\n");
2268 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2269 break;
2270 }
2271 }
2272
2273 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2274 POSTING_READ(intel_dp->output_reg);
2275
2276 intel_dp_aux_native_write_1(intel_dp,
2277 DP_TRAINING_PATTERN_SET,
2278 dp_train_pat);
2279
2280 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2281 DP_TRAINING_PATTERN_DISABLE) {
2282 ret = intel_dp_aux_native_write(intel_dp,
2283 DP_TRAINING_LANE0_SET,
2284 intel_dp->train_set,
2285 intel_dp->lane_count);
2286 if (ret != intel_dp->lane_count)
2287 return false;
2288 }
2289
2290 return true;
2291 }
2292
2293 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2294 {
2295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2296 struct drm_device *dev = intel_dig_port->base.base.dev;
2297 struct drm_i915_private *dev_priv = dev->dev_private;
2298 enum port port = intel_dig_port->port;
2299 uint32_t val;
2300
2301 if (!HAS_DDI(dev))
2302 return;
2303
2304 val = I915_READ(DP_TP_CTL(port));
2305 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2306 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2307 I915_WRITE(DP_TP_CTL(port), val);
2308
2309 /*
2310 * On PORT_A we can have only eDP in SST mode. There the only reason
2311 * we need to set idle transmission mode is to work around a HW issue
2312 * where we enable the pipe while not in idle link-training mode.
2313 * In this case there is requirement to wait for a minimum number of
2314 * idle patterns to be sent.
2315 */
2316 if (port == PORT_A)
2317 return;
2318
2319 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2320 1))
2321 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2322 }
2323
2324 /* Enable corresponding port and start training pattern 1 */
2325 void
2326 intel_dp_start_link_train(struct intel_dp *intel_dp)
2327 {
2328 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2329 struct drm_device *dev = encoder->dev;
2330 int i;
2331 uint8_t voltage;
2332 int voltage_tries, loop_tries;
2333 uint32_t DP = intel_dp->DP;
2334
2335 if (HAS_DDI(dev))
2336 intel_ddi_prepare_link_retrain(encoder);
2337
2338 /* Write the link configuration data */
2339 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2340 intel_dp->link_configuration,
2341 DP_LINK_CONFIGURATION_SIZE);
2342
2343 DP |= DP_PORT_EN;
2344
2345 memset(intel_dp->train_set, 0, 4);
2346 voltage = 0xff;
2347 voltage_tries = 0;
2348 loop_tries = 0;
2349 for (;;) {
2350 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2351 uint8_t link_status[DP_LINK_STATUS_SIZE];
2352
2353 intel_dp_set_signal_levels(intel_dp, &DP);
2354
2355 /* Set training pattern 1 */
2356 if (!intel_dp_set_link_train(intel_dp, DP,
2357 DP_TRAINING_PATTERN_1 |
2358 DP_LINK_SCRAMBLING_DISABLE))
2359 break;
2360
2361 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2362 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2363 DRM_ERROR("failed to get link status\n");
2364 break;
2365 }
2366
2367 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2368 DRM_DEBUG_KMS("clock recovery OK\n");
2369 break;
2370 }
2371
2372 /* Check to see if we've tried the max voltage */
2373 for (i = 0; i < intel_dp->lane_count; i++)
2374 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2375 break;
2376 if (i == intel_dp->lane_count) {
2377 ++loop_tries;
2378 if (loop_tries == 5) {
2379 DRM_DEBUG_KMS("too many full retries, give up\n");
2380 break;
2381 }
2382 memset(intel_dp->train_set, 0, 4);
2383 voltage_tries = 0;
2384 continue;
2385 }
2386
2387 /* Check to see if we've tried the same voltage 5 times */
2388 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2389 ++voltage_tries;
2390 if (voltage_tries == 5) {
2391 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2392 break;
2393 }
2394 } else
2395 voltage_tries = 0;
2396 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2397
2398 /* Compute new intel_dp->train_set as requested by target */
2399 intel_get_adjust_train(intel_dp, link_status);
2400 }
2401
2402 intel_dp->DP = DP;
2403 }
2404
2405 void
2406 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2407 {
2408 bool channel_eq = false;
2409 int tries, cr_tries;
2410 uint32_t DP = intel_dp->DP;
2411
2412 /* channel equalization */
2413 tries = 0;
2414 cr_tries = 0;
2415 channel_eq = false;
2416 for (;;) {
2417 uint8_t link_status[DP_LINK_STATUS_SIZE];
2418
2419 if (cr_tries > 5) {
2420 DRM_ERROR("failed to train DP, aborting\n");
2421 intel_dp_link_down(intel_dp);
2422 break;
2423 }
2424
2425 intel_dp_set_signal_levels(intel_dp, &DP);
2426
2427 /* channel eq pattern */
2428 if (!intel_dp_set_link_train(intel_dp, DP,
2429 DP_TRAINING_PATTERN_2 |
2430 DP_LINK_SCRAMBLING_DISABLE))
2431 break;
2432
2433 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2434 if (!intel_dp_get_link_status(intel_dp, link_status))
2435 break;
2436
2437 /* Make sure clock is still ok */
2438 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2439 intel_dp_start_link_train(intel_dp);
2440 cr_tries++;
2441 continue;
2442 }
2443
2444 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2445 channel_eq = true;
2446 break;
2447 }
2448
2449 /* Try 5 times, then try clock recovery if that fails */
2450 if (tries > 5) {
2451 intel_dp_link_down(intel_dp);
2452 intel_dp_start_link_train(intel_dp);
2453 tries = 0;
2454 cr_tries++;
2455 continue;
2456 }
2457
2458 /* Compute new intel_dp->train_set as requested by target */
2459 intel_get_adjust_train(intel_dp, link_status);
2460 ++tries;
2461 }
2462
2463 intel_dp_set_idle_link_train(intel_dp);
2464
2465 intel_dp->DP = DP;
2466
2467 if (channel_eq)
2468 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2469
2470 }
2471
2472 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2473 {
2474 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2475 DP_TRAINING_PATTERN_DISABLE);
2476 }
2477
2478 static void
2479 intel_dp_link_down(struct intel_dp *intel_dp)
2480 {
2481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2482 enum port port = intel_dig_port->port;
2483 struct drm_device *dev = intel_dig_port->base.base.dev;
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485 struct intel_crtc *intel_crtc =
2486 to_intel_crtc(intel_dig_port->base.base.crtc);
2487 uint32_t DP = intel_dp->DP;
2488
2489 /*
2490 * DDI code has a strict mode set sequence and we should try to respect
2491 * it, otherwise we might hang the machine in many different ways. So we
2492 * really should be disabling the port only on a complete crtc_disable
2493 * sequence. This function is just called under two conditions on DDI
2494 * code:
2495 * - Link train failed while doing crtc_enable, and on this case we
2496 * really should respect the mode set sequence and wait for a
2497 * crtc_disable.
2498 * - Someone turned the monitor off and intel_dp_check_link_status
2499 * called us. We don't need to disable the whole port on this case, so
2500 * when someone turns the monitor on again,
2501 * intel_ddi_prepare_link_retrain will take care of redoing the link
2502 * train.
2503 */
2504 if (HAS_DDI(dev))
2505 return;
2506
2507 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2508 return;
2509
2510 DRM_DEBUG_KMS("\n");
2511
2512 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2513 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2514 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2515 } else {
2516 DP &= ~DP_LINK_TRAIN_MASK;
2517 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2518 }
2519 POSTING_READ(intel_dp->output_reg);
2520
2521 /* We don't really know why we're doing this */
2522 intel_wait_for_vblank(dev, intel_crtc->pipe);
2523
2524 if (HAS_PCH_IBX(dev) &&
2525 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2526 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2527
2528 /* Hardware workaround: leaving our transcoder select
2529 * set to transcoder B while it's off will prevent the
2530 * corresponding HDMI output on transcoder A.
2531 *
2532 * Combine this with another hardware workaround:
2533 * transcoder select bit can only be cleared while the
2534 * port is enabled.
2535 */
2536 DP &= ~DP_PIPEB_SELECT;
2537 I915_WRITE(intel_dp->output_reg, DP);
2538
2539 /* Changes to enable or select take place the vblank
2540 * after being written.
2541 */
2542 if (WARN_ON(crtc == NULL)) {
2543 /* We should never try to disable a port without a crtc
2544 * attached. For paranoia keep the code around for a
2545 * bit. */
2546 POSTING_READ(intel_dp->output_reg);
2547 msleep(50);
2548 } else
2549 intel_wait_for_vblank(dev, intel_crtc->pipe);
2550 }
2551
2552 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2553 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2554 POSTING_READ(intel_dp->output_reg);
2555 msleep(intel_dp->panel_power_down_delay);
2556 }
2557
2558 static bool
2559 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2560 {
2561 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2562
2563 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2564 sizeof(intel_dp->dpcd)) == 0)
2565 return false; /* aux transfer failed */
2566
2567 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2568 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2569 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2570
2571 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2572 return false; /* DPCD not present */
2573
2574 /* Check if the panel supports PSR */
2575 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2576 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2577 intel_dp->psr_dpcd,
2578 sizeof(intel_dp->psr_dpcd));
2579 if (is_edp_psr(intel_dp))
2580 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2581 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2582 DP_DWN_STRM_PORT_PRESENT))
2583 return true; /* native DP sink */
2584
2585 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2586 return true; /* no per-port downstream info */
2587
2588 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2589 intel_dp->downstream_ports,
2590 DP_MAX_DOWNSTREAM_PORTS) == 0)
2591 return false; /* downstream port status fetch failed */
2592
2593 return true;
2594 }
2595
2596 static void
2597 intel_dp_probe_oui(struct intel_dp *intel_dp)
2598 {
2599 u8 buf[3];
2600
2601 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2602 return;
2603
2604 ironlake_edp_panel_vdd_on(intel_dp);
2605
2606 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2607 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2608 buf[0], buf[1], buf[2]);
2609
2610 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2611 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2612 buf[0], buf[1], buf[2]);
2613
2614 ironlake_edp_panel_vdd_off(intel_dp, false);
2615 }
2616
2617 static bool
2618 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2619 {
2620 int ret;
2621
2622 ret = intel_dp_aux_native_read_retry(intel_dp,
2623 DP_DEVICE_SERVICE_IRQ_VECTOR,
2624 sink_irq_vector, 1);
2625 if (!ret)
2626 return false;
2627
2628 return true;
2629 }
2630
2631 static void
2632 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2633 {
2634 /* NAK by default */
2635 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2636 }
2637
2638 /*
2639 * According to DP spec
2640 * 5.1.2:
2641 * 1. Read DPCD
2642 * 2. Configure link according to Receiver Capabilities
2643 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2644 * 4. Check link status on receipt of hot-plug interrupt
2645 */
2646
2647 void
2648 intel_dp_check_link_status(struct intel_dp *intel_dp)
2649 {
2650 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2651 u8 sink_irq_vector;
2652 u8 link_status[DP_LINK_STATUS_SIZE];
2653
2654 if (!intel_encoder->connectors_active)
2655 return;
2656
2657 if (WARN_ON(!intel_encoder->base.crtc))
2658 return;
2659
2660 /* Try to read receiver status if the link appears to be up */
2661 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2662 intel_dp_link_down(intel_dp);
2663 return;
2664 }
2665
2666 /* Now read the DPCD to see if it's actually running */
2667 if (!intel_dp_get_dpcd(intel_dp)) {
2668 intel_dp_link_down(intel_dp);
2669 return;
2670 }
2671
2672 /* Try to read the source of the interrupt */
2673 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2674 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2675 /* Clear interrupt source */
2676 intel_dp_aux_native_write_1(intel_dp,
2677 DP_DEVICE_SERVICE_IRQ_VECTOR,
2678 sink_irq_vector);
2679
2680 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2681 intel_dp_handle_test_request(intel_dp);
2682 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2683 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2684 }
2685
2686 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2687 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2688 drm_get_encoder_name(&intel_encoder->base));
2689 intel_dp_start_link_train(intel_dp);
2690 intel_dp_complete_link_train(intel_dp);
2691 intel_dp_stop_link_train(intel_dp);
2692 }
2693 }
2694
2695 /* XXX this is probably wrong for multiple downstream ports */
2696 static enum drm_connector_status
2697 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2698 {
2699 uint8_t *dpcd = intel_dp->dpcd;
2700 bool hpd;
2701 uint8_t type;
2702
2703 if (!intel_dp_get_dpcd(intel_dp))
2704 return connector_status_disconnected;
2705
2706 /* if there's no downstream port, we're done */
2707 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2708 return connector_status_connected;
2709
2710 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2711 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2712 if (hpd) {
2713 uint8_t reg;
2714 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2715 &reg, 1))
2716 return connector_status_unknown;
2717 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2718 : connector_status_disconnected;
2719 }
2720
2721 /* If no HPD, poke DDC gently */
2722 if (drm_probe_ddc(&intel_dp->adapter))
2723 return connector_status_connected;
2724
2725 /* Well we tried, say unknown for unreliable port types */
2726 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2727 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2728 return connector_status_unknown;
2729
2730 /* Anything else is out of spec, warn and ignore */
2731 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2732 return connector_status_disconnected;
2733 }
2734
2735 static enum drm_connector_status
2736 ironlake_dp_detect(struct intel_dp *intel_dp)
2737 {
2738 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2739 struct drm_i915_private *dev_priv = dev->dev_private;
2740 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2741 enum drm_connector_status status;
2742
2743 /* Can't disconnect eDP, but you can close the lid... */
2744 if (is_edp(intel_dp)) {
2745 status = intel_panel_detect(dev);
2746 if (status == connector_status_unknown)
2747 status = connector_status_connected;
2748 return status;
2749 }
2750
2751 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2752 return connector_status_disconnected;
2753
2754 return intel_dp_detect_dpcd(intel_dp);
2755 }
2756
2757 static enum drm_connector_status
2758 g4x_dp_detect(struct intel_dp *intel_dp)
2759 {
2760 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2763 uint32_t bit;
2764
2765 /* Can't disconnect eDP, but you can close the lid... */
2766 if (is_edp(intel_dp)) {
2767 enum drm_connector_status status;
2768
2769 status = intel_panel_detect(dev);
2770 if (status == connector_status_unknown)
2771 status = connector_status_connected;
2772 return status;
2773 }
2774
2775 switch (intel_dig_port->port) {
2776 case PORT_B:
2777 bit = PORTB_HOTPLUG_LIVE_STATUS;
2778 break;
2779 case PORT_C:
2780 bit = PORTC_HOTPLUG_LIVE_STATUS;
2781 break;
2782 case PORT_D:
2783 bit = PORTD_HOTPLUG_LIVE_STATUS;
2784 break;
2785 default:
2786 return connector_status_unknown;
2787 }
2788
2789 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2790 return connector_status_disconnected;
2791
2792 return intel_dp_detect_dpcd(intel_dp);
2793 }
2794
2795 static struct edid *
2796 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2797 {
2798 struct intel_connector *intel_connector = to_intel_connector(connector);
2799
2800 /* use cached edid if we have one */
2801 if (intel_connector->edid) {
2802 struct edid *edid;
2803 int size;
2804
2805 /* invalid edid */
2806 if (IS_ERR(intel_connector->edid))
2807 return NULL;
2808
2809 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2810 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2811 if (!edid)
2812 return NULL;
2813
2814 return edid;
2815 }
2816
2817 return drm_get_edid(connector, adapter);
2818 }
2819
2820 static int
2821 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2822 {
2823 struct intel_connector *intel_connector = to_intel_connector(connector);
2824
2825 /* use cached edid if we have one */
2826 if (intel_connector->edid) {
2827 /* invalid edid */
2828 if (IS_ERR(intel_connector->edid))
2829 return 0;
2830
2831 return intel_connector_update_modes(connector,
2832 intel_connector->edid);
2833 }
2834
2835 return intel_ddc_get_modes(connector, adapter);
2836 }
2837
2838 static enum drm_connector_status
2839 intel_dp_detect(struct drm_connector *connector, bool force)
2840 {
2841 struct intel_dp *intel_dp = intel_attached_dp(connector);
2842 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2843 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2844 struct drm_device *dev = connector->dev;
2845 enum drm_connector_status status;
2846 struct edid *edid = NULL;
2847
2848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2849 connector->base.id, drm_get_connector_name(connector));
2850
2851 intel_dp->has_audio = false;
2852
2853 if (HAS_PCH_SPLIT(dev))
2854 status = ironlake_dp_detect(intel_dp);
2855 else
2856 status = g4x_dp_detect(intel_dp);
2857
2858 if (status != connector_status_connected)
2859 return status;
2860
2861 intel_dp_probe_oui(intel_dp);
2862
2863 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2864 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2865 } else {
2866 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2867 if (edid) {
2868 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2869 kfree(edid);
2870 }
2871 }
2872
2873 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2874 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2875 return connector_status_connected;
2876 }
2877
2878 static int intel_dp_get_modes(struct drm_connector *connector)
2879 {
2880 struct intel_dp *intel_dp = intel_attached_dp(connector);
2881 struct intel_connector *intel_connector = to_intel_connector(connector);
2882 struct drm_device *dev = connector->dev;
2883 int ret;
2884
2885 /* We should parse the EDID data and find out if it has an audio sink
2886 */
2887
2888 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2889 if (ret)
2890 return ret;
2891
2892 /* if eDP has no EDID, fall back to fixed mode */
2893 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2894 struct drm_display_mode *mode;
2895 mode = drm_mode_duplicate(dev,
2896 intel_connector->panel.fixed_mode);
2897 if (mode) {
2898 drm_mode_probed_add(connector, mode);
2899 return 1;
2900 }
2901 }
2902 return 0;
2903 }
2904
2905 static bool
2906 intel_dp_detect_audio(struct drm_connector *connector)
2907 {
2908 struct intel_dp *intel_dp = intel_attached_dp(connector);
2909 struct edid *edid;
2910 bool has_audio = false;
2911
2912 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2913 if (edid) {
2914 has_audio = drm_detect_monitor_audio(edid);
2915 kfree(edid);
2916 }
2917
2918 return has_audio;
2919 }
2920
2921 static int
2922 intel_dp_set_property(struct drm_connector *connector,
2923 struct drm_property *property,
2924 uint64_t val)
2925 {
2926 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2927 struct intel_connector *intel_connector = to_intel_connector(connector);
2928 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2929 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2930 int ret;
2931
2932 ret = drm_object_property_set_value(&connector->base, property, val);
2933 if (ret)
2934 return ret;
2935
2936 if (property == dev_priv->force_audio_property) {
2937 int i = val;
2938 bool has_audio;
2939
2940 if (i == intel_dp->force_audio)
2941 return 0;
2942
2943 intel_dp->force_audio = i;
2944
2945 if (i == HDMI_AUDIO_AUTO)
2946 has_audio = intel_dp_detect_audio(connector);
2947 else
2948 has_audio = (i == HDMI_AUDIO_ON);
2949
2950 if (has_audio == intel_dp->has_audio)
2951 return 0;
2952
2953 intel_dp->has_audio = has_audio;
2954 goto done;
2955 }
2956
2957 if (property == dev_priv->broadcast_rgb_property) {
2958 bool old_auto = intel_dp->color_range_auto;
2959 uint32_t old_range = intel_dp->color_range;
2960
2961 switch (val) {
2962 case INTEL_BROADCAST_RGB_AUTO:
2963 intel_dp->color_range_auto = true;
2964 break;
2965 case INTEL_BROADCAST_RGB_FULL:
2966 intel_dp->color_range_auto = false;
2967 intel_dp->color_range = 0;
2968 break;
2969 case INTEL_BROADCAST_RGB_LIMITED:
2970 intel_dp->color_range_auto = false;
2971 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2972 break;
2973 default:
2974 return -EINVAL;
2975 }
2976
2977 if (old_auto == intel_dp->color_range_auto &&
2978 old_range == intel_dp->color_range)
2979 return 0;
2980
2981 goto done;
2982 }
2983
2984 if (is_edp(intel_dp) &&
2985 property == connector->dev->mode_config.scaling_mode_property) {
2986 if (val == DRM_MODE_SCALE_NONE) {
2987 DRM_DEBUG_KMS("no scaling not supported\n");
2988 return -EINVAL;
2989 }
2990
2991 if (intel_connector->panel.fitting_mode == val) {
2992 /* the eDP scaling property is not changed */
2993 return 0;
2994 }
2995 intel_connector->panel.fitting_mode = val;
2996
2997 goto done;
2998 }
2999
3000 return -EINVAL;
3001
3002 done:
3003 if (intel_encoder->base.crtc)
3004 intel_crtc_restore_mode(intel_encoder->base.crtc);
3005
3006 return 0;
3007 }
3008
3009 static void
3010 intel_dp_connector_destroy(struct drm_connector *connector)
3011 {
3012 struct intel_connector *intel_connector = to_intel_connector(connector);
3013
3014 if (!IS_ERR_OR_NULL(intel_connector->edid))
3015 kfree(intel_connector->edid);
3016
3017 /* Can't call is_edp() since the encoder may have been destroyed
3018 * already. */
3019 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3020 intel_panel_fini(&intel_connector->panel);
3021
3022 drm_sysfs_connector_remove(connector);
3023 drm_connector_cleanup(connector);
3024 kfree(connector);
3025 }
3026
3027 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3028 {
3029 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3030 struct intel_dp *intel_dp = &intel_dig_port->dp;
3031 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3032
3033 i2c_del_adapter(&intel_dp->adapter);
3034 drm_encoder_cleanup(encoder);
3035 if (is_edp(intel_dp)) {
3036 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3037 mutex_lock(&dev->mode_config.mutex);
3038 ironlake_panel_vdd_off_sync(intel_dp);
3039 mutex_unlock(&dev->mode_config.mutex);
3040 }
3041 kfree(intel_dig_port);
3042 }
3043
3044 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3045 .dpms = intel_connector_dpms,
3046 .detect = intel_dp_detect,
3047 .fill_modes = drm_helper_probe_single_connector_modes,
3048 .set_property = intel_dp_set_property,
3049 .destroy = intel_dp_connector_destroy,
3050 };
3051
3052 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3053 .get_modes = intel_dp_get_modes,
3054 .mode_valid = intel_dp_mode_valid,
3055 .best_encoder = intel_best_encoder,
3056 };
3057
3058 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3059 .destroy = intel_dp_encoder_destroy,
3060 };
3061
3062 static void
3063 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3064 {
3065 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3066
3067 intel_dp_check_link_status(intel_dp);
3068 }
3069
3070 /* Return which DP Port should be selected for Transcoder DP control */
3071 int
3072 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3073 {
3074 struct drm_device *dev = crtc->dev;
3075 struct intel_encoder *intel_encoder;
3076 struct intel_dp *intel_dp;
3077
3078 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3079 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3080
3081 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3082 intel_encoder->type == INTEL_OUTPUT_EDP)
3083 return intel_dp->output_reg;
3084 }
3085
3086 return -1;
3087 }
3088
3089 /* check the VBT to see whether the eDP is on DP-D port */
3090 bool intel_dpd_is_edp(struct drm_device *dev)
3091 {
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 struct child_device_config *p_child;
3094 int i;
3095
3096 if (!dev_priv->vbt.child_dev_num)
3097 return false;
3098
3099 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3100 p_child = dev_priv->vbt.child_dev + i;
3101
3102 if (p_child->dvo_port == PORT_IDPD &&
3103 p_child->device_type == DEVICE_TYPE_eDP)
3104 return true;
3105 }
3106 return false;
3107 }
3108
3109 static void
3110 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3111 {
3112 struct intel_connector *intel_connector = to_intel_connector(connector);
3113
3114 intel_attach_force_audio_property(connector);
3115 intel_attach_broadcast_rgb_property(connector);
3116 intel_dp->color_range_auto = true;
3117
3118 if (is_edp(intel_dp)) {
3119 drm_mode_create_scaling_mode_property(connector->dev);
3120 drm_object_attach_property(
3121 &connector->base,
3122 connector->dev->mode_config.scaling_mode_property,
3123 DRM_MODE_SCALE_ASPECT);
3124 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3125 }
3126 }
3127
3128 static void
3129 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3130 struct intel_dp *intel_dp,
3131 struct edp_power_seq *out)
3132 {
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 struct edp_power_seq cur, vbt, spec, final;
3135 u32 pp_on, pp_off, pp_div, pp;
3136 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3137
3138 if (HAS_PCH_SPLIT(dev)) {
3139 pp_control_reg = PCH_PP_CONTROL;
3140 pp_on_reg = PCH_PP_ON_DELAYS;
3141 pp_off_reg = PCH_PP_OFF_DELAYS;
3142 pp_div_reg = PCH_PP_DIVISOR;
3143 } else {
3144 pp_control_reg = PIPEA_PP_CONTROL;
3145 pp_on_reg = PIPEA_PP_ON_DELAYS;
3146 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3147 pp_div_reg = PIPEA_PP_DIVISOR;
3148 }
3149
3150 /* Workaround: Need to write PP_CONTROL with the unlock key as
3151 * the very first thing. */
3152 pp = ironlake_get_pp_control(intel_dp);
3153 I915_WRITE(pp_control_reg, pp);
3154
3155 pp_on = I915_READ(pp_on_reg);
3156 pp_off = I915_READ(pp_off_reg);
3157 pp_div = I915_READ(pp_div_reg);
3158
3159 /* Pull timing values out of registers */
3160 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3161 PANEL_POWER_UP_DELAY_SHIFT;
3162
3163 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3164 PANEL_LIGHT_ON_DELAY_SHIFT;
3165
3166 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3167 PANEL_LIGHT_OFF_DELAY_SHIFT;
3168
3169 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3170 PANEL_POWER_DOWN_DELAY_SHIFT;
3171
3172 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3173 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3174
3175 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3176 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3177
3178 vbt = dev_priv->vbt.edp_pps;
3179
3180 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3181 * our hw here, which are all in 100usec. */
3182 spec.t1_t3 = 210 * 10;
3183 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3184 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3185 spec.t10 = 500 * 10;
3186 /* This one is special and actually in units of 100ms, but zero
3187 * based in the hw (so we need to add 100 ms). But the sw vbt
3188 * table multiplies it with 1000 to make it in units of 100usec,
3189 * too. */
3190 spec.t11_t12 = (510 + 100) * 10;
3191
3192 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3193 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3194
3195 /* Use the max of the register settings and vbt. If both are
3196 * unset, fall back to the spec limits. */
3197 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3198 spec.field : \
3199 max(cur.field, vbt.field))
3200 assign_final(t1_t3);
3201 assign_final(t8);
3202 assign_final(t9);
3203 assign_final(t10);
3204 assign_final(t11_t12);
3205 #undef assign_final
3206
3207 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3208 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3209 intel_dp->backlight_on_delay = get_delay(t8);
3210 intel_dp->backlight_off_delay = get_delay(t9);
3211 intel_dp->panel_power_down_delay = get_delay(t10);
3212 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3213 #undef get_delay
3214
3215 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3216 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3217 intel_dp->panel_power_cycle_delay);
3218
3219 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3220 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3221
3222 if (out)
3223 *out = final;
3224 }
3225
3226 static void
3227 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3228 struct intel_dp *intel_dp,
3229 struct edp_power_seq *seq)
3230 {
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 u32 pp_on, pp_off, pp_div, port_sel = 0;
3233 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3234 int pp_on_reg, pp_off_reg, pp_div_reg;
3235
3236 if (HAS_PCH_SPLIT(dev)) {
3237 pp_on_reg = PCH_PP_ON_DELAYS;
3238 pp_off_reg = PCH_PP_OFF_DELAYS;
3239 pp_div_reg = PCH_PP_DIVISOR;
3240 } else {
3241 pp_on_reg = PIPEA_PP_ON_DELAYS;
3242 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3243 pp_div_reg = PIPEA_PP_DIVISOR;
3244 }
3245
3246 /* And finally store the new values in the power sequencer. */
3247 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3248 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3249 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3250 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3251 /* Compute the divisor for the pp clock, simply match the Bspec
3252 * formula. */
3253 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3254 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3255 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3256
3257 /* Haswell doesn't have any port selection bits for the panel
3258 * power sequencer any more. */
3259 if (IS_VALLEYVIEW(dev)) {
3260 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3261 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3262 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3263 port_sel = PANEL_POWER_PORT_DP_A;
3264 else
3265 port_sel = PANEL_POWER_PORT_DP_D;
3266 }
3267
3268 pp_on |= port_sel;
3269
3270 I915_WRITE(pp_on_reg, pp_on);
3271 I915_WRITE(pp_off_reg, pp_off);
3272 I915_WRITE(pp_div_reg, pp_div);
3273
3274 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3275 I915_READ(pp_on_reg),
3276 I915_READ(pp_off_reg),
3277 I915_READ(pp_div_reg));
3278 }
3279
3280 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3281 struct intel_connector *intel_connector)
3282 {
3283 struct drm_connector *connector = &intel_connector->base;
3284 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3285 struct drm_device *dev = intel_dig_port->base.base.dev;
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 struct drm_display_mode *fixed_mode = NULL;
3288 struct edp_power_seq power_seq = { 0 };
3289 bool has_dpcd;
3290 struct drm_display_mode *scan;
3291 struct edid *edid;
3292
3293 if (!is_edp(intel_dp))
3294 return true;
3295
3296 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3297
3298 /* Cache DPCD and EDID for edp. */
3299 ironlake_edp_panel_vdd_on(intel_dp);
3300 has_dpcd = intel_dp_get_dpcd(intel_dp);
3301 ironlake_edp_panel_vdd_off(intel_dp, false);
3302
3303 if (has_dpcd) {
3304 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3305 dev_priv->no_aux_handshake =
3306 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3307 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3308 } else {
3309 /* if this fails, presume the device is a ghost */
3310 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3311 return false;
3312 }
3313
3314 /* We now know it's not a ghost, init power sequence regs. */
3315 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3316 &power_seq);
3317
3318 ironlake_edp_panel_vdd_on(intel_dp);
3319 edid = drm_get_edid(connector, &intel_dp->adapter);
3320 if (edid) {
3321 if (drm_add_edid_modes(connector, edid)) {
3322 drm_mode_connector_update_edid_property(connector,
3323 edid);
3324 drm_edid_to_eld(connector, edid);
3325 } else {
3326 kfree(edid);
3327 edid = ERR_PTR(-EINVAL);
3328 }
3329 } else {
3330 edid = ERR_PTR(-ENOENT);
3331 }
3332 intel_connector->edid = edid;
3333
3334 /* prefer fixed mode from EDID if available */
3335 list_for_each_entry(scan, &connector->probed_modes, head) {
3336 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3337 fixed_mode = drm_mode_duplicate(dev, scan);
3338 break;
3339 }
3340 }
3341
3342 /* fallback to VBT if available for eDP */
3343 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3344 fixed_mode = drm_mode_duplicate(dev,
3345 dev_priv->vbt.lfp_lvds_vbt_mode);
3346 if (fixed_mode)
3347 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3348 }
3349
3350 ironlake_edp_panel_vdd_off(intel_dp, false);
3351
3352 intel_panel_init(&intel_connector->panel, fixed_mode);
3353 intel_panel_setup_backlight(connector);
3354
3355 return true;
3356 }
3357
3358 bool
3359 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3360 struct intel_connector *intel_connector)
3361 {
3362 struct drm_connector *connector = &intel_connector->base;
3363 struct intel_dp *intel_dp = &intel_dig_port->dp;
3364 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3365 struct drm_device *dev = intel_encoder->base.dev;
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 enum port port = intel_dig_port->port;
3368 const char *name = NULL;
3369 int type, error;
3370
3371 /* Preserve the current hw state. */
3372 intel_dp->DP = I915_READ(intel_dp->output_reg);
3373 intel_dp->attached_connector = intel_connector;
3374
3375 type = DRM_MODE_CONNECTOR_DisplayPort;
3376 /*
3377 * FIXME : We need to initialize built-in panels before external panels.
3378 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3379 */
3380 switch (port) {
3381 case PORT_A:
3382 type = DRM_MODE_CONNECTOR_eDP;
3383 break;
3384 case PORT_C:
3385 if (IS_VALLEYVIEW(dev))
3386 type = DRM_MODE_CONNECTOR_eDP;
3387 break;
3388 case PORT_D:
3389 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3390 type = DRM_MODE_CONNECTOR_eDP;
3391 break;
3392 default: /* silence GCC warning */
3393 break;
3394 }
3395
3396 /*
3397 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3398 * for DP the encoder type can be set by the caller to
3399 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3400 */
3401 if (type == DRM_MODE_CONNECTOR_eDP)
3402 intel_encoder->type = INTEL_OUTPUT_EDP;
3403
3404 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3405 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3406 port_name(port));
3407
3408 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3409 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3410
3411 connector->interlace_allowed = true;
3412 connector->doublescan_allowed = 0;
3413
3414 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3415 ironlake_panel_vdd_work);
3416
3417 intel_connector_attach_encoder(intel_connector, intel_encoder);
3418 drm_sysfs_connector_add(connector);
3419
3420 if (HAS_DDI(dev))
3421 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3422 else
3423 intel_connector->get_hw_state = intel_connector_get_hw_state;
3424
3425 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3426 if (HAS_DDI(dev)) {
3427 switch (intel_dig_port->port) {
3428 case PORT_A:
3429 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3430 break;
3431 case PORT_B:
3432 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3433 break;
3434 case PORT_C:
3435 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3436 break;
3437 case PORT_D:
3438 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3439 break;
3440 default:
3441 BUG();
3442 }
3443 }
3444
3445 /* Set up the DDC bus. */
3446 switch (port) {
3447 case PORT_A:
3448 intel_encoder->hpd_pin = HPD_PORT_A;
3449 name = "DPDDC-A";
3450 break;
3451 case PORT_B:
3452 intel_encoder->hpd_pin = HPD_PORT_B;
3453 name = "DPDDC-B";
3454 break;
3455 case PORT_C:
3456 intel_encoder->hpd_pin = HPD_PORT_C;
3457 name = "DPDDC-C";
3458 break;
3459 case PORT_D:
3460 intel_encoder->hpd_pin = HPD_PORT_D;
3461 name = "DPDDC-D";
3462 break;
3463 default:
3464 BUG();
3465 }
3466
3467 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3468 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3469 error, port_name(port));
3470
3471 intel_dp->psr_setup_done = false;
3472
3473 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3474 i2c_del_adapter(&intel_dp->adapter);
3475 if (is_edp(intel_dp)) {
3476 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3477 mutex_lock(&dev->mode_config.mutex);
3478 ironlake_panel_vdd_off_sync(intel_dp);
3479 mutex_unlock(&dev->mode_config.mutex);
3480 }
3481 drm_sysfs_connector_remove(connector);
3482 drm_connector_cleanup(connector);
3483 return false;
3484 }
3485
3486 intel_dp_add_properties(intel_dp, connector);
3487
3488 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3489 * 0xd. Failure to do so will result in spurious interrupts being
3490 * generated on the port when a cable is not attached.
3491 */
3492 if (IS_G4X(dev) && !IS_GM45(dev)) {
3493 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3494 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3495 }
3496
3497 return true;
3498 }
3499
3500 void
3501 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3502 {
3503 struct intel_digital_port *intel_dig_port;
3504 struct intel_encoder *intel_encoder;
3505 struct drm_encoder *encoder;
3506 struct intel_connector *intel_connector;
3507
3508 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3509 if (!intel_dig_port)
3510 return;
3511
3512 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3513 if (!intel_connector) {
3514 kfree(intel_dig_port);
3515 return;
3516 }
3517
3518 intel_encoder = &intel_dig_port->base;
3519 encoder = &intel_encoder->base;
3520
3521 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3522 DRM_MODE_ENCODER_TMDS);
3523
3524 intel_encoder->compute_config = intel_dp_compute_config;
3525 intel_encoder->mode_set = intel_dp_mode_set;
3526 intel_encoder->disable = intel_disable_dp;
3527 intel_encoder->post_disable = intel_post_disable_dp;
3528 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3529 intel_encoder->get_config = intel_dp_get_config;
3530 if (IS_VALLEYVIEW(dev)) {
3531 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3532 intel_encoder->pre_enable = vlv_pre_enable_dp;
3533 intel_encoder->enable = vlv_enable_dp;
3534 } else {
3535 intel_encoder->pre_enable = intel_pre_enable_dp;
3536 intel_encoder->enable = intel_enable_dp;
3537 }
3538
3539 intel_dig_port->port = port;
3540 intel_dig_port->dp.output_reg = output_reg;
3541
3542 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3543 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3544 intel_encoder->cloneable = false;
3545 intel_encoder->hot_plug = intel_dp_hot_plug;
3546
3547 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3548 drm_encoder_cleanup(encoder);
3549 kfree(intel_dig_port);
3550 kfree(intel_connector);
3551 }
3552 }
Linux kernel - Deliverables
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