2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
45 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
46 #define IS_PCH_eDP(dp_priv) ((dp_priv)->is_pch_edp)
48 struct intel_dp_priv
{
51 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
57 struct intel_encoder
*intel_encoder
;
58 struct i2c_adapter adapter
;
59 struct i2c_algo_dp_aux_data algo
;
64 intel_dp_link_train(struct intel_encoder
*intel_encoder
, uint32_t DP
,
65 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
]);
68 intel_dp_link_down(struct intel_encoder
*intel_encoder
, uint32_t DP
);
71 intel_edp_link_config (struct intel_encoder
*intel_encoder
,
72 int *lane_num
, int *link_bw
)
74 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
76 *lane_num
= dp_priv
->lane_count
;
77 if (dp_priv
->link_bw
== DP_LINK_BW_1_62
)
79 else if (dp_priv
->link_bw
== DP_LINK_BW_2_7
)
84 intel_dp_max_lane_count(struct intel_encoder
*intel_encoder
)
86 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
87 int max_lane_count
= 4;
89 if (dp_priv
->dpcd
[0] >= 0x11) {
90 max_lane_count
= dp_priv
->dpcd
[2] & 0x1f;
91 switch (max_lane_count
) {
92 case 1: case 2: case 4:
98 return max_lane_count
;
102 intel_dp_max_link_bw(struct intel_encoder
*intel_encoder
)
104 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
105 int max_link_bw
= dp_priv
->dpcd
[1];
107 switch (max_link_bw
) {
108 case DP_LINK_BW_1_62
:
112 max_link_bw
= DP_LINK_BW_1_62
;
119 intel_dp_link_clock(uint8_t link_bw
)
121 if (link_bw
== DP_LINK_BW_2_7
)
127 /* I think this is a fiction */
129 intel_dp_link_required(struct drm_device
*dev
,
130 struct intel_encoder
*intel_encoder
, int pixel_clock
)
132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
135 if (IS_eDP(intel_encoder
) || IS_PCH_eDP(dp_priv
))
136 return (pixel_clock
* dev_priv
->edp_bpp
) / 8;
138 return pixel_clock
* 3;
142 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
144 return (max_link_clock
* max_lanes
* 8) / 10;
148 intel_dp_mode_valid(struct drm_connector
*connector
,
149 struct drm_display_mode
*mode
)
151 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
152 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
153 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder
));
154 int max_lanes
= intel_dp_max_lane_count(intel_encoder
);
156 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
157 which are outside spec tolerances but somehow work by magic */
158 if (!IS_eDP(intel_encoder
) &&
159 (intel_dp_link_required(connector
->dev
, intel_encoder
, mode
->clock
)
160 > intel_dp_max_data_rate(max_link_clock
, max_lanes
)))
161 return MODE_CLOCK_HIGH
;
163 if (mode
->clock
< 10000)
164 return MODE_CLOCK_LOW
;
170 pack_aux(uint8_t *src
, int src_bytes
)
177 for (i
= 0; i
< src_bytes
; i
++)
178 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
183 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
188 for (i
= 0; i
< dst_bytes
; i
++)
189 dst
[i
] = src
>> ((3-i
) * 8);
192 /* hrawclock is 1/4 the FSB frequency */
194 intel_hrawclk(struct drm_device
*dev
)
196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
199 clkcfg
= I915_READ(CLKCFG
);
200 switch (clkcfg
& CLKCFG_FSB_MASK
) {
209 case CLKCFG_FSB_1067
:
211 case CLKCFG_FSB_1333
:
213 /* these two are just a guess; one of them might be right */
214 case CLKCFG_FSB_1600
:
215 case CLKCFG_FSB_1600_ALT
:
223 intel_dp_aux_ch(struct intel_encoder
*intel_encoder
,
224 uint8_t *send
, int send_bytes
,
225 uint8_t *recv
, int recv_size
)
227 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
228 uint32_t output_reg
= dp_priv
->output_reg
;
229 struct drm_device
*dev
= intel_encoder
->enc
.dev
;
230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
231 uint32_t ch_ctl
= output_reg
+ 0x10;
232 uint32_t ch_data
= ch_ctl
+ 4;
237 uint32_t aux_clock_divider
;
240 /* The clock divider is based off the hrawclk,
241 * and would like to run at 2MHz. So, take the
242 * hrawclk value and divide by 2 and use that
244 if (IS_eDP(intel_encoder
)) {
246 aux_clock_divider
= 200; /* SNB eDP input clock at 400Mhz */
248 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
249 } else if (HAS_PCH_SPLIT(dev
))
250 aux_clock_divider
= 62; /* IRL input clock fixed at 125Mhz */
252 aux_clock_divider
= intel_hrawclk(dev
) / 2;
259 /* Must try at least 3 times according to DP spec */
260 for (try = 0; try < 5; try++) {
261 /* Load the send data into the aux channel data registers */
262 for (i
= 0; i
< send_bytes
; i
+= 4) {
263 uint32_t d
= pack_aux(send
+ i
, send_bytes
- i
);
265 I915_WRITE(ch_data
+ i
, d
);
268 ctl
= (DP_AUX_CH_CTL_SEND_BUSY
|
269 DP_AUX_CH_CTL_TIME_OUT_400us
|
270 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
271 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
272 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
274 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
275 DP_AUX_CH_CTL_RECEIVE_ERROR
);
277 /* Send the command and wait for it to complete */
278 I915_WRITE(ch_ctl
, ctl
);
279 (void) I915_READ(ch_ctl
);
282 status
= I915_READ(ch_ctl
);
283 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
287 /* Clear done status and any errors */
288 I915_WRITE(ch_ctl
, (status
|
290 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
291 DP_AUX_CH_CTL_RECEIVE_ERROR
));
292 (void) I915_READ(ch_ctl
);
293 if ((status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) == 0)
297 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
298 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
302 /* Check for timeout or receive error.
303 * Timeouts occur when the sink is not connected
305 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
306 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
310 /* Timeouts occur when the device isn't connected, so they're
311 * "normal" -- don't fill the kernel log with these */
312 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
313 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
317 /* Unload any bytes sent back from the other side */
318 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
319 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
321 if (recv_bytes
> recv_size
)
322 recv_bytes
= recv_size
;
324 for (i
= 0; i
< recv_bytes
; i
+= 4) {
325 uint32_t d
= I915_READ(ch_data
+ i
);
327 unpack_aux(d
, recv
+ i
, recv_bytes
- i
);
333 /* Write data to the aux channel in native mode */
335 intel_dp_aux_native_write(struct intel_encoder
*intel_encoder
,
336 uint16_t address
, uint8_t *send
, int send_bytes
)
345 msg
[0] = AUX_NATIVE_WRITE
<< 4;
346 msg
[1] = address
>> 8;
347 msg
[2] = address
& 0xff;
348 msg
[3] = send_bytes
- 1;
349 memcpy(&msg
[4], send
, send_bytes
);
350 msg_bytes
= send_bytes
+ 4;
352 ret
= intel_dp_aux_ch(intel_encoder
, msg
, msg_bytes
, &ack
, 1);
355 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
357 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
365 /* Write a single byte to the aux channel in native mode */
367 intel_dp_aux_native_write_1(struct intel_encoder
*intel_encoder
,
368 uint16_t address
, uint8_t byte
)
370 return intel_dp_aux_native_write(intel_encoder
, address
, &byte
, 1);
373 /* read bytes from a native aux channel */
375 intel_dp_aux_native_read(struct intel_encoder
*intel_encoder
,
376 uint16_t address
, uint8_t *recv
, int recv_bytes
)
385 msg
[0] = AUX_NATIVE_READ
<< 4;
386 msg
[1] = address
>> 8;
387 msg
[2] = address
& 0xff;
388 msg
[3] = recv_bytes
- 1;
391 reply_bytes
= recv_bytes
+ 1;
394 ret
= intel_dp_aux_ch(intel_encoder
, msg
, msg_bytes
,
401 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
402 memcpy(recv
, reply
+ 1, ret
- 1);
405 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
413 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
414 uint8_t write_byte
, uint8_t *read_byte
)
416 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
417 struct intel_dp_priv
*dp_priv
= container_of(adapter
,
418 struct intel_dp_priv
,
420 struct intel_encoder
*intel_encoder
= dp_priv
->intel_encoder
;
421 uint16_t address
= algo_data
->address
;
428 /* Set up the command byte */
429 if (mode
& MODE_I2C_READ
)
430 msg
[0] = AUX_I2C_READ
<< 4;
432 msg
[0] = AUX_I2C_WRITE
<< 4;
434 if (!(mode
& MODE_I2C_STOP
))
435 msg
[0] |= AUX_I2C_MOT
<< 4;
437 msg
[1] = address
>> 8;
459 ret
= intel_dp_aux_ch(intel_encoder
,
463 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
466 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
467 case AUX_I2C_REPLY_ACK
:
468 if (mode
== MODE_I2C_READ
) {
469 *read_byte
= reply
[1];
471 return reply_bytes
- 1;
472 case AUX_I2C_REPLY_NACK
:
473 DRM_DEBUG_KMS("aux_ch nack\n");
475 case AUX_I2C_REPLY_DEFER
:
476 DRM_DEBUG_KMS("aux_ch defer\n");
480 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply
[0]);
487 intel_dp_i2c_init(struct intel_encoder
*intel_encoder
,
488 struct intel_connector
*intel_connector
, const char *name
)
490 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
492 DRM_DEBUG_KMS("i2c_init %s\n", name
);
493 dp_priv
->algo
.running
= false;
494 dp_priv
->algo
.address
= 0;
495 dp_priv
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
497 memset(&dp_priv
->adapter
, '\0', sizeof (dp_priv
->adapter
));
498 dp_priv
->adapter
.owner
= THIS_MODULE
;
499 dp_priv
->adapter
.class = I2C_CLASS_DDC
;
500 strncpy (dp_priv
->adapter
.name
, name
, sizeof(dp_priv
->adapter
.name
) - 1);
501 dp_priv
->adapter
.name
[sizeof(dp_priv
->adapter
.name
) - 1] = '\0';
502 dp_priv
->adapter
.algo_data
= &dp_priv
->algo
;
503 dp_priv
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
505 return i2c_dp_aux_add_bus(&dp_priv
->adapter
);
509 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
510 struct drm_display_mode
*adjusted_mode
)
512 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
513 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
514 struct drm_device
*dev
= encoder
->dev
;
515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
516 int lane_count
, clock
;
517 int max_lane_count
= intel_dp_max_lane_count(intel_encoder
);
518 int max_clock
= intel_dp_max_link_bw(intel_encoder
) == DP_LINK_BW_2_7
? 1 : 0;
519 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
521 if ((IS_eDP(intel_encoder
) || IS_PCH_eDP(dp_priv
)) &&
522 dev_priv
->panel_fixed_mode
) {
523 struct drm_display_mode
*fixed_mode
= dev_priv
->panel_fixed_mode
;
525 adjusted_mode
->hdisplay
= fixed_mode
->hdisplay
;
526 adjusted_mode
->hsync_start
= fixed_mode
->hsync_start
;
527 adjusted_mode
->hsync_end
= fixed_mode
->hsync_end
;
528 adjusted_mode
->htotal
= fixed_mode
->htotal
;
530 adjusted_mode
->vdisplay
= fixed_mode
->vdisplay
;
531 adjusted_mode
->vsync_start
= fixed_mode
->vsync_start
;
532 adjusted_mode
->vsync_end
= fixed_mode
->vsync_end
;
533 adjusted_mode
->vtotal
= fixed_mode
->vtotal
;
535 adjusted_mode
->clock
= fixed_mode
->clock
;
536 drm_mode_set_crtcinfo(adjusted_mode
, CRTC_INTERLACE_HALVE_V
);
539 * the mode->clock is used to calculate the Data&Link M/N
540 * of the pipe. For the eDP the fixed clock should be used.
542 mode
->clock
= dev_priv
->panel_fixed_mode
->clock
;
545 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
546 for (clock
= 0; clock
<= max_clock
; clock
++) {
547 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
549 if (intel_dp_link_required(encoder
->dev
, intel_encoder
, mode
->clock
)
551 dp_priv
->link_bw
= bws
[clock
];
552 dp_priv
->lane_count
= lane_count
;
553 adjusted_mode
->clock
= intel_dp_link_clock(dp_priv
->link_bw
);
554 DRM_DEBUG_KMS("Display port link bw %02x lane "
555 "count %d clock %d\n",
556 dp_priv
->link_bw
, dp_priv
->lane_count
,
557 adjusted_mode
->clock
);
563 if (IS_eDP(intel_encoder
) || IS_PCH_eDP(dp_priv
)) {
564 /* okay we failed just pick the highest */
565 dp_priv
->lane_count
= max_lane_count
;
566 dp_priv
->link_bw
= bws
[max_clock
];
567 adjusted_mode
->clock
= intel_dp_link_clock(dp_priv
->link_bw
);
568 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
569 "count %d clock %d\n",
570 dp_priv
->link_bw
, dp_priv
->lane_count
,
571 adjusted_mode
->clock
);
577 struct intel_dp_m_n
{
586 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
588 while (*num
> 0xffffff || *den
> 0xffffff) {
595 intel_dp_compute_m_n(int bpp
,
599 struct intel_dp_m_n
*m_n
)
602 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
603 m_n
->gmch_n
= link_clock
* nlanes
;
604 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
605 m_n
->link_m
= pixel_clock
;
606 m_n
->link_n
= link_clock
;
607 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
610 bool intel_pch_has_edp(struct drm_crtc
*crtc
)
612 struct drm_device
*dev
= crtc
->dev
;
613 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
614 struct drm_encoder
*encoder
;
616 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
617 struct intel_encoder
*intel_encoder
;
618 struct intel_dp_priv
*dp_priv
;
620 if (!encoder
|| encoder
->crtc
!= crtc
)
623 intel_encoder
= enc_to_intel_encoder(encoder
);
624 dp_priv
= intel_encoder
->dev_priv
;
626 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
)
627 return dp_priv
->is_pch_edp
;
633 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
634 struct drm_display_mode
*adjusted_mode
)
636 struct drm_device
*dev
= crtc
->dev
;
637 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
638 struct drm_encoder
*encoder
;
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
640 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
641 int lane_count
= 4, bpp
= 24;
642 struct intel_dp_m_n m_n
;
645 * Find the lane count in the intel_encoder private
647 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
648 struct intel_encoder
*intel_encoder
;
649 struct intel_dp_priv
*dp_priv
;
651 if (encoder
->crtc
!= crtc
)
654 intel_encoder
= enc_to_intel_encoder(encoder
);
655 dp_priv
= intel_encoder
->dev_priv
;
657 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
658 lane_count
= dp_priv
->lane_count
;
659 if (IS_PCH_eDP(dp_priv
))
660 bpp
= dev_priv
->edp_bpp
;
666 * Compute the GMCH and Link ratios. The '3' here is
667 * the number of bytes_per_pixel post-LUT, which we always
668 * set up for 8-bits of R/G/B, or 3 bytes total.
670 intel_dp_compute_m_n(bpp
, lane_count
,
671 mode
->clock
, adjusted_mode
->clock
, &m_n
);
673 if (HAS_PCH_SPLIT(dev
)) {
674 if (intel_crtc
->pipe
== 0) {
675 I915_WRITE(TRANSA_DATA_M1
,
676 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
678 I915_WRITE(TRANSA_DATA_N1
, m_n
.gmch_n
);
679 I915_WRITE(TRANSA_DP_LINK_M1
, m_n
.link_m
);
680 I915_WRITE(TRANSA_DP_LINK_N1
, m_n
.link_n
);
682 I915_WRITE(TRANSB_DATA_M1
,
683 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
685 I915_WRITE(TRANSB_DATA_N1
, m_n
.gmch_n
);
686 I915_WRITE(TRANSB_DP_LINK_M1
, m_n
.link_m
);
687 I915_WRITE(TRANSB_DP_LINK_N1
, m_n
.link_n
);
690 if (intel_crtc
->pipe
== 0) {
691 I915_WRITE(PIPEA_GMCH_DATA_M
,
692 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
694 I915_WRITE(PIPEA_GMCH_DATA_N
,
696 I915_WRITE(PIPEA_DP_LINK_M
, m_n
.link_m
);
697 I915_WRITE(PIPEA_DP_LINK_N
, m_n
.link_n
);
699 I915_WRITE(PIPEB_GMCH_DATA_M
,
700 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
702 I915_WRITE(PIPEB_GMCH_DATA_N
,
704 I915_WRITE(PIPEB_DP_LINK_M
, m_n
.link_m
);
705 I915_WRITE(PIPEB_DP_LINK_N
, m_n
.link_n
);
711 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
712 struct drm_display_mode
*adjusted_mode
)
714 struct drm_device
*dev
= encoder
->dev
;
715 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
716 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
717 struct drm_crtc
*crtc
= intel_encoder
->enc
.crtc
;
718 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
720 dp_priv
->DP
= (DP_VOLTAGE_0_4
|
723 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
724 dp_priv
->DP
|= DP_SYNC_HS_HIGH
;
725 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
726 dp_priv
->DP
|= DP_SYNC_VS_HIGH
;
728 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_encoder
))
729 dp_priv
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
731 dp_priv
->DP
|= DP_LINK_TRAIN_OFF
;
733 switch (dp_priv
->lane_count
) {
735 dp_priv
->DP
|= DP_PORT_WIDTH_1
;
738 dp_priv
->DP
|= DP_PORT_WIDTH_2
;
741 dp_priv
->DP
|= DP_PORT_WIDTH_4
;
744 if (dp_priv
->has_audio
)
745 dp_priv
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
747 memset(dp_priv
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
748 dp_priv
->link_configuration
[0] = dp_priv
->link_bw
;
749 dp_priv
->link_configuration
[1] = dp_priv
->lane_count
;
752 * Check for DPCD version > 1.1 and enhanced framing support
754 if (dp_priv
->dpcd
[0] >= 0x11 && (dp_priv
->dpcd
[2] & DP_ENHANCED_FRAME_CAP
)) {
755 dp_priv
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
756 dp_priv
->DP
|= DP_ENHANCED_FRAMING
;
759 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
760 if (intel_crtc
->pipe
== 1 && !HAS_PCH_CPT(dev
))
761 dp_priv
->DP
|= DP_PIPEB_SELECT
;
763 if (IS_eDP(intel_encoder
)) {
764 /* don't miss out required setting for eDP */
765 dp_priv
->DP
|= DP_PLL_ENABLE
;
766 if (adjusted_mode
->clock
< 200000)
767 dp_priv
->DP
|= DP_PLL_FREQ_160MHZ
;
769 dp_priv
->DP
|= DP_PLL_FREQ_270MHZ
;
773 static void ironlake_edp_panel_on (struct drm_device
*dev
)
775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
776 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5000);
779 pp_status
= I915_READ(PCH_PP_STATUS
);
780 if (pp_status
& PP_ON
)
783 pp
= I915_READ(PCH_PP_CONTROL
);
784 pp
|= PANEL_UNLOCK_REGS
| POWER_TARGET_ON
;
785 I915_WRITE(PCH_PP_CONTROL
, pp
);
787 pp_status
= I915_READ(PCH_PP_STATUS
);
788 } while (((pp_status
& PP_ON
) == 0) && !time_after(jiffies
, timeout
));
790 if (time_after(jiffies
, timeout
))
791 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status
);
793 pp
&= ~(PANEL_UNLOCK_REGS
| EDP_FORCE_VDD
);
794 I915_WRITE(PCH_PP_CONTROL
, pp
);
797 static void ironlake_edp_panel_off (struct drm_device
*dev
)
799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
800 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5000);
803 pp
= I915_READ(PCH_PP_CONTROL
);
804 pp
&= ~POWER_TARGET_ON
;
805 I915_WRITE(PCH_PP_CONTROL
, pp
);
807 pp_status
= I915_READ(PCH_PP_STATUS
);
808 } while ((pp_status
& PP_ON
) && !time_after(jiffies
, timeout
));
810 if (time_after(jiffies
, timeout
))
811 DRM_DEBUG_KMS("panel off wait timed out\n");
813 /* Make sure VDD is enabled so DP AUX will work */
815 I915_WRITE(PCH_PP_CONTROL
, pp
);
818 static void ironlake_edp_backlight_on (struct drm_device
*dev
)
820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
824 pp
= I915_READ(PCH_PP_CONTROL
);
825 pp
|= EDP_BLC_ENABLE
;
826 I915_WRITE(PCH_PP_CONTROL
, pp
);
829 static void ironlake_edp_backlight_off (struct drm_device
*dev
)
831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
835 pp
= I915_READ(PCH_PP_CONTROL
);
836 pp
&= ~EDP_BLC_ENABLE
;
837 I915_WRITE(PCH_PP_CONTROL
, pp
);
841 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
843 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
844 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
845 struct drm_device
*dev
= encoder
->dev
;
846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
847 uint32_t dp_reg
= I915_READ(dp_priv
->output_reg
);
849 if (mode
!= DRM_MODE_DPMS_ON
) {
850 if (dp_reg
& DP_PORT_EN
) {
851 intel_dp_link_down(intel_encoder
, dp_priv
->DP
);
852 if (IS_eDP(intel_encoder
) || IS_PCH_eDP(dp_priv
)) {
853 ironlake_edp_backlight_off(dev
);
854 ironlake_edp_panel_off(dev
);
858 if (!(dp_reg
& DP_PORT_EN
)) {
859 intel_dp_link_train(intel_encoder
, dp_priv
->DP
, dp_priv
->link_configuration
);
860 if (IS_eDP(intel_encoder
) || IS_PCH_eDP(dp_priv
)) {
861 ironlake_edp_panel_on(dev
);
862 ironlake_edp_backlight_on(dev
);
866 dp_priv
->dpms_mode
= mode
;
870 * Fetch AUX CH registers 0x202 - 0x207 which contain
871 * link status information
874 intel_dp_get_link_status(struct intel_encoder
*intel_encoder
,
875 uint8_t link_status
[DP_LINK_STATUS_SIZE
])
879 ret
= intel_dp_aux_native_read(intel_encoder
,
881 link_status
, DP_LINK_STATUS_SIZE
);
882 if (ret
!= DP_LINK_STATUS_SIZE
)
888 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
891 return link_status
[r
- DP_LANE0_1_STATUS
];
895 intel_get_adjust_request_voltage(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
898 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
899 int s
= ((lane
& 1) ?
900 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
901 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
902 uint8_t l
= intel_dp_link_status(link_status
, i
);
904 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
908 intel_get_adjust_request_pre_emphasis(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
911 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
912 int s
= ((lane
& 1) ?
913 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
914 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
915 uint8_t l
= intel_dp_link_status(link_status
, i
);
917 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
922 static char *voltage_names
[] = {
923 "0.4V", "0.6V", "0.8V", "1.2V"
925 static char *pre_emph_names
[] = {
926 "0dB", "3.5dB", "6dB", "9.5dB"
928 static char *link_train_names
[] = {
929 "pattern 1", "pattern 2", "idle", "off"
934 * These are source-specific values; current Intel hardware supports
935 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
937 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
940 intel_dp_pre_emphasis_max(uint8_t voltage_swing
)
942 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
943 case DP_TRAIN_VOLTAGE_SWING_400
:
944 return DP_TRAIN_PRE_EMPHASIS_6
;
945 case DP_TRAIN_VOLTAGE_SWING_600
:
946 return DP_TRAIN_PRE_EMPHASIS_6
;
947 case DP_TRAIN_VOLTAGE_SWING_800
:
948 return DP_TRAIN_PRE_EMPHASIS_3_5
;
949 case DP_TRAIN_VOLTAGE_SWING_1200
:
951 return DP_TRAIN_PRE_EMPHASIS_0
;
956 intel_get_adjust_train(struct intel_encoder
*intel_encoder
,
957 uint8_t link_status
[DP_LINK_STATUS_SIZE
],
959 uint8_t train_set
[4])
965 for (lane
= 0; lane
< lane_count
; lane
++) {
966 uint8_t this_v
= intel_get_adjust_request_voltage(link_status
, lane
);
967 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(link_status
, lane
);
975 if (v
>= I830_DP_VOLTAGE_MAX
)
976 v
= I830_DP_VOLTAGE_MAX
| DP_TRAIN_MAX_SWING_REACHED
;
978 if (p
>= intel_dp_pre_emphasis_max(v
))
979 p
= intel_dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
981 for (lane
= 0; lane
< 4; lane
++)
982 train_set
[lane
] = v
| p
;
986 intel_dp_signal_levels(uint8_t train_set
, int lane_count
)
988 uint32_t signal_levels
= 0;
990 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
991 case DP_TRAIN_VOLTAGE_SWING_400
:
993 signal_levels
|= DP_VOLTAGE_0_4
;
995 case DP_TRAIN_VOLTAGE_SWING_600
:
996 signal_levels
|= DP_VOLTAGE_0_6
;
998 case DP_TRAIN_VOLTAGE_SWING_800
:
999 signal_levels
|= DP_VOLTAGE_0_8
;
1001 case DP_TRAIN_VOLTAGE_SWING_1200
:
1002 signal_levels
|= DP_VOLTAGE_1_2
;
1005 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1006 case DP_TRAIN_PRE_EMPHASIS_0
:
1008 signal_levels
|= DP_PRE_EMPHASIS_0
;
1010 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1011 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1013 case DP_TRAIN_PRE_EMPHASIS_6
:
1014 signal_levels
|= DP_PRE_EMPHASIS_6
;
1016 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1017 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1020 return signal_levels
;
1023 /* Gen6's DP voltage swing and pre-emphasis control */
1025 intel_gen6_edp_signal_levels(uint8_t train_set
)
1027 switch (train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|DP_TRAIN_PRE_EMPHASIS_MASK
)) {
1028 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1029 return EDP_LINK_TRAIN_400MV_0DB_SNB_B
;
1030 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1031 return EDP_LINK_TRAIN_400MV_6DB_SNB_B
;
1032 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1033 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B
;
1034 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1035 return EDP_LINK_TRAIN_800MV_0DB_SNB_B
;
1037 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1038 return EDP_LINK_TRAIN_400MV_0DB_SNB_B
;
1043 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1046 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
1047 int s
= (lane
& 1) * 4;
1048 uint8_t l
= intel_dp_link_status(link_status
, i
);
1050 return (l
>> s
) & 0xf;
1053 /* Check for clock recovery is done on all channels */
1055 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1058 uint8_t lane_status
;
1060 for (lane
= 0; lane
< lane_count
; lane
++) {
1061 lane_status
= intel_get_lane_status(link_status
, lane
);
1062 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1068 /* Check to see if channel eq is done on all channels */
1069 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1070 DP_LANE_CHANNEL_EQ_DONE|\
1071 DP_LANE_SYMBOL_LOCKED)
1073 intel_channel_eq_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1076 uint8_t lane_status
;
1079 lane_align
= intel_dp_link_status(link_status
,
1080 DP_LANE_ALIGN_STATUS_UPDATED
);
1081 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1083 for (lane
= 0; lane
< lane_count
; lane
++) {
1084 lane_status
= intel_get_lane_status(link_status
, lane
);
1085 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1092 intel_dp_set_link_train(struct intel_encoder
*intel_encoder
,
1093 uint32_t dp_reg_value
,
1094 uint8_t dp_train_pat
,
1095 uint8_t train_set
[4],
1098 struct drm_device
*dev
= intel_encoder
->enc
.dev
;
1099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1100 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1103 I915_WRITE(dp_priv
->output_reg
, dp_reg_value
);
1104 POSTING_READ(dp_priv
->output_reg
);
1106 intel_wait_for_vblank(dev
);
1108 intel_dp_aux_native_write_1(intel_encoder
,
1109 DP_TRAINING_PATTERN_SET
,
1112 ret
= intel_dp_aux_native_write(intel_encoder
,
1113 DP_TRAINING_LANE0_SET
, train_set
, 4);
1121 intel_dp_link_train(struct intel_encoder
*intel_encoder
, uint32_t DP
,
1122 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
])
1124 struct drm_device
*dev
= intel_encoder
->enc
.dev
;
1125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1126 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1127 uint8_t train_set
[4];
1128 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1131 bool clock_recovery
= false;
1132 bool channel_eq
= false;
1137 /* Write the link configuration data */
1138 intel_dp_aux_native_write(intel_encoder
, DP_LINK_BW_SET
,
1139 link_configuration
, DP_LINK_CONFIGURATION_SIZE
);
1142 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_encoder
))
1143 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1145 DP
&= ~DP_LINK_TRAIN_MASK
;
1146 memset(train_set
, 0, 4);
1149 clock_recovery
= false;
1151 /* Use train_set[0] to set the voltage and pre emphasis values */
1152 uint32_t signal_levels
;
1153 if (IS_GEN6(dev
) && IS_eDP(intel_encoder
)) {
1154 signal_levels
= intel_gen6_edp_signal_levels(train_set
[0]);
1155 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1157 signal_levels
= intel_dp_signal_levels(train_set
[0], dp_priv
->lane_count
);
1158 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1161 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_encoder
))
1162 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1164 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1166 if (!intel_dp_set_link_train(intel_encoder
, reg
,
1167 DP_TRAINING_PATTERN_1
, train_set
, first
))
1170 /* Set training pattern 1 */
1173 if (!intel_dp_get_link_status(intel_encoder
, link_status
))
1176 if (intel_clock_recovery_ok(link_status
, dp_priv
->lane_count
)) {
1177 clock_recovery
= true;
1181 /* Check to see if we've tried the max voltage */
1182 for (i
= 0; i
< dp_priv
->lane_count
; i
++)
1183 if ((train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1185 if (i
== dp_priv
->lane_count
)
1188 /* Check to see if we've tried the same voltage 5 times */
1189 if ((train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1195 voltage
= train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1197 /* Compute new train_set as requested by target */
1198 intel_get_adjust_train(intel_encoder
, link_status
, dp_priv
->lane_count
, train_set
);
1201 /* channel equalization */
1205 /* Use train_set[0] to set the voltage and pre emphasis values */
1206 uint32_t signal_levels
;
1208 if (IS_GEN6(dev
) && IS_eDP(intel_encoder
)) {
1209 signal_levels
= intel_gen6_edp_signal_levels(train_set
[0]);
1210 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1212 signal_levels
= intel_dp_signal_levels(train_set
[0], dp_priv
->lane_count
);
1213 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1216 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_encoder
))
1217 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1219 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1221 /* channel eq pattern */
1222 if (!intel_dp_set_link_train(intel_encoder
, reg
,
1223 DP_TRAINING_PATTERN_2
, train_set
,
1228 if (!intel_dp_get_link_status(intel_encoder
, link_status
))
1231 if (intel_channel_eq_ok(link_status
, dp_priv
->lane_count
)) {
1240 /* Compute new train_set as requested by target */
1241 intel_get_adjust_train(intel_encoder
, link_status
, dp_priv
->lane_count
, train_set
);
1245 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_encoder
))
1246 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1248 reg
= DP
| DP_LINK_TRAIN_OFF
;
1250 I915_WRITE(dp_priv
->output_reg
, reg
);
1251 POSTING_READ(dp_priv
->output_reg
);
1252 intel_dp_aux_native_write_1(intel_encoder
,
1253 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1257 intel_dp_link_down(struct intel_encoder
*intel_encoder
, uint32_t DP
)
1259 struct drm_device
*dev
= intel_encoder
->enc
.dev
;
1260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1261 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1263 DRM_DEBUG_KMS("\n");
1265 if (IS_eDP(intel_encoder
)) {
1266 DP
&= ~DP_PLL_ENABLE
;
1267 I915_WRITE(dp_priv
->output_reg
, DP
);
1268 POSTING_READ(dp_priv
->output_reg
);
1272 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_encoder
)) {
1273 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1274 I915_WRITE(dp_priv
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1275 POSTING_READ(dp_priv
->output_reg
);
1277 DP
&= ~DP_LINK_TRAIN_MASK
;
1278 I915_WRITE(dp_priv
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1279 POSTING_READ(dp_priv
->output_reg
);
1284 if (IS_eDP(intel_encoder
))
1285 DP
|= DP_LINK_TRAIN_OFF
;
1286 I915_WRITE(dp_priv
->output_reg
, DP
& ~DP_PORT_EN
);
1287 POSTING_READ(dp_priv
->output_reg
);
1291 * According to DP spec
1294 * 2. Configure link according to Receiver Capabilities
1295 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1296 * 4. Check link status on receipt of hot-plug interrupt
1300 intel_dp_check_link_status(struct intel_encoder
*intel_encoder
)
1302 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1303 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1305 if (!intel_encoder
->enc
.crtc
)
1308 if (!intel_dp_get_link_status(intel_encoder
, link_status
)) {
1309 intel_dp_link_down(intel_encoder
, dp_priv
->DP
);
1313 if (!intel_channel_eq_ok(link_status
, dp_priv
->lane_count
))
1314 intel_dp_link_train(intel_encoder
, dp_priv
->DP
, dp_priv
->link_configuration
);
1317 static enum drm_connector_status
1318 ironlake_dp_detect(struct drm_connector
*connector
)
1320 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1321 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
1322 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1323 enum drm_connector_status status
;
1325 status
= connector_status_disconnected
;
1326 if (intel_dp_aux_native_read(intel_encoder
,
1327 0x000, dp_priv
->dpcd
,
1328 sizeof (dp_priv
->dpcd
)) == sizeof (dp_priv
->dpcd
))
1330 if (dp_priv
->dpcd
[0] != 0)
1331 status
= connector_status_connected
;
1333 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv
->dpcd
[0],
1334 dp_priv
->dpcd
[1], dp_priv
->dpcd
[2], dp_priv
->dpcd
[3]);
1339 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1341 * \return true if DP port is connected.
1342 * \return false if DP port is disconnected.
1344 static enum drm_connector_status
1345 intel_dp_detect(struct drm_connector
*connector
)
1347 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1348 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
1349 struct drm_device
*dev
= intel_encoder
->enc
.dev
;
1350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1351 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1353 enum drm_connector_status status
;
1355 dp_priv
->has_audio
= false;
1357 if (HAS_PCH_SPLIT(dev
))
1358 return ironlake_dp_detect(connector
);
1360 switch (dp_priv
->output_reg
) {
1362 bit
= DPB_HOTPLUG_INT_STATUS
;
1365 bit
= DPC_HOTPLUG_INT_STATUS
;
1368 bit
= DPD_HOTPLUG_INT_STATUS
;
1371 return connector_status_unknown
;
1374 temp
= I915_READ(PORT_HOTPLUG_STAT
);
1376 if ((temp
& bit
) == 0)
1377 return connector_status_disconnected
;
1379 status
= connector_status_disconnected
;
1380 if (intel_dp_aux_native_read(intel_encoder
,
1381 0x000, dp_priv
->dpcd
,
1382 sizeof (dp_priv
->dpcd
)) == sizeof (dp_priv
->dpcd
))
1384 if (dp_priv
->dpcd
[0] != 0)
1385 status
= connector_status_connected
;
1390 static int intel_dp_get_modes(struct drm_connector
*connector
)
1392 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1393 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
1394 struct drm_device
*dev
= intel_encoder
->enc
.dev
;
1395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1396 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1399 /* We should parse the EDID data and find out if it has an audio sink
1402 ret
= intel_ddc_get_modes(connector
, intel_encoder
->ddc_bus
);
1404 if ((IS_eDP(intel_encoder
) || IS_PCH_eDP(dp_priv
)) &&
1405 !dev_priv
->panel_fixed_mode
) {
1406 struct drm_display_mode
*newmode
;
1407 list_for_each_entry(newmode
, &connector
->probed_modes
,
1409 if (newmode
->type
& DRM_MODE_TYPE_PREFERRED
) {
1410 dev_priv
->panel_fixed_mode
=
1411 drm_mode_duplicate(dev
, newmode
);
1420 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1421 if (IS_eDP(intel_encoder
) || IS_PCH_eDP(dp_priv
)) {
1422 if (dev_priv
->panel_fixed_mode
!= NULL
) {
1423 struct drm_display_mode
*mode
;
1424 mode
= drm_mode_duplicate(dev
, dev_priv
->panel_fixed_mode
);
1425 drm_mode_probed_add(connector
, mode
);
1433 intel_dp_destroy (struct drm_connector
*connector
)
1435 drm_sysfs_connector_remove(connector
);
1436 drm_connector_cleanup(connector
);
1440 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
1441 .dpms
= intel_dp_dpms
,
1442 .mode_fixup
= intel_dp_mode_fixup
,
1443 .prepare
= intel_encoder_prepare
,
1444 .mode_set
= intel_dp_mode_set
,
1445 .commit
= intel_encoder_commit
,
1448 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
1449 .dpms
= drm_helper_connector_dpms
,
1450 .detect
= intel_dp_detect
,
1451 .fill_modes
= drm_helper_probe_single_connector_modes
,
1452 .destroy
= intel_dp_destroy
,
1455 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
1456 .get_modes
= intel_dp_get_modes
,
1457 .mode_valid
= intel_dp_mode_valid
,
1458 .best_encoder
= intel_attached_encoder
,
1461 static void intel_dp_enc_destroy(struct drm_encoder
*encoder
)
1463 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
1465 if (intel_encoder
->i2c_bus
)
1466 intel_i2c_destroy(intel_encoder
->i2c_bus
);
1467 drm_encoder_cleanup(encoder
);
1468 kfree(intel_encoder
);
1471 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
1472 .destroy
= intel_dp_enc_destroy
,
1476 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
1478 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1480 if (dp_priv
->dpms_mode
== DRM_MODE_DPMS_ON
)
1481 intel_dp_check_link_status(intel_encoder
);
1484 /* Return which DP Port should be selected for Transcoder DP control */
1486 intel_trans_dp_port_sel (struct drm_crtc
*crtc
)
1488 struct drm_device
*dev
= crtc
->dev
;
1489 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1490 struct drm_encoder
*encoder
;
1491 struct intel_encoder
*intel_encoder
= NULL
;
1493 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
1494 if (encoder
->crtc
!= crtc
)
1497 intel_encoder
= enc_to_intel_encoder(encoder
);
1498 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1499 struct intel_dp_priv
*dp_priv
= intel_encoder
->dev_priv
;
1500 return dp_priv
->output_reg
;
1506 /* check the VBT to see whether the eDP is on DP-D port */
1507 bool intel_dpd_is_edp(struct drm_device
*dev
)
1509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 struct child_device_config
*p_child
;
1513 if (!dev_priv
->child_dev_num
)
1516 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
1517 p_child
= dev_priv
->child_dev
+ i
;
1519 if (p_child
->dvo_port
== PORT_IDPD
&&
1520 p_child
->device_type
== DEVICE_TYPE_eDP
)
1527 intel_dp_init(struct drm_device
*dev
, int output_reg
)
1529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1530 struct drm_connector
*connector
;
1531 struct intel_encoder
*intel_encoder
;
1532 struct intel_connector
*intel_connector
;
1533 struct intel_dp_priv
*dp_priv
;
1534 const char *name
= NULL
;
1537 intel_encoder
= kcalloc(sizeof(struct intel_encoder
) +
1538 sizeof(struct intel_dp_priv
), 1, GFP_KERNEL
);
1542 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1543 if (!intel_connector
) {
1544 kfree(intel_encoder
);
1548 dp_priv
= (struct intel_dp_priv
*)(intel_encoder
+ 1);
1550 if (HAS_PCH_SPLIT(dev
) && (output_reg
== PCH_DP_D
))
1551 if (intel_dpd_is_edp(dev
))
1552 dp_priv
->is_pch_edp
= true;
1554 if (output_reg
== DP_A
|| IS_PCH_eDP(dp_priv
)) {
1555 type
= DRM_MODE_CONNECTOR_eDP
;
1556 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
1558 type
= DRM_MODE_CONNECTOR_DisplayPort
;
1559 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
1562 connector
= &intel_connector
->base
;
1563 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
1564 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
1566 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1568 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
1569 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
1570 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
1571 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
1572 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
1573 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
1575 if (IS_eDP(intel_encoder
))
1576 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
1578 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
1579 connector
->interlace_allowed
= true;
1580 connector
->doublescan_allowed
= 0;
1582 dp_priv
->intel_encoder
= intel_encoder
;
1583 dp_priv
->output_reg
= output_reg
;
1584 dp_priv
->has_audio
= false;
1585 dp_priv
->dpms_mode
= DRM_MODE_DPMS_ON
;
1586 intel_encoder
->dev_priv
= dp_priv
;
1588 drm_encoder_init(dev
, &intel_encoder
->enc
, &intel_dp_enc_funcs
,
1589 DRM_MODE_ENCODER_TMDS
);
1590 drm_encoder_helper_add(&intel_encoder
->enc
, &intel_dp_helper_funcs
);
1592 drm_mode_connector_attach_encoder(&intel_connector
->base
,
1593 &intel_encoder
->enc
);
1594 drm_sysfs_connector_add(connector
);
1596 /* Set up the DDC bus. */
1597 switch (output_reg
) {
1603 dev_priv
->hotplug_supported_mask
|=
1604 HDMIB_HOTPLUG_INT_STATUS
;
1609 dev_priv
->hotplug_supported_mask
|=
1610 HDMIC_HOTPLUG_INT_STATUS
;
1615 dev_priv
->hotplug_supported_mask
|=
1616 HDMID_HOTPLUG_INT_STATUS
;
1621 intel_dp_i2c_init(intel_encoder
, intel_connector
, name
);
1623 intel_encoder
->ddc_bus
= &dp_priv
->adapter
;
1624 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
1626 if (output_reg
== DP_A
|| IS_PCH_eDP(dp_priv
)) {
1627 /* initialize panel mode from VBT if available for eDP */
1628 if (dev_priv
->lfp_lvds_vbt_mode
) {
1629 dev_priv
->panel_fixed_mode
=
1630 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
1631 if (dev_priv
->panel_fixed_mode
) {
1632 dev_priv
->panel_fixed_mode
->type
|=
1633 DRM_MODE_TYPE_PREFERRED
;
1638 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1639 * 0xd. Failure to do so will result in spurious interrupts being
1640 * generated on the port when a cable is not attached.
1642 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1643 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1644 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);