2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
193 static enum drm_mode_status
194 intel_dp_mode_valid(struct drm_connector
*connector
,
195 struct drm_display_mode
*mode
)
197 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
198 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
199 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
200 int target_clock
= mode
->clock
;
201 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
202 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
204 if (is_edp(intel_dp
) && fixed_mode
) {
205 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
208 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
211 target_clock
= fixed_mode
->clock
;
214 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
215 max_lanes
= intel_dp_max_lane_count(intel_dp
);
217 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
218 mode_rate
= intel_dp_link_required(target_clock
, 18);
220 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
221 return MODE_CLOCK_HIGH
;
223 if (mode
->clock
< 10000)
224 return MODE_CLOCK_LOW
;
226 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
227 return MODE_H_ILLEGAL
;
232 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
239 for (i
= 0; i
< src_bytes
; i
++)
240 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
244 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
249 for (i
= 0; i
< dst_bytes
; i
++)
250 dst
[i
] = src
>> ((3-i
) * 8);
254 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
255 struct intel_dp
*intel_dp
);
257 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
258 struct intel_dp
*intel_dp
);
260 intel_dp_pps_init(struct drm_device
*dev
, struct intel_dp
*intel_dp
);
262 static void pps_lock(struct intel_dp
*intel_dp
)
264 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
265 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
266 struct drm_device
*dev
= encoder
->base
.dev
;
267 struct drm_i915_private
*dev_priv
= to_i915(dev
);
268 enum intel_display_power_domain power_domain
;
271 * See vlv_power_sequencer_reset() why we need
272 * a power domain reference here.
274 power_domain
= intel_display_port_aux_power_domain(encoder
);
275 intel_display_power_get(dev_priv
, power_domain
);
277 mutex_lock(&dev_priv
->pps_mutex
);
280 static void pps_unlock(struct intel_dp
*intel_dp
)
282 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
283 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
284 struct drm_device
*dev
= encoder
->base
.dev
;
285 struct drm_i915_private
*dev_priv
= to_i915(dev
);
286 enum intel_display_power_domain power_domain
;
288 mutex_unlock(&dev_priv
->pps_mutex
);
290 power_domain
= intel_display_port_aux_power_domain(encoder
);
291 intel_display_power_put(dev_priv
, power_domain
);
295 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
297 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
298 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
299 struct drm_i915_private
*dev_priv
= to_i915(dev
);
300 enum pipe pipe
= intel_dp
->pps_pipe
;
301 bool pll_enabled
, release_cl_override
= false;
302 enum dpio_phy phy
= DPIO_PHY(pipe
);
303 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
306 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
307 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
308 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
311 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
312 pipe_name(pipe
), port_name(intel_dig_port
->port
));
314 /* Preserve the BIOS-computed detected bit. This is
315 * supposed to be read-only.
317 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
318 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
319 DP
|= DP_PORT_WIDTH(1);
320 DP
|= DP_LINK_TRAIN_PAT_1
;
322 if (IS_CHERRYVIEW(dev
))
323 DP
|= DP_PIPE_SELECT_CHV(pipe
);
324 else if (pipe
== PIPE_B
)
325 DP
|= DP_PIPEB_SELECT
;
327 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
330 * The DPLL for the pipe must be enabled for this to work.
331 * So enable temporarily it if it's not already enabled.
334 release_cl_override
= IS_CHERRYVIEW(dev
) &&
335 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
337 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
338 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
339 DRM_ERROR("Failed to force on pll for pipe %c!\n",
346 * Similar magic as in intel_dp_enable_port().
347 * We _must_ do this port enable + disable trick
348 * to make this power seqeuencer lock onto the port.
349 * Otherwise even VDD force bit won't work.
351 I915_WRITE(intel_dp
->output_reg
, DP
);
352 POSTING_READ(intel_dp
->output_reg
);
354 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
355 POSTING_READ(intel_dp
->output_reg
);
357 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
358 POSTING_READ(intel_dp
->output_reg
);
361 vlv_force_pll_off(dev
, pipe
);
363 if (release_cl_override
)
364 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
369 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
371 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
372 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
373 struct drm_i915_private
*dev_priv
= to_i915(dev
);
374 struct intel_encoder
*encoder
;
375 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
378 lockdep_assert_held(&dev_priv
->pps_mutex
);
380 /* We should never land here with regular DP ports */
381 WARN_ON(!is_edp(intel_dp
));
383 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
384 return intel_dp
->pps_pipe
;
387 * We don't have power sequencer currently.
388 * Pick one that's not used by other ports.
390 for_each_intel_encoder(dev
, encoder
) {
391 struct intel_dp
*tmp
;
393 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
396 tmp
= enc_to_intel_dp(&encoder
->base
);
398 if (tmp
->pps_pipe
!= INVALID_PIPE
)
399 pipes
&= ~(1 << tmp
->pps_pipe
);
403 * Didn't find one. This should not happen since there
404 * are two power sequencers and up to two eDP ports.
406 if (WARN_ON(pipes
== 0))
409 pipe
= ffs(pipes
) - 1;
411 vlv_steal_power_sequencer(dev
, pipe
);
412 intel_dp
->pps_pipe
= pipe
;
414 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
415 pipe_name(intel_dp
->pps_pipe
),
416 port_name(intel_dig_port
->port
));
418 /* init power sequencer on this pipe and port */
419 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
420 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
423 * Even vdd force doesn't work until we've made
424 * the power sequencer lock in on the port.
426 vlv_power_sequencer_kick(intel_dp
);
428 return intel_dp
->pps_pipe
;
432 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
434 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
435 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
436 struct drm_i915_private
*dev_priv
= to_i915(dev
);
438 lockdep_assert_held(&dev_priv
->pps_mutex
);
440 /* We should never land here with regular DP ports */
441 WARN_ON(!is_edp(intel_dp
));
444 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
445 * mapping needs to be retrieved from VBT, for now just hard-code to
446 * use instance #0 always.
448 if (!intel_dp
->pps_reset
)
451 intel_dp
->pps_reset
= false;
454 * Only the HW needs to be reprogrammed, the SW state is fixed and
455 * has been setup during connector init.
457 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
462 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
465 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
468 return I915_READ(PP_STATUS(pipe
)) & PP_ON
;
471 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
474 return I915_READ(PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
477 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
484 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
486 vlv_pipe_check pipe_check
)
490 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
491 u32 port_sel
= I915_READ(PP_ON_DELAYS(pipe
)) &
492 PANEL_PORT_SELECT_MASK
;
494 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
497 if (!pipe_check(dev_priv
, pipe
))
507 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
509 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
510 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
511 struct drm_i915_private
*dev_priv
= to_i915(dev
);
512 enum port port
= intel_dig_port
->port
;
514 lockdep_assert_held(&dev_priv
->pps_mutex
);
516 /* try to find a pipe with this port selected */
517 /* first pick one where the panel is on */
518 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
520 /* didn't find one? pick one where vdd is on */
521 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
522 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
523 vlv_pipe_has_vdd_on
);
524 /* didn't find one? pick one with just the correct port */
525 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
526 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
529 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
530 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
531 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
536 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
537 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
539 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
540 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
543 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
545 struct drm_device
*dev
= &dev_priv
->drm
;
546 struct intel_encoder
*encoder
;
548 if (WARN_ON(!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
553 * We can't grab pps_mutex here due to deadlock with power_domain
554 * mutex when power_domain functions are called while holding pps_mutex.
555 * That also means that in order to use pps_pipe the code needs to
556 * hold both a power domain reference and pps_mutex, and the power domain
557 * reference get/put must be done while _not_ holding pps_mutex.
558 * pps_{lock,unlock}() do these steps in the correct order, so one
559 * should use them always.
562 for_each_intel_encoder(dev
, encoder
) {
563 struct intel_dp
*intel_dp
;
565 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
568 intel_dp
= enc_to_intel_dp(&encoder
->base
);
570 intel_dp
->pps_reset
= true;
572 intel_dp
->pps_pipe
= INVALID_PIPE
;
576 struct pps_registers
{
584 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
585 struct intel_dp
*intel_dp
,
586 struct pps_registers
*regs
)
590 memset(regs
, 0, sizeof(*regs
));
592 if (IS_BROXTON(dev_priv
))
593 pps_idx
= bxt_power_sequencer_idx(intel_dp
);
594 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
595 pps_idx
= vlv_power_sequencer_pipe(intel_dp
);
597 regs
->pp_ctrl
= PP_CONTROL(pps_idx
);
598 regs
->pp_stat
= PP_STATUS(pps_idx
);
599 regs
->pp_on
= PP_ON_DELAYS(pps_idx
);
600 regs
->pp_off
= PP_OFF_DELAYS(pps_idx
);
601 if (!IS_BROXTON(dev_priv
))
602 regs
->pp_div
= PP_DIVISOR(pps_idx
);
606 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
608 struct pps_registers regs
;
610 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
617 _pp_stat_reg(struct intel_dp
*intel_dp
)
619 struct pps_registers regs
;
621 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
627 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
628 This function only applicable when panel PM state is not to be tracked */
629 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
632 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
634 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
635 struct drm_i915_private
*dev_priv
= to_i915(dev
);
637 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
642 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
643 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
644 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
647 pp_ctrl_reg
= PP_CONTROL(pipe
);
648 pp_div_reg
= PP_DIVISOR(pipe
);
649 pp_div
= I915_READ(pp_div_reg
);
650 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
652 /* 0x1F write to PP_DIV_REG sets max cycle delay */
653 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
654 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
655 msleep(intel_dp
->panel_power_cycle_delay
);
658 pps_unlock(intel_dp
);
663 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
665 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
666 struct drm_i915_private
*dev_priv
= to_i915(dev
);
668 lockdep_assert_held(&dev_priv
->pps_mutex
);
670 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
671 intel_dp
->pps_pipe
== INVALID_PIPE
)
674 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
677 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
679 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
680 struct drm_i915_private
*dev_priv
= to_i915(dev
);
682 lockdep_assert_held(&dev_priv
->pps_mutex
);
684 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
685 intel_dp
->pps_pipe
== INVALID_PIPE
)
688 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
692 intel_dp_check_edp(struct intel_dp
*intel_dp
)
694 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
695 struct drm_i915_private
*dev_priv
= to_i915(dev
);
697 if (!is_edp(intel_dp
))
700 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
701 WARN(1, "eDP powered off while attempting aux channel communication.\n");
702 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
703 I915_READ(_pp_stat_reg(intel_dp
)),
704 I915_READ(_pp_ctrl_reg(intel_dp
)));
709 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
711 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
712 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
713 struct drm_i915_private
*dev_priv
= to_i915(dev
);
714 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
718 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
720 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
721 msecs_to_jiffies_timeout(10));
723 done
= wait_for(C
, 10) == 0;
725 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
732 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
734 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
735 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
741 * The clock divider is based off the hrawclk, and would like to run at
742 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
744 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
747 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
749 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
750 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
756 * The clock divider is based off the cdclk or PCH rawclk, and would
757 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
758 * divide by 2000 and use that
760 if (intel_dig_port
->port
== PORT_A
)
761 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
763 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
766 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
768 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
769 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
771 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
772 /* Workaround for non-ULT HSW */
780 return ilk_get_aux_clock_divider(intel_dp
, index
);
783 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
786 * SKL doesn't need us to program the AUX clock divider (Hardware will
787 * derive the clock from CDCLK automatically). We still implement the
788 * get_aux_clock_divider vfunc to plug-in into the existing code.
790 return index
? 0 : 1;
793 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
796 uint32_t aux_clock_divider
)
798 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
799 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
800 uint32_t precharge
, timeout
;
807 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
808 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
810 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
812 return DP_AUX_CH_CTL_SEND_BUSY
|
814 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
815 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
817 DP_AUX_CH_CTL_RECEIVE_ERROR
|
818 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
819 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
820 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
823 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
828 return DP_AUX_CH_CTL_SEND_BUSY
|
830 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
831 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
832 DP_AUX_CH_CTL_TIME_OUT_1600us
|
833 DP_AUX_CH_CTL_RECEIVE_ERROR
|
834 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
835 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
836 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
840 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
841 const uint8_t *send
, int send_bytes
,
842 uint8_t *recv
, int recv_size
)
844 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
845 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
846 struct drm_i915_private
*dev_priv
= to_i915(dev
);
847 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
848 uint32_t aux_clock_divider
;
849 int i
, ret
, recv_bytes
;
852 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
858 * We will be called with VDD already enabled for dpcd/edid/oui reads.
859 * In such cases we want to leave VDD enabled and it's up to upper layers
860 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
863 vdd
= edp_panel_vdd_on(intel_dp
);
865 /* dp aux is extremely sensitive to irq latency, hence request the
866 * lowest possible wakeup latency and so prevent the cpu from going into
869 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
871 intel_dp_check_edp(intel_dp
);
873 /* Try to wait for any previous AUX channel activity */
874 for (try = 0; try < 3; try++) {
875 status
= I915_READ_NOTRACE(ch_ctl
);
876 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
882 static u32 last_status
= -1;
883 const u32 status
= I915_READ(ch_ctl
);
885 if (status
!= last_status
) {
886 WARN(1, "dp_aux_ch not started status 0x%08x\n",
888 last_status
= status
;
895 /* Only 5 data registers! */
896 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
901 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
902 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
907 /* Must try at least 3 times according to DP spec */
908 for (try = 0; try < 5; try++) {
909 /* Load the send data into the aux channel data registers */
910 for (i
= 0; i
< send_bytes
; i
+= 4)
911 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
912 intel_dp_pack_aux(send
+ i
,
915 /* Send the command and wait for it to complete */
916 I915_WRITE(ch_ctl
, send_ctl
);
918 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
920 /* Clear done status and any errors */
924 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
925 DP_AUX_CH_CTL_RECEIVE_ERROR
);
927 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
930 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
931 * 400us delay required for errors and timeouts
932 * Timeout errors from the HW already meet this
933 * requirement so skip to next iteration
935 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
936 usleep_range(400, 500);
939 if (status
& DP_AUX_CH_CTL_DONE
)
944 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
945 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
951 /* Check for timeout or receive error.
952 * Timeouts occur when the sink is not connected
954 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
955 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
960 /* Timeouts occur when the device isn't connected, so they're
961 * "normal" -- don't fill the kernel log with these */
962 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
963 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
968 /* Unload any bytes sent back from the other side */
969 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
970 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
973 * By BSpec: "Message sizes of 0 or >20 are not allowed."
974 * We have no idea of what happened so we return -EBUSY so
975 * drm layer takes care for the necessary retries.
977 if (recv_bytes
== 0 || recv_bytes
> 20) {
978 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
981 * FIXME: This patch was created on top of a series that
982 * organize the retries at drm level. There EBUSY should
983 * also take care for 1ms wait before retrying.
984 * That aux retries re-org is still needed and after that is
985 * merged we remove this sleep from here.
987 usleep_range(1000, 1500);
992 if (recv_bytes
> recv_size
)
993 recv_bytes
= recv_size
;
995 for (i
= 0; i
< recv_bytes
; i
+= 4)
996 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
997 recv
+ i
, recv_bytes
- i
);
1001 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1004 edp_panel_vdd_off(intel_dp
, false);
1006 pps_unlock(intel_dp
);
1011 #define BARE_ADDRESS_SIZE 3
1012 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1014 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1016 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1017 uint8_t txbuf
[20], rxbuf
[20];
1018 size_t txsize
, rxsize
;
1021 txbuf
[0] = (msg
->request
<< 4) |
1022 ((msg
->address
>> 16) & 0xf);
1023 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1024 txbuf
[2] = msg
->address
& 0xff;
1025 txbuf
[3] = msg
->size
- 1;
1027 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1028 case DP_AUX_NATIVE_WRITE
:
1029 case DP_AUX_I2C_WRITE
:
1030 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1031 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1032 rxsize
= 2; /* 0 or 1 data bytes */
1034 if (WARN_ON(txsize
> 20))
1037 WARN_ON(!msg
->buffer
!= !msg
->size
);
1040 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1042 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1044 msg
->reply
= rxbuf
[0] >> 4;
1047 /* Number of bytes written in a short write. */
1048 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1050 /* Return payload size. */
1056 case DP_AUX_NATIVE_READ
:
1057 case DP_AUX_I2C_READ
:
1058 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1059 rxsize
= msg
->size
+ 1;
1061 if (WARN_ON(rxsize
> 20))
1064 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1066 msg
->reply
= rxbuf
[0] >> 4;
1068 * Assume happy day, and copy the data. The caller is
1069 * expected to check msg->reply before touching it.
1071 * Return payload size.
1074 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1086 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1093 return DP_AUX_CH_CTL(port
);
1096 return DP_AUX_CH_CTL(PORT_B
);
1100 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1101 enum port port
, int index
)
1107 return DP_AUX_CH_DATA(port
, index
);
1110 return DP_AUX_CH_DATA(PORT_B
, index
);
1114 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1119 return DP_AUX_CH_CTL(port
);
1123 return PCH_DP_AUX_CH_CTL(port
);
1126 return DP_AUX_CH_CTL(PORT_A
);
1130 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1131 enum port port
, int index
)
1135 return DP_AUX_CH_DATA(port
, index
);
1139 return PCH_DP_AUX_CH_DATA(port
, index
);
1142 return DP_AUX_CH_DATA(PORT_A
, index
);
1147 * On SKL we don't have Aux for port E so we rely
1148 * on VBT to set a proper alternate aux channel.
1150 static enum port
skl_porte_aux_port(struct drm_i915_private
*dev_priv
)
1152 const struct ddi_vbt_port_info
*info
=
1153 &dev_priv
->vbt
.ddi_port_info
[PORT_E
];
1155 switch (info
->alternate_aux_channel
) {
1165 MISSING_CASE(info
->alternate_aux_channel
);
1170 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1174 port
= skl_porte_aux_port(dev_priv
);
1181 return DP_AUX_CH_CTL(port
);
1184 return DP_AUX_CH_CTL(PORT_A
);
1188 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1189 enum port port
, int index
)
1192 port
= skl_porte_aux_port(dev_priv
);
1199 return DP_AUX_CH_DATA(port
, index
);
1202 return DP_AUX_CH_DATA(PORT_A
, index
);
1206 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1209 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1210 return skl_aux_ctl_reg(dev_priv
, port
);
1211 else if (HAS_PCH_SPLIT(dev_priv
))
1212 return ilk_aux_ctl_reg(dev_priv
, port
);
1214 return g4x_aux_ctl_reg(dev_priv
, port
);
1217 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1218 enum port port
, int index
)
1220 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1221 return skl_aux_data_reg(dev_priv
, port
, index
);
1222 else if (HAS_PCH_SPLIT(dev_priv
))
1223 return ilk_aux_data_reg(dev_priv
, port
, index
);
1225 return g4x_aux_data_reg(dev_priv
, port
, index
);
1228 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1230 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1231 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1234 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1235 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1236 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1240 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1242 kfree(intel_dp
->aux
.name
);
1246 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1248 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1249 enum port port
= intel_dig_port
->port
;
1251 intel_aux_reg_init(intel_dp
);
1252 drm_dp_aux_init(&intel_dp
->aux
);
1254 /* Failure to allocate our preferred name is not critical */
1255 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1256 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1260 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1262 if (intel_dp
->num_sink_rates
) {
1263 *sink_rates
= intel_dp
->sink_rates
;
1264 return intel_dp
->num_sink_rates
;
1267 *sink_rates
= default_rates
;
1269 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1272 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1274 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1275 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1277 /* WaDisableHBR2:skl */
1278 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
))
1281 if ((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) || IS_BROADWELL(dev
) ||
1282 (INTEL_INFO(dev
)->gen
>= 9))
1289 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1291 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1292 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1295 if (IS_BROXTON(dev
)) {
1296 *source_rates
= bxt_rates
;
1297 size
= ARRAY_SIZE(bxt_rates
);
1298 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1299 *source_rates
= skl_rates
;
1300 size
= ARRAY_SIZE(skl_rates
);
1302 *source_rates
= default_rates
;
1303 size
= ARRAY_SIZE(default_rates
);
1306 /* This depends on the fact that 5.4 is last value in the array */
1307 if (!intel_dp_source_supports_hbr2(intel_dp
))
1314 intel_dp_set_clock(struct intel_encoder
*encoder
,
1315 struct intel_crtc_state
*pipe_config
)
1317 struct drm_device
*dev
= encoder
->base
.dev
;
1318 const struct dp_link_dpll
*divisor
= NULL
;
1322 divisor
= gen4_dpll
;
1323 count
= ARRAY_SIZE(gen4_dpll
);
1324 } else if (HAS_PCH_SPLIT(dev
)) {
1326 count
= ARRAY_SIZE(pch_dpll
);
1327 } else if (IS_CHERRYVIEW(dev
)) {
1329 count
= ARRAY_SIZE(chv_dpll
);
1330 } else if (IS_VALLEYVIEW(dev
)) {
1332 count
= ARRAY_SIZE(vlv_dpll
);
1335 if (divisor
&& count
) {
1336 for (i
= 0; i
< count
; i
++) {
1337 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1338 pipe_config
->dpll
= divisor
[i
].dpll
;
1339 pipe_config
->clock_set
= true;
1346 static int intersect_rates(const int *source_rates
, int source_len
,
1347 const int *sink_rates
, int sink_len
,
1350 int i
= 0, j
= 0, k
= 0;
1352 while (i
< source_len
&& j
< sink_len
) {
1353 if (source_rates
[i
] == sink_rates
[j
]) {
1354 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1356 common_rates
[k
] = source_rates
[i
];
1360 } else if (source_rates
[i
] < sink_rates
[j
]) {
1369 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1372 const int *source_rates
, *sink_rates
;
1373 int source_len
, sink_len
;
1375 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1376 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1378 return intersect_rates(source_rates
, source_len
,
1379 sink_rates
, sink_len
,
1383 static void snprintf_int_array(char *str
, size_t len
,
1384 const int *array
, int nelem
)
1390 for (i
= 0; i
< nelem
; i
++) {
1391 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1399 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1401 const int *source_rates
, *sink_rates
;
1402 int source_len
, sink_len
, common_len
;
1403 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1404 char str
[128]; /* FIXME: too big for stack? */
1406 if ((drm_debug
& DRM_UT_KMS
) == 0)
1409 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1410 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1411 DRM_DEBUG_KMS("source rates: %s\n", str
);
1413 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1414 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1415 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1417 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1418 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1419 DRM_DEBUG_KMS("common rates: %s\n", str
);
1422 static int rate_to_index(int find
, const int *rates
)
1426 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1427 if (find
== rates
[i
])
1434 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1436 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1439 len
= intel_dp_common_rates(intel_dp
, rates
);
1440 if (WARN_ON(len
<= 0))
1443 return rates
[len
- 1];
1446 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1448 return rate_to_index(rate
, intel_dp
->sink_rates
);
1451 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1452 uint8_t *link_bw
, uint8_t *rate_select
)
1454 if (intel_dp
->num_sink_rates
) {
1457 intel_dp_rate_select(intel_dp
, port_clock
);
1459 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1465 intel_dp_compute_config(struct intel_encoder
*encoder
,
1466 struct intel_crtc_state
*pipe_config
)
1468 struct drm_device
*dev
= encoder
->base
.dev
;
1469 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1470 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1471 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1472 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1473 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1474 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1475 int lane_count
, clock
;
1476 int min_lane_count
= 1;
1477 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1478 /* Conveniently, the link BW constants become indices with a shift...*/
1482 int link_avail
, link_clock
;
1483 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1485 uint8_t link_bw
, rate_select
;
1487 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1489 /* No common link rates between source and sink */
1490 WARN_ON(common_len
<= 0);
1492 max_clock
= common_len
- 1;
1494 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1495 pipe_config
->has_pch_encoder
= true;
1497 pipe_config
->has_drrs
= false;
1498 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1500 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1501 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1504 if (INTEL_INFO(dev
)->gen
>= 9) {
1506 ret
= skl_update_scaler_crtc(pipe_config
);
1511 if (HAS_GMCH_DISPLAY(dev
))
1512 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1513 intel_connector
->panel
.fitting_mode
);
1515 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1516 intel_connector
->panel
.fitting_mode
);
1519 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1522 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1523 "max bw %d pixel clock %iKHz\n",
1524 max_lane_count
, common_rates
[max_clock
],
1525 adjusted_mode
->crtc_clock
);
1527 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1528 * bpc in between. */
1529 bpp
= pipe_config
->pipe_bpp
;
1530 if (is_edp(intel_dp
)) {
1532 /* Get bpp from vbt only for panels that dont have bpp in edid */
1533 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1534 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1535 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1536 dev_priv
->vbt
.edp
.bpp
);
1537 bpp
= dev_priv
->vbt
.edp
.bpp
;
1541 * Use the maximum clock and number of lanes the eDP panel
1542 * advertizes being capable of. The panels are generally
1543 * designed to support only a single clock and lane
1544 * configuration, and typically these values correspond to the
1545 * native resolution of the panel.
1547 min_lane_count
= max_lane_count
;
1548 min_clock
= max_clock
;
1551 for (; bpp
>= 6*3; bpp
-= 2*3) {
1552 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1555 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1556 for (lane_count
= min_lane_count
;
1557 lane_count
<= max_lane_count
;
1560 link_clock
= common_rates
[clock
];
1561 link_avail
= intel_dp_max_data_rate(link_clock
,
1564 if (mode_rate
<= link_avail
) {
1574 if (intel_dp
->color_range_auto
) {
1577 * CEA-861-E - 5.1 Default Encoding Parameters
1578 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1580 pipe_config
->limited_color_range
=
1581 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1583 pipe_config
->limited_color_range
=
1584 intel_dp
->limited_color_range
;
1587 pipe_config
->lane_count
= lane_count
;
1589 pipe_config
->pipe_bpp
= bpp
;
1590 pipe_config
->port_clock
= common_rates
[clock
];
1592 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1593 &link_bw
, &rate_select
);
1595 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1596 link_bw
, rate_select
, pipe_config
->lane_count
,
1597 pipe_config
->port_clock
, bpp
);
1598 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1599 mode_rate
, link_avail
);
1601 intel_link_compute_m_n(bpp
, lane_count
,
1602 adjusted_mode
->crtc_clock
,
1603 pipe_config
->port_clock
,
1604 &pipe_config
->dp_m_n
);
1606 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1607 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1608 pipe_config
->has_drrs
= true;
1609 intel_link_compute_m_n(bpp
, lane_count
,
1610 intel_connector
->panel
.downclock_mode
->clock
,
1611 pipe_config
->port_clock
,
1612 &pipe_config
->dp_m2_n2
);
1616 * DPLL0 VCO may need to be adjusted to get the correct
1617 * clock for eDP. This will affect cdclk as well.
1619 if (is_edp(intel_dp
) &&
1620 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))) {
1623 switch (pipe_config
->port_clock
/ 2) {
1633 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk_pll_vco
= vco
;
1637 intel_dp_set_clock(encoder
, pipe_config
);
1642 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1643 const struct intel_crtc_state
*pipe_config
)
1645 intel_dp
->link_rate
= pipe_config
->port_clock
;
1646 intel_dp
->lane_count
= pipe_config
->lane_count
;
1647 intel_dp
->link_mst
= intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DP_MST
);
1650 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1652 struct drm_device
*dev
= encoder
->base
.dev
;
1653 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1654 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1655 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1656 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1657 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1659 intel_dp_set_link_params(intel_dp
, crtc
->config
);
1662 * There are four kinds of DP registers:
1669 * IBX PCH and CPU are the same for almost everything,
1670 * except that the CPU DP PLL is configured in this
1673 * CPT PCH is quite different, having many bits moved
1674 * to the TRANS_DP_CTL register instead. That
1675 * configuration happens (oddly) in ironlake_pch_enable
1678 /* Preserve the BIOS-computed detected bit. This is
1679 * supposed to be read-only.
1681 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1683 /* Handle DP bits in common between all three register formats */
1684 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1685 intel_dp
->DP
|= DP_PORT_WIDTH(crtc
->config
->lane_count
);
1687 /* Split out the IBX/CPU vs CPT settings */
1689 if (IS_GEN7(dev
) && port
== PORT_A
) {
1690 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1691 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1692 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1693 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1694 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1696 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1697 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1699 intel_dp
->DP
|= crtc
->pipe
<< 29;
1700 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1703 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1705 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1706 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1707 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1709 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1710 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1712 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1713 !IS_CHERRYVIEW(dev
) && crtc
->config
->limited_color_range
)
1714 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1716 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1717 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1718 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1719 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1720 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1722 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1723 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1725 if (IS_CHERRYVIEW(dev
))
1726 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1727 else if (crtc
->pipe
== PIPE_B
)
1728 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1732 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1733 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1735 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1736 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1738 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1739 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1741 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1742 struct intel_dp
*intel_dp
);
1744 static void wait_panel_status(struct intel_dp
*intel_dp
,
1748 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1749 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1750 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1752 lockdep_assert_held(&dev_priv
->pps_mutex
);
1754 intel_pps_verify_state(dev_priv
, intel_dp
);
1756 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1757 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1759 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1761 I915_READ(pp_stat_reg
),
1762 I915_READ(pp_ctrl_reg
));
1764 if (intel_wait_for_register(dev_priv
,
1765 pp_stat_reg
, mask
, value
,
1767 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1768 I915_READ(pp_stat_reg
),
1769 I915_READ(pp_ctrl_reg
));
1771 DRM_DEBUG_KMS("Wait complete\n");
1774 static void wait_panel_on(struct intel_dp
*intel_dp
)
1776 DRM_DEBUG_KMS("Wait for panel power on\n");
1777 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1780 static void wait_panel_off(struct intel_dp
*intel_dp
)
1782 DRM_DEBUG_KMS("Wait for panel power off time\n");
1783 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1786 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1788 ktime_t panel_power_on_time
;
1789 s64 panel_power_off_duration
;
1791 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1793 /* take the difference of currrent time and panel power off time
1794 * and then make panel wait for t11_t12 if needed. */
1795 panel_power_on_time
= ktime_get_boottime();
1796 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1798 /* When we disable the VDD override bit last we have to do the manual
1800 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1801 wait_remaining_ms_from_jiffies(jiffies
,
1802 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1804 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1807 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1809 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1810 intel_dp
->backlight_on_delay
);
1813 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1815 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1816 intel_dp
->backlight_off_delay
);
1819 /* Read the current pp_control value, unlocking the register if it
1823 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1825 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1826 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1829 lockdep_assert_held(&dev_priv
->pps_mutex
);
1831 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1832 if (WARN_ON(!HAS_DDI(dev_priv
) &&
1833 (control
& PANEL_UNLOCK_MASK
) != PANEL_UNLOCK_REGS
)) {
1834 control
&= ~PANEL_UNLOCK_MASK
;
1835 control
|= PANEL_UNLOCK_REGS
;
1841 * Must be paired with edp_panel_vdd_off().
1842 * Must hold pps_mutex around the whole on/off sequence.
1843 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1845 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1847 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1848 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1849 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1850 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1851 enum intel_display_power_domain power_domain
;
1853 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1854 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1856 lockdep_assert_held(&dev_priv
->pps_mutex
);
1858 if (!is_edp(intel_dp
))
1861 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1862 intel_dp
->want_panel_vdd
= true;
1864 if (edp_have_panel_vdd(intel_dp
))
1865 return need_to_disable
;
1867 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1868 intel_display_power_get(dev_priv
, power_domain
);
1870 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1871 port_name(intel_dig_port
->port
));
1873 if (!edp_have_panel_power(intel_dp
))
1874 wait_panel_power_cycle(intel_dp
);
1876 pp
= ironlake_get_pp_control(intel_dp
);
1877 pp
|= EDP_FORCE_VDD
;
1879 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1880 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1882 I915_WRITE(pp_ctrl_reg
, pp
);
1883 POSTING_READ(pp_ctrl_reg
);
1884 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1885 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1887 * If the panel wasn't on, delay before accessing aux channel
1889 if (!edp_have_panel_power(intel_dp
)) {
1890 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1891 port_name(intel_dig_port
->port
));
1892 msleep(intel_dp
->panel_power_up_delay
);
1895 return need_to_disable
;
1899 * Must be paired with intel_edp_panel_vdd_off() or
1900 * intel_edp_panel_off().
1901 * Nested calls to these functions are not allowed since
1902 * we drop the lock. Caller must use some higher level
1903 * locking to prevent nested calls from other threads.
1905 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1909 if (!is_edp(intel_dp
))
1913 vdd
= edp_panel_vdd_on(intel_dp
);
1914 pps_unlock(intel_dp
);
1916 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1917 port_name(dp_to_dig_port(intel_dp
)->port
));
1920 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1922 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1923 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1924 struct intel_digital_port
*intel_dig_port
=
1925 dp_to_dig_port(intel_dp
);
1926 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1927 enum intel_display_power_domain power_domain
;
1929 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1931 lockdep_assert_held(&dev_priv
->pps_mutex
);
1933 WARN_ON(intel_dp
->want_panel_vdd
);
1935 if (!edp_have_panel_vdd(intel_dp
))
1938 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1939 port_name(intel_dig_port
->port
));
1941 pp
= ironlake_get_pp_control(intel_dp
);
1942 pp
&= ~EDP_FORCE_VDD
;
1944 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1945 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1947 I915_WRITE(pp_ctrl_reg
, pp
);
1948 POSTING_READ(pp_ctrl_reg
);
1950 /* Make sure sequencer is idle before allowing subsequent activity */
1951 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1952 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1954 if ((pp
& PANEL_POWER_ON
) == 0)
1955 intel_dp
->panel_power_off_time
= ktime_get_boottime();
1957 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1958 intel_display_power_put(dev_priv
, power_domain
);
1961 static void edp_panel_vdd_work(struct work_struct
*__work
)
1963 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1964 struct intel_dp
, panel_vdd_work
);
1967 if (!intel_dp
->want_panel_vdd
)
1968 edp_panel_vdd_off_sync(intel_dp
);
1969 pps_unlock(intel_dp
);
1972 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1974 unsigned long delay
;
1977 * Queue the timer to fire a long time from now (relative to the power
1978 * down delay) to keep the panel power up across a sequence of
1981 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1982 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1986 * Must be paired with edp_panel_vdd_on().
1987 * Must hold pps_mutex around the whole on/off sequence.
1988 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1990 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1992 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1994 lockdep_assert_held(&dev_priv
->pps_mutex
);
1996 if (!is_edp(intel_dp
))
1999 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2000 port_name(dp_to_dig_port(intel_dp
)->port
));
2002 intel_dp
->want_panel_vdd
= false;
2005 edp_panel_vdd_off_sync(intel_dp
);
2007 edp_panel_vdd_schedule_off(intel_dp
);
2010 static void edp_panel_on(struct intel_dp
*intel_dp
)
2012 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2013 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2015 i915_reg_t pp_ctrl_reg
;
2017 lockdep_assert_held(&dev_priv
->pps_mutex
);
2019 if (!is_edp(intel_dp
))
2022 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2023 port_name(dp_to_dig_port(intel_dp
)->port
));
2025 if (WARN(edp_have_panel_power(intel_dp
),
2026 "eDP port %c panel power already on\n",
2027 port_name(dp_to_dig_port(intel_dp
)->port
)))
2030 wait_panel_power_cycle(intel_dp
);
2032 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2033 pp
= ironlake_get_pp_control(intel_dp
);
2035 /* ILK workaround: disable reset around power sequence */
2036 pp
&= ~PANEL_POWER_RESET
;
2037 I915_WRITE(pp_ctrl_reg
, pp
);
2038 POSTING_READ(pp_ctrl_reg
);
2041 pp
|= PANEL_POWER_ON
;
2043 pp
|= PANEL_POWER_RESET
;
2045 I915_WRITE(pp_ctrl_reg
, pp
);
2046 POSTING_READ(pp_ctrl_reg
);
2048 wait_panel_on(intel_dp
);
2049 intel_dp
->last_power_on
= jiffies
;
2052 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2053 I915_WRITE(pp_ctrl_reg
, pp
);
2054 POSTING_READ(pp_ctrl_reg
);
2058 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2060 if (!is_edp(intel_dp
))
2064 edp_panel_on(intel_dp
);
2065 pps_unlock(intel_dp
);
2069 static void edp_panel_off(struct intel_dp
*intel_dp
)
2071 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2072 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2073 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2074 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2075 enum intel_display_power_domain power_domain
;
2077 i915_reg_t pp_ctrl_reg
;
2079 lockdep_assert_held(&dev_priv
->pps_mutex
);
2081 if (!is_edp(intel_dp
))
2084 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2085 port_name(dp_to_dig_port(intel_dp
)->port
));
2087 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2088 port_name(dp_to_dig_port(intel_dp
)->port
));
2090 pp
= ironlake_get_pp_control(intel_dp
);
2091 /* We need to switch off panel power _and_ force vdd, for otherwise some
2092 * panels get very unhappy and cease to work. */
2093 pp
&= ~(PANEL_POWER_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2096 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2098 intel_dp
->want_panel_vdd
= false;
2100 I915_WRITE(pp_ctrl_reg
, pp
);
2101 POSTING_READ(pp_ctrl_reg
);
2103 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2104 wait_panel_off(intel_dp
);
2106 /* We got a reference when we enabled the VDD. */
2107 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2108 intel_display_power_put(dev_priv
, power_domain
);
2111 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2113 if (!is_edp(intel_dp
))
2117 edp_panel_off(intel_dp
);
2118 pps_unlock(intel_dp
);
2121 /* Enable backlight in the panel power control. */
2122 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2124 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2125 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2126 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2128 i915_reg_t pp_ctrl_reg
;
2131 * If we enable the backlight right away following a panel power
2132 * on, we may see slight flicker as the panel syncs with the eDP
2133 * link. So delay a bit to make sure the image is solid before
2134 * allowing it to appear.
2136 wait_backlight_on(intel_dp
);
2140 pp
= ironlake_get_pp_control(intel_dp
);
2141 pp
|= EDP_BLC_ENABLE
;
2143 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2145 I915_WRITE(pp_ctrl_reg
, pp
);
2146 POSTING_READ(pp_ctrl_reg
);
2148 pps_unlock(intel_dp
);
2151 /* Enable backlight PWM and backlight PP control. */
2152 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2154 if (!is_edp(intel_dp
))
2157 DRM_DEBUG_KMS("\n");
2159 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2160 _intel_edp_backlight_on(intel_dp
);
2163 /* Disable backlight in the panel power control. */
2164 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2166 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2167 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2169 i915_reg_t pp_ctrl_reg
;
2171 if (!is_edp(intel_dp
))
2176 pp
= ironlake_get_pp_control(intel_dp
);
2177 pp
&= ~EDP_BLC_ENABLE
;
2179 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2181 I915_WRITE(pp_ctrl_reg
, pp
);
2182 POSTING_READ(pp_ctrl_reg
);
2184 pps_unlock(intel_dp
);
2186 intel_dp
->last_backlight_off
= jiffies
;
2187 edp_wait_backlight_off(intel_dp
);
2190 /* Disable backlight PP control and backlight PWM. */
2191 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2193 if (!is_edp(intel_dp
))
2196 DRM_DEBUG_KMS("\n");
2198 _intel_edp_backlight_off(intel_dp
);
2199 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2203 * Hook for controlling the panel power control backlight through the bl_power
2204 * sysfs attribute. Take care to handle multiple calls.
2206 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2209 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2213 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2214 pps_unlock(intel_dp
);
2216 if (is_enabled
== enable
)
2219 DRM_DEBUG_KMS("panel power control backlight %s\n",
2220 enable
? "enable" : "disable");
2223 _intel_edp_backlight_on(intel_dp
);
2225 _intel_edp_backlight_off(intel_dp
);
2228 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2230 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2231 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2232 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2234 I915_STATE_WARN(cur_state
!= state
,
2235 "DP port %c state assertion failure (expected %s, current %s)\n",
2236 port_name(dig_port
->port
),
2237 onoff(state
), onoff(cur_state
));
2239 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2241 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2243 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2245 I915_STATE_WARN(cur_state
!= state
,
2246 "eDP PLL state assertion failure (expected %s, current %s)\n",
2247 onoff(state
), onoff(cur_state
));
2249 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2250 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2252 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2254 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2255 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2256 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2258 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2259 assert_dp_port_disabled(intel_dp
);
2260 assert_edp_pll_disabled(dev_priv
);
2262 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2263 crtc
->config
->port_clock
);
2265 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2267 if (crtc
->config
->port_clock
== 162000)
2268 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2270 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2272 I915_WRITE(DP_A
, intel_dp
->DP
);
2277 * [DevILK] Work around required when enabling DP PLL
2278 * while a pipe is enabled going to FDI:
2279 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2280 * 2. Program DP PLL enable
2282 if (IS_GEN5(dev_priv
))
2283 intel_wait_for_vblank_if_active(&dev_priv
->drm
, !crtc
->pipe
);
2285 intel_dp
->DP
|= DP_PLL_ENABLE
;
2287 I915_WRITE(DP_A
, intel_dp
->DP
);
2292 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2294 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2295 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2296 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2298 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2299 assert_dp_port_disabled(intel_dp
);
2300 assert_edp_pll_enabled(dev_priv
);
2302 DRM_DEBUG_KMS("disabling eDP PLL\n");
2304 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2306 I915_WRITE(DP_A
, intel_dp
->DP
);
2311 /* If the sink supports it, try to set the power state appropriately */
2312 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2316 /* Should have a valid DPCD by this point */
2317 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2320 if (mode
!= DRM_MODE_DPMS_ON
) {
2321 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2325 * When turning on, we need to retry for 1ms to give the sink
2328 for (i
= 0; i
< 3; i
++) {
2329 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2338 DRM_DEBUG_KMS("failed to %s sink power state\n",
2339 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2342 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2345 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2346 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2347 struct drm_device
*dev
= encoder
->base
.dev
;
2348 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2349 enum intel_display_power_domain power_domain
;
2353 power_domain
= intel_display_port_power_domain(encoder
);
2354 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2359 tmp
= I915_READ(intel_dp
->output_reg
);
2361 if (!(tmp
& DP_PORT_EN
))
2364 if (IS_GEN7(dev
) && port
== PORT_A
) {
2365 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2366 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2369 for_each_pipe(dev_priv
, p
) {
2370 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2371 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2379 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2380 i915_mmio_reg_offset(intel_dp
->output_reg
));
2381 } else if (IS_CHERRYVIEW(dev
)) {
2382 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2384 *pipe
= PORT_TO_PIPE(tmp
);
2390 intel_display_power_put(dev_priv
, power_domain
);
2395 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2396 struct intel_crtc_state
*pipe_config
)
2398 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2400 struct drm_device
*dev
= encoder
->base
.dev
;
2401 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2402 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2403 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2405 tmp
= I915_READ(intel_dp
->output_reg
);
2407 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2409 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2410 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2412 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2413 flags
|= DRM_MODE_FLAG_PHSYNC
;
2415 flags
|= DRM_MODE_FLAG_NHSYNC
;
2417 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2418 flags
|= DRM_MODE_FLAG_PVSYNC
;
2420 flags
|= DRM_MODE_FLAG_NVSYNC
;
2422 if (tmp
& DP_SYNC_HS_HIGH
)
2423 flags
|= DRM_MODE_FLAG_PHSYNC
;
2425 flags
|= DRM_MODE_FLAG_NHSYNC
;
2427 if (tmp
& DP_SYNC_VS_HIGH
)
2428 flags
|= DRM_MODE_FLAG_PVSYNC
;
2430 flags
|= DRM_MODE_FLAG_NVSYNC
;
2433 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2435 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2436 !IS_CHERRYVIEW(dev
) && tmp
& DP_COLOR_RANGE_16_235
)
2437 pipe_config
->limited_color_range
= true;
2439 pipe_config
->lane_count
=
2440 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2442 intel_dp_get_m_n(crtc
, pipe_config
);
2444 if (port
== PORT_A
) {
2445 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2446 pipe_config
->port_clock
= 162000;
2448 pipe_config
->port_clock
= 270000;
2451 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2452 intel_dotclock_calculate(pipe_config
->port_clock
,
2453 &pipe_config
->dp_m_n
);
2455 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2456 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2458 * This is a big fat ugly hack.
2460 * Some machines in UEFI boot mode provide us a VBT that has 18
2461 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2462 * unknown we fail to light up. Yet the same BIOS boots up with
2463 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2464 * max, not what it tells us to use.
2466 * Note: This will still be broken if the eDP panel is not lit
2467 * up by the BIOS, and thus we can't get the mode at module
2470 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2471 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2472 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2476 static void intel_disable_dp(struct intel_encoder
*encoder
)
2478 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2479 struct drm_device
*dev
= encoder
->base
.dev
;
2480 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2482 if (crtc
->config
->has_audio
)
2483 intel_audio_codec_disable(encoder
);
2485 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2486 intel_psr_disable(intel_dp
);
2488 /* Make sure the panel is off before trying to change the mode. But also
2489 * ensure that we have vdd while we switch off the panel. */
2490 intel_edp_panel_vdd_on(intel_dp
);
2491 intel_edp_backlight_off(intel_dp
);
2492 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2493 intel_edp_panel_off(intel_dp
);
2495 /* disable the port before the pipe on g4x */
2496 if (INTEL_INFO(dev
)->gen
< 5)
2497 intel_dp_link_down(intel_dp
);
2500 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2502 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2503 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2505 intel_dp_link_down(intel_dp
);
2507 /* Only ilk+ has port A */
2509 ironlake_edp_pll_off(intel_dp
);
2512 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2514 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2516 intel_dp_link_down(intel_dp
);
2519 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2521 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2522 struct drm_device
*dev
= encoder
->base
.dev
;
2523 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2525 intel_dp_link_down(intel_dp
);
2527 mutex_lock(&dev_priv
->sb_lock
);
2529 /* Assert data lane reset */
2530 chv_data_lane_soft_reset(encoder
, true);
2532 mutex_unlock(&dev_priv
->sb_lock
);
2536 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2538 uint8_t dp_train_pat
)
2540 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2541 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2542 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2543 enum port port
= intel_dig_port
->port
;
2546 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2548 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2549 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2551 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2553 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2554 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2555 case DP_TRAINING_PATTERN_DISABLE
:
2556 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2559 case DP_TRAINING_PATTERN_1
:
2560 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2562 case DP_TRAINING_PATTERN_2
:
2563 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2565 case DP_TRAINING_PATTERN_3
:
2566 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2569 I915_WRITE(DP_TP_CTL(port
), temp
);
2571 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2572 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2573 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2575 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2576 case DP_TRAINING_PATTERN_DISABLE
:
2577 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2579 case DP_TRAINING_PATTERN_1
:
2580 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2582 case DP_TRAINING_PATTERN_2
:
2583 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2585 case DP_TRAINING_PATTERN_3
:
2586 DRM_ERROR("DP training pattern 3 not supported\n");
2587 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2592 if (IS_CHERRYVIEW(dev
))
2593 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2595 *DP
&= ~DP_LINK_TRAIN_MASK
;
2597 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2598 case DP_TRAINING_PATTERN_DISABLE
:
2599 *DP
|= DP_LINK_TRAIN_OFF
;
2601 case DP_TRAINING_PATTERN_1
:
2602 *DP
|= DP_LINK_TRAIN_PAT_1
;
2604 case DP_TRAINING_PATTERN_2
:
2605 *DP
|= DP_LINK_TRAIN_PAT_2
;
2607 case DP_TRAINING_PATTERN_3
:
2608 if (IS_CHERRYVIEW(dev
)) {
2609 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2611 DRM_ERROR("DP training pattern 3 not supported\n");
2612 *DP
|= DP_LINK_TRAIN_PAT_2
;
2619 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2621 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2622 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2623 struct intel_crtc
*crtc
=
2624 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
2626 /* enable with pattern 1 (as per spec) */
2627 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2628 DP_TRAINING_PATTERN_1
);
2630 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2631 POSTING_READ(intel_dp
->output_reg
);
2634 * Magic for VLV/CHV. We _must_ first set up the register
2635 * without actually enabling the port, and then do another
2636 * write to enable the port. Otherwise link training will
2637 * fail when the power sequencer is freshly used for this port.
2639 intel_dp
->DP
|= DP_PORT_EN
;
2640 if (crtc
->config
->has_audio
)
2641 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2643 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2644 POSTING_READ(intel_dp
->output_reg
);
2647 static void intel_enable_dp(struct intel_encoder
*encoder
)
2649 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2650 struct drm_device
*dev
= encoder
->base
.dev
;
2651 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2652 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2653 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2654 enum pipe pipe
= crtc
->pipe
;
2656 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2661 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2662 vlv_init_panel_power_sequencer(intel_dp
);
2664 intel_dp_enable_port(intel_dp
);
2666 edp_panel_vdd_on(intel_dp
);
2667 edp_panel_on(intel_dp
);
2668 edp_panel_vdd_off(intel_dp
, true);
2670 pps_unlock(intel_dp
);
2672 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2673 unsigned int lane_mask
= 0x0;
2675 if (IS_CHERRYVIEW(dev
))
2676 lane_mask
= intel_dp_unused_lane_mask(crtc
->config
->lane_count
);
2678 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2682 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2683 intel_dp_start_link_train(intel_dp
);
2684 intel_dp_stop_link_train(intel_dp
);
2686 if (crtc
->config
->has_audio
) {
2687 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2689 intel_audio_codec_enable(encoder
);
2693 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2695 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2697 intel_enable_dp(encoder
);
2698 intel_edp_backlight_on(intel_dp
);
2701 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2703 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2705 intel_edp_backlight_on(intel_dp
);
2706 intel_psr_enable(intel_dp
);
2709 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2711 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2712 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2714 intel_dp_prepare(encoder
);
2716 /* Only ilk+ has port A */
2718 ironlake_edp_pll_on(intel_dp
);
2721 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2723 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2724 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
2725 enum pipe pipe
= intel_dp
->pps_pipe
;
2726 i915_reg_t pp_on_reg
= PP_ON_DELAYS(pipe
);
2728 edp_panel_vdd_off_sync(intel_dp
);
2731 * VLV seems to get confused when multiple power seqeuencers
2732 * have the same port selected (even if only one has power/vdd
2733 * enabled). The failure manifests as vlv_wait_port_ready() failing
2734 * CHV on the other hand doesn't seem to mind having the same port
2735 * selected in multiple power seqeuencers, but let's clear the
2736 * port select always when logically disconnecting a power sequencer
2739 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2740 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2741 I915_WRITE(pp_on_reg
, 0);
2742 POSTING_READ(pp_on_reg
);
2744 intel_dp
->pps_pipe
= INVALID_PIPE
;
2747 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2750 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2751 struct intel_encoder
*encoder
;
2753 lockdep_assert_held(&dev_priv
->pps_mutex
);
2755 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2758 for_each_intel_encoder(dev
, encoder
) {
2759 struct intel_dp
*intel_dp
;
2762 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2765 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2766 port
= dp_to_dig_port(intel_dp
)->port
;
2768 if (intel_dp
->pps_pipe
!= pipe
)
2771 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2772 pipe_name(pipe
), port_name(port
));
2774 WARN(encoder
->base
.crtc
,
2775 "stealing pipe %c power sequencer from active eDP port %c\n",
2776 pipe_name(pipe
), port_name(port
));
2778 /* make sure vdd is off before we steal it */
2779 vlv_detach_power_sequencer(intel_dp
);
2783 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2785 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2786 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2787 struct drm_device
*dev
= encoder
->base
.dev
;
2788 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2789 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2791 lockdep_assert_held(&dev_priv
->pps_mutex
);
2793 if (!is_edp(intel_dp
))
2796 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2800 * If another power sequencer was being used on this
2801 * port previously make sure to turn off vdd there while
2802 * we still have control of it.
2804 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2805 vlv_detach_power_sequencer(intel_dp
);
2808 * We may be stealing the power
2809 * sequencer from another port.
2811 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2813 /* now it's all ours */
2814 intel_dp
->pps_pipe
= crtc
->pipe
;
2816 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2817 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2819 /* init power sequencer on this pipe and port */
2820 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2821 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2824 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2826 vlv_phy_pre_encoder_enable(encoder
);
2828 intel_enable_dp(encoder
);
2831 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2833 intel_dp_prepare(encoder
);
2835 vlv_phy_pre_pll_enable(encoder
);
2838 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2840 chv_phy_pre_encoder_enable(encoder
);
2842 intel_enable_dp(encoder
);
2844 /* Second common lane will stay alive on its own now */
2845 chv_phy_release_cl2_override(encoder
);
2848 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2850 intel_dp_prepare(encoder
);
2852 chv_phy_pre_pll_enable(encoder
);
2855 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
)
2857 chv_phy_post_pll_disable(encoder
);
2861 * Fetch AUX CH registers 0x202 - 0x207 which contain
2862 * link status information
2865 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2867 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
2868 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2871 /* These are source-specific values. */
2873 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2875 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2876 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2877 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2879 if (IS_BROXTON(dev
))
2880 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2881 else if (INTEL_INFO(dev
)->gen
>= 9) {
2882 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2883 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2884 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2885 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2886 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2887 else if (IS_GEN7(dev
) && port
== PORT_A
)
2888 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2889 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2890 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2892 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2896 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2898 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2899 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2901 if (INTEL_INFO(dev
)->gen
>= 9) {
2902 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2903 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2904 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2905 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2906 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2908 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2909 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2910 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2912 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2914 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2915 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2917 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2919 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2921 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2924 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2926 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2927 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2929 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2931 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2933 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2938 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2939 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2941 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2944 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2946 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2949 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2953 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2954 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2955 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2956 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2958 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2963 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
2965 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
2966 unsigned long demph_reg_value
, preemph_reg_value
,
2967 uniqtranscale_reg_value
;
2968 uint8_t train_set
= intel_dp
->train_set
[0];
2970 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2971 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2972 preemph_reg_value
= 0x0004000;
2973 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2975 demph_reg_value
= 0x2B405555;
2976 uniqtranscale_reg_value
= 0x552AB83A;
2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2979 demph_reg_value
= 0x2B404040;
2980 uniqtranscale_reg_value
= 0x5548B83A;
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2983 demph_reg_value
= 0x2B245555;
2984 uniqtranscale_reg_value
= 0x5560B83A;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2987 demph_reg_value
= 0x2B405555;
2988 uniqtranscale_reg_value
= 0x5598DA3A;
2994 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2995 preemph_reg_value
= 0x0002000;
2996 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2998 demph_reg_value
= 0x2B404040;
2999 uniqtranscale_reg_value
= 0x5552B83A;
3001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3002 demph_reg_value
= 0x2B404848;
3003 uniqtranscale_reg_value
= 0x5580B83A;
3005 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3006 demph_reg_value
= 0x2B404040;
3007 uniqtranscale_reg_value
= 0x55ADDA3A;
3013 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3014 preemph_reg_value
= 0x0000000;
3015 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3017 demph_reg_value
= 0x2B305555;
3018 uniqtranscale_reg_value
= 0x5570B83A;
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3021 demph_reg_value
= 0x2B2B4040;
3022 uniqtranscale_reg_value
= 0x55ADDA3A;
3028 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3029 preemph_reg_value
= 0x0006000;
3030 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3032 demph_reg_value
= 0x1B405555;
3033 uniqtranscale_reg_value
= 0x55ADDA3A;
3043 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3044 uniqtranscale_reg_value
, 0);
3049 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3051 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3052 u32 deemph_reg_value
, margin_reg_value
;
3053 bool uniq_trans_scale
= false;
3054 uint8_t train_set
= intel_dp
->train_set
[0];
3056 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3057 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3058 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3060 deemph_reg_value
= 128;
3061 margin_reg_value
= 52;
3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3064 deemph_reg_value
= 128;
3065 margin_reg_value
= 77;
3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3068 deemph_reg_value
= 128;
3069 margin_reg_value
= 102;
3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3072 deemph_reg_value
= 128;
3073 margin_reg_value
= 154;
3074 uniq_trans_scale
= true;
3080 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3081 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3083 deemph_reg_value
= 85;
3084 margin_reg_value
= 78;
3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3087 deemph_reg_value
= 85;
3088 margin_reg_value
= 116;
3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3091 deemph_reg_value
= 85;
3092 margin_reg_value
= 154;
3098 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3099 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3101 deemph_reg_value
= 64;
3102 margin_reg_value
= 104;
3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3105 deemph_reg_value
= 64;
3106 margin_reg_value
= 154;
3112 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3113 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3115 deemph_reg_value
= 43;
3116 margin_reg_value
= 154;
3126 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3127 margin_reg_value
, uniq_trans_scale
);
3133 gen4_signal_levels(uint8_t train_set
)
3135 uint32_t signal_levels
= 0;
3137 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3140 signal_levels
|= DP_VOLTAGE_0_4
;
3142 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3143 signal_levels
|= DP_VOLTAGE_0_6
;
3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3146 signal_levels
|= DP_VOLTAGE_0_8
;
3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3149 signal_levels
|= DP_VOLTAGE_1_2
;
3152 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3153 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3155 signal_levels
|= DP_PRE_EMPHASIS_0
;
3157 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3158 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3160 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3161 signal_levels
|= DP_PRE_EMPHASIS_6
;
3163 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3164 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3167 return signal_levels
;
3170 /* Gen6's DP voltage swing and pre-emphasis control */
3172 gen6_edp_signal_levels(uint8_t train_set
)
3174 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3175 DP_TRAIN_PRE_EMPHASIS_MASK
);
3176 switch (signal_levels
) {
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3179 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3181 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3184 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3187 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3190 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3192 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3193 "0x%x\n", signal_levels
);
3194 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3198 /* Gen7's DP voltage swing and pre-emphasis control */
3200 gen7_edp_signal_levels(uint8_t train_set
)
3202 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3203 DP_TRAIN_PRE_EMPHASIS_MASK
);
3204 switch (signal_levels
) {
3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3206 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3208 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3210 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3213 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3215 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3218 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3220 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3223 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3224 "0x%x\n", signal_levels
);
3225 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3230 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3232 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3233 enum port port
= intel_dig_port
->port
;
3234 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3235 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3236 uint32_t signal_levels
, mask
= 0;
3237 uint8_t train_set
= intel_dp
->train_set
[0];
3240 signal_levels
= ddi_signal_levels(intel_dp
);
3242 if (IS_BROXTON(dev
))
3245 mask
= DDI_BUF_EMP_MASK
;
3246 } else if (IS_CHERRYVIEW(dev
)) {
3247 signal_levels
= chv_signal_levels(intel_dp
);
3248 } else if (IS_VALLEYVIEW(dev
)) {
3249 signal_levels
= vlv_signal_levels(intel_dp
);
3250 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3251 signal_levels
= gen7_edp_signal_levels(train_set
);
3252 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3253 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3254 signal_levels
= gen6_edp_signal_levels(train_set
);
3255 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3257 signal_levels
= gen4_signal_levels(train_set
);
3258 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3262 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3264 DRM_DEBUG_KMS("Using vswing level %d\n",
3265 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3266 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3267 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3268 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3270 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3272 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3273 POSTING_READ(intel_dp
->output_reg
);
3277 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3278 uint8_t dp_train_pat
)
3280 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3281 struct drm_i915_private
*dev_priv
=
3282 to_i915(intel_dig_port
->base
.base
.dev
);
3284 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3286 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3287 POSTING_READ(intel_dp
->output_reg
);
3290 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3292 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3293 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3294 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3295 enum port port
= intel_dig_port
->port
;
3301 val
= I915_READ(DP_TP_CTL(port
));
3302 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3303 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3304 I915_WRITE(DP_TP_CTL(port
), val
);
3307 * On PORT_A we can have only eDP in SST mode. There the only reason
3308 * we need to set idle transmission mode is to work around a HW issue
3309 * where we enable the pipe while not in idle link-training mode.
3310 * In this case there is requirement to wait for a minimum number of
3311 * idle patterns to be sent.
3316 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3317 DP_TP_STATUS_IDLE_DONE
,
3318 DP_TP_STATUS_IDLE_DONE
,
3320 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3324 intel_dp_link_down(struct intel_dp
*intel_dp
)
3326 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3327 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3328 enum port port
= intel_dig_port
->port
;
3329 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3330 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3331 uint32_t DP
= intel_dp
->DP
;
3333 if (WARN_ON(HAS_DDI(dev
)))
3336 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3339 DRM_DEBUG_KMS("\n");
3341 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3342 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3343 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3344 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3346 if (IS_CHERRYVIEW(dev
))
3347 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3349 DP
&= ~DP_LINK_TRAIN_MASK
;
3350 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3352 I915_WRITE(intel_dp
->output_reg
, DP
);
3353 POSTING_READ(intel_dp
->output_reg
);
3355 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3356 I915_WRITE(intel_dp
->output_reg
, DP
);
3357 POSTING_READ(intel_dp
->output_reg
);
3360 * HW workaround for IBX, we need to move the port
3361 * to transcoder A after disabling it to allow the
3362 * matching HDMI port to be enabled on transcoder A.
3364 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3366 * We get CPU/PCH FIFO underruns on the other pipe when
3367 * doing the workaround. Sweep them under the rug.
3369 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3370 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3372 /* always enable with pattern 1 (as per spec) */
3373 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3374 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3375 I915_WRITE(intel_dp
->output_reg
, DP
);
3376 POSTING_READ(intel_dp
->output_reg
);
3379 I915_WRITE(intel_dp
->output_reg
, DP
);
3380 POSTING_READ(intel_dp
->output_reg
);
3382 intel_wait_for_vblank_if_active(&dev_priv
->drm
, PIPE_A
);
3383 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3384 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3387 msleep(intel_dp
->panel_power_down_delay
);
3393 intel_dp_read_dpcd(struct intel_dp
*intel_dp
)
3395 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3396 sizeof(intel_dp
->dpcd
)) < 0)
3397 return false; /* aux transfer failed */
3399 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3401 return intel_dp
->dpcd
[DP_DPCD_REV
] != 0;
3405 intel_edp_init_dpcd(struct intel_dp
*intel_dp
)
3407 struct drm_i915_private
*dev_priv
=
3408 to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
3410 /* this function is meant to be called only once */
3411 WARN_ON(intel_dp
->dpcd
[DP_DPCD_REV
] != 0);
3413 if (!intel_dp_read_dpcd(intel_dp
))
3416 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3417 dev_priv
->no_aux_handshake
= intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3418 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3420 /* Check if the panel supports PSR */
3421 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3423 sizeof(intel_dp
->psr_dpcd
));
3424 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3425 dev_priv
->psr
.sink_support
= true;
3426 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3429 if (INTEL_GEN(dev_priv
) >= 9 &&
3430 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3431 uint8_t frame_sync_cap
;
3433 dev_priv
->psr
.sink_support
= true;
3434 drm_dp_dpcd_read(&intel_dp
->aux
,
3435 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3436 &frame_sync_cap
, 1);
3437 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3438 /* PSR2 needs frame sync as well */
3439 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3440 DRM_DEBUG_KMS("PSR2 %s on sink",
3441 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3444 /* Read the eDP Display control capabilities registers */
3445 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3446 drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3447 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
) ==
3448 sizeof(intel_dp
->edp_dpcd
)))
3449 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3450 intel_dp
->edp_dpcd
);
3452 /* Intermediate frequency support */
3453 if (intel_dp
->edp_dpcd
[0] >= 0x03) { /* eDp v1.4 or higher */
3454 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3457 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3458 sink_rates
, sizeof(sink_rates
));
3460 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3461 int val
= le16_to_cpu(sink_rates
[i
]);
3466 /* Value read is in kHz while drm clock is saved in deca-kHz */
3467 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3469 intel_dp
->num_sink_rates
= i
;
3477 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3479 if (!intel_dp_read_dpcd(intel_dp
))
3482 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3483 &intel_dp
->sink_count
, 1) < 0)
3487 * Sink count can change between short pulse hpd hence
3488 * a member variable in intel_dp will track any changes
3489 * between short pulse interrupts.
3491 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3494 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3495 * a dongle is present but no display. Unless we require to know
3496 * if a dongle is present or not, we don't need to update
3497 * downstream port information. So, an early return here saves
3498 * time from performing other operations which are not required.
3500 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3503 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3504 DP_DWN_STRM_PORT_PRESENT
))
3505 return true; /* native DP sink */
3507 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3508 return true; /* no per-port downstream info */
3510 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3511 intel_dp
->downstream_ports
,
3512 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3513 return false; /* downstream port status fetch failed */
3519 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3523 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3526 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3527 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3528 buf
[0], buf
[1], buf
[2]);
3530 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3531 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3532 buf
[0], buf
[1], buf
[2]);
3536 intel_dp_can_mst(struct intel_dp
*intel_dp
)
3540 if (!i915
.enable_dp_mst
)
3543 if (!intel_dp
->can_mst
)
3546 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3549 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1) != 1)
3552 return buf
[0] & DP_MST_CAP
;
3556 intel_dp_configure_mst(struct intel_dp
*intel_dp
)
3558 if (!i915
.enable_dp_mst
)
3561 if (!intel_dp
->can_mst
)
3564 intel_dp
->is_mst
= intel_dp_can_mst(intel_dp
);
3566 if (intel_dp
->is_mst
)
3567 DRM_DEBUG_KMS("Sink is MST capable\n");
3569 DRM_DEBUG_KMS("Sink is not MST capable\n");
3571 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
3575 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3577 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3578 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3579 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3585 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3586 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3591 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3592 buf
& ~DP_TEST_SINK_START
) < 0) {
3593 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3599 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3601 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3602 DP_TEST_SINK_MISC
, &buf
) < 0) {
3606 count
= buf
& DP_TEST_COUNT_MASK
;
3607 } while (--attempts
&& count
);
3609 if (attempts
== 0) {
3610 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3615 hsw_enable_ips(intel_crtc
);
3619 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3621 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3622 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3623 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3627 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3630 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3633 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3636 if (buf
& DP_TEST_SINK_START
) {
3637 ret
= intel_dp_sink_crc_stop(intel_dp
);
3642 hsw_disable_ips(intel_crtc
);
3644 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3645 buf
| DP_TEST_SINK_START
) < 0) {
3646 hsw_enable_ips(intel_crtc
);
3650 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3654 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3656 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3657 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3658 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3663 ret
= intel_dp_sink_crc_start(intel_dp
);
3668 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3670 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3671 DP_TEST_SINK_MISC
, &buf
) < 0) {
3675 count
= buf
& DP_TEST_COUNT_MASK
;
3677 } while (--attempts
&& count
== 0);
3679 if (attempts
== 0) {
3680 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3685 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3691 intel_dp_sink_crc_stop(intel_dp
);
3696 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3698 return drm_dp_dpcd_read(&intel_dp
->aux
,
3699 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3700 sink_irq_vector
, 1) == 1;
3704 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3708 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3710 sink_irq_vector
, 14);
3717 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3719 uint8_t test_result
= DP_TEST_ACK
;
3723 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3725 uint8_t test_result
= DP_TEST_NAK
;
3729 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3731 uint8_t test_result
= DP_TEST_NAK
;
3732 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3733 struct drm_connector
*connector
= &intel_connector
->base
;
3735 if (intel_connector
->detect_edid
== NULL
||
3736 connector
->edid_corrupt
||
3737 intel_dp
->aux
.i2c_defer_count
> 6) {
3738 /* Check EDID read for NACKs, DEFERs and corruption
3739 * (DP CTS 1.2 Core r1.1)
3740 * 4.2.2.4 : Failed EDID read, I2C_NAK
3741 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3742 * 4.2.2.6 : EDID corruption detected
3743 * Use failsafe mode for all cases
3745 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3746 intel_dp
->aux
.i2c_defer_count
> 0)
3747 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3748 intel_dp
->aux
.i2c_nack_count
,
3749 intel_dp
->aux
.i2c_defer_count
);
3750 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3752 struct edid
*block
= intel_connector
->detect_edid
;
3754 /* We have to write the checksum
3755 * of the last block read
3757 block
+= intel_connector
->detect_edid
->extensions
;
3759 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3760 DP_TEST_EDID_CHECKSUM
,
3763 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3765 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3766 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3769 /* Set test active flag here so userspace doesn't interrupt things */
3770 intel_dp
->compliance_test_active
= 1;
3775 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3777 uint8_t test_result
= DP_TEST_NAK
;
3781 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3783 uint8_t response
= DP_TEST_NAK
;
3787 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3789 DRM_DEBUG_KMS("Could not read test request from sink\n");
3794 case DP_TEST_LINK_TRAINING
:
3795 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3796 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3797 response
= intel_dp_autotest_link_training(intel_dp
);
3799 case DP_TEST_LINK_VIDEO_PATTERN
:
3800 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3801 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3802 response
= intel_dp_autotest_video_pattern(intel_dp
);
3804 case DP_TEST_LINK_EDID_READ
:
3805 DRM_DEBUG_KMS("EDID test requested\n");
3806 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3807 response
= intel_dp_autotest_edid(intel_dp
);
3809 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3810 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3811 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3812 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3815 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3820 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3824 DRM_DEBUG_KMS("Could not write test response to sink\n");
3828 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3832 if (intel_dp
->is_mst
) {
3837 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3841 /* check link status - esi[10] = 0x200c */
3842 if (intel_dp
->active_mst_links
&&
3843 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3844 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3845 intel_dp_start_link_train(intel_dp
);
3846 intel_dp_stop_link_train(intel_dp
);
3849 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3850 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3853 for (retry
= 0; retry
< 3; retry
++) {
3855 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3856 DP_SINK_COUNT_ESI
+1,
3863 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3865 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3873 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3874 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3875 intel_dp
->is_mst
= false;
3876 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3877 /* send a hotplug event */
3878 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3885 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3887 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3888 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3889 u8 link_status
[DP_LINK_STATUS_SIZE
];
3891 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3893 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3894 DRM_ERROR("Failed to get link status\n");
3898 if (!intel_encoder
->base
.crtc
)
3901 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3904 /* if link training is requested we should perform it always */
3905 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
3906 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
3907 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3908 intel_encoder
->base
.name
);
3909 intel_dp_start_link_train(intel_dp
);
3910 intel_dp_stop_link_train(intel_dp
);
3915 * According to DP spec
3918 * 2. Configure link according to Receiver Capabilities
3919 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3920 * 4. Check link status on receipt of hot-plug interrupt
3922 * intel_dp_short_pulse - handles short pulse interrupts
3923 * when full detection is not required.
3924 * Returns %true if short pulse is handled and full detection
3925 * is NOT required and %false otherwise.
3928 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
3930 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3931 u8 sink_irq_vector
= 0;
3932 u8 old_sink_count
= intel_dp
->sink_count
;
3936 * Clearing compliance test variables to allow capturing
3937 * of values for next automated test request.
3939 intel_dp
->compliance_test_active
= 0;
3940 intel_dp
->compliance_test_type
= 0;
3941 intel_dp
->compliance_test_data
= 0;
3944 * Now read the DPCD to see if it's actually running
3945 * If the current value of sink count doesn't match with
3946 * the value that was stored earlier or dpcd read failed
3947 * we need to do full detection
3949 ret
= intel_dp_get_dpcd(intel_dp
);
3951 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
3952 /* No need to proceed if we are going to do full detect */
3956 /* Try to read the source of the interrupt */
3957 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3958 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
3959 sink_irq_vector
!= 0) {
3960 /* Clear interrupt source */
3961 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3962 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3965 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3966 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3967 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3968 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3971 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
3972 intel_dp_check_link_status(intel_dp
);
3973 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
3978 /* XXX this is probably wrong for multiple downstream ports */
3979 static enum drm_connector_status
3980 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3982 uint8_t *dpcd
= intel_dp
->dpcd
;
3985 if (!intel_dp_get_dpcd(intel_dp
))
3986 return connector_status_disconnected
;
3988 if (is_edp(intel_dp
))
3989 return connector_status_connected
;
3991 /* if there's no downstream port, we're done */
3992 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3993 return connector_status_connected
;
3995 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3996 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3997 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3999 return intel_dp
->sink_count
?
4000 connector_status_connected
: connector_status_disconnected
;
4003 if (intel_dp_can_mst(intel_dp
))
4004 return connector_status_connected
;
4006 /* If no HPD, poke DDC gently */
4007 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4008 return connector_status_connected
;
4010 /* Well we tried, say unknown for unreliable port types */
4011 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4012 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4013 if (type
== DP_DS_PORT_TYPE_VGA
||
4014 type
== DP_DS_PORT_TYPE_NON_EDID
)
4015 return connector_status_unknown
;
4017 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4018 DP_DWN_STRM_PORT_TYPE_MASK
;
4019 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4020 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4021 return connector_status_unknown
;
4024 /* Anything else is out of spec, warn and ignore */
4025 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4026 return connector_status_disconnected
;
4029 static enum drm_connector_status
4030 edp_detect(struct intel_dp
*intel_dp
)
4032 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4033 enum drm_connector_status status
;
4035 status
= intel_panel_detect(dev
);
4036 if (status
== connector_status_unknown
)
4037 status
= connector_status_connected
;
4042 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4043 struct intel_digital_port
*port
)
4047 switch (port
->port
) {
4051 bit
= SDE_PORTB_HOTPLUG
;
4054 bit
= SDE_PORTC_HOTPLUG
;
4057 bit
= SDE_PORTD_HOTPLUG
;
4060 MISSING_CASE(port
->port
);
4064 return I915_READ(SDEISR
) & bit
;
4067 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4068 struct intel_digital_port
*port
)
4072 switch (port
->port
) {
4076 bit
= SDE_PORTB_HOTPLUG_CPT
;
4079 bit
= SDE_PORTC_HOTPLUG_CPT
;
4082 bit
= SDE_PORTD_HOTPLUG_CPT
;
4085 bit
= SDE_PORTE_HOTPLUG_SPT
;
4088 MISSING_CASE(port
->port
);
4092 return I915_READ(SDEISR
) & bit
;
4095 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4096 struct intel_digital_port
*port
)
4100 switch (port
->port
) {
4102 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4105 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4108 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4111 MISSING_CASE(port
->port
);
4115 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4118 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4119 struct intel_digital_port
*port
)
4123 switch (port
->port
) {
4125 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4128 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4131 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4134 MISSING_CASE(port
->port
);
4138 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4141 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4142 struct intel_digital_port
*intel_dig_port
)
4144 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4148 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4151 bit
= BXT_DE_PORT_HP_DDIA
;
4154 bit
= BXT_DE_PORT_HP_DDIB
;
4157 bit
= BXT_DE_PORT_HP_DDIC
;
4164 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4168 * intel_digital_port_connected - is the specified port connected?
4169 * @dev_priv: i915 private structure
4170 * @port: the port to test
4172 * Return %true if @port is connected, %false otherwise.
4174 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4175 struct intel_digital_port
*port
)
4177 if (HAS_PCH_IBX(dev_priv
))
4178 return ibx_digital_port_connected(dev_priv
, port
);
4179 else if (HAS_PCH_SPLIT(dev_priv
))
4180 return cpt_digital_port_connected(dev_priv
, port
);
4181 else if (IS_BROXTON(dev_priv
))
4182 return bxt_digital_port_connected(dev_priv
, port
);
4183 else if (IS_GM45(dev_priv
))
4184 return gm45_digital_port_connected(dev_priv
, port
);
4186 return g4x_digital_port_connected(dev_priv
, port
);
4189 static struct edid
*
4190 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4192 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4194 /* use cached edid if we have one */
4195 if (intel_connector
->edid
) {
4197 if (IS_ERR(intel_connector
->edid
))
4200 return drm_edid_duplicate(intel_connector
->edid
);
4202 return drm_get_edid(&intel_connector
->base
,
4203 &intel_dp
->aux
.ddc
);
4207 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4209 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4212 intel_dp_unset_edid(intel_dp
);
4213 edid
= intel_dp_get_edid(intel_dp
);
4214 intel_connector
->detect_edid
= edid
;
4216 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4217 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4219 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4223 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4225 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4227 kfree(intel_connector
->detect_edid
);
4228 intel_connector
->detect_edid
= NULL
;
4230 intel_dp
->has_audio
= false;
4234 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4236 struct drm_connector
*connector
= &intel_connector
->base
;
4237 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4238 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4239 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4240 struct drm_device
*dev
= connector
->dev
;
4241 enum drm_connector_status status
;
4242 enum intel_display_power_domain power_domain
;
4243 u8 sink_irq_vector
= 0;
4245 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4246 intel_display_power_get(to_i915(dev
), power_domain
);
4248 /* Can't disconnect eDP, but you can close the lid... */
4249 if (is_edp(intel_dp
))
4250 status
= edp_detect(intel_dp
);
4251 else if (intel_digital_port_connected(to_i915(dev
),
4252 dp_to_dig_port(intel_dp
)))
4253 status
= intel_dp_detect_dpcd(intel_dp
);
4255 status
= connector_status_disconnected
;
4257 if (status
!= connector_status_connected
) {
4258 intel_dp
->compliance_test_active
= 0;
4259 intel_dp
->compliance_test_type
= 0;
4260 intel_dp
->compliance_test_data
= 0;
4262 if (intel_dp
->is_mst
) {
4263 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4265 intel_dp
->mst_mgr
.mst_state
);
4266 intel_dp
->is_mst
= false;
4267 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4274 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4275 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4277 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4278 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
4279 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
4281 intel_dp_print_rates(intel_dp
);
4283 intel_dp_probe_oui(intel_dp
);
4285 intel_dp_configure_mst(intel_dp
);
4287 if (intel_dp
->is_mst
) {
4289 * If we are in MST mode then this connector
4290 * won't appear connected or have anything
4293 status
= connector_status_disconnected
;
4295 } else if (connector
->status
== connector_status_connected
) {
4297 * If display was connected already and is still connected
4298 * check links status, there has been known issues of
4299 * link loss triggerring long pulse!!!!
4301 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4302 intel_dp_check_link_status(intel_dp
);
4303 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4308 * Clearing NACK and defer counts to get their exact values
4309 * while reading EDID which are required by Compliance tests
4310 * 4.2.2.4 and 4.2.2.5
4312 intel_dp
->aux
.i2c_nack_count
= 0;
4313 intel_dp
->aux
.i2c_defer_count
= 0;
4315 intel_dp_set_edid(intel_dp
);
4317 status
= connector_status_connected
;
4318 intel_dp
->detect_done
= true;
4320 /* Try to read the source of the interrupt */
4321 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4322 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
) &&
4323 sink_irq_vector
!= 0) {
4324 /* Clear interrupt source */
4325 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4326 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4329 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4330 intel_dp_handle_test_request(intel_dp
);
4331 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4332 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4336 if ((status
!= connector_status_connected
) &&
4337 (intel_dp
->is_mst
== false))
4338 intel_dp_unset_edid(intel_dp
);
4340 intel_display_power_put(to_i915(dev
), power_domain
);
4344 static enum drm_connector_status
4345 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4347 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4348 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4349 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4350 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4352 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4353 connector
->base
.id
, connector
->name
);
4355 if (intel_dp
->is_mst
) {
4356 /* MST devices are disconnected from a monitor POV */
4357 intel_dp_unset_edid(intel_dp
);
4358 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4359 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4360 return connector_status_disconnected
;
4363 /* If full detect is not performed yet, do a full detect */
4364 if (!intel_dp
->detect_done
)
4365 intel_dp_long_pulse(intel_dp
->attached_connector
);
4367 intel_dp
->detect_done
= false;
4369 if (is_edp(intel_dp
) || intel_connector
->detect_edid
)
4370 return connector_status_connected
;
4372 return connector_status_disconnected
;
4376 intel_dp_force(struct drm_connector
*connector
)
4378 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4379 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4380 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4381 enum intel_display_power_domain power_domain
;
4383 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4384 connector
->base
.id
, connector
->name
);
4385 intel_dp_unset_edid(intel_dp
);
4387 if (connector
->status
!= connector_status_connected
)
4390 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4391 intel_display_power_get(dev_priv
, power_domain
);
4393 intel_dp_set_edid(intel_dp
);
4395 intel_display_power_put(dev_priv
, power_domain
);
4397 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4398 intel_encoder
->type
= INTEL_OUTPUT_DP
;
4401 static int intel_dp_get_modes(struct drm_connector
*connector
)
4403 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4406 edid
= intel_connector
->detect_edid
;
4408 int ret
= intel_connector_update_modes(connector
, edid
);
4413 /* if eDP has no EDID, fall back to fixed mode */
4414 if (is_edp(intel_attached_dp(connector
)) &&
4415 intel_connector
->panel
.fixed_mode
) {
4416 struct drm_display_mode
*mode
;
4418 mode
= drm_mode_duplicate(connector
->dev
,
4419 intel_connector
->panel
.fixed_mode
);
4421 drm_mode_probed_add(connector
, mode
);
4430 intel_dp_detect_audio(struct drm_connector
*connector
)
4432 bool has_audio
= false;
4435 edid
= to_intel_connector(connector
)->detect_edid
;
4437 has_audio
= drm_detect_monitor_audio(edid
);
4443 intel_dp_set_property(struct drm_connector
*connector
,
4444 struct drm_property
*property
,
4447 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
4448 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4449 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4450 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4453 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4457 if (property
== dev_priv
->force_audio_property
) {
4461 if (i
== intel_dp
->force_audio
)
4464 intel_dp
->force_audio
= i
;
4466 if (i
== HDMI_AUDIO_AUTO
)
4467 has_audio
= intel_dp_detect_audio(connector
);
4469 has_audio
= (i
== HDMI_AUDIO_ON
);
4471 if (has_audio
== intel_dp
->has_audio
)
4474 intel_dp
->has_audio
= has_audio
;
4478 if (property
== dev_priv
->broadcast_rgb_property
) {
4479 bool old_auto
= intel_dp
->color_range_auto
;
4480 bool old_range
= intel_dp
->limited_color_range
;
4483 case INTEL_BROADCAST_RGB_AUTO
:
4484 intel_dp
->color_range_auto
= true;
4486 case INTEL_BROADCAST_RGB_FULL
:
4487 intel_dp
->color_range_auto
= false;
4488 intel_dp
->limited_color_range
= false;
4490 case INTEL_BROADCAST_RGB_LIMITED
:
4491 intel_dp
->color_range_auto
= false;
4492 intel_dp
->limited_color_range
= true;
4498 if (old_auto
== intel_dp
->color_range_auto
&&
4499 old_range
== intel_dp
->limited_color_range
)
4505 if (is_edp(intel_dp
) &&
4506 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4507 if (val
== DRM_MODE_SCALE_NONE
) {
4508 DRM_DEBUG_KMS("no scaling not supported\n");
4511 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4512 val
== DRM_MODE_SCALE_CENTER
) {
4513 DRM_DEBUG_KMS("centering not supported\n");
4517 if (intel_connector
->panel
.fitting_mode
== val
) {
4518 /* the eDP scaling property is not changed */
4521 intel_connector
->panel
.fitting_mode
= val
;
4529 if (intel_encoder
->base
.crtc
)
4530 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4536 intel_dp_connector_register(struct drm_connector
*connector
)
4538 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4541 ret
= intel_connector_register(connector
);
4545 i915_debugfs_connector_add(connector
);
4547 DRM_DEBUG_KMS("registering %s bus for %s\n",
4548 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4550 intel_dp
->aux
.dev
= connector
->kdev
;
4551 return drm_dp_aux_register(&intel_dp
->aux
);
4555 intel_dp_connector_unregister(struct drm_connector
*connector
)
4557 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4558 intel_connector_unregister(connector
);
4562 intel_dp_connector_destroy(struct drm_connector
*connector
)
4564 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4566 kfree(intel_connector
->detect_edid
);
4568 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4569 kfree(intel_connector
->edid
);
4571 /* Can't call is_edp() since the encoder may have been destroyed
4573 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4574 intel_panel_fini(&intel_connector
->panel
);
4576 drm_connector_cleanup(connector
);
4580 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4582 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4583 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4585 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4586 if (is_edp(intel_dp
)) {
4587 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4589 * vdd might still be enabled do to the delayed vdd off.
4590 * Make sure vdd is actually turned off here.
4593 edp_panel_vdd_off_sync(intel_dp
);
4594 pps_unlock(intel_dp
);
4596 if (intel_dp
->edp_notifier
.notifier_call
) {
4597 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4598 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4602 intel_dp_aux_fini(intel_dp
);
4604 drm_encoder_cleanup(encoder
);
4605 kfree(intel_dig_port
);
4608 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4610 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4612 if (!is_edp(intel_dp
))
4616 * vdd might still be enabled do to the delayed vdd off.
4617 * Make sure vdd is actually turned off here.
4619 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4621 edp_panel_vdd_off_sync(intel_dp
);
4622 pps_unlock(intel_dp
);
4625 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4627 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4628 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4629 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4630 enum intel_display_power_domain power_domain
;
4632 lockdep_assert_held(&dev_priv
->pps_mutex
);
4634 if (!edp_have_panel_vdd(intel_dp
))
4638 * The VDD bit needs a power domain reference, so if the bit is
4639 * already enabled when we boot or resume, grab this reference and
4640 * schedule a vdd off, so we don't hold on to the reference
4643 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4644 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4645 intel_display_power_get(dev_priv
, power_domain
);
4647 edp_panel_vdd_schedule_off(intel_dp
);
4650 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4652 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4653 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
4655 if (!HAS_DDI(dev_priv
))
4656 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4658 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4663 /* Reinit the power sequencer, in case BIOS did something with it. */
4664 intel_dp_pps_init(encoder
->dev
, intel_dp
);
4665 intel_edp_panel_vdd_sanitize(intel_dp
);
4667 pps_unlock(intel_dp
);
4670 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4671 .dpms
= drm_atomic_helper_connector_dpms
,
4672 .detect
= intel_dp_detect
,
4673 .force
= intel_dp_force
,
4674 .fill_modes
= drm_helper_probe_single_connector_modes
,
4675 .set_property
= intel_dp_set_property
,
4676 .atomic_get_property
= intel_connector_atomic_get_property
,
4677 .late_register
= intel_dp_connector_register
,
4678 .early_unregister
= intel_dp_connector_unregister
,
4679 .destroy
= intel_dp_connector_destroy
,
4680 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4681 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4684 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4685 .get_modes
= intel_dp_get_modes
,
4686 .mode_valid
= intel_dp_mode_valid
,
4689 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4690 .reset
= intel_dp_encoder_reset
,
4691 .destroy
= intel_dp_encoder_destroy
,
4695 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4697 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4698 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4699 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4700 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4701 enum intel_display_power_domain power_domain
;
4702 enum irqreturn ret
= IRQ_NONE
;
4704 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4705 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4706 intel_dig_port
->base
.type
= INTEL_OUTPUT_DP
;
4708 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4710 * vdd off can generate a long pulse on eDP which
4711 * would require vdd on to handle it, and thus we
4712 * would end up in an endless cycle of
4713 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4715 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4716 port_name(intel_dig_port
->port
));
4720 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4721 port_name(intel_dig_port
->port
),
4722 long_hpd
? "long" : "short");
4724 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4725 intel_display_power_get(dev_priv
, power_domain
);
4728 intel_dp_long_pulse(intel_dp
->attached_connector
);
4729 if (intel_dp
->is_mst
)
4734 if (intel_dp
->is_mst
) {
4735 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4737 * If we were in MST mode, and device is not
4738 * there, get out of MST mode
4740 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4741 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4742 intel_dp
->is_mst
= false;
4743 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4749 if (!intel_dp
->is_mst
) {
4750 if (!intel_dp_short_pulse(intel_dp
)) {
4751 intel_dp_long_pulse(intel_dp
->attached_connector
);
4760 intel_display_power_put(dev_priv
, power_domain
);
4765 /* check the VBT to see whether the eDP is on another port */
4766 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4771 * eDP not supported on g4x. so bail out early just
4772 * for a bit extra safety in case the VBT is bonkers.
4774 if (INTEL_INFO(dev
)->gen
< 5)
4780 return intel_bios_is_port_edp(dev_priv
, port
);
4784 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4786 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4788 intel_attach_force_audio_property(connector
);
4789 intel_attach_broadcast_rgb_property(connector
);
4790 intel_dp
->color_range_auto
= true;
4792 if (is_edp(intel_dp
)) {
4793 drm_mode_create_scaling_mode_property(connector
->dev
);
4794 drm_object_attach_property(
4796 connector
->dev
->mode_config
.scaling_mode_property
,
4797 DRM_MODE_SCALE_ASPECT
);
4798 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4802 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4804 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4805 intel_dp
->last_power_on
= jiffies
;
4806 intel_dp
->last_backlight_off
= jiffies
;
4810 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
4811 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
4813 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4814 struct pps_registers regs
;
4816 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4818 /* Workaround: Need to write PP_CONTROL with the unlock key as
4819 * the very first thing. */
4820 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4822 pp_on
= I915_READ(regs
.pp_on
);
4823 pp_off
= I915_READ(regs
.pp_off
);
4824 if (!IS_BROXTON(dev_priv
)) {
4825 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
4826 pp_div
= I915_READ(regs
.pp_div
);
4829 /* Pull timing values out of registers */
4830 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4831 PANEL_POWER_UP_DELAY_SHIFT
;
4833 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4834 PANEL_LIGHT_ON_DELAY_SHIFT
;
4836 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4837 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4839 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4840 PANEL_POWER_DOWN_DELAY_SHIFT
;
4842 if (IS_BROXTON(dev_priv
)) {
4843 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4844 BXT_POWER_CYCLE_DELAY_SHIFT
;
4846 seq
->t11_t12
= (tmp
- 1) * 1000;
4850 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4851 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4856 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
4858 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4860 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
4864 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
4865 struct intel_dp
*intel_dp
)
4867 struct edp_power_seq hw
;
4868 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
4870 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
4872 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
4873 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
4874 DRM_ERROR("PPS state mismatch\n");
4875 intel_pps_dump_state("sw", sw
);
4876 intel_pps_dump_state("hw", &hw
);
4881 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4882 struct intel_dp
*intel_dp
)
4884 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4885 struct edp_power_seq cur
, vbt
, spec
,
4886 *final
= &intel_dp
->pps_delays
;
4888 lockdep_assert_held(&dev_priv
->pps_mutex
);
4890 /* already initialized? */
4891 if (final
->t11_t12
!= 0)
4894 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
4896 intel_pps_dump_state("cur", &cur
);
4898 vbt
= dev_priv
->vbt
.edp
.pps
;
4900 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4901 * our hw here, which are all in 100usec. */
4902 spec
.t1_t3
= 210 * 10;
4903 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4904 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4905 spec
.t10
= 500 * 10;
4906 /* This one is special and actually in units of 100ms, but zero
4907 * based in the hw (so we need to add 100 ms). But the sw vbt
4908 * table multiplies it with 1000 to make it in units of 100usec,
4910 spec
.t11_t12
= (510 + 100) * 10;
4912 intel_pps_dump_state("vbt", &vbt
);
4914 /* Use the max of the register settings and vbt. If both are
4915 * unset, fall back to the spec limits. */
4916 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4918 max(cur.field, vbt.field))
4919 assign_final(t1_t3
);
4923 assign_final(t11_t12
);
4926 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4927 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4928 intel_dp
->backlight_on_delay
= get_delay(t8
);
4929 intel_dp
->backlight_off_delay
= get_delay(t9
);
4930 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4931 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4934 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4935 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4936 intel_dp
->panel_power_cycle_delay
);
4938 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4939 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4942 * We override the HW backlight delays to 1 because we do manual waits
4943 * on them. For T8, even BSpec recommends doing it. For T9, if we
4944 * don't do this, we'll end up waiting for the backlight off delay
4945 * twice: once when we do the manual sleep, and once when we disable
4946 * the panel and wait for the PP_STATUS bit to become zero.
4953 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4954 struct intel_dp
*intel_dp
)
4956 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4957 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4958 int div
= dev_priv
->rawclk_freq
/ 1000;
4959 struct pps_registers regs
;
4960 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4961 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4963 lockdep_assert_held(&dev_priv
->pps_mutex
);
4965 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4967 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4968 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
4969 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4970 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4971 /* Compute the divisor for the pp clock, simply match the Bspec
4973 if (IS_BROXTON(dev
)) {
4974 pp_div
= I915_READ(regs
.pp_ctrl
);
4975 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
4976 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
4977 << BXT_POWER_CYCLE_DELAY_SHIFT
);
4979 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4980 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4981 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4984 /* Haswell doesn't have any port selection bits for the panel
4985 * power sequencer any more. */
4986 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
4987 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4988 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4990 port_sel
= PANEL_PORT_SELECT_DPA
;
4992 port_sel
= PANEL_PORT_SELECT_DPD
;
4997 I915_WRITE(regs
.pp_on
, pp_on
);
4998 I915_WRITE(regs
.pp_off
, pp_off
);
4999 if (IS_BROXTON(dev
))
5000 I915_WRITE(regs
.pp_ctrl
, pp_div
);
5002 I915_WRITE(regs
.pp_div
, pp_div
);
5004 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5005 I915_READ(regs
.pp_on
),
5006 I915_READ(regs
.pp_off
),
5008 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5009 I915_READ(regs
.pp_div
));
5012 static void intel_dp_pps_init(struct drm_device
*dev
,
5013 struct intel_dp
*intel_dp
)
5015 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5016 vlv_initial_power_sequencer_setup(intel_dp
);
5018 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5019 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5024 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5026 * @refresh_rate: RR to be programmed
5028 * This function gets called when refresh rate (RR) has to be changed from
5029 * one frequency to another. Switches can be between high and low RR
5030 * supported by the panel or to any other RR based on media playback (in
5031 * this case, RR value needs to be passed from user space).
5033 * The caller of this function needs to take a lock on dev_priv->drrs.
5035 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5037 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5038 struct intel_encoder
*encoder
;
5039 struct intel_digital_port
*dig_port
= NULL
;
5040 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5041 struct intel_crtc_state
*config
= NULL
;
5042 struct intel_crtc
*intel_crtc
= NULL
;
5043 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5045 if (refresh_rate
<= 0) {
5046 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5050 if (intel_dp
== NULL
) {
5051 DRM_DEBUG_KMS("DRRS not supported.\n");
5056 * FIXME: This needs proper synchronization with psr state for some
5057 * platforms that cannot have PSR and DRRS enabled at the same time.
5060 dig_port
= dp_to_dig_port(intel_dp
);
5061 encoder
= &dig_port
->base
;
5062 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5065 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5069 config
= intel_crtc
->config
;
5071 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5072 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5076 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5078 index
= DRRS_LOW_RR
;
5080 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5082 "DRRS requested for previously set RR...ignoring\n");
5086 if (!intel_crtc
->active
) {
5087 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5091 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5094 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5097 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5101 DRM_ERROR("Unsupported refreshrate type\n");
5103 } else if (INTEL_INFO(dev
)->gen
> 6) {
5104 i915_reg_t reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5107 val
= I915_READ(reg
);
5108 if (index
> DRRS_HIGH_RR
) {
5109 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5110 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5112 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5114 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5115 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5117 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5119 I915_WRITE(reg
, val
);
5122 dev_priv
->drrs
.refresh_rate_type
= index
;
5124 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5128 * intel_edp_drrs_enable - init drrs struct if supported
5129 * @intel_dp: DP struct
5131 * Initializes frontbuffer_bits and drrs.dp
5133 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5135 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5136 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5137 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5138 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5139 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5141 if (!intel_crtc
->config
->has_drrs
) {
5142 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5146 mutex_lock(&dev_priv
->drrs
.mutex
);
5147 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5148 DRM_ERROR("DRRS already enabled\n");
5152 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5154 dev_priv
->drrs
.dp
= intel_dp
;
5157 mutex_unlock(&dev_priv
->drrs
.mutex
);
5161 * intel_edp_drrs_disable - Disable DRRS
5162 * @intel_dp: DP struct
5165 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5167 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5168 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5169 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5170 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5173 if (!intel_crtc
->config
->has_drrs
)
5176 mutex_lock(&dev_priv
->drrs
.mutex
);
5177 if (!dev_priv
->drrs
.dp
) {
5178 mutex_unlock(&dev_priv
->drrs
.mutex
);
5182 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5183 intel_dp_set_drrs_state(&dev_priv
->drm
,
5184 intel_dp
->attached_connector
->panel
.
5185 fixed_mode
->vrefresh
);
5187 dev_priv
->drrs
.dp
= NULL
;
5188 mutex_unlock(&dev_priv
->drrs
.mutex
);
5190 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5193 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5195 struct drm_i915_private
*dev_priv
=
5196 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5197 struct intel_dp
*intel_dp
;
5199 mutex_lock(&dev_priv
->drrs
.mutex
);
5201 intel_dp
= dev_priv
->drrs
.dp
;
5207 * The delayed work can race with an invalidate hence we need to
5211 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5214 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5215 intel_dp_set_drrs_state(&dev_priv
->drm
,
5216 intel_dp
->attached_connector
->panel
.
5217 downclock_mode
->vrefresh
);
5220 mutex_unlock(&dev_priv
->drrs
.mutex
);
5224 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5225 * @dev_priv: i915 device
5226 * @frontbuffer_bits: frontbuffer plane tracking bits
5228 * This function gets called everytime rendering on the given planes start.
5229 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5231 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5233 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
5234 unsigned int frontbuffer_bits
)
5236 struct drm_crtc
*crtc
;
5239 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5242 cancel_delayed_work(&dev_priv
->drrs
.work
);
5244 mutex_lock(&dev_priv
->drrs
.mutex
);
5245 if (!dev_priv
->drrs
.dp
) {
5246 mutex_unlock(&dev_priv
->drrs
.mutex
);
5250 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5251 pipe
= to_intel_crtc(crtc
)->pipe
;
5253 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5254 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5256 /* invalidate means busy screen hence upclock */
5257 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5258 intel_dp_set_drrs_state(&dev_priv
->drm
,
5259 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5260 fixed_mode
->vrefresh
);
5262 mutex_unlock(&dev_priv
->drrs
.mutex
);
5266 * intel_edp_drrs_flush - Restart Idleness DRRS
5267 * @dev_priv: i915 device
5268 * @frontbuffer_bits: frontbuffer plane tracking bits
5270 * This function gets called every time rendering on the given planes has
5271 * completed or flip on a crtc is completed. So DRRS should be upclocked
5272 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5273 * if no other planes are dirty.
5275 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5277 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
5278 unsigned int frontbuffer_bits
)
5280 struct drm_crtc
*crtc
;
5283 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5286 cancel_delayed_work(&dev_priv
->drrs
.work
);
5288 mutex_lock(&dev_priv
->drrs
.mutex
);
5289 if (!dev_priv
->drrs
.dp
) {
5290 mutex_unlock(&dev_priv
->drrs
.mutex
);
5294 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5295 pipe
= to_intel_crtc(crtc
)->pipe
;
5297 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5298 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5300 /* flush means busy screen hence upclock */
5301 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5302 intel_dp_set_drrs_state(&dev_priv
->drm
,
5303 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5304 fixed_mode
->vrefresh
);
5307 * flush also means no more activity hence schedule downclock, if all
5308 * other fbs are quiescent too
5310 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5311 schedule_delayed_work(&dev_priv
->drrs
.work
,
5312 msecs_to_jiffies(1000));
5313 mutex_unlock(&dev_priv
->drrs
.mutex
);
5317 * DOC: Display Refresh Rate Switching (DRRS)
5319 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5320 * which enables swtching between low and high refresh rates,
5321 * dynamically, based on the usage scenario. This feature is applicable
5322 * for internal panels.
5324 * Indication that the panel supports DRRS is given by the panel EDID, which
5325 * would list multiple refresh rates for one resolution.
5327 * DRRS is of 2 types - static and seamless.
5328 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5329 * (may appear as a blink on screen) and is used in dock-undock scenario.
5330 * Seamless DRRS involves changing RR without any visual effect to the user
5331 * and can be used during normal system usage. This is done by programming
5332 * certain registers.
5334 * Support for static/seamless DRRS may be indicated in the VBT based on
5335 * inputs from the panel spec.
5337 * DRRS saves power by switching to low RR based on usage scenarios.
5339 * The implementation is based on frontbuffer tracking implementation. When
5340 * there is a disturbance on the screen triggered by user activity or a periodic
5341 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5342 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5345 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5346 * and intel_edp_drrs_flush() are called.
5348 * DRRS can be further extended to support other internal panels and also
5349 * the scenario of video playback wherein RR is set based on the rate
5350 * requested by userspace.
5354 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5355 * @intel_connector: eDP connector
5356 * @fixed_mode: preferred mode of panel
5358 * This function is called only once at driver load to initialize basic
5362 * Downclock mode if panel supports it, else return NULL.
5363 * DRRS support is determined by the presence of downclock mode (apart
5364 * from VBT setting).
5366 static struct drm_display_mode
*
5367 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5368 struct drm_display_mode
*fixed_mode
)
5370 struct drm_connector
*connector
= &intel_connector
->base
;
5371 struct drm_device
*dev
= connector
->dev
;
5372 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5373 struct drm_display_mode
*downclock_mode
= NULL
;
5375 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5376 mutex_init(&dev_priv
->drrs
.mutex
);
5378 if (INTEL_INFO(dev
)->gen
<= 6) {
5379 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5383 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5384 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5388 downclock_mode
= intel_find_panel_downclock
5389 (dev
, fixed_mode
, connector
);
5391 if (!downclock_mode
) {
5392 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5396 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5398 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5399 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5400 return downclock_mode
;
5403 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5404 struct intel_connector
*intel_connector
)
5406 struct drm_connector
*connector
= &intel_connector
->base
;
5407 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5408 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5409 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5410 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5411 struct drm_display_mode
*fixed_mode
= NULL
;
5412 struct drm_display_mode
*downclock_mode
= NULL
;
5414 struct drm_display_mode
*scan
;
5416 enum pipe pipe
= INVALID_PIPE
;
5418 if (!is_edp(intel_dp
))
5422 * On IBX/CPT we may get here with LVDS already registered. Since the
5423 * driver uses the only internal power sequencer available for both
5424 * eDP and LVDS bail out early in this case to prevent interfering
5425 * with an already powered-on LVDS power sequencer.
5427 if (intel_get_lvds_encoder(dev
)) {
5428 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5429 DRM_INFO("LVDS was detected, not registering eDP\n");
5436 intel_dp_init_panel_power_timestamps(intel_dp
);
5437 intel_dp_pps_init(dev
, intel_dp
);
5438 intel_edp_panel_vdd_sanitize(intel_dp
);
5440 pps_unlock(intel_dp
);
5442 /* Cache DPCD and EDID for edp. */
5443 has_dpcd
= intel_edp_init_dpcd(intel_dp
);
5446 /* if this fails, presume the device is a ghost */
5447 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5451 mutex_lock(&dev
->mode_config
.mutex
);
5452 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5454 if (drm_add_edid_modes(connector
, edid
)) {
5455 drm_mode_connector_update_edid_property(connector
,
5457 drm_edid_to_eld(connector
, edid
);
5460 edid
= ERR_PTR(-EINVAL
);
5463 edid
= ERR_PTR(-ENOENT
);
5465 intel_connector
->edid
= edid
;
5467 /* prefer fixed mode from EDID if available */
5468 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5469 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5470 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5471 downclock_mode
= intel_dp_drrs_init(
5472 intel_connector
, fixed_mode
);
5477 /* fallback to VBT if available for eDP */
5478 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5479 fixed_mode
= drm_mode_duplicate(dev
,
5480 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5482 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5483 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5484 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5487 mutex_unlock(&dev
->mode_config
.mutex
);
5489 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5490 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5491 register_reboot_notifier(&intel_dp
->edp_notifier
);
5494 * Figure out the current pipe for the initial backlight setup.
5495 * If the current pipe isn't valid, try the PPS pipe, and if that
5496 * fails just assume pipe A.
5498 if (IS_CHERRYVIEW(dev
))
5499 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5501 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5503 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5504 pipe
= intel_dp
->pps_pipe
;
5506 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5509 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5513 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5514 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5515 intel_panel_setup_backlight(connector
, pipe
);
5520 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5522 * vdd might still be enabled do to the delayed vdd off.
5523 * Make sure vdd is actually turned off here.
5526 edp_panel_vdd_off_sync(intel_dp
);
5527 pps_unlock(intel_dp
);
5533 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5534 struct intel_connector
*intel_connector
)
5536 struct drm_connector
*connector
= &intel_connector
->base
;
5537 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5538 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5539 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5540 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5541 enum port port
= intel_dig_port
->port
;
5544 if (WARN(intel_dig_port
->max_lanes
< 1,
5545 "Not enough lanes (%d) for DP on port %c\n",
5546 intel_dig_port
->max_lanes
, port_name(port
)))
5549 intel_dp
->pps_pipe
= INVALID_PIPE
;
5551 /* intel_dp vfuncs */
5552 if (INTEL_INFO(dev
)->gen
>= 9)
5553 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5554 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5555 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5556 else if (HAS_PCH_SPLIT(dev
))
5557 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5559 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5561 if (INTEL_INFO(dev
)->gen
>= 9)
5562 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5564 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5567 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5569 /* Preserve the current hw state. */
5570 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5571 intel_dp
->attached_connector
= intel_connector
;
5573 if (intel_dp_is_edp(dev
, port
))
5574 type
= DRM_MODE_CONNECTOR_eDP
;
5576 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5579 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5580 * for DP the encoder type can be set by the caller to
5581 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5583 if (type
== DRM_MODE_CONNECTOR_eDP
)
5584 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5586 /* eDP only on port B and/or C on vlv/chv */
5587 if (WARN_ON((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
5588 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5591 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5592 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5595 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5596 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5598 connector
->interlace_allowed
= true;
5599 connector
->doublescan_allowed
= 0;
5601 intel_dp_aux_init(intel_dp
, intel_connector
);
5603 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5604 edp_panel_vdd_work
);
5606 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5609 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5611 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5613 /* Set up the hotplug pin. */
5616 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5619 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5620 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5621 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5624 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5627 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5630 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5636 /* init MST on ports that can support it */
5637 if (HAS_DP_MST(dev
) && !is_edp(intel_dp
) &&
5638 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5639 intel_dp_mst_encoder_init(intel_dig_port
,
5640 intel_connector
->base
.base
.id
);
5642 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5643 intel_dp_aux_fini(intel_dp
);
5644 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5648 intel_dp_add_properties(intel_dp
, connector
);
5650 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5651 * 0xd. Failure to do so will result in spurious interrupts being
5652 * generated on the port when a cable is not attached.
5654 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5655 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5656 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5662 drm_connector_cleanup(connector
);
5667 bool intel_dp_init(struct drm_device
*dev
,
5668 i915_reg_t output_reg
,
5671 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5672 struct intel_digital_port
*intel_dig_port
;
5673 struct intel_encoder
*intel_encoder
;
5674 struct drm_encoder
*encoder
;
5675 struct intel_connector
*intel_connector
;
5677 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5678 if (!intel_dig_port
)
5681 intel_connector
= intel_connector_alloc();
5682 if (!intel_connector
)
5683 goto err_connector_alloc
;
5685 intel_encoder
= &intel_dig_port
->base
;
5686 encoder
= &intel_encoder
->base
;
5688 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5689 DRM_MODE_ENCODER_TMDS
, "DP %c", port_name(port
)))
5690 goto err_encoder_init
;
5692 intel_encoder
->compute_config
= intel_dp_compute_config
;
5693 intel_encoder
->disable
= intel_disable_dp
;
5694 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5695 intel_encoder
->get_config
= intel_dp_get_config
;
5696 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5697 if (IS_CHERRYVIEW(dev
)) {
5698 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5699 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5700 intel_encoder
->enable
= vlv_enable_dp
;
5701 intel_encoder
->post_disable
= chv_post_disable_dp
;
5702 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5703 } else if (IS_VALLEYVIEW(dev
)) {
5704 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5705 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5706 intel_encoder
->enable
= vlv_enable_dp
;
5707 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5709 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5710 intel_encoder
->enable
= g4x_enable_dp
;
5711 if (INTEL_INFO(dev
)->gen
>= 5)
5712 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5715 intel_dig_port
->port
= port
;
5716 intel_dig_port
->dp
.output_reg
= output_reg
;
5717 intel_dig_port
->max_lanes
= 4;
5719 intel_encoder
->type
= INTEL_OUTPUT_DP
;
5720 if (IS_CHERRYVIEW(dev
)) {
5722 intel_encoder
->crtc_mask
= 1 << 2;
5724 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5726 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5728 intel_encoder
->cloneable
= 0;
5730 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5731 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5733 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5734 goto err_init_connector
;
5739 drm_encoder_cleanup(encoder
);
5741 kfree(intel_connector
);
5742 err_connector_alloc
:
5743 kfree(intel_dig_port
);
5747 void intel_dp_mst_suspend(struct drm_device
*dev
)
5749 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5753 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5754 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5756 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5759 if (intel_dig_port
->dp
.is_mst
)
5760 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5764 void intel_dp_mst_resume(struct drm_device
*dev
)
5766 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5769 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5770 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5773 if (!intel_dig_port
|| !intel_dig_port
->dp
.can_mst
)
5776 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5778 intel_dp_check_mst_status(&intel_dig_port
->dp
);