2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int chv_rates
[] = { 162000, 202500, 210000, 216000,
99 243000, 270000, 324000, 405000,
100 420000, 432000, 540000 };
101 static const int default_rates
[] = { 162000, 270000, 540000 };
104 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
105 * @intel_dp: DP struct
107 * If a CPU or PCH DP output is attached to an eDP panel, this function
108 * will return true, and false otherwise.
110 static bool is_edp(struct intel_dp
*intel_dp
)
112 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
114 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
117 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
119 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
121 return intel_dig_port
->base
.base
.dev
;
124 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
126 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
129 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
130 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
131 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
132 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
133 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
137 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
139 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
141 switch (max_link_bw
) {
142 case DP_LINK_BW_1_62
:
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw
= DP_LINK_BW_1_62
;
155 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
157 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
158 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
159 u8 source_max
, sink_max
;
162 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
163 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
166 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
168 return min(source_max
, sink_max
);
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 * 270000 * 1 * 8 / 10 == 216000
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
189 intel_dp_link_required(int pixel_clock
, int bpp
)
191 return (pixel_clock
* bpp
+ 9) / 10;
195 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
197 return (max_link_clock
* max_lanes
* 8) / 10;
200 static enum drm_mode_status
201 intel_dp_mode_valid(struct drm_connector
*connector
,
202 struct drm_display_mode
*mode
)
204 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
205 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
206 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
207 int target_clock
= mode
->clock
;
208 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
210 if (is_edp(intel_dp
) && fixed_mode
) {
211 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
214 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
217 target_clock
= fixed_mode
->clock
;
220 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
221 max_lanes
= intel_dp_max_lane_count(intel_dp
);
223 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
224 mode_rate
= intel_dp_link_required(target_clock
, 18);
226 if (mode_rate
> max_rate
)
227 return MODE_CLOCK_HIGH
;
229 if (mode
->clock
< 10000)
230 return MODE_CLOCK_LOW
;
232 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
233 return MODE_H_ILLEGAL
;
238 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
245 for (i
= 0; i
< src_bytes
; i
++)
246 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
250 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
255 for (i
= 0; i
< dst_bytes
; i
++)
256 dst
[i
] = src
>> ((3-i
) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev
))
270 clkcfg
= I915_READ(CLKCFG
);
271 switch (clkcfg
& CLKCFG_FSB_MASK
) {
280 case CLKCFG_FSB_1067
:
282 case CLKCFG_FSB_1333
:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600
:
286 case CLKCFG_FSB_1600_ALT
:
294 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
295 struct intel_dp
*intel_dp
);
297 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
298 struct intel_dp
*intel_dp
);
300 static void pps_lock(struct intel_dp
*intel_dp
)
302 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
303 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
304 struct drm_device
*dev
= encoder
->base
.dev
;
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 enum intel_display_power_domain power_domain
;
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
312 power_domain
= intel_display_port_power_domain(encoder
);
313 intel_display_power_get(dev_priv
, power_domain
);
315 mutex_lock(&dev_priv
->pps_mutex
);
318 static void pps_unlock(struct intel_dp
*intel_dp
)
320 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
321 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
322 struct drm_device
*dev
= encoder
->base
.dev
;
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 enum intel_display_power_domain power_domain
;
326 mutex_unlock(&dev_priv
->pps_mutex
);
328 power_domain
= intel_display_port_power_domain(encoder
);
329 intel_display_power_put(dev_priv
, power_domain
);
333 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
336 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
338 enum pipe pipe
= intel_dp
->pps_pipe
;
342 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe
), port_name(intel_dig_port
->port
));
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
353 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
354 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
355 DP
|= DP_PORT_WIDTH(1);
356 DP
|= DP_LINK_TRAIN_PAT_1
;
358 if (IS_CHERRYVIEW(dev
))
359 DP
|= DP_PIPE_SELECT_CHV(pipe
);
360 else if (pipe
== PIPE_B
)
361 DP
|= DP_PIPEB_SELECT
;
363 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
370 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
371 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
379 I915_WRITE(intel_dp
->output_reg
, DP
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
385 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
386 POSTING_READ(intel_dp
->output_reg
);
389 vlv_force_pll_off(dev
, pipe
);
393 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
396 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
398 struct intel_encoder
*encoder
;
399 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
402 lockdep_assert_held(&dev_priv
->pps_mutex
);
404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp
));
407 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
408 return intel_dp
->pps_pipe
;
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
414 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
456 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
459 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
465 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
471 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
478 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
480 vlv_pipe_check pipe_check
)
484 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
485 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
486 PANEL_PORT_SELECT_MASK
;
488 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
491 if (!pipe_check(dev_priv
, pipe
))
501 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
503 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
504 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 enum port port
= intel_dig_port
->port
;
508 lockdep_assert_held(&dev_priv
->pps_mutex
);
510 /* try to find a pipe with this port selected */
511 /* first pick one where the panel is on */
512 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
516 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
517 vlv_pipe_has_vdd_on
);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
520 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
533 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
534 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
537 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
539 struct drm_device
*dev
= dev_priv
->dev
;
540 struct intel_encoder
*encoder
;
542 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
555 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
556 struct intel_dp
*intel_dp
;
558 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
561 intel_dp
= enc_to_intel_dp(&encoder
->base
);
562 intel_dp
->pps_pipe
= INVALID_PIPE
;
566 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
568 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
571 return BXT_PP_CONTROL(0);
572 else if (HAS_PCH_SPLIT(dev
))
573 return PCH_PP_CONTROL
;
575 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
578 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
580 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
583 return BXT_PP_STATUS(0);
584 else if (HAS_PCH_SPLIT(dev
))
585 return PCH_PP_STATUS
;
587 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
590 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
591 This function only applicable when panel PM state is not to be tracked */
592 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
595 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
597 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 u32 pp_ctrl_reg
, pp_div_reg
;
602 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
607 if (IS_VALLEYVIEW(dev
)) {
608 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
610 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
611 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
612 pp_div
= I915_READ(pp_div_reg
);
613 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
615 /* 0x1F write to PP_DIV_REG sets max cycle delay */
616 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
617 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
618 msleep(intel_dp
->panel_power_cycle_delay
);
621 pps_unlock(intel_dp
);
626 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
628 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
631 lockdep_assert_held(&dev_priv
->pps_mutex
);
633 if (IS_VALLEYVIEW(dev
) &&
634 intel_dp
->pps_pipe
== INVALID_PIPE
)
637 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
640 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
642 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
645 lockdep_assert_held(&dev_priv
->pps_mutex
);
647 if (IS_VALLEYVIEW(dev
) &&
648 intel_dp
->pps_pipe
== INVALID_PIPE
)
651 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
655 intel_dp_check_edp(struct intel_dp
*intel_dp
)
657 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
660 if (!is_edp(intel_dp
))
663 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
664 WARN(1, "eDP powered off while attempting aux channel communication.\n");
665 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
666 I915_READ(_pp_stat_reg(intel_dp
)),
667 I915_READ(_pp_ctrl_reg(intel_dp
)));
672 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
674 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
675 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
677 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
681 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
683 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
684 msecs_to_jiffies_timeout(10));
686 done
= wait_for_atomic(C
, 10) == 0;
688 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
695 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
697 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
698 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
701 * The clock divider is based off the hrawclk, and would like to run at
702 * 2MHz. So, take the hrawclk value and divide by 2 and use that
704 return index
? 0 : intel_hrawclk(dev
) / 2;
707 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
709 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
710 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
716 if (intel_dig_port
->port
== PORT_A
) {
717 return DIV_ROUND_UP(dev_priv
->cdclk_freq
, 2000);
720 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
724 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
726 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
727 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
730 if (intel_dig_port
->port
== PORT_A
) {
733 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
734 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
735 /* Workaround for non-ULT HSW */
742 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
746 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
748 return index
? 0 : 100;
751 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
754 * SKL doesn't need us to program the AUX clock divider (Hardware will
755 * derive the clock from CDCLK automatically). We still implement the
756 * get_aux_clock_divider vfunc to plug-in into the existing code.
758 return index
? 0 : 1;
761 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
764 uint32_t aux_clock_divider
)
766 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
767 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
768 uint32_t precharge
, timeout
;
775 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
776 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
778 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
780 return DP_AUX_CH_CTL_SEND_BUSY
|
782 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
783 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
785 DP_AUX_CH_CTL_RECEIVE_ERROR
|
786 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
787 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
788 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
791 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
796 return DP_AUX_CH_CTL_SEND_BUSY
|
798 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
800 DP_AUX_CH_CTL_TIME_OUT_1600us
|
801 DP_AUX_CH_CTL_RECEIVE_ERROR
|
802 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
803 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
807 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
808 const uint8_t *send
, int send_bytes
,
809 uint8_t *recv
, int recv_size
)
811 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
812 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
814 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
815 uint32_t ch_data
= ch_ctl
+ 4;
816 uint32_t aux_clock_divider
;
817 int i
, ret
, recv_bytes
;
820 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
826 * We will be called with VDD already enabled for dpcd/edid/oui reads.
827 * In such cases we want to leave VDD enabled and it's up to upper layers
828 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
831 vdd
= edp_panel_vdd_on(intel_dp
);
833 /* dp aux is extremely sensitive to irq latency, hence request the
834 * lowest possible wakeup latency and so prevent the cpu from going into
837 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
839 intel_dp_check_edp(intel_dp
);
841 intel_aux_display_runtime_get(dev_priv
);
843 /* Try to wait for any previous AUX channel activity */
844 for (try = 0; try < 3; try++) {
845 status
= I915_READ_NOTRACE(ch_ctl
);
846 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
852 static u32 last_status
= -1;
853 const u32 status
= I915_READ(ch_ctl
);
855 if (status
!= last_status
) {
856 WARN(1, "dp_aux_ch not started status 0x%08x\n",
858 last_status
= status
;
865 /* Only 5 data registers! */
866 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
871 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
872 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
877 /* Must try at least 3 times according to DP spec */
878 for (try = 0; try < 5; try++) {
879 /* Load the send data into the aux channel data registers */
880 for (i
= 0; i
< send_bytes
; i
+= 4)
881 I915_WRITE(ch_data
+ i
,
882 intel_dp_pack_aux(send
+ i
,
885 /* Send the command and wait for it to complete */
886 I915_WRITE(ch_ctl
, send_ctl
);
888 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
890 /* Clear done status and any errors */
894 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
895 DP_AUX_CH_CTL_RECEIVE_ERROR
);
897 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
900 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
901 * 400us delay required for errors and timeouts
902 * Timeout errors from the HW already meet this
903 * requirement so skip to next iteration
905 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
906 usleep_range(400, 500);
909 if (status
& DP_AUX_CH_CTL_DONE
)
914 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
915 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
921 /* Check for timeout or receive error.
922 * Timeouts occur when the sink is not connected
924 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
925 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
930 /* Timeouts occur when the device isn't connected, so they're
931 * "normal" -- don't fill the kernel log with these */
932 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
933 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
938 /* Unload any bytes sent back from the other side */
939 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
940 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
941 if (recv_bytes
> recv_size
)
942 recv_bytes
= recv_size
;
944 for (i
= 0; i
< recv_bytes
; i
+= 4)
945 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
946 recv
+ i
, recv_bytes
- i
);
950 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
951 intel_aux_display_runtime_put(dev_priv
);
954 edp_panel_vdd_off(intel_dp
, false);
956 pps_unlock(intel_dp
);
961 #define BARE_ADDRESS_SIZE 3
962 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
964 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
966 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
967 uint8_t txbuf
[20], rxbuf
[20];
968 size_t txsize
, rxsize
;
971 txbuf
[0] = (msg
->request
<< 4) |
972 ((msg
->address
>> 16) & 0xf);
973 txbuf
[1] = (msg
->address
>> 8) & 0xff;
974 txbuf
[2] = msg
->address
& 0xff;
975 txbuf
[3] = msg
->size
- 1;
977 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
978 case DP_AUX_NATIVE_WRITE
:
979 case DP_AUX_I2C_WRITE
:
980 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
981 rxsize
= 2; /* 0 or 1 data bytes */
983 if (WARN_ON(txsize
> 20))
986 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
988 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
990 msg
->reply
= rxbuf
[0] >> 4;
993 /* Number of bytes written in a short write. */
994 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
996 /* Return payload size. */
1002 case DP_AUX_NATIVE_READ
:
1003 case DP_AUX_I2C_READ
:
1004 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1005 rxsize
= msg
->size
+ 1;
1007 if (WARN_ON(rxsize
> 20))
1010 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1012 msg
->reply
= rxbuf
[0] >> 4;
1014 * Assume happy day, and copy the data. The caller is
1015 * expected to check msg->reply before touching it.
1017 * Return payload size.
1020 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1033 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1035 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1037 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1038 enum port port
= intel_dig_port
->port
;
1039 struct ddi_vbt_port_info
*info
= &dev_priv
->vbt
.ddi_port_info
[port
];
1040 const char *name
= NULL
;
1041 uint32_t porte_aux_ctl_reg
= DPA_AUX_CH_CTL
;
1044 /* On SKL we don't have Aux for port E so we rely on VBT to set
1045 * a proper alternate aux channel.
1047 if (IS_SKYLAKE(dev
) && port
== PORT_E
) {
1048 switch (info
->alternate_aux_channel
) {
1050 porte_aux_ctl_reg
= DPB_AUX_CH_CTL
;
1053 porte_aux_ctl_reg
= DPC_AUX_CH_CTL
;
1056 porte_aux_ctl_reg
= DPD_AUX_CH_CTL
;
1060 porte_aux_ctl_reg
= DPA_AUX_CH_CTL
;
1066 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1070 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1074 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1078 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1082 intel_dp
->aux_ch_ctl_reg
= porte_aux_ctl_reg
;
1090 * The AUX_CTL register is usually DP_CTL + 0x10.
1092 * On Haswell and Broadwell though:
1093 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1094 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1096 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1098 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
) && port
!= PORT_E
)
1099 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1101 intel_dp
->aux
.name
= name
;
1102 intel_dp
->aux
.dev
= dev
->dev
;
1103 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1105 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1106 connector
->base
.kdev
->kobj
.name
);
1108 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1110 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1115 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1116 &intel_dp
->aux
.ddc
.dev
.kobj
,
1117 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1119 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1120 drm_dp_aux_unregister(&intel_dp
->aux
);
1125 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1127 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1129 if (!intel_connector
->mst_port
)
1130 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1131 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1132 intel_connector_unregister(intel_connector
);
1136 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
)
1140 memset(&pipe_config
->dpll_hw_state
, 0,
1141 sizeof(pipe_config
->dpll_hw_state
));
1143 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1144 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1145 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1147 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1148 switch (pipe_config
->port_clock
/ 2) {
1150 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
1154 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
,
1158 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
,
1162 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
,
1165 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1166 results in CDCLK change. Need to handle the change of CDCLK by
1167 disabling pipes and re-enabling them */
1169 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
1173 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
,
1178 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1182 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
)
1184 memset(&pipe_config
->dpll_hw_state
, 0,
1185 sizeof(pipe_config
->dpll_hw_state
));
1187 switch (pipe_config
->port_clock
/ 2) {
1189 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1192 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1195 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1201 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1203 if (intel_dp
->num_sink_rates
) {
1204 *sink_rates
= intel_dp
->sink_rates
;
1205 return intel_dp
->num_sink_rates
;
1208 *sink_rates
= default_rates
;
1210 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1214 intel_dp_source_rates(struct drm_device
*dev
, const int **source_rates
)
1216 if (IS_BROXTON(dev
)) {
1217 *source_rates
= bxt_rates
;
1218 return ARRAY_SIZE(bxt_rates
);
1219 } else if (IS_SKYLAKE(dev
)) {
1220 *source_rates
= skl_rates
;
1221 return ARRAY_SIZE(skl_rates
);
1222 } else if (IS_CHERRYVIEW(dev
)) {
1223 *source_rates
= chv_rates
;
1224 return ARRAY_SIZE(chv_rates
);
1227 *source_rates
= default_rates
;
1229 if (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
)
1230 /* WaDisableHBR2:skl */
1231 return (DP_LINK_BW_2_7
>> 3) + 1;
1232 else if (INTEL_INFO(dev
)->gen
>= 8 ||
1233 (IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)))
1234 return (DP_LINK_BW_5_4
>> 3) + 1;
1236 return (DP_LINK_BW_2_7
>> 3) + 1;
1240 intel_dp_set_clock(struct intel_encoder
*encoder
,
1241 struct intel_crtc_state
*pipe_config
)
1243 struct drm_device
*dev
= encoder
->base
.dev
;
1244 const struct dp_link_dpll
*divisor
= NULL
;
1248 divisor
= gen4_dpll
;
1249 count
= ARRAY_SIZE(gen4_dpll
);
1250 } else if (HAS_PCH_SPLIT(dev
)) {
1252 count
= ARRAY_SIZE(pch_dpll
);
1253 } else if (IS_CHERRYVIEW(dev
)) {
1255 count
= ARRAY_SIZE(chv_dpll
);
1256 } else if (IS_VALLEYVIEW(dev
)) {
1258 count
= ARRAY_SIZE(vlv_dpll
);
1261 if (divisor
&& count
) {
1262 for (i
= 0; i
< count
; i
++) {
1263 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1264 pipe_config
->dpll
= divisor
[i
].dpll
;
1265 pipe_config
->clock_set
= true;
1272 static int intersect_rates(const int *source_rates
, int source_len
,
1273 const int *sink_rates
, int sink_len
,
1276 int i
= 0, j
= 0, k
= 0;
1278 while (i
< source_len
&& j
< sink_len
) {
1279 if (source_rates
[i
] == sink_rates
[j
]) {
1280 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1282 common_rates
[k
] = source_rates
[i
];
1286 } else if (source_rates
[i
] < sink_rates
[j
]) {
1295 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1298 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1299 const int *source_rates
, *sink_rates
;
1300 int source_len
, sink_len
;
1302 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1303 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1305 return intersect_rates(source_rates
, source_len
,
1306 sink_rates
, sink_len
,
1310 static void snprintf_int_array(char *str
, size_t len
,
1311 const int *array
, int nelem
)
1317 for (i
= 0; i
< nelem
; i
++) {
1318 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1326 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1328 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1329 const int *source_rates
, *sink_rates
;
1330 int source_len
, sink_len
, common_len
;
1331 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1332 char str
[128]; /* FIXME: too big for stack? */
1334 if ((drm_debug
& DRM_UT_KMS
) == 0)
1337 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1338 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1339 DRM_DEBUG_KMS("source rates: %s\n", str
);
1341 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1342 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1343 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1345 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1346 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1347 DRM_DEBUG_KMS("common rates: %s\n", str
);
1350 static int rate_to_index(int find
, const int *rates
)
1354 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1355 if (find
== rates
[i
])
1362 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1364 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1367 len
= intel_dp_common_rates(intel_dp
, rates
);
1368 if (WARN_ON(len
<= 0))
1371 return rates
[rate_to_index(0, rates
) - 1];
1374 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1376 return rate_to_index(rate
, intel_dp
->sink_rates
);
1380 intel_dp_compute_config(struct intel_encoder
*encoder
,
1381 struct intel_crtc_state
*pipe_config
)
1383 struct drm_device
*dev
= encoder
->base
.dev
;
1384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1385 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1386 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1387 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1388 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1389 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1390 int lane_count
, clock
;
1391 int min_lane_count
= 1;
1392 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1393 /* Conveniently, the link BW constants become indices with a shift...*/
1397 int link_avail
, link_clock
;
1398 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1401 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1403 /* No common link rates between source and sink */
1404 WARN_ON(common_len
<= 0);
1406 max_clock
= common_len
- 1;
1408 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1409 pipe_config
->has_pch_encoder
= true;
1411 pipe_config
->has_dp_encoder
= true;
1412 pipe_config
->has_drrs
= false;
1413 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1415 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1416 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1419 if (INTEL_INFO(dev
)->gen
>= 9) {
1421 ret
= skl_update_scaler_crtc(pipe_config
);
1426 if (!HAS_PCH_SPLIT(dev
))
1427 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1428 intel_connector
->panel
.fitting_mode
);
1430 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1431 intel_connector
->panel
.fitting_mode
);
1434 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1437 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1438 "max bw %d pixel clock %iKHz\n",
1439 max_lane_count
, common_rates
[max_clock
],
1440 adjusted_mode
->crtc_clock
);
1442 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1443 * bpc in between. */
1444 bpp
= pipe_config
->pipe_bpp
;
1445 if (is_edp(intel_dp
)) {
1447 /* Get bpp from vbt only for panels that dont have bpp in edid */
1448 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1449 (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
)) {
1450 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1451 dev_priv
->vbt
.edp_bpp
);
1452 bpp
= dev_priv
->vbt
.edp_bpp
;
1456 * Use the maximum clock and number of lanes the eDP panel
1457 * advertizes being capable of. The panels are generally
1458 * designed to support only a single clock and lane
1459 * configuration, and typically these values correspond to the
1460 * native resolution of the panel.
1462 min_lane_count
= max_lane_count
;
1463 min_clock
= max_clock
;
1466 for (; bpp
>= 6*3; bpp
-= 2*3) {
1467 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1470 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1471 for (lane_count
= min_lane_count
;
1472 lane_count
<= max_lane_count
;
1475 link_clock
= common_rates
[clock
];
1476 link_avail
= intel_dp_max_data_rate(link_clock
,
1479 if (mode_rate
<= link_avail
) {
1489 if (intel_dp
->color_range_auto
) {
1492 * CEA-861-E - 5.1 Default Encoding Parameters
1493 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1495 pipe_config
->limited_color_range
=
1496 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1498 pipe_config
->limited_color_range
=
1499 intel_dp
->limited_color_range
;
1502 pipe_config
->lane_count
= lane_count
;
1504 if (intel_dp
->num_sink_rates
) {
1505 intel_dp
->link_bw
= 0;
1506 intel_dp
->rate_select
=
1507 intel_dp_rate_select(intel_dp
, common_rates
[clock
]);
1510 drm_dp_link_rate_to_bw_code(common_rates
[clock
]);
1511 intel_dp
->rate_select
= 0;
1514 pipe_config
->pipe_bpp
= bpp
;
1515 pipe_config
->port_clock
= common_rates
[clock
];
1517 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1518 intel_dp
->link_bw
, pipe_config
->lane_count
,
1519 pipe_config
->port_clock
, bpp
);
1520 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1521 mode_rate
, link_avail
);
1523 intel_link_compute_m_n(bpp
, lane_count
,
1524 adjusted_mode
->crtc_clock
,
1525 pipe_config
->port_clock
,
1526 &pipe_config
->dp_m_n
);
1528 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1529 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1530 pipe_config
->has_drrs
= true;
1531 intel_link_compute_m_n(bpp
, lane_count
,
1532 intel_connector
->panel
.downclock_mode
->clock
,
1533 pipe_config
->port_clock
,
1534 &pipe_config
->dp_m2_n2
);
1537 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1538 skl_edp_set_pll_config(pipe_config
);
1539 else if (IS_BROXTON(dev
))
1540 /* handled in ddi */;
1541 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1542 hsw_dp_set_ddi_pll_sel(pipe_config
);
1544 intel_dp_set_clock(encoder
, pipe_config
);
1549 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1551 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1552 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1553 struct drm_device
*dev
= crtc
->base
.dev
;
1554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1557 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1558 crtc
->config
->port_clock
);
1559 dpa_ctl
= I915_READ(DP_A
);
1560 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1562 if (crtc
->config
->port_clock
== 162000) {
1563 /* For a long time we've carried around a ILK-DevA w/a for the
1564 * 160MHz clock. If we're really unlucky, it's still required.
1566 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1567 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1568 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1570 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1571 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1574 I915_WRITE(DP_A
, dpa_ctl
);
1580 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1582 struct drm_device
*dev
= encoder
->base
.dev
;
1583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1584 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1585 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1586 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1587 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1590 * There are four kinds of DP registers:
1597 * IBX PCH and CPU are the same for almost everything,
1598 * except that the CPU DP PLL is configured in this
1601 * CPT PCH is quite different, having many bits moved
1602 * to the TRANS_DP_CTL register instead. That
1603 * configuration happens (oddly) in ironlake_pch_enable
1606 /* Preserve the BIOS-computed detected bit. This is
1607 * supposed to be read-only.
1609 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1611 /* Handle DP bits in common between all three register formats */
1612 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1613 intel_dp
->DP
|= DP_PORT_WIDTH(crtc
->config
->lane_count
);
1615 if (crtc
->config
->has_audio
)
1616 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1618 /* Split out the IBX/CPU vs CPT settings */
1620 if (IS_GEN7(dev
) && port
== PORT_A
) {
1621 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1622 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1623 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1624 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1625 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1627 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1628 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1630 intel_dp
->DP
|= crtc
->pipe
<< 29;
1631 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1634 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1636 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1637 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1638 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1640 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1641 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1643 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1644 crtc
->config
->limited_color_range
)
1645 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1647 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1648 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1649 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1650 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1651 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1653 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1654 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1656 if (IS_CHERRYVIEW(dev
))
1657 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1658 else if (crtc
->pipe
== PIPE_B
)
1659 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1663 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1664 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1666 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1667 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1669 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1670 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1672 static void wait_panel_status(struct intel_dp
*intel_dp
,
1676 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1678 u32 pp_stat_reg
, pp_ctrl_reg
;
1680 lockdep_assert_held(&dev_priv
->pps_mutex
);
1682 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1683 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1685 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1687 I915_READ(pp_stat_reg
),
1688 I915_READ(pp_ctrl_reg
));
1690 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1691 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1692 I915_READ(pp_stat_reg
),
1693 I915_READ(pp_ctrl_reg
));
1696 DRM_DEBUG_KMS("Wait complete\n");
1699 static void wait_panel_on(struct intel_dp
*intel_dp
)
1701 DRM_DEBUG_KMS("Wait for panel power on\n");
1702 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1705 static void wait_panel_off(struct intel_dp
*intel_dp
)
1707 DRM_DEBUG_KMS("Wait for panel power off time\n");
1708 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1711 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1713 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1715 /* When we disable the VDD override bit last we have to do the manual
1717 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1718 intel_dp
->panel_power_cycle_delay
);
1720 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1723 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1725 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1726 intel_dp
->backlight_on_delay
);
1729 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1731 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1732 intel_dp
->backlight_off_delay
);
1735 /* Read the current pp_control value, unlocking the register if it
1739 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1741 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1745 lockdep_assert_held(&dev_priv
->pps_mutex
);
1747 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1748 if (!IS_BROXTON(dev
)) {
1749 control
&= ~PANEL_UNLOCK_MASK
;
1750 control
|= PANEL_UNLOCK_REGS
;
1756 * Must be paired with edp_panel_vdd_off().
1757 * Must hold pps_mutex around the whole on/off sequence.
1758 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1760 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1762 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1763 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1764 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 enum intel_display_power_domain power_domain
;
1768 u32 pp_stat_reg
, pp_ctrl_reg
;
1769 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1771 lockdep_assert_held(&dev_priv
->pps_mutex
);
1773 if (!is_edp(intel_dp
))
1776 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1777 intel_dp
->want_panel_vdd
= true;
1779 if (edp_have_panel_vdd(intel_dp
))
1780 return need_to_disable
;
1782 power_domain
= intel_display_port_power_domain(intel_encoder
);
1783 intel_display_power_get(dev_priv
, power_domain
);
1785 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1786 port_name(intel_dig_port
->port
));
1788 if (!edp_have_panel_power(intel_dp
))
1789 wait_panel_power_cycle(intel_dp
);
1791 pp
= ironlake_get_pp_control(intel_dp
);
1792 pp
|= EDP_FORCE_VDD
;
1794 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1795 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1797 I915_WRITE(pp_ctrl_reg
, pp
);
1798 POSTING_READ(pp_ctrl_reg
);
1799 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1800 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1802 * If the panel wasn't on, delay before accessing aux channel
1804 if (!edp_have_panel_power(intel_dp
)) {
1805 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1806 port_name(intel_dig_port
->port
));
1807 msleep(intel_dp
->panel_power_up_delay
);
1810 return need_to_disable
;
1814 * Must be paired with intel_edp_panel_vdd_off() or
1815 * intel_edp_panel_off().
1816 * Nested calls to these functions are not allowed since
1817 * we drop the lock. Caller must use some higher level
1818 * locking to prevent nested calls from other threads.
1820 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1824 if (!is_edp(intel_dp
))
1828 vdd
= edp_panel_vdd_on(intel_dp
);
1829 pps_unlock(intel_dp
);
1831 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1832 port_name(dp_to_dig_port(intel_dp
)->port
));
1835 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1837 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1839 struct intel_digital_port
*intel_dig_port
=
1840 dp_to_dig_port(intel_dp
);
1841 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1842 enum intel_display_power_domain power_domain
;
1844 u32 pp_stat_reg
, pp_ctrl_reg
;
1846 lockdep_assert_held(&dev_priv
->pps_mutex
);
1848 WARN_ON(intel_dp
->want_panel_vdd
);
1850 if (!edp_have_panel_vdd(intel_dp
))
1853 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1854 port_name(intel_dig_port
->port
));
1856 pp
= ironlake_get_pp_control(intel_dp
);
1857 pp
&= ~EDP_FORCE_VDD
;
1859 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1860 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1862 I915_WRITE(pp_ctrl_reg
, pp
);
1863 POSTING_READ(pp_ctrl_reg
);
1865 /* Make sure sequencer is idle before allowing subsequent activity */
1866 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1867 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1869 if ((pp
& POWER_TARGET_ON
) == 0)
1870 intel_dp
->last_power_cycle
= jiffies
;
1872 power_domain
= intel_display_port_power_domain(intel_encoder
);
1873 intel_display_power_put(dev_priv
, power_domain
);
1876 static void edp_panel_vdd_work(struct work_struct
*__work
)
1878 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1879 struct intel_dp
, panel_vdd_work
);
1882 if (!intel_dp
->want_panel_vdd
)
1883 edp_panel_vdd_off_sync(intel_dp
);
1884 pps_unlock(intel_dp
);
1887 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1889 unsigned long delay
;
1892 * Queue the timer to fire a long time from now (relative to the power
1893 * down delay) to keep the panel power up across a sequence of
1896 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1897 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1901 * Must be paired with edp_panel_vdd_on().
1902 * Must hold pps_mutex around the whole on/off sequence.
1903 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1905 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1907 struct drm_i915_private
*dev_priv
=
1908 intel_dp_to_dev(intel_dp
)->dev_private
;
1910 lockdep_assert_held(&dev_priv
->pps_mutex
);
1912 if (!is_edp(intel_dp
))
1915 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1916 port_name(dp_to_dig_port(intel_dp
)->port
));
1918 intel_dp
->want_panel_vdd
= false;
1921 edp_panel_vdd_off_sync(intel_dp
);
1923 edp_panel_vdd_schedule_off(intel_dp
);
1926 static void edp_panel_on(struct intel_dp
*intel_dp
)
1928 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1933 lockdep_assert_held(&dev_priv
->pps_mutex
);
1935 if (!is_edp(intel_dp
))
1938 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1939 port_name(dp_to_dig_port(intel_dp
)->port
));
1941 if (WARN(edp_have_panel_power(intel_dp
),
1942 "eDP port %c panel power already on\n",
1943 port_name(dp_to_dig_port(intel_dp
)->port
)))
1946 wait_panel_power_cycle(intel_dp
);
1948 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1949 pp
= ironlake_get_pp_control(intel_dp
);
1951 /* ILK workaround: disable reset around power sequence */
1952 pp
&= ~PANEL_POWER_RESET
;
1953 I915_WRITE(pp_ctrl_reg
, pp
);
1954 POSTING_READ(pp_ctrl_reg
);
1957 pp
|= POWER_TARGET_ON
;
1959 pp
|= PANEL_POWER_RESET
;
1961 I915_WRITE(pp_ctrl_reg
, pp
);
1962 POSTING_READ(pp_ctrl_reg
);
1964 wait_panel_on(intel_dp
);
1965 intel_dp
->last_power_on
= jiffies
;
1968 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1969 I915_WRITE(pp_ctrl_reg
, pp
);
1970 POSTING_READ(pp_ctrl_reg
);
1974 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1976 if (!is_edp(intel_dp
))
1980 edp_panel_on(intel_dp
);
1981 pps_unlock(intel_dp
);
1985 static void edp_panel_off(struct intel_dp
*intel_dp
)
1987 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1988 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1989 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1991 enum intel_display_power_domain power_domain
;
1995 lockdep_assert_held(&dev_priv
->pps_mutex
);
1997 if (!is_edp(intel_dp
))
2000 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2001 port_name(dp_to_dig_port(intel_dp
)->port
));
2003 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2004 port_name(dp_to_dig_port(intel_dp
)->port
));
2006 pp
= ironlake_get_pp_control(intel_dp
);
2007 /* We need to switch off panel power _and_ force vdd, for otherwise some
2008 * panels get very unhappy and cease to work. */
2009 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2012 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2014 intel_dp
->want_panel_vdd
= false;
2016 I915_WRITE(pp_ctrl_reg
, pp
);
2017 POSTING_READ(pp_ctrl_reg
);
2019 intel_dp
->last_power_cycle
= jiffies
;
2020 wait_panel_off(intel_dp
);
2022 /* We got a reference when we enabled the VDD. */
2023 power_domain
= intel_display_port_power_domain(intel_encoder
);
2024 intel_display_power_put(dev_priv
, power_domain
);
2027 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2029 if (!is_edp(intel_dp
))
2033 edp_panel_off(intel_dp
);
2034 pps_unlock(intel_dp
);
2037 /* Enable backlight in the panel power control. */
2038 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2040 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2041 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2047 * If we enable the backlight right away following a panel power
2048 * on, we may see slight flicker as the panel syncs with the eDP
2049 * link. So delay a bit to make sure the image is solid before
2050 * allowing it to appear.
2052 wait_backlight_on(intel_dp
);
2056 pp
= ironlake_get_pp_control(intel_dp
);
2057 pp
|= EDP_BLC_ENABLE
;
2059 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2061 I915_WRITE(pp_ctrl_reg
, pp
);
2062 POSTING_READ(pp_ctrl_reg
);
2064 pps_unlock(intel_dp
);
2067 /* Enable backlight PWM and backlight PP control. */
2068 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2070 if (!is_edp(intel_dp
))
2073 DRM_DEBUG_KMS("\n");
2075 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2076 _intel_edp_backlight_on(intel_dp
);
2079 /* Disable backlight in the panel power control. */
2080 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2082 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2087 if (!is_edp(intel_dp
))
2092 pp
= ironlake_get_pp_control(intel_dp
);
2093 pp
&= ~EDP_BLC_ENABLE
;
2095 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2097 I915_WRITE(pp_ctrl_reg
, pp
);
2098 POSTING_READ(pp_ctrl_reg
);
2100 pps_unlock(intel_dp
);
2102 intel_dp
->last_backlight_off
= jiffies
;
2103 edp_wait_backlight_off(intel_dp
);
2106 /* Disable backlight PP control and backlight PWM. */
2107 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2109 if (!is_edp(intel_dp
))
2112 DRM_DEBUG_KMS("\n");
2114 _intel_edp_backlight_off(intel_dp
);
2115 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2119 * Hook for controlling the panel power control backlight through the bl_power
2120 * sysfs attribute. Take care to handle multiple calls.
2122 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2125 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2129 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2130 pps_unlock(intel_dp
);
2132 if (is_enabled
== enable
)
2135 DRM_DEBUG_KMS("panel power control backlight %s\n",
2136 enable
? "enable" : "disable");
2139 _intel_edp_backlight_on(intel_dp
);
2141 _intel_edp_backlight_off(intel_dp
);
2144 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2147 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2148 struct drm_device
*dev
= crtc
->dev
;
2149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2152 assert_pipe_disabled(dev_priv
,
2153 to_intel_crtc(crtc
)->pipe
);
2155 DRM_DEBUG_KMS("\n");
2156 dpa_ctl
= I915_READ(DP_A
);
2157 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
2158 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2160 /* We don't adjust intel_dp->DP while tearing down the link, to
2161 * facilitate link retraining (e.g. after hotplug). Hence clear all
2162 * enable bits here to ensure that we don't enable too much. */
2163 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
2164 intel_dp
->DP
|= DP_PLL_ENABLE
;
2165 I915_WRITE(DP_A
, intel_dp
->DP
);
2170 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2172 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2173 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2174 struct drm_device
*dev
= crtc
->dev
;
2175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2178 assert_pipe_disabled(dev_priv
,
2179 to_intel_crtc(crtc
)->pipe
);
2181 dpa_ctl
= I915_READ(DP_A
);
2182 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
2183 "dp pll off, should be on\n");
2184 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2186 /* We can't rely on the value tracked for the DP register in
2187 * intel_dp->DP because link_down must not change that (otherwise link
2188 * re-training will fail. */
2189 dpa_ctl
&= ~DP_PLL_ENABLE
;
2190 I915_WRITE(DP_A
, dpa_ctl
);
2195 /* If the sink supports it, try to set the power state appropriately */
2196 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2200 /* Should have a valid DPCD by this point */
2201 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2204 if (mode
!= DRM_MODE_DPMS_ON
) {
2205 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2209 * When turning on, we need to retry for 1ms to give the sink
2212 for (i
= 0; i
< 3; i
++) {
2213 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2222 DRM_DEBUG_KMS("failed to %s sink power state\n",
2223 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2226 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2229 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2230 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2231 struct drm_device
*dev
= encoder
->base
.dev
;
2232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2233 enum intel_display_power_domain power_domain
;
2236 power_domain
= intel_display_port_power_domain(encoder
);
2237 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2240 tmp
= I915_READ(intel_dp
->output_reg
);
2242 if (!(tmp
& DP_PORT_EN
))
2245 if (IS_GEN7(dev
) && port
== PORT_A
) {
2246 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2247 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2250 for_each_pipe(dev_priv
, p
) {
2251 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2252 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2258 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2259 intel_dp
->output_reg
);
2260 } else if (IS_CHERRYVIEW(dev
)) {
2261 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2263 *pipe
= PORT_TO_PIPE(tmp
);
2269 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2270 struct intel_crtc_state
*pipe_config
)
2272 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2274 struct drm_device
*dev
= encoder
->base
.dev
;
2275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2276 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2277 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2280 tmp
= I915_READ(intel_dp
->output_reg
);
2282 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2284 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2285 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2287 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2288 flags
|= DRM_MODE_FLAG_PHSYNC
;
2290 flags
|= DRM_MODE_FLAG_NHSYNC
;
2292 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2293 flags
|= DRM_MODE_FLAG_PVSYNC
;
2295 flags
|= DRM_MODE_FLAG_NVSYNC
;
2297 if (tmp
& DP_SYNC_HS_HIGH
)
2298 flags
|= DRM_MODE_FLAG_PHSYNC
;
2300 flags
|= DRM_MODE_FLAG_NHSYNC
;
2302 if (tmp
& DP_SYNC_VS_HIGH
)
2303 flags
|= DRM_MODE_FLAG_PVSYNC
;
2305 flags
|= DRM_MODE_FLAG_NVSYNC
;
2308 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2310 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2311 tmp
& DP_COLOR_RANGE_16_235
)
2312 pipe_config
->limited_color_range
= true;
2314 pipe_config
->has_dp_encoder
= true;
2316 pipe_config
->lane_count
=
2317 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2319 intel_dp_get_m_n(crtc
, pipe_config
);
2321 if (port
== PORT_A
) {
2322 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2323 pipe_config
->port_clock
= 162000;
2325 pipe_config
->port_clock
= 270000;
2328 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2329 &pipe_config
->dp_m_n
);
2331 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2332 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2334 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2336 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2337 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2339 * This is a big fat ugly hack.
2341 * Some machines in UEFI boot mode provide us a VBT that has 18
2342 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2343 * unknown we fail to light up. Yet the same BIOS boots up with
2344 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2345 * max, not what it tells us to use.
2347 * Note: This will still be broken if the eDP panel is not lit
2348 * up by the BIOS, and thus we can't get the mode at module
2351 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2352 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2353 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2357 static void intel_disable_dp(struct intel_encoder
*encoder
)
2359 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2360 struct drm_device
*dev
= encoder
->base
.dev
;
2361 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2363 if (crtc
->config
->has_audio
)
2364 intel_audio_codec_disable(encoder
);
2366 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2367 intel_psr_disable(intel_dp
);
2369 /* Make sure the panel is off before trying to change the mode. But also
2370 * ensure that we have vdd while we switch off the panel. */
2371 intel_edp_panel_vdd_on(intel_dp
);
2372 intel_edp_backlight_off(intel_dp
);
2373 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2374 intel_edp_panel_off(intel_dp
);
2376 /* disable the port before the pipe on g4x */
2377 if (INTEL_INFO(dev
)->gen
< 5)
2378 intel_dp_link_down(intel_dp
);
2381 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2383 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2384 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2386 intel_dp_link_down(intel_dp
);
2388 ironlake_edp_pll_off(intel_dp
);
2391 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2393 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2395 intel_dp_link_down(intel_dp
);
2398 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2400 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2401 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2402 struct drm_device
*dev
= encoder
->base
.dev
;
2403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2404 struct intel_crtc
*intel_crtc
=
2405 to_intel_crtc(encoder
->base
.crtc
);
2406 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2407 enum pipe pipe
= intel_crtc
->pipe
;
2410 intel_dp_link_down(intel_dp
);
2412 mutex_lock(&dev_priv
->sb_lock
);
2414 /* Propagate soft reset to data lane reset */
2415 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2416 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2417 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2419 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2420 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2421 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2423 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2424 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2425 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2427 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2428 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2429 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2431 mutex_unlock(&dev_priv
->sb_lock
);
2435 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2437 uint8_t dp_train_pat
)
2439 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2440 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2442 enum port port
= intel_dig_port
->port
;
2445 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2447 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2448 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2450 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2452 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2453 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2454 case DP_TRAINING_PATTERN_DISABLE
:
2455 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2458 case DP_TRAINING_PATTERN_1
:
2459 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2461 case DP_TRAINING_PATTERN_2
:
2462 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2464 case DP_TRAINING_PATTERN_3
:
2465 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2468 I915_WRITE(DP_TP_CTL(port
), temp
);
2470 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2471 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2472 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2474 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2475 case DP_TRAINING_PATTERN_DISABLE
:
2476 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2478 case DP_TRAINING_PATTERN_1
:
2479 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2481 case DP_TRAINING_PATTERN_2
:
2482 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2484 case DP_TRAINING_PATTERN_3
:
2485 DRM_ERROR("DP training pattern 3 not supported\n");
2486 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2491 if (IS_CHERRYVIEW(dev
))
2492 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2494 *DP
&= ~DP_LINK_TRAIN_MASK
;
2496 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2497 case DP_TRAINING_PATTERN_DISABLE
:
2498 *DP
|= DP_LINK_TRAIN_OFF
;
2500 case DP_TRAINING_PATTERN_1
:
2501 *DP
|= DP_LINK_TRAIN_PAT_1
;
2503 case DP_TRAINING_PATTERN_2
:
2504 *DP
|= DP_LINK_TRAIN_PAT_2
;
2506 case DP_TRAINING_PATTERN_3
:
2507 if (IS_CHERRYVIEW(dev
)) {
2508 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2510 DRM_ERROR("DP training pattern 3 not supported\n");
2511 *DP
|= DP_LINK_TRAIN_PAT_2
;
2518 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2520 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2523 /* enable with pattern 1 (as per spec) */
2524 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2525 DP_TRAINING_PATTERN_1
);
2527 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2528 POSTING_READ(intel_dp
->output_reg
);
2531 * Magic for VLV/CHV. We _must_ first set up the register
2532 * without actually enabling the port, and then do another
2533 * write to enable the port. Otherwise link training will
2534 * fail when the power sequencer is freshly used for this port.
2536 intel_dp
->DP
|= DP_PORT_EN
;
2538 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2539 POSTING_READ(intel_dp
->output_reg
);
2542 static void intel_enable_dp(struct intel_encoder
*encoder
)
2544 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2545 struct drm_device
*dev
= encoder
->base
.dev
;
2546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2547 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2548 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2549 unsigned int lane_mask
= 0x0;
2551 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2556 if (IS_VALLEYVIEW(dev
))
2557 vlv_init_panel_power_sequencer(intel_dp
);
2559 intel_dp_enable_port(intel_dp
);
2561 edp_panel_vdd_on(intel_dp
);
2562 edp_panel_on(intel_dp
);
2563 edp_panel_vdd_off(intel_dp
, true);
2565 pps_unlock(intel_dp
);
2567 if (IS_VALLEYVIEW(dev
))
2568 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2571 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2572 intel_dp_start_link_train(intel_dp
);
2573 intel_dp_complete_link_train(intel_dp
);
2574 intel_dp_stop_link_train(intel_dp
);
2576 if (crtc
->config
->has_audio
) {
2577 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2578 pipe_name(crtc
->pipe
));
2579 intel_audio_codec_enable(encoder
);
2583 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2585 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2587 intel_enable_dp(encoder
);
2588 intel_edp_backlight_on(intel_dp
);
2591 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2593 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2595 intel_edp_backlight_on(intel_dp
);
2596 intel_psr_enable(intel_dp
);
2599 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2601 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2602 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2604 intel_dp_prepare(encoder
);
2606 /* Only ilk+ has port A */
2607 if (dport
->port
== PORT_A
) {
2608 ironlake_set_pll_cpu_edp(intel_dp
);
2609 ironlake_edp_pll_on(intel_dp
);
2613 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2615 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2616 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2617 enum pipe pipe
= intel_dp
->pps_pipe
;
2618 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2620 edp_panel_vdd_off_sync(intel_dp
);
2623 * VLV seems to get confused when multiple power seqeuencers
2624 * have the same port selected (even if only one has power/vdd
2625 * enabled). The failure manifests as vlv_wait_port_ready() failing
2626 * CHV on the other hand doesn't seem to mind having the same port
2627 * selected in multiple power seqeuencers, but let's clear the
2628 * port select always when logically disconnecting a power sequencer
2631 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2632 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2633 I915_WRITE(pp_on_reg
, 0);
2634 POSTING_READ(pp_on_reg
);
2636 intel_dp
->pps_pipe
= INVALID_PIPE
;
2639 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2643 struct intel_encoder
*encoder
;
2645 lockdep_assert_held(&dev_priv
->pps_mutex
);
2647 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2650 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2652 struct intel_dp
*intel_dp
;
2655 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2658 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2659 port
= dp_to_dig_port(intel_dp
)->port
;
2661 if (intel_dp
->pps_pipe
!= pipe
)
2664 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2665 pipe_name(pipe
), port_name(port
));
2667 WARN(encoder
->base
.crtc
,
2668 "stealing pipe %c power sequencer from active eDP port %c\n",
2669 pipe_name(pipe
), port_name(port
));
2671 /* make sure vdd is off before we steal it */
2672 vlv_detach_power_sequencer(intel_dp
);
2676 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2678 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2679 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2680 struct drm_device
*dev
= encoder
->base
.dev
;
2681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2682 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2684 lockdep_assert_held(&dev_priv
->pps_mutex
);
2686 if (!is_edp(intel_dp
))
2689 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2693 * If another power sequencer was being used on this
2694 * port previously make sure to turn off vdd there while
2695 * we still have control of it.
2697 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2698 vlv_detach_power_sequencer(intel_dp
);
2701 * We may be stealing the power
2702 * sequencer from another port.
2704 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2706 /* now it's all ours */
2707 intel_dp
->pps_pipe
= crtc
->pipe
;
2709 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2710 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2712 /* init power sequencer on this pipe and port */
2713 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2714 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2717 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2719 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2720 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2721 struct drm_device
*dev
= encoder
->base
.dev
;
2722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2723 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2724 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2725 int pipe
= intel_crtc
->pipe
;
2728 mutex_lock(&dev_priv
->sb_lock
);
2730 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2737 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2738 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2739 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2741 mutex_unlock(&dev_priv
->sb_lock
);
2743 intel_enable_dp(encoder
);
2746 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2748 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2749 struct drm_device
*dev
= encoder
->base
.dev
;
2750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2751 struct intel_crtc
*intel_crtc
=
2752 to_intel_crtc(encoder
->base
.crtc
);
2753 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2754 int pipe
= intel_crtc
->pipe
;
2756 intel_dp_prepare(encoder
);
2758 /* Program Tx lane resets to default */
2759 mutex_lock(&dev_priv
->sb_lock
);
2760 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2761 DPIO_PCS_TX_LANE2_RESET
|
2762 DPIO_PCS_TX_LANE1_RESET
);
2763 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2764 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2765 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2766 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2767 DPIO_PCS_CLK_SOFT_RESET
);
2769 /* Fix up inter-pair skew failure */
2770 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2771 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2772 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2773 mutex_unlock(&dev_priv
->sb_lock
);
2776 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2778 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2779 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2780 struct drm_device
*dev
= encoder
->base
.dev
;
2781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2782 struct intel_crtc
*intel_crtc
=
2783 to_intel_crtc(encoder
->base
.crtc
);
2784 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2785 int pipe
= intel_crtc
->pipe
;
2786 int data
, i
, stagger
;
2789 mutex_lock(&dev_priv
->sb_lock
);
2791 /* allow hardware to manage TX FIFO reset source */
2792 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2793 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2794 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2796 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2797 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2798 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2800 /* Deassert soft data lane reset*/
2801 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2802 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2803 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2805 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2806 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2807 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2809 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2810 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2811 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2813 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2814 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2815 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2817 /* Program Tx lane latency optimal setting*/
2818 for (i
= 0; i
< 4; i
++) {
2819 /* Set the upar bit */
2820 data
= (i
== 1) ? 0x0 : 0x1;
2821 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2822 data
<< DPIO_UPAR_SHIFT
);
2825 /* Data lane stagger programming */
2826 if (intel_crtc
->config
->port_clock
> 270000)
2828 else if (intel_crtc
->config
->port_clock
> 135000)
2830 else if (intel_crtc
->config
->port_clock
> 67500)
2832 else if (intel_crtc
->config
->port_clock
> 33750)
2837 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2838 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2839 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2841 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2842 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2843 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2845 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
2846 DPIO_LANESTAGGER_STRAP(stagger
) |
2847 DPIO_LANESTAGGER_STRAP_OVRD
|
2848 DPIO_TX1_STAGGER_MASK(0x1f) |
2849 DPIO_TX1_STAGGER_MULT(6) |
2850 DPIO_TX2_STAGGER_MULT(0));
2852 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
2853 DPIO_LANESTAGGER_STRAP(stagger
) |
2854 DPIO_LANESTAGGER_STRAP_OVRD
|
2855 DPIO_TX1_STAGGER_MASK(0x1f) |
2856 DPIO_TX1_STAGGER_MULT(7) |
2857 DPIO_TX2_STAGGER_MULT(5));
2859 mutex_unlock(&dev_priv
->sb_lock
);
2861 intel_enable_dp(encoder
);
2864 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2866 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2867 struct drm_device
*dev
= encoder
->base
.dev
;
2868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2869 struct intel_crtc
*intel_crtc
=
2870 to_intel_crtc(encoder
->base
.crtc
);
2871 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2872 enum pipe pipe
= intel_crtc
->pipe
;
2875 intel_dp_prepare(encoder
);
2877 mutex_lock(&dev_priv
->sb_lock
);
2879 /* program left/right clock distribution */
2880 if (pipe
!= PIPE_B
) {
2881 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2882 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2884 val
|= CHV_BUFLEFTENA1_FORCE
;
2886 val
|= CHV_BUFRIGHTENA1_FORCE
;
2887 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2889 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2890 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2892 val
|= CHV_BUFLEFTENA2_FORCE
;
2894 val
|= CHV_BUFRIGHTENA2_FORCE
;
2895 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2898 /* program clock channel usage */
2899 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2900 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2902 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2904 val
|= CHV_PCS_USEDCLKCHANNEL
;
2905 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2907 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2908 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2910 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2912 val
|= CHV_PCS_USEDCLKCHANNEL
;
2913 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2916 * This a a bit weird since generally CL
2917 * matches the pipe, but here we need to
2918 * pick the CL based on the port.
2920 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2922 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2924 val
|= CHV_CMN_USEDCLKCHANNEL
;
2925 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2927 mutex_unlock(&dev_priv
->sb_lock
);
2931 * Native read with retry for link status and receiver capability reads for
2932 * cases where the sink may still be asleep.
2934 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2935 * supposed to retry 3 times per the spec.
2938 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2939 void *buffer
, size_t size
)
2945 * Sometime we just get the same incorrect byte repeated
2946 * over the entire buffer. Doing just one throw away read
2947 * initially seems to "solve" it.
2949 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2951 for (i
= 0; i
< 3; i
++) {
2952 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2962 * Fetch AUX CH registers 0x202 - 0x207 which contain
2963 * link status information
2966 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2968 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2971 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2974 /* These are source-specific values. */
2976 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2978 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2980 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2982 if (IS_BROXTON(dev
))
2983 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2984 else if (INTEL_INFO(dev
)->gen
>= 9) {
2985 if (dev_priv
->edp_low_vswing
&& port
== PORT_A
)
2986 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2987 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2988 } else if (IS_VALLEYVIEW(dev
))
2989 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2990 else if (IS_GEN7(dev
) && port
== PORT_A
)
2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2992 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2993 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2995 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2999 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3001 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3002 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3004 if (INTEL_INFO(dev
)->gen
>= 9) {
3005 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3009 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3011 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3013 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3015 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3017 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3018 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3020 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3022 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3027 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3029 } else if (IS_VALLEYVIEW(dev
)) {
3030 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3039 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3041 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3042 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3049 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3052 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3054 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3056 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3061 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3066 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3068 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3070 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3071 struct intel_crtc
*intel_crtc
=
3072 to_intel_crtc(dport
->base
.base
.crtc
);
3073 unsigned long demph_reg_value
, preemph_reg_value
,
3074 uniqtranscale_reg_value
;
3075 uint8_t train_set
= intel_dp
->train_set
[0];
3076 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3077 int pipe
= intel_crtc
->pipe
;
3079 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3080 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3081 preemph_reg_value
= 0x0004000;
3082 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3084 demph_reg_value
= 0x2B405555;
3085 uniqtranscale_reg_value
= 0x552AB83A;
3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3088 demph_reg_value
= 0x2B404040;
3089 uniqtranscale_reg_value
= 0x5548B83A;
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3092 demph_reg_value
= 0x2B245555;
3093 uniqtranscale_reg_value
= 0x5560B83A;
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3096 demph_reg_value
= 0x2B405555;
3097 uniqtranscale_reg_value
= 0x5598DA3A;
3103 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3104 preemph_reg_value
= 0x0002000;
3105 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3107 demph_reg_value
= 0x2B404040;
3108 uniqtranscale_reg_value
= 0x5552B83A;
3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3111 demph_reg_value
= 0x2B404848;
3112 uniqtranscale_reg_value
= 0x5580B83A;
3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3115 demph_reg_value
= 0x2B404040;
3116 uniqtranscale_reg_value
= 0x55ADDA3A;
3122 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3123 preemph_reg_value
= 0x0000000;
3124 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3126 demph_reg_value
= 0x2B305555;
3127 uniqtranscale_reg_value
= 0x5570B83A;
3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3130 demph_reg_value
= 0x2B2B4040;
3131 uniqtranscale_reg_value
= 0x55ADDA3A;
3137 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3138 preemph_reg_value
= 0x0006000;
3139 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3140 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3141 demph_reg_value
= 0x1B405555;
3142 uniqtranscale_reg_value
= 0x55ADDA3A;
3152 mutex_lock(&dev_priv
->sb_lock
);
3153 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3154 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3155 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3156 uniqtranscale_reg_value
);
3157 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3158 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3159 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3160 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3161 mutex_unlock(&dev_priv
->sb_lock
);
3166 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3168 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3170 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3171 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3172 u32 deemph_reg_value
, margin_reg_value
, val
;
3173 uint8_t train_set
= intel_dp
->train_set
[0];
3174 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3175 enum pipe pipe
= intel_crtc
->pipe
;
3178 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3179 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3180 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3182 deemph_reg_value
= 128;
3183 margin_reg_value
= 52;
3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3186 deemph_reg_value
= 128;
3187 margin_reg_value
= 77;
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3190 deemph_reg_value
= 128;
3191 margin_reg_value
= 102;
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3194 deemph_reg_value
= 128;
3195 margin_reg_value
= 154;
3196 /* FIXME extra to set for 1200 */
3202 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3203 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3205 deemph_reg_value
= 85;
3206 margin_reg_value
= 78;
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3209 deemph_reg_value
= 85;
3210 margin_reg_value
= 116;
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3213 deemph_reg_value
= 85;
3214 margin_reg_value
= 154;
3220 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3221 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3223 deemph_reg_value
= 64;
3224 margin_reg_value
= 104;
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3227 deemph_reg_value
= 64;
3228 margin_reg_value
= 154;
3234 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3235 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3237 deemph_reg_value
= 43;
3238 margin_reg_value
= 154;
3248 mutex_lock(&dev_priv
->sb_lock
);
3250 /* Clear calc init */
3251 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3252 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3253 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3254 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3255 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3257 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3258 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3259 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3260 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3261 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3263 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3264 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3265 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3266 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3268 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3269 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3270 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3271 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3273 /* Program swing deemph */
3274 for (i
= 0; i
< 4; i
++) {
3275 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3276 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3277 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3278 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3281 /* Program swing margin */
3282 for (i
= 0; i
< 4; i
++) {
3283 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3284 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3285 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3286 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3289 /* Disable unique transition scale */
3290 for (i
= 0; i
< 4; i
++) {
3291 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3292 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3293 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3296 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3297 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3298 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3299 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3302 * The document said it needs to set bit 27 for ch0 and bit 26
3303 * for ch1. Might be a typo in the doc.
3304 * For now, for this unique transition scale selection, set bit
3305 * 27 for ch0 and ch1.
3307 for (i
= 0; i
< 4; i
++) {
3308 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3309 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3310 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3313 for (i
= 0; i
< 4; i
++) {
3314 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3315 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3316 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3317 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3321 /* Start swing calculation */
3322 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3323 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3324 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3326 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3327 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3328 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3331 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3332 val
|= DPIO_LRC_BYPASS
;
3333 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3335 mutex_unlock(&dev_priv
->sb_lock
);
3341 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3342 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3344 struct intel_crtc
*crtc
=
3345 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
3349 uint8_t voltage_max
;
3350 uint8_t preemph_max
;
3352 for (lane
= 0; lane
< crtc
->config
->lane_count
; lane
++) {
3353 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3354 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3362 voltage_max
= intel_dp_voltage_max(intel_dp
);
3363 if (v
>= voltage_max
)
3364 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3366 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3367 if (p
>= preemph_max
)
3368 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3370 for (lane
= 0; lane
< 4; lane
++)
3371 intel_dp
->train_set
[lane
] = v
| p
;
3375 gen4_signal_levels(uint8_t train_set
)
3377 uint32_t signal_levels
= 0;
3379 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3382 signal_levels
|= DP_VOLTAGE_0_4
;
3384 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3385 signal_levels
|= DP_VOLTAGE_0_6
;
3387 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3388 signal_levels
|= DP_VOLTAGE_0_8
;
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3391 signal_levels
|= DP_VOLTAGE_1_2
;
3394 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3395 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3397 signal_levels
|= DP_PRE_EMPHASIS_0
;
3399 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3400 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3402 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3403 signal_levels
|= DP_PRE_EMPHASIS_6
;
3405 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3406 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3409 return signal_levels
;
3412 /* Gen6's DP voltage swing and pre-emphasis control */
3414 gen6_edp_signal_levels(uint8_t train_set
)
3416 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3417 DP_TRAIN_PRE_EMPHASIS_MASK
);
3418 switch (signal_levels
) {
3419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3421 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3423 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3424 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3426 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3427 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3428 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3429 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3431 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3432 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3434 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3435 "0x%x\n", signal_levels
);
3436 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3440 /* Gen7's DP voltage swing and pre-emphasis control */
3442 gen7_edp_signal_levels(uint8_t train_set
)
3444 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3445 DP_TRAIN_PRE_EMPHASIS_MASK
);
3446 switch (signal_levels
) {
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3448 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3449 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3450 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3452 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3454 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3455 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3457 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3460 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3462 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3465 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3466 "0x%x\n", signal_levels
);
3467 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3471 /* Properly updates "DP" with the correct signal levels. */
3473 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3475 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3476 enum port port
= intel_dig_port
->port
;
3477 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3478 uint32_t signal_levels
, mask
= 0;
3479 uint8_t train_set
= intel_dp
->train_set
[0];
3482 signal_levels
= ddi_signal_levels(intel_dp
);
3484 if (IS_BROXTON(dev
))
3487 mask
= DDI_BUF_EMP_MASK
;
3488 } else if (IS_CHERRYVIEW(dev
)) {
3489 signal_levels
= chv_signal_levels(intel_dp
);
3490 } else if (IS_VALLEYVIEW(dev
)) {
3491 signal_levels
= vlv_signal_levels(intel_dp
);
3492 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3493 signal_levels
= gen7_edp_signal_levels(train_set
);
3494 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3495 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3496 signal_levels
= gen6_edp_signal_levels(train_set
);
3497 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3499 signal_levels
= gen4_signal_levels(train_set
);
3500 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3504 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3506 DRM_DEBUG_KMS("Using vswing level %d\n",
3507 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3508 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3509 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3510 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3512 *DP
= (*DP
& ~mask
) | signal_levels
;
3516 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3518 uint8_t dp_train_pat
)
3520 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3521 struct drm_i915_private
*dev_priv
=
3522 to_i915(intel_dig_port
->base
.base
.dev
);
3523 struct intel_crtc
*crtc
=
3524 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3525 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3528 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3530 I915_WRITE(intel_dp
->output_reg
, *DP
);
3531 POSTING_READ(intel_dp
->output_reg
);
3533 buf
[0] = dp_train_pat
;
3534 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3535 DP_TRAINING_PATTERN_DISABLE
) {
3536 /* don't write DP_TRAINING_LANEx_SET on disable */
3539 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3540 memcpy(buf
+ 1, intel_dp
->train_set
, crtc
->config
->lane_count
);
3541 len
= crtc
->config
->lane_count
+ 1;
3544 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3551 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3552 uint8_t dp_train_pat
)
3554 if (!intel_dp
->train_set_valid
)
3555 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3556 intel_dp_set_signal_levels(intel_dp
, DP
);
3557 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3561 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3562 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3564 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3565 struct drm_i915_private
*dev_priv
=
3566 to_i915(intel_dig_port
->base
.base
.dev
);
3567 struct intel_crtc
*crtc
=
3568 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3571 intel_get_adjust_train(intel_dp
, link_status
);
3572 intel_dp_set_signal_levels(intel_dp
, DP
);
3574 I915_WRITE(intel_dp
->output_reg
, *DP
);
3575 POSTING_READ(intel_dp
->output_reg
);
3577 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3578 intel_dp
->train_set
, crtc
->config
->lane_count
);
3580 return ret
== crtc
->config
->lane_count
;
3583 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3585 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3586 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3588 enum port port
= intel_dig_port
->port
;
3594 val
= I915_READ(DP_TP_CTL(port
));
3595 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3596 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3597 I915_WRITE(DP_TP_CTL(port
), val
);
3600 * On PORT_A we can have only eDP in SST mode. There the only reason
3601 * we need to set idle transmission mode is to work around a HW issue
3602 * where we enable the pipe while not in idle link-training mode.
3603 * In this case there is requirement to wait for a minimum number of
3604 * idle patterns to be sent.
3609 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3611 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3614 /* Enable corresponding port and start training pattern 1 */
3616 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3618 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3619 struct intel_crtc
*crtc
=
3620 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
3621 struct drm_device
*dev
= encoder
->dev
;
3624 int voltage_tries
, loop_tries
;
3625 uint32_t DP
= intel_dp
->DP
;
3626 uint8_t link_config
[2];
3629 intel_ddi_prepare_link_retrain(encoder
);
3631 /* Write the link configuration data */
3632 link_config
[0] = intel_dp
->link_bw
;
3633 link_config
[1] = crtc
->config
->lane_count
;
3634 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3635 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3636 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3637 if (intel_dp
->num_sink_rates
)
3638 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_RATE_SET
,
3639 &intel_dp
->rate_select
, 1);
3642 link_config
[1] = DP_SET_ANSI_8B10B
;
3643 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3647 /* clock recovery */
3648 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3649 DP_TRAINING_PATTERN_1
|
3650 DP_LINK_SCRAMBLING_DISABLE
)) {
3651 DRM_ERROR("failed to enable link training\n");
3659 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3661 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3662 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3663 DRM_ERROR("failed to get link status\n");
3667 if (drm_dp_clock_recovery_ok(link_status
, crtc
->config
->lane_count
)) {
3668 DRM_DEBUG_KMS("clock recovery OK\n");
3673 * if we used previously trained voltage and pre-emphasis values
3674 * and we don't get clock recovery, reset link training values
3676 if (intel_dp
->train_set_valid
) {
3677 DRM_DEBUG_KMS("clock recovery not ok, reset");
3678 /* clear the flag as we are not reusing train set */
3679 intel_dp
->train_set_valid
= false;
3680 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3681 DP_TRAINING_PATTERN_1
|
3682 DP_LINK_SCRAMBLING_DISABLE
)) {
3683 DRM_ERROR("failed to enable link training\n");
3689 /* Check to see if we've tried the max voltage */
3690 for (i
= 0; i
< crtc
->config
->lane_count
; i
++)
3691 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3693 if (i
== crtc
->config
->lane_count
) {
3695 if (loop_tries
== 5) {
3696 DRM_ERROR("too many full retries, give up\n");
3699 intel_dp_reset_link_train(intel_dp
, &DP
,
3700 DP_TRAINING_PATTERN_1
|
3701 DP_LINK_SCRAMBLING_DISABLE
);
3706 /* Check to see if we've tried the same voltage 5 times */
3707 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3709 if (voltage_tries
== 5) {
3710 DRM_ERROR("too many voltage retries, give up\n");
3715 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3717 /* Update training set as requested by target */
3718 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3719 DRM_ERROR("failed to update link training\n");
3728 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3730 struct intel_crtc
*crtc
=
3731 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
3732 bool channel_eq
= false;
3733 int tries
, cr_tries
;
3734 uint32_t DP
= intel_dp
->DP
;
3735 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3737 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3738 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3739 training_pattern
= DP_TRAINING_PATTERN_3
;
3741 /* channel equalization */
3742 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3744 DP_LINK_SCRAMBLING_DISABLE
)) {
3745 DRM_ERROR("failed to start channel equalization\n");
3753 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3756 DRM_ERROR("failed to train DP, aborting\n");
3760 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3761 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3762 DRM_ERROR("failed to get link status\n");
3766 /* Make sure clock is still ok */
3767 if (!drm_dp_clock_recovery_ok(link_status
,
3768 crtc
->config
->lane_count
)) {
3769 intel_dp
->train_set_valid
= false;
3770 intel_dp_start_link_train(intel_dp
);
3771 intel_dp_set_link_train(intel_dp
, &DP
,
3773 DP_LINK_SCRAMBLING_DISABLE
);
3778 if (drm_dp_channel_eq_ok(link_status
,
3779 crtc
->config
->lane_count
)) {
3784 /* Try 5 times, then try clock recovery if that fails */
3786 intel_dp
->train_set_valid
= false;
3787 intel_dp_start_link_train(intel_dp
);
3788 intel_dp_set_link_train(intel_dp
, &DP
,
3790 DP_LINK_SCRAMBLING_DISABLE
);
3796 /* Update training set as requested by target */
3797 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3798 DRM_ERROR("failed to update link training\n");
3804 intel_dp_set_idle_link_train(intel_dp
);
3809 intel_dp
->train_set_valid
= true;
3810 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3814 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3816 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3817 DP_TRAINING_PATTERN_DISABLE
);
3821 intel_dp_link_down(struct intel_dp
*intel_dp
)
3823 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3824 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3825 enum port port
= intel_dig_port
->port
;
3826 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3828 uint32_t DP
= intel_dp
->DP
;
3830 if (WARN_ON(HAS_DDI(dev
)))
3833 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3836 DRM_DEBUG_KMS("\n");
3838 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3839 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3840 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3841 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3843 if (IS_CHERRYVIEW(dev
))
3844 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3846 DP
&= ~DP_LINK_TRAIN_MASK
;
3847 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3849 I915_WRITE(intel_dp
->output_reg
, DP
);
3850 POSTING_READ(intel_dp
->output_reg
);
3852 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3853 I915_WRITE(intel_dp
->output_reg
, DP
);
3854 POSTING_READ(intel_dp
->output_reg
);
3857 * HW workaround for IBX, we need to move the port
3858 * to transcoder A after disabling it to allow the
3859 * matching HDMI port to be enabled on transcoder A.
3861 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3862 /* always enable with pattern 1 (as per spec) */
3863 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3864 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3865 I915_WRITE(intel_dp
->output_reg
, DP
);
3866 POSTING_READ(intel_dp
->output_reg
);
3869 I915_WRITE(intel_dp
->output_reg
, DP
);
3870 POSTING_READ(intel_dp
->output_reg
);
3873 msleep(intel_dp
->panel_power_down_delay
);
3877 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3879 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3880 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3884 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3885 sizeof(intel_dp
->dpcd
)) < 0)
3886 return false; /* aux transfer failed */
3888 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3890 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3891 return false; /* DPCD not present */
3893 /* Check if the panel supports PSR */
3894 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3895 if (is_edp(intel_dp
)) {
3896 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3898 sizeof(intel_dp
->psr_dpcd
));
3899 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3900 dev_priv
->psr
.sink_support
= true;
3901 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3904 if (INTEL_INFO(dev
)->gen
>= 9 &&
3905 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3906 uint8_t frame_sync_cap
;
3908 dev_priv
->psr
.sink_support
= true;
3909 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3910 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3911 &frame_sync_cap
, 1);
3912 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3913 /* PSR2 needs frame sync as well */
3914 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3915 DRM_DEBUG_KMS("PSR2 %s on sink",
3916 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3920 /* Training Pattern 3 support, both source and sink */
3921 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3922 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3923 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3924 intel_dp
->use_tps3
= true;
3925 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3927 intel_dp
->use_tps3
= false;
3929 /* Intermediate frequency support */
3930 if (is_edp(intel_dp
) &&
3931 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3932 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3933 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3934 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3937 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3938 DP_SUPPORTED_LINK_RATES
,
3940 sizeof(sink_rates
));
3942 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3943 int val
= le16_to_cpu(sink_rates
[i
]);
3948 /* Value read is in kHz while drm clock is saved in deca-kHz */
3949 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3951 intel_dp
->num_sink_rates
= i
;
3954 intel_dp_print_rates(intel_dp
);
3956 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3957 DP_DWN_STRM_PORT_PRESENT
))
3958 return true; /* native DP sink */
3960 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3961 return true; /* no per-port downstream info */
3963 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3964 intel_dp
->downstream_ports
,
3965 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3966 return false; /* downstream port status fetch failed */
3972 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3976 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3979 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3980 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3981 buf
[0], buf
[1], buf
[2]);
3983 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3984 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3985 buf
[0], buf
[1], buf
[2]);
3989 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3993 if (!intel_dp
->can_mst
)
3996 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3999 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
4000 if (buf
[0] & DP_MST_CAP
) {
4001 DRM_DEBUG_KMS("Sink is MST capable\n");
4002 intel_dp
->is_mst
= true;
4004 DRM_DEBUG_KMS("Sink is not MST capable\n");
4005 intel_dp
->is_mst
= false;
4009 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4010 return intel_dp
->is_mst
;
4013 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
4015 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4016 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
4020 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
4021 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4026 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4027 buf
& ~DP_TEST_SINK_START
) < 0) {
4028 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4033 intel_dp
->sink_crc
.started
= false;
4035 hsw_enable_ips(intel_crtc
);
4039 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
4041 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4042 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
4046 if (intel_dp
->sink_crc
.started
) {
4047 ret
= intel_dp_sink_crc_stop(intel_dp
);
4052 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
4055 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
4058 intel_dp
->sink_crc
.last_count
= buf
& DP_TEST_COUNT_MASK
;
4060 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4063 hsw_disable_ips(intel_crtc
);
4065 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4066 buf
| DP_TEST_SINK_START
) < 0) {
4067 hsw_enable_ips(intel_crtc
);
4071 intel_dp
->sink_crc
.started
= true;
4075 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
4077 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4078 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
4079 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
4085 ret
= intel_dp_sink_crc_start(intel_dp
);
4090 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4092 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4093 DP_TEST_SINK_MISC
, &buf
) < 0) {
4097 count
= buf
& DP_TEST_COUNT_MASK
;
4100 * Count might be reset during the loop. In this case
4101 * last known count needs to be reset as well.
4104 intel_dp
->sink_crc
.last_count
= 0;
4106 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4111 old_equal_new
= (count
== intel_dp
->sink_crc
.last_count
&&
4112 !memcmp(intel_dp
->sink_crc
.last_crc
, crc
,
4115 } while (--attempts
&& (count
== 0 || old_equal_new
));
4117 intel_dp
->sink_crc
.last_count
= buf
& DP_TEST_COUNT_MASK
;
4118 memcpy(intel_dp
->sink_crc
.last_crc
, crc
, 6 * sizeof(u8
));
4120 if (attempts
== 0) {
4121 if (old_equal_new
) {
4122 DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
4124 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4131 intel_dp_sink_crc_stop(intel_dp
);
4136 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4138 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4139 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4140 sink_irq_vector
, 1) == 1;
4144 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4148 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4150 sink_irq_vector
, 14);
4157 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4159 uint8_t test_result
= DP_TEST_ACK
;
4163 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4165 uint8_t test_result
= DP_TEST_NAK
;
4169 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4171 uint8_t test_result
= DP_TEST_NAK
;
4172 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4173 struct drm_connector
*connector
= &intel_connector
->base
;
4175 if (intel_connector
->detect_edid
== NULL
||
4176 connector
->edid_corrupt
||
4177 intel_dp
->aux
.i2c_defer_count
> 6) {
4178 /* Check EDID read for NACKs, DEFERs and corruption
4179 * (DP CTS 1.2 Core r1.1)
4180 * 4.2.2.4 : Failed EDID read, I2C_NAK
4181 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4182 * 4.2.2.6 : EDID corruption detected
4183 * Use failsafe mode for all cases
4185 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4186 intel_dp
->aux
.i2c_defer_count
> 0)
4187 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4188 intel_dp
->aux
.i2c_nack_count
,
4189 intel_dp
->aux
.i2c_defer_count
);
4190 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
4192 struct edid
*block
= intel_connector
->detect_edid
;
4194 /* We have to write the checksum
4195 * of the last block read
4197 block
+= intel_connector
->detect_edid
->extensions
;
4199 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4200 DP_TEST_EDID_CHECKSUM
,
4203 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4205 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4206 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
4209 /* Set test active flag here so userspace doesn't interrupt things */
4210 intel_dp
->compliance_test_active
= 1;
4215 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4217 uint8_t test_result
= DP_TEST_NAK
;
4221 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4223 uint8_t response
= DP_TEST_NAK
;
4227 intel_dp
->compliance_test_active
= 0;
4228 intel_dp
->compliance_test_type
= 0;
4229 intel_dp
->compliance_test_data
= 0;
4231 intel_dp
->aux
.i2c_nack_count
= 0;
4232 intel_dp
->aux
.i2c_defer_count
= 0;
4234 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4236 DRM_DEBUG_KMS("Could not read test request from sink\n");
4241 case DP_TEST_LINK_TRAINING
:
4242 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4243 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4244 response
= intel_dp_autotest_link_training(intel_dp
);
4246 case DP_TEST_LINK_VIDEO_PATTERN
:
4247 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4248 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4249 response
= intel_dp_autotest_video_pattern(intel_dp
);
4251 case DP_TEST_LINK_EDID_READ
:
4252 DRM_DEBUG_KMS("EDID test requested\n");
4253 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4254 response
= intel_dp_autotest_edid(intel_dp
);
4256 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4257 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4258 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4259 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4262 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4267 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4271 DRM_DEBUG_KMS("Could not write test response to sink\n");
4275 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4277 struct intel_crtc
*crtc
=
4278 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
4281 if (intel_dp
->is_mst
) {
4286 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4290 /* check link status - esi[10] = 0x200c */
4291 if (intel_dp
->active_mst_links
&&
4292 !drm_dp_channel_eq_ok(&esi
[10], crtc
->config
->lane_count
)) {
4293 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4294 intel_dp_start_link_train(intel_dp
);
4295 intel_dp_complete_link_train(intel_dp
);
4296 intel_dp_stop_link_train(intel_dp
);
4299 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4300 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4303 for (retry
= 0; retry
< 3; retry
++) {
4305 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4306 DP_SINK_COUNT_ESI
+1,
4313 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4315 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4323 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4324 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4325 intel_dp
->is_mst
= false;
4326 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4327 /* send a hotplug event */
4328 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4335 * According to DP spec
4338 * 2. Configure link according to Receiver Capabilities
4339 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4340 * 4. Check link status on receipt of hot-plug interrupt
4343 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4345 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4346 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4347 struct intel_crtc
*crtc
=
4348 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
4350 u8 link_status
[DP_LINK_STATUS_SIZE
];
4352 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4354 if (!intel_encoder
->base
.crtc
)
4357 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4360 /* Try to read receiver status if the link appears to be up */
4361 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4365 /* Now read the DPCD to see if it's actually running */
4366 if (!intel_dp_get_dpcd(intel_dp
)) {
4370 /* Try to read the source of the interrupt */
4371 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4372 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4373 /* Clear interrupt source */
4374 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4375 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4378 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4379 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4380 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4381 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4384 if (!drm_dp_channel_eq_ok(link_status
, crtc
->config
->lane_count
)) {
4385 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4386 intel_encoder
->base
.name
);
4387 intel_dp_start_link_train(intel_dp
);
4388 intel_dp_complete_link_train(intel_dp
);
4389 intel_dp_stop_link_train(intel_dp
);
4393 /* XXX this is probably wrong for multiple downstream ports */
4394 static enum drm_connector_status
4395 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4397 uint8_t *dpcd
= intel_dp
->dpcd
;
4400 if (!intel_dp_get_dpcd(intel_dp
))
4401 return connector_status_disconnected
;
4403 /* if there's no downstream port, we're done */
4404 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4405 return connector_status_connected
;
4407 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4408 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4409 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4412 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4414 return connector_status_unknown
;
4416 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4417 : connector_status_disconnected
;
4420 /* If no HPD, poke DDC gently */
4421 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4422 return connector_status_connected
;
4424 /* Well we tried, say unknown for unreliable port types */
4425 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4426 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4427 if (type
== DP_DS_PORT_TYPE_VGA
||
4428 type
== DP_DS_PORT_TYPE_NON_EDID
)
4429 return connector_status_unknown
;
4431 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4432 DP_DWN_STRM_PORT_TYPE_MASK
;
4433 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4434 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4435 return connector_status_unknown
;
4438 /* Anything else is out of spec, warn and ignore */
4439 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4440 return connector_status_disconnected
;
4443 static enum drm_connector_status
4444 edp_detect(struct intel_dp
*intel_dp
)
4446 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4447 enum drm_connector_status status
;
4449 status
= intel_panel_detect(dev
);
4450 if (status
== connector_status_unknown
)
4451 status
= connector_status_connected
;
4456 static enum drm_connector_status
4457 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4459 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4461 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4463 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4464 return connector_status_disconnected
;
4466 return intel_dp_detect_dpcd(intel_dp
);
4469 static int g4x_digital_port_connected(struct drm_device
*dev
,
4470 struct intel_digital_port
*intel_dig_port
)
4472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4475 if (IS_VALLEYVIEW(dev
)) {
4476 switch (intel_dig_port
->port
) {
4478 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4481 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4484 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4490 switch (intel_dig_port
->port
) {
4492 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4495 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4498 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4505 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4510 static enum drm_connector_status
4511 g4x_dp_detect(struct intel_dp
*intel_dp
)
4513 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4514 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4517 /* Can't disconnect eDP, but you can close the lid... */
4518 if (is_edp(intel_dp
)) {
4519 enum drm_connector_status status
;
4521 status
= intel_panel_detect(dev
);
4522 if (status
== connector_status_unknown
)
4523 status
= connector_status_connected
;
4527 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4529 return connector_status_unknown
;
4531 return connector_status_disconnected
;
4533 return intel_dp_detect_dpcd(intel_dp
);
4536 static struct edid
*
4537 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4539 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4541 /* use cached edid if we have one */
4542 if (intel_connector
->edid
) {
4544 if (IS_ERR(intel_connector
->edid
))
4547 return drm_edid_duplicate(intel_connector
->edid
);
4549 return drm_get_edid(&intel_connector
->base
,
4550 &intel_dp
->aux
.ddc
);
4554 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4556 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4559 edid
= intel_dp_get_edid(intel_dp
);
4560 intel_connector
->detect_edid
= edid
;
4562 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4563 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4565 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4569 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4571 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4573 kfree(intel_connector
->detect_edid
);
4574 intel_connector
->detect_edid
= NULL
;
4576 intel_dp
->has_audio
= false;
4579 static enum intel_display_power_domain
4580 intel_dp_power_get(struct intel_dp
*dp
)
4582 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4583 enum intel_display_power_domain power_domain
;
4585 power_domain
= intel_display_port_power_domain(encoder
);
4586 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4588 return power_domain
;
4592 intel_dp_power_put(struct intel_dp
*dp
,
4593 enum intel_display_power_domain power_domain
)
4595 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4596 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4599 static enum drm_connector_status
4600 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4602 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4603 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4604 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4605 struct drm_device
*dev
= connector
->dev
;
4606 enum drm_connector_status status
;
4607 enum intel_display_power_domain power_domain
;
4611 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4612 connector
->base
.id
, connector
->name
);
4613 intel_dp_unset_edid(intel_dp
);
4615 if (intel_dp
->is_mst
) {
4616 /* MST devices are disconnected from a monitor POV */
4617 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4618 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4619 return connector_status_disconnected
;
4622 power_domain
= intel_dp_power_get(intel_dp
);
4624 /* Can't disconnect eDP, but you can close the lid... */
4625 if (is_edp(intel_dp
))
4626 status
= edp_detect(intel_dp
);
4627 else if (HAS_PCH_SPLIT(dev
))
4628 status
= ironlake_dp_detect(intel_dp
);
4630 status
= g4x_dp_detect(intel_dp
);
4631 if (status
!= connector_status_connected
)
4634 intel_dp_probe_oui(intel_dp
);
4636 ret
= intel_dp_probe_mst(intel_dp
);
4638 /* if we are in MST mode then this connector
4639 won't appear connected or have anything with EDID on it */
4640 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4641 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4642 status
= connector_status_disconnected
;
4646 intel_dp_set_edid(intel_dp
);
4648 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4649 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4650 status
= connector_status_connected
;
4652 /* Try to read the source of the interrupt */
4653 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4654 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4655 /* Clear interrupt source */
4656 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4657 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4660 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4661 intel_dp_handle_test_request(intel_dp
);
4662 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4663 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4667 intel_dp_power_put(intel_dp
, power_domain
);
4672 intel_dp_force(struct drm_connector
*connector
)
4674 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4675 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4676 enum intel_display_power_domain power_domain
;
4678 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4679 connector
->base
.id
, connector
->name
);
4680 intel_dp_unset_edid(intel_dp
);
4682 if (connector
->status
!= connector_status_connected
)
4685 power_domain
= intel_dp_power_get(intel_dp
);
4687 intel_dp_set_edid(intel_dp
);
4689 intel_dp_power_put(intel_dp
, power_domain
);
4691 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4692 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4695 static int intel_dp_get_modes(struct drm_connector
*connector
)
4697 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4700 edid
= intel_connector
->detect_edid
;
4702 int ret
= intel_connector_update_modes(connector
, edid
);
4707 /* if eDP has no EDID, fall back to fixed mode */
4708 if (is_edp(intel_attached_dp(connector
)) &&
4709 intel_connector
->panel
.fixed_mode
) {
4710 struct drm_display_mode
*mode
;
4712 mode
= drm_mode_duplicate(connector
->dev
,
4713 intel_connector
->panel
.fixed_mode
);
4715 drm_mode_probed_add(connector
, mode
);
4724 intel_dp_detect_audio(struct drm_connector
*connector
)
4726 bool has_audio
= false;
4729 edid
= to_intel_connector(connector
)->detect_edid
;
4731 has_audio
= drm_detect_monitor_audio(edid
);
4737 intel_dp_set_property(struct drm_connector
*connector
,
4738 struct drm_property
*property
,
4741 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4742 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4743 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4744 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4747 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4751 if (property
== dev_priv
->force_audio_property
) {
4755 if (i
== intel_dp
->force_audio
)
4758 intel_dp
->force_audio
= i
;
4760 if (i
== HDMI_AUDIO_AUTO
)
4761 has_audio
= intel_dp_detect_audio(connector
);
4763 has_audio
= (i
== HDMI_AUDIO_ON
);
4765 if (has_audio
== intel_dp
->has_audio
)
4768 intel_dp
->has_audio
= has_audio
;
4772 if (property
== dev_priv
->broadcast_rgb_property
) {
4773 bool old_auto
= intel_dp
->color_range_auto
;
4774 bool old_range
= intel_dp
->limited_color_range
;
4777 case INTEL_BROADCAST_RGB_AUTO
:
4778 intel_dp
->color_range_auto
= true;
4780 case INTEL_BROADCAST_RGB_FULL
:
4781 intel_dp
->color_range_auto
= false;
4782 intel_dp
->limited_color_range
= false;
4784 case INTEL_BROADCAST_RGB_LIMITED
:
4785 intel_dp
->color_range_auto
= false;
4786 intel_dp
->limited_color_range
= true;
4792 if (old_auto
== intel_dp
->color_range_auto
&&
4793 old_range
== intel_dp
->limited_color_range
)
4799 if (is_edp(intel_dp
) &&
4800 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4801 if (val
== DRM_MODE_SCALE_NONE
) {
4802 DRM_DEBUG_KMS("no scaling not supported\n");
4806 if (intel_connector
->panel
.fitting_mode
== val
) {
4807 /* the eDP scaling property is not changed */
4810 intel_connector
->panel
.fitting_mode
= val
;
4818 if (intel_encoder
->base
.crtc
)
4819 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4825 intel_dp_connector_destroy(struct drm_connector
*connector
)
4827 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4829 kfree(intel_connector
->detect_edid
);
4831 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4832 kfree(intel_connector
->edid
);
4834 /* Can't call is_edp() since the encoder may have been destroyed
4836 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4837 intel_panel_fini(&intel_connector
->panel
);
4839 drm_connector_cleanup(connector
);
4843 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4845 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4846 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4848 drm_dp_aux_unregister(&intel_dp
->aux
);
4849 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4850 if (is_edp(intel_dp
)) {
4851 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4853 * vdd might still be enabled do to the delayed vdd off.
4854 * Make sure vdd is actually turned off here.
4857 edp_panel_vdd_off_sync(intel_dp
);
4858 pps_unlock(intel_dp
);
4860 if (intel_dp
->edp_notifier
.notifier_call
) {
4861 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4862 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4865 drm_encoder_cleanup(encoder
);
4866 kfree(intel_dig_port
);
4869 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4871 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4873 if (!is_edp(intel_dp
))
4877 * vdd might still be enabled do to the delayed vdd off.
4878 * Make sure vdd is actually turned off here.
4880 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4882 edp_panel_vdd_off_sync(intel_dp
);
4883 pps_unlock(intel_dp
);
4886 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4888 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4889 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4891 enum intel_display_power_domain power_domain
;
4893 lockdep_assert_held(&dev_priv
->pps_mutex
);
4895 if (!edp_have_panel_vdd(intel_dp
))
4899 * The VDD bit needs a power domain reference, so if the bit is
4900 * already enabled when we boot or resume, grab this reference and
4901 * schedule a vdd off, so we don't hold on to the reference
4904 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4905 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4906 intel_display_power_get(dev_priv
, power_domain
);
4908 edp_panel_vdd_schedule_off(intel_dp
);
4911 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4913 struct intel_dp
*intel_dp
;
4915 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4918 intel_dp
= enc_to_intel_dp(encoder
);
4923 * Read out the current power sequencer assignment,
4924 * in case the BIOS did something with it.
4926 if (IS_VALLEYVIEW(encoder
->dev
))
4927 vlv_initial_power_sequencer_setup(intel_dp
);
4929 intel_edp_panel_vdd_sanitize(intel_dp
);
4931 pps_unlock(intel_dp
);
4934 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4935 .dpms
= drm_atomic_helper_connector_dpms
,
4936 .detect
= intel_dp_detect
,
4937 .force
= intel_dp_force
,
4938 .fill_modes
= drm_helper_probe_single_connector_modes
,
4939 .set_property
= intel_dp_set_property
,
4940 .atomic_get_property
= intel_connector_atomic_get_property
,
4941 .destroy
= intel_dp_connector_destroy
,
4942 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4943 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4946 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4947 .get_modes
= intel_dp_get_modes
,
4948 .mode_valid
= intel_dp_mode_valid
,
4949 .best_encoder
= intel_best_encoder
,
4952 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4953 .reset
= intel_dp_encoder_reset
,
4954 .destroy
= intel_dp_encoder_destroy
,
4958 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4960 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4961 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4962 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4964 enum intel_display_power_domain power_domain
;
4965 enum irqreturn ret
= IRQ_NONE
;
4967 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4968 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4970 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4972 * vdd off can generate a long pulse on eDP which
4973 * would require vdd on to handle it, and thus we
4974 * would end up in an endless cycle of
4975 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4977 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4978 port_name(intel_dig_port
->port
));
4982 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4983 port_name(intel_dig_port
->port
),
4984 long_hpd
? "long" : "short");
4986 power_domain
= intel_display_port_power_domain(intel_encoder
);
4987 intel_display_power_get(dev_priv
, power_domain
);
4990 /* indicate that we need to restart link training */
4991 intel_dp
->train_set_valid
= false;
4993 if (HAS_PCH_SPLIT(dev
)) {
4994 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4997 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
5001 if (!intel_dp_get_dpcd(intel_dp
)) {
5005 intel_dp_probe_oui(intel_dp
);
5007 if (!intel_dp_probe_mst(intel_dp
))
5011 if (intel_dp
->is_mst
) {
5012 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
5016 if (!intel_dp
->is_mst
) {
5018 * we'll check the link status via the normal hot plug path later -
5019 * but for short hpds we should check it now
5021 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
5022 intel_dp_check_link_status(intel_dp
);
5023 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
5031 /* if we were in MST mode, and device is not there get out of MST mode */
5032 if (intel_dp
->is_mst
) {
5033 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5034 intel_dp
->is_mst
= false;
5035 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
5038 intel_display_power_put(dev_priv
, power_domain
);
5043 /* Return which DP Port should be selected for Transcoder DP control */
5045 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
5047 struct drm_device
*dev
= crtc
->dev
;
5048 struct intel_encoder
*intel_encoder
;
5049 struct intel_dp
*intel_dp
;
5051 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5052 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5054 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
5055 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
5056 return intel_dp
->output_reg
;
5062 /* check the VBT to see whether the eDP is on DP-D port */
5063 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
5065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5066 union child_device_config
*p_child
;
5068 static const short port_mapping
[] = {
5069 [PORT_B
] = PORT_IDPB
,
5070 [PORT_C
] = PORT_IDPC
,
5071 [PORT_D
] = PORT_IDPD
,
5077 if (!dev_priv
->vbt
.child_dev_num
)
5080 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
5081 p_child
= dev_priv
->vbt
.child_dev
+ i
;
5083 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
5084 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
5085 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
5092 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5094 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5096 intel_attach_force_audio_property(connector
);
5097 intel_attach_broadcast_rgb_property(connector
);
5098 intel_dp
->color_range_auto
= true;
5100 if (is_edp(intel_dp
)) {
5101 drm_mode_create_scaling_mode_property(connector
->dev
);
5102 drm_object_attach_property(
5104 connector
->dev
->mode_config
.scaling_mode_property
,
5105 DRM_MODE_SCALE_ASPECT
);
5106 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5110 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5112 intel_dp
->last_power_cycle
= jiffies
;
5113 intel_dp
->last_power_on
= jiffies
;
5114 intel_dp
->last_backlight_off
= jiffies
;
5118 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5119 struct intel_dp
*intel_dp
)
5121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5122 struct edp_power_seq cur
, vbt
, spec
,
5123 *final
= &intel_dp
->pps_delays
;
5124 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5125 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
= 0;
5127 lockdep_assert_held(&dev_priv
->pps_mutex
);
5129 /* already initialized? */
5130 if (final
->t11_t12
!= 0)
5133 if (IS_BROXTON(dev
)) {
5135 * TODO: BXT has 2 sets of PPS registers.
5136 * Correct Register for Broxton need to be identified
5137 * using VBT. hardcoding for now
5139 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5140 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5141 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5142 } else if (HAS_PCH_SPLIT(dev
)) {
5143 pp_ctrl_reg
= PCH_PP_CONTROL
;
5144 pp_on_reg
= PCH_PP_ON_DELAYS
;
5145 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5146 pp_div_reg
= PCH_PP_DIVISOR
;
5148 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5150 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
5151 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5152 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5153 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5156 /* Workaround: Need to write PP_CONTROL with the unlock key as
5157 * the very first thing. */
5158 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5160 pp_on
= I915_READ(pp_on_reg
);
5161 pp_off
= I915_READ(pp_off_reg
);
5162 if (!IS_BROXTON(dev
)) {
5163 I915_WRITE(pp_ctrl_reg
, pp_ctl
);
5164 pp_div
= I915_READ(pp_div_reg
);
5167 /* Pull timing values out of registers */
5168 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5169 PANEL_POWER_UP_DELAY_SHIFT
;
5171 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5172 PANEL_LIGHT_ON_DELAY_SHIFT
;
5174 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5175 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5177 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5178 PANEL_POWER_DOWN_DELAY_SHIFT
;
5180 if (IS_BROXTON(dev
)) {
5181 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5182 BXT_POWER_CYCLE_DELAY_SHIFT
;
5184 cur
.t11_t12
= (tmp
- 1) * 1000;
5188 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5189 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5192 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5193 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5195 vbt
= dev_priv
->vbt
.edp_pps
;
5197 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5198 * our hw here, which are all in 100usec. */
5199 spec
.t1_t3
= 210 * 10;
5200 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5201 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5202 spec
.t10
= 500 * 10;
5203 /* This one is special and actually in units of 100ms, but zero
5204 * based in the hw (so we need to add 100 ms). But the sw vbt
5205 * table multiplies it with 1000 to make it in units of 100usec,
5207 spec
.t11_t12
= (510 + 100) * 10;
5209 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5210 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5212 /* Use the max of the register settings and vbt. If both are
5213 * unset, fall back to the spec limits. */
5214 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5216 max(cur.field, vbt.field))
5217 assign_final(t1_t3
);
5221 assign_final(t11_t12
);
5224 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5225 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5226 intel_dp
->backlight_on_delay
= get_delay(t8
);
5227 intel_dp
->backlight_off_delay
= get_delay(t9
);
5228 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5229 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5232 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5233 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5234 intel_dp
->panel_power_cycle_delay
);
5236 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5237 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5241 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5242 struct intel_dp
*intel_dp
)
5244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5245 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5246 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5247 int pp_on_reg
, pp_off_reg
, pp_div_reg
= 0, pp_ctrl_reg
;
5248 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5249 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5251 lockdep_assert_held(&dev_priv
->pps_mutex
);
5253 if (IS_BROXTON(dev
)) {
5255 * TODO: BXT has 2 sets of PPS registers.
5256 * Correct Register for Broxton need to be identified
5257 * using VBT. hardcoding for now
5259 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5260 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5261 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5263 } else if (HAS_PCH_SPLIT(dev
)) {
5264 pp_on_reg
= PCH_PP_ON_DELAYS
;
5265 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5266 pp_div_reg
= PCH_PP_DIVISOR
;
5268 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5270 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5271 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5272 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5276 * And finally store the new values in the power sequencer. The
5277 * backlight delays are set to 1 because we do manual waits on them. For
5278 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5279 * we'll end up waiting for the backlight off delay twice: once when we
5280 * do the manual sleep, and once when we disable the panel and wait for
5281 * the PP_STATUS bit to become zero.
5283 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5284 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5285 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5286 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5287 /* Compute the divisor for the pp clock, simply match the Bspec
5289 if (IS_BROXTON(dev
)) {
5290 pp_div
= I915_READ(pp_ctrl_reg
);
5291 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5292 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5293 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5295 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5296 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5297 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5300 /* Haswell doesn't have any port selection bits for the panel
5301 * power sequencer any more. */
5302 if (IS_VALLEYVIEW(dev
)) {
5303 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5304 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5306 port_sel
= PANEL_PORT_SELECT_DPA
;
5308 port_sel
= PANEL_PORT_SELECT_DPD
;
5313 I915_WRITE(pp_on_reg
, pp_on
);
5314 I915_WRITE(pp_off_reg
, pp_off
);
5315 if (IS_BROXTON(dev
))
5316 I915_WRITE(pp_ctrl_reg
, pp_div
);
5318 I915_WRITE(pp_div_reg
, pp_div
);
5320 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5321 I915_READ(pp_on_reg
),
5322 I915_READ(pp_off_reg
),
5324 (I915_READ(pp_ctrl_reg
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5325 I915_READ(pp_div_reg
));
5329 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5331 * @refresh_rate: RR to be programmed
5333 * This function gets called when refresh rate (RR) has to be changed from
5334 * one frequency to another. Switches can be between high and low RR
5335 * supported by the panel or to any other RR based on media playback (in
5336 * this case, RR value needs to be passed from user space).
5338 * The caller of this function needs to take a lock on dev_priv->drrs.
5340 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5343 struct intel_encoder
*encoder
;
5344 struct intel_digital_port
*dig_port
= NULL
;
5345 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5346 struct intel_crtc_state
*config
= NULL
;
5347 struct intel_crtc
*intel_crtc
= NULL
;
5349 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5351 if (refresh_rate
<= 0) {
5352 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5356 if (intel_dp
== NULL
) {
5357 DRM_DEBUG_KMS("DRRS not supported.\n");
5362 * FIXME: This needs proper synchronization with psr state for some
5363 * platforms that cannot have PSR and DRRS enabled at the same time.
5366 dig_port
= dp_to_dig_port(intel_dp
);
5367 encoder
= &dig_port
->base
;
5368 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5371 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5375 config
= intel_crtc
->config
;
5377 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5378 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5382 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5384 index
= DRRS_LOW_RR
;
5386 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5388 "DRRS requested for previously set RR...ignoring\n");
5392 if (!intel_crtc
->active
) {
5393 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5397 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5400 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5403 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5407 DRM_ERROR("Unsupported refreshrate type\n");
5409 } else if (INTEL_INFO(dev
)->gen
> 6) {
5410 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5411 val
= I915_READ(reg
);
5413 if (index
> DRRS_HIGH_RR
) {
5414 if (IS_VALLEYVIEW(dev
))
5415 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5417 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5419 if (IS_VALLEYVIEW(dev
))
5420 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5422 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5424 I915_WRITE(reg
, val
);
5427 dev_priv
->drrs
.refresh_rate_type
= index
;
5429 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5433 * intel_edp_drrs_enable - init drrs struct if supported
5434 * @intel_dp: DP struct
5436 * Initializes frontbuffer_bits and drrs.dp
5438 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5440 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5442 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5443 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5444 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5446 if (!intel_crtc
->config
->has_drrs
) {
5447 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5451 mutex_lock(&dev_priv
->drrs
.mutex
);
5452 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5453 DRM_ERROR("DRRS already enabled\n");
5457 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5459 dev_priv
->drrs
.dp
= intel_dp
;
5462 mutex_unlock(&dev_priv
->drrs
.mutex
);
5466 * intel_edp_drrs_disable - Disable DRRS
5467 * @intel_dp: DP struct
5470 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5472 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5474 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5475 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5476 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5478 if (!intel_crtc
->config
->has_drrs
)
5481 mutex_lock(&dev_priv
->drrs
.mutex
);
5482 if (!dev_priv
->drrs
.dp
) {
5483 mutex_unlock(&dev_priv
->drrs
.mutex
);
5487 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5488 intel_dp_set_drrs_state(dev_priv
->dev
,
5489 intel_dp
->attached_connector
->panel
.
5490 fixed_mode
->vrefresh
);
5492 dev_priv
->drrs
.dp
= NULL
;
5493 mutex_unlock(&dev_priv
->drrs
.mutex
);
5495 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5498 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5500 struct drm_i915_private
*dev_priv
=
5501 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5502 struct intel_dp
*intel_dp
;
5504 mutex_lock(&dev_priv
->drrs
.mutex
);
5506 intel_dp
= dev_priv
->drrs
.dp
;
5512 * The delayed work can race with an invalidate hence we need to
5516 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5519 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5520 intel_dp_set_drrs_state(dev_priv
->dev
,
5521 intel_dp
->attached_connector
->panel
.
5522 downclock_mode
->vrefresh
);
5525 mutex_unlock(&dev_priv
->drrs
.mutex
);
5529 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5531 * @frontbuffer_bits: frontbuffer plane tracking bits
5533 * This function gets called everytime rendering on the given planes start.
5534 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5536 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5538 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5539 unsigned frontbuffer_bits
)
5541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5542 struct drm_crtc
*crtc
;
5545 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5548 cancel_delayed_work(&dev_priv
->drrs
.work
);
5550 mutex_lock(&dev_priv
->drrs
.mutex
);
5551 if (!dev_priv
->drrs
.dp
) {
5552 mutex_unlock(&dev_priv
->drrs
.mutex
);
5556 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5557 pipe
= to_intel_crtc(crtc
)->pipe
;
5559 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5560 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5562 /* invalidate means busy screen hence upclock */
5563 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5564 intel_dp_set_drrs_state(dev_priv
->dev
,
5565 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5566 fixed_mode
->vrefresh
);
5568 mutex_unlock(&dev_priv
->drrs
.mutex
);
5572 * intel_edp_drrs_flush - Restart Idleness DRRS
5574 * @frontbuffer_bits: frontbuffer plane tracking bits
5576 * This function gets called every time rendering on the given planes has
5577 * completed or flip on a crtc is completed. So DRRS should be upclocked
5578 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5579 * if no other planes are dirty.
5581 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5583 void intel_edp_drrs_flush(struct drm_device
*dev
,
5584 unsigned frontbuffer_bits
)
5586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5587 struct drm_crtc
*crtc
;
5590 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5593 cancel_delayed_work(&dev_priv
->drrs
.work
);
5595 mutex_lock(&dev_priv
->drrs
.mutex
);
5596 if (!dev_priv
->drrs
.dp
) {
5597 mutex_unlock(&dev_priv
->drrs
.mutex
);
5601 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5602 pipe
= to_intel_crtc(crtc
)->pipe
;
5604 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5605 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5607 /* flush means busy screen hence upclock */
5608 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5609 intel_dp_set_drrs_state(dev_priv
->dev
,
5610 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5611 fixed_mode
->vrefresh
);
5614 * flush also means no more activity hence schedule downclock, if all
5615 * other fbs are quiescent too
5617 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5618 schedule_delayed_work(&dev_priv
->drrs
.work
,
5619 msecs_to_jiffies(1000));
5620 mutex_unlock(&dev_priv
->drrs
.mutex
);
5624 * DOC: Display Refresh Rate Switching (DRRS)
5626 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5627 * which enables swtching between low and high refresh rates,
5628 * dynamically, based on the usage scenario. This feature is applicable
5629 * for internal panels.
5631 * Indication that the panel supports DRRS is given by the panel EDID, which
5632 * would list multiple refresh rates for one resolution.
5634 * DRRS is of 2 types - static and seamless.
5635 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5636 * (may appear as a blink on screen) and is used in dock-undock scenario.
5637 * Seamless DRRS involves changing RR without any visual effect to the user
5638 * and can be used during normal system usage. This is done by programming
5639 * certain registers.
5641 * Support for static/seamless DRRS may be indicated in the VBT based on
5642 * inputs from the panel spec.
5644 * DRRS saves power by switching to low RR based on usage scenarios.
5647 * The implementation is based on frontbuffer tracking implementation.
5648 * When there is a disturbance on the screen triggered by user activity or a
5649 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5650 * When there is no movement on screen, after a timeout of 1 second, a switch
5651 * to low RR is made.
5652 * For integration with frontbuffer tracking code,
5653 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5655 * DRRS can be further extended to support other internal panels and also
5656 * the scenario of video playback wherein RR is set based on the rate
5657 * requested by userspace.
5661 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5662 * @intel_connector: eDP connector
5663 * @fixed_mode: preferred mode of panel
5665 * This function is called only once at driver load to initialize basic
5669 * Downclock mode if panel supports it, else return NULL.
5670 * DRRS support is determined by the presence of downclock mode (apart
5671 * from VBT setting).
5673 static struct drm_display_mode
*
5674 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5675 struct drm_display_mode
*fixed_mode
)
5677 struct drm_connector
*connector
= &intel_connector
->base
;
5678 struct drm_device
*dev
= connector
->dev
;
5679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5680 struct drm_display_mode
*downclock_mode
= NULL
;
5682 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5683 mutex_init(&dev_priv
->drrs
.mutex
);
5685 if (INTEL_INFO(dev
)->gen
<= 6) {
5686 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5690 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5691 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5695 downclock_mode
= intel_find_panel_downclock
5696 (dev
, fixed_mode
, connector
);
5698 if (!downclock_mode
) {
5699 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5703 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5705 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5706 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5707 return downclock_mode
;
5710 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5711 struct intel_connector
*intel_connector
)
5713 struct drm_connector
*connector
= &intel_connector
->base
;
5714 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5715 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5716 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5718 struct drm_display_mode
*fixed_mode
= NULL
;
5719 struct drm_display_mode
*downclock_mode
= NULL
;
5721 struct drm_display_mode
*scan
;
5723 enum pipe pipe
= INVALID_PIPE
;
5725 if (!is_edp(intel_dp
))
5729 intel_edp_panel_vdd_sanitize(intel_dp
);
5730 pps_unlock(intel_dp
);
5732 /* Cache DPCD and EDID for edp. */
5733 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5736 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5737 dev_priv
->no_aux_handshake
=
5738 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5739 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5741 /* if this fails, presume the device is a ghost */
5742 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5746 /* We now know it's not a ghost, init power sequence regs. */
5748 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5749 pps_unlock(intel_dp
);
5751 mutex_lock(&dev
->mode_config
.mutex
);
5752 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5754 if (drm_add_edid_modes(connector
, edid
)) {
5755 drm_mode_connector_update_edid_property(connector
,
5757 drm_edid_to_eld(connector
, edid
);
5760 edid
= ERR_PTR(-EINVAL
);
5763 edid
= ERR_PTR(-ENOENT
);
5765 intel_connector
->edid
= edid
;
5767 /* prefer fixed mode from EDID if available */
5768 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5769 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5770 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5771 downclock_mode
= intel_dp_drrs_init(
5772 intel_connector
, fixed_mode
);
5777 /* fallback to VBT if available for eDP */
5778 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5779 fixed_mode
= drm_mode_duplicate(dev
,
5780 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5782 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5784 mutex_unlock(&dev
->mode_config
.mutex
);
5786 if (IS_VALLEYVIEW(dev
)) {
5787 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5788 register_reboot_notifier(&intel_dp
->edp_notifier
);
5791 * Figure out the current pipe for the initial backlight setup.
5792 * If the current pipe isn't valid, try the PPS pipe, and if that
5793 * fails just assume pipe A.
5795 if (IS_CHERRYVIEW(dev
))
5796 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5798 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5800 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5801 pipe
= intel_dp
->pps_pipe
;
5803 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5806 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5810 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5811 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5812 intel_panel_setup_backlight(connector
, pipe
);
5818 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5819 struct intel_connector
*intel_connector
)
5821 struct drm_connector
*connector
= &intel_connector
->base
;
5822 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5823 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5824 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5826 enum port port
= intel_dig_port
->port
;
5829 intel_dp
->pps_pipe
= INVALID_PIPE
;
5831 /* intel_dp vfuncs */
5832 if (INTEL_INFO(dev
)->gen
>= 9)
5833 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5834 else if (IS_VALLEYVIEW(dev
))
5835 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5836 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5837 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5838 else if (HAS_PCH_SPLIT(dev
))
5839 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5841 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5843 if (INTEL_INFO(dev
)->gen
>= 9)
5844 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5846 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5848 /* Preserve the current hw state. */
5849 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5850 intel_dp
->attached_connector
= intel_connector
;
5852 if (intel_dp_is_edp(dev
, port
))
5853 type
= DRM_MODE_CONNECTOR_eDP
;
5855 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5858 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5859 * for DP the encoder type can be set by the caller to
5860 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5862 if (type
== DRM_MODE_CONNECTOR_eDP
)
5863 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5865 /* eDP only on port B and/or C on vlv/chv */
5866 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5867 port
!= PORT_B
&& port
!= PORT_C
))
5870 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5871 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5874 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5875 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5877 connector
->interlace_allowed
= true;
5878 connector
->doublescan_allowed
= 0;
5880 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5881 edp_panel_vdd_work
);
5883 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5884 drm_connector_register(connector
);
5887 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5889 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5890 intel_connector
->unregister
= intel_dp_connector_unregister
;
5892 /* Set up the hotplug pin. */
5895 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5898 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5899 if (IS_BROXTON(dev_priv
) && (INTEL_REVID(dev
) < BXT_REVID_B0
))
5900 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5903 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5906 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5912 if (is_edp(intel_dp
)) {
5914 intel_dp_init_panel_power_timestamps(intel_dp
);
5915 if (IS_VALLEYVIEW(dev
))
5916 vlv_initial_power_sequencer_setup(intel_dp
);
5918 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5919 pps_unlock(intel_dp
);
5922 intel_dp_aux_init(intel_dp
, intel_connector
);
5924 /* init MST on ports that can support it */
5925 if (HAS_DP_MST(dev
) &&
5926 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5927 intel_dp_mst_encoder_init(intel_dig_port
,
5928 intel_connector
->base
.base
.id
);
5930 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5931 drm_dp_aux_unregister(&intel_dp
->aux
);
5932 if (is_edp(intel_dp
)) {
5933 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5935 * vdd might still be enabled do to the delayed vdd off.
5936 * Make sure vdd is actually turned off here.
5939 edp_panel_vdd_off_sync(intel_dp
);
5940 pps_unlock(intel_dp
);
5942 drm_connector_unregister(connector
);
5943 drm_connector_cleanup(connector
);
5947 intel_dp_add_properties(intel_dp
, connector
);
5949 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5950 * 0xd. Failure to do so will result in spurious interrupts being
5951 * generated on the port when a cable is not attached.
5953 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5954 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5955 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5958 i915_debugfs_connector_add(connector
);
5964 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5967 struct intel_digital_port
*intel_dig_port
;
5968 struct intel_encoder
*intel_encoder
;
5969 struct drm_encoder
*encoder
;
5970 struct intel_connector
*intel_connector
;
5972 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5973 if (!intel_dig_port
)
5976 intel_connector
= intel_connector_alloc();
5977 if (!intel_connector
) {
5978 kfree(intel_dig_port
);
5982 intel_encoder
= &intel_dig_port
->base
;
5983 encoder
= &intel_encoder
->base
;
5985 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5986 DRM_MODE_ENCODER_TMDS
);
5988 intel_encoder
->compute_config
= intel_dp_compute_config
;
5989 intel_encoder
->disable
= intel_disable_dp
;
5990 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5991 intel_encoder
->get_config
= intel_dp_get_config
;
5992 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5993 if (IS_CHERRYVIEW(dev
)) {
5994 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5995 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5996 intel_encoder
->enable
= vlv_enable_dp
;
5997 intel_encoder
->post_disable
= chv_post_disable_dp
;
5998 } else if (IS_VALLEYVIEW(dev
)) {
5999 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6000 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6001 intel_encoder
->enable
= vlv_enable_dp
;
6002 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6004 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6005 intel_encoder
->enable
= g4x_enable_dp
;
6006 if (INTEL_INFO(dev
)->gen
>= 5)
6007 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6010 intel_dig_port
->port
= port
;
6011 intel_dig_port
->dp
.output_reg
= output_reg
;
6013 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
6014 if (IS_CHERRYVIEW(dev
)) {
6016 intel_encoder
->crtc_mask
= 1 << 2;
6018 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6020 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6022 intel_encoder
->cloneable
= 0;
6024 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6025 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6027 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
6028 drm_encoder_cleanup(encoder
);
6029 kfree(intel_dig_port
);
6030 kfree(intel_connector
);
6034 void intel_dp_mst_suspend(struct drm_device
*dev
)
6036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6040 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6041 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6042 if (!intel_dig_port
)
6045 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
6046 if (!intel_dig_port
->dp
.can_mst
)
6048 if (intel_dig_port
->dp
.is_mst
)
6049 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6054 void intel_dp_mst_resume(struct drm_device
*dev
)
6056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6059 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6060 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6061 if (!intel_dig_port
)
6063 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
6066 if (!intel_dig_port
->dp
.can_mst
)
6069 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6071 intel_dp_check_mst_status(&intel_dig_port
->dp
);