2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
293 static void pps_lock(struct intel_dp
*intel_dp
)
295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
296 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
297 struct drm_device
*dev
= encoder
->base
.dev
;
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 enum intel_display_power_domain power_domain
;
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
305 power_domain
= intel_display_port_power_domain(encoder
);
306 intel_display_power_get(dev_priv
, power_domain
);
308 mutex_lock(&dev_priv
->pps_mutex
);
311 static void pps_unlock(struct intel_dp
*intel_dp
)
313 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
314 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
315 struct drm_device
*dev
= encoder
->base
.dev
;
316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 enum intel_display_power_domain power_domain
;
319 mutex_unlock(&dev_priv
->pps_mutex
);
321 power_domain
= intel_display_port_power_domain(encoder
);
322 intel_display_power_put(dev_priv
, power_domain
);
326 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
328 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
329 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
331 struct intel_encoder
*encoder
;
332 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
333 struct edp_power_seq power_seq
;
335 lockdep_assert_held(&dev_priv
->pps_mutex
);
337 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
338 return intel_dp
->pps_pipe
;
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
344 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
346 struct intel_dp
*tmp
;
348 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
351 tmp
= enc_to_intel_dp(&encoder
->base
);
353 if (tmp
->pps_pipe
!= INVALID_PIPE
)
354 pipes
&= ~(1 << tmp
->pps_pipe
);
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
361 if (WARN_ON(pipes
== 0))
364 intel_dp
->pps_pipe
= ffs(pipes
) - 1;
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp
->pps_pipe
),
368 port_name(intel_dig_port
->port
));
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
372 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
375 return intel_dp
->pps_pipe
;
378 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
381 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
387 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
393 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
400 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
402 vlv_pipe_check pipe_check
)
406 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
407 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
408 PANEL_PORT_SELECT_MASK
;
410 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
413 if (!pipe_check(dev_priv
, pipe
))
423 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
425 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
426 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
428 struct edp_power_seq power_seq
;
429 enum port port
= intel_dig_port
->port
;
431 lockdep_assert_held(&dev_priv
->pps_mutex
);
433 /* try to find a pipe with this port selected */
434 /* first pick one where the panel is on */
435 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
439 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
440 vlv_pipe_has_vdd_on
);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
443 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
456 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
457 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
461 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
463 struct drm_device
*dev
= dev_priv
->dev
;
464 struct intel_encoder
*encoder
;
466 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
479 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
480 struct intel_dp
*intel_dp
;
482 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
485 intel_dp
= enc_to_intel_dp(&encoder
->base
);
486 intel_dp
->pps_pipe
= INVALID_PIPE
;
490 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
492 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
494 if (HAS_PCH_SPLIT(dev
))
495 return PCH_PP_CONTROL
;
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
500 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
502 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
504 if (HAS_PCH_SPLIT(dev
))
505 return PCH_PP_STATUS
;
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
510 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
515 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
517 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
520 u32 pp_ctrl_reg
, pp_div_reg
;
522 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
527 if (IS_VALLEYVIEW(dev
)) {
528 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
530 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
531 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
532 pp_div
= I915_READ(pp_div_reg
);
533 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
537 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
538 msleep(intel_dp
->panel_power_cycle_delay
);
541 pps_unlock(intel_dp
);
546 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
548 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
551 lockdep_assert_held(&dev_priv
->pps_mutex
);
553 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
556 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
558 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
561 lockdep_assert_held(&dev_priv
->pps_mutex
);
563 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
567 intel_dp_check_edp(struct intel_dp
*intel_dp
)
569 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
572 if (!is_edp(intel_dp
))
575 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
578 I915_READ(_pp_stat_reg(intel_dp
)),
579 I915_READ(_pp_ctrl_reg(intel_dp
)));
584 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
586 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
587 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
589 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
593 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
595 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
596 msecs_to_jiffies_timeout(10));
598 done
= wait_for_atomic(C
, 10) == 0;
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
607 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
609 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
610 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
616 return index
? 0 : intel_hrawclk(dev
) / 2;
619 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
621 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
622 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
627 if (intel_dig_port
->port
== PORT_A
) {
628 if (IS_GEN6(dev
) || IS_GEN7(dev
))
629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
631 return 225; /* eDP input clock at 450Mhz */
633 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
637 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
639 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
640 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
643 if (intel_dig_port
->port
== PORT_A
) {
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
647 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
648 /* Workaround for non-ULT HSW */
655 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
659 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
661 return index
? 0 : 100;
664 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
667 uint32_t aux_clock_divider
)
669 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
670 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
671 uint32_t precharge
, timeout
;
678 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
679 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
681 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
683 return DP_AUX_CH_CTL_SEND_BUSY
|
685 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
686 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
688 DP_AUX_CH_CTL_RECEIVE_ERROR
|
689 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
690 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
691 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
695 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
696 uint8_t *send
, int send_bytes
,
697 uint8_t *recv
, int recv_size
)
699 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
700 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
702 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
703 uint32_t ch_data
= ch_ctl
+ 4;
704 uint32_t aux_clock_divider
;
705 int i
, ret
, recv_bytes
;
708 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
719 vdd
= edp_panel_vdd_on(intel_dp
);
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
725 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
727 intel_dp_check_edp(intel_dp
);
729 intel_aux_display_runtime_get(dev_priv
);
731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
733 status
= I915_READ_NOTRACE(ch_ctl
);
734 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
752 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
753 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i
= 0; i
< send_bytes
; i
+= 4)
762 I915_WRITE(ch_data
+ i
,
763 pack_aux(send
+ i
, send_bytes
- i
));
765 /* Send the command and wait for it to complete */
766 I915_WRITE(ch_ctl
, send_ctl
);
768 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
770 /* Clear done status and any errors */
774 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
775 DP_AUX_CH_CTL_RECEIVE_ERROR
);
777 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
778 DP_AUX_CH_CTL_RECEIVE_ERROR
))
780 if (status
& DP_AUX_CH_CTL_DONE
)
783 if (status
& DP_AUX_CH_CTL_DONE
)
787 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
796 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
804 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
810 /* Unload any bytes sent back from the other side */
811 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
813 if (recv_bytes
> recv_size
)
814 recv_bytes
= recv_size
;
816 for (i
= 0; i
< recv_bytes
; i
+= 4)
817 unpack_aux(I915_READ(ch_data
+ i
),
818 recv
+ i
, recv_bytes
- i
);
822 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
823 intel_aux_display_runtime_put(dev_priv
);
826 edp_panel_vdd_off(intel_dp
, false);
828 pps_unlock(intel_dp
);
833 #define BARE_ADDRESS_SIZE 3
834 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
836 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
838 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
839 uint8_t txbuf
[20], rxbuf
[20];
840 size_t txsize
, rxsize
;
843 txbuf
[0] = msg
->request
<< 4;
844 txbuf
[1] = msg
->address
>> 8;
845 txbuf
[2] = msg
->address
& 0xff;
846 txbuf
[3] = msg
->size
- 1;
848 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
849 case DP_AUX_NATIVE_WRITE
:
850 case DP_AUX_I2C_WRITE
:
851 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
854 if (WARN_ON(txsize
> 20))
857 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
859 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
861 msg
->reply
= rxbuf
[0] >> 4;
863 /* Return payload size. */
868 case DP_AUX_NATIVE_READ
:
869 case DP_AUX_I2C_READ
:
870 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
871 rxsize
= msg
->size
+ 1;
873 if (WARN_ON(rxsize
> 20))
876 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
878 msg
->reply
= rxbuf
[0] >> 4;
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
883 * Return payload size.
886 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
899 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
901 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
902 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
903 enum port port
= intel_dig_port
->port
;
904 const char *name
= NULL
;
909 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
913 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
917 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
921 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
929 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
931 intel_dp
->aux
.name
= name
;
932 intel_dp
->aux
.dev
= dev
->dev
;
933 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
935 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
936 connector
->base
.kdev
->kobj
.name
);
938 ret
= drm_dp_aux_register(&intel_dp
->aux
);
940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
945 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
946 &intel_dp
->aux
.ddc
.dev
.kobj
,
947 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
950 drm_dp_aux_unregister(&intel_dp
->aux
);
955 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
957 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
959 if (!intel_connector
->mst_port
)
960 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
961 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
962 intel_connector_unregister(intel_connector
);
966 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
969 case DP_LINK_BW_1_62
:
970 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
973 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
976 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
982 intel_dp_set_clock(struct intel_encoder
*encoder
,
983 struct intel_crtc_config
*pipe_config
, int link_bw
)
985 struct drm_device
*dev
= encoder
->base
.dev
;
986 const struct dp_link_dpll
*divisor
= NULL
;
991 count
= ARRAY_SIZE(gen4_dpll
);
992 } else if (HAS_PCH_SPLIT(dev
)) {
994 count
= ARRAY_SIZE(pch_dpll
);
995 } else if (IS_CHERRYVIEW(dev
)) {
997 count
= ARRAY_SIZE(chv_dpll
);
998 } else if (IS_VALLEYVIEW(dev
)) {
1000 count
= ARRAY_SIZE(vlv_dpll
);
1003 if (divisor
&& count
) {
1004 for (i
= 0; i
< count
; i
++) {
1005 if (link_bw
== divisor
[i
].link_bw
) {
1006 pipe_config
->dpll
= divisor
[i
].dpll
;
1007 pipe_config
->clock_set
= true;
1015 intel_dp_compute_config(struct intel_encoder
*encoder
,
1016 struct intel_crtc_config
*pipe_config
)
1018 struct drm_device
*dev
= encoder
->base
.dev
;
1019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1020 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1021 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1022 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1023 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1024 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1025 int lane_count
, clock
;
1026 int min_lane_count
= 1;
1027 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1028 /* Conveniently, the link BW constants become indices with a shift...*/
1030 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1032 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1033 int link_avail
, link_clock
;
1035 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1036 pipe_config
->has_pch_encoder
= true;
1038 pipe_config
->has_dp_encoder
= true;
1039 pipe_config
->has_drrs
= false;
1040 pipe_config
->has_audio
= intel_dp
->has_audio
;
1042 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1043 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1045 if (!HAS_PCH_SPLIT(dev
))
1046 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1047 intel_connector
->panel
.fitting_mode
);
1049 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1050 intel_connector
->panel
.fitting_mode
);
1053 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
1058 max_lane_count
, bws
[max_clock
],
1059 adjusted_mode
->crtc_clock
);
1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
1063 bpp
= pipe_config
->pipe_bpp
;
1064 if (is_edp(intel_dp
)) {
1065 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv
->vbt
.edp_bpp
);
1068 bpp
= dev_priv
->vbt
.edp_bpp
;
1072 * Use the maximum clock and number of lanes the eDP panel
1073 * advertizes being capable of. The panels are generally
1074 * designed to support only a single clock and lane
1075 * configuration, and typically these values correspond to the
1076 * native resolution of the panel.
1078 min_lane_count
= max_lane_count
;
1079 min_clock
= max_clock
;
1082 for (; bpp
>= 6*3; bpp
-= 2*3) {
1083 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1086 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1087 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1088 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1089 link_avail
= intel_dp_max_data_rate(link_clock
,
1092 if (mode_rate
<= link_avail
) {
1102 if (intel_dp
->color_range_auto
) {
1105 * CEA-861-E - 5.1 Default Encoding Parameters
1106 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1108 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1109 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1111 intel_dp
->color_range
= 0;
1114 if (intel_dp
->color_range
)
1115 pipe_config
->limited_color_range
= true;
1117 intel_dp
->link_bw
= bws
[clock
];
1118 intel_dp
->lane_count
= lane_count
;
1119 pipe_config
->pipe_bpp
= bpp
;
1120 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1122 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1123 intel_dp
->link_bw
, intel_dp
->lane_count
,
1124 pipe_config
->port_clock
, bpp
);
1125 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1126 mode_rate
, link_avail
);
1128 intel_link_compute_m_n(bpp
, lane_count
,
1129 adjusted_mode
->crtc_clock
,
1130 pipe_config
->port_clock
,
1131 &pipe_config
->dp_m_n
);
1133 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1134 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1135 pipe_config
->has_drrs
= true;
1136 intel_link_compute_m_n(bpp
, lane_count
,
1137 intel_connector
->panel
.downclock_mode
->clock
,
1138 pipe_config
->port_clock
,
1139 &pipe_config
->dp_m2_n2
);
1142 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1143 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1145 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1150 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1152 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1153 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1154 struct drm_device
*dev
= crtc
->base
.dev
;
1155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1158 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1159 dpa_ctl
= I915_READ(DP_A
);
1160 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1162 if (crtc
->config
.port_clock
== 162000) {
1163 /* For a long time we've carried around a ILK-DevA w/a for the
1164 * 160MHz clock. If we're really unlucky, it's still required.
1166 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1167 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1168 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1170 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1171 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1174 I915_WRITE(DP_A
, dpa_ctl
);
1180 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1182 struct drm_device
*dev
= encoder
->base
.dev
;
1183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1184 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1185 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1186 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1187 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1190 * There are four kinds of DP registers:
1197 * IBX PCH and CPU are the same for almost everything,
1198 * except that the CPU DP PLL is configured in this
1201 * CPT PCH is quite different, having many bits moved
1202 * to the TRANS_DP_CTL register instead. That
1203 * configuration happens (oddly) in ironlake_pch_enable
1206 /* Preserve the BIOS-computed detected bit. This is
1207 * supposed to be read-only.
1209 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1211 /* Handle DP bits in common between all three register formats */
1212 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1213 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1215 if (crtc
->config
.has_audio
) {
1216 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1217 pipe_name(crtc
->pipe
));
1218 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1219 intel_write_eld(&encoder
->base
, adjusted_mode
);
1222 /* Split out the IBX/CPU vs CPT settings */
1224 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1225 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1226 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1227 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1228 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1229 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1231 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1232 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1234 intel_dp
->DP
|= crtc
->pipe
<< 29;
1235 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1236 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1237 intel_dp
->DP
|= intel_dp
->color_range
;
1239 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1240 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1241 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1242 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1243 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1245 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1246 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1248 if (!IS_CHERRYVIEW(dev
)) {
1249 if (crtc
->pipe
== 1)
1250 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1252 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1255 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1259 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1260 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1262 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1263 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1265 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1266 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1268 static void wait_panel_status(struct intel_dp
*intel_dp
,
1272 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1274 u32 pp_stat_reg
, pp_ctrl_reg
;
1276 lockdep_assert_held(&dev_priv
->pps_mutex
);
1278 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1279 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1281 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1283 I915_READ(pp_stat_reg
),
1284 I915_READ(pp_ctrl_reg
));
1286 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1287 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1288 I915_READ(pp_stat_reg
),
1289 I915_READ(pp_ctrl_reg
));
1292 DRM_DEBUG_KMS("Wait complete\n");
1295 static void wait_panel_on(struct intel_dp
*intel_dp
)
1297 DRM_DEBUG_KMS("Wait for panel power on\n");
1298 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1301 static void wait_panel_off(struct intel_dp
*intel_dp
)
1303 DRM_DEBUG_KMS("Wait for panel power off time\n");
1304 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1307 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1309 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1311 /* When we disable the VDD override bit last we have to do the manual
1313 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1314 intel_dp
->panel_power_cycle_delay
);
1316 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1319 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1321 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1322 intel_dp
->backlight_on_delay
);
1325 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1327 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1328 intel_dp
->backlight_off_delay
);
1331 /* Read the current pp_control value, unlocking the register if it
1335 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1337 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1341 lockdep_assert_held(&dev_priv
->pps_mutex
);
1343 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1344 control
&= ~PANEL_UNLOCK_MASK
;
1345 control
|= PANEL_UNLOCK_REGS
;
1350 * Must be paired with edp_panel_vdd_off().
1351 * Must hold pps_mutex around the whole on/off sequence.
1352 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1354 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1356 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1357 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1358 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1360 enum intel_display_power_domain power_domain
;
1362 u32 pp_stat_reg
, pp_ctrl_reg
;
1363 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1365 lockdep_assert_held(&dev_priv
->pps_mutex
);
1367 if (!is_edp(intel_dp
))
1370 intel_dp
->want_panel_vdd
= true;
1372 if (edp_have_panel_vdd(intel_dp
))
1373 return need_to_disable
;
1375 power_domain
= intel_display_port_power_domain(intel_encoder
);
1376 intel_display_power_get(dev_priv
, power_domain
);
1378 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1380 if (!edp_have_panel_power(intel_dp
))
1381 wait_panel_power_cycle(intel_dp
);
1383 pp
= ironlake_get_pp_control(intel_dp
);
1384 pp
|= EDP_FORCE_VDD
;
1386 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1387 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1389 I915_WRITE(pp_ctrl_reg
, pp
);
1390 POSTING_READ(pp_ctrl_reg
);
1391 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1392 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1394 * If the panel wasn't on, delay before accessing aux channel
1396 if (!edp_have_panel_power(intel_dp
)) {
1397 DRM_DEBUG_KMS("eDP was not running\n");
1398 msleep(intel_dp
->panel_power_up_delay
);
1401 return need_to_disable
;
1405 * Must be paired with intel_edp_panel_vdd_off() or
1406 * intel_edp_panel_off().
1407 * Nested calls to these functions are not allowed since
1408 * we drop the lock. Caller must use some higher level
1409 * locking to prevent nested calls from other threads.
1411 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1415 if (!is_edp(intel_dp
))
1419 vdd
= edp_panel_vdd_on(intel_dp
);
1420 pps_unlock(intel_dp
);
1422 WARN(!vdd
, "eDP VDD already requested on\n");
1425 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1427 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1429 struct intel_digital_port
*intel_dig_port
=
1430 dp_to_dig_port(intel_dp
);
1431 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1432 enum intel_display_power_domain power_domain
;
1434 u32 pp_stat_reg
, pp_ctrl_reg
;
1436 lockdep_assert_held(&dev_priv
->pps_mutex
);
1438 WARN_ON(intel_dp
->want_panel_vdd
);
1440 if (!edp_have_panel_vdd(intel_dp
))
1443 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1445 pp
= ironlake_get_pp_control(intel_dp
);
1446 pp
&= ~EDP_FORCE_VDD
;
1448 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1449 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1451 I915_WRITE(pp_ctrl_reg
, pp
);
1452 POSTING_READ(pp_ctrl_reg
);
1454 /* Make sure sequencer is idle before allowing subsequent activity */
1455 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1456 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1458 if ((pp
& POWER_TARGET_ON
) == 0)
1459 intel_dp
->last_power_cycle
= jiffies
;
1461 power_domain
= intel_display_port_power_domain(intel_encoder
);
1462 intel_display_power_put(dev_priv
, power_domain
);
1465 static void edp_panel_vdd_work(struct work_struct
*__work
)
1467 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1468 struct intel_dp
, panel_vdd_work
);
1471 if (!intel_dp
->want_panel_vdd
)
1472 edp_panel_vdd_off_sync(intel_dp
);
1473 pps_unlock(intel_dp
);
1476 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1478 unsigned long delay
;
1481 * Queue the timer to fire a long time from now (relative to the power
1482 * down delay) to keep the panel power up across a sequence of
1485 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1486 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1490 * Must be paired with edp_panel_vdd_on().
1491 * Must hold pps_mutex around the whole on/off sequence.
1492 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1494 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1496 struct drm_i915_private
*dev_priv
=
1497 intel_dp_to_dev(intel_dp
)->dev_private
;
1499 lockdep_assert_held(&dev_priv
->pps_mutex
);
1501 if (!is_edp(intel_dp
))
1504 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1506 intel_dp
->want_panel_vdd
= false;
1509 edp_panel_vdd_off_sync(intel_dp
);
1511 edp_panel_vdd_schedule_off(intel_dp
);
1515 * Must be paired with intel_edp_panel_vdd_on().
1516 * Nested calls to these functions are not allowed since
1517 * we drop the lock. Caller must use some higher level
1518 * locking to prevent nested calls from other threads.
1520 static void intel_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1522 if (!is_edp(intel_dp
))
1526 edp_panel_vdd_off(intel_dp
, sync
);
1527 pps_unlock(intel_dp
);
1530 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1532 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1537 if (!is_edp(intel_dp
))
1540 DRM_DEBUG_KMS("Turn eDP power on\n");
1544 if (edp_have_panel_power(intel_dp
)) {
1545 DRM_DEBUG_KMS("eDP power already on\n");
1549 wait_panel_power_cycle(intel_dp
);
1551 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1552 pp
= ironlake_get_pp_control(intel_dp
);
1554 /* ILK workaround: disable reset around power sequence */
1555 pp
&= ~PANEL_POWER_RESET
;
1556 I915_WRITE(pp_ctrl_reg
, pp
);
1557 POSTING_READ(pp_ctrl_reg
);
1560 pp
|= POWER_TARGET_ON
;
1562 pp
|= PANEL_POWER_RESET
;
1564 I915_WRITE(pp_ctrl_reg
, pp
);
1565 POSTING_READ(pp_ctrl_reg
);
1567 wait_panel_on(intel_dp
);
1568 intel_dp
->last_power_on
= jiffies
;
1571 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1572 I915_WRITE(pp_ctrl_reg
, pp
);
1573 POSTING_READ(pp_ctrl_reg
);
1577 pps_unlock(intel_dp
);
1580 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1582 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1583 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1584 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1586 enum intel_display_power_domain power_domain
;
1590 if (!is_edp(intel_dp
))
1593 DRM_DEBUG_KMS("Turn eDP power off\n");
1597 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1599 pp
= ironlake_get_pp_control(intel_dp
);
1600 /* We need to switch off panel power _and_ force vdd, for otherwise some
1601 * panels get very unhappy and cease to work. */
1602 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1605 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1607 intel_dp
->want_panel_vdd
= false;
1609 I915_WRITE(pp_ctrl_reg
, pp
);
1610 POSTING_READ(pp_ctrl_reg
);
1612 intel_dp
->last_power_cycle
= jiffies
;
1613 wait_panel_off(intel_dp
);
1615 /* We got a reference when we enabled the VDD. */
1616 power_domain
= intel_display_port_power_domain(intel_encoder
);
1617 intel_display_power_put(dev_priv
, power_domain
);
1619 pps_unlock(intel_dp
);
1622 /* Enable backlight in the panel power control. */
1623 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1625 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1626 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1632 * If we enable the backlight right away following a panel power
1633 * on, we may see slight flicker as the panel syncs with the eDP
1634 * link. So delay a bit to make sure the image is solid before
1635 * allowing it to appear.
1637 wait_backlight_on(intel_dp
);
1641 pp
= ironlake_get_pp_control(intel_dp
);
1642 pp
|= EDP_BLC_ENABLE
;
1644 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1646 I915_WRITE(pp_ctrl_reg
, pp
);
1647 POSTING_READ(pp_ctrl_reg
);
1649 pps_unlock(intel_dp
);
1652 /* Enable backlight PWM and backlight PP control. */
1653 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1655 if (!is_edp(intel_dp
))
1658 DRM_DEBUG_KMS("\n");
1660 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1661 _intel_edp_backlight_on(intel_dp
);
1664 /* Disable backlight in the panel power control. */
1665 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1667 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1672 if (!is_edp(intel_dp
))
1677 pp
= ironlake_get_pp_control(intel_dp
);
1678 pp
&= ~EDP_BLC_ENABLE
;
1680 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1682 I915_WRITE(pp_ctrl_reg
, pp
);
1683 POSTING_READ(pp_ctrl_reg
);
1685 pps_unlock(intel_dp
);
1687 intel_dp
->last_backlight_off
= jiffies
;
1688 edp_wait_backlight_off(intel_dp
);
1691 /* Disable backlight PP control and backlight PWM. */
1692 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1694 if (!is_edp(intel_dp
))
1697 DRM_DEBUG_KMS("\n");
1699 _intel_edp_backlight_off(intel_dp
);
1700 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1704 * Hook for controlling the panel power control backlight through the bl_power
1705 * sysfs attribute. Take care to handle multiple calls.
1707 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1710 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1714 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1715 pps_unlock(intel_dp
);
1717 if (is_enabled
== enable
)
1720 DRM_DEBUG_KMS("panel power control backlight %s\n",
1721 enable
? "enable" : "disable");
1724 _intel_edp_backlight_on(intel_dp
);
1726 _intel_edp_backlight_off(intel_dp
);
1729 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1731 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1732 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1733 struct drm_device
*dev
= crtc
->dev
;
1734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1737 assert_pipe_disabled(dev_priv
,
1738 to_intel_crtc(crtc
)->pipe
);
1740 DRM_DEBUG_KMS("\n");
1741 dpa_ctl
= I915_READ(DP_A
);
1742 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1743 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1745 /* We don't adjust intel_dp->DP while tearing down the link, to
1746 * facilitate link retraining (e.g. after hotplug). Hence clear all
1747 * enable bits here to ensure that we don't enable too much. */
1748 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1749 intel_dp
->DP
|= DP_PLL_ENABLE
;
1750 I915_WRITE(DP_A
, intel_dp
->DP
);
1755 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1757 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1758 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1759 struct drm_device
*dev
= crtc
->dev
;
1760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1763 assert_pipe_disabled(dev_priv
,
1764 to_intel_crtc(crtc
)->pipe
);
1766 dpa_ctl
= I915_READ(DP_A
);
1767 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1768 "dp pll off, should be on\n");
1769 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1771 /* We can't rely on the value tracked for the DP register in
1772 * intel_dp->DP because link_down must not change that (otherwise link
1773 * re-training will fail. */
1774 dpa_ctl
&= ~DP_PLL_ENABLE
;
1775 I915_WRITE(DP_A
, dpa_ctl
);
1780 /* If the sink supports it, try to set the power state appropriately */
1781 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1785 /* Should have a valid DPCD by this point */
1786 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1789 if (mode
!= DRM_MODE_DPMS_ON
) {
1790 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1794 * When turning on, we need to retry for 1ms to give the sink
1797 for (i
= 0; i
< 3; i
++) {
1798 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1807 DRM_DEBUG_KMS("failed to %s sink power state\n",
1808 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1811 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1814 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1815 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1816 struct drm_device
*dev
= encoder
->base
.dev
;
1817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1818 enum intel_display_power_domain power_domain
;
1821 power_domain
= intel_display_port_power_domain(encoder
);
1822 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1825 tmp
= I915_READ(intel_dp
->output_reg
);
1827 if (!(tmp
& DP_PORT_EN
))
1830 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1831 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1832 } else if (IS_CHERRYVIEW(dev
)) {
1833 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1834 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1835 *pipe
= PORT_TO_PIPE(tmp
);
1841 switch (intel_dp
->output_reg
) {
1843 trans_sel
= TRANS_DP_PORT_SEL_B
;
1846 trans_sel
= TRANS_DP_PORT_SEL_C
;
1849 trans_sel
= TRANS_DP_PORT_SEL_D
;
1855 for_each_pipe(dev_priv
, i
) {
1856 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1857 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1863 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1864 intel_dp
->output_reg
);
1870 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1871 struct intel_crtc_config
*pipe_config
)
1873 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1875 struct drm_device
*dev
= encoder
->base
.dev
;
1876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1877 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1878 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1881 tmp
= I915_READ(intel_dp
->output_reg
);
1882 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1883 pipe_config
->has_audio
= true;
1885 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1886 if (tmp
& DP_SYNC_HS_HIGH
)
1887 flags
|= DRM_MODE_FLAG_PHSYNC
;
1889 flags
|= DRM_MODE_FLAG_NHSYNC
;
1891 if (tmp
& DP_SYNC_VS_HIGH
)
1892 flags
|= DRM_MODE_FLAG_PVSYNC
;
1894 flags
|= DRM_MODE_FLAG_NVSYNC
;
1896 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1897 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1898 flags
|= DRM_MODE_FLAG_PHSYNC
;
1900 flags
|= DRM_MODE_FLAG_NHSYNC
;
1902 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1903 flags
|= DRM_MODE_FLAG_PVSYNC
;
1905 flags
|= DRM_MODE_FLAG_NVSYNC
;
1908 pipe_config
->adjusted_mode
.flags
|= flags
;
1910 pipe_config
->has_dp_encoder
= true;
1912 intel_dp_get_m_n(crtc
, pipe_config
);
1914 if (port
== PORT_A
) {
1915 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1916 pipe_config
->port_clock
= 162000;
1918 pipe_config
->port_clock
= 270000;
1921 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1922 &pipe_config
->dp_m_n
);
1924 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1925 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1927 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1929 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1930 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1932 * This is a big fat ugly hack.
1934 * Some machines in UEFI boot mode provide us a VBT that has 18
1935 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1936 * unknown we fail to light up. Yet the same BIOS boots up with
1937 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1938 * max, not what it tells us to use.
1940 * Note: This will still be broken if the eDP panel is not lit
1941 * up by the BIOS, and thus we can't get the mode at module
1944 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1945 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1946 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1950 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1952 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1955 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1962 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1965 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1966 struct edp_vsc_psr
*vsc_psr
)
1968 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1969 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1971 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1972 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1973 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1974 uint32_t *data
= (uint32_t *) vsc_psr
;
1977 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1978 the video DIP being updated before program video DIP data buffer
1979 registers for DIP being updated. */
1980 I915_WRITE(ctl_reg
, 0);
1981 POSTING_READ(ctl_reg
);
1983 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1984 if (i
< sizeof(struct edp_vsc_psr
))
1985 I915_WRITE(data_reg
+ i
, *data
++);
1987 I915_WRITE(data_reg
+ i
, 0);
1990 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1991 POSTING_READ(ctl_reg
);
1994 static void intel_edp_psr_setup_vsc(struct intel_dp
*intel_dp
)
1996 struct edp_vsc_psr psr_vsc
;
1998 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1999 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
2000 psr_vsc
.sdp_header
.HB0
= 0;
2001 psr_vsc
.sdp_header
.HB1
= 0x7;
2002 psr_vsc
.sdp_header
.HB2
= 0x2;
2003 psr_vsc
.sdp_header
.HB3
= 0x8;
2004 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
2007 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
2009 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2010 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 uint32_t aux_clock_divider
;
2013 int precharge
= 0x3;
2014 int msg_size
= 5; /* Header(4) + Message(1) */
2015 bool only_standby
= false;
2017 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
2019 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2020 only_standby
= true;
2022 /* Enable PSR in sink */
2023 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
2024 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2025 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
2027 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2028 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
2030 /* Setup AUX registers */
2031 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
2032 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
2033 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
2034 DP_AUX_CH_CTL_TIME_OUT_400us
|
2035 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
2036 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
2037 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
2040 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
2042 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2043 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2045 uint32_t max_sleep_time
= 0x1f;
2046 uint32_t idle_frames
= 1;
2048 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
2049 bool only_standby
= false;
2051 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2052 only_standby
= true;
2054 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
2055 val
|= EDP_PSR_LINK_STANDBY
;
2056 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
2057 val
|= EDP_PSR_TP1_TIME_0us
;
2058 val
|= EDP_PSR_SKIP_AUX_EXIT
;
2059 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
2061 val
|= EDP_PSR_LINK_DISABLE
;
2063 I915_WRITE(EDP_PSR_CTL(dev
), val
|
2064 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
2065 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
2066 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
2070 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
2072 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2073 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2075 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
2076 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2078 lockdep_assert_held(&dev_priv
->psr
.lock
);
2079 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
2080 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
2082 dev_priv
->psr
.source_ok
= false;
2084 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
2085 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2089 if (!i915
.enable_psr
) {
2090 DRM_DEBUG_KMS("PSR disable by flag\n");
2094 /* Below limitations aren't valid for Broadwell */
2095 if (IS_BROADWELL(dev
))
2098 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
2100 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2104 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2105 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2110 dev_priv
->psr
.source_ok
= true;
2114 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
2116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2117 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2120 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2121 WARN_ON(dev_priv
->psr
.active
);
2122 lockdep_assert_held(&dev_priv
->psr
.lock
);
2124 /* Enable PSR on the panel */
2125 intel_edp_psr_enable_sink(intel_dp
);
2127 /* Enable PSR on the host */
2128 intel_edp_psr_enable_source(intel_dp
);
2130 dev_priv
->psr
.active
= true;
2133 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
2135 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2138 if (!HAS_PSR(dev
)) {
2139 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2143 if (!is_edp_psr(intel_dp
)) {
2144 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2148 mutex_lock(&dev_priv
->psr
.lock
);
2149 if (dev_priv
->psr
.enabled
) {
2150 DRM_DEBUG_KMS("PSR already in use\n");
2154 if (!intel_edp_psr_match_conditions(intel_dp
))
2157 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
2159 intel_edp_psr_setup_vsc(intel_dp
);
2161 /* Avoid continuous PSR exit by masking memup and hpd */
2162 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
2163 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
2165 dev_priv
->psr
.enabled
= intel_dp
;
2167 mutex_unlock(&dev_priv
->psr
.lock
);
2170 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
2172 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2175 mutex_lock(&dev_priv
->psr
.lock
);
2176 if (!dev_priv
->psr
.enabled
) {
2177 mutex_unlock(&dev_priv
->psr
.lock
);
2181 if (dev_priv
->psr
.active
) {
2182 I915_WRITE(EDP_PSR_CTL(dev
),
2183 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
2185 /* Wait till PSR is idle */
2186 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
2187 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
2188 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2190 dev_priv
->psr
.active
= false;
2192 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2195 dev_priv
->psr
.enabled
= NULL
;
2196 mutex_unlock(&dev_priv
->psr
.lock
);
2198 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
2201 static void intel_edp_psr_work(struct work_struct
*work
)
2203 struct drm_i915_private
*dev_priv
=
2204 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
2205 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
2207 mutex_lock(&dev_priv
->psr
.lock
);
2208 intel_dp
= dev_priv
->psr
.enabled
;
2214 * The delayed work can race with an invalidate hence we need to
2215 * recheck. Since psr_flush first clears this and then reschedules we
2216 * won't ever miss a flush when bailing out here.
2218 if (dev_priv
->psr
.busy_frontbuffer_bits
)
2221 intel_edp_psr_do_enable(intel_dp
);
2223 mutex_unlock(&dev_priv
->psr
.lock
);
2226 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
2228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2230 if (dev_priv
->psr
.active
) {
2231 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
2233 WARN_ON(!(val
& EDP_PSR_ENABLE
));
2235 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
2237 dev_priv
->psr
.active
= false;
2242 void intel_edp_psr_invalidate(struct drm_device
*dev
,
2243 unsigned frontbuffer_bits
)
2245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2246 struct drm_crtc
*crtc
;
2249 mutex_lock(&dev_priv
->psr
.lock
);
2250 if (!dev_priv
->psr
.enabled
) {
2251 mutex_unlock(&dev_priv
->psr
.lock
);
2255 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2256 pipe
= to_intel_crtc(crtc
)->pipe
;
2258 intel_edp_psr_do_exit(dev
);
2260 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2262 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2263 mutex_unlock(&dev_priv
->psr
.lock
);
2266 void intel_edp_psr_flush(struct drm_device
*dev
,
2267 unsigned frontbuffer_bits
)
2269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2270 struct drm_crtc
*crtc
;
2273 mutex_lock(&dev_priv
->psr
.lock
);
2274 if (!dev_priv
->psr
.enabled
) {
2275 mutex_unlock(&dev_priv
->psr
.lock
);
2279 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2280 pipe
= to_intel_crtc(crtc
)->pipe
;
2281 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2284 * On Haswell sprite plane updates don't result in a psr invalidating
2285 * signal in the hardware. Which means we need to manually fake this in
2286 * software for all flushes, not just when we've seen a preceding
2287 * invalidation through frontbuffer rendering.
2289 if (IS_HASWELL(dev
) &&
2290 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2291 intel_edp_psr_do_exit(dev
);
2293 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2294 schedule_delayed_work(&dev_priv
->psr
.work
,
2295 msecs_to_jiffies(100));
2296 mutex_unlock(&dev_priv
->psr
.lock
);
2299 void intel_edp_psr_init(struct drm_device
*dev
)
2301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2303 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2304 mutex_init(&dev_priv
->psr
.lock
);
2307 static void intel_disable_dp(struct intel_encoder
*encoder
)
2309 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2310 struct drm_device
*dev
= encoder
->base
.dev
;
2312 /* Make sure the panel is off before trying to change the mode. But also
2313 * ensure that we have vdd while we switch off the panel. */
2314 intel_edp_panel_vdd_on(intel_dp
);
2315 intel_edp_backlight_off(intel_dp
);
2316 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2317 intel_edp_panel_off(intel_dp
);
2319 /* disable the port before the pipe on g4x */
2320 if (INTEL_INFO(dev
)->gen
< 5)
2321 intel_dp_link_down(intel_dp
);
2324 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2326 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2327 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2329 intel_dp_link_down(intel_dp
);
2331 ironlake_edp_pll_off(intel_dp
);
2334 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2336 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2338 intel_dp_link_down(intel_dp
);
2341 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2343 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2344 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2345 struct drm_device
*dev
= encoder
->base
.dev
;
2346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2347 struct intel_crtc
*intel_crtc
=
2348 to_intel_crtc(encoder
->base
.crtc
);
2349 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2350 enum pipe pipe
= intel_crtc
->pipe
;
2353 intel_dp_link_down(intel_dp
);
2355 mutex_lock(&dev_priv
->dpio_lock
);
2357 /* Propagate soft reset to data lane reset */
2358 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2359 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2360 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2362 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2363 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2364 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2366 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2367 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2368 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2370 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2371 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2372 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2374 mutex_unlock(&dev_priv
->dpio_lock
);
2378 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2380 uint8_t dp_train_pat
)
2382 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2383 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2385 enum port port
= intel_dig_port
->port
;
2388 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2390 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2391 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2393 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2395 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2396 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2397 case DP_TRAINING_PATTERN_DISABLE
:
2398 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2401 case DP_TRAINING_PATTERN_1
:
2402 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2404 case DP_TRAINING_PATTERN_2
:
2405 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2407 case DP_TRAINING_PATTERN_3
:
2408 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2411 I915_WRITE(DP_TP_CTL(port
), temp
);
2413 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2414 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2416 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2417 case DP_TRAINING_PATTERN_DISABLE
:
2418 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2420 case DP_TRAINING_PATTERN_1
:
2421 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2423 case DP_TRAINING_PATTERN_2
:
2424 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2426 case DP_TRAINING_PATTERN_3
:
2427 DRM_ERROR("DP training pattern 3 not supported\n");
2428 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2433 if (IS_CHERRYVIEW(dev
))
2434 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2436 *DP
&= ~DP_LINK_TRAIN_MASK
;
2438 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2439 case DP_TRAINING_PATTERN_DISABLE
:
2440 *DP
|= DP_LINK_TRAIN_OFF
;
2442 case DP_TRAINING_PATTERN_1
:
2443 *DP
|= DP_LINK_TRAIN_PAT_1
;
2445 case DP_TRAINING_PATTERN_2
:
2446 *DP
|= DP_LINK_TRAIN_PAT_2
;
2448 case DP_TRAINING_PATTERN_3
:
2449 if (IS_CHERRYVIEW(dev
)) {
2450 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2452 DRM_ERROR("DP training pattern 3 not supported\n");
2453 *DP
|= DP_LINK_TRAIN_PAT_2
;
2460 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2462 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2465 intel_dp
->DP
|= DP_PORT_EN
;
2467 /* enable with pattern 1 (as per spec) */
2468 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2469 DP_TRAINING_PATTERN_1
);
2471 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2472 POSTING_READ(intel_dp
->output_reg
);
2475 static void intel_enable_dp(struct intel_encoder
*encoder
)
2477 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2478 struct drm_device
*dev
= encoder
->base
.dev
;
2479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2480 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2482 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2485 intel_dp_enable_port(intel_dp
);
2486 intel_edp_panel_vdd_on(intel_dp
);
2487 intel_edp_panel_on(intel_dp
);
2488 intel_edp_panel_vdd_off(intel_dp
, true);
2489 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2490 intel_dp_start_link_train(intel_dp
);
2491 intel_dp_complete_link_train(intel_dp
);
2492 intel_dp_stop_link_train(intel_dp
);
2495 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2497 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2499 intel_enable_dp(encoder
);
2500 intel_edp_backlight_on(intel_dp
);
2503 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2505 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2507 intel_edp_backlight_on(intel_dp
);
2510 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2512 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2513 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2515 intel_dp_prepare(encoder
);
2517 /* Only ilk+ has port A */
2518 if (dport
->port
== PORT_A
) {
2519 ironlake_set_pll_cpu_edp(intel_dp
);
2520 ironlake_edp_pll_on(intel_dp
);
2524 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2528 struct intel_encoder
*encoder
;
2530 lockdep_assert_held(&dev_priv
->pps_mutex
);
2532 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2534 struct intel_dp
*intel_dp
;
2537 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2540 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2541 port
= dp_to_dig_port(intel_dp
)->port
;
2543 if (intel_dp
->pps_pipe
!= pipe
)
2546 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2547 pipe_name(pipe
), port_name(port
));
2549 /* make sure vdd is off before we steal it */
2550 edp_panel_vdd_off_sync(intel_dp
);
2552 intel_dp
->pps_pipe
= INVALID_PIPE
;
2556 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2558 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2559 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2560 struct drm_device
*dev
= encoder
->base
.dev
;
2561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2562 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2563 struct edp_power_seq power_seq
;
2565 lockdep_assert_held(&dev_priv
->pps_mutex
);
2567 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2571 * If another power sequencer was being used on this
2572 * port previously make sure to turn off vdd there while
2573 * we still have control of it.
2575 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2576 edp_panel_vdd_off_sync(intel_dp
);
2579 * We may be stealing the power
2580 * sequencer from another port.
2582 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2584 /* now it's all ours */
2585 intel_dp
->pps_pipe
= crtc
->pipe
;
2587 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2588 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2590 /* init power sequencer on this pipe and port */
2591 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2592 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2596 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2598 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2599 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2600 struct drm_device
*dev
= encoder
->base
.dev
;
2601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2602 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2603 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2604 int pipe
= intel_crtc
->pipe
;
2607 mutex_lock(&dev_priv
->dpio_lock
);
2609 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2616 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2617 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2618 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2620 mutex_unlock(&dev_priv
->dpio_lock
);
2622 if (is_edp(intel_dp
)) {
2624 vlv_init_panel_power_sequencer(intel_dp
);
2625 pps_unlock(intel_dp
);
2628 intel_enable_dp(encoder
);
2630 vlv_wait_port_ready(dev_priv
, dport
);
2633 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2635 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2636 struct drm_device
*dev
= encoder
->base
.dev
;
2637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2638 struct intel_crtc
*intel_crtc
=
2639 to_intel_crtc(encoder
->base
.crtc
);
2640 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2641 int pipe
= intel_crtc
->pipe
;
2643 intel_dp_prepare(encoder
);
2645 /* Program Tx lane resets to default */
2646 mutex_lock(&dev_priv
->dpio_lock
);
2647 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2648 DPIO_PCS_TX_LANE2_RESET
|
2649 DPIO_PCS_TX_LANE1_RESET
);
2650 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2651 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2652 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2653 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2654 DPIO_PCS_CLK_SOFT_RESET
);
2656 /* Fix up inter-pair skew failure */
2657 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2658 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2659 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2660 mutex_unlock(&dev_priv
->dpio_lock
);
2663 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2665 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2666 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2667 struct drm_device
*dev
= encoder
->base
.dev
;
2668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2669 struct intel_crtc
*intel_crtc
=
2670 to_intel_crtc(encoder
->base
.crtc
);
2671 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2672 int pipe
= intel_crtc
->pipe
;
2676 mutex_lock(&dev_priv
->dpio_lock
);
2678 /* Deassert soft data lane reset*/
2679 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2680 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2681 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2683 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2684 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2685 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2687 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2688 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2689 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2691 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2692 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2693 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2695 /* Program Tx lane latency optimal setting*/
2696 for (i
= 0; i
< 4; i
++) {
2697 /* Set the latency optimal bit */
2698 data
= (i
== 1) ? 0x0 : 0x6;
2699 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2700 data
<< DPIO_FRC_LATENCY_SHFIT
);
2702 /* Set the upar bit */
2703 data
= (i
== 1) ? 0x0 : 0x1;
2704 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2705 data
<< DPIO_UPAR_SHIFT
);
2708 /* Data lane stagger programming */
2709 /* FIXME: Fix up value only after power analysis */
2711 mutex_unlock(&dev_priv
->dpio_lock
);
2713 if (is_edp(intel_dp
)) {
2715 vlv_init_panel_power_sequencer(intel_dp
);
2716 pps_unlock(intel_dp
);
2719 intel_enable_dp(encoder
);
2721 vlv_wait_port_ready(dev_priv
, dport
);
2724 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2726 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2727 struct drm_device
*dev
= encoder
->base
.dev
;
2728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2729 struct intel_crtc
*intel_crtc
=
2730 to_intel_crtc(encoder
->base
.crtc
);
2731 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2732 enum pipe pipe
= intel_crtc
->pipe
;
2735 intel_dp_prepare(encoder
);
2737 mutex_lock(&dev_priv
->dpio_lock
);
2739 /* program left/right clock distribution */
2740 if (pipe
!= PIPE_B
) {
2741 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2742 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2744 val
|= CHV_BUFLEFTENA1_FORCE
;
2746 val
|= CHV_BUFRIGHTENA1_FORCE
;
2747 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2749 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2750 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2752 val
|= CHV_BUFLEFTENA2_FORCE
;
2754 val
|= CHV_BUFRIGHTENA2_FORCE
;
2755 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2758 /* program clock channel usage */
2759 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2760 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2762 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2764 val
|= CHV_PCS_USEDCLKCHANNEL
;
2765 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2767 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2768 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2770 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2772 val
|= CHV_PCS_USEDCLKCHANNEL
;
2773 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2776 * This a a bit weird since generally CL
2777 * matches the pipe, but here we need to
2778 * pick the CL based on the port.
2780 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2782 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2784 val
|= CHV_CMN_USEDCLKCHANNEL
;
2785 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2787 mutex_unlock(&dev_priv
->dpio_lock
);
2791 * Native read with retry for link status and receiver capability reads for
2792 * cases where the sink may still be asleep.
2794 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2795 * supposed to retry 3 times per the spec.
2798 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2799 void *buffer
, size_t size
)
2804 for (i
= 0; i
< 3; i
++) {
2805 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2815 * Fetch AUX CH registers 0x202 - 0x207 which contain
2816 * link status information
2819 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2821 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2824 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2827 /* These are source-specific values. */
2829 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2831 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2832 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2834 if (IS_VALLEYVIEW(dev
))
2835 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2836 else if (IS_GEN7(dev
) && port
== PORT_A
)
2837 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2838 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2839 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2841 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2845 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2847 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2848 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2850 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2851 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2852 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2853 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2854 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2855 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2856 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2857 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2858 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2860 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2862 } else if (IS_VALLEYVIEW(dev
)) {
2863 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2865 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2866 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2867 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2869 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2870 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2872 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2874 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2875 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2876 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2877 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2878 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2880 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2882 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2885 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2886 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2887 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2889 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2890 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2891 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2892 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2894 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2899 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2901 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2903 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2904 struct intel_crtc
*intel_crtc
=
2905 to_intel_crtc(dport
->base
.base
.crtc
);
2906 unsigned long demph_reg_value
, preemph_reg_value
,
2907 uniqtranscale_reg_value
;
2908 uint8_t train_set
= intel_dp
->train_set
[0];
2909 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2910 int pipe
= intel_crtc
->pipe
;
2912 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2913 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2914 preemph_reg_value
= 0x0004000;
2915 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2917 demph_reg_value
= 0x2B405555;
2918 uniqtranscale_reg_value
= 0x552AB83A;
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2921 demph_reg_value
= 0x2B404040;
2922 uniqtranscale_reg_value
= 0x5548B83A;
2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2925 demph_reg_value
= 0x2B245555;
2926 uniqtranscale_reg_value
= 0x5560B83A;
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2929 demph_reg_value
= 0x2B405555;
2930 uniqtranscale_reg_value
= 0x5598DA3A;
2936 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2937 preemph_reg_value
= 0x0002000;
2938 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2940 demph_reg_value
= 0x2B404040;
2941 uniqtranscale_reg_value
= 0x5552B83A;
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2944 demph_reg_value
= 0x2B404848;
2945 uniqtranscale_reg_value
= 0x5580B83A;
2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2948 demph_reg_value
= 0x2B404040;
2949 uniqtranscale_reg_value
= 0x55ADDA3A;
2955 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2956 preemph_reg_value
= 0x0000000;
2957 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2959 demph_reg_value
= 0x2B305555;
2960 uniqtranscale_reg_value
= 0x5570B83A;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2963 demph_reg_value
= 0x2B2B4040;
2964 uniqtranscale_reg_value
= 0x55ADDA3A;
2970 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2971 preemph_reg_value
= 0x0006000;
2972 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2974 demph_reg_value
= 0x1B405555;
2975 uniqtranscale_reg_value
= 0x55ADDA3A;
2985 mutex_lock(&dev_priv
->dpio_lock
);
2986 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2987 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2988 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2989 uniqtranscale_reg_value
);
2990 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2991 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2992 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2993 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2994 mutex_unlock(&dev_priv
->dpio_lock
);
2999 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
3001 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3003 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3004 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3005 u32 deemph_reg_value
, margin_reg_value
, val
;
3006 uint8_t train_set
= intel_dp
->train_set
[0];
3007 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3008 enum pipe pipe
= intel_crtc
->pipe
;
3011 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3012 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3013 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3015 deemph_reg_value
= 128;
3016 margin_reg_value
= 52;
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3019 deemph_reg_value
= 128;
3020 margin_reg_value
= 77;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3023 deemph_reg_value
= 128;
3024 margin_reg_value
= 102;
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3027 deemph_reg_value
= 128;
3028 margin_reg_value
= 154;
3029 /* FIXME extra to set for 1200 */
3035 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3036 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3038 deemph_reg_value
= 85;
3039 margin_reg_value
= 78;
3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3042 deemph_reg_value
= 85;
3043 margin_reg_value
= 116;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3046 deemph_reg_value
= 85;
3047 margin_reg_value
= 154;
3053 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3054 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3056 deemph_reg_value
= 64;
3057 margin_reg_value
= 104;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3060 deemph_reg_value
= 64;
3061 margin_reg_value
= 154;
3067 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3068 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3070 deemph_reg_value
= 43;
3071 margin_reg_value
= 154;
3081 mutex_lock(&dev_priv
->dpio_lock
);
3083 /* Clear calc init */
3084 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3085 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3086 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3088 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3089 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3090 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3092 /* Program swing deemph */
3093 for (i
= 0; i
< 4; i
++) {
3094 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3095 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3096 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3097 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3100 /* Program swing margin */
3101 for (i
= 0; i
< 4; i
++) {
3102 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3103 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3104 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3105 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3108 /* Disable unique transition scale */
3109 for (i
= 0; i
< 4; i
++) {
3110 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3111 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3112 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3115 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3116 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3117 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3118 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3121 * The document said it needs to set bit 27 for ch0 and bit 26
3122 * for ch1. Might be a typo in the doc.
3123 * For now, for this unique transition scale selection, set bit
3124 * 27 for ch0 and ch1.
3126 for (i
= 0; i
< 4; i
++) {
3127 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3128 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3129 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3132 for (i
= 0; i
< 4; i
++) {
3133 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3134 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3135 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3136 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3140 /* Start swing calculation */
3141 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3142 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3143 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3145 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3146 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3147 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3150 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3151 val
|= DPIO_LRC_BYPASS
;
3152 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3154 mutex_unlock(&dev_priv
->dpio_lock
);
3160 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3161 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3166 uint8_t voltage_max
;
3167 uint8_t preemph_max
;
3169 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3170 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3171 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3179 voltage_max
= intel_dp_voltage_max(intel_dp
);
3180 if (v
>= voltage_max
)
3181 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3183 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3184 if (p
>= preemph_max
)
3185 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3187 for (lane
= 0; lane
< 4; lane
++)
3188 intel_dp
->train_set
[lane
] = v
| p
;
3192 intel_gen4_signal_levels(uint8_t train_set
)
3194 uint32_t signal_levels
= 0;
3196 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3199 signal_levels
|= DP_VOLTAGE_0_4
;
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3202 signal_levels
|= DP_VOLTAGE_0_6
;
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3205 signal_levels
|= DP_VOLTAGE_0_8
;
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3208 signal_levels
|= DP_VOLTAGE_1_2
;
3211 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3212 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3214 signal_levels
|= DP_PRE_EMPHASIS_0
;
3216 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3217 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3219 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3220 signal_levels
|= DP_PRE_EMPHASIS_6
;
3222 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3223 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3226 return signal_levels
;
3229 /* Gen6's DP voltage swing and pre-emphasis control */
3231 intel_gen6_edp_signal_levels(uint8_t train_set
)
3233 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3234 DP_TRAIN_PRE_EMPHASIS_MASK
);
3235 switch (signal_levels
) {
3236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3238 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3240 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3243 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3246 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3249 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3251 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3252 "0x%x\n", signal_levels
);
3253 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3257 /* Gen7's DP voltage swing and pre-emphasis control */
3259 intel_gen7_edp_signal_levels(uint8_t train_set
)
3261 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3262 DP_TRAIN_PRE_EMPHASIS_MASK
);
3263 switch (signal_levels
) {
3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3265 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3267 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3268 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3269 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3272 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3274 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3277 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3279 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3282 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3283 "0x%x\n", signal_levels
);
3284 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3288 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3290 intel_hsw_signal_levels(uint8_t train_set
)
3292 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3293 DP_TRAIN_PRE_EMPHASIS_MASK
);
3294 switch (signal_levels
) {
3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3296 return DDI_BUF_TRANS_SELECT(0);
3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3298 return DDI_BUF_TRANS_SELECT(1);
3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3300 return DDI_BUF_TRANS_SELECT(2);
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3302 return DDI_BUF_TRANS_SELECT(3);
3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3305 return DDI_BUF_TRANS_SELECT(4);
3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3307 return DDI_BUF_TRANS_SELECT(5);
3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3309 return DDI_BUF_TRANS_SELECT(6);
3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3312 return DDI_BUF_TRANS_SELECT(7);
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3314 return DDI_BUF_TRANS_SELECT(8);
3316 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3317 "0x%x\n", signal_levels
);
3318 return DDI_BUF_TRANS_SELECT(0);
3322 /* Properly updates "DP" with the correct signal levels. */
3324 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3326 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3327 enum port port
= intel_dig_port
->port
;
3328 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3329 uint32_t signal_levels
, mask
;
3330 uint8_t train_set
= intel_dp
->train_set
[0];
3332 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3333 signal_levels
= intel_hsw_signal_levels(train_set
);
3334 mask
= DDI_BUF_EMP_MASK
;
3335 } else if (IS_CHERRYVIEW(dev
)) {
3336 signal_levels
= intel_chv_signal_levels(intel_dp
);
3338 } else if (IS_VALLEYVIEW(dev
)) {
3339 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3341 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3342 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3343 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3344 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3345 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3346 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3348 signal_levels
= intel_gen4_signal_levels(train_set
);
3349 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3352 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3354 *DP
= (*DP
& ~mask
) | signal_levels
;
3358 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3360 uint8_t dp_train_pat
)
3362 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3363 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3365 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3368 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3370 I915_WRITE(intel_dp
->output_reg
, *DP
);
3371 POSTING_READ(intel_dp
->output_reg
);
3373 buf
[0] = dp_train_pat
;
3374 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3375 DP_TRAINING_PATTERN_DISABLE
) {
3376 /* don't write DP_TRAINING_LANEx_SET on disable */
3379 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3380 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3381 len
= intel_dp
->lane_count
+ 1;
3384 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3391 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3392 uint8_t dp_train_pat
)
3394 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3395 intel_dp_set_signal_levels(intel_dp
, DP
);
3396 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3400 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3401 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3403 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3404 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3408 intel_get_adjust_train(intel_dp
, link_status
);
3409 intel_dp_set_signal_levels(intel_dp
, DP
);
3411 I915_WRITE(intel_dp
->output_reg
, *DP
);
3412 POSTING_READ(intel_dp
->output_reg
);
3414 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3415 intel_dp
->train_set
, intel_dp
->lane_count
);
3417 return ret
== intel_dp
->lane_count
;
3420 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3422 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3423 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3425 enum port port
= intel_dig_port
->port
;
3431 val
= I915_READ(DP_TP_CTL(port
));
3432 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3433 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3434 I915_WRITE(DP_TP_CTL(port
), val
);
3437 * On PORT_A we can have only eDP in SST mode. There the only reason
3438 * we need to set idle transmission mode is to work around a HW issue
3439 * where we enable the pipe while not in idle link-training mode.
3440 * In this case there is requirement to wait for a minimum number of
3441 * idle patterns to be sent.
3446 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3448 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3451 /* Enable corresponding port and start training pattern 1 */
3453 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3455 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3456 struct drm_device
*dev
= encoder
->dev
;
3459 int voltage_tries
, loop_tries
;
3460 uint32_t DP
= intel_dp
->DP
;
3461 uint8_t link_config
[2];
3464 intel_ddi_prepare_link_retrain(encoder
);
3466 /* Write the link configuration data */
3467 link_config
[0] = intel_dp
->link_bw
;
3468 link_config
[1] = intel_dp
->lane_count
;
3469 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3470 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3471 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3474 link_config
[1] = DP_SET_ANSI_8B10B
;
3475 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3479 /* clock recovery */
3480 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3481 DP_TRAINING_PATTERN_1
|
3482 DP_LINK_SCRAMBLING_DISABLE
)) {
3483 DRM_ERROR("failed to enable link training\n");
3491 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3493 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3494 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3495 DRM_ERROR("failed to get link status\n");
3499 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3500 DRM_DEBUG_KMS("clock recovery OK\n");
3504 /* Check to see if we've tried the max voltage */
3505 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3506 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3508 if (i
== intel_dp
->lane_count
) {
3510 if (loop_tries
== 5) {
3511 DRM_ERROR("too many full retries, give up\n");
3514 intel_dp_reset_link_train(intel_dp
, &DP
,
3515 DP_TRAINING_PATTERN_1
|
3516 DP_LINK_SCRAMBLING_DISABLE
);
3521 /* Check to see if we've tried the same voltage 5 times */
3522 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3524 if (voltage_tries
== 5) {
3525 DRM_ERROR("too many voltage retries, give up\n");
3530 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3532 /* Update training set as requested by target */
3533 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3534 DRM_ERROR("failed to update link training\n");
3543 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3545 bool channel_eq
= false;
3546 int tries
, cr_tries
;
3547 uint32_t DP
= intel_dp
->DP
;
3548 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3550 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3551 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3552 training_pattern
= DP_TRAINING_PATTERN_3
;
3554 /* channel equalization */
3555 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3557 DP_LINK_SCRAMBLING_DISABLE
)) {
3558 DRM_ERROR("failed to start channel equalization\n");
3566 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3569 DRM_ERROR("failed to train DP, aborting\n");
3573 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3574 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3575 DRM_ERROR("failed to get link status\n");
3579 /* Make sure clock is still ok */
3580 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3581 intel_dp_start_link_train(intel_dp
);
3582 intel_dp_set_link_train(intel_dp
, &DP
,
3584 DP_LINK_SCRAMBLING_DISABLE
);
3589 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3594 /* Try 5 times, then try clock recovery if that fails */
3596 intel_dp_link_down(intel_dp
);
3597 intel_dp_start_link_train(intel_dp
);
3598 intel_dp_set_link_train(intel_dp
, &DP
,
3600 DP_LINK_SCRAMBLING_DISABLE
);
3606 /* Update training set as requested by target */
3607 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3608 DRM_ERROR("failed to update link training\n");
3614 intel_dp_set_idle_link_train(intel_dp
);
3619 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3623 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3625 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3626 DP_TRAINING_PATTERN_DISABLE
);
3630 intel_dp_link_down(struct intel_dp
*intel_dp
)
3632 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3633 enum port port
= intel_dig_port
->port
;
3634 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3636 struct intel_crtc
*intel_crtc
=
3637 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3638 uint32_t DP
= intel_dp
->DP
;
3640 if (WARN_ON(HAS_DDI(dev
)))
3643 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3646 DRM_DEBUG_KMS("\n");
3648 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3649 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3650 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3652 if (IS_CHERRYVIEW(dev
))
3653 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3655 DP
&= ~DP_LINK_TRAIN_MASK
;
3656 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3658 POSTING_READ(intel_dp
->output_reg
);
3660 if (HAS_PCH_IBX(dev
) &&
3661 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3662 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3664 /* Hardware workaround: leaving our transcoder select
3665 * set to transcoder B while it's off will prevent the
3666 * corresponding HDMI output on transcoder A.
3668 * Combine this with another hardware workaround:
3669 * transcoder select bit can only be cleared while the
3672 DP
&= ~DP_PIPEB_SELECT
;
3673 I915_WRITE(intel_dp
->output_reg
, DP
);
3675 /* Changes to enable or select take place the vblank
3676 * after being written.
3678 if (WARN_ON(crtc
== NULL
)) {
3679 /* We should never try to disable a port without a crtc
3680 * attached. For paranoia keep the code around for a
3682 POSTING_READ(intel_dp
->output_reg
);
3685 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3688 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3689 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3690 POSTING_READ(intel_dp
->output_reg
);
3691 msleep(intel_dp
->panel_power_down_delay
);
3695 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3697 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3698 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3701 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3702 sizeof(intel_dp
->dpcd
)) < 0)
3703 return false; /* aux transfer failed */
3705 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3707 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3708 return false; /* DPCD not present */
3710 /* Check if the panel supports PSR */
3711 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3712 if (is_edp(intel_dp
)) {
3713 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3715 sizeof(intel_dp
->psr_dpcd
));
3716 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3717 dev_priv
->psr
.sink_support
= true;
3718 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3722 /* Training Pattern 3 support */
3723 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3724 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3725 intel_dp
->use_tps3
= true;
3726 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3728 intel_dp
->use_tps3
= false;
3730 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3731 DP_DWN_STRM_PORT_PRESENT
))
3732 return true; /* native DP sink */
3734 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3735 return true; /* no per-port downstream info */
3737 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3738 intel_dp
->downstream_ports
,
3739 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3740 return false; /* downstream port status fetch failed */
3746 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3750 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3753 intel_edp_panel_vdd_on(intel_dp
);
3755 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3756 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3757 buf
[0], buf
[1], buf
[2]);
3759 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3760 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3761 buf
[0], buf
[1], buf
[2]);
3763 intel_edp_panel_vdd_off(intel_dp
, false);
3767 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3771 if (!intel_dp
->can_mst
)
3774 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3777 intel_edp_panel_vdd_on(intel_dp
);
3778 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3779 if (buf
[0] & DP_MST_CAP
) {
3780 DRM_DEBUG_KMS("Sink is MST capable\n");
3781 intel_dp
->is_mst
= true;
3783 DRM_DEBUG_KMS("Sink is not MST capable\n");
3784 intel_dp
->is_mst
= false;
3787 intel_edp_panel_vdd_off(intel_dp
, false);
3789 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3790 return intel_dp
->is_mst
;
3793 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3795 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3796 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3797 struct intel_crtc
*intel_crtc
=
3798 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3801 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3804 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3807 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3808 DP_TEST_SINK_START
) < 0)
3811 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3812 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3813 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3815 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3818 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3823 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3825 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3826 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3827 sink_irq_vector
, 1) == 1;
3831 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3835 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3837 sink_irq_vector
, 14);
3845 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3847 /* NAK by default */
3848 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3852 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3856 if (intel_dp
->is_mst
) {
3861 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3865 /* check link status - esi[10] = 0x200c */
3866 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3867 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3868 intel_dp_start_link_train(intel_dp
);
3869 intel_dp_complete_link_train(intel_dp
);
3870 intel_dp_stop_link_train(intel_dp
);
3873 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3874 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3877 for (retry
= 0; retry
< 3; retry
++) {
3879 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3880 DP_SINK_COUNT_ESI
+1,
3887 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3889 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3897 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3898 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3899 intel_dp
->is_mst
= false;
3900 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3901 /* send a hotplug event */
3902 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3909 * According to DP spec
3912 * 2. Configure link according to Receiver Capabilities
3913 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3914 * 4. Check link status on receipt of hot-plug interrupt
3917 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3919 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3920 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3922 u8 link_status
[DP_LINK_STATUS_SIZE
];
3924 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3926 if (!intel_encoder
->connectors_active
)
3929 if (WARN_ON(!intel_encoder
->base
.crtc
))
3932 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3935 /* Try to read receiver status if the link appears to be up */
3936 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3940 /* Now read the DPCD to see if it's actually running */
3941 if (!intel_dp_get_dpcd(intel_dp
)) {
3945 /* Try to read the source of the interrupt */
3946 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3947 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3948 /* Clear interrupt source */
3949 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3950 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3953 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3954 intel_dp_handle_test_request(intel_dp
);
3955 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3956 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3959 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3960 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3961 intel_encoder
->base
.name
);
3962 intel_dp_start_link_train(intel_dp
);
3963 intel_dp_complete_link_train(intel_dp
);
3964 intel_dp_stop_link_train(intel_dp
);
3968 /* XXX this is probably wrong for multiple downstream ports */
3969 static enum drm_connector_status
3970 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3972 uint8_t *dpcd
= intel_dp
->dpcd
;
3975 if (!intel_dp_get_dpcd(intel_dp
))
3976 return connector_status_disconnected
;
3978 /* if there's no downstream port, we're done */
3979 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3980 return connector_status_connected
;
3982 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3983 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3984 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3987 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3989 return connector_status_unknown
;
3991 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3992 : connector_status_disconnected
;
3995 /* If no HPD, poke DDC gently */
3996 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3997 return connector_status_connected
;
3999 /* Well we tried, say unknown for unreliable port types */
4000 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4001 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4002 if (type
== DP_DS_PORT_TYPE_VGA
||
4003 type
== DP_DS_PORT_TYPE_NON_EDID
)
4004 return connector_status_unknown
;
4006 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4007 DP_DWN_STRM_PORT_TYPE_MASK
;
4008 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4009 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4010 return connector_status_unknown
;
4013 /* Anything else is out of spec, warn and ignore */
4014 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4015 return connector_status_disconnected
;
4018 static enum drm_connector_status
4019 edp_detect(struct intel_dp
*intel_dp
)
4021 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4022 enum drm_connector_status status
;
4024 status
= intel_panel_detect(dev
);
4025 if (status
== connector_status_unknown
)
4026 status
= connector_status_connected
;
4031 static enum drm_connector_status
4032 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4034 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4036 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4038 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4039 return connector_status_disconnected
;
4041 return intel_dp_detect_dpcd(intel_dp
);
4044 static int g4x_digital_port_connected(struct drm_device
*dev
,
4045 struct intel_digital_port
*intel_dig_port
)
4047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4050 if (IS_VALLEYVIEW(dev
)) {
4051 switch (intel_dig_port
->port
) {
4053 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4056 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4059 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4065 switch (intel_dig_port
->port
) {
4067 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4070 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4073 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4080 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4085 static enum drm_connector_status
4086 g4x_dp_detect(struct intel_dp
*intel_dp
)
4088 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4089 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4092 /* Can't disconnect eDP, but you can close the lid... */
4093 if (is_edp(intel_dp
)) {
4094 enum drm_connector_status status
;
4096 status
= intel_panel_detect(dev
);
4097 if (status
== connector_status_unknown
)
4098 status
= connector_status_connected
;
4102 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4104 return connector_status_unknown
;
4106 return connector_status_disconnected
;
4108 return intel_dp_detect_dpcd(intel_dp
);
4111 static struct edid
*
4112 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4114 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4116 /* use cached edid if we have one */
4117 if (intel_connector
->edid
) {
4119 if (IS_ERR(intel_connector
->edid
))
4122 return drm_edid_duplicate(intel_connector
->edid
);
4124 return drm_get_edid(&intel_connector
->base
,
4125 &intel_dp
->aux
.ddc
);
4129 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4131 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4134 edid
= intel_dp_get_edid(intel_dp
);
4135 intel_connector
->detect_edid
= edid
;
4137 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4138 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4140 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4144 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4146 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4148 kfree(intel_connector
->detect_edid
);
4149 intel_connector
->detect_edid
= NULL
;
4151 intel_dp
->has_audio
= false;
4154 static enum intel_display_power_domain
4155 intel_dp_power_get(struct intel_dp
*dp
)
4157 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4158 enum intel_display_power_domain power_domain
;
4160 power_domain
= intel_display_port_power_domain(encoder
);
4161 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4163 return power_domain
;
4167 intel_dp_power_put(struct intel_dp
*dp
,
4168 enum intel_display_power_domain power_domain
)
4170 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4171 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4174 static enum drm_connector_status
4175 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4177 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4178 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4179 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4180 struct drm_device
*dev
= connector
->dev
;
4181 enum drm_connector_status status
;
4182 enum intel_display_power_domain power_domain
;
4185 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4186 connector
->base
.id
, connector
->name
);
4187 intel_dp_unset_edid(intel_dp
);
4189 if (intel_dp
->is_mst
) {
4190 /* MST devices are disconnected from a monitor POV */
4191 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4192 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4193 return connector_status_disconnected
;
4196 power_domain
= intel_dp_power_get(intel_dp
);
4198 /* Can't disconnect eDP, but you can close the lid... */
4199 if (is_edp(intel_dp
))
4200 status
= edp_detect(intel_dp
);
4201 else if (HAS_PCH_SPLIT(dev
))
4202 status
= ironlake_dp_detect(intel_dp
);
4204 status
= g4x_dp_detect(intel_dp
);
4205 if (status
!= connector_status_connected
)
4208 intel_dp_probe_oui(intel_dp
);
4210 ret
= intel_dp_probe_mst(intel_dp
);
4212 /* if we are in MST mode then this connector
4213 won't appear connected or have anything with EDID on it */
4214 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4215 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4216 status
= connector_status_disconnected
;
4220 intel_dp_set_edid(intel_dp
);
4222 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4223 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4224 status
= connector_status_connected
;
4227 intel_dp_power_put(intel_dp
, power_domain
);
4232 intel_dp_force(struct drm_connector
*connector
)
4234 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4235 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4236 enum intel_display_power_domain power_domain
;
4238 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4239 connector
->base
.id
, connector
->name
);
4240 intel_dp_unset_edid(intel_dp
);
4242 if (connector
->status
!= connector_status_connected
)
4245 power_domain
= intel_dp_power_get(intel_dp
);
4247 intel_dp_set_edid(intel_dp
);
4249 intel_dp_power_put(intel_dp
, power_domain
);
4251 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4252 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4255 static int intel_dp_get_modes(struct drm_connector
*connector
)
4257 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4260 edid
= intel_connector
->detect_edid
;
4262 int ret
= intel_connector_update_modes(connector
, edid
);
4267 /* if eDP has no EDID, fall back to fixed mode */
4268 if (is_edp(intel_attached_dp(connector
)) &&
4269 intel_connector
->panel
.fixed_mode
) {
4270 struct drm_display_mode
*mode
;
4272 mode
= drm_mode_duplicate(connector
->dev
,
4273 intel_connector
->panel
.fixed_mode
);
4275 drm_mode_probed_add(connector
, mode
);
4284 intel_dp_detect_audio(struct drm_connector
*connector
)
4286 bool has_audio
= false;
4289 edid
= to_intel_connector(connector
)->detect_edid
;
4291 has_audio
= drm_detect_monitor_audio(edid
);
4297 intel_dp_set_property(struct drm_connector
*connector
,
4298 struct drm_property
*property
,
4301 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4302 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4303 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4304 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4307 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4311 if (property
== dev_priv
->force_audio_property
) {
4315 if (i
== intel_dp
->force_audio
)
4318 intel_dp
->force_audio
= i
;
4320 if (i
== HDMI_AUDIO_AUTO
)
4321 has_audio
= intel_dp_detect_audio(connector
);
4323 has_audio
= (i
== HDMI_AUDIO_ON
);
4325 if (has_audio
== intel_dp
->has_audio
)
4328 intel_dp
->has_audio
= has_audio
;
4332 if (property
== dev_priv
->broadcast_rgb_property
) {
4333 bool old_auto
= intel_dp
->color_range_auto
;
4334 uint32_t old_range
= intel_dp
->color_range
;
4337 case INTEL_BROADCAST_RGB_AUTO
:
4338 intel_dp
->color_range_auto
= true;
4340 case INTEL_BROADCAST_RGB_FULL
:
4341 intel_dp
->color_range_auto
= false;
4342 intel_dp
->color_range
= 0;
4344 case INTEL_BROADCAST_RGB_LIMITED
:
4345 intel_dp
->color_range_auto
= false;
4346 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4352 if (old_auto
== intel_dp
->color_range_auto
&&
4353 old_range
== intel_dp
->color_range
)
4359 if (is_edp(intel_dp
) &&
4360 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4361 if (val
== DRM_MODE_SCALE_NONE
) {
4362 DRM_DEBUG_KMS("no scaling not supported\n");
4366 if (intel_connector
->panel
.fitting_mode
== val
) {
4367 /* the eDP scaling property is not changed */
4370 intel_connector
->panel
.fitting_mode
= val
;
4378 if (intel_encoder
->base
.crtc
)
4379 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4385 intel_dp_connector_destroy(struct drm_connector
*connector
)
4387 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4389 kfree(intel_connector
->detect_edid
);
4391 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4392 kfree(intel_connector
->edid
);
4394 /* Can't call is_edp() since the encoder may have been destroyed
4396 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4397 intel_panel_fini(&intel_connector
->panel
);
4399 drm_connector_cleanup(connector
);
4403 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4405 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4406 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4408 drm_dp_aux_unregister(&intel_dp
->aux
);
4409 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4410 drm_encoder_cleanup(encoder
);
4411 if (is_edp(intel_dp
)) {
4412 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4414 * vdd might still be enabled do to the delayed vdd off.
4415 * Make sure vdd is actually turned off here.
4418 edp_panel_vdd_off_sync(intel_dp
);
4419 pps_unlock(intel_dp
);
4421 if (intel_dp
->edp_notifier
.notifier_call
) {
4422 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4423 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4426 kfree(intel_dig_port
);
4429 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4431 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4433 if (!is_edp(intel_dp
))
4437 * vdd might still be enabled do to the delayed vdd off.
4438 * Make sure vdd is actually turned off here.
4441 edp_panel_vdd_off_sync(intel_dp
);
4442 pps_unlock(intel_dp
);
4445 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4447 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4450 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4451 .dpms
= intel_connector_dpms
,
4452 .detect
= intel_dp_detect
,
4453 .force
= intel_dp_force
,
4454 .fill_modes
= drm_helper_probe_single_connector_modes
,
4455 .set_property
= intel_dp_set_property
,
4456 .destroy
= intel_dp_connector_destroy
,
4459 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4460 .get_modes
= intel_dp_get_modes
,
4461 .mode_valid
= intel_dp_mode_valid
,
4462 .best_encoder
= intel_best_encoder
,
4465 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4466 .reset
= intel_dp_encoder_reset
,
4467 .destroy
= intel_dp_encoder_destroy
,
4471 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4477 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4479 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4480 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4481 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4483 enum intel_display_power_domain power_domain
;
4486 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4487 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4489 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4490 port_name(intel_dig_port
->port
),
4491 long_hpd
? "long" : "short");
4493 power_domain
= intel_display_port_power_domain(intel_encoder
);
4494 intel_display_power_get(dev_priv
, power_domain
);
4498 if (HAS_PCH_SPLIT(dev
)) {
4499 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4502 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4506 if (!intel_dp_get_dpcd(intel_dp
)) {
4510 intel_dp_probe_oui(intel_dp
);
4512 if (!intel_dp_probe_mst(intel_dp
))
4516 if (intel_dp
->is_mst
) {
4517 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4521 if (!intel_dp
->is_mst
) {
4523 * we'll check the link status via the normal hot plug path later -
4524 * but for short hpds we should check it now
4526 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4527 intel_dp_check_link_status(intel_dp
);
4528 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4534 /* if we were in MST mode, and device is not there get out of MST mode */
4535 if (intel_dp
->is_mst
) {
4536 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4537 intel_dp
->is_mst
= false;
4538 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4541 intel_display_power_put(dev_priv
, power_domain
);
4546 /* Return which DP Port should be selected for Transcoder DP control */
4548 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4550 struct drm_device
*dev
= crtc
->dev
;
4551 struct intel_encoder
*intel_encoder
;
4552 struct intel_dp
*intel_dp
;
4554 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4555 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4557 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4558 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4559 return intel_dp
->output_reg
;
4565 /* check the VBT to see whether the eDP is on DP-D port */
4566 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4569 union child_device_config
*p_child
;
4571 static const short port_mapping
[] = {
4572 [PORT_B
] = PORT_IDPB
,
4573 [PORT_C
] = PORT_IDPC
,
4574 [PORT_D
] = PORT_IDPD
,
4580 if (!dev_priv
->vbt
.child_dev_num
)
4583 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4584 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4586 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4587 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4588 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4595 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4597 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4599 intel_attach_force_audio_property(connector
);
4600 intel_attach_broadcast_rgb_property(connector
);
4601 intel_dp
->color_range_auto
= true;
4603 if (is_edp(intel_dp
)) {
4604 drm_mode_create_scaling_mode_property(connector
->dev
);
4605 drm_object_attach_property(
4607 connector
->dev
->mode_config
.scaling_mode_property
,
4608 DRM_MODE_SCALE_ASPECT
);
4609 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4613 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4615 intel_dp
->last_power_cycle
= jiffies
;
4616 intel_dp
->last_power_on
= jiffies
;
4617 intel_dp
->last_backlight_off
= jiffies
;
4621 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4622 struct intel_dp
*intel_dp
,
4623 struct edp_power_seq
*out
)
4625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4626 struct edp_power_seq cur
, vbt
, spec
, final
;
4627 u32 pp_on
, pp_off
, pp_div
, pp
;
4628 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4630 lockdep_assert_held(&dev_priv
->pps_mutex
);
4632 if (HAS_PCH_SPLIT(dev
)) {
4633 pp_ctrl_reg
= PCH_PP_CONTROL
;
4634 pp_on_reg
= PCH_PP_ON_DELAYS
;
4635 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4636 pp_div_reg
= PCH_PP_DIVISOR
;
4638 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4640 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4641 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4642 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4643 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4646 /* Workaround: Need to write PP_CONTROL with the unlock key as
4647 * the very first thing. */
4648 pp
= ironlake_get_pp_control(intel_dp
);
4649 I915_WRITE(pp_ctrl_reg
, pp
);
4651 pp_on
= I915_READ(pp_on_reg
);
4652 pp_off
= I915_READ(pp_off_reg
);
4653 pp_div
= I915_READ(pp_div_reg
);
4655 /* Pull timing values out of registers */
4656 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4657 PANEL_POWER_UP_DELAY_SHIFT
;
4659 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4660 PANEL_LIGHT_ON_DELAY_SHIFT
;
4662 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4663 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4665 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4666 PANEL_POWER_DOWN_DELAY_SHIFT
;
4668 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4669 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4671 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4672 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4674 vbt
= dev_priv
->vbt
.edp_pps
;
4676 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4677 * our hw here, which are all in 100usec. */
4678 spec
.t1_t3
= 210 * 10;
4679 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4680 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4681 spec
.t10
= 500 * 10;
4682 /* This one is special and actually in units of 100ms, but zero
4683 * based in the hw (so we need to add 100 ms). But the sw vbt
4684 * table multiplies it with 1000 to make it in units of 100usec,
4686 spec
.t11_t12
= (510 + 100) * 10;
4688 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4689 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4691 /* Use the max of the register settings and vbt. If both are
4692 * unset, fall back to the spec limits. */
4693 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4695 max(cur.field, vbt.field))
4696 assign_final(t1_t3
);
4700 assign_final(t11_t12
);
4703 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4704 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4705 intel_dp
->backlight_on_delay
= get_delay(t8
);
4706 intel_dp
->backlight_off_delay
= get_delay(t9
);
4707 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4708 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4711 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4712 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4713 intel_dp
->panel_power_cycle_delay
);
4715 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4716 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4723 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4724 struct intel_dp
*intel_dp
,
4725 struct edp_power_seq
*seq
)
4727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4728 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4729 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4730 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4731 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4733 lockdep_assert_held(&dev_priv
->pps_mutex
);
4735 if (HAS_PCH_SPLIT(dev
)) {
4736 pp_on_reg
= PCH_PP_ON_DELAYS
;
4737 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4738 pp_div_reg
= PCH_PP_DIVISOR
;
4740 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4742 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4743 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4744 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4748 * And finally store the new values in the power sequencer. The
4749 * backlight delays are set to 1 because we do manual waits on them. For
4750 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4751 * we'll end up waiting for the backlight off delay twice: once when we
4752 * do the manual sleep, and once when we disable the panel and wait for
4753 * the PP_STATUS bit to become zero.
4755 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4756 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4757 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4758 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4759 /* Compute the divisor for the pp clock, simply match the Bspec
4761 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4762 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4763 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4765 /* Haswell doesn't have any port selection bits for the panel
4766 * power sequencer any more. */
4767 if (IS_VALLEYVIEW(dev
)) {
4768 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4769 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4771 port_sel
= PANEL_PORT_SELECT_DPA
;
4773 port_sel
= PANEL_PORT_SELECT_DPD
;
4778 I915_WRITE(pp_on_reg
, pp_on
);
4779 I915_WRITE(pp_off_reg
, pp_off
);
4780 I915_WRITE(pp_div_reg
, pp_div
);
4782 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4783 I915_READ(pp_on_reg
),
4784 I915_READ(pp_off_reg
),
4785 I915_READ(pp_div_reg
));
4788 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4791 struct intel_encoder
*encoder
;
4792 struct intel_dp
*intel_dp
= NULL
;
4793 struct intel_crtc_config
*config
= NULL
;
4794 struct intel_crtc
*intel_crtc
= NULL
;
4795 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4797 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4799 if (refresh_rate
<= 0) {
4800 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4804 if (intel_connector
== NULL
) {
4805 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4810 * FIXME: This needs proper synchronization with psr state. But really
4811 * hard to tell without seeing the user of this function of this code.
4812 * Check locking and ordering once that lands.
4814 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4815 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4819 encoder
= intel_attached_encoder(&intel_connector
->base
);
4820 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4821 intel_crtc
= encoder
->new_crtc
;
4824 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4828 config
= &intel_crtc
->config
;
4830 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4831 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4835 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4836 index
= DRRS_LOW_RR
;
4838 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4840 "DRRS requested for previously set RR...ignoring\n");
4844 if (!intel_crtc
->active
) {
4845 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4849 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4850 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4851 val
= I915_READ(reg
);
4852 if (index
> DRRS_HIGH_RR
) {
4853 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4854 intel_dp_set_m_n(intel_crtc
);
4856 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4858 I915_WRITE(reg
, val
);
4862 * mutex taken to ensure that there is no race between differnt
4863 * drrs calls trying to update refresh rate. This scenario may occur
4864 * in future when idleness detection based DRRS in kernel and
4865 * possible calls from user space to set differnt RR are made.
4868 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4870 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4872 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4874 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4877 static struct drm_display_mode
*
4878 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4879 struct intel_connector
*intel_connector
,
4880 struct drm_display_mode
*fixed_mode
)
4882 struct drm_connector
*connector
= &intel_connector
->base
;
4883 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4884 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4886 struct drm_display_mode
*downclock_mode
= NULL
;
4888 if (INTEL_INFO(dev
)->gen
<= 6) {
4889 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4893 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4894 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4898 downclock_mode
= intel_find_panel_downclock
4899 (dev
, fixed_mode
, connector
);
4901 if (!downclock_mode
) {
4902 DRM_DEBUG_KMS("DRRS not supported\n");
4906 dev_priv
->drrs
.connector
= intel_connector
;
4908 mutex_init(&intel_dp
->drrs_state
.mutex
);
4910 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4912 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4913 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4914 return downclock_mode
;
4917 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
4919 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4921 struct intel_dp
*intel_dp
;
4922 enum intel_display_power_domain power_domain
;
4924 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4927 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4931 if (!edp_have_panel_vdd(intel_dp
))
4934 * The VDD bit needs a power domain reference, so if the bit is
4935 * already enabled when we boot or resume, grab this reference and
4936 * schedule a vdd off, so we don't hold on to the reference
4939 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4940 power_domain
= intel_display_port_power_domain(intel_encoder
);
4941 intel_display_power_get(dev_priv
, power_domain
);
4943 edp_panel_vdd_schedule_off(intel_dp
);
4945 pps_unlock(intel_dp
);
4948 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4949 struct intel_connector
*intel_connector
,
4950 struct edp_power_seq
*power_seq
)
4952 struct drm_connector
*connector
= &intel_connector
->base
;
4953 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4954 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4955 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4957 struct drm_display_mode
*fixed_mode
= NULL
;
4958 struct drm_display_mode
*downclock_mode
= NULL
;
4960 struct drm_display_mode
*scan
;
4963 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4965 if (!is_edp(intel_dp
))
4968 intel_edp_panel_vdd_sanitize(intel_encoder
);
4970 /* Cache DPCD and EDID for edp. */
4971 intel_edp_panel_vdd_on(intel_dp
);
4972 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4973 intel_edp_panel_vdd_off(intel_dp
, false);
4976 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4977 dev_priv
->no_aux_handshake
=
4978 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4979 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4981 /* if this fails, presume the device is a ghost */
4982 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4986 /* We now know it's not a ghost, init power sequence regs. */
4988 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4989 pps_unlock(intel_dp
);
4991 mutex_lock(&dev
->mode_config
.mutex
);
4992 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4994 if (drm_add_edid_modes(connector
, edid
)) {
4995 drm_mode_connector_update_edid_property(connector
,
4997 drm_edid_to_eld(connector
, edid
);
5000 edid
= ERR_PTR(-EINVAL
);
5003 edid
= ERR_PTR(-ENOENT
);
5005 intel_connector
->edid
= edid
;
5007 /* prefer fixed mode from EDID if available */
5008 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5009 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5010 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5011 downclock_mode
= intel_dp_drrs_init(
5013 intel_connector
, fixed_mode
);
5018 /* fallback to VBT if available for eDP */
5019 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5020 fixed_mode
= drm_mode_duplicate(dev
,
5021 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5023 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5025 mutex_unlock(&dev
->mode_config
.mutex
);
5027 if (IS_VALLEYVIEW(dev
)) {
5028 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5029 register_reboot_notifier(&intel_dp
->edp_notifier
);
5032 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5033 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5034 intel_panel_setup_backlight(connector
);
5040 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5041 struct intel_connector
*intel_connector
)
5043 struct drm_connector
*connector
= &intel_connector
->base
;
5044 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5045 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5046 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5048 enum port port
= intel_dig_port
->port
;
5049 struct edp_power_seq power_seq
= { 0 };
5052 intel_dp
->pps_pipe
= INVALID_PIPE
;
5054 /* intel_dp vfuncs */
5055 if (IS_VALLEYVIEW(dev
))
5056 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5057 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5058 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5059 else if (HAS_PCH_SPLIT(dev
))
5060 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5062 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5064 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5066 /* Preserve the current hw state. */
5067 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5068 intel_dp
->attached_connector
= intel_connector
;
5070 if (intel_dp_is_edp(dev
, port
))
5071 type
= DRM_MODE_CONNECTOR_eDP
;
5073 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5076 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5077 * for DP the encoder type can be set by the caller to
5078 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5080 if (type
== DRM_MODE_CONNECTOR_eDP
)
5081 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5083 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5084 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5087 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5088 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5090 connector
->interlace_allowed
= true;
5091 connector
->doublescan_allowed
= 0;
5093 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5094 edp_panel_vdd_work
);
5096 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5097 drm_connector_register(connector
);
5100 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5102 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5103 intel_connector
->unregister
= intel_dp_connector_unregister
;
5105 /* Set up the hotplug pin. */
5108 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5111 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5114 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5117 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5123 if (is_edp(intel_dp
)) {
5125 if (IS_VALLEYVIEW(dev
)) {
5126 vlv_initial_power_sequencer_setup(intel_dp
);
5128 intel_dp_init_panel_power_timestamps(intel_dp
);
5129 intel_dp_init_panel_power_sequencer(dev
, intel_dp
,
5132 pps_unlock(intel_dp
);
5135 intel_dp_aux_init(intel_dp
, intel_connector
);
5137 /* init MST on ports that can support it */
5138 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5139 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5140 intel_dp_mst_encoder_init(intel_dig_port
,
5141 intel_connector
->base
.base
.id
);
5145 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
5146 drm_dp_aux_unregister(&intel_dp
->aux
);
5147 if (is_edp(intel_dp
)) {
5148 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5150 * vdd might still be enabled do to the delayed vdd off.
5151 * Make sure vdd is actually turned off here.
5154 edp_panel_vdd_off_sync(intel_dp
);
5155 pps_unlock(intel_dp
);
5157 drm_connector_unregister(connector
);
5158 drm_connector_cleanup(connector
);
5162 intel_dp_add_properties(intel_dp
, connector
);
5164 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5165 * 0xd. Failure to do so will result in spurious interrupts being
5166 * generated on the port when a cable is not attached.
5168 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5169 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5170 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5177 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5180 struct intel_digital_port
*intel_dig_port
;
5181 struct intel_encoder
*intel_encoder
;
5182 struct drm_encoder
*encoder
;
5183 struct intel_connector
*intel_connector
;
5185 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5186 if (!intel_dig_port
)
5189 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5190 if (!intel_connector
) {
5191 kfree(intel_dig_port
);
5195 intel_encoder
= &intel_dig_port
->base
;
5196 encoder
= &intel_encoder
->base
;
5198 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5199 DRM_MODE_ENCODER_TMDS
);
5201 intel_encoder
->compute_config
= intel_dp_compute_config
;
5202 intel_encoder
->disable
= intel_disable_dp
;
5203 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5204 intel_encoder
->get_config
= intel_dp_get_config
;
5205 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5206 if (IS_CHERRYVIEW(dev
)) {
5207 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5208 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5209 intel_encoder
->enable
= vlv_enable_dp
;
5210 intel_encoder
->post_disable
= chv_post_disable_dp
;
5211 } else if (IS_VALLEYVIEW(dev
)) {
5212 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5213 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5214 intel_encoder
->enable
= vlv_enable_dp
;
5215 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5217 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5218 intel_encoder
->enable
= g4x_enable_dp
;
5219 if (INTEL_INFO(dev
)->gen
>= 5)
5220 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5223 intel_dig_port
->port
= port
;
5224 intel_dig_port
->dp
.output_reg
= output_reg
;
5226 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5227 if (IS_CHERRYVIEW(dev
)) {
5229 intel_encoder
->crtc_mask
= 1 << 2;
5231 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5233 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5235 intel_encoder
->cloneable
= 0;
5236 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5238 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5239 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5241 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5242 drm_encoder_cleanup(encoder
);
5243 kfree(intel_dig_port
);
5244 kfree(intel_connector
);
5248 void intel_dp_mst_suspend(struct drm_device
*dev
)
5250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5254 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5255 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5256 if (!intel_dig_port
)
5259 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5260 if (!intel_dig_port
->dp
.can_mst
)
5262 if (intel_dig_port
->dp
.is_mst
)
5263 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5268 void intel_dp_mst_resume(struct drm_device
*dev
)
5270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5273 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5274 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5275 if (!intel_dig_port
)
5277 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5280 if (!intel_dig_port
->dp
.can_mst
)
5283 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5285 intel_dp_check_mst_status(&intel_dig_port
->dp
);