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drm/i915: Run psr_setup unconditionally
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44 };
45
46 static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51 };
52
53 static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58 };
59
60 static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65 };
66
67 /*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71 static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83 };
84
85 /**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92 static bool is_edp(struct intel_dp *intel_dp)
93 {
94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
97 }
98
99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
100 {
101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
104 }
105
106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107 {
108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
109 }
110
111 static void intel_dp_link_down(struct intel_dp *intel_dp);
112 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
113 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
114
115 static int
116 intel_dp_max_link_bw(struct intel_dp *intel_dp)
117 {
118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
127 INTEL_INFO(dev)->gen >= 8) &&
128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
129 max_link_bw = DP_LINK_BW_5_4;
130 else
131 max_link_bw = DP_LINK_BW_2_7;
132 break;
133 default:
134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw);
136 max_link_bw = DP_LINK_BW_1_62;
137 break;
138 }
139 return max_link_bw;
140 }
141
142 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
143 {
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 struct drm_device *dev = intel_dig_port->base.base.dev;
146 u8 source_max, sink_max;
147
148 source_max = 4;
149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
151 source_max = 2;
152
153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
154
155 return min(source_max, sink_max);
156 }
157
158 /*
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
161 *
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
163 *
164 * 270000 * 1 * 8 / 10 == 216000
165 *
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
170 *
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
173 */
174
175 static int
176 intel_dp_link_required(int pixel_clock, int bpp)
177 {
178 return (pixel_clock * bpp + 9) / 10;
179 }
180
181 static int
182 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
183 {
184 return (max_link_clock * max_lanes * 8) / 10;
185 }
186
187 static enum drm_mode_status
188 intel_dp_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
190 {
191 struct intel_dp *intel_dp = intel_attached_dp(connector);
192 struct intel_connector *intel_connector = to_intel_connector(connector);
193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
194 int target_clock = mode->clock;
195 int max_rate, mode_rate, max_lanes, max_link_clock;
196
197 if (is_edp(intel_dp) && fixed_mode) {
198 if (mode->hdisplay > fixed_mode->hdisplay)
199 return MODE_PANEL;
200
201 if (mode->vdisplay > fixed_mode->vdisplay)
202 return MODE_PANEL;
203
204 target_clock = fixed_mode->clock;
205 }
206
207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
208 max_lanes = intel_dp_max_lane_count(intel_dp);
209
210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
211 mode_rate = intel_dp_link_required(target_clock, 18);
212
213 if (mode_rate > max_rate)
214 return MODE_CLOCK_HIGH;
215
216 if (mode->clock < 10000)
217 return MODE_CLOCK_LOW;
218
219 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
220 return MODE_H_ILLEGAL;
221
222 return MODE_OK;
223 }
224
225 static uint32_t
226 pack_aux(uint8_t *src, int src_bytes)
227 {
228 int i;
229 uint32_t v = 0;
230
231 if (src_bytes > 4)
232 src_bytes = 4;
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
235 return v;
236 }
237
238 static void
239 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
240 {
241 int i;
242 if (dst_bytes > 4)
243 dst_bytes = 4;
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
246 }
247
248 /* hrawclock is 1/4 the FSB frequency */
249 static int
250 intel_hrawclk(struct drm_device *dev)
251 {
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 uint32_t clkcfg;
254
255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
256 if (IS_VALLEYVIEW(dev))
257 return 200;
258
259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280 }
281
282 static void
283 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
284 struct intel_dp *intel_dp,
285 struct edp_power_seq *out);
286 static void
287 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
288 struct intel_dp *intel_dp,
289 struct edp_power_seq *out);
290
291 static enum pipe
292 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
293 {
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum port port = intel_dig_port->port;
299 enum pipe pipe;
300
301 /* modeset should have pipe */
302 if (crtc)
303 return to_intel_crtc(crtc)->pipe;
304
305 /* init time, try to find a pipe with this port selected */
306 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
307 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
308 PANEL_PORT_SELECT_MASK;
309 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
310 return pipe;
311 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317 }
318
319 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320 {
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327 }
328
329 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330 {
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337 }
338
339 static bool edp_have_panel_power(struct intel_dp *intel_dp)
340 {
341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
342 struct drm_i915_private *dev_priv = dev->dev_private;
343
344 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
345 }
346
347 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
348 {
349 struct drm_device *dev = intel_dp_to_dev(intel_dp);
350 struct drm_i915_private *dev_priv = dev->dev_private;
351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
353 enum intel_display_power_domain power_domain;
354
355 power_domain = intel_display_port_power_domain(intel_encoder);
356 return intel_display_power_enabled(dev_priv, power_domain) &&
357 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
358 }
359
360 static void
361 intel_dp_check_edp(struct intel_dp *intel_dp)
362 {
363 struct drm_device *dev = intel_dp_to_dev(intel_dp);
364 struct drm_i915_private *dev_priv = dev->dev_private;
365
366 if (!is_edp(intel_dp))
367 return;
368
369 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
370 WARN(1, "eDP powered off while attempting aux channel communication.\n");
371 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
372 I915_READ(_pp_stat_reg(intel_dp)),
373 I915_READ(_pp_ctrl_reg(intel_dp)));
374 }
375 }
376
377 static uint32_t
378 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
379 {
380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
381 struct drm_device *dev = intel_dig_port->base.base.dev;
382 struct drm_i915_private *dev_priv = dev->dev_private;
383 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
384 uint32_t status;
385 bool done;
386
387 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
388 if (has_aux_irq)
389 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
390 msecs_to_jiffies_timeout(10));
391 else
392 done = wait_for_atomic(C, 10) == 0;
393 if (!done)
394 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
395 has_aux_irq);
396 #undef C
397
398 return status;
399 }
400
401 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
402 {
403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
404 struct drm_device *dev = intel_dig_port->base.base.dev;
405
406 /*
407 * The clock divider is based off the hrawclk, and would like to run at
408 * 2MHz. So, take the hrawclk value and divide by 2 and use that
409 */
410 return index ? 0 : intel_hrawclk(dev) / 2;
411 }
412
413 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414 {
415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
416 struct drm_device *dev = intel_dig_port->base.base.dev;
417
418 if (index)
419 return 0;
420
421 if (intel_dig_port->port == PORT_A) {
422 if (IS_GEN6(dev) || IS_GEN7(dev))
423 return 200; /* SNB & IVB eDP input clock at 400Mhz */
424 else
425 return 225; /* eDP input clock at 450Mhz */
426 } else {
427 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
428 }
429 }
430
431 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432 {
433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
434 struct drm_device *dev = intel_dig_port->base.base.dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436
437 if (intel_dig_port->port == PORT_A) {
438 if (index)
439 return 0;
440 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
441 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
442 /* Workaround for non-ULT HSW */
443 switch (index) {
444 case 0: return 63;
445 case 1: return 72;
446 default: return 0;
447 }
448 } else {
449 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
450 }
451 }
452
453 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
454 {
455 return index ? 0 : 100;
456 }
457
458 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
459 bool has_aux_irq,
460 int send_bytes,
461 uint32_t aux_clock_divider)
462 {
463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
464 struct drm_device *dev = intel_dig_port->base.base.dev;
465 uint32_t precharge, timeout;
466
467 if (IS_GEN6(dev))
468 precharge = 3;
469 else
470 precharge = 5;
471
472 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
473 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
474 else
475 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
476
477 return DP_AUX_CH_CTL_SEND_BUSY |
478 DP_AUX_CH_CTL_DONE |
479 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 timeout |
482 DP_AUX_CH_CTL_RECEIVE_ERROR |
483 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
484 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
485 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
486 }
487
488 static int
489 intel_dp_aux_ch(struct intel_dp *intel_dp,
490 uint8_t *send, int send_bytes,
491 uint8_t *recv, int recv_size)
492 {
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
497 uint32_t ch_data = ch_ctl + 4;
498 uint32_t aux_clock_divider;
499 int i, ret, recv_bytes;
500 uint32_t status;
501 int try, clock = 0;
502 bool has_aux_irq = HAS_AUX_IRQ(dev);
503 bool vdd;
504
505 vdd = _edp_panel_vdd_on(intel_dp);
506
507 /* dp aux is extremely sensitive to irq latency, hence request the
508 * lowest possible wakeup latency and so prevent the cpu from going into
509 * deep sleep states.
510 */
511 pm_qos_update_request(&dev_priv->pm_qos, 0);
512
513 intel_dp_check_edp(intel_dp);
514
515 intel_aux_display_runtime_get(dev_priv);
516
517 /* Try to wait for any previous AUX channel activity */
518 for (try = 0; try < 3; try++) {
519 status = I915_READ_NOTRACE(ch_ctl);
520 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
521 break;
522 msleep(1);
523 }
524
525 if (try == 3) {
526 WARN(1, "dp_aux_ch not started status 0x%08x\n",
527 I915_READ(ch_ctl));
528 ret = -EBUSY;
529 goto out;
530 }
531
532 /* Only 5 data registers! */
533 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
534 ret = -E2BIG;
535 goto out;
536 }
537
538 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
539 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
540 has_aux_irq,
541 send_bytes,
542 aux_clock_divider);
543
544 /* Must try at least 3 times according to DP spec */
545 for (try = 0; try < 5; try++) {
546 /* Load the send data into the aux channel data registers */
547 for (i = 0; i < send_bytes; i += 4)
548 I915_WRITE(ch_data + i,
549 pack_aux(send + i, send_bytes - i));
550
551 /* Send the command and wait for it to complete */
552 I915_WRITE(ch_ctl, send_ctl);
553
554 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
555
556 /* Clear done status and any errors */
557 I915_WRITE(ch_ctl,
558 status |
559 DP_AUX_CH_CTL_DONE |
560 DP_AUX_CH_CTL_TIME_OUT_ERROR |
561 DP_AUX_CH_CTL_RECEIVE_ERROR);
562
563 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
564 DP_AUX_CH_CTL_RECEIVE_ERROR))
565 continue;
566 if (status & DP_AUX_CH_CTL_DONE)
567 break;
568 }
569 if (status & DP_AUX_CH_CTL_DONE)
570 break;
571 }
572
573 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
574 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
575 ret = -EBUSY;
576 goto out;
577 }
578
579 /* Check for timeout or receive error.
580 * Timeouts occur when the sink is not connected
581 */
582 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
583 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
584 ret = -EIO;
585 goto out;
586 }
587
588 /* Timeouts occur when the device isn't connected, so they're
589 * "normal" -- don't fill the kernel log with these */
590 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
591 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
592 ret = -ETIMEDOUT;
593 goto out;
594 }
595
596 /* Unload any bytes sent back from the other side */
597 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
598 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
599 if (recv_bytes > recv_size)
600 recv_bytes = recv_size;
601
602 for (i = 0; i < recv_bytes; i += 4)
603 unpack_aux(I915_READ(ch_data + i),
604 recv + i, recv_bytes - i);
605
606 ret = recv_bytes;
607 out:
608 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
609 intel_aux_display_runtime_put(dev_priv);
610
611 if (vdd)
612 edp_panel_vdd_off(intel_dp, false);
613
614 return ret;
615 }
616
617 #define BARE_ADDRESS_SIZE 3
618 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
619 static ssize_t
620 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
621 {
622 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
623 uint8_t txbuf[20], rxbuf[20];
624 size_t txsize, rxsize;
625 int ret;
626
627 txbuf[0] = msg->request << 4;
628 txbuf[1] = msg->address >> 8;
629 txbuf[2] = msg->address & 0xff;
630 txbuf[3] = msg->size - 1;
631
632 switch (msg->request & ~DP_AUX_I2C_MOT) {
633 case DP_AUX_NATIVE_WRITE:
634 case DP_AUX_I2C_WRITE:
635 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
636 rxsize = 1;
637
638 if (WARN_ON(txsize > 20))
639 return -E2BIG;
640
641 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
642
643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
646
647 /* Return payload size. */
648 ret = msg->size;
649 }
650 break;
651
652 case DP_AUX_NATIVE_READ:
653 case DP_AUX_I2C_READ:
654 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
655 rxsize = msg->size + 1;
656
657 if (WARN_ON(rxsize > 20))
658 return -E2BIG;
659
660 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
661 if (ret > 0) {
662 msg->reply = rxbuf[0] >> 4;
663 /*
664 * Assume happy day, and copy the data. The caller is
665 * expected to check msg->reply before touching it.
666 *
667 * Return payload size.
668 */
669 ret--;
670 memcpy(msg->buffer, rxbuf + 1, ret);
671 }
672 break;
673
674 default:
675 ret = -EINVAL;
676 break;
677 }
678
679 return ret;
680 }
681
682 static void
683 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
684 {
685 struct drm_device *dev = intel_dp_to_dev(intel_dp);
686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 enum port port = intel_dig_port->port;
688 const char *name = NULL;
689 int ret;
690
691 switch (port) {
692 case PORT_A:
693 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
694 name = "DPDDC-A";
695 break;
696 case PORT_B:
697 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
698 name = "DPDDC-B";
699 break;
700 case PORT_C:
701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
702 name = "DPDDC-C";
703 break;
704 case PORT_D:
705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
706 name = "DPDDC-D";
707 break;
708 default:
709 BUG();
710 }
711
712 if (!HAS_DDI(dev))
713 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
714
715 intel_dp->aux.name = name;
716 intel_dp->aux.dev = dev->dev;
717 intel_dp->aux.transfer = intel_dp_aux_transfer;
718
719 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
720 connector->base.kdev->kobj.name);
721
722 ret = drm_dp_aux_register(&intel_dp->aux);
723 if (ret < 0) {
724 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
725 name, ret);
726 return;
727 }
728
729 ret = sysfs_create_link(&connector->base.kdev->kobj,
730 &intel_dp->aux.ddc.dev.kobj,
731 intel_dp->aux.ddc.dev.kobj.name);
732 if (ret < 0) {
733 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
734 drm_dp_aux_unregister(&intel_dp->aux);
735 }
736 }
737
738 static void
739 intel_dp_connector_unregister(struct intel_connector *intel_connector)
740 {
741 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
742
743 sysfs_remove_link(&intel_connector->base.kdev->kobj,
744 intel_dp->aux.ddc.dev.kobj.name);
745 intel_connector_unregister(intel_connector);
746 }
747
748 static void
749 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
750 {
751 switch (link_bw) {
752 case DP_LINK_BW_1_62:
753 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
754 break;
755 case DP_LINK_BW_2_7:
756 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
757 break;
758 case DP_LINK_BW_5_4:
759 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
760 break;
761 }
762 }
763
764 static void
765 intel_dp_set_clock(struct intel_encoder *encoder,
766 struct intel_crtc_config *pipe_config, int link_bw)
767 {
768 struct drm_device *dev = encoder->base.dev;
769 const struct dp_link_dpll *divisor = NULL;
770 int i, count = 0;
771
772 if (IS_G4X(dev)) {
773 divisor = gen4_dpll;
774 count = ARRAY_SIZE(gen4_dpll);
775 } else if (HAS_PCH_SPLIT(dev)) {
776 divisor = pch_dpll;
777 count = ARRAY_SIZE(pch_dpll);
778 } else if (IS_CHERRYVIEW(dev)) {
779 divisor = chv_dpll;
780 count = ARRAY_SIZE(chv_dpll);
781 } else if (IS_VALLEYVIEW(dev)) {
782 divisor = vlv_dpll;
783 count = ARRAY_SIZE(vlv_dpll);
784 }
785
786 if (divisor && count) {
787 for (i = 0; i < count; i++) {
788 if (link_bw == divisor[i].link_bw) {
789 pipe_config->dpll = divisor[i].dpll;
790 pipe_config->clock_set = true;
791 break;
792 }
793 }
794 }
795 }
796
797 static void
798 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
799 {
800 struct drm_device *dev = crtc->base.dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
802 enum transcoder transcoder = crtc->config.cpu_transcoder;
803
804 I915_WRITE(PIPE_DATA_M2(transcoder),
805 TU_SIZE(m_n->tu) | m_n->gmch_m);
806 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
807 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
808 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
809 }
810
811 bool
812 intel_dp_compute_config(struct intel_encoder *encoder,
813 struct intel_crtc_config *pipe_config)
814 {
815 struct drm_device *dev = encoder->base.dev;
816 struct drm_i915_private *dev_priv = dev->dev_private;
817 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
818 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
819 enum port port = dp_to_dig_port(intel_dp)->port;
820 struct intel_crtc *intel_crtc = encoder->new_crtc;
821 struct intel_connector *intel_connector = intel_dp->attached_connector;
822 int lane_count, clock;
823 int min_lane_count = 1;
824 int max_lane_count = intel_dp_max_lane_count(intel_dp);
825 /* Conveniently, the link BW constants become indices with a shift...*/
826 int min_clock = 0;
827 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
828 int bpp, mode_rate;
829 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
830 int link_avail, link_clock;
831
832 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
833 pipe_config->has_pch_encoder = true;
834
835 pipe_config->has_dp_encoder = true;
836 pipe_config->has_audio = intel_dp->has_audio;
837
838 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
839 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
840 adjusted_mode);
841 if (!HAS_PCH_SPLIT(dev))
842 intel_gmch_panel_fitting(intel_crtc, pipe_config,
843 intel_connector->panel.fitting_mode);
844 else
845 intel_pch_panel_fitting(intel_crtc, pipe_config,
846 intel_connector->panel.fitting_mode);
847 }
848
849 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
850 return false;
851
852 DRM_DEBUG_KMS("DP link computation with max lane count %i "
853 "max bw %02x pixel clock %iKHz\n",
854 max_lane_count, bws[max_clock],
855 adjusted_mode->crtc_clock);
856
857 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
858 * bpc in between. */
859 bpp = pipe_config->pipe_bpp;
860 if (is_edp(intel_dp)) {
861 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
862 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
863 dev_priv->vbt.edp_bpp);
864 bpp = dev_priv->vbt.edp_bpp;
865 }
866
867 if (IS_BROADWELL(dev)) {
868 /* Yes, it's an ugly hack. */
869 min_lane_count = max_lane_count;
870 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
871 min_lane_count);
872 } else if (dev_priv->vbt.edp_lanes) {
873 min_lane_count = min(dev_priv->vbt.edp_lanes,
874 max_lane_count);
875 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
876 min_lane_count);
877 }
878
879 if (dev_priv->vbt.edp_rate) {
880 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
881 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
882 bws[min_clock]);
883 }
884 }
885
886 for (; bpp >= 6*3; bpp -= 2*3) {
887 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
888 bpp);
889
890 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
891 for (clock = min_clock; clock <= max_clock; clock++) {
892 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
893 link_avail = intel_dp_max_data_rate(link_clock,
894 lane_count);
895
896 if (mode_rate <= link_avail) {
897 goto found;
898 }
899 }
900 }
901 }
902
903 return false;
904
905 found:
906 if (intel_dp->color_range_auto) {
907 /*
908 * See:
909 * CEA-861-E - 5.1 Default Encoding Parameters
910 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
911 */
912 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
913 intel_dp->color_range = DP_COLOR_RANGE_16_235;
914 else
915 intel_dp->color_range = 0;
916 }
917
918 if (intel_dp->color_range)
919 pipe_config->limited_color_range = true;
920
921 intel_dp->link_bw = bws[clock];
922 intel_dp->lane_count = lane_count;
923 pipe_config->pipe_bpp = bpp;
924 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
925
926 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
927 intel_dp->link_bw, intel_dp->lane_count,
928 pipe_config->port_clock, bpp);
929 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
930 mode_rate, link_avail);
931
932 intel_link_compute_m_n(bpp, lane_count,
933 adjusted_mode->crtc_clock,
934 pipe_config->port_clock,
935 &pipe_config->dp_m_n);
936
937 if (intel_connector->panel.downclock_mode != NULL &&
938 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
939 intel_link_compute_m_n(bpp, lane_count,
940 intel_connector->panel.downclock_mode->clock,
941 pipe_config->port_clock,
942 &pipe_config->dp_m2_n2);
943 }
944
945 if (HAS_DDI(dev))
946 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
947 else
948 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
949
950 return true;
951 }
952
953 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
954 {
955 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
956 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
957 struct drm_device *dev = crtc->base.dev;
958 struct drm_i915_private *dev_priv = dev->dev_private;
959 u32 dpa_ctl;
960
961 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
962 dpa_ctl = I915_READ(DP_A);
963 dpa_ctl &= ~DP_PLL_FREQ_MASK;
964
965 if (crtc->config.port_clock == 162000) {
966 /* For a long time we've carried around a ILK-DevA w/a for the
967 * 160MHz clock. If we're really unlucky, it's still required.
968 */
969 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
970 dpa_ctl |= DP_PLL_FREQ_160MHZ;
971 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
972 } else {
973 dpa_ctl |= DP_PLL_FREQ_270MHZ;
974 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
975 }
976
977 I915_WRITE(DP_A, dpa_ctl);
978
979 POSTING_READ(DP_A);
980 udelay(500);
981 }
982
983 static void intel_dp_prepare(struct intel_encoder *encoder)
984 {
985 struct drm_device *dev = encoder->base.dev;
986 struct drm_i915_private *dev_priv = dev->dev_private;
987 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
988 enum port port = dp_to_dig_port(intel_dp)->port;
989 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
990 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
991
992 /*
993 * There are four kinds of DP registers:
994 *
995 * IBX PCH
996 * SNB CPU
997 * IVB CPU
998 * CPT PCH
999 *
1000 * IBX PCH and CPU are the same for almost everything,
1001 * except that the CPU DP PLL is configured in this
1002 * register
1003 *
1004 * CPT PCH is quite different, having many bits moved
1005 * to the TRANS_DP_CTL register instead. That
1006 * configuration happens (oddly) in ironlake_pch_enable
1007 */
1008
1009 /* Preserve the BIOS-computed detected bit. This is
1010 * supposed to be read-only.
1011 */
1012 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1013
1014 /* Handle DP bits in common between all three register formats */
1015 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1016 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1017
1018 if (crtc->config.has_audio) {
1019 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1020 pipe_name(crtc->pipe));
1021 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1022 intel_write_eld(&encoder->base, adjusted_mode);
1023 }
1024
1025 /* Split out the IBX/CPU vs CPT settings */
1026
1027 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1028 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1029 intel_dp->DP |= DP_SYNC_HS_HIGH;
1030 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1031 intel_dp->DP |= DP_SYNC_VS_HIGH;
1032 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1033
1034 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1035 intel_dp->DP |= DP_ENHANCED_FRAMING;
1036
1037 intel_dp->DP |= crtc->pipe << 29;
1038 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1039 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1040 intel_dp->DP |= intel_dp->color_range;
1041
1042 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1043 intel_dp->DP |= DP_SYNC_HS_HIGH;
1044 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1045 intel_dp->DP |= DP_SYNC_VS_HIGH;
1046 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1047
1048 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1049 intel_dp->DP |= DP_ENHANCED_FRAMING;
1050
1051 if (!IS_CHERRYVIEW(dev)) {
1052 if (crtc->pipe == 1)
1053 intel_dp->DP |= DP_PIPEB_SELECT;
1054 } else {
1055 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1056 }
1057 } else {
1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059 }
1060 }
1061
1062 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1063 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1064
1065 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1066 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1067
1068 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1069 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1070
1071 static void wait_panel_status(struct intel_dp *intel_dp,
1072 u32 mask,
1073 u32 value)
1074 {
1075 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 u32 pp_stat_reg, pp_ctrl_reg;
1078
1079 pp_stat_reg = _pp_stat_reg(intel_dp);
1080 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1081
1082 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1083 mask, value,
1084 I915_READ(pp_stat_reg),
1085 I915_READ(pp_ctrl_reg));
1086
1087 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1088 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1089 I915_READ(pp_stat_reg),
1090 I915_READ(pp_ctrl_reg));
1091 }
1092
1093 DRM_DEBUG_KMS("Wait complete\n");
1094 }
1095
1096 static void wait_panel_on(struct intel_dp *intel_dp)
1097 {
1098 DRM_DEBUG_KMS("Wait for panel power on\n");
1099 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1100 }
1101
1102 static void wait_panel_off(struct intel_dp *intel_dp)
1103 {
1104 DRM_DEBUG_KMS("Wait for panel power off time\n");
1105 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1106 }
1107
1108 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1109 {
1110 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1111
1112 /* When we disable the VDD override bit last we have to do the manual
1113 * wait. */
1114 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1115 intel_dp->panel_power_cycle_delay);
1116
1117 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1118 }
1119
1120 static void wait_backlight_on(struct intel_dp *intel_dp)
1121 {
1122 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1123 intel_dp->backlight_on_delay);
1124 }
1125
1126 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1127 {
1128 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1129 intel_dp->backlight_off_delay);
1130 }
1131
1132 /* Read the current pp_control value, unlocking the register if it
1133 * is locked
1134 */
1135
1136 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1137 {
1138 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140 u32 control;
1141
1142 control = I915_READ(_pp_ctrl_reg(intel_dp));
1143 control &= ~PANEL_UNLOCK_MASK;
1144 control |= PANEL_UNLOCK_REGS;
1145 return control;
1146 }
1147
1148 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1149 {
1150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1151 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1152 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 enum intel_display_power_domain power_domain;
1155 u32 pp;
1156 u32 pp_stat_reg, pp_ctrl_reg;
1157 bool need_to_disable = !intel_dp->want_panel_vdd;
1158
1159 if (!is_edp(intel_dp))
1160 return false;
1161
1162 intel_dp->want_panel_vdd = true;
1163
1164 if (edp_have_panel_vdd(intel_dp))
1165 return need_to_disable;
1166
1167 power_domain = intel_display_port_power_domain(intel_encoder);
1168 intel_display_power_get(dev_priv, power_domain);
1169
1170 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1171
1172 if (!edp_have_panel_power(intel_dp))
1173 wait_panel_power_cycle(intel_dp);
1174
1175 pp = ironlake_get_pp_control(intel_dp);
1176 pp |= EDP_FORCE_VDD;
1177
1178 pp_stat_reg = _pp_stat_reg(intel_dp);
1179 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1180
1181 I915_WRITE(pp_ctrl_reg, pp);
1182 POSTING_READ(pp_ctrl_reg);
1183 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1184 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1185 /*
1186 * If the panel wasn't on, delay before accessing aux channel
1187 */
1188 if (!edp_have_panel_power(intel_dp)) {
1189 DRM_DEBUG_KMS("eDP was not running\n");
1190 msleep(intel_dp->panel_power_up_delay);
1191 }
1192
1193 return need_to_disable;
1194 }
1195
1196 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1197 {
1198 if (is_edp(intel_dp)) {
1199 bool vdd = _edp_panel_vdd_on(intel_dp);
1200
1201 WARN(!vdd, "eDP VDD already requested on\n");
1202 }
1203 }
1204
1205 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1206 {
1207 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1208 struct drm_i915_private *dev_priv = dev->dev_private;
1209 u32 pp;
1210 u32 pp_stat_reg, pp_ctrl_reg;
1211
1212 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1213
1214 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1215 struct intel_digital_port *intel_dig_port =
1216 dp_to_dig_port(intel_dp);
1217 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1218 enum intel_display_power_domain power_domain;
1219
1220 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1221
1222 pp = ironlake_get_pp_control(intel_dp);
1223 pp &= ~EDP_FORCE_VDD;
1224
1225 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1226 pp_stat_reg = _pp_stat_reg(intel_dp);
1227
1228 I915_WRITE(pp_ctrl_reg, pp);
1229 POSTING_READ(pp_ctrl_reg);
1230
1231 /* Make sure sequencer is idle before allowing subsequent activity */
1232 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1233 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1234
1235 if ((pp & POWER_TARGET_ON) == 0)
1236 intel_dp->last_power_cycle = jiffies;
1237
1238 power_domain = intel_display_port_power_domain(intel_encoder);
1239 intel_display_power_put(dev_priv, power_domain);
1240 }
1241 }
1242
1243 static void edp_panel_vdd_work(struct work_struct *__work)
1244 {
1245 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1246 struct intel_dp, panel_vdd_work);
1247 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1248
1249 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1250 edp_panel_vdd_off_sync(intel_dp);
1251 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1252 }
1253
1254 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1255 {
1256 if (!is_edp(intel_dp))
1257 return;
1258
1259 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1260
1261 intel_dp->want_panel_vdd = false;
1262
1263 if (sync) {
1264 edp_panel_vdd_off_sync(intel_dp);
1265 } else {
1266 /*
1267 * Queue the timer to fire a long
1268 * time from now (relative to the power down delay)
1269 * to keep the panel power up across a sequence of operations
1270 */
1271 schedule_delayed_work(&intel_dp->panel_vdd_work,
1272 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1273 }
1274 }
1275
1276 void intel_edp_panel_on(struct intel_dp *intel_dp)
1277 {
1278 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 u32 pp;
1281 u32 pp_ctrl_reg;
1282
1283 if (!is_edp(intel_dp))
1284 return;
1285
1286 DRM_DEBUG_KMS("Turn eDP power on\n");
1287
1288 if (edp_have_panel_power(intel_dp)) {
1289 DRM_DEBUG_KMS("eDP power already on\n");
1290 return;
1291 }
1292
1293 wait_panel_power_cycle(intel_dp);
1294
1295 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1296 pp = ironlake_get_pp_control(intel_dp);
1297 if (IS_GEN5(dev)) {
1298 /* ILK workaround: disable reset around power sequence */
1299 pp &= ~PANEL_POWER_RESET;
1300 I915_WRITE(pp_ctrl_reg, pp);
1301 POSTING_READ(pp_ctrl_reg);
1302 }
1303
1304 pp |= POWER_TARGET_ON;
1305 if (!IS_GEN5(dev))
1306 pp |= PANEL_POWER_RESET;
1307
1308 I915_WRITE(pp_ctrl_reg, pp);
1309 POSTING_READ(pp_ctrl_reg);
1310
1311 wait_panel_on(intel_dp);
1312 intel_dp->last_power_on = jiffies;
1313
1314 if (IS_GEN5(dev)) {
1315 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1316 I915_WRITE(pp_ctrl_reg, pp);
1317 POSTING_READ(pp_ctrl_reg);
1318 }
1319 }
1320
1321 void intel_edp_panel_off(struct intel_dp *intel_dp)
1322 {
1323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1324 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1325 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1326 struct drm_i915_private *dev_priv = dev->dev_private;
1327 enum intel_display_power_domain power_domain;
1328 u32 pp;
1329 u32 pp_ctrl_reg;
1330
1331 if (!is_edp(intel_dp))
1332 return;
1333
1334 DRM_DEBUG_KMS("Turn eDP power off\n");
1335
1336 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1337
1338 pp = ironlake_get_pp_control(intel_dp);
1339 /* We need to switch off panel power _and_ force vdd, for otherwise some
1340 * panels get very unhappy and cease to work. */
1341 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1342 EDP_BLC_ENABLE);
1343
1344 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1345
1346 intel_dp->want_panel_vdd = false;
1347
1348 I915_WRITE(pp_ctrl_reg, pp);
1349 POSTING_READ(pp_ctrl_reg);
1350
1351 intel_dp->last_power_cycle = jiffies;
1352 wait_panel_off(intel_dp);
1353
1354 /* We got a reference when we enabled the VDD. */
1355 power_domain = intel_display_port_power_domain(intel_encoder);
1356 intel_display_power_put(dev_priv, power_domain);
1357 }
1358
1359 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1360 {
1361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1362 struct drm_device *dev = intel_dig_port->base.base.dev;
1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 u32 pp;
1365 u32 pp_ctrl_reg;
1366
1367 if (!is_edp(intel_dp))
1368 return;
1369
1370 DRM_DEBUG_KMS("\n");
1371
1372 intel_panel_enable_backlight(intel_dp->attached_connector);
1373
1374 /*
1375 * If we enable the backlight right away following a panel power
1376 * on, we may see slight flicker as the panel syncs with the eDP
1377 * link. So delay a bit to make sure the image is solid before
1378 * allowing it to appear.
1379 */
1380 wait_backlight_on(intel_dp);
1381 pp = ironlake_get_pp_control(intel_dp);
1382 pp |= EDP_BLC_ENABLE;
1383
1384 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1385
1386 I915_WRITE(pp_ctrl_reg, pp);
1387 POSTING_READ(pp_ctrl_reg);
1388 }
1389
1390 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1391 {
1392 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1393 struct drm_i915_private *dev_priv = dev->dev_private;
1394 u32 pp;
1395 u32 pp_ctrl_reg;
1396
1397 if (!is_edp(intel_dp))
1398 return;
1399
1400 DRM_DEBUG_KMS("\n");
1401 pp = ironlake_get_pp_control(intel_dp);
1402 pp &= ~EDP_BLC_ENABLE;
1403
1404 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1405
1406 I915_WRITE(pp_ctrl_reg, pp);
1407 POSTING_READ(pp_ctrl_reg);
1408 intel_dp->last_backlight_off = jiffies;
1409
1410 edp_wait_backlight_off(intel_dp);
1411
1412 intel_panel_disable_backlight(intel_dp->attached_connector);
1413 }
1414
1415 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1416 {
1417 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1418 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1419 struct drm_device *dev = crtc->dev;
1420 struct drm_i915_private *dev_priv = dev->dev_private;
1421 u32 dpa_ctl;
1422
1423 assert_pipe_disabled(dev_priv,
1424 to_intel_crtc(crtc)->pipe);
1425
1426 DRM_DEBUG_KMS("\n");
1427 dpa_ctl = I915_READ(DP_A);
1428 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1429 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1430
1431 /* We don't adjust intel_dp->DP while tearing down the link, to
1432 * facilitate link retraining (e.g. after hotplug). Hence clear all
1433 * enable bits here to ensure that we don't enable too much. */
1434 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1435 intel_dp->DP |= DP_PLL_ENABLE;
1436 I915_WRITE(DP_A, intel_dp->DP);
1437 POSTING_READ(DP_A);
1438 udelay(200);
1439 }
1440
1441 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1442 {
1443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1444 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1445 struct drm_device *dev = crtc->dev;
1446 struct drm_i915_private *dev_priv = dev->dev_private;
1447 u32 dpa_ctl;
1448
1449 assert_pipe_disabled(dev_priv,
1450 to_intel_crtc(crtc)->pipe);
1451
1452 dpa_ctl = I915_READ(DP_A);
1453 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1454 "dp pll off, should be on\n");
1455 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1456
1457 /* We can't rely on the value tracked for the DP register in
1458 * intel_dp->DP because link_down must not change that (otherwise link
1459 * re-training will fail. */
1460 dpa_ctl &= ~DP_PLL_ENABLE;
1461 I915_WRITE(DP_A, dpa_ctl);
1462 POSTING_READ(DP_A);
1463 udelay(200);
1464 }
1465
1466 /* If the sink supports it, try to set the power state appropriately */
1467 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1468 {
1469 int ret, i;
1470
1471 /* Should have a valid DPCD by this point */
1472 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1473 return;
1474
1475 if (mode != DRM_MODE_DPMS_ON) {
1476 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1477 DP_SET_POWER_D3);
1478 if (ret != 1)
1479 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1480 } else {
1481 /*
1482 * When turning on, we need to retry for 1ms to give the sink
1483 * time to wake up.
1484 */
1485 for (i = 0; i < 3; i++) {
1486 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1487 DP_SET_POWER_D0);
1488 if (ret == 1)
1489 break;
1490 msleep(1);
1491 }
1492 }
1493 }
1494
1495 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1496 enum pipe *pipe)
1497 {
1498 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1499 enum port port = dp_to_dig_port(intel_dp)->port;
1500 struct drm_device *dev = encoder->base.dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1502 enum intel_display_power_domain power_domain;
1503 u32 tmp;
1504
1505 power_domain = intel_display_port_power_domain(encoder);
1506 if (!intel_display_power_enabled(dev_priv, power_domain))
1507 return false;
1508
1509 tmp = I915_READ(intel_dp->output_reg);
1510
1511 if (!(tmp & DP_PORT_EN))
1512 return false;
1513
1514 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1515 *pipe = PORT_TO_PIPE_CPT(tmp);
1516 } else if (IS_CHERRYVIEW(dev)) {
1517 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1518 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1519 *pipe = PORT_TO_PIPE(tmp);
1520 } else {
1521 u32 trans_sel;
1522 u32 trans_dp;
1523 int i;
1524
1525 switch (intel_dp->output_reg) {
1526 case PCH_DP_B:
1527 trans_sel = TRANS_DP_PORT_SEL_B;
1528 break;
1529 case PCH_DP_C:
1530 trans_sel = TRANS_DP_PORT_SEL_C;
1531 break;
1532 case PCH_DP_D:
1533 trans_sel = TRANS_DP_PORT_SEL_D;
1534 break;
1535 default:
1536 return true;
1537 }
1538
1539 for_each_pipe(i) {
1540 trans_dp = I915_READ(TRANS_DP_CTL(i));
1541 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1542 *pipe = i;
1543 return true;
1544 }
1545 }
1546
1547 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1548 intel_dp->output_reg);
1549 }
1550
1551 return true;
1552 }
1553
1554 static void intel_dp_get_config(struct intel_encoder *encoder,
1555 struct intel_crtc_config *pipe_config)
1556 {
1557 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1558 u32 tmp, flags = 0;
1559 struct drm_device *dev = encoder->base.dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 enum port port = dp_to_dig_port(intel_dp)->port;
1562 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1563 int dotclock;
1564
1565 tmp = I915_READ(intel_dp->output_reg);
1566 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1567 pipe_config->has_audio = true;
1568
1569 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1570 if (tmp & DP_SYNC_HS_HIGH)
1571 flags |= DRM_MODE_FLAG_PHSYNC;
1572 else
1573 flags |= DRM_MODE_FLAG_NHSYNC;
1574
1575 if (tmp & DP_SYNC_VS_HIGH)
1576 flags |= DRM_MODE_FLAG_PVSYNC;
1577 else
1578 flags |= DRM_MODE_FLAG_NVSYNC;
1579 } else {
1580 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1581 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1582 flags |= DRM_MODE_FLAG_PHSYNC;
1583 else
1584 flags |= DRM_MODE_FLAG_NHSYNC;
1585
1586 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1587 flags |= DRM_MODE_FLAG_PVSYNC;
1588 else
1589 flags |= DRM_MODE_FLAG_NVSYNC;
1590 }
1591
1592 pipe_config->adjusted_mode.flags |= flags;
1593
1594 pipe_config->has_dp_encoder = true;
1595
1596 intel_dp_get_m_n(crtc, pipe_config);
1597
1598 if (port == PORT_A) {
1599 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1600 pipe_config->port_clock = 162000;
1601 else
1602 pipe_config->port_clock = 270000;
1603 }
1604
1605 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1606 &pipe_config->dp_m_n);
1607
1608 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1609 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1610
1611 pipe_config->adjusted_mode.crtc_clock = dotclock;
1612
1613 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1614 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1615 /*
1616 * This is a big fat ugly hack.
1617 *
1618 * Some machines in UEFI boot mode provide us a VBT that has 18
1619 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1620 * unknown we fail to light up. Yet the same BIOS boots up with
1621 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1622 * max, not what it tells us to use.
1623 *
1624 * Note: This will still be broken if the eDP panel is not lit
1625 * up by the BIOS, and thus we can't get the mode at module
1626 * load.
1627 */
1628 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1629 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1630 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1631 }
1632 }
1633
1634 static bool is_edp_psr(struct intel_dp *intel_dp)
1635 {
1636 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1637 }
1638
1639 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1640 {
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642
1643 if (!HAS_PSR(dev))
1644 return false;
1645
1646 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1647 }
1648
1649 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1650 struct edp_vsc_psr *vsc_psr)
1651 {
1652 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1653 struct drm_device *dev = dig_port->base.base.dev;
1654 struct drm_i915_private *dev_priv = dev->dev_private;
1655 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1656 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1657 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1658 uint32_t *data = (uint32_t *) vsc_psr;
1659 unsigned int i;
1660
1661 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1662 the video DIP being updated before program video DIP data buffer
1663 registers for DIP being updated. */
1664 I915_WRITE(ctl_reg, 0);
1665 POSTING_READ(ctl_reg);
1666
1667 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1668 if (i < sizeof(struct edp_vsc_psr))
1669 I915_WRITE(data_reg + i, *data++);
1670 else
1671 I915_WRITE(data_reg + i, 0);
1672 }
1673
1674 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1675 POSTING_READ(ctl_reg);
1676 }
1677
1678 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1679 {
1680 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 struct edp_vsc_psr psr_vsc;
1683
1684 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1685 memset(&psr_vsc, 0, sizeof(psr_vsc));
1686 psr_vsc.sdp_header.HB0 = 0;
1687 psr_vsc.sdp_header.HB1 = 0x7;
1688 psr_vsc.sdp_header.HB2 = 0x2;
1689 psr_vsc.sdp_header.HB3 = 0x8;
1690 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1691
1692 /* Avoid continuous PSR exit by masking memup and hpd */
1693 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1694 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1695 }
1696
1697 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1698 {
1699 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1700 struct drm_device *dev = dig_port->base.base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 uint32_t aux_clock_divider;
1703 int precharge = 0x3;
1704 int msg_size = 5; /* Header(4) + Message(1) */
1705 bool only_standby = false;
1706
1707 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1708
1709 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1710 only_standby = true;
1711
1712 /* Enable PSR in sink */
1713 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1714 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1715 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1716 else
1717 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1718 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1719
1720 /* Setup AUX registers */
1721 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1722 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1723 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1724 DP_AUX_CH_CTL_TIME_OUT_400us |
1725 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1726 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1727 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1728 }
1729
1730 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1731 {
1732 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1733 struct drm_device *dev = dig_port->base.base.dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 uint32_t max_sleep_time = 0x1f;
1736 uint32_t idle_frames = 1;
1737 uint32_t val = 0x0;
1738 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1739 bool only_standby = false;
1740
1741 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1742 only_standby = true;
1743
1744 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1745 val |= EDP_PSR_LINK_STANDBY;
1746 val |= EDP_PSR_TP2_TP3_TIME_0us;
1747 val |= EDP_PSR_TP1_TIME_0us;
1748 val |= EDP_PSR_SKIP_AUX_EXIT;
1749 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1750 } else
1751 val |= EDP_PSR_LINK_DISABLE;
1752
1753 I915_WRITE(EDP_PSR_CTL(dev), val |
1754 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1755 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1756 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1757 EDP_PSR_ENABLE);
1758 }
1759
1760 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1761 {
1762 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1763 struct drm_device *dev = dig_port->base.base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 struct drm_crtc *crtc = dig_port->base.base.crtc;
1766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1767 struct drm_i915_gem_object *obj = intel_fb_obj(crtc->primary->fb);
1768 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1769
1770 dev_priv->psr.source_ok = false;
1771
1772 if (!HAS_PSR(dev)) {
1773 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1774 return false;
1775 }
1776
1777 if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP ||
1778 dig_port->port != PORT_A)) {
1779 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1780 return false;
1781 }
1782
1783 if (!i915.enable_psr) {
1784 DRM_DEBUG_KMS("PSR disable by flag\n");
1785 return false;
1786 }
1787
1788 crtc = dig_port->base.base.crtc;
1789 if (crtc == NULL) {
1790 DRM_DEBUG_KMS("crtc not active for PSR\n");
1791 return false;
1792 }
1793
1794 intel_crtc = to_intel_crtc(crtc);
1795 if (!intel_crtc_active(crtc)) {
1796 DRM_DEBUG_KMS("crtc not active for PSR\n");
1797 return false;
1798 }
1799
1800 if (obj->tiling_mode != I915_TILING_X ||
1801 obj->fence_reg == I915_FENCE_REG_NONE) {
1802 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1803 return false;
1804 }
1805
1806 /* Below limitations aren't valid for Broadwell */
1807 if (IS_BROADWELL(dev))
1808 goto out;
1809
1810 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1811 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1812 return false;
1813 }
1814
1815 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1816 S3D_ENABLE) {
1817 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1818 return false;
1819 }
1820
1821 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1822 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1823 return false;
1824 }
1825
1826 out:
1827 dev_priv->psr.source_ok = true;
1828 return true;
1829 }
1830
1831 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1832 {
1833 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1834 struct drm_device *dev = intel_dig_port->base.base.dev;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836
1837 if (intel_edp_is_psr_enabled(dev))
1838 return;
1839
1840 /* Enable PSR on the panel */
1841 intel_edp_psr_enable_sink(intel_dp);
1842
1843 /* Enable PSR on the host */
1844 intel_edp_psr_enable_source(intel_dp);
1845
1846 dev_priv->psr.enabled = true;
1847 dev_priv->psr.active = true;
1848 }
1849
1850 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1851 {
1852 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1853
1854 if (!HAS_PSR(dev)) {
1855 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1856 return;
1857 }
1858
1859 if (!is_edp_psr(intel_dp)) {
1860 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1861 return;
1862 }
1863
1864 /* Setup PSR once */
1865 intel_edp_psr_setup(intel_dp);
1866
1867 if (intel_edp_psr_match_conditions(intel_dp))
1868 intel_edp_psr_do_enable(intel_dp);
1869 }
1870
1871 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1872 {
1873 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1874 struct drm_i915_private *dev_priv = dev->dev_private;
1875
1876 if (!dev_priv->psr.enabled)
1877 return;
1878
1879 I915_WRITE(EDP_PSR_CTL(dev),
1880 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1881
1882 /* Wait till PSR is idle */
1883 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1884 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1885 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1886
1887 dev_priv->psr.enabled = false;
1888 }
1889
1890 static void intel_edp_psr_work(struct work_struct *work)
1891 {
1892 struct drm_i915_private *dev_priv =
1893 container_of(work, typeof(*dev_priv), psr.work.work);
1894 struct drm_device *dev = dev_priv->dev;
1895 struct intel_encoder *encoder;
1896 struct intel_dp *intel_dp = NULL;
1897
1898 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1899 if (encoder->type == INTEL_OUTPUT_EDP) {
1900 intel_dp = enc_to_intel_dp(&encoder->base);
1901
1902 if (!intel_edp_psr_match_conditions(intel_dp))
1903 intel_edp_psr_disable(intel_dp);
1904 else
1905 intel_edp_psr_do_enable(intel_dp);
1906 }
1907 }
1908
1909 static void intel_edp_psr_inactivate(struct drm_device *dev)
1910 {
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1912
1913 dev_priv->psr.active = false;
1914
1915 I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
1916 & ~EDP_PSR_ENABLE);
1917 }
1918
1919 void intel_edp_psr_exit(struct drm_device *dev)
1920 {
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922
1923 if (!HAS_PSR(dev))
1924 return;
1925
1926 if (!dev_priv->psr.enabled)
1927 return;
1928
1929 cancel_delayed_work_sync(&dev_priv->psr.work);
1930
1931 if (dev_priv->psr.active)
1932 intel_edp_psr_inactivate(dev);
1933
1934 schedule_delayed_work(&dev_priv->psr.work,
1935 msecs_to_jiffies(100));
1936 }
1937
1938 void intel_edp_psr_init(struct drm_device *dev)
1939 {
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941
1942 if (!HAS_PSR(dev))
1943 return;
1944
1945 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
1946 }
1947
1948 static void intel_disable_dp(struct intel_encoder *encoder)
1949 {
1950 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1951 enum port port = dp_to_dig_port(intel_dp)->port;
1952 struct drm_device *dev = encoder->base.dev;
1953
1954 /* Make sure the panel is off before trying to change the mode. But also
1955 * ensure that we have vdd while we switch off the panel. */
1956 intel_edp_panel_vdd_on(intel_dp);
1957 intel_edp_backlight_off(intel_dp);
1958 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1959 intel_edp_panel_off(intel_dp);
1960
1961 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1962 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1963 intel_dp_link_down(intel_dp);
1964 }
1965
1966 static void g4x_post_disable_dp(struct intel_encoder *encoder)
1967 {
1968 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1969 enum port port = dp_to_dig_port(intel_dp)->port;
1970
1971 if (port != PORT_A)
1972 return;
1973
1974 intel_dp_link_down(intel_dp);
1975 ironlake_edp_pll_off(intel_dp);
1976 }
1977
1978 static void vlv_post_disable_dp(struct intel_encoder *encoder)
1979 {
1980 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1981
1982 intel_dp_link_down(intel_dp);
1983 }
1984
1985 static void chv_post_disable_dp(struct intel_encoder *encoder)
1986 {
1987 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1988 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1989 struct drm_device *dev = encoder->base.dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct intel_crtc *intel_crtc =
1992 to_intel_crtc(encoder->base.crtc);
1993 enum dpio_channel ch = vlv_dport_to_channel(dport);
1994 enum pipe pipe = intel_crtc->pipe;
1995 u32 val;
1996
1997 intel_dp_link_down(intel_dp);
1998
1999 mutex_lock(&dev_priv->dpio_lock);
2000
2001 /* Propagate soft reset to data lane reset */
2002 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2003 val |= CHV_PCS_REQ_SOFTRESET_EN;
2004 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2005
2006 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2007 val |= CHV_PCS_REQ_SOFTRESET_EN;
2008 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2009
2010 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2011 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2012 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2013
2014 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2015 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2016 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2017
2018 mutex_unlock(&dev_priv->dpio_lock);
2019 }
2020
2021 static void intel_enable_dp(struct intel_encoder *encoder)
2022 {
2023 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2024 struct drm_device *dev = encoder->base.dev;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2027
2028 if (WARN_ON(dp_reg & DP_PORT_EN))
2029 return;
2030
2031 intel_edp_panel_vdd_on(intel_dp);
2032 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2033 intel_dp_start_link_train(intel_dp);
2034 intel_edp_panel_on(intel_dp);
2035 edp_panel_vdd_off(intel_dp, true);
2036 intel_dp_complete_link_train(intel_dp);
2037 intel_dp_stop_link_train(intel_dp);
2038 }
2039
2040 static void g4x_enable_dp(struct intel_encoder *encoder)
2041 {
2042 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2043
2044 intel_enable_dp(encoder);
2045 intel_edp_backlight_on(intel_dp);
2046 }
2047
2048 static void vlv_enable_dp(struct intel_encoder *encoder)
2049 {
2050 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2051
2052 intel_edp_backlight_on(intel_dp);
2053 }
2054
2055 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2056 {
2057 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2058 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2059
2060 intel_dp_prepare(encoder);
2061
2062 /* Only ilk+ has port A */
2063 if (dport->port == PORT_A) {
2064 ironlake_set_pll_cpu_edp(intel_dp);
2065 ironlake_edp_pll_on(intel_dp);
2066 }
2067 }
2068
2069 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2070 {
2071 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2072 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2073 struct drm_device *dev = encoder->base.dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2076 enum dpio_channel port = vlv_dport_to_channel(dport);
2077 int pipe = intel_crtc->pipe;
2078 struct edp_power_seq power_seq;
2079 u32 val;
2080
2081 mutex_lock(&dev_priv->dpio_lock);
2082
2083 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2084 val = 0;
2085 if (pipe)
2086 val |= (1<<21);
2087 else
2088 val &= ~(1<<21);
2089 val |= 0x001000c4;
2090 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2091 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2092 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2093
2094 mutex_unlock(&dev_priv->dpio_lock);
2095
2096 if (is_edp(intel_dp)) {
2097 /* init power sequencer on this pipe and port */
2098 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2099 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2100 &power_seq);
2101 }
2102
2103 intel_enable_dp(encoder);
2104
2105 vlv_wait_port_ready(dev_priv, dport);
2106 }
2107
2108 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2109 {
2110 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2111 struct drm_device *dev = encoder->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 struct intel_crtc *intel_crtc =
2114 to_intel_crtc(encoder->base.crtc);
2115 enum dpio_channel port = vlv_dport_to_channel(dport);
2116 int pipe = intel_crtc->pipe;
2117
2118 intel_dp_prepare(encoder);
2119
2120 /* Program Tx lane resets to default */
2121 mutex_lock(&dev_priv->dpio_lock);
2122 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2123 DPIO_PCS_TX_LANE2_RESET |
2124 DPIO_PCS_TX_LANE1_RESET);
2125 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2126 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2127 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2128 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2129 DPIO_PCS_CLK_SOFT_RESET);
2130
2131 /* Fix up inter-pair skew failure */
2132 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2135 mutex_unlock(&dev_priv->dpio_lock);
2136 }
2137
2138 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2139 {
2140 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2141 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2142 struct drm_device *dev = encoder->base.dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 struct edp_power_seq power_seq;
2145 struct intel_crtc *intel_crtc =
2146 to_intel_crtc(encoder->base.crtc);
2147 enum dpio_channel ch = vlv_dport_to_channel(dport);
2148 int pipe = intel_crtc->pipe;
2149 int data, i;
2150 u32 val;
2151
2152 mutex_lock(&dev_priv->dpio_lock);
2153
2154 /* Deassert soft data lane reset*/
2155 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2156 val |= CHV_PCS_REQ_SOFTRESET_EN;
2157 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2158
2159 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2160 val |= CHV_PCS_REQ_SOFTRESET_EN;
2161 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2162
2163 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2164 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2165 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2166
2167 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2168 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2169 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2170
2171 /* Program Tx lane latency optimal setting*/
2172 for (i = 0; i < 4; i++) {
2173 /* Set the latency optimal bit */
2174 data = (i == 1) ? 0x0 : 0x6;
2175 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2176 data << DPIO_FRC_LATENCY_SHFIT);
2177
2178 /* Set the upar bit */
2179 data = (i == 1) ? 0x0 : 0x1;
2180 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2181 data << DPIO_UPAR_SHIFT);
2182 }
2183
2184 /* Data lane stagger programming */
2185 /* FIXME: Fix up value only after power analysis */
2186
2187 mutex_unlock(&dev_priv->dpio_lock);
2188
2189 if (is_edp(intel_dp)) {
2190 /* init power sequencer on this pipe and port */
2191 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2192 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2193 &power_seq);
2194 }
2195
2196 intel_enable_dp(encoder);
2197
2198 vlv_wait_port_ready(dev_priv, dport);
2199 }
2200
2201 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2202 {
2203 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2204 struct drm_device *dev = encoder->base.dev;
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 struct intel_crtc *intel_crtc =
2207 to_intel_crtc(encoder->base.crtc);
2208 enum dpio_channel ch = vlv_dport_to_channel(dport);
2209 enum pipe pipe = intel_crtc->pipe;
2210 u32 val;
2211
2212 mutex_lock(&dev_priv->dpio_lock);
2213
2214 /* program left/right clock distribution */
2215 if (pipe != PIPE_B) {
2216 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2217 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2218 if (ch == DPIO_CH0)
2219 val |= CHV_BUFLEFTENA1_FORCE;
2220 if (ch == DPIO_CH1)
2221 val |= CHV_BUFRIGHTENA1_FORCE;
2222 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2223 } else {
2224 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2225 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2226 if (ch == DPIO_CH0)
2227 val |= CHV_BUFLEFTENA2_FORCE;
2228 if (ch == DPIO_CH1)
2229 val |= CHV_BUFRIGHTENA2_FORCE;
2230 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2231 }
2232
2233 /* program clock channel usage */
2234 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2235 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2236 if (pipe != PIPE_B)
2237 val &= ~CHV_PCS_USEDCLKCHANNEL;
2238 else
2239 val |= CHV_PCS_USEDCLKCHANNEL;
2240 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2241
2242 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2243 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2244 if (pipe != PIPE_B)
2245 val &= ~CHV_PCS_USEDCLKCHANNEL;
2246 else
2247 val |= CHV_PCS_USEDCLKCHANNEL;
2248 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2249
2250 /*
2251 * This a a bit weird since generally CL
2252 * matches the pipe, but here we need to
2253 * pick the CL based on the port.
2254 */
2255 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2256 if (pipe != PIPE_B)
2257 val &= ~CHV_CMN_USEDCLKCHANNEL;
2258 else
2259 val |= CHV_CMN_USEDCLKCHANNEL;
2260 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2261
2262 mutex_unlock(&dev_priv->dpio_lock);
2263 }
2264
2265 /*
2266 * Native read with retry for link status and receiver capability reads for
2267 * cases where the sink may still be asleep.
2268 *
2269 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2270 * supposed to retry 3 times per the spec.
2271 */
2272 static ssize_t
2273 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2274 void *buffer, size_t size)
2275 {
2276 ssize_t ret;
2277 int i;
2278
2279 for (i = 0; i < 3; i++) {
2280 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2281 if (ret == size)
2282 return ret;
2283 msleep(1);
2284 }
2285
2286 return ret;
2287 }
2288
2289 /*
2290 * Fetch AUX CH registers 0x202 - 0x207 which contain
2291 * link status information
2292 */
2293 static bool
2294 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2295 {
2296 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2297 DP_LANE0_1_STATUS,
2298 link_status,
2299 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2300 }
2301
2302 /* These are source-specific values. */
2303 static uint8_t
2304 intel_dp_voltage_max(struct intel_dp *intel_dp)
2305 {
2306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2307 enum port port = dp_to_dig_port(intel_dp)->port;
2308
2309 if (IS_VALLEYVIEW(dev))
2310 return DP_TRAIN_VOLTAGE_SWING_1200;
2311 else if (IS_GEN7(dev) && port == PORT_A)
2312 return DP_TRAIN_VOLTAGE_SWING_800;
2313 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2314 return DP_TRAIN_VOLTAGE_SWING_1200;
2315 else
2316 return DP_TRAIN_VOLTAGE_SWING_800;
2317 }
2318
2319 static uint8_t
2320 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2321 {
2322 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2323 enum port port = dp_to_dig_port(intel_dp)->port;
2324
2325 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2326 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2327 case DP_TRAIN_VOLTAGE_SWING_400:
2328 return DP_TRAIN_PRE_EMPHASIS_9_5;
2329 case DP_TRAIN_VOLTAGE_SWING_600:
2330 return DP_TRAIN_PRE_EMPHASIS_6;
2331 case DP_TRAIN_VOLTAGE_SWING_800:
2332 return DP_TRAIN_PRE_EMPHASIS_3_5;
2333 case DP_TRAIN_VOLTAGE_SWING_1200:
2334 default:
2335 return DP_TRAIN_PRE_EMPHASIS_0;
2336 }
2337 } else if (IS_VALLEYVIEW(dev)) {
2338 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2339 case DP_TRAIN_VOLTAGE_SWING_400:
2340 return DP_TRAIN_PRE_EMPHASIS_9_5;
2341 case DP_TRAIN_VOLTAGE_SWING_600:
2342 return DP_TRAIN_PRE_EMPHASIS_6;
2343 case DP_TRAIN_VOLTAGE_SWING_800:
2344 return DP_TRAIN_PRE_EMPHASIS_3_5;
2345 case DP_TRAIN_VOLTAGE_SWING_1200:
2346 default:
2347 return DP_TRAIN_PRE_EMPHASIS_0;
2348 }
2349 } else if (IS_GEN7(dev) && port == PORT_A) {
2350 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2351 case DP_TRAIN_VOLTAGE_SWING_400:
2352 return DP_TRAIN_PRE_EMPHASIS_6;
2353 case DP_TRAIN_VOLTAGE_SWING_600:
2354 case DP_TRAIN_VOLTAGE_SWING_800:
2355 return DP_TRAIN_PRE_EMPHASIS_3_5;
2356 default:
2357 return DP_TRAIN_PRE_EMPHASIS_0;
2358 }
2359 } else {
2360 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2361 case DP_TRAIN_VOLTAGE_SWING_400:
2362 return DP_TRAIN_PRE_EMPHASIS_6;
2363 case DP_TRAIN_VOLTAGE_SWING_600:
2364 return DP_TRAIN_PRE_EMPHASIS_6;
2365 case DP_TRAIN_VOLTAGE_SWING_800:
2366 return DP_TRAIN_PRE_EMPHASIS_3_5;
2367 case DP_TRAIN_VOLTAGE_SWING_1200:
2368 default:
2369 return DP_TRAIN_PRE_EMPHASIS_0;
2370 }
2371 }
2372 }
2373
2374 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2375 {
2376 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2379 struct intel_crtc *intel_crtc =
2380 to_intel_crtc(dport->base.base.crtc);
2381 unsigned long demph_reg_value, preemph_reg_value,
2382 uniqtranscale_reg_value;
2383 uint8_t train_set = intel_dp->train_set[0];
2384 enum dpio_channel port = vlv_dport_to_channel(dport);
2385 int pipe = intel_crtc->pipe;
2386
2387 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2388 case DP_TRAIN_PRE_EMPHASIS_0:
2389 preemph_reg_value = 0x0004000;
2390 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2391 case DP_TRAIN_VOLTAGE_SWING_400:
2392 demph_reg_value = 0x2B405555;
2393 uniqtranscale_reg_value = 0x552AB83A;
2394 break;
2395 case DP_TRAIN_VOLTAGE_SWING_600:
2396 demph_reg_value = 0x2B404040;
2397 uniqtranscale_reg_value = 0x5548B83A;
2398 break;
2399 case DP_TRAIN_VOLTAGE_SWING_800:
2400 demph_reg_value = 0x2B245555;
2401 uniqtranscale_reg_value = 0x5560B83A;
2402 break;
2403 case DP_TRAIN_VOLTAGE_SWING_1200:
2404 demph_reg_value = 0x2B405555;
2405 uniqtranscale_reg_value = 0x5598DA3A;
2406 break;
2407 default:
2408 return 0;
2409 }
2410 break;
2411 case DP_TRAIN_PRE_EMPHASIS_3_5:
2412 preemph_reg_value = 0x0002000;
2413 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2414 case DP_TRAIN_VOLTAGE_SWING_400:
2415 demph_reg_value = 0x2B404040;
2416 uniqtranscale_reg_value = 0x5552B83A;
2417 break;
2418 case DP_TRAIN_VOLTAGE_SWING_600:
2419 demph_reg_value = 0x2B404848;
2420 uniqtranscale_reg_value = 0x5580B83A;
2421 break;
2422 case DP_TRAIN_VOLTAGE_SWING_800:
2423 demph_reg_value = 0x2B404040;
2424 uniqtranscale_reg_value = 0x55ADDA3A;
2425 break;
2426 default:
2427 return 0;
2428 }
2429 break;
2430 case DP_TRAIN_PRE_EMPHASIS_6:
2431 preemph_reg_value = 0x0000000;
2432 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2433 case DP_TRAIN_VOLTAGE_SWING_400:
2434 demph_reg_value = 0x2B305555;
2435 uniqtranscale_reg_value = 0x5570B83A;
2436 break;
2437 case DP_TRAIN_VOLTAGE_SWING_600:
2438 demph_reg_value = 0x2B2B4040;
2439 uniqtranscale_reg_value = 0x55ADDA3A;
2440 break;
2441 default:
2442 return 0;
2443 }
2444 break;
2445 case DP_TRAIN_PRE_EMPHASIS_9_5:
2446 preemph_reg_value = 0x0006000;
2447 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2448 case DP_TRAIN_VOLTAGE_SWING_400:
2449 demph_reg_value = 0x1B405555;
2450 uniqtranscale_reg_value = 0x55ADDA3A;
2451 break;
2452 default:
2453 return 0;
2454 }
2455 break;
2456 default:
2457 return 0;
2458 }
2459
2460 mutex_lock(&dev_priv->dpio_lock);
2461 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2462 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2463 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2464 uniqtranscale_reg_value);
2465 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2466 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2467 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2468 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2469 mutex_unlock(&dev_priv->dpio_lock);
2470
2471 return 0;
2472 }
2473
2474 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2475 {
2476 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2479 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2480 u32 deemph_reg_value, margin_reg_value, val;
2481 uint8_t train_set = intel_dp->train_set[0];
2482 enum dpio_channel ch = vlv_dport_to_channel(dport);
2483 enum pipe pipe = intel_crtc->pipe;
2484 int i;
2485
2486 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2487 case DP_TRAIN_PRE_EMPHASIS_0:
2488 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2489 case DP_TRAIN_VOLTAGE_SWING_400:
2490 deemph_reg_value = 128;
2491 margin_reg_value = 52;
2492 break;
2493 case DP_TRAIN_VOLTAGE_SWING_600:
2494 deemph_reg_value = 128;
2495 margin_reg_value = 77;
2496 break;
2497 case DP_TRAIN_VOLTAGE_SWING_800:
2498 deemph_reg_value = 128;
2499 margin_reg_value = 102;
2500 break;
2501 case DP_TRAIN_VOLTAGE_SWING_1200:
2502 deemph_reg_value = 128;
2503 margin_reg_value = 154;
2504 /* FIXME extra to set for 1200 */
2505 break;
2506 default:
2507 return 0;
2508 }
2509 break;
2510 case DP_TRAIN_PRE_EMPHASIS_3_5:
2511 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2512 case DP_TRAIN_VOLTAGE_SWING_400:
2513 deemph_reg_value = 85;
2514 margin_reg_value = 78;
2515 break;
2516 case DP_TRAIN_VOLTAGE_SWING_600:
2517 deemph_reg_value = 85;
2518 margin_reg_value = 116;
2519 break;
2520 case DP_TRAIN_VOLTAGE_SWING_800:
2521 deemph_reg_value = 85;
2522 margin_reg_value = 154;
2523 break;
2524 default:
2525 return 0;
2526 }
2527 break;
2528 case DP_TRAIN_PRE_EMPHASIS_6:
2529 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2530 case DP_TRAIN_VOLTAGE_SWING_400:
2531 deemph_reg_value = 64;
2532 margin_reg_value = 104;
2533 break;
2534 case DP_TRAIN_VOLTAGE_SWING_600:
2535 deemph_reg_value = 64;
2536 margin_reg_value = 154;
2537 break;
2538 default:
2539 return 0;
2540 }
2541 break;
2542 case DP_TRAIN_PRE_EMPHASIS_9_5:
2543 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2544 case DP_TRAIN_VOLTAGE_SWING_400:
2545 deemph_reg_value = 43;
2546 margin_reg_value = 154;
2547 break;
2548 default:
2549 return 0;
2550 }
2551 break;
2552 default:
2553 return 0;
2554 }
2555
2556 mutex_lock(&dev_priv->dpio_lock);
2557
2558 /* Clear calc init */
2559 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2560 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2561 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2562
2563 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2564 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2565 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2566
2567 /* Program swing deemph */
2568 for (i = 0; i < 4; i++) {
2569 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2570 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2571 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2572 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2573 }
2574
2575 /* Program swing margin */
2576 for (i = 0; i < 4; i++) {
2577 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2578 val &= ~DPIO_SWING_MARGIN_MASK;
2579 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2580 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2581 }
2582
2583 /* Disable unique transition scale */
2584 for (i = 0; i < 4; i++) {
2585 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2586 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2587 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2588 }
2589
2590 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2591 == DP_TRAIN_PRE_EMPHASIS_0) &&
2592 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2593 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2594
2595 /*
2596 * The document said it needs to set bit 27 for ch0 and bit 26
2597 * for ch1. Might be a typo in the doc.
2598 * For now, for this unique transition scale selection, set bit
2599 * 27 for ch0 and ch1.
2600 */
2601 for (i = 0; i < 4; i++) {
2602 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2603 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2604 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2605 }
2606
2607 for (i = 0; i < 4; i++) {
2608 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2609 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2610 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2611 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2612 }
2613 }
2614
2615 /* Start swing calculation */
2616 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2617 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2618 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2619
2620 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2621 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2622 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2623
2624 /* LRC Bypass */
2625 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2626 val |= DPIO_LRC_BYPASS;
2627 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2628
2629 mutex_unlock(&dev_priv->dpio_lock);
2630
2631 return 0;
2632 }
2633
2634 static void
2635 intel_get_adjust_train(struct intel_dp *intel_dp,
2636 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2637 {
2638 uint8_t v = 0;
2639 uint8_t p = 0;
2640 int lane;
2641 uint8_t voltage_max;
2642 uint8_t preemph_max;
2643
2644 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2645 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2646 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2647
2648 if (this_v > v)
2649 v = this_v;
2650 if (this_p > p)
2651 p = this_p;
2652 }
2653
2654 voltage_max = intel_dp_voltage_max(intel_dp);
2655 if (v >= voltage_max)
2656 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2657
2658 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2659 if (p >= preemph_max)
2660 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2661
2662 for (lane = 0; lane < 4; lane++)
2663 intel_dp->train_set[lane] = v | p;
2664 }
2665
2666 static uint32_t
2667 intel_gen4_signal_levels(uint8_t train_set)
2668 {
2669 uint32_t signal_levels = 0;
2670
2671 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2672 case DP_TRAIN_VOLTAGE_SWING_400:
2673 default:
2674 signal_levels |= DP_VOLTAGE_0_4;
2675 break;
2676 case DP_TRAIN_VOLTAGE_SWING_600:
2677 signal_levels |= DP_VOLTAGE_0_6;
2678 break;
2679 case DP_TRAIN_VOLTAGE_SWING_800:
2680 signal_levels |= DP_VOLTAGE_0_8;
2681 break;
2682 case DP_TRAIN_VOLTAGE_SWING_1200:
2683 signal_levels |= DP_VOLTAGE_1_2;
2684 break;
2685 }
2686 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2687 case DP_TRAIN_PRE_EMPHASIS_0:
2688 default:
2689 signal_levels |= DP_PRE_EMPHASIS_0;
2690 break;
2691 case DP_TRAIN_PRE_EMPHASIS_3_5:
2692 signal_levels |= DP_PRE_EMPHASIS_3_5;
2693 break;
2694 case DP_TRAIN_PRE_EMPHASIS_6:
2695 signal_levels |= DP_PRE_EMPHASIS_6;
2696 break;
2697 case DP_TRAIN_PRE_EMPHASIS_9_5:
2698 signal_levels |= DP_PRE_EMPHASIS_9_5;
2699 break;
2700 }
2701 return signal_levels;
2702 }
2703
2704 /* Gen6's DP voltage swing and pre-emphasis control */
2705 static uint32_t
2706 intel_gen6_edp_signal_levels(uint8_t train_set)
2707 {
2708 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2709 DP_TRAIN_PRE_EMPHASIS_MASK);
2710 switch (signal_levels) {
2711 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2712 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2713 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2714 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2715 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2716 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2717 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2718 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2719 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2720 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2721 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2722 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2723 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2724 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2725 default:
2726 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2727 "0x%x\n", signal_levels);
2728 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2729 }
2730 }
2731
2732 /* Gen7's DP voltage swing and pre-emphasis control */
2733 static uint32_t
2734 intel_gen7_edp_signal_levels(uint8_t train_set)
2735 {
2736 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2737 DP_TRAIN_PRE_EMPHASIS_MASK);
2738 switch (signal_levels) {
2739 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2740 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2741 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2742 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2743 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2744 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2745
2746 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2747 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2748 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2749 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2750
2751 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2752 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2753 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2754 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2755
2756 default:
2757 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2758 "0x%x\n", signal_levels);
2759 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2760 }
2761 }
2762
2763 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2764 static uint32_t
2765 intel_hsw_signal_levels(uint8_t train_set)
2766 {
2767 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2768 DP_TRAIN_PRE_EMPHASIS_MASK);
2769 switch (signal_levels) {
2770 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2771 return DDI_BUF_EMP_400MV_0DB_HSW;
2772 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2773 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2774 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2775 return DDI_BUF_EMP_400MV_6DB_HSW;
2776 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2777 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2778
2779 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2780 return DDI_BUF_EMP_600MV_0DB_HSW;
2781 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2782 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2783 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2784 return DDI_BUF_EMP_600MV_6DB_HSW;
2785
2786 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2787 return DDI_BUF_EMP_800MV_0DB_HSW;
2788 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2789 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2790 default:
2791 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2792 "0x%x\n", signal_levels);
2793 return DDI_BUF_EMP_400MV_0DB_HSW;
2794 }
2795 }
2796
2797 /* Properly updates "DP" with the correct signal levels. */
2798 static void
2799 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2800 {
2801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2802 enum port port = intel_dig_port->port;
2803 struct drm_device *dev = intel_dig_port->base.base.dev;
2804 uint32_t signal_levels, mask;
2805 uint8_t train_set = intel_dp->train_set[0];
2806
2807 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2808 signal_levels = intel_hsw_signal_levels(train_set);
2809 mask = DDI_BUF_EMP_MASK;
2810 } else if (IS_CHERRYVIEW(dev)) {
2811 signal_levels = intel_chv_signal_levels(intel_dp);
2812 mask = 0;
2813 } else if (IS_VALLEYVIEW(dev)) {
2814 signal_levels = intel_vlv_signal_levels(intel_dp);
2815 mask = 0;
2816 } else if (IS_GEN7(dev) && port == PORT_A) {
2817 signal_levels = intel_gen7_edp_signal_levels(train_set);
2818 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2819 } else if (IS_GEN6(dev) && port == PORT_A) {
2820 signal_levels = intel_gen6_edp_signal_levels(train_set);
2821 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2822 } else {
2823 signal_levels = intel_gen4_signal_levels(train_set);
2824 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2825 }
2826
2827 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2828
2829 *DP = (*DP & ~mask) | signal_levels;
2830 }
2831
2832 static bool
2833 intel_dp_set_link_train(struct intel_dp *intel_dp,
2834 uint32_t *DP,
2835 uint8_t dp_train_pat)
2836 {
2837 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2838 struct drm_device *dev = intel_dig_port->base.base.dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 enum port port = intel_dig_port->port;
2841 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2842 int ret, len;
2843
2844 if (HAS_DDI(dev)) {
2845 uint32_t temp = I915_READ(DP_TP_CTL(port));
2846
2847 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2848 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2849 else
2850 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2851
2852 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2853 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2854 case DP_TRAINING_PATTERN_DISABLE:
2855 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2856
2857 break;
2858 case DP_TRAINING_PATTERN_1:
2859 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2860 break;
2861 case DP_TRAINING_PATTERN_2:
2862 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2863 break;
2864 case DP_TRAINING_PATTERN_3:
2865 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2866 break;
2867 }
2868 I915_WRITE(DP_TP_CTL(port), temp);
2869
2870 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2871 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2872
2873 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2874 case DP_TRAINING_PATTERN_DISABLE:
2875 *DP |= DP_LINK_TRAIN_OFF_CPT;
2876 break;
2877 case DP_TRAINING_PATTERN_1:
2878 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2879 break;
2880 case DP_TRAINING_PATTERN_2:
2881 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2882 break;
2883 case DP_TRAINING_PATTERN_3:
2884 DRM_ERROR("DP training pattern 3 not supported\n");
2885 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2886 break;
2887 }
2888
2889 } else {
2890 *DP &= ~DP_LINK_TRAIN_MASK;
2891
2892 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2893 case DP_TRAINING_PATTERN_DISABLE:
2894 *DP |= DP_LINK_TRAIN_OFF;
2895 break;
2896 case DP_TRAINING_PATTERN_1:
2897 *DP |= DP_LINK_TRAIN_PAT_1;
2898 break;
2899 case DP_TRAINING_PATTERN_2:
2900 *DP |= DP_LINK_TRAIN_PAT_2;
2901 break;
2902 case DP_TRAINING_PATTERN_3:
2903 DRM_ERROR("DP training pattern 3 not supported\n");
2904 *DP |= DP_LINK_TRAIN_PAT_2;
2905 break;
2906 }
2907 }
2908
2909 I915_WRITE(intel_dp->output_reg, *DP);
2910 POSTING_READ(intel_dp->output_reg);
2911
2912 buf[0] = dp_train_pat;
2913 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2914 DP_TRAINING_PATTERN_DISABLE) {
2915 /* don't write DP_TRAINING_LANEx_SET on disable */
2916 len = 1;
2917 } else {
2918 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2919 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2920 len = intel_dp->lane_count + 1;
2921 }
2922
2923 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2924 buf, len);
2925
2926 return ret == len;
2927 }
2928
2929 static bool
2930 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2931 uint8_t dp_train_pat)
2932 {
2933 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2934 intel_dp_set_signal_levels(intel_dp, DP);
2935 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2936 }
2937
2938 static bool
2939 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2940 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2941 {
2942 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2943 struct drm_device *dev = intel_dig_port->base.base.dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 int ret;
2946
2947 intel_get_adjust_train(intel_dp, link_status);
2948 intel_dp_set_signal_levels(intel_dp, DP);
2949
2950 I915_WRITE(intel_dp->output_reg, *DP);
2951 POSTING_READ(intel_dp->output_reg);
2952
2953 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2954 intel_dp->train_set, intel_dp->lane_count);
2955
2956 return ret == intel_dp->lane_count;
2957 }
2958
2959 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2960 {
2961 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2962 struct drm_device *dev = intel_dig_port->base.base.dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 enum port port = intel_dig_port->port;
2965 uint32_t val;
2966
2967 if (!HAS_DDI(dev))
2968 return;
2969
2970 val = I915_READ(DP_TP_CTL(port));
2971 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2972 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2973 I915_WRITE(DP_TP_CTL(port), val);
2974
2975 /*
2976 * On PORT_A we can have only eDP in SST mode. There the only reason
2977 * we need to set idle transmission mode is to work around a HW issue
2978 * where we enable the pipe while not in idle link-training mode.
2979 * In this case there is requirement to wait for a minimum number of
2980 * idle patterns to be sent.
2981 */
2982 if (port == PORT_A)
2983 return;
2984
2985 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2986 1))
2987 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2988 }
2989
2990 /* Enable corresponding port and start training pattern 1 */
2991 void
2992 intel_dp_start_link_train(struct intel_dp *intel_dp)
2993 {
2994 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2995 struct drm_device *dev = encoder->dev;
2996 int i;
2997 uint8_t voltage;
2998 int voltage_tries, loop_tries;
2999 uint32_t DP = intel_dp->DP;
3000 uint8_t link_config[2];
3001
3002 if (HAS_DDI(dev))
3003 intel_ddi_prepare_link_retrain(encoder);
3004
3005 /* Write the link configuration data */
3006 link_config[0] = intel_dp->link_bw;
3007 link_config[1] = intel_dp->lane_count;
3008 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3009 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3010 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3011
3012 link_config[0] = 0;
3013 link_config[1] = DP_SET_ANSI_8B10B;
3014 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3015
3016 DP |= DP_PORT_EN;
3017
3018 /* clock recovery */
3019 if (!intel_dp_reset_link_train(intel_dp, &DP,
3020 DP_TRAINING_PATTERN_1 |
3021 DP_LINK_SCRAMBLING_DISABLE)) {
3022 DRM_ERROR("failed to enable link training\n");
3023 return;
3024 }
3025
3026 voltage = 0xff;
3027 voltage_tries = 0;
3028 loop_tries = 0;
3029 for (;;) {
3030 uint8_t link_status[DP_LINK_STATUS_SIZE];
3031
3032 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3033 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3034 DRM_ERROR("failed to get link status\n");
3035 break;
3036 }
3037
3038 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3039 DRM_DEBUG_KMS("clock recovery OK\n");
3040 break;
3041 }
3042
3043 /* Check to see if we've tried the max voltage */
3044 for (i = 0; i < intel_dp->lane_count; i++)
3045 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3046 break;
3047 if (i == intel_dp->lane_count) {
3048 ++loop_tries;
3049 if (loop_tries == 5) {
3050 DRM_ERROR("too many full retries, give up\n");
3051 break;
3052 }
3053 intel_dp_reset_link_train(intel_dp, &DP,
3054 DP_TRAINING_PATTERN_1 |
3055 DP_LINK_SCRAMBLING_DISABLE);
3056 voltage_tries = 0;
3057 continue;
3058 }
3059
3060 /* Check to see if we've tried the same voltage 5 times */
3061 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3062 ++voltage_tries;
3063 if (voltage_tries == 5) {
3064 DRM_ERROR("too many voltage retries, give up\n");
3065 break;
3066 }
3067 } else
3068 voltage_tries = 0;
3069 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3070
3071 /* Update training set as requested by target */
3072 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3073 DRM_ERROR("failed to update link training\n");
3074 break;
3075 }
3076 }
3077
3078 intel_dp->DP = DP;
3079 }
3080
3081 void
3082 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3083 {
3084 bool channel_eq = false;
3085 int tries, cr_tries;
3086 uint32_t DP = intel_dp->DP;
3087 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3088
3089 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3090 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3091 training_pattern = DP_TRAINING_PATTERN_3;
3092
3093 /* channel equalization */
3094 if (!intel_dp_set_link_train(intel_dp, &DP,
3095 training_pattern |
3096 DP_LINK_SCRAMBLING_DISABLE)) {
3097 DRM_ERROR("failed to start channel equalization\n");
3098 return;
3099 }
3100
3101 tries = 0;
3102 cr_tries = 0;
3103 channel_eq = false;
3104 for (;;) {
3105 uint8_t link_status[DP_LINK_STATUS_SIZE];
3106
3107 if (cr_tries > 5) {
3108 DRM_ERROR("failed to train DP, aborting\n");
3109 break;
3110 }
3111
3112 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3113 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3114 DRM_ERROR("failed to get link status\n");
3115 break;
3116 }
3117
3118 /* Make sure clock is still ok */
3119 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3120 intel_dp_start_link_train(intel_dp);
3121 intel_dp_set_link_train(intel_dp, &DP,
3122 training_pattern |
3123 DP_LINK_SCRAMBLING_DISABLE);
3124 cr_tries++;
3125 continue;
3126 }
3127
3128 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3129 channel_eq = true;
3130 break;
3131 }
3132
3133 /* Try 5 times, then try clock recovery if that fails */
3134 if (tries > 5) {
3135 intel_dp_link_down(intel_dp);
3136 intel_dp_start_link_train(intel_dp);
3137 intel_dp_set_link_train(intel_dp, &DP,
3138 training_pattern |
3139 DP_LINK_SCRAMBLING_DISABLE);
3140 tries = 0;
3141 cr_tries++;
3142 continue;
3143 }
3144
3145 /* Update training set as requested by target */
3146 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3147 DRM_ERROR("failed to update link training\n");
3148 break;
3149 }
3150 ++tries;
3151 }
3152
3153 intel_dp_set_idle_link_train(intel_dp);
3154
3155 intel_dp->DP = DP;
3156
3157 if (channel_eq)
3158 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3159
3160 }
3161
3162 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3163 {
3164 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3165 DP_TRAINING_PATTERN_DISABLE);
3166 }
3167
3168 static void
3169 intel_dp_link_down(struct intel_dp *intel_dp)
3170 {
3171 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3172 enum port port = intel_dig_port->port;
3173 struct drm_device *dev = intel_dig_port->base.base.dev;
3174 struct drm_i915_private *dev_priv = dev->dev_private;
3175 struct intel_crtc *intel_crtc =
3176 to_intel_crtc(intel_dig_port->base.base.crtc);
3177 uint32_t DP = intel_dp->DP;
3178
3179 if (WARN_ON(HAS_DDI(dev)))
3180 return;
3181
3182 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3183 return;
3184
3185 DRM_DEBUG_KMS("\n");
3186
3187 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3188 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3189 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3190 } else {
3191 DP &= ~DP_LINK_TRAIN_MASK;
3192 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3193 }
3194 POSTING_READ(intel_dp->output_reg);
3195
3196 if (HAS_PCH_IBX(dev) &&
3197 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3198 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3199
3200 /* Hardware workaround: leaving our transcoder select
3201 * set to transcoder B while it's off will prevent the
3202 * corresponding HDMI output on transcoder A.
3203 *
3204 * Combine this with another hardware workaround:
3205 * transcoder select bit can only be cleared while the
3206 * port is enabled.
3207 */
3208 DP &= ~DP_PIPEB_SELECT;
3209 I915_WRITE(intel_dp->output_reg, DP);
3210
3211 /* Changes to enable or select take place the vblank
3212 * after being written.
3213 */
3214 if (WARN_ON(crtc == NULL)) {
3215 /* We should never try to disable a port without a crtc
3216 * attached. For paranoia keep the code around for a
3217 * bit. */
3218 POSTING_READ(intel_dp->output_reg);
3219 msleep(50);
3220 } else
3221 intel_wait_for_vblank(dev, intel_crtc->pipe);
3222 }
3223
3224 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3225 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3226 POSTING_READ(intel_dp->output_reg);
3227 msleep(intel_dp->panel_power_down_delay);
3228 }
3229
3230 static bool
3231 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3232 {
3233 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3234 struct drm_device *dev = dig_port->base.base.dev;
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3236
3237 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3238
3239 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3240 sizeof(intel_dp->dpcd)) < 0)
3241 return false; /* aux transfer failed */
3242
3243 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3244 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3245 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3246
3247 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3248 return false; /* DPCD not present */
3249
3250 /* Check if the panel supports PSR */
3251 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3252 if (is_edp(intel_dp)) {
3253 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3254 intel_dp->psr_dpcd,
3255 sizeof(intel_dp->psr_dpcd));
3256 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3257 dev_priv->psr.sink_support = true;
3258 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3259 }
3260 }
3261
3262 /* Training Pattern 3 support */
3263 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3264 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3265 intel_dp->use_tps3 = true;
3266 DRM_DEBUG_KMS("Displayport TPS3 supported");
3267 } else
3268 intel_dp->use_tps3 = false;
3269
3270 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3271 DP_DWN_STRM_PORT_PRESENT))
3272 return true; /* native DP sink */
3273
3274 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3275 return true; /* no per-port downstream info */
3276
3277 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3278 intel_dp->downstream_ports,
3279 DP_MAX_DOWNSTREAM_PORTS) < 0)
3280 return false; /* downstream port status fetch failed */
3281
3282 return true;
3283 }
3284
3285 static void
3286 intel_dp_probe_oui(struct intel_dp *intel_dp)
3287 {
3288 u8 buf[3];
3289
3290 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3291 return;
3292
3293 intel_edp_panel_vdd_on(intel_dp);
3294
3295 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3296 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3297 buf[0], buf[1], buf[2]);
3298
3299 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3300 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3301 buf[0], buf[1], buf[2]);
3302
3303 edp_panel_vdd_off(intel_dp, false);
3304 }
3305
3306 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3307 {
3308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3309 struct drm_device *dev = intel_dig_port->base.base.dev;
3310 struct intel_crtc *intel_crtc =
3311 to_intel_crtc(intel_dig_port->base.base.crtc);
3312 u8 buf[1];
3313
3314 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3315 return -EAGAIN;
3316
3317 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3318 return -ENOTTY;
3319
3320 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3321 DP_TEST_SINK_START) < 0)
3322 return -EAGAIN;
3323
3324 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3325 intel_wait_for_vblank(dev, intel_crtc->pipe);
3326 intel_wait_for_vblank(dev, intel_crtc->pipe);
3327
3328 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3329 return -EAGAIN;
3330
3331 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3332 return 0;
3333 }
3334
3335 static bool
3336 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3337 {
3338 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3339 DP_DEVICE_SERVICE_IRQ_VECTOR,
3340 sink_irq_vector, 1) == 1;
3341 }
3342
3343 static void
3344 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3345 {
3346 /* NAK by default */
3347 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3348 }
3349
3350 /*
3351 * According to DP spec
3352 * 5.1.2:
3353 * 1. Read DPCD
3354 * 2. Configure link according to Receiver Capabilities
3355 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3356 * 4. Check link status on receipt of hot-plug interrupt
3357 */
3358
3359 void
3360 intel_dp_check_link_status(struct intel_dp *intel_dp)
3361 {
3362 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3363 u8 sink_irq_vector;
3364 u8 link_status[DP_LINK_STATUS_SIZE];
3365
3366 /* FIXME: This access isn't protected by any locks. */
3367 if (!intel_encoder->connectors_active)
3368 return;
3369
3370 if (WARN_ON(!intel_encoder->base.crtc))
3371 return;
3372
3373 /* Try to read receiver status if the link appears to be up */
3374 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3375 return;
3376 }
3377
3378 /* Now read the DPCD to see if it's actually running */
3379 if (!intel_dp_get_dpcd(intel_dp)) {
3380 return;
3381 }
3382
3383 /* Try to read the source of the interrupt */
3384 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3385 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3386 /* Clear interrupt source */
3387 drm_dp_dpcd_writeb(&intel_dp->aux,
3388 DP_DEVICE_SERVICE_IRQ_VECTOR,
3389 sink_irq_vector);
3390
3391 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3392 intel_dp_handle_test_request(intel_dp);
3393 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3394 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3395 }
3396
3397 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3398 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3399 intel_encoder->base.name);
3400 intel_dp_start_link_train(intel_dp);
3401 intel_dp_complete_link_train(intel_dp);
3402 intel_dp_stop_link_train(intel_dp);
3403 }
3404 }
3405
3406 /* XXX this is probably wrong for multiple downstream ports */
3407 static enum drm_connector_status
3408 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3409 {
3410 uint8_t *dpcd = intel_dp->dpcd;
3411 uint8_t type;
3412
3413 if (!intel_dp_get_dpcd(intel_dp))
3414 return connector_status_disconnected;
3415
3416 /* if there's no downstream port, we're done */
3417 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3418 return connector_status_connected;
3419
3420 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3421 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3422 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3423 uint8_t reg;
3424
3425 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3426 &reg, 1) < 0)
3427 return connector_status_unknown;
3428
3429 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3430 : connector_status_disconnected;
3431 }
3432
3433 /* If no HPD, poke DDC gently */
3434 if (drm_probe_ddc(&intel_dp->aux.ddc))
3435 return connector_status_connected;
3436
3437 /* Well we tried, say unknown for unreliable port types */
3438 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3439 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3440 if (type == DP_DS_PORT_TYPE_VGA ||
3441 type == DP_DS_PORT_TYPE_NON_EDID)
3442 return connector_status_unknown;
3443 } else {
3444 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3445 DP_DWN_STRM_PORT_TYPE_MASK;
3446 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3447 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3448 return connector_status_unknown;
3449 }
3450
3451 /* Anything else is out of spec, warn and ignore */
3452 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3453 return connector_status_disconnected;
3454 }
3455
3456 static enum drm_connector_status
3457 ironlake_dp_detect(struct intel_dp *intel_dp)
3458 {
3459 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3460 struct drm_i915_private *dev_priv = dev->dev_private;
3461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3462 enum drm_connector_status status;
3463
3464 /* Can't disconnect eDP, but you can close the lid... */
3465 if (is_edp(intel_dp)) {
3466 status = intel_panel_detect(dev);
3467 if (status == connector_status_unknown)
3468 status = connector_status_connected;
3469 return status;
3470 }
3471
3472 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3473 return connector_status_disconnected;
3474
3475 return intel_dp_detect_dpcd(intel_dp);
3476 }
3477
3478 static enum drm_connector_status
3479 g4x_dp_detect(struct intel_dp *intel_dp)
3480 {
3481 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3484 uint32_t bit;
3485
3486 /* Can't disconnect eDP, but you can close the lid... */
3487 if (is_edp(intel_dp)) {
3488 enum drm_connector_status status;
3489
3490 status = intel_panel_detect(dev);
3491 if (status == connector_status_unknown)
3492 status = connector_status_connected;
3493 return status;
3494 }
3495
3496 if (IS_VALLEYVIEW(dev)) {
3497 switch (intel_dig_port->port) {
3498 case PORT_B:
3499 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3500 break;
3501 case PORT_C:
3502 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3503 break;
3504 case PORT_D:
3505 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3506 break;
3507 default:
3508 return connector_status_unknown;
3509 }
3510 } else {
3511 switch (intel_dig_port->port) {
3512 case PORT_B:
3513 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3514 break;
3515 case PORT_C:
3516 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3517 break;
3518 case PORT_D:
3519 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3520 break;
3521 default:
3522 return connector_status_unknown;
3523 }
3524 }
3525
3526 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3527 return connector_status_disconnected;
3528
3529 return intel_dp_detect_dpcd(intel_dp);
3530 }
3531
3532 static struct edid *
3533 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3534 {
3535 struct intel_connector *intel_connector = to_intel_connector(connector);
3536
3537 /* use cached edid if we have one */
3538 if (intel_connector->edid) {
3539 /* invalid edid */
3540 if (IS_ERR(intel_connector->edid))
3541 return NULL;
3542
3543 return drm_edid_duplicate(intel_connector->edid);
3544 }
3545
3546 return drm_get_edid(connector, adapter);
3547 }
3548
3549 static int
3550 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3551 {
3552 struct intel_connector *intel_connector = to_intel_connector(connector);
3553
3554 /* use cached edid if we have one */
3555 if (intel_connector->edid) {
3556 /* invalid edid */
3557 if (IS_ERR(intel_connector->edid))
3558 return 0;
3559
3560 return intel_connector_update_modes(connector,
3561 intel_connector->edid);
3562 }
3563
3564 return intel_ddc_get_modes(connector, adapter);
3565 }
3566
3567 static enum drm_connector_status
3568 intel_dp_detect(struct drm_connector *connector, bool force)
3569 {
3570 struct intel_dp *intel_dp = intel_attached_dp(connector);
3571 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3572 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3573 struct drm_device *dev = connector->dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 enum drm_connector_status status;
3576 enum intel_display_power_domain power_domain;
3577 struct edid *edid = NULL;
3578
3579 intel_runtime_pm_get(dev_priv);
3580
3581 power_domain = intel_display_port_power_domain(intel_encoder);
3582 intel_display_power_get(dev_priv, power_domain);
3583
3584 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3585 connector->base.id, connector->name);
3586
3587 intel_dp->has_audio = false;
3588
3589 if (HAS_PCH_SPLIT(dev))
3590 status = ironlake_dp_detect(intel_dp);
3591 else
3592 status = g4x_dp_detect(intel_dp);
3593
3594 if (status != connector_status_connected)
3595 goto out;
3596
3597 intel_dp_probe_oui(intel_dp);
3598
3599 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3600 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3601 } else {
3602 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3603 if (edid) {
3604 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3605 kfree(edid);
3606 }
3607 }
3608
3609 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3610 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3611 status = connector_status_connected;
3612
3613 out:
3614 intel_display_power_put(dev_priv, power_domain);
3615
3616 intel_runtime_pm_put(dev_priv);
3617
3618 return status;
3619 }
3620
3621 static int intel_dp_get_modes(struct drm_connector *connector)
3622 {
3623 struct intel_dp *intel_dp = intel_attached_dp(connector);
3624 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3625 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3626 struct intel_connector *intel_connector = to_intel_connector(connector);
3627 struct drm_device *dev = connector->dev;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 enum intel_display_power_domain power_domain;
3630 int ret;
3631
3632 /* We should parse the EDID data and find out if it has an audio sink
3633 */
3634
3635 power_domain = intel_display_port_power_domain(intel_encoder);
3636 intel_display_power_get(dev_priv, power_domain);
3637
3638 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3639 intel_display_power_put(dev_priv, power_domain);
3640 if (ret)
3641 return ret;
3642
3643 /* if eDP has no EDID, fall back to fixed mode */
3644 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3645 struct drm_display_mode *mode;
3646 mode = drm_mode_duplicate(dev,
3647 intel_connector->panel.fixed_mode);
3648 if (mode) {
3649 drm_mode_probed_add(connector, mode);
3650 return 1;
3651 }
3652 }
3653 return 0;
3654 }
3655
3656 static bool
3657 intel_dp_detect_audio(struct drm_connector *connector)
3658 {
3659 struct intel_dp *intel_dp = intel_attached_dp(connector);
3660 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3661 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3662 struct drm_device *dev = connector->dev;
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664 enum intel_display_power_domain power_domain;
3665 struct edid *edid;
3666 bool has_audio = false;
3667
3668 power_domain = intel_display_port_power_domain(intel_encoder);
3669 intel_display_power_get(dev_priv, power_domain);
3670
3671 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3672 if (edid) {
3673 has_audio = drm_detect_monitor_audio(edid);
3674 kfree(edid);
3675 }
3676
3677 intel_display_power_put(dev_priv, power_domain);
3678
3679 return has_audio;
3680 }
3681
3682 static int
3683 intel_dp_set_property(struct drm_connector *connector,
3684 struct drm_property *property,
3685 uint64_t val)
3686 {
3687 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3688 struct intel_connector *intel_connector = to_intel_connector(connector);
3689 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3690 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3691 int ret;
3692
3693 ret = drm_object_property_set_value(&connector->base, property, val);
3694 if (ret)
3695 return ret;
3696
3697 if (property == dev_priv->force_audio_property) {
3698 int i = val;
3699 bool has_audio;
3700
3701 if (i == intel_dp->force_audio)
3702 return 0;
3703
3704 intel_dp->force_audio = i;
3705
3706 if (i == HDMI_AUDIO_AUTO)
3707 has_audio = intel_dp_detect_audio(connector);
3708 else
3709 has_audio = (i == HDMI_AUDIO_ON);
3710
3711 if (has_audio == intel_dp->has_audio)
3712 return 0;
3713
3714 intel_dp->has_audio = has_audio;
3715 goto done;
3716 }
3717
3718 if (property == dev_priv->broadcast_rgb_property) {
3719 bool old_auto = intel_dp->color_range_auto;
3720 uint32_t old_range = intel_dp->color_range;
3721
3722 switch (val) {
3723 case INTEL_BROADCAST_RGB_AUTO:
3724 intel_dp->color_range_auto = true;
3725 break;
3726 case INTEL_BROADCAST_RGB_FULL:
3727 intel_dp->color_range_auto = false;
3728 intel_dp->color_range = 0;
3729 break;
3730 case INTEL_BROADCAST_RGB_LIMITED:
3731 intel_dp->color_range_auto = false;
3732 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3733 break;
3734 default:
3735 return -EINVAL;
3736 }
3737
3738 if (old_auto == intel_dp->color_range_auto &&
3739 old_range == intel_dp->color_range)
3740 return 0;
3741
3742 goto done;
3743 }
3744
3745 if (is_edp(intel_dp) &&
3746 property == connector->dev->mode_config.scaling_mode_property) {
3747 if (val == DRM_MODE_SCALE_NONE) {
3748 DRM_DEBUG_KMS("no scaling not supported\n");
3749 return -EINVAL;
3750 }
3751
3752 if (intel_connector->panel.fitting_mode == val) {
3753 /* the eDP scaling property is not changed */
3754 return 0;
3755 }
3756 intel_connector->panel.fitting_mode = val;
3757
3758 goto done;
3759 }
3760
3761 return -EINVAL;
3762
3763 done:
3764 if (intel_encoder->base.crtc)
3765 intel_crtc_restore_mode(intel_encoder->base.crtc);
3766
3767 return 0;
3768 }
3769
3770 static void
3771 intel_dp_connector_destroy(struct drm_connector *connector)
3772 {
3773 struct intel_connector *intel_connector = to_intel_connector(connector);
3774
3775 if (!IS_ERR_OR_NULL(intel_connector->edid))
3776 kfree(intel_connector->edid);
3777
3778 /* Can't call is_edp() since the encoder may have been destroyed
3779 * already. */
3780 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3781 intel_panel_fini(&intel_connector->panel);
3782
3783 drm_connector_cleanup(connector);
3784 kfree(connector);
3785 }
3786
3787 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3788 {
3789 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3790 struct intel_dp *intel_dp = &intel_dig_port->dp;
3791 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3792
3793 drm_dp_aux_unregister(&intel_dp->aux);
3794 drm_encoder_cleanup(encoder);
3795 if (is_edp(intel_dp)) {
3796 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3797 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3798 edp_panel_vdd_off_sync(intel_dp);
3799 drm_modeset_unlock(&dev->mode_config.connection_mutex);
3800 }
3801 kfree(intel_dig_port);
3802 }
3803
3804 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3805 .dpms = intel_connector_dpms,
3806 .detect = intel_dp_detect,
3807 .fill_modes = drm_helper_probe_single_connector_modes,
3808 .set_property = intel_dp_set_property,
3809 .destroy = intel_dp_connector_destroy,
3810 };
3811
3812 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3813 .get_modes = intel_dp_get_modes,
3814 .mode_valid = intel_dp_mode_valid,
3815 .best_encoder = intel_best_encoder,
3816 };
3817
3818 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3819 .destroy = intel_dp_encoder_destroy,
3820 };
3821
3822 static void
3823 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3824 {
3825 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3826
3827 intel_dp_check_link_status(intel_dp);
3828 }
3829
3830 bool
3831 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
3832 {
3833 struct intel_dp *intel_dp = &intel_dig_port->dp;
3834
3835 if (long_hpd)
3836 return true;
3837
3838 /*
3839 * we'll check the link status via the normal hot plug path later -
3840 * but for short hpds we should check it now
3841 */
3842 intel_dp_check_link_status(intel_dp);
3843 return false;
3844 }
3845
3846 /* Return which DP Port should be selected for Transcoder DP control */
3847 int
3848 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3849 {
3850 struct drm_device *dev = crtc->dev;
3851 struct intel_encoder *intel_encoder;
3852 struct intel_dp *intel_dp;
3853
3854 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3855 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3856
3857 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3858 intel_encoder->type == INTEL_OUTPUT_EDP)
3859 return intel_dp->output_reg;
3860 }
3861
3862 return -1;
3863 }
3864
3865 /* check the VBT to see whether the eDP is on DP-D port */
3866 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3867 {
3868 struct drm_i915_private *dev_priv = dev->dev_private;
3869 union child_device_config *p_child;
3870 int i;
3871 static const short port_mapping[] = {
3872 [PORT_B] = PORT_IDPB,
3873 [PORT_C] = PORT_IDPC,
3874 [PORT_D] = PORT_IDPD,
3875 };
3876
3877 if (port == PORT_A)
3878 return true;
3879
3880 if (!dev_priv->vbt.child_dev_num)
3881 return false;
3882
3883 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3884 p_child = dev_priv->vbt.child_dev + i;
3885
3886 if (p_child->common.dvo_port == port_mapping[port] &&
3887 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3888 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3889 return true;
3890 }
3891 return false;
3892 }
3893
3894 static void
3895 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3896 {
3897 struct intel_connector *intel_connector = to_intel_connector(connector);
3898
3899 intel_attach_force_audio_property(connector);
3900 intel_attach_broadcast_rgb_property(connector);
3901 intel_dp->color_range_auto = true;
3902
3903 if (is_edp(intel_dp)) {
3904 drm_mode_create_scaling_mode_property(connector->dev);
3905 drm_object_attach_property(
3906 &connector->base,
3907 connector->dev->mode_config.scaling_mode_property,
3908 DRM_MODE_SCALE_ASPECT);
3909 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3910 }
3911 }
3912
3913 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3914 {
3915 intel_dp->last_power_cycle = jiffies;
3916 intel_dp->last_power_on = jiffies;
3917 intel_dp->last_backlight_off = jiffies;
3918 }
3919
3920 static void
3921 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3922 struct intel_dp *intel_dp,
3923 struct edp_power_seq *out)
3924 {
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 struct edp_power_seq cur, vbt, spec, final;
3927 u32 pp_on, pp_off, pp_div, pp;
3928 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3929
3930 if (HAS_PCH_SPLIT(dev)) {
3931 pp_ctrl_reg = PCH_PP_CONTROL;
3932 pp_on_reg = PCH_PP_ON_DELAYS;
3933 pp_off_reg = PCH_PP_OFF_DELAYS;
3934 pp_div_reg = PCH_PP_DIVISOR;
3935 } else {
3936 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3937
3938 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3939 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3940 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3941 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3942 }
3943
3944 /* Workaround: Need to write PP_CONTROL with the unlock key as
3945 * the very first thing. */
3946 pp = ironlake_get_pp_control(intel_dp);
3947 I915_WRITE(pp_ctrl_reg, pp);
3948
3949 pp_on = I915_READ(pp_on_reg);
3950 pp_off = I915_READ(pp_off_reg);
3951 pp_div = I915_READ(pp_div_reg);
3952
3953 /* Pull timing values out of registers */
3954 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3955 PANEL_POWER_UP_DELAY_SHIFT;
3956
3957 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3958 PANEL_LIGHT_ON_DELAY_SHIFT;
3959
3960 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3961 PANEL_LIGHT_OFF_DELAY_SHIFT;
3962
3963 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3964 PANEL_POWER_DOWN_DELAY_SHIFT;
3965
3966 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3967 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3968
3969 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3970 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3971
3972 vbt = dev_priv->vbt.edp_pps;
3973
3974 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3975 * our hw here, which are all in 100usec. */
3976 spec.t1_t3 = 210 * 10;
3977 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3978 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3979 spec.t10 = 500 * 10;
3980 /* This one is special and actually in units of 100ms, but zero
3981 * based in the hw (so we need to add 100 ms). But the sw vbt
3982 * table multiplies it with 1000 to make it in units of 100usec,
3983 * too. */
3984 spec.t11_t12 = (510 + 100) * 10;
3985
3986 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3987 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3988
3989 /* Use the max of the register settings and vbt. If both are
3990 * unset, fall back to the spec limits. */
3991 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3992 spec.field : \
3993 max(cur.field, vbt.field))
3994 assign_final(t1_t3);
3995 assign_final(t8);
3996 assign_final(t9);
3997 assign_final(t10);
3998 assign_final(t11_t12);
3999 #undef assign_final
4000
4001 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4002 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4003 intel_dp->backlight_on_delay = get_delay(t8);
4004 intel_dp->backlight_off_delay = get_delay(t9);
4005 intel_dp->panel_power_down_delay = get_delay(t10);
4006 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4007 #undef get_delay
4008
4009 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4010 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4011 intel_dp->panel_power_cycle_delay);
4012
4013 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4014 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4015
4016 if (out)
4017 *out = final;
4018 }
4019
4020 static void
4021 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4022 struct intel_dp *intel_dp,
4023 struct edp_power_seq *seq)
4024 {
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 u32 pp_on, pp_off, pp_div, port_sel = 0;
4027 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4028 int pp_on_reg, pp_off_reg, pp_div_reg;
4029
4030 if (HAS_PCH_SPLIT(dev)) {
4031 pp_on_reg = PCH_PP_ON_DELAYS;
4032 pp_off_reg = PCH_PP_OFF_DELAYS;
4033 pp_div_reg = PCH_PP_DIVISOR;
4034 } else {
4035 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4036
4037 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4038 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4039 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4040 }
4041
4042 /*
4043 * And finally store the new values in the power sequencer. The
4044 * backlight delays are set to 1 because we do manual waits on them. For
4045 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4046 * we'll end up waiting for the backlight off delay twice: once when we
4047 * do the manual sleep, and once when we disable the panel and wait for
4048 * the PP_STATUS bit to become zero.
4049 */
4050 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4051 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4052 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4053 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4054 /* Compute the divisor for the pp clock, simply match the Bspec
4055 * formula. */
4056 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4057 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4058 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4059
4060 /* Haswell doesn't have any port selection bits for the panel
4061 * power sequencer any more. */
4062 if (IS_VALLEYVIEW(dev)) {
4063 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4064 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4065 else
4066 port_sel = PANEL_PORT_SELECT_DPC_VLV;
4067 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4068 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4069 port_sel = PANEL_PORT_SELECT_DPA;
4070 else
4071 port_sel = PANEL_PORT_SELECT_DPD;
4072 }
4073
4074 pp_on |= port_sel;
4075
4076 I915_WRITE(pp_on_reg, pp_on);
4077 I915_WRITE(pp_off_reg, pp_off);
4078 I915_WRITE(pp_div_reg, pp_div);
4079
4080 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4081 I915_READ(pp_on_reg),
4082 I915_READ(pp_off_reg),
4083 I915_READ(pp_div_reg));
4084 }
4085
4086 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4087 {
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_encoder *encoder;
4090 struct intel_dp *intel_dp = NULL;
4091 struct intel_crtc_config *config = NULL;
4092 struct intel_crtc *intel_crtc = NULL;
4093 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4094 u32 reg, val;
4095 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4096
4097 if (refresh_rate <= 0) {
4098 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4099 return;
4100 }
4101
4102 if (intel_connector == NULL) {
4103 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4104 return;
4105 }
4106
4107 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4108 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4109 return;
4110 }
4111
4112 encoder = intel_attached_encoder(&intel_connector->base);
4113 intel_dp = enc_to_intel_dp(&encoder->base);
4114 intel_crtc = encoder->new_crtc;
4115
4116 if (!intel_crtc) {
4117 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4118 return;
4119 }
4120
4121 config = &intel_crtc->config;
4122
4123 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4124 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4125 return;
4126 }
4127
4128 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4129 index = DRRS_LOW_RR;
4130
4131 if (index == intel_dp->drrs_state.refresh_rate_type) {
4132 DRM_DEBUG_KMS(
4133 "DRRS requested for previously set RR...ignoring\n");
4134 return;
4135 }
4136
4137 if (!intel_crtc->active) {
4138 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4139 return;
4140 }
4141
4142 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4143 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4144 val = I915_READ(reg);
4145 if (index > DRRS_HIGH_RR) {
4146 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4147 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4148 } else {
4149 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4150 }
4151 I915_WRITE(reg, val);
4152 }
4153
4154 /*
4155 * mutex taken to ensure that there is no race between differnt
4156 * drrs calls trying to update refresh rate. This scenario may occur
4157 * in future when idleness detection based DRRS in kernel and
4158 * possible calls from user space to set differnt RR are made.
4159 */
4160
4161 mutex_lock(&intel_dp->drrs_state.mutex);
4162
4163 intel_dp->drrs_state.refresh_rate_type = index;
4164
4165 mutex_unlock(&intel_dp->drrs_state.mutex);
4166
4167 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4168 }
4169
4170 static struct drm_display_mode *
4171 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4172 struct intel_connector *intel_connector,
4173 struct drm_display_mode *fixed_mode)
4174 {
4175 struct drm_connector *connector = &intel_connector->base;
4176 struct intel_dp *intel_dp = &intel_dig_port->dp;
4177 struct drm_device *dev = intel_dig_port->base.base.dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct drm_display_mode *downclock_mode = NULL;
4180
4181 if (INTEL_INFO(dev)->gen <= 6) {
4182 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4183 return NULL;
4184 }
4185
4186 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4187 DRM_INFO("VBT doesn't support DRRS\n");
4188 return NULL;
4189 }
4190
4191 downclock_mode = intel_find_panel_downclock
4192 (dev, fixed_mode, connector);
4193
4194 if (!downclock_mode) {
4195 DRM_INFO("DRRS not supported\n");
4196 return NULL;
4197 }
4198
4199 dev_priv->drrs.connector = intel_connector;
4200
4201 mutex_init(&intel_dp->drrs_state.mutex);
4202
4203 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4204
4205 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4206 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4207 return downclock_mode;
4208 }
4209
4210 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4211 struct intel_connector *intel_connector,
4212 struct edp_power_seq *power_seq)
4213 {
4214 struct drm_connector *connector = &intel_connector->base;
4215 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4216 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4217 struct drm_device *dev = intel_encoder->base.dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct drm_display_mode *fixed_mode = NULL;
4220 struct drm_display_mode *downclock_mode = NULL;
4221 bool has_dpcd;
4222 struct drm_display_mode *scan;
4223 struct edid *edid;
4224
4225 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4226
4227 if (!is_edp(intel_dp))
4228 return true;
4229
4230 /* The VDD bit needs a power domain reference, so if the bit is already
4231 * enabled when we boot, grab this reference. */
4232 if (edp_have_panel_vdd(intel_dp)) {
4233 enum intel_display_power_domain power_domain;
4234 power_domain = intel_display_port_power_domain(intel_encoder);
4235 intel_display_power_get(dev_priv, power_domain);
4236 }
4237
4238 /* Cache DPCD and EDID for edp. */
4239 intel_edp_panel_vdd_on(intel_dp);
4240 has_dpcd = intel_dp_get_dpcd(intel_dp);
4241 edp_panel_vdd_off(intel_dp, false);
4242
4243 if (has_dpcd) {
4244 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4245 dev_priv->no_aux_handshake =
4246 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4247 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4248 } else {
4249 /* if this fails, presume the device is a ghost */
4250 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4251 return false;
4252 }
4253
4254 /* We now know it's not a ghost, init power sequence regs. */
4255 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4256
4257 mutex_lock(&dev->mode_config.mutex);
4258 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4259 if (edid) {
4260 if (drm_add_edid_modes(connector, edid)) {
4261 drm_mode_connector_update_edid_property(connector,
4262 edid);
4263 drm_edid_to_eld(connector, edid);
4264 } else {
4265 kfree(edid);
4266 edid = ERR_PTR(-EINVAL);
4267 }
4268 } else {
4269 edid = ERR_PTR(-ENOENT);
4270 }
4271 intel_connector->edid = edid;
4272
4273 /* prefer fixed mode from EDID if available */
4274 list_for_each_entry(scan, &connector->probed_modes, head) {
4275 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4276 fixed_mode = drm_mode_duplicate(dev, scan);
4277 downclock_mode = intel_dp_drrs_init(
4278 intel_dig_port,
4279 intel_connector, fixed_mode);
4280 break;
4281 }
4282 }
4283
4284 /* fallback to VBT if available for eDP */
4285 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4286 fixed_mode = drm_mode_duplicate(dev,
4287 dev_priv->vbt.lfp_lvds_vbt_mode);
4288 if (fixed_mode)
4289 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4290 }
4291 mutex_unlock(&dev->mode_config.mutex);
4292
4293 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4294 intel_panel_setup_backlight(connector);
4295
4296 return true;
4297 }
4298
4299 bool
4300 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4301 struct intel_connector *intel_connector)
4302 {
4303 struct drm_connector *connector = &intel_connector->base;
4304 struct intel_dp *intel_dp = &intel_dig_port->dp;
4305 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4306 struct drm_device *dev = intel_encoder->base.dev;
4307 struct drm_i915_private *dev_priv = dev->dev_private;
4308 enum port port = intel_dig_port->port;
4309 struct edp_power_seq power_seq = { 0 };
4310 int type;
4311
4312 /* intel_dp vfuncs */
4313 if (IS_VALLEYVIEW(dev))
4314 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4315 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4316 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4317 else if (HAS_PCH_SPLIT(dev))
4318 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4319 else
4320 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4321
4322 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4323
4324 /* Preserve the current hw state. */
4325 intel_dp->DP = I915_READ(intel_dp->output_reg);
4326 intel_dp->attached_connector = intel_connector;
4327
4328 if (intel_dp_is_edp(dev, port))
4329 type = DRM_MODE_CONNECTOR_eDP;
4330 else
4331 type = DRM_MODE_CONNECTOR_DisplayPort;
4332
4333 /*
4334 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4335 * for DP the encoder type can be set by the caller to
4336 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4337 */
4338 if (type == DRM_MODE_CONNECTOR_eDP)
4339 intel_encoder->type = INTEL_OUTPUT_EDP;
4340
4341 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4342 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4343 port_name(port));
4344
4345 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4346 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4347
4348 connector->interlace_allowed = true;
4349 connector->doublescan_allowed = 0;
4350
4351 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4352 edp_panel_vdd_work);
4353
4354 intel_connector_attach_encoder(intel_connector, intel_encoder);
4355 drm_sysfs_connector_add(connector);
4356
4357 if (HAS_DDI(dev))
4358 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4359 else
4360 intel_connector->get_hw_state = intel_connector_get_hw_state;
4361 intel_connector->unregister = intel_dp_connector_unregister;
4362
4363 /* Set up the hotplug pin. */
4364 switch (port) {
4365 case PORT_A:
4366 intel_encoder->hpd_pin = HPD_PORT_A;
4367 break;
4368 case PORT_B:
4369 intel_encoder->hpd_pin = HPD_PORT_B;
4370 break;
4371 case PORT_C:
4372 intel_encoder->hpd_pin = HPD_PORT_C;
4373 break;
4374 case PORT_D:
4375 intel_encoder->hpd_pin = HPD_PORT_D;
4376 break;
4377 default:
4378 BUG();
4379 }
4380
4381 if (is_edp(intel_dp)) {
4382 intel_dp_init_panel_power_timestamps(intel_dp);
4383 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4384 }
4385
4386 intel_dp_aux_init(intel_dp, intel_connector);
4387
4388 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4389 drm_dp_aux_unregister(&intel_dp->aux);
4390 if (is_edp(intel_dp)) {
4391 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4392 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4393 edp_panel_vdd_off_sync(intel_dp);
4394 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4395 }
4396 drm_sysfs_connector_remove(connector);
4397 drm_connector_cleanup(connector);
4398 return false;
4399 }
4400
4401 intel_dp_add_properties(intel_dp, connector);
4402
4403 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4404 * 0xd. Failure to do so will result in spurious interrupts being
4405 * generated on the port when a cable is not attached.
4406 */
4407 if (IS_G4X(dev) && !IS_GM45(dev)) {
4408 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4409 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4410 }
4411
4412 return true;
4413 }
4414
4415 void
4416 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4417 {
4418 struct drm_i915_private *dev_priv = dev->dev_private;
4419 struct intel_digital_port *intel_dig_port;
4420 struct intel_encoder *intel_encoder;
4421 struct drm_encoder *encoder;
4422 struct intel_connector *intel_connector;
4423
4424 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4425 if (!intel_dig_port)
4426 return;
4427
4428 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4429 if (!intel_connector) {
4430 kfree(intel_dig_port);
4431 return;
4432 }
4433
4434 intel_encoder = &intel_dig_port->base;
4435 encoder = &intel_encoder->base;
4436
4437 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4438 DRM_MODE_ENCODER_TMDS);
4439
4440 intel_encoder->compute_config = intel_dp_compute_config;
4441 intel_encoder->disable = intel_disable_dp;
4442 intel_encoder->get_hw_state = intel_dp_get_hw_state;
4443 intel_encoder->get_config = intel_dp_get_config;
4444 if (IS_CHERRYVIEW(dev)) {
4445 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4446 intel_encoder->pre_enable = chv_pre_enable_dp;
4447 intel_encoder->enable = vlv_enable_dp;
4448 intel_encoder->post_disable = chv_post_disable_dp;
4449 } else if (IS_VALLEYVIEW(dev)) {
4450 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4451 intel_encoder->pre_enable = vlv_pre_enable_dp;
4452 intel_encoder->enable = vlv_enable_dp;
4453 intel_encoder->post_disable = vlv_post_disable_dp;
4454 } else {
4455 intel_encoder->pre_enable = g4x_pre_enable_dp;
4456 intel_encoder->enable = g4x_enable_dp;
4457 intel_encoder->post_disable = g4x_post_disable_dp;
4458 }
4459
4460 intel_dig_port->port = port;
4461 intel_dig_port->dp.output_reg = output_reg;
4462
4463 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4464 if (IS_CHERRYVIEW(dev)) {
4465 if (port == PORT_D)
4466 intel_encoder->crtc_mask = 1 << 2;
4467 else
4468 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4469 } else {
4470 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4471 }
4472 intel_encoder->cloneable = 0;
4473 intel_encoder->hot_plug = intel_dp_hot_plug;
4474
4475 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4476 dev_priv->hpd_irq_port[port] = intel_dig_port;
4477
4478 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4479 drm_encoder_cleanup(encoder);
4480 kfree(intel_dig_port);
4481 kfree(intel_connector);
4482 }
4483 }
Linux kernel - Deliverables
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