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65959a29ab2bd2c81f09be689a1396fe9094e08b
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 struct intel_dp {
46 struct intel_encoder base;
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 bool has_audio;
51 int force_audio;
52 int dpms_mode;
53 uint8_t link_bw;
54 uint8_t lane_count;
55 uint8_t dpcd[4];
56 struct i2c_adapter adapter;
57 struct i2c_algo_dp_aux_data algo;
58 bool is_pch_edp;
59 uint8_t train_set[4];
60 uint8_t link_status[DP_LINK_STATUS_SIZE];
61
62 struct drm_property *force_audio_property;
63 };
64
65 /**
66 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
67 * @intel_dp: DP struct
68 *
69 * If a CPU or PCH DP output is attached to an eDP panel, this function
70 * will return true, and false otherwise.
71 */
72 static bool is_edp(struct intel_dp *intel_dp)
73 {
74 return intel_dp->base.type == INTEL_OUTPUT_EDP;
75 }
76
77 /**
78 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
79 * @intel_dp: DP struct
80 *
81 * Returns true if the given DP struct corresponds to a PCH DP port attached
82 * to an eDP panel, false otherwise. Helpful for determining whether we
83 * may need FDI resources for a given DP output or not.
84 */
85 static bool is_pch_edp(struct intel_dp *intel_dp)
86 {
87 return intel_dp->is_pch_edp;
88 }
89
90 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
91 {
92 return container_of(encoder, struct intel_dp, base.base);
93 }
94
95 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
96 {
97 return container_of(intel_attached_encoder(connector),
98 struct intel_dp, base);
99 }
100
101 /**
102 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
103 * @encoder: DRM encoder
104 *
105 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
106 * by intel_display.c.
107 */
108 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
109 {
110 struct intel_dp *intel_dp;
111
112 if (!encoder)
113 return false;
114
115 intel_dp = enc_to_intel_dp(encoder);
116
117 return is_pch_edp(intel_dp);
118 }
119
120 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
122 static void intel_dp_link_down(struct intel_dp *intel_dp);
123
124 void
125 intel_edp_link_config (struct intel_encoder *intel_encoder,
126 int *lane_num, int *link_bw)
127 {
128 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
129
130 *lane_num = intel_dp->lane_count;
131 if (intel_dp->link_bw == DP_LINK_BW_1_62)
132 *link_bw = 162000;
133 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
134 *link_bw = 270000;
135 }
136
137 static int
138 intel_dp_max_lane_count(struct intel_dp *intel_dp)
139 {
140 int max_lane_count = 4;
141
142 if (intel_dp->dpcd[0] >= 0x11) {
143 max_lane_count = intel_dp->dpcd[2] & 0x1f;
144 switch (max_lane_count) {
145 case 1: case 2: case 4:
146 break;
147 default:
148 max_lane_count = 4;
149 }
150 }
151 return max_lane_count;
152 }
153
154 static int
155 intel_dp_max_link_bw(struct intel_dp *intel_dp)
156 {
157 int max_link_bw = intel_dp->dpcd[1];
158
159 switch (max_link_bw) {
160 case DP_LINK_BW_1_62:
161 case DP_LINK_BW_2_7:
162 break;
163 default:
164 max_link_bw = DP_LINK_BW_1_62;
165 break;
166 }
167 return max_link_bw;
168 }
169
170 static int
171 intel_dp_link_clock(uint8_t link_bw)
172 {
173 if (link_bw == DP_LINK_BW_2_7)
174 return 270000;
175 else
176 return 162000;
177 }
178
179 /* I think this is a fiction */
180 static int
181 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
182 {
183 struct drm_i915_private *dev_priv = dev->dev_private;
184
185 if (is_edp(intel_dp))
186 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
187 else
188 return pixel_clock * 3;
189 }
190
191 static int
192 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
193 {
194 return (max_link_clock * max_lanes * 8) / 10;
195 }
196
197 static int
198 intel_dp_mode_valid(struct drm_connector *connector,
199 struct drm_display_mode *mode)
200 {
201 struct intel_dp *intel_dp = intel_attached_dp(connector);
202 struct drm_device *dev = connector->dev;
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
205 int max_lanes = intel_dp_max_lane_count(intel_dp);
206
207 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
208 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
209 return MODE_PANEL;
210
211 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
212 return MODE_PANEL;
213 }
214
215 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
216 which are outside spec tolerances but somehow work by magic */
217 if (!is_edp(intel_dp) &&
218 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
219 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
220 return MODE_CLOCK_HIGH;
221
222 if (mode->clock < 10000)
223 return MODE_CLOCK_LOW;
224
225 return MODE_OK;
226 }
227
228 static uint32_t
229 pack_aux(uint8_t *src, int src_bytes)
230 {
231 int i;
232 uint32_t v = 0;
233
234 if (src_bytes > 4)
235 src_bytes = 4;
236 for (i = 0; i < src_bytes; i++)
237 v |= ((uint32_t) src[i]) << ((3-i) * 8);
238 return v;
239 }
240
241 static void
242 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
243 {
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249 }
250
251 /* hrawclock is 1/4 the FSB frequency */
252 static int
253 intel_hrawclk(struct drm_device *dev)
254 {
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
258 clkcfg = I915_READ(CLKCFG);
259 switch (clkcfg & CLKCFG_FSB_MASK) {
260 case CLKCFG_FSB_400:
261 return 100;
262 case CLKCFG_FSB_533:
263 return 133;
264 case CLKCFG_FSB_667:
265 return 166;
266 case CLKCFG_FSB_800:
267 return 200;
268 case CLKCFG_FSB_1067:
269 return 266;
270 case CLKCFG_FSB_1333:
271 return 333;
272 /* these two are just a guess; one of them might be right */
273 case CLKCFG_FSB_1600:
274 case CLKCFG_FSB_1600_ALT:
275 return 400;
276 default:
277 return 133;
278 }
279 }
280
281 static int
282 intel_dp_aux_ch(struct intel_dp *intel_dp,
283 uint8_t *send, int send_bytes,
284 uint8_t *recv, int recv_size)
285 {
286 uint32_t output_reg = intel_dp->output_reg;
287 struct drm_device *dev = intel_dp->base.base.dev;
288 struct drm_i915_private *dev_priv = dev->dev_private;
289 uint32_t ch_ctl = output_reg + 0x10;
290 uint32_t ch_data = ch_ctl + 4;
291 int i;
292 int recv_bytes;
293 uint32_t status;
294 uint32_t aux_clock_divider;
295 int try, precharge;
296
297 /* The clock divider is based off the hrawclk,
298 * and would like to run at 2MHz. So, take the
299 * hrawclk value and divide by 2 and use that
300 *
301 * Note that PCH attached eDP panels should use a 125MHz input
302 * clock divider.
303 */
304 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
305 if (IS_GEN6(dev))
306 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
307 else
308 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
309 } else if (HAS_PCH_SPLIT(dev))
310 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
311 else
312 aux_clock_divider = intel_hrawclk(dev) / 2;
313
314 if (IS_GEN6(dev))
315 precharge = 3;
316 else
317 precharge = 5;
318
319 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
320 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
321 I915_READ(ch_ctl));
322 return -EBUSY;
323 }
324
325 /* Must try at least 3 times according to DP spec */
326 for (try = 0; try < 5; try++) {
327 /* Load the send data into the aux channel data registers */
328 for (i = 0; i < send_bytes; i += 4)
329 I915_WRITE(ch_data + i,
330 pack_aux(send + i, send_bytes - i));
331
332 /* Send the command and wait for it to complete */
333 I915_WRITE(ch_ctl,
334 DP_AUX_CH_CTL_SEND_BUSY |
335 DP_AUX_CH_CTL_TIME_OUT_400us |
336 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
337 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
338 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
339 DP_AUX_CH_CTL_DONE |
340 DP_AUX_CH_CTL_TIME_OUT_ERROR |
341 DP_AUX_CH_CTL_RECEIVE_ERROR);
342 for (;;) {
343 status = I915_READ(ch_ctl);
344 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
345 break;
346 udelay(100);
347 }
348
349 /* Clear done status and any errors */
350 I915_WRITE(ch_ctl,
351 status |
352 DP_AUX_CH_CTL_DONE |
353 DP_AUX_CH_CTL_TIME_OUT_ERROR |
354 DP_AUX_CH_CTL_RECEIVE_ERROR);
355 if (status & DP_AUX_CH_CTL_DONE)
356 break;
357 }
358
359 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
360 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
361 return -EBUSY;
362 }
363
364 /* Check for timeout or receive error.
365 * Timeouts occur when the sink is not connected
366 */
367 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
368 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
369 return -EIO;
370 }
371
372 /* Timeouts occur when the device isn't connected, so they're
373 * "normal" -- don't fill the kernel log with these */
374 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
375 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
376 return -ETIMEDOUT;
377 }
378
379 /* Unload any bytes sent back from the other side */
380 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
381 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
382 if (recv_bytes > recv_size)
383 recv_bytes = recv_size;
384
385 for (i = 0; i < recv_bytes; i += 4)
386 unpack_aux(I915_READ(ch_data + i),
387 recv + i, recv_bytes - i);
388
389 return recv_bytes;
390 }
391
392 /* Write data to the aux channel in native mode */
393 static int
394 intel_dp_aux_native_write(struct intel_dp *intel_dp,
395 uint16_t address, uint8_t *send, int send_bytes)
396 {
397 int ret;
398 uint8_t msg[20];
399 int msg_bytes;
400 uint8_t ack;
401
402 if (send_bytes > 16)
403 return -1;
404 msg[0] = AUX_NATIVE_WRITE << 4;
405 msg[1] = address >> 8;
406 msg[2] = address & 0xff;
407 msg[3] = send_bytes - 1;
408 memcpy(&msg[4], send, send_bytes);
409 msg_bytes = send_bytes + 4;
410 for (;;) {
411 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
412 if (ret < 0)
413 return ret;
414 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
415 break;
416 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
417 udelay(100);
418 else
419 return -EIO;
420 }
421 return send_bytes;
422 }
423
424 /* Write a single byte to the aux channel in native mode */
425 static int
426 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
427 uint16_t address, uint8_t byte)
428 {
429 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
430 }
431
432 /* read bytes from a native aux channel */
433 static int
434 intel_dp_aux_native_read(struct intel_dp *intel_dp,
435 uint16_t address, uint8_t *recv, int recv_bytes)
436 {
437 uint8_t msg[4];
438 int msg_bytes;
439 uint8_t reply[20];
440 int reply_bytes;
441 uint8_t ack;
442 int ret;
443
444 msg[0] = AUX_NATIVE_READ << 4;
445 msg[1] = address >> 8;
446 msg[2] = address & 0xff;
447 msg[3] = recv_bytes - 1;
448
449 msg_bytes = 4;
450 reply_bytes = recv_bytes + 1;
451
452 for (;;) {
453 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
454 reply, reply_bytes);
455 if (ret == 0)
456 return -EPROTO;
457 if (ret < 0)
458 return ret;
459 ack = reply[0];
460 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
461 memcpy(recv, reply + 1, ret - 1);
462 return ret - 1;
463 }
464 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
465 udelay(100);
466 else
467 return -EIO;
468 }
469 }
470
471 static int
472 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
473 uint8_t write_byte, uint8_t *read_byte)
474 {
475 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
476 struct intel_dp *intel_dp = container_of(adapter,
477 struct intel_dp,
478 adapter);
479 uint16_t address = algo_data->address;
480 uint8_t msg[5];
481 uint8_t reply[2];
482 unsigned retry;
483 int msg_bytes;
484 int reply_bytes;
485 int ret;
486
487 /* Set up the command byte */
488 if (mode & MODE_I2C_READ)
489 msg[0] = AUX_I2C_READ << 4;
490 else
491 msg[0] = AUX_I2C_WRITE << 4;
492
493 if (!(mode & MODE_I2C_STOP))
494 msg[0] |= AUX_I2C_MOT << 4;
495
496 msg[1] = address >> 8;
497 msg[2] = address;
498
499 switch (mode) {
500 case MODE_I2C_WRITE:
501 msg[3] = 0;
502 msg[4] = write_byte;
503 msg_bytes = 5;
504 reply_bytes = 1;
505 break;
506 case MODE_I2C_READ:
507 msg[3] = 0;
508 msg_bytes = 4;
509 reply_bytes = 2;
510 break;
511 default:
512 msg_bytes = 3;
513 reply_bytes = 1;
514 break;
515 }
516
517 for (retry = 0; retry < 5; retry++) {
518 ret = intel_dp_aux_ch(intel_dp,
519 msg, msg_bytes,
520 reply, reply_bytes);
521 if (ret < 0) {
522 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
523 return ret;
524 }
525
526 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
527 case AUX_NATIVE_REPLY_ACK:
528 /* I2C-over-AUX Reply field is only valid
529 * when paired with AUX ACK.
530 */
531 break;
532 case AUX_NATIVE_REPLY_NACK:
533 DRM_DEBUG_KMS("aux_ch native nack\n");
534 return -EREMOTEIO;
535 case AUX_NATIVE_REPLY_DEFER:
536 udelay(100);
537 continue;
538 default:
539 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
540 reply[0]);
541 return -EREMOTEIO;
542 }
543
544 switch (reply[0] & AUX_I2C_REPLY_MASK) {
545 case AUX_I2C_REPLY_ACK:
546 if (mode == MODE_I2C_READ) {
547 *read_byte = reply[1];
548 }
549 return reply_bytes - 1;
550 case AUX_I2C_REPLY_NACK:
551 DRM_DEBUG_KMS("aux_i2c nack\n");
552 return -EREMOTEIO;
553 case AUX_I2C_REPLY_DEFER:
554 DRM_DEBUG_KMS("aux_i2c defer\n");
555 udelay(100);
556 break;
557 default:
558 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
559 return -EREMOTEIO;
560 }
561 }
562
563 DRM_ERROR("too many retries, giving up\n");
564 return -EREMOTEIO;
565 }
566
567 static int
568 intel_dp_i2c_init(struct intel_dp *intel_dp,
569 struct intel_connector *intel_connector, const char *name)
570 {
571 DRM_DEBUG_KMS("i2c_init %s\n", name);
572 intel_dp->algo.running = false;
573 intel_dp->algo.address = 0;
574 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
575
576 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
577 intel_dp->adapter.owner = THIS_MODULE;
578 intel_dp->adapter.class = I2C_CLASS_DDC;
579 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
580 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
581 intel_dp->adapter.algo_data = &intel_dp->algo;
582 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
583
584 return i2c_dp_aux_add_bus(&intel_dp->adapter);
585 }
586
587 static bool
588 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
589 struct drm_display_mode *adjusted_mode)
590 {
591 struct drm_device *dev = encoder->dev;
592 struct drm_i915_private *dev_priv = dev->dev_private;
593 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
594 int lane_count, clock;
595 int max_lane_count = intel_dp_max_lane_count(intel_dp);
596 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
597 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
598
599 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
600 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
601 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
602 mode, adjusted_mode);
603 /*
604 * the mode->clock is used to calculate the Data&Link M/N
605 * of the pipe. For the eDP the fixed clock should be used.
606 */
607 mode->clock = dev_priv->panel_fixed_mode->clock;
608 }
609
610 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
611 for (clock = 0; clock <= max_clock; clock++) {
612 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
613
614 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
615 <= link_avail) {
616 intel_dp->link_bw = bws[clock];
617 intel_dp->lane_count = lane_count;
618 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
619 DRM_DEBUG_KMS("Display port link bw %02x lane "
620 "count %d clock %d\n",
621 intel_dp->link_bw, intel_dp->lane_count,
622 adjusted_mode->clock);
623 return true;
624 }
625 }
626 }
627
628 if (is_edp(intel_dp)) {
629 /* okay we failed just pick the highest */
630 intel_dp->lane_count = max_lane_count;
631 intel_dp->link_bw = bws[max_clock];
632 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
633 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
634 "count %d clock %d\n",
635 intel_dp->link_bw, intel_dp->lane_count,
636 adjusted_mode->clock);
637
638 return true;
639 }
640
641 return false;
642 }
643
644 struct intel_dp_m_n {
645 uint32_t tu;
646 uint32_t gmch_m;
647 uint32_t gmch_n;
648 uint32_t link_m;
649 uint32_t link_n;
650 };
651
652 static void
653 intel_reduce_ratio(uint32_t *num, uint32_t *den)
654 {
655 while (*num > 0xffffff || *den > 0xffffff) {
656 *num >>= 1;
657 *den >>= 1;
658 }
659 }
660
661 static void
662 intel_dp_compute_m_n(int bpp,
663 int nlanes,
664 int pixel_clock,
665 int link_clock,
666 struct intel_dp_m_n *m_n)
667 {
668 m_n->tu = 64;
669 m_n->gmch_m = (pixel_clock * bpp) >> 3;
670 m_n->gmch_n = link_clock * nlanes;
671 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
672 m_n->link_m = pixel_clock;
673 m_n->link_n = link_clock;
674 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
675 }
676
677 void
678 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
679 struct drm_display_mode *adjusted_mode)
680 {
681 struct drm_device *dev = crtc->dev;
682 struct drm_mode_config *mode_config = &dev->mode_config;
683 struct drm_encoder *encoder;
684 struct drm_i915_private *dev_priv = dev->dev_private;
685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
686 int lane_count = 4, bpp = 24;
687 struct intel_dp_m_n m_n;
688 int pipe = intel_crtc->pipe;
689
690 /*
691 * Find the lane count in the intel_encoder private
692 */
693 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
694 struct intel_dp *intel_dp;
695
696 if (encoder->crtc != crtc)
697 continue;
698
699 intel_dp = enc_to_intel_dp(encoder);
700 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
701 lane_count = intel_dp->lane_count;
702 break;
703 } else if (is_edp(intel_dp)) {
704 lane_count = dev_priv->edp.lanes;
705 bpp = dev_priv->edp.bpp;
706 break;
707 }
708 }
709
710 /*
711 * Compute the GMCH and Link ratios. The '3' here is
712 * the number of bytes_per_pixel post-LUT, which we always
713 * set up for 8-bits of R/G/B, or 3 bytes total.
714 */
715 intel_dp_compute_m_n(bpp, lane_count,
716 mode->clock, adjusted_mode->clock, &m_n);
717
718 if (HAS_PCH_SPLIT(dev)) {
719 I915_WRITE(TRANSDATA_M1(pipe),
720 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
721 m_n.gmch_m);
722 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
723 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
724 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
725 } else {
726 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
728 m_n.gmch_m);
729 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
730 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
731 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
732 }
733 }
734
735 static void
736 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
737 struct drm_display_mode *adjusted_mode)
738 {
739 struct drm_device *dev = encoder->dev;
740 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
741 struct drm_crtc *crtc = intel_dp->base.base.crtc;
742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
743
744 intel_dp->DP = (DP_VOLTAGE_0_4 |
745 DP_PRE_EMPHASIS_0);
746
747 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
748 intel_dp->DP |= DP_SYNC_HS_HIGH;
749 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
750 intel_dp->DP |= DP_SYNC_VS_HIGH;
751
752 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
753 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
754 else
755 intel_dp->DP |= DP_LINK_TRAIN_OFF;
756
757 switch (intel_dp->lane_count) {
758 case 1:
759 intel_dp->DP |= DP_PORT_WIDTH_1;
760 break;
761 case 2:
762 intel_dp->DP |= DP_PORT_WIDTH_2;
763 break;
764 case 4:
765 intel_dp->DP |= DP_PORT_WIDTH_4;
766 break;
767 }
768 if (intel_dp->has_audio)
769 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
770
771 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
772 intel_dp->link_configuration[0] = intel_dp->link_bw;
773 intel_dp->link_configuration[1] = intel_dp->lane_count;
774
775 /*
776 * Check for DPCD version > 1.1 and enhanced framing support
777 */
778 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
779 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
780 intel_dp->DP |= DP_ENHANCED_FRAMING;
781 }
782
783 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
784 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
785 intel_dp->DP |= DP_PIPEB_SELECT;
786
787 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
788 /* don't miss out required setting for eDP */
789 intel_dp->DP |= DP_PLL_ENABLE;
790 if (adjusted_mode->clock < 200000)
791 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
792 else
793 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
794 }
795 }
796
797 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
798 {
799 struct drm_device *dev = intel_dp->base.base.dev;
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 u32 pp;
802
803 /*
804 * If the panel wasn't on, make sure there's not a currently
805 * active PP sequence before enabling AUX VDD.
806 */
807 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
808 msleep(dev_priv->panel_t3);
809
810 pp = I915_READ(PCH_PP_CONTROL);
811 pp |= EDP_FORCE_VDD;
812 I915_WRITE(PCH_PP_CONTROL, pp);
813 POSTING_READ(PCH_PP_CONTROL);
814 }
815
816 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
817 {
818 struct drm_device *dev = intel_dp->base.base.dev;
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 u32 pp;
821
822 pp = I915_READ(PCH_PP_CONTROL);
823 pp &= ~EDP_FORCE_VDD;
824 I915_WRITE(PCH_PP_CONTROL, pp);
825 POSTING_READ(PCH_PP_CONTROL);
826
827 /* Make sure sequencer is idle before allowing subsequent activity */
828 msleep(dev_priv->panel_t12);
829 }
830
831 /* Returns true if the panel was already on when called */
832 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
833 {
834 struct drm_device *dev = intel_dp->base.base.dev;
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
837
838 if (I915_READ(PCH_PP_STATUS) & PP_ON)
839 return true;
840
841 pp = I915_READ(PCH_PP_CONTROL);
842
843 /* ILK workaround: disable reset around power sequence */
844 pp &= ~PANEL_POWER_RESET;
845 I915_WRITE(PCH_PP_CONTROL, pp);
846 POSTING_READ(PCH_PP_CONTROL);
847
848 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
849 I915_WRITE(PCH_PP_CONTROL, pp);
850 POSTING_READ(PCH_PP_CONTROL);
851
852 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
853 5000))
854 DRM_ERROR("panel on wait timed out: 0x%08x\n",
855 I915_READ(PCH_PP_STATUS));
856
857 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
858 I915_WRITE(PCH_PP_CONTROL, pp);
859 POSTING_READ(PCH_PP_CONTROL);
860
861 return false;
862 }
863
864 static void ironlake_edp_panel_off (struct drm_device *dev)
865 {
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
868 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
869
870 pp = I915_READ(PCH_PP_CONTROL);
871
872 /* ILK workaround: disable reset around power sequence */
873 pp &= ~PANEL_POWER_RESET;
874 I915_WRITE(PCH_PP_CONTROL, pp);
875 POSTING_READ(PCH_PP_CONTROL);
876
877 pp &= ~POWER_TARGET_ON;
878 I915_WRITE(PCH_PP_CONTROL, pp);
879 POSTING_READ(PCH_PP_CONTROL);
880
881 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
882 DRM_ERROR("panel off wait timed out: 0x%08x\n",
883 I915_READ(PCH_PP_STATUS));
884
885 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
886 I915_WRITE(PCH_PP_CONTROL, pp);
887 POSTING_READ(PCH_PP_CONTROL);
888 }
889
890 static void ironlake_edp_backlight_on (struct drm_device *dev)
891 {
892 struct drm_i915_private *dev_priv = dev->dev_private;
893 u32 pp;
894
895 DRM_DEBUG_KMS("\n");
896 /*
897 * If we enable the backlight right away following a panel power
898 * on, we may see slight flicker as the panel syncs with the eDP
899 * link. So delay a bit to make sure the image is solid before
900 * allowing it to appear.
901 */
902 msleep(300);
903 pp = I915_READ(PCH_PP_CONTROL);
904 pp |= EDP_BLC_ENABLE;
905 I915_WRITE(PCH_PP_CONTROL, pp);
906 }
907
908 static void ironlake_edp_backlight_off (struct drm_device *dev)
909 {
910 struct drm_i915_private *dev_priv = dev->dev_private;
911 u32 pp;
912
913 DRM_DEBUG_KMS("\n");
914 pp = I915_READ(PCH_PP_CONTROL);
915 pp &= ~EDP_BLC_ENABLE;
916 I915_WRITE(PCH_PP_CONTROL, pp);
917 }
918
919 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
920 {
921 struct drm_device *dev = encoder->dev;
922 struct drm_i915_private *dev_priv = dev->dev_private;
923 u32 dpa_ctl;
924
925 DRM_DEBUG_KMS("\n");
926 dpa_ctl = I915_READ(DP_A);
927 dpa_ctl |= DP_PLL_ENABLE;
928 I915_WRITE(DP_A, dpa_ctl);
929 POSTING_READ(DP_A);
930 udelay(200);
931 }
932
933 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
934 {
935 struct drm_device *dev = encoder->dev;
936 struct drm_i915_private *dev_priv = dev->dev_private;
937 u32 dpa_ctl;
938
939 dpa_ctl = I915_READ(DP_A);
940 dpa_ctl &= ~DP_PLL_ENABLE;
941 I915_WRITE(DP_A, dpa_ctl);
942 POSTING_READ(DP_A);
943 udelay(200);
944 }
945
946 static void intel_dp_prepare(struct drm_encoder *encoder)
947 {
948 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
949 struct drm_device *dev = encoder->dev;
950
951 if (is_edp(intel_dp)) {
952 ironlake_edp_backlight_off(dev);
953 ironlake_edp_panel_off(dev);
954 if (!is_pch_edp(intel_dp))
955 ironlake_edp_pll_on(encoder);
956 else
957 ironlake_edp_pll_off(encoder);
958 }
959 intel_dp_link_down(intel_dp);
960 }
961
962 static void intel_dp_commit(struct drm_encoder *encoder)
963 {
964 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
965 struct drm_device *dev = encoder->dev;
966
967 if (is_edp(intel_dp))
968 ironlake_edp_panel_vdd_on(intel_dp);
969
970 intel_dp_start_link_train(intel_dp);
971
972 if (is_edp(intel_dp)) {
973 ironlake_edp_panel_on(intel_dp);
974 ironlake_edp_panel_vdd_off(intel_dp);
975 }
976
977 intel_dp_complete_link_train(intel_dp);
978
979 if (is_edp(intel_dp))
980 ironlake_edp_backlight_on(dev);
981 }
982
983 static void
984 intel_dp_dpms(struct drm_encoder *encoder, int mode)
985 {
986 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
987 struct drm_device *dev = encoder->dev;
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
990
991 if (mode != DRM_MODE_DPMS_ON) {
992 if (is_edp(intel_dp))
993 ironlake_edp_backlight_off(dev);
994 intel_dp_link_down(intel_dp);
995 if (is_edp(intel_dp))
996 ironlake_edp_panel_off(dev);
997 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
998 ironlake_edp_pll_off(encoder);
999 } else {
1000 if (is_edp(intel_dp))
1001 ironlake_edp_panel_vdd_on(intel_dp);
1002 if (!(dp_reg & DP_PORT_EN)) {
1003 intel_dp_start_link_train(intel_dp);
1004 if (is_edp(intel_dp)) {
1005 ironlake_edp_panel_on(intel_dp);
1006 ironlake_edp_panel_vdd_off(intel_dp);
1007 }
1008 intel_dp_complete_link_train(intel_dp);
1009 }
1010 if (is_edp(intel_dp))
1011 ironlake_edp_backlight_on(dev);
1012 }
1013 intel_dp->dpms_mode = mode;
1014 }
1015
1016 /*
1017 * Fetch AUX CH registers 0x202 - 0x207 which contain
1018 * link status information
1019 */
1020 static bool
1021 intel_dp_get_link_status(struct intel_dp *intel_dp)
1022 {
1023 int ret;
1024
1025 ret = intel_dp_aux_native_read(intel_dp,
1026 DP_LANE0_1_STATUS,
1027 intel_dp->link_status, DP_LINK_STATUS_SIZE);
1028 if (ret != DP_LINK_STATUS_SIZE)
1029 return false;
1030 return true;
1031 }
1032
1033 static uint8_t
1034 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1035 int r)
1036 {
1037 return link_status[r - DP_LANE0_1_STATUS];
1038 }
1039
1040 static uint8_t
1041 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1042 int lane)
1043 {
1044 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1045 int s = ((lane & 1) ?
1046 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1047 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1048 uint8_t l = intel_dp_link_status(link_status, i);
1049
1050 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1051 }
1052
1053 static uint8_t
1054 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1055 int lane)
1056 {
1057 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1058 int s = ((lane & 1) ?
1059 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1060 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1061 uint8_t l = intel_dp_link_status(link_status, i);
1062
1063 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1064 }
1065
1066
1067 #if 0
1068 static char *voltage_names[] = {
1069 "0.4V", "0.6V", "0.8V", "1.2V"
1070 };
1071 static char *pre_emph_names[] = {
1072 "0dB", "3.5dB", "6dB", "9.5dB"
1073 };
1074 static char *link_train_names[] = {
1075 "pattern 1", "pattern 2", "idle", "off"
1076 };
1077 #endif
1078
1079 /*
1080 * These are source-specific values; current Intel hardware supports
1081 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1082 */
1083 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1084
1085 static uint8_t
1086 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1087 {
1088 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1089 case DP_TRAIN_VOLTAGE_SWING_400:
1090 return DP_TRAIN_PRE_EMPHASIS_6;
1091 case DP_TRAIN_VOLTAGE_SWING_600:
1092 return DP_TRAIN_PRE_EMPHASIS_6;
1093 case DP_TRAIN_VOLTAGE_SWING_800:
1094 return DP_TRAIN_PRE_EMPHASIS_3_5;
1095 case DP_TRAIN_VOLTAGE_SWING_1200:
1096 default:
1097 return DP_TRAIN_PRE_EMPHASIS_0;
1098 }
1099 }
1100
1101 static void
1102 intel_get_adjust_train(struct intel_dp *intel_dp)
1103 {
1104 uint8_t v = 0;
1105 uint8_t p = 0;
1106 int lane;
1107
1108 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1109 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1110 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1111
1112 if (this_v > v)
1113 v = this_v;
1114 if (this_p > p)
1115 p = this_p;
1116 }
1117
1118 if (v >= I830_DP_VOLTAGE_MAX)
1119 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1120
1121 if (p >= intel_dp_pre_emphasis_max(v))
1122 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1123
1124 for (lane = 0; lane < 4; lane++)
1125 intel_dp->train_set[lane] = v | p;
1126 }
1127
1128 static uint32_t
1129 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1130 {
1131 uint32_t signal_levels = 0;
1132
1133 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1134 case DP_TRAIN_VOLTAGE_SWING_400:
1135 default:
1136 signal_levels |= DP_VOLTAGE_0_4;
1137 break;
1138 case DP_TRAIN_VOLTAGE_SWING_600:
1139 signal_levels |= DP_VOLTAGE_0_6;
1140 break;
1141 case DP_TRAIN_VOLTAGE_SWING_800:
1142 signal_levels |= DP_VOLTAGE_0_8;
1143 break;
1144 case DP_TRAIN_VOLTAGE_SWING_1200:
1145 signal_levels |= DP_VOLTAGE_1_2;
1146 break;
1147 }
1148 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1149 case DP_TRAIN_PRE_EMPHASIS_0:
1150 default:
1151 signal_levels |= DP_PRE_EMPHASIS_0;
1152 break;
1153 case DP_TRAIN_PRE_EMPHASIS_3_5:
1154 signal_levels |= DP_PRE_EMPHASIS_3_5;
1155 break;
1156 case DP_TRAIN_PRE_EMPHASIS_6:
1157 signal_levels |= DP_PRE_EMPHASIS_6;
1158 break;
1159 case DP_TRAIN_PRE_EMPHASIS_9_5:
1160 signal_levels |= DP_PRE_EMPHASIS_9_5;
1161 break;
1162 }
1163 return signal_levels;
1164 }
1165
1166 /* Gen6's DP voltage swing and pre-emphasis control */
1167 static uint32_t
1168 intel_gen6_edp_signal_levels(uint8_t train_set)
1169 {
1170 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1171 DP_TRAIN_PRE_EMPHASIS_MASK);
1172 switch (signal_levels) {
1173 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1174 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1175 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1176 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1177 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1178 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1179 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1180 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1181 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1182 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1183 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1184 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1185 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1186 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1187 default:
1188 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1189 "0x%x\n", signal_levels);
1190 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1191 }
1192 }
1193
1194 static uint8_t
1195 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1196 int lane)
1197 {
1198 int i = DP_LANE0_1_STATUS + (lane >> 1);
1199 int s = (lane & 1) * 4;
1200 uint8_t l = intel_dp_link_status(link_status, i);
1201
1202 return (l >> s) & 0xf;
1203 }
1204
1205 /* Check for clock recovery is done on all channels */
1206 static bool
1207 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1208 {
1209 int lane;
1210 uint8_t lane_status;
1211
1212 for (lane = 0; lane < lane_count; lane++) {
1213 lane_status = intel_get_lane_status(link_status, lane);
1214 if ((lane_status & DP_LANE_CR_DONE) == 0)
1215 return false;
1216 }
1217 return true;
1218 }
1219
1220 /* Check to see if channel eq is done on all channels */
1221 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1222 DP_LANE_CHANNEL_EQ_DONE|\
1223 DP_LANE_SYMBOL_LOCKED)
1224 static bool
1225 intel_channel_eq_ok(struct intel_dp *intel_dp)
1226 {
1227 uint8_t lane_align;
1228 uint8_t lane_status;
1229 int lane;
1230
1231 lane_align = intel_dp_link_status(intel_dp->link_status,
1232 DP_LANE_ALIGN_STATUS_UPDATED);
1233 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1234 return false;
1235 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1236 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1237 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1238 return false;
1239 }
1240 return true;
1241 }
1242
1243 static bool
1244 intel_dp_set_link_train(struct intel_dp *intel_dp,
1245 uint32_t dp_reg_value,
1246 uint8_t dp_train_pat)
1247 {
1248 struct drm_device *dev = intel_dp->base.base.dev;
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 int ret;
1251
1252 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1253 POSTING_READ(intel_dp->output_reg);
1254
1255 intel_dp_aux_native_write_1(intel_dp,
1256 DP_TRAINING_PATTERN_SET,
1257 dp_train_pat);
1258
1259 ret = intel_dp_aux_native_write(intel_dp,
1260 DP_TRAINING_LANE0_SET,
1261 intel_dp->train_set, 4);
1262 if (ret != 4)
1263 return false;
1264
1265 return true;
1266 }
1267
1268 /* Enable corresponding port and start training pattern 1 */
1269 static void
1270 intel_dp_start_link_train(struct intel_dp *intel_dp)
1271 {
1272 struct drm_device *dev = intel_dp->base.base.dev;
1273 struct drm_i915_private *dev_priv = dev->dev_private;
1274 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1275 int i;
1276 uint8_t voltage;
1277 bool clock_recovery = false;
1278 int tries;
1279 u32 reg;
1280 uint32_t DP = intel_dp->DP;
1281
1282 /* Enable output, wait for it to become active */
1283 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1284 POSTING_READ(intel_dp->output_reg);
1285 intel_wait_for_vblank(dev, intel_crtc->pipe);
1286
1287 /* Write the link configuration data */
1288 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1289 intel_dp->link_configuration,
1290 DP_LINK_CONFIGURATION_SIZE);
1291
1292 DP |= DP_PORT_EN;
1293 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1294 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1295 else
1296 DP &= ~DP_LINK_TRAIN_MASK;
1297 memset(intel_dp->train_set, 0, 4);
1298 voltage = 0xff;
1299 tries = 0;
1300 clock_recovery = false;
1301 for (;;) {
1302 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1303 uint32_t signal_levels;
1304 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1305 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1306 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1307 } else {
1308 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1309 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1310 }
1311
1312 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1313 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1314 else
1315 reg = DP | DP_LINK_TRAIN_PAT_1;
1316
1317 if (!intel_dp_set_link_train(intel_dp, reg,
1318 DP_TRAINING_PATTERN_1))
1319 break;
1320 /* Set training pattern 1 */
1321
1322 udelay(100);
1323 if (!intel_dp_get_link_status(intel_dp))
1324 break;
1325
1326 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1327 clock_recovery = true;
1328 break;
1329 }
1330
1331 /* Check to see if we've tried the max voltage */
1332 for (i = 0; i < intel_dp->lane_count; i++)
1333 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1334 break;
1335 if (i == intel_dp->lane_count)
1336 break;
1337
1338 /* Check to see if we've tried the same voltage 5 times */
1339 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1340 ++tries;
1341 if (tries == 5)
1342 break;
1343 } else
1344 tries = 0;
1345 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1346
1347 /* Compute new intel_dp->train_set as requested by target */
1348 intel_get_adjust_train(intel_dp);
1349 }
1350
1351 intel_dp->DP = DP;
1352 }
1353
1354 static void
1355 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1356 {
1357 struct drm_device *dev = intel_dp->base.base.dev;
1358 struct drm_i915_private *dev_priv = dev->dev_private;
1359 bool channel_eq = false;
1360 int tries, cr_tries;
1361 u32 reg;
1362 uint32_t DP = intel_dp->DP;
1363
1364 /* channel equalization */
1365 tries = 0;
1366 cr_tries = 0;
1367 channel_eq = false;
1368 for (;;) {
1369 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1370 uint32_t signal_levels;
1371
1372 if (cr_tries > 5) {
1373 DRM_ERROR("failed to train DP, aborting\n");
1374 intel_dp_link_down(intel_dp);
1375 break;
1376 }
1377
1378 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1379 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1380 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1381 } else {
1382 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1383 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1384 }
1385
1386 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1387 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1388 else
1389 reg = DP | DP_LINK_TRAIN_PAT_2;
1390
1391 /* channel eq pattern */
1392 if (!intel_dp_set_link_train(intel_dp, reg,
1393 DP_TRAINING_PATTERN_2))
1394 break;
1395
1396 udelay(400);
1397 if (!intel_dp_get_link_status(intel_dp))
1398 break;
1399
1400 /* Make sure clock is still ok */
1401 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1402 intel_dp_start_link_train(intel_dp);
1403 cr_tries++;
1404 continue;
1405 }
1406
1407 if (intel_channel_eq_ok(intel_dp)) {
1408 channel_eq = true;
1409 break;
1410 }
1411
1412 /* Try 5 times, then try clock recovery if that fails */
1413 if (tries > 5) {
1414 intel_dp_link_down(intel_dp);
1415 intel_dp_start_link_train(intel_dp);
1416 tries = 0;
1417 cr_tries++;
1418 continue;
1419 }
1420
1421 /* Compute new intel_dp->train_set as requested by target */
1422 intel_get_adjust_train(intel_dp);
1423 ++tries;
1424 }
1425
1426 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1427 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1428 else
1429 reg = DP | DP_LINK_TRAIN_OFF;
1430
1431 I915_WRITE(intel_dp->output_reg, reg);
1432 POSTING_READ(intel_dp->output_reg);
1433 intel_dp_aux_native_write_1(intel_dp,
1434 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1435 }
1436
1437 static void
1438 intel_dp_link_down(struct intel_dp *intel_dp)
1439 {
1440 struct drm_device *dev = intel_dp->base.base.dev;
1441 struct drm_i915_private *dev_priv = dev->dev_private;
1442 uint32_t DP = intel_dp->DP;
1443
1444 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1445 return;
1446
1447 DRM_DEBUG_KMS("\n");
1448
1449 if (is_edp(intel_dp)) {
1450 DP &= ~DP_PLL_ENABLE;
1451 I915_WRITE(intel_dp->output_reg, DP);
1452 POSTING_READ(intel_dp->output_reg);
1453 udelay(100);
1454 }
1455
1456 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1457 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1458 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1459 } else {
1460 DP &= ~DP_LINK_TRAIN_MASK;
1461 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1462 }
1463 POSTING_READ(intel_dp->output_reg);
1464
1465 msleep(17);
1466
1467 if (is_edp(intel_dp))
1468 DP |= DP_LINK_TRAIN_OFF;
1469
1470 if (!HAS_PCH_CPT(dev) &&
1471 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1472 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1473 /* Hardware workaround: leaving our transcoder select
1474 * set to transcoder B while it's off will prevent the
1475 * corresponding HDMI output on transcoder A.
1476 *
1477 * Combine this with another hardware workaround:
1478 * transcoder select bit can only be cleared while the
1479 * port is enabled.
1480 */
1481 DP &= ~DP_PIPEB_SELECT;
1482 I915_WRITE(intel_dp->output_reg, DP);
1483
1484 /* Changes to enable or select take place the vblank
1485 * after being written.
1486 */
1487 intel_wait_for_vblank(dev, intel_crtc->pipe);
1488 }
1489
1490 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1491 POSTING_READ(intel_dp->output_reg);
1492 }
1493
1494 /*
1495 * According to DP spec
1496 * 5.1.2:
1497 * 1. Read DPCD
1498 * 2. Configure link according to Receiver Capabilities
1499 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1500 * 4. Check link status on receipt of hot-plug interrupt
1501 */
1502
1503 static void
1504 intel_dp_check_link_status(struct intel_dp *intel_dp)
1505 {
1506 if (!intel_dp->base.base.crtc)
1507 return;
1508
1509 if (!intel_dp_get_link_status(intel_dp)) {
1510 intel_dp_link_down(intel_dp);
1511 return;
1512 }
1513
1514 if (!intel_channel_eq_ok(intel_dp)) {
1515 intel_dp_start_link_train(intel_dp);
1516 intel_dp_complete_link_train(intel_dp);
1517 }
1518 }
1519
1520 static enum drm_connector_status
1521 ironlake_dp_detect(struct intel_dp *intel_dp)
1522 {
1523 enum drm_connector_status status;
1524
1525 /* Can't disconnect eDP, but you can close the lid... */
1526 if (is_edp(intel_dp)) {
1527 status = intel_panel_detect(intel_dp->base.base.dev);
1528 if (status == connector_status_unknown)
1529 status = connector_status_connected;
1530 return status;
1531 }
1532
1533 status = connector_status_disconnected;
1534 if (intel_dp_aux_native_read(intel_dp,
1535 0x000, intel_dp->dpcd,
1536 sizeof (intel_dp->dpcd))
1537 == sizeof(intel_dp->dpcd)) {
1538 if (intel_dp->dpcd[0] != 0)
1539 status = connector_status_connected;
1540 }
1541 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1542 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1543 return status;
1544 }
1545
1546 static enum drm_connector_status
1547 g4x_dp_detect(struct intel_dp *intel_dp)
1548 {
1549 struct drm_device *dev = intel_dp->base.base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 enum drm_connector_status status;
1552 uint32_t temp, bit;
1553
1554 switch (intel_dp->output_reg) {
1555 case DP_B:
1556 bit = DPB_HOTPLUG_INT_STATUS;
1557 break;
1558 case DP_C:
1559 bit = DPC_HOTPLUG_INT_STATUS;
1560 break;
1561 case DP_D:
1562 bit = DPD_HOTPLUG_INT_STATUS;
1563 break;
1564 default:
1565 return connector_status_unknown;
1566 }
1567
1568 temp = I915_READ(PORT_HOTPLUG_STAT);
1569
1570 if ((temp & bit) == 0)
1571 return connector_status_disconnected;
1572
1573 status = connector_status_disconnected;
1574 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1575 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1576 {
1577 if (intel_dp->dpcd[0] != 0)
1578 status = connector_status_connected;
1579 }
1580
1581 return status;
1582 }
1583
1584 /**
1585 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1586 *
1587 * \return true if DP port is connected.
1588 * \return false if DP port is disconnected.
1589 */
1590 static enum drm_connector_status
1591 intel_dp_detect(struct drm_connector *connector, bool force)
1592 {
1593 struct intel_dp *intel_dp = intel_attached_dp(connector);
1594 struct drm_device *dev = intel_dp->base.base.dev;
1595 enum drm_connector_status status;
1596 struct edid *edid = NULL;
1597
1598 intel_dp->has_audio = false;
1599
1600 if (HAS_PCH_SPLIT(dev))
1601 status = ironlake_dp_detect(intel_dp);
1602 else
1603 status = g4x_dp_detect(intel_dp);
1604 if (status != connector_status_connected)
1605 return status;
1606
1607 if (intel_dp->force_audio) {
1608 intel_dp->has_audio = intel_dp->force_audio > 0;
1609 } else {
1610 edid = drm_get_edid(connector, &intel_dp->adapter);
1611 if (edid) {
1612 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1613 connector->display_info.raw_edid = NULL;
1614 kfree(edid);
1615 }
1616 }
1617
1618 return connector_status_connected;
1619 }
1620
1621 static int intel_dp_get_modes(struct drm_connector *connector)
1622 {
1623 struct intel_dp *intel_dp = intel_attached_dp(connector);
1624 struct drm_device *dev = intel_dp->base.base.dev;
1625 struct drm_i915_private *dev_priv = dev->dev_private;
1626 int ret;
1627
1628 /* We should parse the EDID data and find out if it has an audio sink
1629 */
1630
1631 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1632 if (ret) {
1633 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1634 struct drm_display_mode *newmode;
1635 list_for_each_entry(newmode, &connector->probed_modes,
1636 head) {
1637 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1638 dev_priv->panel_fixed_mode =
1639 drm_mode_duplicate(dev, newmode);
1640 break;
1641 }
1642 }
1643 }
1644
1645 return ret;
1646 }
1647
1648 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1649 if (is_edp(intel_dp)) {
1650 if (dev_priv->panel_fixed_mode != NULL) {
1651 struct drm_display_mode *mode;
1652 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1653 drm_mode_probed_add(connector, mode);
1654 return 1;
1655 }
1656 }
1657 return 0;
1658 }
1659
1660 static int
1661 intel_dp_set_property(struct drm_connector *connector,
1662 struct drm_property *property,
1663 uint64_t val)
1664 {
1665 struct intel_dp *intel_dp = intel_attached_dp(connector);
1666 int ret;
1667
1668 ret = drm_connector_property_set_value(connector, property, val);
1669 if (ret)
1670 return ret;
1671
1672 if (property == intel_dp->force_audio_property) {
1673 if (val == intel_dp->force_audio)
1674 return 0;
1675
1676 intel_dp->force_audio = val;
1677
1678 if (val > 0 && intel_dp->has_audio)
1679 return 0;
1680 if (val < 0 && !intel_dp->has_audio)
1681 return 0;
1682
1683 intel_dp->has_audio = val > 0;
1684 goto done;
1685 }
1686
1687 return -EINVAL;
1688
1689 done:
1690 if (intel_dp->base.base.crtc) {
1691 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1692 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1693 crtc->x, crtc->y,
1694 crtc->fb);
1695 }
1696
1697 return 0;
1698 }
1699
1700 static void
1701 intel_dp_destroy (struct drm_connector *connector)
1702 {
1703 drm_sysfs_connector_remove(connector);
1704 drm_connector_cleanup(connector);
1705 kfree(connector);
1706 }
1707
1708 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1709 {
1710 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1711
1712 i2c_del_adapter(&intel_dp->adapter);
1713 drm_encoder_cleanup(encoder);
1714 kfree(intel_dp);
1715 }
1716
1717 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1718 .dpms = intel_dp_dpms,
1719 .mode_fixup = intel_dp_mode_fixup,
1720 .prepare = intel_dp_prepare,
1721 .mode_set = intel_dp_mode_set,
1722 .commit = intel_dp_commit,
1723 };
1724
1725 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1726 .dpms = drm_helper_connector_dpms,
1727 .detect = intel_dp_detect,
1728 .fill_modes = drm_helper_probe_single_connector_modes,
1729 .set_property = intel_dp_set_property,
1730 .destroy = intel_dp_destroy,
1731 };
1732
1733 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1734 .get_modes = intel_dp_get_modes,
1735 .mode_valid = intel_dp_mode_valid,
1736 .best_encoder = intel_best_encoder,
1737 };
1738
1739 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1740 .destroy = intel_dp_encoder_destroy,
1741 };
1742
1743 static void
1744 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1745 {
1746 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1747
1748 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1749 intel_dp_check_link_status(intel_dp);
1750 }
1751
1752 /* Return which DP Port should be selected for Transcoder DP control */
1753 int
1754 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1755 {
1756 struct drm_device *dev = crtc->dev;
1757 struct drm_mode_config *mode_config = &dev->mode_config;
1758 struct drm_encoder *encoder;
1759
1760 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1761 struct intel_dp *intel_dp;
1762
1763 if (encoder->crtc != crtc)
1764 continue;
1765
1766 intel_dp = enc_to_intel_dp(encoder);
1767 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1768 return intel_dp->output_reg;
1769 }
1770
1771 return -1;
1772 }
1773
1774 /* check the VBT to see whether the eDP is on DP-D port */
1775 bool intel_dpd_is_edp(struct drm_device *dev)
1776 {
1777 struct drm_i915_private *dev_priv = dev->dev_private;
1778 struct child_device_config *p_child;
1779 int i;
1780
1781 if (!dev_priv->child_dev_num)
1782 return false;
1783
1784 for (i = 0; i < dev_priv->child_dev_num; i++) {
1785 p_child = dev_priv->child_dev + i;
1786
1787 if (p_child->dvo_port == PORT_IDPD &&
1788 p_child->device_type == DEVICE_TYPE_eDP)
1789 return true;
1790 }
1791 return false;
1792 }
1793
1794 static void
1795 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1796 {
1797 struct drm_device *dev = connector->dev;
1798
1799 intel_dp->force_audio_property =
1800 drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2);
1801 if (intel_dp->force_audio_property) {
1802 intel_dp->force_audio_property->values[0] = -1;
1803 intel_dp->force_audio_property->values[1] = 1;
1804 drm_connector_attach_property(connector, intel_dp->force_audio_property, 0);
1805 }
1806 }
1807
1808 void
1809 intel_dp_init(struct drm_device *dev, int output_reg)
1810 {
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 struct drm_connector *connector;
1813 struct intel_dp *intel_dp;
1814 struct intel_encoder *intel_encoder;
1815 struct intel_connector *intel_connector;
1816 const char *name = NULL;
1817 int type;
1818
1819 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1820 if (!intel_dp)
1821 return;
1822
1823 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1824 if (!intel_connector) {
1825 kfree(intel_dp);
1826 return;
1827 }
1828 intel_encoder = &intel_dp->base;
1829
1830 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1831 if (intel_dpd_is_edp(dev))
1832 intel_dp->is_pch_edp = true;
1833
1834 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1835 type = DRM_MODE_CONNECTOR_eDP;
1836 intel_encoder->type = INTEL_OUTPUT_EDP;
1837 } else {
1838 type = DRM_MODE_CONNECTOR_DisplayPort;
1839 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1840 }
1841
1842 connector = &intel_connector->base;
1843 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1844 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1845
1846 connector->polled = DRM_CONNECTOR_POLL_HPD;
1847
1848 if (output_reg == DP_B || output_reg == PCH_DP_B)
1849 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1850 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1851 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1852 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1853 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1854
1855 if (is_edp(intel_dp))
1856 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1857
1858 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1859 connector->interlace_allowed = true;
1860 connector->doublescan_allowed = 0;
1861
1862 intel_dp->output_reg = output_reg;
1863 intel_dp->has_audio = false;
1864 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1865
1866 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1867 DRM_MODE_ENCODER_TMDS);
1868 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1869
1870 intel_connector_attach_encoder(intel_connector, intel_encoder);
1871 drm_sysfs_connector_add(connector);
1872
1873 /* Set up the DDC bus. */
1874 switch (output_reg) {
1875 case DP_A:
1876 name = "DPDDC-A";
1877 break;
1878 case DP_B:
1879 case PCH_DP_B:
1880 dev_priv->hotplug_supported_mask |=
1881 HDMIB_HOTPLUG_INT_STATUS;
1882 name = "DPDDC-B";
1883 break;
1884 case DP_C:
1885 case PCH_DP_C:
1886 dev_priv->hotplug_supported_mask |=
1887 HDMIC_HOTPLUG_INT_STATUS;
1888 name = "DPDDC-C";
1889 break;
1890 case DP_D:
1891 case PCH_DP_D:
1892 dev_priv->hotplug_supported_mask |=
1893 HDMID_HOTPLUG_INT_STATUS;
1894 name = "DPDDC-D";
1895 break;
1896 }
1897
1898 intel_dp_i2c_init(intel_dp, intel_connector, name);
1899
1900 /* Cache some DPCD data in the eDP case */
1901 if (is_edp(intel_dp)) {
1902 int ret;
1903 u32 pp_on, pp_div;
1904
1905 pp_on = I915_READ(PCH_PP_ON_DELAYS);
1906 pp_div = I915_READ(PCH_PP_DIVISOR);
1907
1908 /* Get T3 & T12 values (note: VESA not bspec terminology) */
1909 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
1910 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
1911 dev_priv->panel_t12 = pp_div & 0xf;
1912 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
1913
1914 ironlake_edp_panel_vdd_on(intel_dp);
1915 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1916 intel_dp->dpcd,
1917 sizeof(intel_dp->dpcd));
1918 if (ret == sizeof(intel_dp->dpcd)) {
1919 if (intel_dp->dpcd[0] >= 0x11)
1920 dev_priv->no_aux_handshake = intel_dp->dpcd[3] &
1921 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1922 } else {
1923 DRM_ERROR("failed to retrieve link info\n");
1924 }
1925 ironlake_edp_panel_vdd_off(intel_dp);
1926 }
1927
1928 intel_encoder->hot_plug = intel_dp_hot_plug;
1929
1930 if (is_edp(intel_dp)) {
1931 /* initialize panel mode from VBT if available for eDP */
1932 if (dev_priv->lfp_lvds_vbt_mode) {
1933 dev_priv->panel_fixed_mode =
1934 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1935 if (dev_priv->panel_fixed_mode) {
1936 dev_priv->panel_fixed_mode->type |=
1937 DRM_MODE_TYPE_PREFERRED;
1938 }
1939 }
1940 }
1941
1942 intel_dp_add_properties(intel_dp, connector);
1943
1944 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1945 * 0xd. Failure to do so will result in spurious interrupts being
1946 * generated on the port when a cable is not attached.
1947 */
1948 if (IS_G4X(dev) && !IS_GM45(dev)) {
1949 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1950 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1951 }
1952 }
Linux kernel - Deliverables
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