projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: don't disable DP port after a failed link training
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44 };
45
46 static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51 };
52
53 static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58 };
59
60 static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65 };
66
67 /**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74 static bool is_edp(struct intel_dp *intel_dp)
75 {
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
79 }
80
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
82 {
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
86 }
87
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89 {
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
91 }
92
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94
95 static int
96 intel_dp_max_link_bw(struct intel_dp *intel_dp)
97 {
98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
107 default:
108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114 }
115
116 /*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
133 static int
134 intel_dp_link_required(int pixel_clock, int bpp)
135 {
136 return (pixel_clock * bpp + 9) / 10;
137 }
138
139 static int
140 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141 {
142 return (max_link_clock * max_lanes * 8) / 10;
143 }
144
145 static enum drm_mode_status
146 intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148 {
149 struct intel_dp *intel_dp = intel_attached_dp(connector);
150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
154
155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
157 return MODE_PANEL;
158
159 if (mode->vdisplay > fixed_mode->vdisplay)
160 return MODE_PANEL;
161
162 target_clock = fixed_mode->clock;
163 }
164
165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
172 return MODE_CLOCK_HIGH;
173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
180 return MODE_OK;
181 }
182
183 static uint32_t
184 pack_aux(uint8_t *src, int src_bytes)
185 {
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194 }
195
196 static void
197 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198 {
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204 }
205
206 /* hrawclock is 1/4 the FSB frequency */
207 static int
208 intel_hrawclk(struct drm_device *dev)
209 {
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238 }
239
240 static void
241 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244 static void
245 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249 static enum pipe
250 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251 {
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275 }
276
277 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278 {
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285 }
286
287 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288 {
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295 }
296
297 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298 {
299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
300 struct drm_i915_private *dev_priv = dev->dev_private;
301
302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
303 }
304
305 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306 {
307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
308 struct drm_i915_private *dev_priv = dev->dev_private;
309
310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
311 }
312
313 static void
314 intel_dp_check_edp(struct intel_dp *intel_dp)
315 {
316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
317 struct drm_i915_private *dev_priv = dev->dev_private;
318
319 if (!is_edp(intel_dp))
320 return;
321
322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
327 }
328 }
329
330 static uint32_t
331 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332 {
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
337 uint32_t status;
338 bool done;
339
340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
341 if (has_aux_irq)
342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
343 msecs_to_jiffies_timeout(10));
344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349 #undef C
350
351 return status;
352 }
353
354 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
356 {
357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
359 struct drm_i915_private *dev_priv = dev->dev_private;
360
361 /* The clock divider is based off the hrawclk,
362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
367 */
368 if (IS_VALLEYVIEW(dev)) {
369 return index ? 0 : 100;
370 } else if (intel_dig_port->port == PORT_A) {
371 if (index)
372 return 0;
373 if (HAS_DDI(dev))
374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
377 else
378 return 225; /* eDP input clock at 450Mhz */
379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
386 } else if (HAS_PCH_SPLIT(dev)) {
387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
388 } else {
389 return index ? 0 :intel_hrawclk(dev) / 2;
390 }
391 }
392
393 static int
394 intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397 {
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
403 uint32_t aux_clock_divider;
404 int i, ret, recv_bytes;
405 uint32_t status;
406 int try, precharge, clock = 0;
407 bool has_aux_irq = true;
408 uint32_t timeout;
409
410 /* dp aux is extremely sensitive to irq latency, hence request the
411 * lowest possible wakeup latency and so prevent the cpu from going into
412 * deep sleep states.
413 */
414 pm_qos_update_request(&dev_priv->pm_qos, 0);
415
416 intel_dp_check_edp(intel_dp);
417
418 if (IS_GEN6(dev))
419 precharge = 3;
420 else
421 precharge = 5;
422
423 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
424 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
425 else
426 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
427
428 intel_aux_display_runtime_get(dev_priv);
429
430 /* Try to wait for any previous AUX channel activity */
431 for (try = 0; try < 3; try++) {
432 status = I915_READ_NOTRACE(ch_ctl);
433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
434 break;
435 msleep(1);
436 }
437
438 if (try == 3) {
439 WARN(1, "dp_aux_ch not started status 0x%08x\n",
440 I915_READ(ch_ctl));
441 ret = -EBUSY;
442 goto out;
443 }
444
445 /* Only 5 data registers! */
446 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
447 ret = -E2BIG;
448 goto out;
449 }
450
451 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
452 /* Must try at least 3 times according to DP spec */
453 for (try = 0; try < 5; try++) {
454 /* Load the send data into the aux channel data registers */
455 for (i = 0; i < send_bytes; i += 4)
456 I915_WRITE(ch_data + i,
457 pack_aux(send + i, send_bytes - i));
458
459 /* Send the command and wait for it to complete */
460 I915_WRITE(ch_ctl,
461 DP_AUX_CH_CTL_SEND_BUSY |
462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
463 timeout |
464 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
465 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
466 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
467 DP_AUX_CH_CTL_DONE |
468 DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR);
470
471 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
472
473 /* Clear done status and any errors */
474 I915_WRITE(ch_ctl,
475 status |
476 DP_AUX_CH_CTL_DONE |
477 DP_AUX_CH_CTL_TIME_OUT_ERROR |
478 DP_AUX_CH_CTL_RECEIVE_ERROR);
479
480 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR))
482 continue;
483 if (status & DP_AUX_CH_CTL_DONE)
484 break;
485 }
486 if (status & DP_AUX_CH_CTL_DONE)
487 break;
488 }
489
490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
492 ret = -EBUSY;
493 goto out;
494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
501 ret = -EIO;
502 goto out;
503 }
504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
509 ret = -ETIMEDOUT;
510 goto out;
511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
518
519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
522
523 ret = recv_bytes;
524 out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526 intel_aux_display_runtime_put(dev_priv);
527
528 return ret;
529 }
530
531 /* Write data to the aux channel in native mode */
532 static int
533 intel_dp_aux_native_write(struct intel_dp *intel_dp,
534 uint16_t address, uint8_t *send, int send_bytes)
535 {
536 int ret;
537 uint8_t msg[20];
538 int msg_bytes;
539 uint8_t ack;
540
541 if (WARN_ON(send_bytes > 16))
542 return -E2BIG;
543
544 intel_dp_check_edp(intel_dp);
545 msg[0] = DP_AUX_NATIVE_WRITE << 4;
546 msg[1] = address >> 8;
547 msg[2] = address & 0xff;
548 msg[3] = send_bytes - 1;
549 memcpy(&msg[4], send, send_bytes);
550 msg_bytes = send_bytes + 4;
551 for (;;) {
552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
553 if (ret < 0)
554 return ret;
555 ack >>= 4;
556 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
557 break;
558 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
559 udelay(100);
560 else
561 return -EIO;
562 }
563 return send_bytes;
564 }
565
566 /* Write a single byte to the aux channel in native mode */
567 static int
568 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
569 uint16_t address, uint8_t byte)
570 {
571 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
572 }
573
574 /* read bytes from a native aux channel */
575 static int
576 intel_dp_aux_native_read(struct intel_dp *intel_dp,
577 uint16_t address, uint8_t *recv, int recv_bytes)
578 {
579 uint8_t msg[4];
580 int msg_bytes;
581 uint8_t reply[20];
582 int reply_bytes;
583 uint8_t ack;
584 int ret;
585
586 if (WARN_ON(recv_bytes > 19))
587 return -E2BIG;
588
589 intel_dp_check_edp(intel_dp);
590 msg[0] = DP_AUX_NATIVE_READ << 4;
591 msg[1] = address >> 8;
592 msg[2] = address & 0xff;
593 msg[3] = recv_bytes - 1;
594
595 msg_bytes = 4;
596 reply_bytes = recv_bytes + 1;
597
598 for (;;) {
599 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
600 reply, reply_bytes);
601 if (ret == 0)
602 return -EPROTO;
603 if (ret < 0)
604 return ret;
605 ack = reply[0] >> 4;
606 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
607 memcpy(recv, reply + 1, ret - 1);
608 return ret - 1;
609 }
610 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
611 udelay(100);
612 else
613 return -EIO;
614 }
615 }
616
617 static int
618 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
619 uint8_t write_byte, uint8_t *read_byte)
620 {
621 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
622 struct intel_dp *intel_dp = container_of(adapter,
623 struct intel_dp,
624 adapter);
625 uint16_t address = algo_data->address;
626 uint8_t msg[5];
627 uint8_t reply[2];
628 unsigned retry;
629 int msg_bytes;
630 int reply_bytes;
631 int ret;
632
633 ironlake_edp_panel_vdd_on(intel_dp);
634 intel_dp_check_edp(intel_dp);
635 /* Set up the command byte */
636 if (mode & MODE_I2C_READ)
637 msg[0] = DP_AUX_I2C_READ << 4;
638 else
639 msg[0] = DP_AUX_I2C_WRITE << 4;
640
641 if (!(mode & MODE_I2C_STOP))
642 msg[0] |= DP_AUX_I2C_MOT << 4;
643
644 msg[1] = address >> 8;
645 msg[2] = address;
646
647 switch (mode) {
648 case MODE_I2C_WRITE:
649 msg[3] = 0;
650 msg[4] = write_byte;
651 msg_bytes = 5;
652 reply_bytes = 1;
653 break;
654 case MODE_I2C_READ:
655 msg[3] = 0;
656 msg_bytes = 4;
657 reply_bytes = 2;
658 break;
659 default:
660 msg_bytes = 3;
661 reply_bytes = 1;
662 break;
663 }
664
665 /*
666 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
667 * required to retry at least seven times upon receiving AUX_DEFER
668 * before giving up the AUX transaction.
669 */
670 for (retry = 0; retry < 7; retry++) {
671 ret = intel_dp_aux_ch(intel_dp,
672 msg, msg_bytes,
673 reply, reply_bytes);
674 if (ret < 0) {
675 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
676 goto out;
677 }
678
679 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
680 case DP_AUX_NATIVE_REPLY_ACK:
681 /* I2C-over-AUX Reply field is only valid
682 * when paired with AUX ACK.
683 */
684 break;
685 case DP_AUX_NATIVE_REPLY_NACK:
686 DRM_DEBUG_KMS("aux_ch native nack\n");
687 ret = -EREMOTEIO;
688 goto out;
689 case DP_AUX_NATIVE_REPLY_DEFER:
690 /*
691 * For now, just give more slack to branch devices. We
692 * could check the DPCD for I2C bit rate capabilities,
693 * and if available, adjust the interval. We could also
694 * be more careful with DP-to-Legacy adapters where a
695 * long legacy cable may force very low I2C bit rates.
696 */
697 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
698 DP_DWN_STRM_PORT_PRESENT)
699 usleep_range(500, 600);
700 else
701 usleep_range(300, 400);
702 continue;
703 default:
704 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
705 reply[0]);
706 ret = -EREMOTEIO;
707 goto out;
708 }
709
710 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
711 case DP_AUX_I2C_REPLY_ACK:
712 if (mode == MODE_I2C_READ) {
713 *read_byte = reply[1];
714 }
715 ret = reply_bytes - 1;
716 goto out;
717 case DP_AUX_I2C_REPLY_NACK:
718 DRM_DEBUG_KMS("aux_i2c nack\n");
719 ret = -EREMOTEIO;
720 goto out;
721 case DP_AUX_I2C_REPLY_DEFER:
722 DRM_DEBUG_KMS("aux_i2c defer\n");
723 udelay(100);
724 break;
725 default:
726 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
727 ret = -EREMOTEIO;
728 goto out;
729 }
730 }
731
732 DRM_ERROR("too many retries, giving up\n");
733 ret = -EREMOTEIO;
734
735 out:
736 ironlake_edp_panel_vdd_off(intel_dp, false);
737 return ret;
738 }
739
740 static int
741 intel_dp_i2c_init(struct intel_dp *intel_dp,
742 struct intel_connector *intel_connector, const char *name)
743 {
744 int ret;
745
746 DRM_DEBUG_KMS("i2c_init %s\n", name);
747 intel_dp->algo.running = false;
748 intel_dp->algo.address = 0;
749 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
750
751 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
752 intel_dp->adapter.owner = THIS_MODULE;
753 intel_dp->adapter.class = I2C_CLASS_DDC;
754 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
755 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
756 intel_dp->adapter.algo_data = &intel_dp->algo;
757 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
758
759 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
760 return ret;
761 }
762
763 static void
764 intel_dp_set_clock(struct intel_encoder *encoder,
765 struct intel_crtc_config *pipe_config, int link_bw)
766 {
767 struct drm_device *dev = encoder->base.dev;
768 const struct dp_link_dpll *divisor = NULL;
769 int i, count = 0;
770
771 if (IS_G4X(dev)) {
772 divisor = gen4_dpll;
773 count = ARRAY_SIZE(gen4_dpll);
774 } else if (IS_HASWELL(dev)) {
775 /* Haswell has special-purpose DP DDI clocks. */
776 } else if (HAS_PCH_SPLIT(dev)) {
777 divisor = pch_dpll;
778 count = ARRAY_SIZE(pch_dpll);
779 } else if (IS_VALLEYVIEW(dev)) {
780 divisor = vlv_dpll;
781 count = ARRAY_SIZE(vlv_dpll);
782 }
783
784 if (divisor && count) {
785 for (i = 0; i < count; i++) {
786 if (link_bw == divisor[i].link_bw) {
787 pipe_config->dpll = divisor[i].dpll;
788 pipe_config->clock_set = true;
789 break;
790 }
791 }
792 }
793 }
794
795 bool
796 intel_dp_compute_config(struct intel_encoder *encoder,
797 struct intel_crtc_config *pipe_config)
798 {
799 struct drm_device *dev = encoder->base.dev;
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
802 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
803 enum port port = dp_to_dig_port(intel_dp)->port;
804 struct intel_crtc *intel_crtc = encoder->new_crtc;
805 struct intel_connector *intel_connector = intel_dp->attached_connector;
806 int lane_count, clock;
807 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
808 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
809 int bpp, mode_rate;
810 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
811 int link_avail, link_clock;
812
813 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
814 pipe_config->has_pch_encoder = true;
815
816 pipe_config->has_dp_encoder = true;
817
818 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
819 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
820 adjusted_mode);
821 if (!HAS_PCH_SPLIT(dev))
822 intel_gmch_panel_fitting(intel_crtc, pipe_config,
823 intel_connector->panel.fitting_mode);
824 else
825 intel_pch_panel_fitting(intel_crtc, pipe_config,
826 intel_connector->panel.fitting_mode);
827 }
828
829 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
830 return false;
831
832 DRM_DEBUG_KMS("DP link computation with max lane count %i "
833 "max bw %02x pixel clock %iKHz\n",
834 max_lane_count, bws[max_clock],
835 adjusted_mode->crtc_clock);
836
837 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
838 * bpc in between. */
839 bpp = pipe_config->pipe_bpp;
840 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
841 dev_priv->vbt.edp_bpp < bpp) {
842 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
843 dev_priv->vbt.edp_bpp);
844 bpp = dev_priv->vbt.edp_bpp;
845 }
846
847 for (; bpp >= 6*3; bpp -= 2*3) {
848 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
849 bpp);
850
851 for (clock = 0; clock <= max_clock; clock++) {
852 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
853 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
854 link_avail = intel_dp_max_data_rate(link_clock,
855 lane_count);
856
857 if (mode_rate <= link_avail) {
858 goto found;
859 }
860 }
861 }
862 }
863
864 return false;
865
866 found:
867 if (intel_dp->color_range_auto) {
868 /*
869 * See:
870 * CEA-861-E - 5.1 Default Encoding Parameters
871 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
872 */
873 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
874 intel_dp->color_range = DP_COLOR_RANGE_16_235;
875 else
876 intel_dp->color_range = 0;
877 }
878
879 if (intel_dp->color_range)
880 pipe_config->limited_color_range = true;
881
882 intel_dp->link_bw = bws[clock];
883 intel_dp->lane_count = lane_count;
884 pipe_config->pipe_bpp = bpp;
885 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
886
887 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
888 intel_dp->link_bw, intel_dp->lane_count,
889 pipe_config->port_clock, bpp);
890 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
891 mode_rate, link_avail);
892
893 intel_link_compute_m_n(bpp, lane_count,
894 adjusted_mode->crtc_clock,
895 pipe_config->port_clock,
896 &pipe_config->dp_m_n);
897
898 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
899
900 return true;
901 }
902
903 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
904 {
905 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
906 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
907 struct drm_device *dev = crtc->base.dev;
908 struct drm_i915_private *dev_priv = dev->dev_private;
909 u32 dpa_ctl;
910
911 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
912 dpa_ctl = I915_READ(DP_A);
913 dpa_ctl &= ~DP_PLL_FREQ_MASK;
914
915 if (crtc->config.port_clock == 162000) {
916 /* For a long time we've carried around a ILK-DevA w/a for the
917 * 160MHz clock. If we're really unlucky, it's still required.
918 */
919 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
920 dpa_ctl |= DP_PLL_FREQ_160MHZ;
921 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
922 } else {
923 dpa_ctl |= DP_PLL_FREQ_270MHZ;
924 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
925 }
926
927 I915_WRITE(DP_A, dpa_ctl);
928
929 POSTING_READ(DP_A);
930 udelay(500);
931 }
932
933 static void intel_dp_mode_set(struct intel_encoder *encoder)
934 {
935 struct drm_device *dev = encoder->base.dev;
936 struct drm_i915_private *dev_priv = dev->dev_private;
937 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
938 enum port port = dp_to_dig_port(intel_dp)->port;
939 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
940 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
941
942 /*
943 * There are four kinds of DP registers:
944 *
945 * IBX PCH
946 * SNB CPU
947 * IVB CPU
948 * CPT PCH
949 *
950 * IBX PCH and CPU are the same for almost everything,
951 * except that the CPU DP PLL is configured in this
952 * register
953 *
954 * CPT PCH is quite different, having many bits moved
955 * to the TRANS_DP_CTL register instead. That
956 * configuration happens (oddly) in ironlake_pch_enable
957 */
958
959 /* Preserve the BIOS-computed detected bit. This is
960 * supposed to be read-only.
961 */
962 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
963
964 /* Handle DP bits in common between all three register formats */
965 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
966 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
967
968 if (intel_dp->has_audio) {
969 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
970 pipe_name(crtc->pipe));
971 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
972 intel_write_eld(&encoder->base, adjusted_mode);
973 }
974
975 /* Split out the IBX/CPU vs CPT settings */
976
977 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
978 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
979 intel_dp->DP |= DP_SYNC_HS_HIGH;
980 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
981 intel_dp->DP |= DP_SYNC_VS_HIGH;
982 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
983
984 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
985 intel_dp->DP |= DP_ENHANCED_FRAMING;
986
987 intel_dp->DP |= crtc->pipe << 29;
988 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
989 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
990 intel_dp->DP |= intel_dp->color_range;
991
992 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
993 intel_dp->DP |= DP_SYNC_HS_HIGH;
994 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
995 intel_dp->DP |= DP_SYNC_VS_HIGH;
996 intel_dp->DP |= DP_LINK_TRAIN_OFF;
997
998 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
999 intel_dp->DP |= DP_ENHANCED_FRAMING;
1000
1001 if (crtc->pipe == 1)
1002 intel_dp->DP |= DP_PIPEB_SELECT;
1003 } else {
1004 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1005 }
1006
1007 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1008 ironlake_set_pll_cpu_edp(intel_dp);
1009 }
1010
1011 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1012 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1013
1014 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1015 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1016
1017 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1018 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1019
1020 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1021 u32 mask,
1022 u32 value)
1023 {
1024 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1025 struct drm_i915_private *dev_priv = dev->dev_private;
1026 u32 pp_stat_reg, pp_ctrl_reg;
1027
1028 pp_stat_reg = _pp_stat_reg(intel_dp);
1029 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1030
1031 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1032 mask, value,
1033 I915_READ(pp_stat_reg),
1034 I915_READ(pp_ctrl_reg));
1035
1036 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1037 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1038 I915_READ(pp_stat_reg),
1039 I915_READ(pp_ctrl_reg));
1040 }
1041
1042 DRM_DEBUG_KMS("Wait complete\n");
1043 }
1044
1045 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1046 {
1047 DRM_DEBUG_KMS("Wait for panel power on\n");
1048 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1049 }
1050
1051 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1052 {
1053 DRM_DEBUG_KMS("Wait for panel power off time\n");
1054 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1055 }
1056
1057 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1058 {
1059 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1060 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1061 }
1062
1063
1064 /* Read the current pp_control value, unlocking the register if it
1065 * is locked
1066 */
1067
1068 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1069 {
1070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 u32 control;
1073
1074 control = I915_READ(_pp_ctrl_reg(intel_dp));
1075 control &= ~PANEL_UNLOCK_MASK;
1076 control |= PANEL_UNLOCK_REGS;
1077 return control;
1078 }
1079
1080 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1081 {
1082 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 u32 pp;
1085 u32 pp_stat_reg, pp_ctrl_reg;
1086
1087 if (!is_edp(intel_dp))
1088 return;
1089
1090 WARN(intel_dp->want_panel_vdd,
1091 "eDP VDD already requested on\n");
1092
1093 intel_dp->want_panel_vdd = true;
1094
1095 if (ironlake_edp_have_panel_vdd(intel_dp))
1096 return;
1097
1098 intel_runtime_pm_get(dev_priv);
1099
1100 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1101
1102 if (!ironlake_edp_have_panel_power(intel_dp))
1103 ironlake_wait_panel_power_cycle(intel_dp);
1104
1105 pp = ironlake_get_pp_control(intel_dp);
1106 pp |= EDP_FORCE_VDD;
1107
1108 pp_stat_reg = _pp_stat_reg(intel_dp);
1109 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1110
1111 I915_WRITE(pp_ctrl_reg, pp);
1112 POSTING_READ(pp_ctrl_reg);
1113 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1114 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1115 /*
1116 * If the panel wasn't on, delay before accessing aux channel
1117 */
1118 if (!ironlake_edp_have_panel_power(intel_dp)) {
1119 DRM_DEBUG_KMS("eDP was not running\n");
1120 msleep(intel_dp->panel_power_up_delay);
1121 }
1122 }
1123
1124 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1125 {
1126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128 u32 pp;
1129 u32 pp_stat_reg, pp_ctrl_reg;
1130
1131 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1132
1133 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1134 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1135
1136 pp = ironlake_get_pp_control(intel_dp);
1137 pp &= ~EDP_FORCE_VDD;
1138
1139 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1140 pp_stat_reg = _pp_stat_reg(intel_dp);
1141
1142 I915_WRITE(pp_ctrl_reg, pp);
1143 POSTING_READ(pp_ctrl_reg);
1144
1145 /* Make sure sequencer is idle before allowing subsequent activity */
1146 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1147 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1148
1149 if ((pp & POWER_TARGET_ON) == 0)
1150 msleep(intel_dp->panel_power_cycle_delay);
1151
1152 intel_runtime_pm_put(dev_priv);
1153 }
1154 }
1155
1156 static void ironlake_panel_vdd_work(struct work_struct *__work)
1157 {
1158 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1159 struct intel_dp, panel_vdd_work);
1160 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1161
1162 mutex_lock(&dev->mode_config.mutex);
1163 ironlake_panel_vdd_off_sync(intel_dp);
1164 mutex_unlock(&dev->mode_config.mutex);
1165 }
1166
1167 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1168 {
1169 if (!is_edp(intel_dp))
1170 return;
1171
1172 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1173
1174 intel_dp->want_panel_vdd = false;
1175
1176 if (sync) {
1177 ironlake_panel_vdd_off_sync(intel_dp);
1178 } else {
1179 /*
1180 * Queue the timer to fire a long
1181 * time from now (relative to the power down delay)
1182 * to keep the panel power up across a sequence of operations
1183 */
1184 schedule_delayed_work(&intel_dp->panel_vdd_work,
1185 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1186 }
1187 }
1188
1189 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1190 {
1191 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193 u32 pp;
1194 u32 pp_ctrl_reg;
1195
1196 if (!is_edp(intel_dp))
1197 return;
1198
1199 DRM_DEBUG_KMS("Turn eDP power on\n");
1200
1201 if (ironlake_edp_have_panel_power(intel_dp)) {
1202 DRM_DEBUG_KMS("eDP power already on\n");
1203 return;
1204 }
1205
1206 ironlake_wait_panel_power_cycle(intel_dp);
1207
1208 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1209 pp = ironlake_get_pp_control(intel_dp);
1210 if (IS_GEN5(dev)) {
1211 /* ILK workaround: disable reset around power sequence */
1212 pp &= ~PANEL_POWER_RESET;
1213 I915_WRITE(pp_ctrl_reg, pp);
1214 POSTING_READ(pp_ctrl_reg);
1215 }
1216
1217 pp |= POWER_TARGET_ON;
1218 if (!IS_GEN5(dev))
1219 pp |= PANEL_POWER_RESET;
1220
1221 I915_WRITE(pp_ctrl_reg, pp);
1222 POSTING_READ(pp_ctrl_reg);
1223
1224 ironlake_wait_panel_on(intel_dp);
1225
1226 if (IS_GEN5(dev)) {
1227 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1228 I915_WRITE(pp_ctrl_reg, pp);
1229 POSTING_READ(pp_ctrl_reg);
1230 }
1231 }
1232
1233 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1234 {
1235 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 u32 pp;
1238 u32 pp_ctrl_reg;
1239
1240 if (!is_edp(intel_dp))
1241 return;
1242
1243 DRM_DEBUG_KMS("Turn eDP power off\n");
1244
1245 pp = ironlake_get_pp_control(intel_dp);
1246 /* We need to switch off panel power _and_ force vdd, for otherwise some
1247 * panels get very unhappy and cease to work. */
1248 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1249
1250 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1251
1252 I915_WRITE(pp_ctrl_reg, pp);
1253 POSTING_READ(pp_ctrl_reg);
1254
1255 ironlake_wait_panel_off(intel_dp);
1256 }
1257
1258 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1259 {
1260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1261 struct drm_device *dev = intel_dig_port->base.base.dev;
1262 struct drm_i915_private *dev_priv = dev->dev_private;
1263 u32 pp;
1264 u32 pp_ctrl_reg;
1265
1266 if (!is_edp(intel_dp))
1267 return;
1268
1269 DRM_DEBUG_KMS("\n");
1270 /*
1271 * If we enable the backlight right away following a panel power
1272 * on, we may see slight flicker as the panel syncs with the eDP
1273 * link. So delay a bit to make sure the image is solid before
1274 * allowing it to appear.
1275 */
1276 msleep(intel_dp->backlight_on_delay);
1277 pp = ironlake_get_pp_control(intel_dp);
1278 pp |= EDP_BLC_ENABLE;
1279
1280 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1281
1282 I915_WRITE(pp_ctrl_reg, pp);
1283 POSTING_READ(pp_ctrl_reg);
1284
1285 intel_panel_enable_backlight(intel_dp->attached_connector);
1286 }
1287
1288 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1289 {
1290 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1291 struct drm_i915_private *dev_priv = dev->dev_private;
1292 u32 pp;
1293 u32 pp_ctrl_reg;
1294
1295 if (!is_edp(intel_dp))
1296 return;
1297
1298 intel_panel_disable_backlight(intel_dp->attached_connector);
1299
1300 DRM_DEBUG_KMS("\n");
1301 pp = ironlake_get_pp_control(intel_dp);
1302 pp &= ~EDP_BLC_ENABLE;
1303
1304 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1305
1306 I915_WRITE(pp_ctrl_reg, pp);
1307 POSTING_READ(pp_ctrl_reg);
1308 msleep(intel_dp->backlight_off_delay);
1309 }
1310
1311 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1312 {
1313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1314 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1315 struct drm_device *dev = crtc->dev;
1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 u32 dpa_ctl;
1318
1319 assert_pipe_disabled(dev_priv,
1320 to_intel_crtc(crtc)->pipe);
1321
1322 DRM_DEBUG_KMS("\n");
1323 dpa_ctl = I915_READ(DP_A);
1324 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1325 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1326
1327 /* We don't adjust intel_dp->DP while tearing down the link, to
1328 * facilitate link retraining (e.g. after hotplug). Hence clear all
1329 * enable bits here to ensure that we don't enable too much. */
1330 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1331 intel_dp->DP |= DP_PLL_ENABLE;
1332 I915_WRITE(DP_A, intel_dp->DP);
1333 POSTING_READ(DP_A);
1334 udelay(200);
1335 }
1336
1337 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1338 {
1339 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1340 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1341 struct drm_device *dev = crtc->dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 u32 dpa_ctl;
1344
1345 assert_pipe_disabled(dev_priv,
1346 to_intel_crtc(crtc)->pipe);
1347
1348 dpa_ctl = I915_READ(DP_A);
1349 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1350 "dp pll off, should be on\n");
1351 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1352
1353 /* We can't rely on the value tracked for the DP register in
1354 * intel_dp->DP because link_down must not change that (otherwise link
1355 * re-training will fail. */
1356 dpa_ctl &= ~DP_PLL_ENABLE;
1357 I915_WRITE(DP_A, dpa_ctl);
1358 POSTING_READ(DP_A);
1359 udelay(200);
1360 }
1361
1362 /* If the sink supports it, try to set the power state appropriately */
1363 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1364 {
1365 int ret, i;
1366
1367 /* Should have a valid DPCD by this point */
1368 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1369 return;
1370
1371 if (mode != DRM_MODE_DPMS_ON) {
1372 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1373 DP_SET_POWER_D3);
1374 if (ret != 1)
1375 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1376 } else {
1377 /*
1378 * When turning on, we need to retry for 1ms to give the sink
1379 * time to wake up.
1380 */
1381 for (i = 0; i < 3; i++) {
1382 ret = intel_dp_aux_native_write_1(intel_dp,
1383 DP_SET_POWER,
1384 DP_SET_POWER_D0);
1385 if (ret == 1)
1386 break;
1387 msleep(1);
1388 }
1389 }
1390 }
1391
1392 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1393 enum pipe *pipe)
1394 {
1395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1396 enum port port = dp_to_dig_port(intel_dp)->port;
1397 struct drm_device *dev = encoder->base.dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 u32 tmp = I915_READ(intel_dp->output_reg);
1400
1401 if (!(tmp & DP_PORT_EN))
1402 return false;
1403
1404 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1405 *pipe = PORT_TO_PIPE_CPT(tmp);
1406 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1407 *pipe = PORT_TO_PIPE(tmp);
1408 } else {
1409 u32 trans_sel;
1410 u32 trans_dp;
1411 int i;
1412
1413 switch (intel_dp->output_reg) {
1414 case PCH_DP_B:
1415 trans_sel = TRANS_DP_PORT_SEL_B;
1416 break;
1417 case PCH_DP_C:
1418 trans_sel = TRANS_DP_PORT_SEL_C;
1419 break;
1420 case PCH_DP_D:
1421 trans_sel = TRANS_DP_PORT_SEL_D;
1422 break;
1423 default:
1424 return true;
1425 }
1426
1427 for_each_pipe(i) {
1428 trans_dp = I915_READ(TRANS_DP_CTL(i));
1429 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1430 *pipe = i;
1431 return true;
1432 }
1433 }
1434
1435 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1436 intel_dp->output_reg);
1437 }
1438
1439 return true;
1440 }
1441
1442 static void intel_dp_get_config(struct intel_encoder *encoder,
1443 struct intel_crtc_config *pipe_config)
1444 {
1445 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1446 u32 tmp, flags = 0;
1447 struct drm_device *dev = encoder->base.dev;
1448 struct drm_i915_private *dev_priv = dev->dev_private;
1449 enum port port = dp_to_dig_port(intel_dp)->port;
1450 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1451 int dotclock;
1452
1453 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1454 tmp = I915_READ(intel_dp->output_reg);
1455 if (tmp & DP_SYNC_HS_HIGH)
1456 flags |= DRM_MODE_FLAG_PHSYNC;
1457 else
1458 flags |= DRM_MODE_FLAG_NHSYNC;
1459
1460 if (tmp & DP_SYNC_VS_HIGH)
1461 flags |= DRM_MODE_FLAG_PVSYNC;
1462 else
1463 flags |= DRM_MODE_FLAG_NVSYNC;
1464 } else {
1465 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1466 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1467 flags |= DRM_MODE_FLAG_PHSYNC;
1468 else
1469 flags |= DRM_MODE_FLAG_NHSYNC;
1470
1471 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1472 flags |= DRM_MODE_FLAG_PVSYNC;
1473 else
1474 flags |= DRM_MODE_FLAG_NVSYNC;
1475 }
1476
1477 pipe_config->adjusted_mode.flags |= flags;
1478
1479 pipe_config->has_dp_encoder = true;
1480
1481 intel_dp_get_m_n(crtc, pipe_config);
1482
1483 if (port == PORT_A) {
1484 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1485 pipe_config->port_clock = 162000;
1486 else
1487 pipe_config->port_clock = 270000;
1488 }
1489
1490 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1491 &pipe_config->dp_m_n);
1492
1493 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1494 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1495
1496 pipe_config->adjusted_mode.crtc_clock = dotclock;
1497
1498 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1499 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1500 /*
1501 * This is a big fat ugly hack.
1502 *
1503 * Some machines in UEFI boot mode provide us a VBT that has 18
1504 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1505 * unknown we fail to light up. Yet the same BIOS boots up with
1506 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1507 * max, not what it tells us to use.
1508 *
1509 * Note: This will still be broken if the eDP panel is not lit
1510 * up by the BIOS, and thus we can't get the mode at module
1511 * load.
1512 */
1513 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1514 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1515 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1516 }
1517 }
1518
1519 static bool is_edp_psr(struct drm_device *dev)
1520 {
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523 return dev_priv->psr.sink_support;
1524 }
1525
1526 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1527 {
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529
1530 if (!HAS_PSR(dev))
1531 return false;
1532
1533 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1534 }
1535
1536 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1537 struct edp_vsc_psr *vsc_psr)
1538 {
1539 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1540 struct drm_device *dev = dig_port->base.base.dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1543 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1544 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1545 uint32_t *data = (uint32_t *) vsc_psr;
1546 unsigned int i;
1547
1548 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1549 the video DIP being updated before program video DIP data buffer
1550 registers for DIP being updated. */
1551 I915_WRITE(ctl_reg, 0);
1552 POSTING_READ(ctl_reg);
1553
1554 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1555 if (i < sizeof(struct edp_vsc_psr))
1556 I915_WRITE(data_reg + i, *data++);
1557 else
1558 I915_WRITE(data_reg + i, 0);
1559 }
1560
1561 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1562 POSTING_READ(ctl_reg);
1563 }
1564
1565 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1566 {
1567 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569 struct edp_vsc_psr psr_vsc;
1570
1571 if (intel_dp->psr_setup_done)
1572 return;
1573
1574 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1575 memset(&psr_vsc, 0, sizeof(psr_vsc));
1576 psr_vsc.sdp_header.HB0 = 0;
1577 psr_vsc.sdp_header.HB1 = 0x7;
1578 psr_vsc.sdp_header.HB2 = 0x2;
1579 psr_vsc.sdp_header.HB3 = 0x8;
1580 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1581
1582 /* Avoid continuous PSR exit by masking memup and hpd */
1583 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1584 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1585
1586 intel_dp->psr_setup_done = true;
1587 }
1588
1589 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1590 {
1591 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1594 int precharge = 0x3;
1595 int msg_size = 5; /* Header(4) + Message(1) */
1596
1597 /* Enable PSR in sink */
1598 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1599 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1600 DP_PSR_ENABLE &
1601 ~DP_PSR_MAIN_LINK_ACTIVE);
1602 else
1603 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1604 DP_PSR_ENABLE |
1605 DP_PSR_MAIN_LINK_ACTIVE);
1606
1607 /* Setup AUX registers */
1608 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1609 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1610 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1611 DP_AUX_CH_CTL_TIME_OUT_400us |
1612 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1613 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1614 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1615 }
1616
1617 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1618 {
1619 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 uint32_t max_sleep_time = 0x1f;
1622 uint32_t idle_frames = 1;
1623 uint32_t val = 0x0;
1624 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1625
1626 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1627 val |= EDP_PSR_LINK_STANDBY;
1628 val |= EDP_PSR_TP2_TP3_TIME_0us;
1629 val |= EDP_PSR_TP1_TIME_0us;
1630 val |= EDP_PSR_SKIP_AUX_EXIT;
1631 } else
1632 val |= EDP_PSR_LINK_DISABLE;
1633
1634 I915_WRITE(EDP_PSR_CTL(dev), val |
1635 IS_BROADWELL(dev) ? 0 : link_entry_time |
1636 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1637 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1638 EDP_PSR_ENABLE);
1639 }
1640
1641 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1642 {
1643 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1644 struct drm_device *dev = dig_port->base.base.dev;
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646 struct drm_crtc *crtc = dig_port->base.base.crtc;
1647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1648 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1649 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1650
1651 dev_priv->psr.source_ok = false;
1652
1653 if (!HAS_PSR(dev)) {
1654 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1655 return false;
1656 }
1657
1658 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1659 (dig_port->port != PORT_A)) {
1660 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1661 return false;
1662 }
1663
1664 if (!i915_enable_psr) {
1665 DRM_DEBUG_KMS("PSR disable by flag\n");
1666 return false;
1667 }
1668
1669 crtc = dig_port->base.base.crtc;
1670 if (crtc == NULL) {
1671 DRM_DEBUG_KMS("crtc not active for PSR\n");
1672 return false;
1673 }
1674
1675 intel_crtc = to_intel_crtc(crtc);
1676 if (!intel_crtc_active(crtc)) {
1677 DRM_DEBUG_KMS("crtc not active for PSR\n");
1678 return false;
1679 }
1680
1681 obj = to_intel_framebuffer(crtc->fb)->obj;
1682 if (obj->tiling_mode != I915_TILING_X ||
1683 obj->fence_reg == I915_FENCE_REG_NONE) {
1684 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1685 return false;
1686 }
1687
1688 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1689 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1690 return false;
1691 }
1692
1693 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1694 S3D_ENABLE) {
1695 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1696 return false;
1697 }
1698
1699 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1700 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1701 return false;
1702 }
1703
1704 dev_priv->psr.source_ok = true;
1705 return true;
1706 }
1707
1708 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1709 {
1710 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1711
1712 if (!intel_edp_psr_match_conditions(intel_dp) ||
1713 intel_edp_is_psr_enabled(dev))
1714 return;
1715
1716 /* Setup PSR once */
1717 intel_edp_psr_setup(intel_dp);
1718
1719 /* Enable PSR on the panel */
1720 intel_edp_psr_enable_sink(intel_dp);
1721
1722 /* Enable PSR on the host */
1723 intel_edp_psr_enable_source(intel_dp);
1724 }
1725
1726 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1727 {
1728 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1729
1730 if (intel_edp_psr_match_conditions(intel_dp) &&
1731 !intel_edp_is_psr_enabled(dev))
1732 intel_edp_psr_do_enable(intel_dp);
1733 }
1734
1735 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1736 {
1737 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1738 struct drm_i915_private *dev_priv = dev->dev_private;
1739
1740 if (!intel_edp_is_psr_enabled(dev))
1741 return;
1742
1743 I915_WRITE(EDP_PSR_CTL(dev),
1744 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1745
1746 /* Wait till PSR is idle */
1747 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1748 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1749 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1750 }
1751
1752 void intel_edp_psr_update(struct drm_device *dev)
1753 {
1754 struct intel_encoder *encoder;
1755 struct intel_dp *intel_dp = NULL;
1756
1757 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1758 if (encoder->type == INTEL_OUTPUT_EDP) {
1759 intel_dp = enc_to_intel_dp(&encoder->base);
1760
1761 if (!is_edp_psr(dev))
1762 return;
1763
1764 if (!intel_edp_psr_match_conditions(intel_dp))
1765 intel_edp_psr_disable(intel_dp);
1766 else
1767 if (!intel_edp_is_psr_enabled(dev))
1768 intel_edp_psr_do_enable(intel_dp);
1769 }
1770 }
1771
1772 static void intel_disable_dp(struct intel_encoder *encoder)
1773 {
1774 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1775 enum port port = dp_to_dig_port(intel_dp)->port;
1776 struct drm_device *dev = encoder->base.dev;
1777
1778 /* Make sure the panel is off before trying to change the mode. But also
1779 * ensure that we have vdd while we switch off the panel. */
1780 ironlake_edp_backlight_off(intel_dp);
1781 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1782 ironlake_edp_panel_off(intel_dp);
1783
1784 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1785 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1786 intel_dp_link_down(intel_dp);
1787 }
1788
1789 static void intel_post_disable_dp(struct intel_encoder *encoder)
1790 {
1791 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1792 enum port port = dp_to_dig_port(intel_dp)->port;
1793 struct drm_device *dev = encoder->base.dev;
1794
1795 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1796 intel_dp_link_down(intel_dp);
1797 if (!IS_VALLEYVIEW(dev))
1798 ironlake_edp_pll_off(intel_dp);
1799 }
1800 }
1801
1802 static void intel_enable_dp(struct intel_encoder *encoder)
1803 {
1804 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1805 struct drm_device *dev = encoder->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1808
1809 if (WARN_ON(dp_reg & DP_PORT_EN))
1810 return;
1811
1812 ironlake_edp_panel_vdd_on(intel_dp);
1813 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1814 intel_dp_start_link_train(intel_dp);
1815 ironlake_edp_panel_on(intel_dp);
1816 ironlake_edp_panel_vdd_off(intel_dp, true);
1817 intel_dp_complete_link_train(intel_dp);
1818 intel_dp_stop_link_train(intel_dp);
1819 }
1820
1821 static void g4x_enable_dp(struct intel_encoder *encoder)
1822 {
1823 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1824
1825 intel_enable_dp(encoder);
1826 ironlake_edp_backlight_on(intel_dp);
1827 }
1828
1829 static void vlv_enable_dp(struct intel_encoder *encoder)
1830 {
1831 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1832
1833 ironlake_edp_backlight_on(intel_dp);
1834 }
1835
1836 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1837 {
1838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1839 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1840
1841 if (dport->port == PORT_A)
1842 ironlake_edp_pll_on(intel_dp);
1843 }
1844
1845 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1846 {
1847 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1848 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1849 struct drm_device *dev = encoder->base.dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1852 enum dpio_channel port = vlv_dport_to_channel(dport);
1853 int pipe = intel_crtc->pipe;
1854 struct edp_power_seq power_seq;
1855 u32 val;
1856
1857 mutex_lock(&dev_priv->dpio_lock);
1858
1859 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1860 val = 0;
1861 if (pipe)
1862 val |= (1<<21);
1863 else
1864 val &= ~(1<<21);
1865 val |= 0x001000c4;
1866 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1867 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1868 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1869
1870 mutex_unlock(&dev_priv->dpio_lock);
1871
1872 /* init power sequencer on this pipe and port */
1873 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1874 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1875 &power_seq);
1876
1877 intel_enable_dp(encoder);
1878
1879 vlv_wait_port_ready(dev_priv, dport);
1880 }
1881
1882 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1883 {
1884 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1885 struct drm_device *dev = encoder->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_crtc *intel_crtc =
1888 to_intel_crtc(encoder->base.crtc);
1889 enum dpio_channel port = vlv_dport_to_channel(dport);
1890 int pipe = intel_crtc->pipe;
1891
1892 /* Program Tx lane resets to default */
1893 mutex_lock(&dev_priv->dpio_lock);
1894 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1895 DPIO_PCS_TX_LANE2_RESET |
1896 DPIO_PCS_TX_LANE1_RESET);
1897 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1898 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1899 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1900 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1901 DPIO_PCS_CLK_SOFT_RESET);
1902
1903 /* Fix up inter-pair skew failure */
1904 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1905 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1906 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1907 mutex_unlock(&dev_priv->dpio_lock);
1908 }
1909
1910 /*
1911 * Native read with retry for link status and receiver capability reads for
1912 * cases where the sink may still be asleep.
1913 */
1914 static bool
1915 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1916 uint8_t *recv, int recv_bytes)
1917 {
1918 int ret, i;
1919
1920 /*
1921 * Sinks are *supposed* to come up within 1ms from an off state,
1922 * but we're also supposed to retry 3 times per the spec.
1923 */
1924 for (i = 0; i < 3; i++) {
1925 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1926 recv_bytes);
1927 if (ret == recv_bytes)
1928 return true;
1929 msleep(1);
1930 }
1931
1932 return false;
1933 }
1934
1935 /*
1936 * Fetch AUX CH registers 0x202 - 0x207 which contain
1937 * link status information
1938 */
1939 static bool
1940 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1941 {
1942 return intel_dp_aux_native_read_retry(intel_dp,
1943 DP_LANE0_1_STATUS,
1944 link_status,
1945 DP_LINK_STATUS_SIZE);
1946 }
1947
1948 /*
1949 * These are source-specific values; current Intel hardware supports
1950 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1951 */
1952
1953 static uint8_t
1954 intel_dp_voltage_max(struct intel_dp *intel_dp)
1955 {
1956 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1957 enum port port = dp_to_dig_port(intel_dp)->port;
1958
1959 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1960 return DP_TRAIN_VOLTAGE_SWING_1200;
1961 else if (IS_GEN7(dev) && port == PORT_A)
1962 return DP_TRAIN_VOLTAGE_SWING_800;
1963 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1964 return DP_TRAIN_VOLTAGE_SWING_1200;
1965 else
1966 return DP_TRAIN_VOLTAGE_SWING_800;
1967 }
1968
1969 static uint8_t
1970 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1971 {
1972 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1973 enum port port = dp_to_dig_port(intel_dp)->port;
1974
1975 if (IS_BROADWELL(dev)) {
1976 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1977 case DP_TRAIN_VOLTAGE_SWING_400:
1978 case DP_TRAIN_VOLTAGE_SWING_600:
1979 return DP_TRAIN_PRE_EMPHASIS_6;
1980 case DP_TRAIN_VOLTAGE_SWING_800:
1981 return DP_TRAIN_PRE_EMPHASIS_3_5;
1982 case DP_TRAIN_VOLTAGE_SWING_1200:
1983 default:
1984 return DP_TRAIN_PRE_EMPHASIS_0;
1985 }
1986 } else if (IS_HASWELL(dev)) {
1987 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1988 case DP_TRAIN_VOLTAGE_SWING_400:
1989 return DP_TRAIN_PRE_EMPHASIS_9_5;
1990 case DP_TRAIN_VOLTAGE_SWING_600:
1991 return DP_TRAIN_PRE_EMPHASIS_6;
1992 case DP_TRAIN_VOLTAGE_SWING_800:
1993 return DP_TRAIN_PRE_EMPHASIS_3_5;
1994 case DP_TRAIN_VOLTAGE_SWING_1200:
1995 default:
1996 return DP_TRAIN_PRE_EMPHASIS_0;
1997 }
1998 } else if (IS_VALLEYVIEW(dev)) {
1999 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2000 case DP_TRAIN_VOLTAGE_SWING_400:
2001 return DP_TRAIN_PRE_EMPHASIS_9_5;
2002 case DP_TRAIN_VOLTAGE_SWING_600:
2003 return DP_TRAIN_PRE_EMPHASIS_6;
2004 case DP_TRAIN_VOLTAGE_SWING_800:
2005 return DP_TRAIN_PRE_EMPHASIS_3_5;
2006 case DP_TRAIN_VOLTAGE_SWING_1200:
2007 default:
2008 return DP_TRAIN_PRE_EMPHASIS_0;
2009 }
2010 } else if (IS_GEN7(dev) && port == PORT_A) {
2011 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2012 case DP_TRAIN_VOLTAGE_SWING_400:
2013 return DP_TRAIN_PRE_EMPHASIS_6;
2014 case DP_TRAIN_VOLTAGE_SWING_600:
2015 case DP_TRAIN_VOLTAGE_SWING_800:
2016 return DP_TRAIN_PRE_EMPHASIS_3_5;
2017 default:
2018 return DP_TRAIN_PRE_EMPHASIS_0;
2019 }
2020 } else {
2021 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2022 case DP_TRAIN_VOLTAGE_SWING_400:
2023 return DP_TRAIN_PRE_EMPHASIS_6;
2024 case DP_TRAIN_VOLTAGE_SWING_600:
2025 return DP_TRAIN_PRE_EMPHASIS_6;
2026 case DP_TRAIN_VOLTAGE_SWING_800:
2027 return DP_TRAIN_PRE_EMPHASIS_3_5;
2028 case DP_TRAIN_VOLTAGE_SWING_1200:
2029 default:
2030 return DP_TRAIN_PRE_EMPHASIS_0;
2031 }
2032 }
2033 }
2034
2035 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2036 {
2037 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2040 struct intel_crtc *intel_crtc =
2041 to_intel_crtc(dport->base.base.crtc);
2042 unsigned long demph_reg_value, preemph_reg_value,
2043 uniqtranscale_reg_value;
2044 uint8_t train_set = intel_dp->train_set[0];
2045 enum dpio_channel port = vlv_dport_to_channel(dport);
2046 int pipe = intel_crtc->pipe;
2047
2048 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2049 case DP_TRAIN_PRE_EMPHASIS_0:
2050 preemph_reg_value = 0x0004000;
2051 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2052 case DP_TRAIN_VOLTAGE_SWING_400:
2053 demph_reg_value = 0x2B405555;
2054 uniqtranscale_reg_value = 0x552AB83A;
2055 break;
2056 case DP_TRAIN_VOLTAGE_SWING_600:
2057 demph_reg_value = 0x2B404040;
2058 uniqtranscale_reg_value = 0x5548B83A;
2059 break;
2060 case DP_TRAIN_VOLTAGE_SWING_800:
2061 demph_reg_value = 0x2B245555;
2062 uniqtranscale_reg_value = 0x5560B83A;
2063 break;
2064 case DP_TRAIN_VOLTAGE_SWING_1200:
2065 demph_reg_value = 0x2B405555;
2066 uniqtranscale_reg_value = 0x5598DA3A;
2067 break;
2068 default:
2069 return 0;
2070 }
2071 break;
2072 case DP_TRAIN_PRE_EMPHASIS_3_5:
2073 preemph_reg_value = 0x0002000;
2074 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2075 case DP_TRAIN_VOLTAGE_SWING_400:
2076 demph_reg_value = 0x2B404040;
2077 uniqtranscale_reg_value = 0x5552B83A;
2078 break;
2079 case DP_TRAIN_VOLTAGE_SWING_600:
2080 demph_reg_value = 0x2B404848;
2081 uniqtranscale_reg_value = 0x5580B83A;
2082 break;
2083 case DP_TRAIN_VOLTAGE_SWING_800:
2084 demph_reg_value = 0x2B404040;
2085 uniqtranscale_reg_value = 0x55ADDA3A;
2086 break;
2087 default:
2088 return 0;
2089 }
2090 break;
2091 case DP_TRAIN_PRE_EMPHASIS_6:
2092 preemph_reg_value = 0x0000000;
2093 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2094 case DP_TRAIN_VOLTAGE_SWING_400:
2095 demph_reg_value = 0x2B305555;
2096 uniqtranscale_reg_value = 0x5570B83A;
2097 break;
2098 case DP_TRAIN_VOLTAGE_SWING_600:
2099 demph_reg_value = 0x2B2B4040;
2100 uniqtranscale_reg_value = 0x55ADDA3A;
2101 break;
2102 default:
2103 return 0;
2104 }
2105 break;
2106 case DP_TRAIN_PRE_EMPHASIS_9_5:
2107 preemph_reg_value = 0x0006000;
2108 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2109 case DP_TRAIN_VOLTAGE_SWING_400:
2110 demph_reg_value = 0x1B405555;
2111 uniqtranscale_reg_value = 0x55ADDA3A;
2112 break;
2113 default:
2114 return 0;
2115 }
2116 break;
2117 default:
2118 return 0;
2119 }
2120
2121 mutex_lock(&dev_priv->dpio_lock);
2122 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2123 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2124 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2125 uniqtranscale_reg_value);
2126 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2127 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2128 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2129 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2130 mutex_unlock(&dev_priv->dpio_lock);
2131
2132 return 0;
2133 }
2134
2135 static void
2136 intel_get_adjust_train(struct intel_dp *intel_dp,
2137 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2138 {
2139 uint8_t v = 0;
2140 uint8_t p = 0;
2141 int lane;
2142 uint8_t voltage_max;
2143 uint8_t preemph_max;
2144
2145 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2146 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2147 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2148
2149 if (this_v > v)
2150 v = this_v;
2151 if (this_p > p)
2152 p = this_p;
2153 }
2154
2155 voltage_max = intel_dp_voltage_max(intel_dp);
2156 if (v >= voltage_max)
2157 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2158
2159 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2160 if (p >= preemph_max)
2161 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2162
2163 for (lane = 0; lane < 4; lane++)
2164 intel_dp->train_set[lane] = v | p;
2165 }
2166
2167 static uint32_t
2168 intel_gen4_signal_levels(uint8_t train_set)
2169 {
2170 uint32_t signal_levels = 0;
2171
2172 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2173 case DP_TRAIN_VOLTAGE_SWING_400:
2174 default:
2175 signal_levels |= DP_VOLTAGE_0_4;
2176 break;
2177 case DP_TRAIN_VOLTAGE_SWING_600:
2178 signal_levels |= DP_VOLTAGE_0_6;
2179 break;
2180 case DP_TRAIN_VOLTAGE_SWING_800:
2181 signal_levels |= DP_VOLTAGE_0_8;
2182 break;
2183 case DP_TRAIN_VOLTAGE_SWING_1200:
2184 signal_levels |= DP_VOLTAGE_1_2;
2185 break;
2186 }
2187 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2188 case DP_TRAIN_PRE_EMPHASIS_0:
2189 default:
2190 signal_levels |= DP_PRE_EMPHASIS_0;
2191 break;
2192 case DP_TRAIN_PRE_EMPHASIS_3_5:
2193 signal_levels |= DP_PRE_EMPHASIS_3_5;
2194 break;
2195 case DP_TRAIN_PRE_EMPHASIS_6:
2196 signal_levels |= DP_PRE_EMPHASIS_6;
2197 break;
2198 case DP_TRAIN_PRE_EMPHASIS_9_5:
2199 signal_levels |= DP_PRE_EMPHASIS_9_5;
2200 break;
2201 }
2202 return signal_levels;
2203 }
2204
2205 /* Gen6's DP voltage swing and pre-emphasis control */
2206 static uint32_t
2207 intel_gen6_edp_signal_levels(uint8_t train_set)
2208 {
2209 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2210 DP_TRAIN_PRE_EMPHASIS_MASK);
2211 switch (signal_levels) {
2212 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2213 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2214 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2215 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2216 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2217 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2218 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2219 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2220 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2221 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2222 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2223 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2224 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2225 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2226 default:
2227 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2228 "0x%x\n", signal_levels);
2229 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2230 }
2231 }
2232
2233 /* Gen7's DP voltage swing and pre-emphasis control */
2234 static uint32_t
2235 intel_gen7_edp_signal_levels(uint8_t train_set)
2236 {
2237 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2238 DP_TRAIN_PRE_EMPHASIS_MASK);
2239 switch (signal_levels) {
2240 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2241 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2242 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2243 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2244 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2245 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2246
2247 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2248 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2249 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2250 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2251
2252 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2253 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2254 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2255 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2256
2257 default:
2258 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2259 "0x%x\n", signal_levels);
2260 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2261 }
2262 }
2263
2264 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2265 static uint32_t
2266 intel_hsw_signal_levels(uint8_t train_set)
2267 {
2268 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2269 DP_TRAIN_PRE_EMPHASIS_MASK);
2270 switch (signal_levels) {
2271 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2272 return DDI_BUF_EMP_400MV_0DB_HSW;
2273 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2274 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2275 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2276 return DDI_BUF_EMP_400MV_6DB_HSW;
2277 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2278 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2279
2280 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2281 return DDI_BUF_EMP_600MV_0DB_HSW;
2282 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2283 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2284 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2285 return DDI_BUF_EMP_600MV_6DB_HSW;
2286
2287 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2288 return DDI_BUF_EMP_800MV_0DB_HSW;
2289 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2290 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2291 default:
2292 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2293 "0x%x\n", signal_levels);
2294 return DDI_BUF_EMP_400MV_0DB_HSW;
2295 }
2296 }
2297
2298 static uint32_t
2299 intel_bdw_signal_levels(uint8_t train_set)
2300 {
2301 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2302 DP_TRAIN_PRE_EMPHASIS_MASK);
2303 switch (signal_levels) {
2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2305 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2306 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2307 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2308 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2309 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2310
2311 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2312 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2313 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2315 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2316 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2317
2318 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2319 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2320 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2321 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2322
2323 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2324 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2325
2326 default:
2327 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2328 "0x%x\n", signal_levels);
2329 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2330 }
2331 }
2332
2333 /* Properly updates "DP" with the correct signal levels. */
2334 static void
2335 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2336 {
2337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2338 enum port port = intel_dig_port->port;
2339 struct drm_device *dev = intel_dig_port->base.base.dev;
2340 uint32_t signal_levels, mask;
2341 uint8_t train_set = intel_dp->train_set[0];
2342
2343 if (IS_BROADWELL(dev)) {
2344 signal_levels = intel_bdw_signal_levels(train_set);
2345 mask = DDI_BUF_EMP_MASK;
2346 } else if (IS_HASWELL(dev)) {
2347 signal_levels = intel_hsw_signal_levels(train_set);
2348 mask = DDI_BUF_EMP_MASK;
2349 } else if (IS_VALLEYVIEW(dev)) {
2350 signal_levels = intel_vlv_signal_levels(intel_dp);
2351 mask = 0;
2352 } else if (IS_GEN7(dev) && port == PORT_A) {
2353 signal_levels = intel_gen7_edp_signal_levels(train_set);
2354 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2355 } else if (IS_GEN6(dev) && port == PORT_A) {
2356 signal_levels = intel_gen6_edp_signal_levels(train_set);
2357 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2358 } else {
2359 signal_levels = intel_gen4_signal_levels(train_set);
2360 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2361 }
2362
2363 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2364
2365 *DP = (*DP & ~mask) | signal_levels;
2366 }
2367
2368 static bool
2369 intel_dp_set_link_train(struct intel_dp *intel_dp,
2370 uint32_t *DP,
2371 uint8_t dp_train_pat)
2372 {
2373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2374 struct drm_device *dev = intel_dig_port->base.base.dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 enum port port = intel_dig_port->port;
2377 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2378 int ret, len;
2379
2380 if (HAS_DDI(dev)) {
2381 uint32_t temp = I915_READ(DP_TP_CTL(port));
2382
2383 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2384 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2385 else
2386 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2387
2388 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2389 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2390 case DP_TRAINING_PATTERN_DISABLE:
2391 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2392
2393 break;
2394 case DP_TRAINING_PATTERN_1:
2395 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2396 break;
2397 case DP_TRAINING_PATTERN_2:
2398 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2399 break;
2400 case DP_TRAINING_PATTERN_3:
2401 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2402 break;
2403 }
2404 I915_WRITE(DP_TP_CTL(port), temp);
2405
2406 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2407 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2408
2409 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2410 case DP_TRAINING_PATTERN_DISABLE:
2411 *DP |= DP_LINK_TRAIN_OFF_CPT;
2412 break;
2413 case DP_TRAINING_PATTERN_1:
2414 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2415 break;
2416 case DP_TRAINING_PATTERN_2:
2417 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2418 break;
2419 case DP_TRAINING_PATTERN_3:
2420 DRM_ERROR("DP training pattern 3 not supported\n");
2421 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2422 break;
2423 }
2424
2425 } else {
2426 *DP &= ~DP_LINK_TRAIN_MASK;
2427
2428 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2429 case DP_TRAINING_PATTERN_DISABLE:
2430 *DP |= DP_LINK_TRAIN_OFF;
2431 break;
2432 case DP_TRAINING_PATTERN_1:
2433 *DP |= DP_LINK_TRAIN_PAT_1;
2434 break;
2435 case DP_TRAINING_PATTERN_2:
2436 *DP |= DP_LINK_TRAIN_PAT_2;
2437 break;
2438 case DP_TRAINING_PATTERN_3:
2439 DRM_ERROR("DP training pattern 3 not supported\n");
2440 *DP |= DP_LINK_TRAIN_PAT_2;
2441 break;
2442 }
2443 }
2444
2445 I915_WRITE(intel_dp->output_reg, *DP);
2446 POSTING_READ(intel_dp->output_reg);
2447
2448 buf[0] = dp_train_pat;
2449 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2450 DP_TRAINING_PATTERN_DISABLE) {
2451 /* don't write DP_TRAINING_LANEx_SET on disable */
2452 len = 1;
2453 } else {
2454 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2455 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2456 len = intel_dp->lane_count + 1;
2457 }
2458
2459 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2460 buf, len);
2461
2462 return ret == len;
2463 }
2464
2465 static bool
2466 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2467 uint8_t dp_train_pat)
2468 {
2469 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2470 intel_dp_set_signal_levels(intel_dp, DP);
2471 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2472 }
2473
2474 static bool
2475 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2476 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2477 {
2478 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2479 struct drm_device *dev = intel_dig_port->base.base.dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 int ret;
2482
2483 intel_get_adjust_train(intel_dp, link_status);
2484 intel_dp_set_signal_levels(intel_dp, DP);
2485
2486 I915_WRITE(intel_dp->output_reg, *DP);
2487 POSTING_READ(intel_dp->output_reg);
2488
2489 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2490 intel_dp->train_set,
2491 intel_dp->lane_count);
2492
2493 return ret == intel_dp->lane_count;
2494 }
2495
2496 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2497 {
2498 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2499 struct drm_device *dev = intel_dig_port->base.base.dev;
2500 struct drm_i915_private *dev_priv = dev->dev_private;
2501 enum port port = intel_dig_port->port;
2502 uint32_t val;
2503
2504 if (!HAS_DDI(dev))
2505 return;
2506
2507 val = I915_READ(DP_TP_CTL(port));
2508 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2509 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2510 I915_WRITE(DP_TP_CTL(port), val);
2511
2512 /*
2513 * On PORT_A we can have only eDP in SST mode. There the only reason
2514 * we need to set idle transmission mode is to work around a HW issue
2515 * where we enable the pipe while not in idle link-training mode.
2516 * In this case there is requirement to wait for a minimum number of
2517 * idle patterns to be sent.
2518 */
2519 if (port == PORT_A)
2520 return;
2521
2522 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2523 1))
2524 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2525 }
2526
2527 /* Enable corresponding port and start training pattern 1 */
2528 void
2529 intel_dp_start_link_train(struct intel_dp *intel_dp)
2530 {
2531 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2532 struct drm_device *dev = encoder->dev;
2533 int i;
2534 uint8_t voltage;
2535 int voltage_tries, loop_tries;
2536 uint32_t DP = intel_dp->DP;
2537 uint8_t link_config[2];
2538
2539 if (HAS_DDI(dev))
2540 intel_ddi_prepare_link_retrain(encoder);
2541
2542 /* Write the link configuration data */
2543 link_config[0] = intel_dp->link_bw;
2544 link_config[1] = intel_dp->lane_count;
2545 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2546 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2547 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2548
2549 link_config[0] = 0;
2550 link_config[1] = DP_SET_ANSI_8B10B;
2551 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2552
2553 DP |= DP_PORT_EN;
2554
2555 /* clock recovery */
2556 if (!intel_dp_reset_link_train(intel_dp, &DP,
2557 DP_TRAINING_PATTERN_1 |
2558 DP_LINK_SCRAMBLING_DISABLE)) {
2559 DRM_ERROR("failed to enable link training\n");
2560 return;
2561 }
2562
2563 voltage = 0xff;
2564 voltage_tries = 0;
2565 loop_tries = 0;
2566 for (;;) {
2567 uint8_t link_status[DP_LINK_STATUS_SIZE];
2568
2569 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2570 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2571 DRM_ERROR("failed to get link status\n");
2572 break;
2573 }
2574
2575 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2576 DRM_DEBUG_KMS("clock recovery OK\n");
2577 break;
2578 }
2579
2580 /* Check to see if we've tried the max voltage */
2581 for (i = 0; i < intel_dp->lane_count; i++)
2582 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2583 break;
2584 if (i == intel_dp->lane_count) {
2585 ++loop_tries;
2586 if (loop_tries == 5) {
2587 DRM_ERROR("too many full retries, give up\n");
2588 break;
2589 }
2590 intel_dp_reset_link_train(intel_dp, &DP,
2591 DP_TRAINING_PATTERN_1 |
2592 DP_LINK_SCRAMBLING_DISABLE);
2593 voltage_tries = 0;
2594 continue;
2595 }
2596
2597 /* Check to see if we've tried the same voltage 5 times */
2598 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2599 ++voltage_tries;
2600 if (voltage_tries == 5) {
2601 DRM_ERROR("too many voltage retries, give up\n");
2602 break;
2603 }
2604 } else
2605 voltage_tries = 0;
2606 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2607
2608 /* Update training set as requested by target */
2609 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2610 DRM_ERROR("failed to update link training\n");
2611 break;
2612 }
2613 }
2614
2615 intel_dp->DP = DP;
2616 }
2617
2618 void
2619 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2620 {
2621 bool channel_eq = false;
2622 int tries, cr_tries;
2623 uint32_t DP = intel_dp->DP;
2624
2625 /* channel equalization */
2626 if (!intel_dp_set_link_train(intel_dp, &DP,
2627 DP_TRAINING_PATTERN_2 |
2628 DP_LINK_SCRAMBLING_DISABLE)) {
2629 DRM_ERROR("failed to start channel equalization\n");
2630 return;
2631 }
2632
2633 tries = 0;
2634 cr_tries = 0;
2635 channel_eq = false;
2636 for (;;) {
2637 uint8_t link_status[DP_LINK_STATUS_SIZE];
2638
2639 if (cr_tries > 5) {
2640 DRM_ERROR("failed to train DP, aborting\n");
2641 break;
2642 }
2643
2644 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2645 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2646 DRM_ERROR("failed to get link status\n");
2647 break;
2648 }
2649
2650 /* Make sure clock is still ok */
2651 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2652 intel_dp_start_link_train(intel_dp);
2653 intel_dp_set_link_train(intel_dp, &DP,
2654 DP_TRAINING_PATTERN_2 |
2655 DP_LINK_SCRAMBLING_DISABLE);
2656 cr_tries++;
2657 continue;
2658 }
2659
2660 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2661 channel_eq = true;
2662 break;
2663 }
2664
2665 /* Try 5 times, then try clock recovery if that fails */
2666 if (tries > 5) {
2667 intel_dp_link_down(intel_dp);
2668 intel_dp_start_link_train(intel_dp);
2669 intel_dp_set_link_train(intel_dp, &DP,
2670 DP_TRAINING_PATTERN_2 |
2671 DP_LINK_SCRAMBLING_DISABLE);
2672 tries = 0;
2673 cr_tries++;
2674 continue;
2675 }
2676
2677 /* Update training set as requested by target */
2678 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2679 DRM_ERROR("failed to update link training\n");
2680 break;
2681 }
2682 ++tries;
2683 }
2684
2685 intel_dp_set_idle_link_train(intel_dp);
2686
2687 intel_dp->DP = DP;
2688
2689 if (channel_eq)
2690 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2691
2692 }
2693
2694 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2695 {
2696 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2697 DP_TRAINING_PATTERN_DISABLE);
2698 }
2699
2700 static void
2701 intel_dp_link_down(struct intel_dp *intel_dp)
2702 {
2703 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2704 enum port port = intel_dig_port->port;
2705 struct drm_device *dev = intel_dig_port->base.base.dev;
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 struct intel_crtc *intel_crtc =
2708 to_intel_crtc(intel_dig_port->base.base.crtc);
2709 uint32_t DP = intel_dp->DP;
2710
2711 /*
2712 * DDI code has a strict mode set sequence and we should try to respect
2713 * it, otherwise we might hang the machine in many different ways. So we
2714 * really should be disabling the port only on a complete crtc_disable
2715 * sequence. This function is just called under two conditions on DDI
2716 * code:
2717 * - Link train failed while doing crtc_enable, and on this case we
2718 * really should respect the mode set sequence and wait for a
2719 * crtc_disable.
2720 * - Someone turned the monitor off and intel_dp_check_link_status
2721 * called us. We don't need to disable the whole port on this case, so
2722 * when someone turns the monitor on again,
2723 * intel_ddi_prepare_link_retrain will take care of redoing the link
2724 * train.
2725 */
2726 if (HAS_DDI(dev))
2727 return;
2728
2729 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2730 return;
2731
2732 DRM_DEBUG_KMS("\n");
2733
2734 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2735 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2736 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2737 } else {
2738 DP &= ~DP_LINK_TRAIN_MASK;
2739 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2740 }
2741 POSTING_READ(intel_dp->output_reg);
2742
2743 /* We don't really know why we're doing this */
2744 intel_wait_for_vblank(dev, intel_crtc->pipe);
2745
2746 if (HAS_PCH_IBX(dev) &&
2747 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2748 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2749
2750 /* Hardware workaround: leaving our transcoder select
2751 * set to transcoder B while it's off will prevent the
2752 * corresponding HDMI output on transcoder A.
2753 *
2754 * Combine this with another hardware workaround:
2755 * transcoder select bit can only be cleared while the
2756 * port is enabled.
2757 */
2758 DP &= ~DP_PIPEB_SELECT;
2759 I915_WRITE(intel_dp->output_reg, DP);
2760
2761 /* Changes to enable or select take place the vblank
2762 * after being written.
2763 */
2764 if (WARN_ON(crtc == NULL)) {
2765 /* We should never try to disable a port without a crtc
2766 * attached. For paranoia keep the code around for a
2767 * bit. */
2768 POSTING_READ(intel_dp->output_reg);
2769 msleep(50);
2770 } else
2771 intel_wait_for_vblank(dev, intel_crtc->pipe);
2772 }
2773
2774 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2775 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2776 POSTING_READ(intel_dp->output_reg);
2777 msleep(intel_dp->panel_power_down_delay);
2778 }
2779
2780 static bool
2781 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2782 {
2783 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2784 struct drm_device *dev = dig_port->base.base.dev;
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786
2787 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2788
2789 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2790 sizeof(intel_dp->dpcd)) == 0)
2791 return false; /* aux transfer failed */
2792
2793 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2794 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2795 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2796
2797 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2798 return false; /* DPCD not present */
2799
2800 /* Check if the panel supports PSR */
2801 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2802 if (is_edp(intel_dp)) {
2803 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2804 intel_dp->psr_dpcd,
2805 sizeof(intel_dp->psr_dpcd));
2806 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2807 dev_priv->psr.sink_support = true;
2808 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2809 }
2810 }
2811
2812 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2813 DP_DWN_STRM_PORT_PRESENT))
2814 return true; /* native DP sink */
2815
2816 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2817 return true; /* no per-port downstream info */
2818
2819 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2820 intel_dp->downstream_ports,
2821 DP_MAX_DOWNSTREAM_PORTS) == 0)
2822 return false; /* downstream port status fetch failed */
2823
2824 return true;
2825 }
2826
2827 static void
2828 intel_dp_probe_oui(struct intel_dp *intel_dp)
2829 {
2830 u8 buf[3];
2831
2832 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2833 return;
2834
2835 ironlake_edp_panel_vdd_on(intel_dp);
2836
2837 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2838 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2839 buf[0], buf[1], buf[2]);
2840
2841 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2842 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2843 buf[0], buf[1], buf[2]);
2844
2845 ironlake_edp_panel_vdd_off(intel_dp, false);
2846 }
2847
2848 static bool
2849 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2850 {
2851 int ret;
2852
2853 ret = intel_dp_aux_native_read_retry(intel_dp,
2854 DP_DEVICE_SERVICE_IRQ_VECTOR,
2855 sink_irq_vector, 1);
2856 if (!ret)
2857 return false;
2858
2859 return true;
2860 }
2861
2862 static void
2863 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2864 {
2865 /* NAK by default */
2866 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2867 }
2868
2869 /*
2870 * According to DP spec
2871 * 5.1.2:
2872 * 1. Read DPCD
2873 * 2. Configure link according to Receiver Capabilities
2874 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2875 * 4. Check link status on receipt of hot-plug interrupt
2876 */
2877
2878 void
2879 intel_dp_check_link_status(struct intel_dp *intel_dp)
2880 {
2881 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2882 u8 sink_irq_vector;
2883 u8 link_status[DP_LINK_STATUS_SIZE];
2884
2885 if (!intel_encoder->connectors_active)
2886 return;
2887
2888 if (WARN_ON(!intel_encoder->base.crtc))
2889 return;
2890
2891 /* Try to read receiver status if the link appears to be up */
2892 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2893 return;
2894 }
2895
2896 /* Now read the DPCD to see if it's actually running */
2897 if (!intel_dp_get_dpcd(intel_dp)) {
2898 return;
2899 }
2900
2901 /* Try to read the source of the interrupt */
2902 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2903 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2904 /* Clear interrupt source */
2905 intel_dp_aux_native_write_1(intel_dp,
2906 DP_DEVICE_SERVICE_IRQ_VECTOR,
2907 sink_irq_vector);
2908
2909 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2910 intel_dp_handle_test_request(intel_dp);
2911 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2912 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2913 }
2914
2915 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2916 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2917 drm_get_encoder_name(&intel_encoder->base));
2918 intel_dp_start_link_train(intel_dp);
2919 intel_dp_complete_link_train(intel_dp);
2920 intel_dp_stop_link_train(intel_dp);
2921 }
2922 }
2923
2924 /* XXX this is probably wrong for multiple downstream ports */
2925 static enum drm_connector_status
2926 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2927 {
2928 uint8_t *dpcd = intel_dp->dpcd;
2929 uint8_t type;
2930
2931 if (!intel_dp_get_dpcd(intel_dp))
2932 return connector_status_disconnected;
2933
2934 /* if there's no downstream port, we're done */
2935 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2936 return connector_status_connected;
2937
2938 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2939 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2940 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2941 uint8_t reg;
2942 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2943 &reg, 1))
2944 return connector_status_unknown;
2945 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2946 : connector_status_disconnected;
2947 }
2948
2949 /* If no HPD, poke DDC gently */
2950 if (drm_probe_ddc(&intel_dp->adapter))
2951 return connector_status_connected;
2952
2953 /* Well we tried, say unknown for unreliable port types */
2954 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2955 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2956 if (type == DP_DS_PORT_TYPE_VGA ||
2957 type == DP_DS_PORT_TYPE_NON_EDID)
2958 return connector_status_unknown;
2959 } else {
2960 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2961 DP_DWN_STRM_PORT_TYPE_MASK;
2962 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2963 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2964 return connector_status_unknown;
2965 }
2966
2967 /* Anything else is out of spec, warn and ignore */
2968 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2969 return connector_status_disconnected;
2970 }
2971
2972 static enum drm_connector_status
2973 ironlake_dp_detect(struct intel_dp *intel_dp)
2974 {
2975 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2978 enum drm_connector_status status;
2979
2980 /* Can't disconnect eDP, but you can close the lid... */
2981 if (is_edp(intel_dp)) {
2982 status = intel_panel_detect(dev);
2983 if (status == connector_status_unknown)
2984 status = connector_status_connected;
2985 return status;
2986 }
2987
2988 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2989 return connector_status_disconnected;
2990
2991 return intel_dp_detect_dpcd(intel_dp);
2992 }
2993
2994 static enum drm_connector_status
2995 g4x_dp_detect(struct intel_dp *intel_dp)
2996 {
2997 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2998 struct drm_i915_private *dev_priv = dev->dev_private;
2999 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3000 uint32_t bit;
3001
3002 /* Can't disconnect eDP, but you can close the lid... */
3003 if (is_edp(intel_dp)) {
3004 enum drm_connector_status status;
3005
3006 status = intel_panel_detect(dev);
3007 if (status == connector_status_unknown)
3008 status = connector_status_connected;
3009 return status;
3010 }
3011
3012 switch (intel_dig_port->port) {
3013 case PORT_B:
3014 bit = PORTB_HOTPLUG_LIVE_STATUS;
3015 break;
3016 case PORT_C:
3017 bit = PORTC_HOTPLUG_LIVE_STATUS;
3018 break;
3019 case PORT_D:
3020 bit = PORTD_HOTPLUG_LIVE_STATUS;
3021 break;
3022 default:
3023 return connector_status_unknown;
3024 }
3025
3026 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3027 return connector_status_disconnected;
3028
3029 return intel_dp_detect_dpcd(intel_dp);
3030 }
3031
3032 static struct edid *
3033 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3034 {
3035 struct intel_connector *intel_connector = to_intel_connector(connector);
3036
3037 /* use cached edid if we have one */
3038 if (intel_connector->edid) {
3039 /* invalid edid */
3040 if (IS_ERR(intel_connector->edid))
3041 return NULL;
3042
3043 return drm_edid_duplicate(intel_connector->edid);
3044 }
3045
3046 return drm_get_edid(connector, adapter);
3047 }
3048
3049 static int
3050 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3051 {
3052 struct intel_connector *intel_connector = to_intel_connector(connector);
3053
3054 /* use cached edid if we have one */
3055 if (intel_connector->edid) {
3056 /* invalid edid */
3057 if (IS_ERR(intel_connector->edid))
3058 return 0;
3059
3060 return intel_connector_update_modes(connector,
3061 intel_connector->edid);
3062 }
3063
3064 return intel_ddc_get_modes(connector, adapter);
3065 }
3066
3067 static enum drm_connector_status
3068 intel_dp_detect(struct drm_connector *connector, bool force)
3069 {
3070 struct intel_dp *intel_dp = intel_attached_dp(connector);
3071 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3072 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3073 struct drm_device *dev = connector->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 enum drm_connector_status status;
3076 struct edid *edid = NULL;
3077
3078 intel_runtime_pm_get(dev_priv);
3079
3080 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3081 connector->base.id, drm_get_connector_name(connector));
3082
3083 intel_dp->has_audio = false;
3084
3085 if (HAS_PCH_SPLIT(dev))
3086 status = ironlake_dp_detect(intel_dp);
3087 else
3088 status = g4x_dp_detect(intel_dp);
3089
3090 if (status != connector_status_connected)
3091 goto out;
3092
3093 intel_dp_probe_oui(intel_dp);
3094
3095 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3096 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3097 } else {
3098 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3099 if (edid) {
3100 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3101 kfree(edid);
3102 }
3103 }
3104
3105 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3106 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3107 status = connector_status_connected;
3108
3109 out:
3110 intel_runtime_pm_put(dev_priv);
3111 return status;
3112 }
3113
3114 static int intel_dp_get_modes(struct drm_connector *connector)
3115 {
3116 struct intel_dp *intel_dp = intel_attached_dp(connector);
3117 struct intel_connector *intel_connector = to_intel_connector(connector);
3118 struct drm_device *dev = connector->dev;
3119 int ret;
3120
3121 /* We should parse the EDID data and find out if it has an audio sink
3122 */
3123
3124 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3125 if (ret)
3126 return ret;
3127
3128 /* if eDP has no EDID, fall back to fixed mode */
3129 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3130 struct drm_display_mode *mode;
3131 mode = drm_mode_duplicate(dev,
3132 intel_connector->panel.fixed_mode);
3133 if (mode) {
3134 drm_mode_probed_add(connector, mode);
3135 return 1;
3136 }
3137 }
3138 return 0;
3139 }
3140
3141 static bool
3142 intel_dp_detect_audio(struct drm_connector *connector)
3143 {
3144 struct intel_dp *intel_dp = intel_attached_dp(connector);
3145 struct edid *edid;
3146 bool has_audio = false;
3147
3148 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3149 if (edid) {
3150 has_audio = drm_detect_monitor_audio(edid);
3151 kfree(edid);
3152 }
3153
3154 return has_audio;
3155 }
3156
3157 static int
3158 intel_dp_set_property(struct drm_connector *connector,
3159 struct drm_property *property,
3160 uint64_t val)
3161 {
3162 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3163 struct intel_connector *intel_connector = to_intel_connector(connector);
3164 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3165 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3166 int ret;
3167
3168 ret = drm_object_property_set_value(&connector->base, property, val);
3169 if (ret)
3170 return ret;
3171
3172 if (property == dev_priv->force_audio_property) {
3173 int i = val;
3174 bool has_audio;
3175
3176 if (i == intel_dp->force_audio)
3177 return 0;
3178
3179 intel_dp->force_audio = i;
3180
3181 if (i == HDMI_AUDIO_AUTO)
3182 has_audio = intel_dp_detect_audio(connector);
3183 else
3184 has_audio = (i == HDMI_AUDIO_ON);
3185
3186 if (has_audio == intel_dp->has_audio)
3187 return 0;
3188
3189 intel_dp->has_audio = has_audio;
3190 goto done;
3191 }
3192
3193 if (property == dev_priv->broadcast_rgb_property) {
3194 bool old_auto = intel_dp->color_range_auto;
3195 uint32_t old_range = intel_dp->color_range;
3196
3197 switch (val) {
3198 case INTEL_BROADCAST_RGB_AUTO:
3199 intel_dp->color_range_auto = true;
3200 break;
3201 case INTEL_BROADCAST_RGB_FULL:
3202 intel_dp->color_range_auto = false;
3203 intel_dp->color_range = 0;
3204 break;
3205 case INTEL_BROADCAST_RGB_LIMITED:
3206 intel_dp->color_range_auto = false;
3207 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3208 break;
3209 default:
3210 return -EINVAL;
3211 }
3212
3213 if (old_auto == intel_dp->color_range_auto &&
3214 old_range == intel_dp->color_range)
3215 return 0;
3216
3217 goto done;
3218 }
3219
3220 if (is_edp(intel_dp) &&
3221 property == connector->dev->mode_config.scaling_mode_property) {
3222 if (val == DRM_MODE_SCALE_NONE) {
3223 DRM_DEBUG_KMS("no scaling not supported\n");
3224 return -EINVAL;
3225 }
3226
3227 if (intel_connector->panel.fitting_mode == val) {
3228 /* the eDP scaling property is not changed */
3229 return 0;
3230 }
3231 intel_connector->panel.fitting_mode = val;
3232
3233 goto done;
3234 }
3235
3236 return -EINVAL;
3237
3238 done:
3239 if (intel_encoder->base.crtc)
3240 intel_crtc_restore_mode(intel_encoder->base.crtc);
3241
3242 return 0;
3243 }
3244
3245 static void
3246 intel_dp_connector_destroy(struct drm_connector *connector)
3247 {
3248 struct intel_connector *intel_connector = to_intel_connector(connector);
3249
3250 if (!IS_ERR_OR_NULL(intel_connector->edid))
3251 kfree(intel_connector->edid);
3252
3253 /* Can't call is_edp() since the encoder may have been destroyed
3254 * already. */
3255 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3256 intel_panel_fini(&intel_connector->panel);
3257
3258 drm_connector_cleanup(connector);
3259 kfree(connector);
3260 }
3261
3262 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3263 {
3264 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3265 struct intel_dp *intel_dp = &intel_dig_port->dp;
3266 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3267
3268 i2c_del_adapter(&intel_dp->adapter);
3269 drm_encoder_cleanup(encoder);
3270 if (is_edp(intel_dp)) {
3271 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3272 mutex_lock(&dev->mode_config.mutex);
3273 ironlake_panel_vdd_off_sync(intel_dp);
3274 mutex_unlock(&dev->mode_config.mutex);
3275 }
3276 kfree(intel_dig_port);
3277 }
3278
3279 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3280 .dpms = intel_connector_dpms,
3281 .detect = intel_dp_detect,
3282 .fill_modes = drm_helper_probe_single_connector_modes,
3283 .set_property = intel_dp_set_property,
3284 .destroy = intel_dp_connector_destroy,
3285 };
3286
3287 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3288 .get_modes = intel_dp_get_modes,
3289 .mode_valid = intel_dp_mode_valid,
3290 .best_encoder = intel_best_encoder,
3291 };
3292
3293 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3294 .destroy = intel_dp_encoder_destroy,
3295 };
3296
3297 static void
3298 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3299 {
3300 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3301
3302 intel_dp_check_link_status(intel_dp);
3303 }
3304
3305 /* Return which DP Port should be selected for Transcoder DP control */
3306 int
3307 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3308 {
3309 struct drm_device *dev = crtc->dev;
3310 struct intel_encoder *intel_encoder;
3311 struct intel_dp *intel_dp;
3312
3313 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3314 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3315
3316 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3317 intel_encoder->type == INTEL_OUTPUT_EDP)
3318 return intel_dp->output_reg;
3319 }
3320
3321 return -1;
3322 }
3323
3324 /* check the VBT to see whether the eDP is on DP-D port */
3325 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3326 {
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 union child_device_config *p_child;
3329 int i;
3330 static const short port_mapping[] = {
3331 [PORT_B] = PORT_IDPB,
3332 [PORT_C] = PORT_IDPC,
3333 [PORT_D] = PORT_IDPD,
3334 };
3335
3336 if (port == PORT_A)
3337 return true;
3338
3339 if (!dev_priv->vbt.child_dev_num)
3340 return false;
3341
3342 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3343 p_child = dev_priv->vbt.child_dev + i;
3344
3345 if (p_child->common.dvo_port == port_mapping[port] &&
3346 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3347 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3348 return true;
3349 }
3350 return false;
3351 }
3352
3353 static void
3354 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3355 {
3356 struct intel_connector *intel_connector = to_intel_connector(connector);
3357
3358 intel_attach_force_audio_property(connector);
3359 intel_attach_broadcast_rgb_property(connector);
3360 intel_dp->color_range_auto = true;
3361
3362 if (is_edp(intel_dp)) {
3363 drm_mode_create_scaling_mode_property(connector->dev);
3364 drm_object_attach_property(
3365 &connector->base,
3366 connector->dev->mode_config.scaling_mode_property,
3367 DRM_MODE_SCALE_ASPECT);
3368 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3369 }
3370 }
3371
3372 static void
3373 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3374 struct intel_dp *intel_dp,
3375 struct edp_power_seq *out)
3376 {
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 struct edp_power_seq cur, vbt, spec, final;
3379 u32 pp_on, pp_off, pp_div, pp;
3380 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3381
3382 if (HAS_PCH_SPLIT(dev)) {
3383 pp_ctrl_reg = PCH_PP_CONTROL;
3384 pp_on_reg = PCH_PP_ON_DELAYS;
3385 pp_off_reg = PCH_PP_OFF_DELAYS;
3386 pp_div_reg = PCH_PP_DIVISOR;
3387 } else {
3388 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3389
3390 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3391 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3392 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3393 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3394 }
3395
3396 /* Workaround: Need to write PP_CONTROL with the unlock key as
3397 * the very first thing. */
3398 pp = ironlake_get_pp_control(intel_dp);
3399 I915_WRITE(pp_ctrl_reg, pp);
3400
3401 pp_on = I915_READ(pp_on_reg);
3402 pp_off = I915_READ(pp_off_reg);
3403 pp_div = I915_READ(pp_div_reg);
3404
3405 /* Pull timing values out of registers */
3406 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3407 PANEL_POWER_UP_DELAY_SHIFT;
3408
3409 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3410 PANEL_LIGHT_ON_DELAY_SHIFT;
3411
3412 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3413 PANEL_LIGHT_OFF_DELAY_SHIFT;
3414
3415 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3416 PANEL_POWER_DOWN_DELAY_SHIFT;
3417
3418 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3419 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3420
3421 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3422 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3423
3424 vbt = dev_priv->vbt.edp_pps;
3425
3426 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3427 * our hw here, which are all in 100usec. */
3428 spec.t1_t3 = 210 * 10;
3429 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3430 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3431 spec.t10 = 500 * 10;
3432 /* This one is special and actually in units of 100ms, but zero
3433 * based in the hw (so we need to add 100 ms). But the sw vbt
3434 * table multiplies it with 1000 to make it in units of 100usec,
3435 * too. */
3436 spec.t11_t12 = (510 + 100) * 10;
3437
3438 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3439 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3440
3441 /* Use the max of the register settings and vbt. If both are
3442 * unset, fall back to the spec limits. */
3443 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3444 spec.field : \
3445 max(cur.field, vbt.field))
3446 assign_final(t1_t3);
3447 assign_final(t8);
3448 assign_final(t9);
3449 assign_final(t10);
3450 assign_final(t11_t12);
3451 #undef assign_final
3452
3453 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3454 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3455 intel_dp->backlight_on_delay = get_delay(t8);
3456 intel_dp->backlight_off_delay = get_delay(t9);
3457 intel_dp->panel_power_down_delay = get_delay(t10);
3458 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3459 #undef get_delay
3460
3461 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3462 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3463 intel_dp->panel_power_cycle_delay);
3464
3465 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3466 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3467
3468 if (out)
3469 *out = final;
3470 }
3471
3472 static void
3473 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3474 struct intel_dp *intel_dp,
3475 struct edp_power_seq *seq)
3476 {
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 u32 pp_on, pp_off, pp_div, port_sel = 0;
3479 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3480 int pp_on_reg, pp_off_reg, pp_div_reg;
3481
3482 if (HAS_PCH_SPLIT(dev)) {
3483 pp_on_reg = PCH_PP_ON_DELAYS;
3484 pp_off_reg = PCH_PP_OFF_DELAYS;
3485 pp_div_reg = PCH_PP_DIVISOR;
3486 } else {
3487 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3488
3489 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3490 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3491 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3492 }
3493
3494 /* And finally store the new values in the power sequencer. */
3495 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3496 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3497 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3498 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3499 /* Compute the divisor for the pp clock, simply match the Bspec
3500 * formula. */
3501 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3502 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3503 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3504
3505 /* Haswell doesn't have any port selection bits for the panel
3506 * power sequencer any more. */
3507 if (IS_VALLEYVIEW(dev)) {
3508 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3509 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3510 else
3511 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3512 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3513 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3514 port_sel = PANEL_PORT_SELECT_DPA;
3515 else
3516 port_sel = PANEL_PORT_SELECT_DPD;
3517 }
3518
3519 pp_on |= port_sel;
3520
3521 I915_WRITE(pp_on_reg, pp_on);
3522 I915_WRITE(pp_off_reg, pp_off);
3523 I915_WRITE(pp_div_reg, pp_div);
3524
3525 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3526 I915_READ(pp_on_reg),
3527 I915_READ(pp_off_reg),
3528 I915_READ(pp_div_reg));
3529 }
3530
3531 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3532 struct intel_connector *intel_connector)
3533 {
3534 struct drm_connector *connector = &intel_connector->base;
3535 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3536 struct drm_device *dev = intel_dig_port->base.base.dev;
3537 struct drm_i915_private *dev_priv = dev->dev_private;
3538 struct drm_display_mode *fixed_mode = NULL;
3539 struct edp_power_seq power_seq = { 0 };
3540 bool has_dpcd;
3541 struct drm_display_mode *scan;
3542 struct edid *edid;
3543
3544 if (!is_edp(intel_dp))
3545 return true;
3546
3547 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3548
3549 /* Cache DPCD and EDID for edp. */
3550 ironlake_edp_panel_vdd_on(intel_dp);
3551 has_dpcd = intel_dp_get_dpcd(intel_dp);
3552 ironlake_edp_panel_vdd_off(intel_dp, false);
3553
3554 if (has_dpcd) {
3555 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3556 dev_priv->no_aux_handshake =
3557 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3558 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3559 } else {
3560 /* if this fails, presume the device is a ghost */
3561 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3562 return false;
3563 }
3564
3565 /* We now know it's not a ghost, init power sequence regs. */
3566 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3567 &power_seq);
3568
3569 edid = drm_get_edid(connector, &intel_dp->adapter);
3570 if (edid) {
3571 if (drm_add_edid_modes(connector, edid)) {
3572 drm_mode_connector_update_edid_property(connector,
3573 edid);
3574 drm_edid_to_eld(connector, edid);
3575 } else {
3576 kfree(edid);
3577 edid = ERR_PTR(-EINVAL);
3578 }
3579 } else {
3580 edid = ERR_PTR(-ENOENT);
3581 }
3582 intel_connector->edid = edid;
3583
3584 /* prefer fixed mode from EDID if available */
3585 list_for_each_entry(scan, &connector->probed_modes, head) {
3586 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3587 fixed_mode = drm_mode_duplicate(dev, scan);
3588 break;
3589 }
3590 }
3591
3592 /* fallback to VBT if available for eDP */
3593 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3594 fixed_mode = drm_mode_duplicate(dev,
3595 dev_priv->vbt.lfp_lvds_vbt_mode);
3596 if (fixed_mode)
3597 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3598 }
3599
3600 intel_panel_init(&intel_connector->panel, fixed_mode);
3601 intel_panel_setup_backlight(connector);
3602
3603 return true;
3604 }
3605
3606 bool
3607 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3608 struct intel_connector *intel_connector)
3609 {
3610 struct drm_connector *connector = &intel_connector->base;
3611 struct intel_dp *intel_dp = &intel_dig_port->dp;
3612 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3613 struct drm_device *dev = intel_encoder->base.dev;
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615 enum port port = intel_dig_port->port;
3616 const char *name = NULL;
3617 int type, error;
3618
3619 /* Preserve the current hw state. */
3620 intel_dp->DP = I915_READ(intel_dp->output_reg);
3621 intel_dp->attached_connector = intel_connector;
3622
3623 if (intel_dp_is_edp(dev, port))
3624 type = DRM_MODE_CONNECTOR_eDP;
3625 else
3626 type = DRM_MODE_CONNECTOR_DisplayPort;
3627
3628 /*
3629 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3630 * for DP the encoder type can be set by the caller to
3631 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3632 */
3633 if (type == DRM_MODE_CONNECTOR_eDP)
3634 intel_encoder->type = INTEL_OUTPUT_EDP;
3635
3636 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3637 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3638 port_name(port));
3639
3640 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3641 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3642
3643 connector->interlace_allowed = true;
3644 connector->doublescan_allowed = 0;
3645
3646 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3647 ironlake_panel_vdd_work);
3648
3649 intel_connector_attach_encoder(intel_connector, intel_encoder);
3650 drm_sysfs_connector_add(connector);
3651
3652 if (HAS_DDI(dev))
3653 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3654 else
3655 intel_connector->get_hw_state = intel_connector_get_hw_state;
3656
3657 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3658 if (HAS_DDI(dev)) {
3659 switch (intel_dig_port->port) {
3660 case PORT_A:
3661 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3662 break;
3663 case PORT_B:
3664 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3665 break;
3666 case PORT_C:
3667 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3668 break;
3669 case PORT_D:
3670 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3671 break;
3672 default:
3673 BUG();
3674 }
3675 }
3676
3677 /* Set up the DDC bus. */
3678 switch (port) {
3679 case PORT_A:
3680 intel_encoder->hpd_pin = HPD_PORT_A;
3681 name = "DPDDC-A";
3682 break;
3683 case PORT_B:
3684 intel_encoder->hpd_pin = HPD_PORT_B;
3685 name = "DPDDC-B";
3686 break;
3687 case PORT_C:
3688 intel_encoder->hpd_pin = HPD_PORT_C;
3689 name = "DPDDC-C";
3690 break;
3691 case PORT_D:
3692 intel_encoder->hpd_pin = HPD_PORT_D;
3693 name = "DPDDC-D";
3694 break;
3695 default:
3696 BUG();
3697 }
3698
3699 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3700 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3701 error, port_name(port));
3702
3703 intel_dp->psr_setup_done = false;
3704
3705 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3706 i2c_del_adapter(&intel_dp->adapter);
3707 if (is_edp(intel_dp)) {
3708 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3709 mutex_lock(&dev->mode_config.mutex);
3710 ironlake_panel_vdd_off_sync(intel_dp);
3711 mutex_unlock(&dev->mode_config.mutex);
3712 }
3713 drm_sysfs_connector_remove(connector);
3714 drm_connector_cleanup(connector);
3715 return false;
3716 }
3717
3718 intel_dp_add_properties(intel_dp, connector);
3719
3720 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3721 * 0xd. Failure to do so will result in spurious interrupts being
3722 * generated on the port when a cable is not attached.
3723 */
3724 if (IS_G4X(dev) && !IS_GM45(dev)) {
3725 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3726 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3727 }
3728
3729 return true;
3730 }
3731
3732 void
3733 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3734 {
3735 struct intel_digital_port *intel_dig_port;
3736 struct intel_encoder *intel_encoder;
3737 struct drm_encoder *encoder;
3738 struct intel_connector *intel_connector;
3739
3740 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3741 if (!intel_dig_port)
3742 return;
3743
3744 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3745 if (!intel_connector) {
3746 kfree(intel_dig_port);
3747 return;
3748 }
3749
3750 intel_encoder = &intel_dig_port->base;
3751 encoder = &intel_encoder->base;
3752
3753 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3754 DRM_MODE_ENCODER_TMDS);
3755
3756 intel_encoder->compute_config = intel_dp_compute_config;
3757 intel_encoder->mode_set = intel_dp_mode_set;
3758 intel_encoder->disable = intel_disable_dp;
3759 intel_encoder->post_disable = intel_post_disable_dp;
3760 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3761 intel_encoder->get_config = intel_dp_get_config;
3762 if (IS_VALLEYVIEW(dev)) {
3763 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3764 intel_encoder->pre_enable = vlv_pre_enable_dp;
3765 intel_encoder->enable = vlv_enable_dp;
3766 } else {
3767 intel_encoder->pre_enable = g4x_pre_enable_dp;
3768 intel_encoder->enable = g4x_enable_dp;
3769 }
3770
3771 intel_dig_port->port = port;
3772 intel_dig_port->dp.output_reg = output_reg;
3773
3774 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3775 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3776 intel_encoder->cloneable = false;
3777 intel_encoder->hot_plug = intel_dp_hot_plug;
3778
3779 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3780 drm_encoder_cleanup(encoder);
3781 kfree(intel_dig_port);
3782 kfree(intel_connector);
3783 }
3784 }
Linux kernel - Deliverables
This page took 0.451961 seconds and 5 git commands to generate.