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Merge tag 'v3.14' into drm-intel-next-queued
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44 };
45
46 static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51 };
52
53 static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58 };
59
60 static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65 };
66
67 /**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74 static bool is_edp(struct intel_dp *intel_dp)
75 {
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
79 }
80
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
82 {
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
86 }
87
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89 {
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
91 }
92
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
96
97 static int
98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
99 {
100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
113 break;
114 default:
115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121 }
122
123 /*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
140 static int
141 intel_dp_link_required(int pixel_clock, int bpp)
142 {
143 return (pixel_clock * bpp + 9) / 10;
144 }
145
146 static int
147 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148 {
149 return (max_link_clock * max_lanes * 8) / 10;
150 }
151
152 static enum drm_mode_status
153 intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155 {
156 struct intel_dp *intel_dp = intel_attached_dp(connector);
157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
161
162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
164 return MODE_PANEL;
165
166 if (mode->vdisplay > fixed_mode->vdisplay)
167 return MODE_PANEL;
168
169 target_clock = fixed_mode->clock;
170 }
171
172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
179 return MODE_CLOCK_HIGH;
180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
187 return MODE_OK;
188 }
189
190 static uint32_t
191 pack_aux(uint8_t *src, int src_bytes)
192 {
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201 }
202
203 static void
204 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205 {
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211 }
212
213 /* hrawclock is 1/4 the FSB frequency */
214 static int
215 intel_hrawclk(struct drm_device *dev)
216 {
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245 }
246
247 static void
248 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251 static void
252 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256 static enum pipe
257 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258 {
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282 }
283
284 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285 {
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292 }
293
294 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295 {
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302 }
303
304 static bool edp_have_panel_power(struct intel_dp *intel_dp)
305 {
306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
307 struct drm_i915_private *dev_priv = dev->dev_private;
308
309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
310 }
311
312 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
313 {
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
318 }
319
320 static void
321 intel_dp_check_edp(struct intel_dp *intel_dp)
322 {
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 if (!is_edp(intel_dp))
327 return;
328
329 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
332 I915_READ(_pp_stat_reg(intel_dp)),
333 I915_READ(_pp_ctrl_reg(intel_dp)));
334 }
335 }
336
337 static uint32_t
338 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
339 {
340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
341 struct drm_device *dev = intel_dig_port->base.base.dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
343 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
344 uint32_t status;
345 bool done;
346
347 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
348 if (has_aux_irq)
349 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
350 msecs_to_jiffies_timeout(10));
351 else
352 done = wait_for_atomic(C, 10) == 0;
353 if (!done)
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
355 has_aux_irq);
356 #undef C
357
358 return status;
359 }
360
361 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
362 {
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365
366 /*
367 * The clock divider is based off the hrawclk, and would like to run at
368 * 2MHz. So, take the hrawclk value and divide by 2 and use that
369 */
370 return index ? 0 : intel_hrawclk(dev) / 2;
371 }
372
373 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
374 {
375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
376 struct drm_device *dev = intel_dig_port->base.base.dev;
377
378 if (index)
379 return 0;
380
381 if (intel_dig_port->port == PORT_A) {
382 if (IS_GEN6(dev) || IS_GEN7(dev))
383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
384 else
385 return 225; /* eDP input clock at 450Mhz */
386 } else {
387 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
388 }
389 }
390
391 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
392 {
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct drm_device *dev = intel_dig_port->base.base.dev;
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (intel_dig_port->port == PORT_A) {
398 if (index)
399 return 0;
400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
401 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
402 /* Workaround for non-ULT HSW */
403 switch (index) {
404 case 0: return 63;
405 case 1: return 72;
406 default: return 0;
407 }
408 } else {
409 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
410 }
411 }
412
413 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414 {
415 return index ? 0 : 100;
416 }
417
418 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
419 bool has_aux_irq,
420 int send_bytes,
421 uint32_t aux_clock_divider)
422 {
423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
424 struct drm_device *dev = intel_dig_port->base.base.dev;
425 uint32_t precharge, timeout;
426
427 if (IS_GEN6(dev))
428 precharge = 3;
429 else
430 precharge = 5;
431
432 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
433 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
434 else
435 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
436
437 return DP_AUX_CH_CTL_SEND_BUSY |
438 DP_AUX_CH_CTL_DONE |
439 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
440 DP_AUX_CH_CTL_TIME_OUT_ERROR |
441 timeout |
442 DP_AUX_CH_CTL_RECEIVE_ERROR |
443 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
444 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
445 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
446 }
447
448 static int
449 intel_dp_aux_ch(struct intel_dp *intel_dp,
450 uint8_t *send, int send_bytes,
451 uint8_t *recv, int recv_size)
452 {
453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
454 struct drm_device *dev = intel_dig_port->base.base.dev;
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
457 uint32_t ch_data = ch_ctl + 4;
458 uint32_t aux_clock_divider;
459 int i, ret, recv_bytes;
460 uint32_t status;
461 int try, clock = 0;
462 bool has_aux_irq = HAS_AUX_IRQ(dev);
463 bool vdd;
464
465 vdd = _edp_panel_vdd_on(intel_dp);
466
467 /* dp aux is extremely sensitive to irq latency, hence request the
468 * lowest possible wakeup latency and so prevent the cpu from going into
469 * deep sleep states.
470 */
471 pm_qos_update_request(&dev_priv->pm_qos, 0);
472
473 intel_dp_check_edp(intel_dp);
474
475 intel_aux_display_runtime_get(dev_priv);
476
477 /* Try to wait for any previous AUX channel activity */
478 for (try = 0; try < 3; try++) {
479 status = I915_READ_NOTRACE(ch_ctl);
480 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
481 break;
482 msleep(1);
483 }
484
485 if (try == 3) {
486 WARN(1, "dp_aux_ch not started status 0x%08x\n",
487 I915_READ(ch_ctl));
488 ret = -EBUSY;
489 goto out;
490 }
491
492 /* Only 5 data registers! */
493 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
494 ret = -E2BIG;
495 goto out;
496 }
497
498 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
499 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
500 has_aux_irq,
501 send_bytes,
502 aux_clock_divider);
503
504 /* Must try at least 3 times according to DP spec */
505 for (try = 0; try < 5; try++) {
506 /* Load the send data into the aux channel data registers */
507 for (i = 0; i < send_bytes; i += 4)
508 I915_WRITE(ch_data + i,
509 pack_aux(send + i, send_bytes - i));
510
511 /* Send the command and wait for it to complete */
512 I915_WRITE(ch_ctl, send_ctl);
513
514 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
515
516 /* Clear done status and any errors */
517 I915_WRITE(ch_ctl,
518 status |
519 DP_AUX_CH_CTL_DONE |
520 DP_AUX_CH_CTL_TIME_OUT_ERROR |
521 DP_AUX_CH_CTL_RECEIVE_ERROR);
522
523 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
524 DP_AUX_CH_CTL_RECEIVE_ERROR))
525 continue;
526 if (status & DP_AUX_CH_CTL_DONE)
527 break;
528 }
529 if (status & DP_AUX_CH_CTL_DONE)
530 break;
531 }
532
533 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
534 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
535 ret = -EBUSY;
536 goto out;
537 }
538
539 /* Check for timeout or receive error.
540 * Timeouts occur when the sink is not connected
541 */
542 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
543 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
544 ret = -EIO;
545 goto out;
546 }
547
548 /* Timeouts occur when the device isn't connected, so they're
549 * "normal" -- don't fill the kernel log with these */
550 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
551 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
552 ret = -ETIMEDOUT;
553 goto out;
554 }
555
556 /* Unload any bytes sent back from the other side */
557 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
558 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
559 if (recv_bytes > recv_size)
560 recv_bytes = recv_size;
561
562 for (i = 0; i < recv_bytes; i += 4)
563 unpack_aux(I915_READ(ch_data + i),
564 recv + i, recv_bytes - i);
565
566 ret = recv_bytes;
567 out:
568 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
569 intel_aux_display_runtime_put(dev_priv);
570
571 if (vdd)
572 edp_panel_vdd_off(intel_dp, false);
573
574 return ret;
575 }
576
577 #define HEADER_SIZE 4
578 static ssize_t
579 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
580 {
581 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
582 uint8_t txbuf[20], rxbuf[20];
583 size_t txsize, rxsize;
584 int ret;
585
586 txbuf[0] = msg->request << 4;
587 txbuf[1] = msg->address >> 8;
588 txbuf[2] = msg->address & 0xff;
589 txbuf[3] = msg->size - 1;
590
591 switch (msg->request & ~DP_AUX_I2C_MOT) {
592 case DP_AUX_NATIVE_WRITE:
593 case DP_AUX_I2C_WRITE:
594 txsize = HEADER_SIZE + msg->size;
595 rxsize = 1;
596
597 if (WARN_ON(txsize > 20))
598 return -E2BIG;
599
600 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
601
602 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
603 if (ret > 0) {
604 msg->reply = rxbuf[0] >> 4;
605
606 /* Return payload size. */
607 ret = msg->size;
608 }
609 break;
610
611 case DP_AUX_NATIVE_READ:
612 case DP_AUX_I2C_READ:
613 txsize = HEADER_SIZE;
614 rxsize = msg->size + 1;
615
616 if (WARN_ON(rxsize > 20))
617 return -E2BIG;
618
619 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
620 if (ret > 0) {
621 msg->reply = rxbuf[0] >> 4;
622 /*
623 * Assume happy day, and copy the data. The caller is
624 * expected to check msg->reply before touching it.
625 *
626 * Return payload size.
627 */
628 ret--;
629 memcpy(msg->buffer, rxbuf + 1, ret);
630 }
631 break;
632
633 default:
634 ret = -EINVAL;
635 break;
636 }
637
638 return ret;
639 }
640
641 static void
642 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
643 {
644 struct drm_device *dev = intel_dp_to_dev(intel_dp);
645 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
646 enum port port = intel_dig_port->port;
647 const char *name = NULL;
648 int ret;
649
650 switch (port) {
651 case PORT_A:
652 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
653 name = "DPDDC-A";
654 break;
655 case PORT_B:
656 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
657 name = "DPDDC-B";
658 break;
659 case PORT_C:
660 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
661 name = "DPDDC-C";
662 break;
663 case PORT_D:
664 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
665 name = "DPDDC-D";
666 break;
667 default:
668 BUG();
669 }
670
671 if (!HAS_DDI(dev))
672 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
673
674 intel_dp->aux.name = name;
675 intel_dp->aux.dev = dev->dev;
676 intel_dp->aux.transfer = intel_dp_aux_transfer;
677
678 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
679 connector->base.kdev->kobj.name);
680
681 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
682 if (ret < 0) {
683 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
684 name, ret);
685 return;
686 }
687
688 ret = sysfs_create_link(&connector->base.kdev->kobj,
689 &intel_dp->aux.ddc.dev.kobj,
690 intel_dp->aux.ddc.dev.kobj.name);
691 if (ret < 0) {
692 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
693 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
694 }
695 }
696
697 static void
698 intel_dp_connector_unregister(struct intel_connector *intel_connector)
699 {
700 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
701
702 sysfs_remove_link(&intel_connector->base.kdev->kobj,
703 intel_dp->aux.ddc.dev.kobj.name);
704 intel_connector_unregister(intel_connector);
705 }
706
707 static void
708 intel_dp_set_clock(struct intel_encoder *encoder,
709 struct intel_crtc_config *pipe_config, int link_bw)
710 {
711 struct drm_device *dev = encoder->base.dev;
712 const struct dp_link_dpll *divisor = NULL;
713 int i, count = 0;
714
715 if (IS_G4X(dev)) {
716 divisor = gen4_dpll;
717 count = ARRAY_SIZE(gen4_dpll);
718 } else if (IS_HASWELL(dev)) {
719 /* Haswell has special-purpose DP DDI clocks. */
720 } else if (HAS_PCH_SPLIT(dev)) {
721 divisor = pch_dpll;
722 count = ARRAY_SIZE(pch_dpll);
723 } else if (IS_VALLEYVIEW(dev)) {
724 divisor = vlv_dpll;
725 count = ARRAY_SIZE(vlv_dpll);
726 }
727
728 if (divisor && count) {
729 for (i = 0; i < count; i++) {
730 if (link_bw == divisor[i].link_bw) {
731 pipe_config->dpll = divisor[i].dpll;
732 pipe_config->clock_set = true;
733 break;
734 }
735 }
736 }
737 }
738
739 bool
740 intel_dp_compute_config(struct intel_encoder *encoder,
741 struct intel_crtc_config *pipe_config)
742 {
743 struct drm_device *dev = encoder->base.dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
746 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
747 enum port port = dp_to_dig_port(intel_dp)->port;
748 struct intel_crtc *intel_crtc = encoder->new_crtc;
749 struct intel_connector *intel_connector = intel_dp->attached_connector;
750 int lane_count, clock;
751 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
752 /* Conveniently, the link BW constants become indices with a shift...*/
753 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
754 int bpp, mode_rate;
755 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
756 int link_avail, link_clock;
757
758 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
759 pipe_config->has_pch_encoder = true;
760
761 pipe_config->has_dp_encoder = true;
762
763 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
764 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
765 adjusted_mode);
766 if (!HAS_PCH_SPLIT(dev))
767 intel_gmch_panel_fitting(intel_crtc, pipe_config,
768 intel_connector->panel.fitting_mode);
769 else
770 intel_pch_panel_fitting(intel_crtc, pipe_config,
771 intel_connector->panel.fitting_mode);
772 }
773
774 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
775 return false;
776
777 DRM_DEBUG_KMS("DP link computation with max lane count %i "
778 "max bw %02x pixel clock %iKHz\n",
779 max_lane_count, bws[max_clock],
780 adjusted_mode->crtc_clock);
781
782 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
783 * bpc in between. */
784 bpp = pipe_config->pipe_bpp;
785 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
786 dev_priv->vbt.edp_bpp < bpp) {
787 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
788 dev_priv->vbt.edp_bpp);
789 bpp = dev_priv->vbt.edp_bpp;
790 }
791
792 for (; bpp >= 6*3; bpp -= 2*3) {
793 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
794 bpp);
795
796 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
797 for (clock = 0; clock <= max_clock; clock++) {
798 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
799 link_avail = intel_dp_max_data_rate(link_clock,
800 lane_count);
801
802 if (mode_rate <= link_avail) {
803 goto found;
804 }
805 }
806 }
807 }
808
809 return false;
810
811 found:
812 if (intel_dp->color_range_auto) {
813 /*
814 * See:
815 * CEA-861-E - 5.1 Default Encoding Parameters
816 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
817 */
818 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
819 intel_dp->color_range = DP_COLOR_RANGE_16_235;
820 else
821 intel_dp->color_range = 0;
822 }
823
824 if (intel_dp->color_range)
825 pipe_config->limited_color_range = true;
826
827 intel_dp->link_bw = bws[clock];
828 intel_dp->lane_count = lane_count;
829 pipe_config->pipe_bpp = bpp;
830 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
831
832 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
833 intel_dp->link_bw, intel_dp->lane_count,
834 pipe_config->port_clock, bpp);
835 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
836 mode_rate, link_avail);
837
838 intel_link_compute_m_n(bpp, lane_count,
839 adjusted_mode->crtc_clock,
840 pipe_config->port_clock,
841 &pipe_config->dp_m_n);
842
843 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
844
845 return true;
846 }
847
848 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
849 {
850 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
851 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
852 struct drm_device *dev = crtc->base.dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
854 u32 dpa_ctl;
855
856 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
857 dpa_ctl = I915_READ(DP_A);
858 dpa_ctl &= ~DP_PLL_FREQ_MASK;
859
860 if (crtc->config.port_clock == 162000) {
861 /* For a long time we've carried around a ILK-DevA w/a for the
862 * 160MHz clock. If we're really unlucky, it's still required.
863 */
864 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
865 dpa_ctl |= DP_PLL_FREQ_160MHZ;
866 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
867 } else {
868 dpa_ctl |= DP_PLL_FREQ_270MHZ;
869 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
870 }
871
872 I915_WRITE(DP_A, dpa_ctl);
873
874 POSTING_READ(DP_A);
875 udelay(500);
876 }
877
878 static void intel_dp_mode_set(struct intel_encoder *encoder)
879 {
880 struct drm_device *dev = encoder->base.dev;
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
883 enum port port = dp_to_dig_port(intel_dp)->port;
884 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
885 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
886
887 /*
888 * There are four kinds of DP registers:
889 *
890 * IBX PCH
891 * SNB CPU
892 * IVB CPU
893 * CPT PCH
894 *
895 * IBX PCH and CPU are the same for almost everything,
896 * except that the CPU DP PLL is configured in this
897 * register
898 *
899 * CPT PCH is quite different, having many bits moved
900 * to the TRANS_DP_CTL register instead. That
901 * configuration happens (oddly) in ironlake_pch_enable
902 */
903
904 /* Preserve the BIOS-computed detected bit. This is
905 * supposed to be read-only.
906 */
907 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
908
909 /* Handle DP bits in common between all three register formats */
910 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
911 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
912
913 if (intel_dp->has_audio) {
914 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
915 pipe_name(crtc->pipe));
916 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
917 intel_write_eld(&encoder->base, adjusted_mode);
918 }
919
920 /* Split out the IBX/CPU vs CPT settings */
921
922 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
923 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
924 intel_dp->DP |= DP_SYNC_HS_HIGH;
925 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
926 intel_dp->DP |= DP_SYNC_VS_HIGH;
927 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
928
929 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
930 intel_dp->DP |= DP_ENHANCED_FRAMING;
931
932 intel_dp->DP |= crtc->pipe << 29;
933 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
934 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
935 intel_dp->DP |= intel_dp->color_range;
936
937 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
938 intel_dp->DP |= DP_SYNC_HS_HIGH;
939 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
940 intel_dp->DP |= DP_SYNC_VS_HIGH;
941 intel_dp->DP |= DP_LINK_TRAIN_OFF;
942
943 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
944 intel_dp->DP |= DP_ENHANCED_FRAMING;
945
946 if (crtc->pipe == 1)
947 intel_dp->DP |= DP_PIPEB_SELECT;
948 } else {
949 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
950 }
951
952 if (port == PORT_A && !IS_VALLEYVIEW(dev))
953 ironlake_set_pll_cpu_edp(intel_dp);
954 }
955
956 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
957 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
958
959 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
960 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
961
962 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
963 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
964
965 static void wait_panel_status(struct intel_dp *intel_dp,
966 u32 mask,
967 u32 value)
968 {
969 struct drm_device *dev = intel_dp_to_dev(intel_dp);
970 struct drm_i915_private *dev_priv = dev->dev_private;
971 u32 pp_stat_reg, pp_ctrl_reg;
972
973 pp_stat_reg = _pp_stat_reg(intel_dp);
974 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
975
976 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
977 mask, value,
978 I915_READ(pp_stat_reg),
979 I915_READ(pp_ctrl_reg));
980
981 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
982 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
983 I915_READ(pp_stat_reg),
984 I915_READ(pp_ctrl_reg));
985 }
986
987 DRM_DEBUG_KMS("Wait complete\n");
988 }
989
990 static void wait_panel_on(struct intel_dp *intel_dp)
991 {
992 DRM_DEBUG_KMS("Wait for panel power on\n");
993 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
994 }
995
996 static void wait_panel_off(struct intel_dp *intel_dp)
997 {
998 DRM_DEBUG_KMS("Wait for panel power off time\n");
999 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1000 }
1001
1002 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1003 {
1004 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1005
1006 /* When we disable the VDD override bit last we have to do the manual
1007 * wait. */
1008 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1009 intel_dp->panel_power_cycle_delay);
1010
1011 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1012 }
1013
1014 static void wait_backlight_on(struct intel_dp *intel_dp)
1015 {
1016 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1017 intel_dp->backlight_on_delay);
1018 }
1019
1020 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1021 {
1022 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1023 intel_dp->backlight_off_delay);
1024 }
1025
1026 /* Read the current pp_control value, unlocking the register if it
1027 * is locked
1028 */
1029
1030 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1031 {
1032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034 u32 control;
1035
1036 control = I915_READ(_pp_ctrl_reg(intel_dp));
1037 control &= ~PANEL_UNLOCK_MASK;
1038 control |= PANEL_UNLOCK_REGS;
1039 return control;
1040 }
1041
1042 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1043 {
1044 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046 u32 pp;
1047 u32 pp_stat_reg, pp_ctrl_reg;
1048 bool need_to_disable = !intel_dp->want_panel_vdd;
1049
1050 if (!is_edp(intel_dp))
1051 return false;
1052
1053 intel_dp->want_panel_vdd = true;
1054
1055 if (edp_have_panel_vdd(intel_dp))
1056 return need_to_disable;
1057
1058 intel_runtime_pm_get(dev_priv);
1059
1060 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1061
1062 if (!edp_have_panel_power(intel_dp))
1063 wait_panel_power_cycle(intel_dp);
1064
1065 pp = ironlake_get_pp_control(intel_dp);
1066 pp |= EDP_FORCE_VDD;
1067
1068 pp_stat_reg = _pp_stat_reg(intel_dp);
1069 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1070
1071 I915_WRITE(pp_ctrl_reg, pp);
1072 POSTING_READ(pp_ctrl_reg);
1073 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1074 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1075 /*
1076 * If the panel wasn't on, delay before accessing aux channel
1077 */
1078 if (!edp_have_panel_power(intel_dp)) {
1079 DRM_DEBUG_KMS("eDP was not running\n");
1080 msleep(intel_dp->panel_power_up_delay);
1081 }
1082
1083 return need_to_disable;
1084 }
1085
1086 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1087 {
1088 if (is_edp(intel_dp)) {
1089 bool vdd = _edp_panel_vdd_on(intel_dp);
1090
1091 WARN(!vdd, "eDP VDD already requested on\n");
1092 }
1093 }
1094
1095 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1096 {
1097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 u32 pp;
1100 u32 pp_stat_reg, pp_ctrl_reg;
1101
1102 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1103
1104 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1105 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1106
1107 pp = ironlake_get_pp_control(intel_dp);
1108 pp &= ~EDP_FORCE_VDD;
1109
1110 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1111 pp_stat_reg = _pp_stat_reg(intel_dp);
1112
1113 I915_WRITE(pp_ctrl_reg, pp);
1114 POSTING_READ(pp_ctrl_reg);
1115
1116 /* Make sure sequencer is idle before allowing subsequent activity */
1117 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1118 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1119
1120 if ((pp & POWER_TARGET_ON) == 0)
1121 intel_dp->last_power_cycle = jiffies;
1122
1123 intel_runtime_pm_put(dev_priv);
1124 }
1125 }
1126
1127 static void edp_panel_vdd_work(struct work_struct *__work)
1128 {
1129 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1130 struct intel_dp, panel_vdd_work);
1131 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1132
1133 mutex_lock(&dev->mode_config.mutex);
1134 edp_panel_vdd_off_sync(intel_dp);
1135 mutex_unlock(&dev->mode_config.mutex);
1136 }
1137
1138 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1139 {
1140 if (!is_edp(intel_dp))
1141 return;
1142
1143 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1144
1145 intel_dp->want_panel_vdd = false;
1146
1147 if (sync) {
1148 edp_panel_vdd_off_sync(intel_dp);
1149 } else {
1150 /*
1151 * Queue the timer to fire a long
1152 * time from now (relative to the power down delay)
1153 * to keep the panel power up across a sequence of operations
1154 */
1155 schedule_delayed_work(&intel_dp->panel_vdd_work,
1156 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1157 }
1158 }
1159
1160 void intel_edp_panel_on(struct intel_dp *intel_dp)
1161 {
1162 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1163 struct drm_i915_private *dev_priv = dev->dev_private;
1164 u32 pp;
1165 u32 pp_ctrl_reg;
1166
1167 if (!is_edp(intel_dp))
1168 return;
1169
1170 DRM_DEBUG_KMS("Turn eDP power on\n");
1171
1172 if (edp_have_panel_power(intel_dp)) {
1173 DRM_DEBUG_KMS("eDP power already on\n");
1174 return;
1175 }
1176
1177 wait_panel_power_cycle(intel_dp);
1178
1179 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1180 pp = ironlake_get_pp_control(intel_dp);
1181 if (IS_GEN5(dev)) {
1182 /* ILK workaround: disable reset around power sequence */
1183 pp &= ~PANEL_POWER_RESET;
1184 I915_WRITE(pp_ctrl_reg, pp);
1185 POSTING_READ(pp_ctrl_reg);
1186 }
1187
1188 pp |= POWER_TARGET_ON;
1189 if (!IS_GEN5(dev))
1190 pp |= PANEL_POWER_RESET;
1191
1192 I915_WRITE(pp_ctrl_reg, pp);
1193 POSTING_READ(pp_ctrl_reg);
1194
1195 wait_panel_on(intel_dp);
1196 intel_dp->last_power_on = jiffies;
1197
1198 if (IS_GEN5(dev)) {
1199 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1200 I915_WRITE(pp_ctrl_reg, pp);
1201 POSTING_READ(pp_ctrl_reg);
1202 }
1203 }
1204
1205 void intel_edp_panel_off(struct intel_dp *intel_dp)
1206 {
1207 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1208 struct drm_i915_private *dev_priv = dev->dev_private;
1209 u32 pp;
1210 u32 pp_ctrl_reg;
1211
1212 if (!is_edp(intel_dp))
1213 return;
1214
1215 DRM_DEBUG_KMS("Turn eDP power off\n");
1216
1217 edp_wait_backlight_off(intel_dp);
1218
1219 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1220
1221 pp = ironlake_get_pp_control(intel_dp);
1222 /* We need to switch off panel power _and_ force vdd, for otherwise some
1223 * panels get very unhappy and cease to work. */
1224 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1225 EDP_BLC_ENABLE);
1226
1227 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1228
1229 intel_dp->want_panel_vdd = false;
1230
1231 I915_WRITE(pp_ctrl_reg, pp);
1232 POSTING_READ(pp_ctrl_reg);
1233
1234 intel_dp->last_power_cycle = jiffies;
1235 wait_panel_off(intel_dp);
1236
1237 /* We got a reference when we enabled the VDD. */
1238 intel_runtime_pm_put(dev_priv);
1239 }
1240
1241 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1242 {
1243 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1244 struct drm_device *dev = intel_dig_port->base.base.dev;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 u32 pp;
1247 u32 pp_ctrl_reg;
1248
1249 if (!is_edp(intel_dp))
1250 return;
1251
1252 DRM_DEBUG_KMS("\n");
1253 /*
1254 * If we enable the backlight right away following a panel power
1255 * on, we may see slight flicker as the panel syncs with the eDP
1256 * link. So delay a bit to make sure the image is solid before
1257 * allowing it to appear.
1258 */
1259 wait_backlight_on(intel_dp);
1260 pp = ironlake_get_pp_control(intel_dp);
1261 pp |= EDP_BLC_ENABLE;
1262
1263 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1264
1265 I915_WRITE(pp_ctrl_reg, pp);
1266 POSTING_READ(pp_ctrl_reg);
1267
1268 intel_panel_enable_backlight(intel_dp->attached_connector);
1269 }
1270
1271 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1272 {
1273 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 u32 pp;
1276 u32 pp_ctrl_reg;
1277
1278 if (!is_edp(intel_dp))
1279 return;
1280
1281 intel_panel_disable_backlight(intel_dp->attached_connector);
1282
1283 DRM_DEBUG_KMS("\n");
1284 pp = ironlake_get_pp_control(intel_dp);
1285 pp &= ~EDP_BLC_ENABLE;
1286
1287 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1288
1289 I915_WRITE(pp_ctrl_reg, pp);
1290 POSTING_READ(pp_ctrl_reg);
1291 intel_dp->last_backlight_off = jiffies;
1292 }
1293
1294 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1295 {
1296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1298 struct drm_device *dev = crtc->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 u32 dpa_ctl;
1301
1302 assert_pipe_disabled(dev_priv,
1303 to_intel_crtc(crtc)->pipe);
1304
1305 DRM_DEBUG_KMS("\n");
1306 dpa_ctl = I915_READ(DP_A);
1307 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1308 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1309
1310 /* We don't adjust intel_dp->DP while tearing down the link, to
1311 * facilitate link retraining (e.g. after hotplug). Hence clear all
1312 * enable bits here to ensure that we don't enable too much. */
1313 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1314 intel_dp->DP |= DP_PLL_ENABLE;
1315 I915_WRITE(DP_A, intel_dp->DP);
1316 POSTING_READ(DP_A);
1317 udelay(200);
1318 }
1319
1320 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1321 {
1322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1323 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1324 struct drm_device *dev = crtc->dev;
1325 struct drm_i915_private *dev_priv = dev->dev_private;
1326 u32 dpa_ctl;
1327
1328 assert_pipe_disabled(dev_priv,
1329 to_intel_crtc(crtc)->pipe);
1330
1331 dpa_ctl = I915_READ(DP_A);
1332 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1333 "dp pll off, should be on\n");
1334 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1335
1336 /* We can't rely on the value tracked for the DP register in
1337 * intel_dp->DP because link_down must not change that (otherwise link
1338 * re-training will fail. */
1339 dpa_ctl &= ~DP_PLL_ENABLE;
1340 I915_WRITE(DP_A, dpa_ctl);
1341 POSTING_READ(DP_A);
1342 udelay(200);
1343 }
1344
1345 /* If the sink supports it, try to set the power state appropriately */
1346 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1347 {
1348 int ret, i;
1349
1350 /* Should have a valid DPCD by this point */
1351 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1352 return;
1353
1354 if (mode != DRM_MODE_DPMS_ON) {
1355 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1356 DP_SET_POWER_D3);
1357 if (ret != 1)
1358 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1359 } else {
1360 /*
1361 * When turning on, we need to retry for 1ms to give the sink
1362 * time to wake up.
1363 */
1364 for (i = 0; i < 3; i++) {
1365 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1366 DP_SET_POWER_D0);
1367 if (ret == 1)
1368 break;
1369 msleep(1);
1370 }
1371 }
1372 }
1373
1374 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1375 enum pipe *pipe)
1376 {
1377 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1378 enum port port = dp_to_dig_port(intel_dp)->port;
1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 enum intel_display_power_domain power_domain;
1382 u32 tmp;
1383
1384 power_domain = intel_display_port_power_domain(encoder);
1385 if (!intel_display_power_enabled(dev_priv, power_domain))
1386 return false;
1387
1388 tmp = I915_READ(intel_dp->output_reg);
1389
1390 if (!(tmp & DP_PORT_EN))
1391 return false;
1392
1393 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1394 *pipe = PORT_TO_PIPE_CPT(tmp);
1395 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1396 *pipe = PORT_TO_PIPE(tmp);
1397 } else {
1398 u32 trans_sel;
1399 u32 trans_dp;
1400 int i;
1401
1402 switch (intel_dp->output_reg) {
1403 case PCH_DP_B:
1404 trans_sel = TRANS_DP_PORT_SEL_B;
1405 break;
1406 case PCH_DP_C:
1407 trans_sel = TRANS_DP_PORT_SEL_C;
1408 break;
1409 case PCH_DP_D:
1410 trans_sel = TRANS_DP_PORT_SEL_D;
1411 break;
1412 default:
1413 return true;
1414 }
1415
1416 for_each_pipe(i) {
1417 trans_dp = I915_READ(TRANS_DP_CTL(i));
1418 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1419 *pipe = i;
1420 return true;
1421 }
1422 }
1423
1424 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1425 intel_dp->output_reg);
1426 }
1427
1428 return true;
1429 }
1430
1431 static void intel_dp_get_config(struct intel_encoder *encoder,
1432 struct intel_crtc_config *pipe_config)
1433 {
1434 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1435 u32 tmp, flags = 0;
1436 struct drm_device *dev = encoder->base.dev;
1437 struct drm_i915_private *dev_priv = dev->dev_private;
1438 enum port port = dp_to_dig_port(intel_dp)->port;
1439 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1440 int dotclock;
1441
1442 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1443 tmp = I915_READ(intel_dp->output_reg);
1444 if (tmp & DP_SYNC_HS_HIGH)
1445 flags |= DRM_MODE_FLAG_PHSYNC;
1446 else
1447 flags |= DRM_MODE_FLAG_NHSYNC;
1448
1449 if (tmp & DP_SYNC_VS_HIGH)
1450 flags |= DRM_MODE_FLAG_PVSYNC;
1451 else
1452 flags |= DRM_MODE_FLAG_NVSYNC;
1453 } else {
1454 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1455 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1456 flags |= DRM_MODE_FLAG_PHSYNC;
1457 else
1458 flags |= DRM_MODE_FLAG_NHSYNC;
1459
1460 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1461 flags |= DRM_MODE_FLAG_PVSYNC;
1462 else
1463 flags |= DRM_MODE_FLAG_NVSYNC;
1464 }
1465
1466 pipe_config->adjusted_mode.flags |= flags;
1467
1468 pipe_config->has_dp_encoder = true;
1469
1470 intel_dp_get_m_n(crtc, pipe_config);
1471
1472 if (port == PORT_A) {
1473 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1474 pipe_config->port_clock = 162000;
1475 else
1476 pipe_config->port_clock = 270000;
1477 }
1478
1479 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1480 &pipe_config->dp_m_n);
1481
1482 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1483 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1484
1485 pipe_config->adjusted_mode.crtc_clock = dotclock;
1486
1487 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1488 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1489 /*
1490 * This is a big fat ugly hack.
1491 *
1492 * Some machines in UEFI boot mode provide us a VBT that has 18
1493 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1494 * unknown we fail to light up. Yet the same BIOS boots up with
1495 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1496 * max, not what it tells us to use.
1497 *
1498 * Note: This will still be broken if the eDP panel is not lit
1499 * up by the BIOS, and thus we can't get the mode at module
1500 * load.
1501 */
1502 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1503 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1504 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1505 }
1506 }
1507
1508 static bool is_edp_psr(struct drm_device *dev)
1509 {
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
1512 return dev_priv->psr.sink_support;
1513 }
1514
1515 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1516 {
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518
1519 if (!HAS_PSR(dev))
1520 return false;
1521
1522 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1523 }
1524
1525 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1526 struct edp_vsc_psr *vsc_psr)
1527 {
1528 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1529 struct drm_device *dev = dig_port->base.base.dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1532 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1533 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1534 uint32_t *data = (uint32_t *) vsc_psr;
1535 unsigned int i;
1536
1537 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1538 the video DIP being updated before program video DIP data buffer
1539 registers for DIP being updated. */
1540 I915_WRITE(ctl_reg, 0);
1541 POSTING_READ(ctl_reg);
1542
1543 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1544 if (i < sizeof(struct edp_vsc_psr))
1545 I915_WRITE(data_reg + i, *data++);
1546 else
1547 I915_WRITE(data_reg + i, 0);
1548 }
1549
1550 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1551 POSTING_READ(ctl_reg);
1552 }
1553
1554 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1555 {
1556 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 struct edp_vsc_psr psr_vsc;
1559
1560 if (intel_dp->psr_setup_done)
1561 return;
1562
1563 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1564 memset(&psr_vsc, 0, sizeof(psr_vsc));
1565 psr_vsc.sdp_header.HB0 = 0;
1566 psr_vsc.sdp_header.HB1 = 0x7;
1567 psr_vsc.sdp_header.HB2 = 0x2;
1568 psr_vsc.sdp_header.HB3 = 0x8;
1569 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1570
1571 /* Avoid continuous PSR exit by masking memup and hpd */
1572 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1573 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1574
1575 intel_dp->psr_setup_done = true;
1576 }
1577
1578 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1579 {
1580 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 uint32_t aux_clock_divider;
1583 int precharge = 0x3;
1584 int msg_size = 5; /* Header(4) + Message(1) */
1585
1586 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1587
1588 /* Enable PSR in sink */
1589 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1590 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1591 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1592 else
1593 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1594 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1595
1596 /* Setup AUX registers */
1597 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1598 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1599 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1600 DP_AUX_CH_CTL_TIME_OUT_400us |
1601 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1602 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1603 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1604 }
1605
1606 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1607 {
1608 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 uint32_t max_sleep_time = 0x1f;
1611 uint32_t idle_frames = 1;
1612 uint32_t val = 0x0;
1613 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1614
1615 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1616 val |= EDP_PSR_LINK_STANDBY;
1617 val |= EDP_PSR_TP2_TP3_TIME_0us;
1618 val |= EDP_PSR_TP1_TIME_0us;
1619 val |= EDP_PSR_SKIP_AUX_EXIT;
1620 } else
1621 val |= EDP_PSR_LINK_DISABLE;
1622
1623 I915_WRITE(EDP_PSR_CTL(dev), val |
1624 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1625 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1626 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1627 EDP_PSR_ENABLE);
1628 }
1629
1630 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1631 {
1632 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1633 struct drm_device *dev = dig_port->base.base.dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 struct drm_crtc *crtc = dig_port->base.base.crtc;
1636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1637 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1638 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1639
1640 dev_priv->psr.source_ok = false;
1641
1642 if (!HAS_PSR(dev)) {
1643 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1644 return false;
1645 }
1646
1647 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1648 (dig_port->port != PORT_A)) {
1649 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1650 return false;
1651 }
1652
1653 if (!i915.enable_psr) {
1654 DRM_DEBUG_KMS("PSR disable by flag\n");
1655 return false;
1656 }
1657
1658 crtc = dig_port->base.base.crtc;
1659 if (crtc == NULL) {
1660 DRM_DEBUG_KMS("crtc not active for PSR\n");
1661 return false;
1662 }
1663
1664 intel_crtc = to_intel_crtc(crtc);
1665 if (!intel_crtc_active(crtc)) {
1666 DRM_DEBUG_KMS("crtc not active for PSR\n");
1667 return false;
1668 }
1669
1670 obj = to_intel_framebuffer(crtc->fb)->obj;
1671 if (obj->tiling_mode != I915_TILING_X ||
1672 obj->fence_reg == I915_FENCE_REG_NONE) {
1673 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1674 return false;
1675 }
1676
1677 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1678 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1679 return false;
1680 }
1681
1682 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1683 S3D_ENABLE) {
1684 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1685 return false;
1686 }
1687
1688 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1689 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1690 return false;
1691 }
1692
1693 dev_priv->psr.source_ok = true;
1694 return true;
1695 }
1696
1697 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1698 {
1699 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1700
1701 if (!intel_edp_psr_match_conditions(intel_dp) ||
1702 intel_edp_is_psr_enabled(dev))
1703 return;
1704
1705 /* Setup PSR once */
1706 intel_edp_psr_setup(intel_dp);
1707
1708 /* Enable PSR on the panel */
1709 intel_edp_psr_enable_sink(intel_dp);
1710
1711 /* Enable PSR on the host */
1712 intel_edp_psr_enable_source(intel_dp);
1713 }
1714
1715 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1716 {
1717 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1718
1719 if (intel_edp_psr_match_conditions(intel_dp) &&
1720 !intel_edp_is_psr_enabled(dev))
1721 intel_edp_psr_do_enable(intel_dp);
1722 }
1723
1724 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1725 {
1726 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728
1729 if (!intel_edp_is_psr_enabled(dev))
1730 return;
1731
1732 I915_WRITE(EDP_PSR_CTL(dev),
1733 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1734
1735 /* Wait till PSR is idle */
1736 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1737 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1738 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1739 }
1740
1741 void intel_edp_psr_update(struct drm_device *dev)
1742 {
1743 struct intel_encoder *encoder;
1744 struct intel_dp *intel_dp = NULL;
1745
1746 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1747 if (encoder->type == INTEL_OUTPUT_EDP) {
1748 intel_dp = enc_to_intel_dp(&encoder->base);
1749
1750 if (!is_edp_psr(dev))
1751 return;
1752
1753 if (!intel_edp_psr_match_conditions(intel_dp))
1754 intel_edp_psr_disable(intel_dp);
1755 else
1756 if (!intel_edp_is_psr_enabled(dev))
1757 intel_edp_psr_do_enable(intel_dp);
1758 }
1759 }
1760
1761 static void intel_disable_dp(struct intel_encoder *encoder)
1762 {
1763 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1764 enum port port = dp_to_dig_port(intel_dp)->port;
1765 struct drm_device *dev = encoder->base.dev;
1766
1767 /* Make sure the panel is off before trying to change the mode. But also
1768 * ensure that we have vdd while we switch off the panel. */
1769 intel_edp_panel_vdd_on(intel_dp);
1770 intel_edp_backlight_off(intel_dp);
1771 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1772 intel_edp_panel_off(intel_dp);
1773
1774 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1775 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1776 intel_dp_link_down(intel_dp);
1777 }
1778
1779 static void intel_post_disable_dp(struct intel_encoder *encoder)
1780 {
1781 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1782 enum port port = dp_to_dig_port(intel_dp)->port;
1783 struct drm_device *dev = encoder->base.dev;
1784
1785 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1786 intel_dp_link_down(intel_dp);
1787 if (!IS_VALLEYVIEW(dev))
1788 ironlake_edp_pll_off(intel_dp);
1789 }
1790 }
1791
1792 static void intel_enable_dp(struct intel_encoder *encoder)
1793 {
1794 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1795 struct drm_device *dev = encoder->base.dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1798
1799 if (WARN_ON(dp_reg & DP_PORT_EN))
1800 return;
1801
1802 intel_edp_panel_vdd_on(intel_dp);
1803 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1804 intel_dp_start_link_train(intel_dp);
1805 intel_edp_panel_on(intel_dp);
1806 edp_panel_vdd_off(intel_dp, true);
1807 intel_dp_complete_link_train(intel_dp);
1808 intel_dp_stop_link_train(intel_dp);
1809 }
1810
1811 static void g4x_enable_dp(struct intel_encoder *encoder)
1812 {
1813 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1814
1815 intel_enable_dp(encoder);
1816 intel_edp_backlight_on(intel_dp);
1817 }
1818
1819 static void vlv_enable_dp(struct intel_encoder *encoder)
1820 {
1821 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1822
1823 intel_edp_backlight_on(intel_dp);
1824 }
1825
1826 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1827 {
1828 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1829 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1830
1831 if (dport->port == PORT_A)
1832 ironlake_edp_pll_on(intel_dp);
1833 }
1834
1835 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1836 {
1837 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1838 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1839 struct drm_device *dev = encoder->base.dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1842 enum dpio_channel port = vlv_dport_to_channel(dport);
1843 int pipe = intel_crtc->pipe;
1844 struct edp_power_seq power_seq;
1845 u32 val;
1846
1847 mutex_lock(&dev_priv->dpio_lock);
1848
1849 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1850 val = 0;
1851 if (pipe)
1852 val |= (1<<21);
1853 else
1854 val &= ~(1<<21);
1855 val |= 0x001000c4;
1856 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1857 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1858 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1859
1860 mutex_unlock(&dev_priv->dpio_lock);
1861
1862 if (is_edp(intel_dp)) {
1863 /* init power sequencer on this pipe and port */
1864 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1865 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1866 &power_seq);
1867 }
1868
1869 intel_enable_dp(encoder);
1870
1871 vlv_wait_port_ready(dev_priv, dport);
1872 }
1873
1874 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1875 {
1876 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1877 struct drm_device *dev = encoder->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_crtc *intel_crtc =
1880 to_intel_crtc(encoder->base.crtc);
1881 enum dpio_channel port = vlv_dport_to_channel(dport);
1882 int pipe = intel_crtc->pipe;
1883
1884 /* Program Tx lane resets to default */
1885 mutex_lock(&dev_priv->dpio_lock);
1886 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1887 DPIO_PCS_TX_LANE2_RESET |
1888 DPIO_PCS_TX_LANE1_RESET);
1889 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1890 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1891 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1892 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1893 DPIO_PCS_CLK_SOFT_RESET);
1894
1895 /* Fix up inter-pair skew failure */
1896 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1897 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1898 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1899 mutex_unlock(&dev_priv->dpio_lock);
1900 }
1901
1902 /*
1903 * Native read with retry for link status and receiver capability reads for
1904 * cases where the sink may still be asleep.
1905 *
1906 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1907 * supposed to retry 3 times per the spec.
1908 */
1909 static ssize_t
1910 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1911 void *buffer, size_t size)
1912 {
1913 ssize_t ret;
1914 int i;
1915
1916 for (i = 0; i < 3; i++) {
1917 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1918 if (ret == size)
1919 return ret;
1920 msleep(1);
1921 }
1922
1923 return ret;
1924 }
1925
1926 /*
1927 * Fetch AUX CH registers 0x202 - 0x207 which contain
1928 * link status information
1929 */
1930 static bool
1931 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1932 {
1933 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1934 DP_LANE0_1_STATUS,
1935 link_status,
1936 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
1937 }
1938
1939 /*
1940 * These are source-specific values; current Intel hardware supports
1941 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1942 */
1943
1944 static uint8_t
1945 intel_dp_voltage_max(struct intel_dp *intel_dp)
1946 {
1947 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1948 enum port port = dp_to_dig_port(intel_dp)->port;
1949
1950 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1951 return DP_TRAIN_VOLTAGE_SWING_1200;
1952 else if (IS_GEN7(dev) && port == PORT_A)
1953 return DP_TRAIN_VOLTAGE_SWING_800;
1954 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1955 return DP_TRAIN_VOLTAGE_SWING_1200;
1956 else
1957 return DP_TRAIN_VOLTAGE_SWING_800;
1958 }
1959
1960 static uint8_t
1961 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1962 {
1963 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1964 enum port port = dp_to_dig_port(intel_dp)->port;
1965
1966 if (IS_BROADWELL(dev)) {
1967 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1968 case DP_TRAIN_VOLTAGE_SWING_400:
1969 case DP_TRAIN_VOLTAGE_SWING_600:
1970 return DP_TRAIN_PRE_EMPHASIS_6;
1971 case DP_TRAIN_VOLTAGE_SWING_800:
1972 return DP_TRAIN_PRE_EMPHASIS_3_5;
1973 case DP_TRAIN_VOLTAGE_SWING_1200:
1974 default:
1975 return DP_TRAIN_PRE_EMPHASIS_0;
1976 }
1977 } else if (IS_HASWELL(dev)) {
1978 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1979 case DP_TRAIN_VOLTAGE_SWING_400:
1980 return DP_TRAIN_PRE_EMPHASIS_9_5;
1981 case DP_TRAIN_VOLTAGE_SWING_600:
1982 return DP_TRAIN_PRE_EMPHASIS_6;
1983 case DP_TRAIN_VOLTAGE_SWING_800:
1984 return DP_TRAIN_PRE_EMPHASIS_3_5;
1985 case DP_TRAIN_VOLTAGE_SWING_1200:
1986 default:
1987 return DP_TRAIN_PRE_EMPHASIS_0;
1988 }
1989 } else if (IS_VALLEYVIEW(dev)) {
1990 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1991 case DP_TRAIN_VOLTAGE_SWING_400:
1992 return DP_TRAIN_PRE_EMPHASIS_9_5;
1993 case DP_TRAIN_VOLTAGE_SWING_600:
1994 return DP_TRAIN_PRE_EMPHASIS_6;
1995 case DP_TRAIN_VOLTAGE_SWING_800:
1996 return DP_TRAIN_PRE_EMPHASIS_3_5;
1997 case DP_TRAIN_VOLTAGE_SWING_1200:
1998 default:
1999 return DP_TRAIN_PRE_EMPHASIS_0;
2000 }
2001 } else if (IS_GEN7(dev) && port == PORT_A) {
2002 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2003 case DP_TRAIN_VOLTAGE_SWING_400:
2004 return DP_TRAIN_PRE_EMPHASIS_6;
2005 case DP_TRAIN_VOLTAGE_SWING_600:
2006 case DP_TRAIN_VOLTAGE_SWING_800:
2007 return DP_TRAIN_PRE_EMPHASIS_3_5;
2008 default:
2009 return DP_TRAIN_PRE_EMPHASIS_0;
2010 }
2011 } else {
2012 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2013 case DP_TRAIN_VOLTAGE_SWING_400:
2014 return DP_TRAIN_PRE_EMPHASIS_6;
2015 case DP_TRAIN_VOLTAGE_SWING_600:
2016 return DP_TRAIN_PRE_EMPHASIS_6;
2017 case DP_TRAIN_VOLTAGE_SWING_800:
2018 return DP_TRAIN_PRE_EMPHASIS_3_5;
2019 case DP_TRAIN_VOLTAGE_SWING_1200:
2020 default:
2021 return DP_TRAIN_PRE_EMPHASIS_0;
2022 }
2023 }
2024 }
2025
2026 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2027 {
2028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2031 struct intel_crtc *intel_crtc =
2032 to_intel_crtc(dport->base.base.crtc);
2033 unsigned long demph_reg_value, preemph_reg_value,
2034 uniqtranscale_reg_value;
2035 uint8_t train_set = intel_dp->train_set[0];
2036 enum dpio_channel port = vlv_dport_to_channel(dport);
2037 int pipe = intel_crtc->pipe;
2038
2039 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2040 case DP_TRAIN_PRE_EMPHASIS_0:
2041 preemph_reg_value = 0x0004000;
2042 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2043 case DP_TRAIN_VOLTAGE_SWING_400:
2044 demph_reg_value = 0x2B405555;
2045 uniqtranscale_reg_value = 0x552AB83A;
2046 break;
2047 case DP_TRAIN_VOLTAGE_SWING_600:
2048 demph_reg_value = 0x2B404040;
2049 uniqtranscale_reg_value = 0x5548B83A;
2050 break;
2051 case DP_TRAIN_VOLTAGE_SWING_800:
2052 demph_reg_value = 0x2B245555;
2053 uniqtranscale_reg_value = 0x5560B83A;
2054 break;
2055 case DP_TRAIN_VOLTAGE_SWING_1200:
2056 demph_reg_value = 0x2B405555;
2057 uniqtranscale_reg_value = 0x5598DA3A;
2058 break;
2059 default:
2060 return 0;
2061 }
2062 break;
2063 case DP_TRAIN_PRE_EMPHASIS_3_5:
2064 preemph_reg_value = 0x0002000;
2065 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2066 case DP_TRAIN_VOLTAGE_SWING_400:
2067 demph_reg_value = 0x2B404040;
2068 uniqtranscale_reg_value = 0x5552B83A;
2069 break;
2070 case DP_TRAIN_VOLTAGE_SWING_600:
2071 demph_reg_value = 0x2B404848;
2072 uniqtranscale_reg_value = 0x5580B83A;
2073 break;
2074 case DP_TRAIN_VOLTAGE_SWING_800:
2075 demph_reg_value = 0x2B404040;
2076 uniqtranscale_reg_value = 0x55ADDA3A;
2077 break;
2078 default:
2079 return 0;
2080 }
2081 break;
2082 case DP_TRAIN_PRE_EMPHASIS_6:
2083 preemph_reg_value = 0x0000000;
2084 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2085 case DP_TRAIN_VOLTAGE_SWING_400:
2086 demph_reg_value = 0x2B305555;
2087 uniqtranscale_reg_value = 0x5570B83A;
2088 break;
2089 case DP_TRAIN_VOLTAGE_SWING_600:
2090 demph_reg_value = 0x2B2B4040;
2091 uniqtranscale_reg_value = 0x55ADDA3A;
2092 break;
2093 default:
2094 return 0;
2095 }
2096 break;
2097 case DP_TRAIN_PRE_EMPHASIS_9_5:
2098 preemph_reg_value = 0x0006000;
2099 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2100 case DP_TRAIN_VOLTAGE_SWING_400:
2101 demph_reg_value = 0x1B405555;
2102 uniqtranscale_reg_value = 0x55ADDA3A;
2103 break;
2104 default:
2105 return 0;
2106 }
2107 break;
2108 default:
2109 return 0;
2110 }
2111
2112 mutex_lock(&dev_priv->dpio_lock);
2113 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2114 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2115 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2116 uniqtranscale_reg_value);
2117 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2118 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2119 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2120 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2121 mutex_unlock(&dev_priv->dpio_lock);
2122
2123 return 0;
2124 }
2125
2126 static void
2127 intel_get_adjust_train(struct intel_dp *intel_dp,
2128 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2129 {
2130 uint8_t v = 0;
2131 uint8_t p = 0;
2132 int lane;
2133 uint8_t voltage_max;
2134 uint8_t preemph_max;
2135
2136 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2137 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2138 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2139
2140 if (this_v > v)
2141 v = this_v;
2142 if (this_p > p)
2143 p = this_p;
2144 }
2145
2146 voltage_max = intel_dp_voltage_max(intel_dp);
2147 if (v >= voltage_max)
2148 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2149
2150 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2151 if (p >= preemph_max)
2152 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2153
2154 for (lane = 0; lane < 4; lane++)
2155 intel_dp->train_set[lane] = v | p;
2156 }
2157
2158 static uint32_t
2159 intel_gen4_signal_levels(uint8_t train_set)
2160 {
2161 uint32_t signal_levels = 0;
2162
2163 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2164 case DP_TRAIN_VOLTAGE_SWING_400:
2165 default:
2166 signal_levels |= DP_VOLTAGE_0_4;
2167 break;
2168 case DP_TRAIN_VOLTAGE_SWING_600:
2169 signal_levels |= DP_VOLTAGE_0_6;
2170 break;
2171 case DP_TRAIN_VOLTAGE_SWING_800:
2172 signal_levels |= DP_VOLTAGE_0_8;
2173 break;
2174 case DP_TRAIN_VOLTAGE_SWING_1200:
2175 signal_levels |= DP_VOLTAGE_1_2;
2176 break;
2177 }
2178 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2179 case DP_TRAIN_PRE_EMPHASIS_0:
2180 default:
2181 signal_levels |= DP_PRE_EMPHASIS_0;
2182 break;
2183 case DP_TRAIN_PRE_EMPHASIS_3_5:
2184 signal_levels |= DP_PRE_EMPHASIS_3_5;
2185 break;
2186 case DP_TRAIN_PRE_EMPHASIS_6:
2187 signal_levels |= DP_PRE_EMPHASIS_6;
2188 break;
2189 case DP_TRAIN_PRE_EMPHASIS_9_5:
2190 signal_levels |= DP_PRE_EMPHASIS_9_5;
2191 break;
2192 }
2193 return signal_levels;
2194 }
2195
2196 /* Gen6's DP voltage swing and pre-emphasis control */
2197 static uint32_t
2198 intel_gen6_edp_signal_levels(uint8_t train_set)
2199 {
2200 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2201 DP_TRAIN_PRE_EMPHASIS_MASK);
2202 switch (signal_levels) {
2203 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2204 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2205 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2206 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2207 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2208 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2209 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2210 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2211 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2212 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2213 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2214 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2215 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2216 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2217 default:
2218 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2219 "0x%x\n", signal_levels);
2220 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2221 }
2222 }
2223
2224 /* Gen7's DP voltage swing and pre-emphasis control */
2225 static uint32_t
2226 intel_gen7_edp_signal_levels(uint8_t train_set)
2227 {
2228 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2229 DP_TRAIN_PRE_EMPHASIS_MASK);
2230 switch (signal_levels) {
2231 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2232 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2233 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2234 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2235 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2236 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2237
2238 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2239 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2240 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2241 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2242
2243 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2244 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2245 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2246 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2247
2248 default:
2249 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2250 "0x%x\n", signal_levels);
2251 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2252 }
2253 }
2254
2255 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2256 static uint32_t
2257 intel_hsw_signal_levels(uint8_t train_set)
2258 {
2259 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2260 DP_TRAIN_PRE_EMPHASIS_MASK);
2261 switch (signal_levels) {
2262 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2263 return DDI_BUF_EMP_400MV_0DB_HSW;
2264 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2265 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2266 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2267 return DDI_BUF_EMP_400MV_6DB_HSW;
2268 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2269 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2270
2271 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2272 return DDI_BUF_EMP_600MV_0DB_HSW;
2273 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2274 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2275 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2276 return DDI_BUF_EMP_600MV_6DB_HSW;
2277
2278 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2279 return DDI_BUF_EMP_800MV_0DB_HSW;
2280 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2281 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2282 default:
2283 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2284 "0x%x\n", signal_levels);
2285 return DDI_BUF_EMP_400MV_0DB_HSW;
2286 }
2287 }
2288
2289 static uint32_t
2290 intel_bdw_signal_levels(uint8_t train_set)
2291 {
2292 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2293 DP_TRAIN_PRE_EMPHASIS_MASK);
2294 switch (signal_levels) {
2295 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2296 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2297 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2298 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2299 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2300 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2301
2302 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2303 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2304 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2305 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2306 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2307 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2308
2309 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2310 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2311 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2312 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2313
2314 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2315 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2316
2317 default:
2318 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2319 "0x%x\n", signal_levels);
2320 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2321 }
2322 }
2323
2324 /* Properly updates "DP" with the correct signal levels. */
2325 static void
2326 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2327 {
2328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2329 enum port port = intel_dig_port->port;
2330 struct drm_device *dev = intel_dig_port->base.base.dev;
2331 uint32_t signal_levels, mask;
2332 uint8_t train_set = intel_dp->train_set[0];
2333
2334 if (IS_BROADWELL(dev)) {
2335 signal_levels = intel_bdw_signal_levels(train_set);
2336 mask = DDI_BUF_EMP_MASK;
2337 } else if (IS_HASWELL(dev)) {
2338 signal_levels = intel_hsw_signal_levels(train_set);
2339 mask = DDI_BUF_EMP_MASK;
2340 } else if (IS_VALLEYVIEW(dev)) {
2341 signal_levels = intel_vlv_signal_levels(intel_dp);
2342 mask = 0;
2343 } else if (IS_GEN7(dev) && port == PORT_A) {
2344 signal_levels = intel_gen7_edp_signal_levels(train_set);
2345 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2346 } else if (IS_GEN6(dev) && port == PORT_A) {
2347 signal_levels = intel_gen6_edp_signal_levels(train_set);
2348 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2349 } else {
2350 signal_levels = intel_gen4_signal_levels(train_set);
2351 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2352 }
2353
2354 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2355
2356 *DP = (*DP & ~mask) | signal_levels;
2357 }
2358
2359 static bool
2360 intel_dp_set_link_train(struct intel_dp *intel_dp,
2361 uint32_t *DP,
2362 uint8_t dp_train_pat)
2363 {
2364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2365 struct drm_device *dev = intel_dig_port->base.base.dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 enum port port = intel_dig_port->port;
2368 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2369 int ret, len;
2370
2371 if (HAS_DDI(dev)) {
2372 uint32_t temp = I915_READ(DP_TP_CTL(port));
2373
2374 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2375 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2376 else
2377 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2378
2379 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2380 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2381 case DP_TRAINING_PATTERN_DISABLE:
2382 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2383
2384 break;
2385 case DP_TRAINING_PATTERN_1:
2386 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2387 break;
2388 case DP_TRAINING_PATTERN_2:
2389 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2390 break;
2391 case DP_TRAINING_PATTERN_3:
2392 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2393 break;
2394 }
2395 I915_WRITE(DP_TP_CTL(port), temp);
2396
2397 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2398 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2399
2400 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2401 case DP_TRAINING_PATTERN_DISABLE:
2402 *DP |= DP_LINK_TRAIN_OFF_CPT;
2403 break;
2404 case DP_TRAINING_PATTERN_1:
2405 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2406 break;
2407 case DP_TRAINING_PATTERN_2:
2408 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2409 break;
2410 case DP_TRAINING_PATTERN_3:
2411 DRM_ERROR("DP training pattern 3 not supported\n");
2412 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2413 break;
2414 }
2415
2416 } else {
2417 *DP &= ~DP_LINK_TRAIN_MASK;
2418
2419 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2420 case DP_TRAINING_PATTERN_DISABLE:
2421 *DP |= DP_LINK_TRAIN_OFF;
2422 break;
2423 case DP_TRAINING_PATTERN_1:
2424 *DP |= DP_LINK_TRAIN_PAT_1;
2425 break;
2426 case DP_TRAINING_PATTERN_2:
2427 *DP |= DP_LINK_TRAIN_PAT_2;
2428 break;
2429 case DP_TRAINING_PATTERN_3:
2430 DRM_ERROR("DP training pattern 3 not supported\n");
2431 *DP |= DP_LINK_TRAIN_PAT_2;
2432 break;
2433 }
2434 }
2435
2436 I915_WRITE(intel_dp->output_reg, *DP);
2437 POSTING_READ(intel_dp->output_reg);
2438
2439 buf[0] = dp_train_pat;
2440 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2441 DP_TRAINING_PATTERN_DISABLE) {
2442 /* don't write DP_TRAINING_LANEx_SET on disable */
2443 len = 1;
2444 } else {
2445 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2446 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2447 len = intel_dp->lane_count + 1;
2448 }
2449
2450 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2451 buf, len);
2452
2453 return ret == len;
2454 }
2455
2456 static bool
2457 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2458 uint8_t dp_train_pat)
2459 {
2460 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2461 intel_dp_set_signal_levels(intel_dp, DP);
2462 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2463 }
2464
2465 static bool
2466 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2467 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2468 {
2469 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2470 struct drm_device *dev = intel_dig_port->base.base.dev;
2471 struct drm_i915_private *dev_priv = dev->dev_private;
2472 int ret;
2473
2474 intel_get_adjust_train(intel_dp, link_status);
2475 intel_dp_set_signal_levels(intel_dp, DP);
2476
2477 I915_WRITE(intel_dp->output_reg, *DP);
2478 POSTING_READ(intel_dp->output_reg);
2479
2480 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2481 intel_dp->train_set, intel_dp->lane_count);
2482
2483 return ret == intel_dp->lane_count;
2484 }
2485
2486 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2487 {
2488 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2489 struct drm_device *dev = intel_dig_port->base.base.dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 enum port port = intel_dig_port->port;
2492 uint32_t val;
2493
2494 if (!HAS_DDI(dev))
2495 return;
2496
2497 val = I915_READ(DP_TP_CTL(port));
2498 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2499 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2500 I915_WRITE(DP_TP_CTL(port), val);
2501
2502 /*
2503 * On PORT_A we can have only eDP in SST mode. There the only reason
2504 * we need to set idle transmission mode is to work around a HW issue
2505 * where we enable the pipe while not in idle link-training mode.
2506 * In this case there is requirement to wait for a minimum number of
2507 * idle patterns to be sent.
2508 */
2509 if (port == PORT_A)
2510 return;
2511
2512 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2513 1))
2514 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2515 }
2516
2517 /* Enable corresponding port and start training pattern 1 */
2518 void
2519 intel_dp_start_link_train(struct intel_dp *intel_dp)
2520 {
2521 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2522 struct drm_device *dev = encoder->dev;
2523 int i;
2524 uint8_t voltage;
2525 int voltage_tries, loop_tries;
2526 uint32_t DP = intel_dp->DP;
2527 uint8_t link_config[2];
2528
2529 if (HAS_DDI(dev))
2530 intel_ddi_prepare_link_retrain(encoder);
2531
2532 /* Write the link configuration data */
2533 link_config[0] = intel_dp->link_bw;
2534 link_config[1] = intel_dp->lane_count;
2535 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2536 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2537 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2538
2539 link_config[0] = 0;
2540 link_config[1] = DP_SET_ANSI_8B10B;
2541 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2542
2543 DP |= DP_PORT_EN;
2544
2545 /* clock recovery */
2546 if (!intel_dp_reset_link_train(intel_dp, &DP,
2547 DP_TRAINING_PATTERN_1 |
2548 DP_LINK_SCRAMBLING_DISABLE)) {
2549 DRM_ERROR("failed to enable link training\n");
2550 return;
2551 }
2552
2553 voltage = 0xff;
2554 voltage_tries = 0;
2555 loop_tries = 0;
2556 for (;;) {
2557 uint8_t link_status[DP_LINK_STATUS_SIZE];
2558
2559 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2560 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2561 DRM_ERROR("failed to get link status\n");
2562 break;
2563 }
2564
2565 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2566 DRM_DEBUG_KMS("clock recovery OK\n");
2567 break;
2568 }
2569
2570 /* Check to see if we've tried the max voltage */
2571 for (i = 0; i < intel_dp->lane_count; i++)
2572 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2573 break;
2574 if (i == intel_dp->lane_count) {
2575 ++loop_tries;
2576 if (loop_tries == 5) {
2577 DRM_ERROR("too many full retries, give up\n");
2578 break;
2579 }
2580 intel_dp_reset_link_train(intel_dp, &DP,
2581 DP_TRAINING_PATTERN_1 |
2582 DP_LINK_SCRAMBLING_DISABLE);
2583 voltage_tries = 0;
2584 continue;
2585 }
2586
2587 /* Check to see if we've tried the same voltage 5 times */
2588 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2589 ++voltage_tries;
2590 if (voltage_tries == 5) {
2591 DRM_ERROR("too many voltage retries, give up\n");
2592 break;
2593 }
2594 } else
2595 voltage_tries = 0;
2596 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2597
2598 /* Update training set as requested by target */
2599 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2600 DRM_ERROR("failed to update link training\n");
2601 break;
2602 }
2603 }
2604
2605 intel_dp->DP = DP;
2606 }
2607
2608 void
2609 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2610 {
2611 bool channel_eq = false;
2612 int tries, cr_tries;
2613 uint32_t DP = intel_dp->DP;
2614 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2615
2616 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2617 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2618 training_pattern = DP_TRAINING_PATTERN_3;
2619
2620 /* channel equalization */
2621 if (!intel_dp_set_link_train(intel_dp, &DP,
2622 training_pattern |
2623 DP_LINK_SCRAMBLING_DISABLE)) {
2624 DRM_ERROR("failed to start channel equalization\n");
2625 return;
2626 }
2627
2628 tries = 0;
2629 cr_tries = 0;
2630 channel_eq = false;
2631 for (;;) {
2632 uint8_t link_status[DP_LINK_STATUS_SIZE];
2633
2634 if (cr_tries > 5) {
2635 DRM_ERROR("failed to train DP, aborting\n");
2636 break;
2637 }
2638
2639 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2640 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2641 DRM_ERROR("failed to get link status\n");
2642 break;
2643 }
2644
2645 /* Make sure clock is still ok */
2646 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2647 intel_dp_start_link_train(intel_dp);
2648 intel_dp_set_link_train(intel_dp, &DP,
2649 training_pattern |
2650 DP_LINK_SCRAMBLING_DISABLE);
2651 cr_tries++;
2652 continue;
2653 }
2654
2655 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2656 channel_eq = true;
2657 break;
2658 }
2659
2660 /* Try 5 times, then try clock recovery if that fails */
2661 if (tries > 5) {
2662 intel_dp_link_down(intel_dp);
2663 intel_dp_start_link_train(intel_dp);
2664 intel_dp_set_link_train(intel_dp, &DP,
2665 training_pattern |
2666 DP_LINK_SCRAMBLING_DISABLE);
2667 tries = 0;
2668 cr_tries++;
2669 continue;
2670 }
2671
2672 /* Update training set as requested by target */
2673 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2674 DRM_ERROR("failed to update link training\n");
2675 break;
2676 }
2677 ++tries;
2678 }
2679
2680 intel_dp_set_idle_link_train(intel_dp);
2681
2682 intel_dp->DP = DP;
2683
2684 if (channel_eq)
2685 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2686
2687 }
2688
2689 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2690 {
2691 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2692 DP_TRAINING_PATTERN_DISABLE);
2693 }
2694
2695 static void
2696 intel_dp_link_down(struct intel_dp *intel_dp)
2697 {
2698 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2699 enum port port = intel_dig_port->port;
2700 struct drm_device *dev = intel_dig_port->base.base.dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 struct intel_crtc *intel_crtc =
2703 to_intel_crtc(intel_dig_port->base.base.crtc);
2704 uint32_t DP = intel_dp->DP;
2705
2706 /*
2707 * DDI code has a strict mode set sequence and we should try to respect
2708 * it, otherwise we might hang the machine in many different ways. So we
2709 * really should be disabling the port only on a complete crtc_disable
2710 * sequence. This function is just called under two conditions on DDI
2711 * code:
2712 * - Link train failed while doing crtc_enable, and on this case we
2713 * really should respect the mode set sequence and wait for a
2714 * crtc_disable.
2715 * - Someone turned the monitor off and intel_dp_check_link_status
2716 * called us. We don't need to disable the whole port on this case, so
2717 * when someone turns the monitor on again,
2718 * intel_ddi_prepare_link_retrain will take care of redoing the link
2719 * train.
2720 */
2721 if (HAS_DDI(dev))
2722 return;
2723
2724 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2725 return;
2726
2727 DRM_DEBUG_KMS("\n");
2728
2729 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2730 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2731 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2732 } else {
2733 DP &= ~DP_LINK_TRAIN_MASK;
2734 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2735 }
2736 POSTING_READ(intel_dp->output_reg);
2737
2738 /* We don't really know why we're doing this */
2739 intel_wait_for_vblank(dev, intel_crtc->pipe);
2740
2741 if (HAS_PCH_IBX(dev) &&
2742 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2743 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2744
2745 /* Hardware workaround: leaving our transcoder select
2746 * set to transcoder B while it's off will prevent the
2747 * corresponding HDMI output on transcoder A.
2748 *
2749 * Combine this with another hardware workaround:
2750 * transcoder select bit can only be cleared while the
2751 * port is enabled.
2752 */
2753 DP &= ~DP_PIPEB_SELECT;
2754 I915_WRITE(intel_dp->output_reg, DP);
2755
2756 /* Changes to enable or select take place the vblank
2757 * after being written.
2758 */
2759 if (WARN_ON(crtc == NULL)) {
2760 /* We should never try to disable a port without a crtc
2761 * attached. For paranoia keep the code around for a
2762 * bit. */
2763 POSTING_READ(intel_dp->output_reg);
2764 msleep(50);
2765 } else
2766 intel_wait_for_vblank(dev, intel_crtc->pipe);
2767 }
2768
2769 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2770 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2771 POSTING_READ(intel_dp->output_reg);
2772 msleep(intel_dp->panel_power_down_delay);
2773 }
2774
2775 static bool
2776 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2777 {
2778 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2779 struct drm_device *dev = dig_port->base.base.dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781
2782 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2783
2784 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2785 sizeof(intel_dp->dpcd)) < 0)
2786 return false; /* aux transfer failed */
2787
2788 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2789 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2790 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2791
2792 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2793 return false; /* DPCD not present */
2794
2795 /* Check if the panel supports PSR */
2796 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2797 if (is_edp(intel_dp)) {
2798 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2799 intel_dp->psr_dpcd,
2800 sizeof(intel_dp->psr_dpcd));
2801 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2802 dev_priv->psr.sink_support = true;
2803 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2804 }
2805 }
2806
2807 /* Training Pattern 3 support */
2808 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2809 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2810 intel_dp->use_tps3 = true;
2811 DRM_DEBUG_KMS("Displayport TPS3 supported");
2812 } else
2813 intel_dp->use_tps3 = false;
2814
2815 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2816 DP_DWN_STRM_PORT_PRESENT))
2817 return true; /* native DP sink */
2818
2819 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2820 return true; /* no per-port downstream info */
2821
2822 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2823 intel_dp->downstream_ports,
2824 DP_MAX_DOWNSTREAM_PORTS) < 0)
2825 return false; /* downstream port status fetch failed */
2826
2827 return true;
2828 }
2829
2830 static void
2831 intel_dp_probe_oui(struct intel_dp *intel_dp)
2832 {
2833 u8 buf[3];
2834
2835 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2836 return;
2837
2838 intel_edp_panel_vdd_on(intel_dp);
2839
2840 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2841 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2842 buf[0], buf[1], buf[2]);
2843
2844 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2845 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2846 buf[0], buf[1], buf[2]);
2847
2848 edp_panel_vdd_off(intel_dp, false);
2849 }
2850
2851 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2852 {
2853 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2854 struct drm_device *dev = intel_dig_port->base.base.dev;
2855 struct intel_crtc *intel_crtc =
2856 to_intel_crtc(intel_dig_port->base.base.crtc);
2857 u8 buf[1];
2858
2859 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2860 return -EAGAIN;
2861
2862 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2863 return -ENOTTY;
2864
2865 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2866 DP_TEST_SINK_START) < 0)
2867 return -EAGAIN;
2868
2869 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2870 intel_wait_for_vblank(dev, intel_crtc->pipe);
2871 intel_wait_for_vblank(dev, intel_crtc->pipe);
2872
2873 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2874 return -EAGAIN;
2875
2876 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2877 return 0;
2878 }
2879
2880 static bool
2881 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2882 {
2883 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2884 DP_DEVICE_SERVICE_IRQ_VECTOR,
2885 sink_irq_vector, 1) == 1;
2886 }
2887
2888 static void
2889 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2890 {
2891 /* NAK by default */
2892 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2893 }
2894
2895 /*
2896 * According to DP spec
2897 * 5.1.2:
2898 * 1. Read DPCD
2899 * 2. Configure link according to Receiver Capabilities
2900 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2901 * 4. Check link status on receipt of hot-plug interrupt
2902 */
2903
2904 void
2905 intel_dp_check_link_status(struct intel_dp *intel_dp)
2906 {
2907 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2908 u8 sink_irq_vector;
2909 u8 link_status[DP_LINK_STATUS_SIZE];
2910
2911 if (!intel_encoder->connectors_active)
2912 return;
2913
2914 if (WARN_ON(!intel_encoder->base.crtc))
2915 return;
2916
2917 /* Try to read receiver status if the link appears to be up */
2918 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2919 return;
2920 }
2921
2922 /* Now read the DPCD to see if it's actually running */
2923 if (!intel_dp_get_dpcd(intel_dp)) {
2924 return;
2925 }
2926
2927 /* Try to read the source of the interrupt */
2928 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2929 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2930 /* Clear interrupt source */
2931 drm_dp_dpcd_writeb(&intel_dp->aux,
2932 DP_DEVICE_SERVICE_IRQ_VECTOR,
2933 sink_irq_vector);
2934
2935 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2936 intel_dp_handle_test_request(intel_dp);
2937 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2938 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2939 }
2940
2941 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2942 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2943 drm_get_encoder_name(&intel_encoder->base));
2944 intel_dp_start_link_train(intel_dp);
2945 intel_dp_complete_link_train(intel_dp);
2946 intel_dp_stop_link_train(intel_dp);
2947 }
2948 }
2949
2950 /* XXX this is probably wrong for multiple downstream ports */
2951 static enum drm_connector_status
2952 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2953 {
2954 uint8_t *dpcd = intel_dp->dpcd;
2955 uint8_t type;
2956
2957 if (!intel_dp_get_dpcd(intel_dp))
2958 return connector_status_disconnected;
2959
2960 /* if there's no downstream port, we're done */
2961 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2962 return connector_status_connected;
2963
2964 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2965 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2966 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2967 uint8_t reg;
2968
2969 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
2970 &reg, 1) < 0)
2971 return connector_status_unknown;
2972
2973 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2974 : connector_status_disconnected;
2975 }
2976
2977 /* If no HPD, poke DDC gently */
2978 if (drm_probe_ddc(&intel_dp->aux.ddc))
2979 return connector_status_connected;
2980
2981 /* Well we tried, say unknown for unreliable port types */
2982 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2983 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2984 if (type == DP_DS_PORT_TYPE_VGA ||
2985 type == DP_DS_PORT_TYPE_NON_EDID)
2986 return connector_status_unknown;
2987 } else {
2988 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2989 DP_DWN_STRM_PORT_TYPE_MASK;
2990 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2991 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2992 return connector_status_unknown;
2993 }
2994
2995 /* Anything else is out of spec, warn and ignore */
2996 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2997 return connector_status_disconnected;
2998 }
2999
3000 static enum drm_connector_status
3001 ironlake_dp_detect(struct intel_dp *intel_dp)
3002 {
3003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3006 enum drm_connector_status status;
3007
3008 /* Can't disconnect eDP, but you can close the lid... */
3009 if (is_edp(intel_dp)) {
3010 status = intel_panel_detect(dev);
3011 if (status == connector_status_unknown)
3012 status = connector_status_connected;
3013 return status;
3014 }
3015
3016 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3017 return connector_status_disconnected;
3018
3019 return intel_dp_detect_dpcd(intel_dp);
3020 }
3021
3022 static enum drm_connector_status
3023 g4x_dp_detect(struct intel_dp *intel_dp)
3024 {
3025 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3026 struct drm_i915_private *dev_priv = dev->dev_private;
3027 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3028 uint32_t bit;
3029
3030 /* Can't disconnect eDP, but you can close the lid... */
3031 if (is_edp(intel_dp)) {
3032 enum drm_connector_status status;
3033
3034 status = intel_panel_detect(dev);
3035 if (status == connector_status_unknown)
3036 status = connector_status_connected;
3037 return status;
3038 }
3039
3040 if (IS_VALLEYVIEW(dev)) {
3041 switch (intel_dig_port->port) {
3042 case PORT_B:
3043 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3044 break;
3045 case PORT_C:
3046 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3047 break;
3048 case PORT_D:
3049 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3050 break;
3051 default:
3052 return connector_status_unknown;
3053 }
3054 } else {
3055 switch (intel_dig_port->port) {
3056 case PORT_B:
3057 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3058 break;
3059 case PORT_C:
3060 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3061 break;
3062 case PORT_D:
3063 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3064 break;
3065 default:
3066 return connector_status_unknown;
3067 }
3068 }
3069
3070 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3071 return connector_status_disconnected;
3072
3073 return intel_dp_detect_dpcd(intel_dp);
3074 }
3075
3076 static struct edid *
3077 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3078 {
3079 struct intel_connector *intel_connector = to_intel_connector(connector);
3080
3081 /* use cached edid if we have one */
3082 if (intel_connector->edid) {
3083 /* invalid edid */
3084 if (IS_ERR(intel_connector->edid))
3085 return NULL;
3086
3087 return drm_edid_duplicate(intel_connector->edid);
3088 }
3089
3090 return drm_get_edid(connector, adapter);
3091 }
3092
3093 static int
3094 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3095 {
3096 struct intel_connector *intel_connector = to_intel_connector(connector);
3097
3098 /* use cached edid if we have one */
3099 if (intel_connector->edid) {
3100 /* invalid edid */
3101 if (IS_ERR(intel_connector->edid))
3102 return 0;
3103
3104 return intel_connector_update_modes(connector,
3105 intel_connector->edid);
3106 }
3107
3108 return intel_ddc_get_modes(connector, adapter);
3109 }
3110
3111 static enum drm_connector_status
3112 intel_dp_detect(struct drm_connector *connector, bool force)
3113 {
3114 struct intel_dp *intel_dp = intel_attached_dp(connector);
3115 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3116 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3117 struct drm_device *dev = connector->dev;
3118 struct drm_i915_private *dev_priv = dev->dev_private;
3119 enum drm_connector_status status;
3120 enum intel_display_power_domain power_domain;
3121 struct edid *edid = NULL;
3122
3123 intel_runtime_pm_get(dev_priv);
3124
3125 power_domain = intel_display_port_power_domain(intel_encoder);
3126 intel_display_power_get(dev_priv, power_domain);
3127
3128 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3129 connector->base.id, drm_get_connector_name(connector));
3130
3131 intel_dp->has_audio = false;
3132
3133 if (HAS_PCH_SPLIT(dev))
3134 status = ironlake_dp_detect(intel_dp);
3135 else
3136 status = g4x_dp_detect(intel_dp);
3137
3138 if (status != connector_status_connected)
3139 goto out;
3140
3141 intel_dp_probe_oui(intel_dp);
3142
3143 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3144 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3145 } else {
3146 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3147 if (edid) {
3148 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3149 kfree(edid);
3150 }
3151 }
3152
3153 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3154 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3155 status = connector_status_connected;
3156
3157 out:
3158 intel_display_power_put(dev_priv, power_domain);
3159
3160 intel_runtime_pm_put(dev_priv);
3161
3162 return status;
3163 }
3164
3165 static int intel_dp_get_modes(struct drm_connector *connector)
3166 {
3167 struct intel_dp *intel_dp = intel_attached_dp(connector);
3168 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3169 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3170 struct intel_connector *intel_connector = to_intel_connector(connector);
3171 struct drm_device *dev = connector->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 enum intel_display_power_domain power_domain;
3174 int ret;
3175
3176 /* We should parse the EDID data and find out if it has an audio sink
3177 */
3178
3179 power_domain = intel_display_port_power_domain(intel_encoder);
3180 intel_display_power_get(dev_priv, power_domain);
3181
3182 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3183 intel_display_power_put(dev_priv, power_domain);
3184 if (ret)
3185 return ret;
3186
3187 /* if eDP has no EDID, fall back to fixed mode */
3188 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3189 struct drm_display_mode *mode;
3190 mode = drm_mode_duplicate(dev,
3191 intel_connector->panel.fixed_mode);
3192 if (mode) {
3193 drm_mode_probed_add(connector, mode);
3194 return 1;
3195 }
3196 }
3197 return 0;
3198 }
3199
3200 static bool
3201 intel_dp_detect_audio(struct drm_connector *connector)
3202 {
3203 struct intel_dp *intel_dp = intel_attached_dp(connector);
3204 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3205 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3206 struct drm_device *dev = connector->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 enum intel_display_power_domain power_domain;
3209 struct edid *edid;
3210 bool has_audio = false;
3211
3212 power_domain = intel_display_port_power_domain(intel_encoder);
3213 intel_display_power_get(dev_priv, power_domain);
3214
3215 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3216 if (edid) {
3217 has_audio = drm_detect_monitor_audio(edid);
3218 kfree(edid);
3219 }
3220
3221 intel_display_power_put(dev_priv, power_domain);
3222
3223 return has_audio;
3224 }
3225
3226 static int
3227 intel_dp_set_property(struct drm_connector *connector,
3228 struct drm_property *property,
3229 uint64_t val)
3230 {
3231 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3232 struct intel_connector *intel_connector = to_intel_connector(connector);
3233 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3234 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3235 int ret;
3236
3237 ret = drm_object_property_set_value(&connector->base, property, val);
3238 if (ret)
3239 return ret;
3240
3241 if (property == dev_priv->force_audio_property) {
3242 int i = val;
3243 bool has_audio;
3244
3245 if (i == intel_dp->force_audio)
3246 return 0;
3247
3248 intel_dp->force_audio = i;
3249
3250 if (i == HDMI_AUDIO_AUTO)
3251 has_audio = intel_dp_detect_audio(connector);
3252 else
3253 has_audio = (i == HDMI_AUDIO_ON);
3254
3255 if (has_audio == intel_dp->has_audio)
3256 return 0;
3257
3258 intel_dp->has_audio = has_audio;
3259 goto done;
3260 }
3261
3262 if (property == dev_priv->broadcast_rgb_property) {
3263 bool old_auto = intel_dp->color_range_auto;
3264 uint32_t old_range = intel_dp->color_range;
3265
3266 switch (val) {
3267 case INTEL_BROADCAST_RGB_AUTO:
3268 intel_dp->color_range_auto = true;
3269 break;
3270 case INTEL_BROADCAST_RGB_FULL:
3271 intel_dp->color_range_auto = false;
3272 intel_dp->color_range = 0;
3273 break;
3274 case INTEL_BROADCAST_RGB_LIMITED:
3275 intel_dp->color_range_auto = false;
3276 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3277 break;
3278 default:
3279 return -EINVAL;
3280 }
3281
3282 if (old_auto == intel_dp->color_range_auto &&
3283 old_range == intel_dp->color_range)
3284 return 0;
3285
3286 goto done;
3287 }
3288
3289 if (is_edp(intel_dp) &&
3290 property == connector->dev->mode_config.scaling_mode_property) {
3291 if (val == DRM_MODE_SCALE_NONE) {
3292 DRM_DEBUG_KMS("no scaling not supported\n");
3293 return -EINVAL;
3294 }
3295
3296 if (intel_connector->panel.fitting_mode == val) {
3297 /* the eDP scaling property is not changed */
3298 return 0;
3299 }
3300 intel_connector->panel.fitting_mode = val;
3301
3302 goto done;
3303 }
3304
3305 return -EINVAL;
3306
3307 done:
3308 if (intel_encoder->base.crtc)
3309 intel_crtc_restore_mode(intel_encoder->base.crtc);
3310
3311 return 0;
3312 }
3313
3314 static void
3315 intel_dp_connector_destroy(struct drm_connector *connector)
3316 {
3317 struct intel_connector *intel_connector = to_intel_connector(connector);
3318
3319 if (!IS_ERR_OR_NULL(intel_connector->edid))
3320 kfree(intel_connector->edid);
3321
3322 /* Can't call is_edp() since the encoder may have been destroyed
3323 * already. */
3324 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3325 intel_panel_fini(&intel_connector->panel);
3326
3327 drm_connector_cleanup(connector);
3328 kfree(connector);
3329 }
3330
3331 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3332 {
3333 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3334 struct intel_dp *intel_dp = &intel_dig_port->dp;
3335 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3336
3337 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3338 drm_encoder_cleanup(encoder);
3339 if (is_edp(intel_dp)) {
3340 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3341 mutex_lock(&dev->mode_config.mutex);
3342 edp_panel_vdd_off_sync(intel_dp);
3343 mutex_unlock(&dev->mode_config.mutex);
3344 }
3345 kfree(intel_dig_port);
3346 }
3347
3348 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3349 .dpms = intel_connector_dpms,
3350 .detect = intel_dp_detect,
3351 .fill_modes = drm_helper_probe_single_connector_modes,
3352 .set_property = intel_dp_set_property,
3353 .destroy = intel_dp_connector_destroy,
3354 };
3355
3356 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3357 .get_modes = intel_dp_get_modes,
3358 .mode_valid = intel_dp_mode_valid,
3359 .best_encoder = intel_best_encoder,
3360 };
3361
3362 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3363 .destroy = intel_dp_encoder_destroy,
3364 };
3365
3366 static void
3367 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3368 {
3369 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3370
3371 intel_dp_check_link_status(intel_dp);
3372 }
3373
3374 /* Return which DP Port should be selected for Transcoder DP control */
3375 int
3376 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3377 {
3378 struct drm_device *dev = crtc->dev;
3379 struct intel_encoder *intel_encoder;
3380 struct intel_dp *intel_dp;
3381
3382 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3383 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3384
3385 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3386 intel_encoder->type == INTEL_OUTPUT_EDP)
3387 return intel_dp->output_reg;
3388 }
3389
3390 return -1;
3391 }
3392
3393 /* check the VBT to see whether the eDP is on DP-D port */
3394 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3395 {
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3397 union child_device_config *p_child;
3398 int i;
3399 static const short port_mapping[] = {
3400 [PORT_B] = PORT_IDPB,
3401 [PORT_C] = PORT_IDPC,
3402 [PORT_D] = PORT_IDPD,
3403 };
3404
3405 if (port == PORT_A)
3406 return true;
3407
3408 if (!dev_priv->vbt.child_dev_num)
3409 return false;
3410
3411 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3412 p_child = dev_priv->vbt.child_dev + i;
3413
3414 if (p_child->common.dvo_port == port_mapping[port] &&
3415 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3416 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3417 return true;
3418 }
3419 return false;
3420 }
3421
3422 static void
3423 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3424 {
3425 struct intel_connector *intel_connector = to_intel_connector(connector);
3426
3427 intel_attach_force_audio_property(connector);
3428 intel_attach_broadcast_rgb_property(connector);
3429 intel_dp->color_range_auto = true;
3430
3431 if (is_edp(intel_dp)) {
3432 drm_mode_create_scaling_mode_property(connector->dev);
3433 drm_object_attach_property(
3434 &connector->base,
3435 connector->dev->mode_config.scaling_mode_property,
3436 DRM_MODE_SCALE_ASPECT);
3437 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3438 }
3439 }
3440
3441 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3442 {
3443 intel_dp->last_power_cycle = jiffies;
3444 intel_dp->last_power_on = jiffies;
3445 intel_dp->last_backlight_off = jiffies;
3446 }
3447
3448 static void
3449 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3450 struct intel_dp *intel_dp,
3451 struct edp_power_seq *out)
3452 {
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct edp_power_seq cur, vbt, spec, final;
3455 u32 pp_on, pp_off, pp_div, pp;
3456 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3457
3458 if (HAS_PCH_SPLIT(dev)) {
3459 pp_ctrl_reg = PCH_PP_CONTROL;
3460 pp_on_reg = PCH_PP_ON_DELAYS;
3461 pp_off_reg = PCH_PP_OFF_DELAYS;
3462 pp_div_reg = PCH_PP_DIVISOR;
3463 } else {
3464 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3465
3466 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3467 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3468 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3469 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3470 }
3471
3472 /* Workaround: Need to write PP_CONTROL with the unlock key as
3473 * the very first thing. */
3474 pp = ironlake_get_pp_control(intel_dp);
3475 I915_WRITE(pp_ctrl_reg, pp);
3476
3477 pp_on = I915_READ(pp_on_reg);
3478 pp_off = I915_READ(pp_off_reg);
3479 pp_div = I915_READ(pp_div_reg);
3480
3481 /* Pull timing values out of registers */
3482 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3483 PANEL_POWER_UP_DELAY_SHIFT;
3484
3485 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3486 PANEL_LIGHT_ON_DELAY_SHIFT;
3487
3488 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3489 PANEL_LIGHT_OFF_DELAY_SHIFT;
3490
3491 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3492 PANEL_POWER_DOWN_DELAY_SHIFT;
3493
3494 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3495 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3496
3497 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3498 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3499
3500 vbt = dev_priv->vbt.edp_pps;
3501
3502 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3503 * our hw here, which are all in 100usec. */
3504 spec.t1_t3 = 210 * 10;
3505 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3506 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3507 spec.t10 = 500 * 10;
3508 /* This one is special and actually in units of 100ms, but zero
3509 * based in the hw (so we need to add 100 ms). But the sw vbt
3510 * table multiplies it with 1000 to make it in units of 100usec,
3511 * too. */
3512 spec.t11_t12 = (510 + 100) * 10;
3513
3514 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3515 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3516
3517 /* Use the max of the register settings and vbt. If both are
3518 * unset, fall back to the spec limits. */
3519 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3520 spec.field : \
3521 max(cur.field, vbt.field))
3522 assign_final(t1_t3);
3523 assign_final(t8);
3524 assign_final(t9);
3525 assign_final(t10);
3526 assign_final(t11_t12);
3527 #undef assign_final
3528
3529 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3530 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3531 intel_dp->backlight_on_delay = get_delay(t8);
3532 intel_dp->backlight_off_delay = get_delay(t9);
3533 intel_dp->panel_power_down_delay = get_delay(t10);
3534 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3535 #undef get_delay
3536
3537 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3538 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3539 intel_dp->panel_power_cycle_delay);
3540
3541 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3542 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3543
3544 if (out)
3545 *out = final;
3546 }
3547
3548 static void
3549 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3550 struct intel_dp *intel_dp,
3551 struct edp_power_seq *seq)
3552 {
3553 struct drm_i915_private *dev_priv = dev->dev_private;
3554 u32 pp_on, pp_off, pp_div, port_sel = 0;
3555 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3556 int pp_on_reg, pp_off_reg, pp_div_reg;
3557
3558 if (HAS_PCH_SPLIT(dev)) {
3559 pp_on_reg = PCH_PP_ON_DELAYS;
3560 pp_off_reg = PCH_PP_OFF_DELAYS;
3561 pp_div_reg = PCH_PP_DIVISOR;
3562 } else {
3563 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3564
3565 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3566 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3567 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3568 }
3569
3570 /*
3571 * And finally store the new values in the power sequencer. The
3572 * backlight delays are set to 1 because we do manual waits on them. For
3573 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3574 * we'll end up waiting for the backlight off delay twice: once when we
3575 * do the manual sleep, and once when we disable the panel and wait for
3576 * the PP_STATUS bit to become zero.
3577 */
3578 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3579 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3580 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3581 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3582 /* Compute the divisor for the pp clock, simply match the Bspec
3583 * formula. */
3584 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3585 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3586 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3587
3588 /* Haswell doesn't have any port selection bits for the panel
3589 * power sequencer any more. */
3590 if (IS_VALLEYVIEW(dev)) {
3591 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3592 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3593 else
3594 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3595 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3596 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3597 port_sel = PANEL_PORT_SELECT_DPA;
3598 else
3599 port_sel = PANEL_PORT_SELECT_DPD;
3600 }
3601
3602 pp_on |= port_sel;
3603
3604 I915_WRITE(pp_on_reg, pp_on);
3605 I915_WRITE(pp_off_reg, pp_off);
3606 I915_WRITE(pp_div_reg, pp_div);
3607
3608 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3609 I915_READ(pp_on_reg),
3610 I915_READ(pp_off_reg),
3611 I915_READ(pp_div_reg));
3612 }
3613
3614 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3615 struct intel_connector *intel_connector,
3616 struct edp_power_seq *power_seq)
3617 {
3618 struct drm_connector *connector = &intel_connector->base;
3619 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3620 struct drm_device *dev = intel_dig_port->base.base.dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct drm_display_mode *fixed_mode = NULL;
3623 bool has_dpcd;
3624 struct drm_display_mode *scan;
3625 struct edid *edid;
3626
3627 if (!is_edp(intel_dp))
3628 return true;
3629
3630 /* Cache DPCD and EDID for edp. */
3631 intel_edp_panel_vdd_on(intel_dp);
3632 has_dpcd = intel_dp_get_dpcd(intel_dp);
3633 edp_panel_vdd_off(intel_dp, false);
3634
3635 if (has_dpcd) {
3636 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3637 dev_priv->no_aux_handshake =
3638 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3639 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3640 } else {
3641 /* if this fails, presume the device is a ghost */
3642 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3643 return false;
3644 }
3645
3646 /* We now know it's not a ghost, init power sequence regs. */
3647 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3648
3649 mutex_lock(&dev->mode_config.mutex);
3650 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
3651 if (edid) {
3652 if (drm_add_edid_modes(connector, edid)) {
3653 drm_mode_connector_update_edid_property(connector,
3654 edid);
3655 drm_edid_to_eld(connector, edid);
3656 } else {
3657 kfree(edid);
3658 edid = ERR_PTR(-EINVAL);
3659 }
3660 } else {
3661 edid = ERR_PTR(-ENOENT);
3662 }
3663 intel_connector->edid = edid;
3664
3665 /* prefer fixed mode from EDID if available */
3666 list_for_each_entry(scan, &connector->probed_modes, head) {
3667 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3668 fixed_mode = drm_mode_duplicate(dev, scan);
3669 break;
3670 }
3671 }
3672
3673 /* fallback to VBT if available for eDP */
3674 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3675 fixed_mode = drm_mode_duplicate(dev,
3676 dev_priv->vbt.lfp_lvds_vbt_mode);
3677 if (fixed_mode)
3678 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3679 }
3680 mutex_unlock(&dev->mode_config.mutex);
3681
3682 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3683 intel_panel_setup_backlight(connector);
3684
3685 return true;
3686 }
3687
3688 bool
3689 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3690 struct intel_connector *intel_connector)
3691 {
3692 struct drm_connector *connector = &intel_connector->base;
3693 struct intel_dp *intel_dp = &intel_dig_port->dp;
3694 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3695 struct drm_device *dev = intel_encoder->base.dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 enum port port = intel_dig_port->port;
3698 struct edp_power_seq power_seq = { 0 };
3699 int type;
3700
3701 /* intel_dp vfuncs */
3702 if (IS_VALLEYVIEW(dev))
3703 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3704 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3705 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3706 else if (HAS_PCH_SPLIT(dev))
3707 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3708 else
3709 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3710
3711 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3712
3713 /* Preserve the current hw state. */
3714 intel_dp->DP = I915_READ(intel_dp->output_reg);
3715 intel_dp->attached_connector = intel_connector;
3716
3717 if (intel_dp_is_edp(dev, port))
3718 type = DRM_MODE_CONNECTOR_eDP;
3719 else
3720 type = DRM_MODE_CONNECTOR_DisplayPort;
3721
3722 /*
3723 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3724 * for DP the encoder type can be set by the caller to
3725 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3726 */
3727 if (type == DRM_MODE_CONNECTOR_eDP)
3728 intel_encoder->type = INTEL_OUTPUT_EDP;
3729
3730 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3731 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3732 port_name(port));
3733
3734 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3735 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3736
3737 connector->interlace_allowed = true;
3738 connector->doublescan_allowed = 0;
3739
3740 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3741 edp_panel_vdd_work);
3742
3743 intel_connector_attach_encoder(intel_connector, intel_encoder);
3744 drm_sysfs_connector_add(connector);
3745
3746 if (HAS_DDI(dev))
3747 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3748 else
3749 intel_connector->get_hw_state = intel_connector_get_hw_state;
3750 intel_connector->unregister = intel_dp_connector_unregister;
3751
3752 /* Set up the hotplug pin. */
3753 switch (port) {
3754 case PORT_A:
3755 intel_encoder->hpd_pin = HPD_PORT_A;
3756 break;
3757 case PORT_B:
3758 intel_encoder->hpd_pin = HPD_PORT_B;
3759 break;
3760 case PORT_C:
3761 intel_encoder->hpd_pin = HPD_PORT_C;
3762 break;
3763 case PORT_D:
3764 intel_encoder->hpd_pin = HPD_PORT_D;
3765 break;
3766 default:
3767 BUG();
3768 }
3769
3770 if (is_edp(intel_dp)) {
3771 intel_dp_init_panel_power_timestamps(intel_dp);
3772 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3773 }
3774
3775 intel_dp_aux_init(intel_dp, intel_connector);
3776
3777 intel_dp->psr_setup_done = false;
3778
3779 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3780 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3781 if (is_edp(intel_dp)) {
3782 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3783 mutex_lock(&dev->mode_config.mutex);
3784 edp_panel_vdd_off_sync(intel_dp);
3785 mutex_unlock(&dev->mode_config.mutex);
3786 }
3787 drm_sysfs_connector_remove(connector);
3788 drm_connector_cleanup(connector);
3789 return false;
3790 }
3791
3792 intel_dp_add_properties(intel_dp, connector);
3793
3794 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3795 * 0xd. Failure to do so will result in spurious interrupts being
3796 * generated on the port when a cable is not attached.
3797 */
3798 if (IS_G4X(dev) && !IS_GM45(dev)) {
3799 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3800 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3801 }
3802
3803 return true;
3804 }
3805
3806 void
3807 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3808 {
3809 struct intel_digital_port *intel_dig_port;
3810 struct intel_encoder *intel_encoder;
3811 struct drm_encoder *encoder;
3812 struct intel_connector *intel_connector;
3813
3814 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3815 if (!intel_dig_port)
3816 return;
3817
3818 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3819 if (!intel_connector) {
3820 kfree(intel_dig_port);
3821 return;
3822 }
3823
3824 intel_encoder = &intel_dig_port->base;
3825 encoder = &intel_encoder->base;
3826
3827 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3828 DRM_MODE_ENCODER_TMDS);
3829
3830 intel_encoder->compute_config = intel_dp_compute_config;
3831 intel_encoder->mode_set = intel_dp_mode_set;
3832 intel_encoder->disable = intel_disable_dp;
3833 intel_encoder->post_disable = intel_post_disable_dp;
3834 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3835 intel_encoder->get_config = intel_dp_get_config;
3836 if (IS_VALLEYVIEW(dev)) {
3837 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3838 intel_encoder->pre_enable = vlv_pre_enable_dp;
3839 intel_encoder->enable = vlv_enable_dp;
3840 } else {
3841 intel_encoder->pre_enable = g4x_pre_enable_dp;
3842 intel_encoder->enable = g4x_enable_dp;
3843 }
3844
3845 intel_dig_port->port = port;
3846 intel_dig_port->dp.output_reg = output_reg;
3847
3848 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3849 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3850 intel_encoder->cloneable = 0;
3851 intel_encoder->hot_plug = intel_dp_hot_plug;
3852
3853 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3854 drm_encoder_cleanup(encoder);
3855 kfree(intel_dig_port);
3856 kfree(intel_connector);
3857 }
3858 }
Linux kernel - Deliverables
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