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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 /**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63 static bool is_pch_edp(struct intel_dp *intel_dp)
64 {
65 return intel_dp->is_pch_edp;
66 }
67
68 /**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74 static bool is_cpu_edp(struct intel_dp *intel_dp)
75 {
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77 }
78
79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
80 {
81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
84 }
85
86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87 {
88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
89 }
90
91 /**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99 {
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108 }
109
110 static void intel_dp_link_down(struct intel_dp *intel_dp);
111
112 static int
113 intel_dp_max_link_bw(struct intel_dp *intel_dp)
114 {
115 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
116
117 switch (max_link_bw) {
118 case DP_LINK_BW_1_62:
119 case DP_LINK_BW_2_7:
120 break;
121 default:
122 max_link_bw = DP_LINK_BW_1_62;
123 break;
124 }
125 return max_link_bw;
126 }
127
128 /*
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
131 *
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
133 *
134 * 270000 * 1 * 8 / 10 == 216000
135 *
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
140 *
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
143 */
144
145 static int
146 intel_dp_link_required(int pixel_clock, int bpp)
147 {
148 return (pixel_clock * bpp + 9) / 10;
149 }
150
151 static int
152 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
153 {
154 return (max_link_clock * max_lanes * 8) / 10;
155 }
156
157 static int
158 intel_dp_mode_valid(struct drm_connector *connector,
159 struct drm_display_mode *mode)
160 {
161 struct intel_dp *intel_dp = intel_attached_dp(connector);
162 struct intel_connector *intel_connector = to_intel_connector(connector);
163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
166
167 if (is_edp(intel_dp) && fixed_mode) {
168 if (mode->hdisplay > fixed_mode->hdisplay)
169 return MODE_PANEL;
170
171 if (mode->vdisplay > fixed_mode->vdisplay)
172 return MODE_PANEL;
173
174 target_clock = fixed_mode->clock;
175 }
176
177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
179
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
182
183 if (mode_rate > max_rate)
184 return MODE_CLOCK_HIGH;
185
186 if (mode->clock < 10000)
187 return MODE_CLOCK_LOW;
188
189 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
190 return MODE_H_ILLEGAL;
191
192 return MODE_OK;
193 }
194
195 static uint32_t
196 pack_aux(uint8_t *src, int src_bytes)
197 {
198 int i;
199 uint32_t v = 0;
200
201 if (src_bytes > 4)
202 src_bytes = 4;
203 for (i = 0; i < src_bytes; i++)
204 v |= ((uint32_t) src[i]) << ((3-i) * 8);
205 return v;
206 }
207
208 static void
209 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
210 {
211 int i;
212 if (dst_bytes > 4)
213 dst_bytes = 4;
214 for (i = 0; i < dst_bytes; i++)
215 dst[i] = src >> ((3-i) * 8);
216 }
217
218 /* hrawclock is 1/4 the FSB frequency */
219 static int
220 intel_hrawclk(struct drm_device *dev)
221 {
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 uint32_t clkcfg;
224
225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev))
227 return 200;
228
229 clkcfg = I915_READ(CLKCFG);
230 switch (clkcfg & CLKCFG_FSB_MASK) {
231 case CLKCFG_FSB_400:
232 return 100;
233 case CLKCFG_FSB_533:
234 return 133;
235 case CLKCFG_FSB_667:
236 return 166;
237 case CLKCFG_FSB_800:
238 return 200;
239 case CLKCFG_FSB_1067:
240 return 266;
241 case CLKCFG_FSB_1333:
242 return 333;
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600:
245 case CLKCFG_FSB_1600_ALT:
246 return 400;
247 default:
248 return 133;
249 }
250 }
251
252 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
253 {
254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 u32 pp_stat_reg;
257
258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
260 }
261
262 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
263 {
264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 u32 pp_ctrl_reg;
267
268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
270 }
271
272 static void
273 intel_dp_check_edp(struct intel_dp *intel_dp)
274 {
275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
276 struct drm_i915_private *dev_priv = dev->dev_private;
277 u32 pp_stat_reg, pp_ctrl_reg;
278
279 if (!is_edp(intel_dp))
280 return;
281
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
284
285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
288 I915_READ(pp_stat_reg),
289 I915_READ(pp_ctrl_reg));
290 }
291 }
292
293 static uint32_t
294 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
295 {
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
300 uint32_t status;
301 bool done;
302
303 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
304 if (has_aux_irq)
305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10));
307 else
308 done = wait_for_atomic(C, 10) == 0;
309 if (!done)
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
311 has_aux_irq);
312 #undef C
313
314 return status;
315 }
316
317 static int
318 intel_dp_aux_ch(struct intel_dp *intel_dp,
319 uint8_t *send, int send_bytes,
320 uint8_t *recv, int recv_size)
321 {
322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
326 uint32_t ch_data = ch_ctl + 4;
327 int i, ret, recv_bytes;
328 uint32_t status;
329 uint32_t aux_clock_divider;
330 int try, precharge;
331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
332
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
335 * deep sleep states.
336 */
337 pm_qos_update_request(&dev_priv->pm_qos, 0);
338
339 intel_dp_check_edp(intel_dp);
340 /* The clock divider is based off the hrawclk,
341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
343 *
344 * Note that PCH attached eDP panels should use a 125MHz input
345 * clock divider.
346 */
347 if (is_cpu_edp(intel_dp)) {
348 if (HAS_DDI(dev))
349 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
350 else if (IS_VALLEYVIEW(dev))
351 aux_clock_divider = 100;
352 else if (IS_GEN6(dev) || IS_GEN7(dev))
353 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
354 else
355 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
356 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider = 74;
359 } else if (HAS_PCH_SPLIT(dev)) {
360 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
361 } else {
362 aux_clock_divider = intel_hrawclk(dev) / 2;
363 }
364
365 if (IS_GEN6(dev))
366 precharge = 3;
367 else
368 precharge = 5;
369
370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
372 status = I915_READ_NOTRACE(ch_ctl);
373 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
374 break;
375 msleep(1);
376 }
377
378 if (try == 3) {
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
380 I915_READ(ch_ctl));
381 ret = -EBUSY;
382 goto out;
383 }
384
385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
388 for (i = 0; i < send_bytes; i += 4)
389 I915_WRITE(ch_data + i,
390 pack_aux(send + i, send_bytes - i));
391
392 /* Send the command and wait for it to complete */
393 I915_WRITE(ch_ctl,
394 DP_AUX_CH_CTL_SEND_BUSY |
395 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
396 DP_AUX_CH_CTL_TIME_OUT_400us |
397 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
398 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
399 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
400 DP_AUX_CH_CTL_DONE |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR |
402 DP_AUX_CH_CTL_RECEIVE_ERROR);
403
404 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
405
406 /* Clear done status and any errors */
407 I915_WRITE(ch_ctl,
408 status |
409 DP_AUX_CH_CTL_DONE |
410 DP_AUX_CH_CTL_TIME_OUT_ERROR |
411 DP_AUX_CH_CTL_RECEIVE_ERROR);
412
413 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR))
415 continue;
416 if (status & DP_AUX_CH_CTL_DONE)
417 break;
418 }
419
420 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
422 ret = -EBUSY;
423 goto out;
424 }
425
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
428 */
429 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
431 ret = -EIO;
432 goto out;
433 }
434
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
437 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
439 ret = -ETIMEDOUT;
440 goto out;
441 }
442
443 /* Unload any bytes sent back from the other side */
444 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
446 if (recv_bytes > recv_size)
447 recv_bytes = recv_size;
448
449 for (i = 0; i < recv_bytes; i += 4)
450 unpack_aux(I915_READ(ch_data + i),
451 recv + i, recv_bytes - i);
452
453 ret = recv_bytes;
454 out:
455 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
456
457 return ret;
458 }
459
460 /* Write data to the aux channel in native mode */
461 static int
462 intel_dp_aux_native_write(struct intel_dp *intel_dp,
463 uint16_t address, uint8_t *send, int send_bytes)
464 {
465 int ret;
466 uint8_t msg[20];
467 int msg_bytes;
468 uint8_t ack;
469
470 intel_dp_check_edp(intel_dp);
471 if (send_bytes > 16)
472 return -1;
473 msg[0] = AUX_NATIVE_WRITE << 4;
474 msg[1] = address >> 8;
475 msg[2] = address & 0xff;
476 msg[3] = send_bytes - 1;
477 memcpy(&msg[4], send, send_bytes);
478 msg_bytes = send_bytes + 4;
479 for (;;) {
480 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
481 if (ret < 0)
482 return ret;
483 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
484 break;
485 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
486 udelay(100);
487 else
488 return -EIO;
489 }
490 return send_bytes;
491 }
492
493 /* Write a single byte to the aux channel in native mode */
494 static int
495 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
496 uint16_t address, uint8_t byte)
497 {
498 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
499 }
500
501 /* read bytes from a native aux channel */
502 static int
503 intel_dp_aux_native_read(struct intel_dp *intel_dp,
504 uint16_t address, uint8_t *recv, int recv_bytes)
505 {
506 uint8_t msg[4];
507 int msg_bytes;
508 uint8_t reply[20];
509 int reply_bytes;
510 uint8_t ack;
511 int ret;
512
513 intel_dp_check_edp(intel_dp);
514 msg[0] = AUX_NATIVE_READ << 4;
515 msg[1] = address >> 8;
516 msg[2] = address & 0xff;
517 msg[3] = recv_bytes - 1;
518
519 msg_bytes = 4;
520 reply_bytes = recv_bytes + 1;
521
522 for (;;) {
523 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
524 reply, reply_bytes);
525 if (ret == 0)
526 return -EPROTO;
527 if (ret < 0)
528 return ret;
529 ack = reply[0];
530 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
531 memcpy(recv, reply + 1, ret - 1);
532 return ret - 1;
533 }
534 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
535 udelay(100);
536 else
537 return -EIO;
538 }
539 }
540
541 static int
542 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
543 uint8_t write_byte, uint8_t *read_byte)
544 {
545 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
546 struct intel_dp *intel_dp = container_of(adapter,
547 struct intel_dp,
548 adapter);
549 uint16_t address = algo_data->address;
550 uint8_t msg[5];
551 uint8_t reply[2];
552 unsigned retry;
553 int msg_bytes;
554 int reply_bytes;
555 int ret;
556
557 intel_dp_check_edp(intel_dp);
558 /* Set up the command byte */
559 if (mode & MODE_I2C_READ)
560 msg[0] = AUX_I2C_READ << 4;
561 else
562 msg[0] = AUX_I2C_WRITE << 4;
563
564 if (!(mode & MODE_I2C_STOP))
565 msg[0] |= AUX_I2C_MOT << 4;
566
567 msg[1] = address >> 8;
568 msg[2] = address;
569
570 switch (mode) {
571 case MODE_I2C_WRITE:
572 msg[3] = 0;
573 msg[4] = write_byte;
574 msg_bytes = 5;
575 reply_bytes = 1;
576 break;
577 case MODE_I2C_READ:
578 msg[3] = 0;
579 msg_bytes = 4;
580 reply_bytes = 2;
581 break;
582 default:
583 msg_bytes = 3;
584 reply_bytes = 1;
585 break;
586 }
587
588 for (retry = 0; retry < 5; retry++) {
589 ret = intel_dp_aux_ch(intel_dp,
590 msg, msg_bytes,
591 reply, reply_bytes);
592 if (ret < 0) {
593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
594 return ret;
595 }
596
597 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
598 case AUX_NATIVE_REPLY_ACK:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
601 */
602 break;
603 case AUX_NATIVE_REPLY_NACK:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
605 return -EREMOTEIO;
606 case AUX_NATIVE_REPLY_DEFER:
607 udelay(100);
608 continue;
609 default:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
611 reply[0]);
612 return -EREMOTEIO;
613 }
614
615 switch (reply[0] & AUX_I2C_REPLY_MASK) {
616 case AUX_I2C_REPLY_ACK:
617 if (mode == MODE_I2C_READ) {
618 *read_byte = reply[1];
619 }
620 return reply_bytes - 1;
621 case AUX_I2C_REPLY_NACK:
622 DRM_DEBUG_KMS("aux_i2c nack\n");
623 return -EREMOTEIO;
624 case AUX_I2C_REPLY_DEFER:
625 DRM_DEBUG_KMS("aux_i2c defer\n");
626 udelay(100);
627 break;
628 default:
629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
630 return -EREMOTEIO;
631 }
632 }
633
634 DRM_ERROR("too many retries, giving up\n");
635 return -EREMOTEIO;
636 }
637
638 static int
639 intel_dp_i2c_init(struct intel_dp *intel_dp,
640 struct intel_connector *intel_connector, const char *name)
641 {
642 int ret;
643
644 DRM_DEBUG_KMS("i2c_init %s\n", name);
645 intel_dp->algo.running = false;
646 intel_dp->algo.address = 0;
647 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
648
649 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
650 intel_dp->adapter.owner = THIS_MODULE;
651 intel_dp->adapter.class = I2C_CLASS_DDC;
652 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
653 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
654 intel_dp->adapter.algo_data = &intel_dp->algo;
655 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
656
657 ironlake_edp_panel_vdd_on(intel_dp);
658 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
659 ironlake_edp_panel_vdd_off(intel_dp, false);
660 return ret;
661 }
662
663 static void
664 intel_dp_set_clock(struct intel_encoder *encoder,
665 struct intel_crtc_config *pipe_config, int link_bw)
666 {
667 struct drm_device *dev = encoder->base.dev;
668
669 if (IS_G4X(dev)) {
670 if (link_bw == DP_LINK_BW_1_62) {
671 pipe_config->dpll.p1 = 2;
672 pipe_config->dpll.p2 = 10;
673 pipe_config->dpll.n = 2;
674 pipe_config->dpll.m1 = 23;
675 pipe_config->dpll.m2 = 8;
676 } else {
677 pipe_config->dpll.p1 = 1;
678 pipe_config->dpll.p2 = 10;
679 pipe_config->dpll.n = 1;
680 pipe_config->dpll.m1 = 14;
681 pipe_config->dpll.m2 = 2;
682 }
683 pipe_config->clock_set = true;
684 } else if (IS_HASWELL(dev)) {
685 /* Haswell has special-purpose DP DDI clocks. */
686 } else if (HAS_PCH_SPLIT(dev)) {
687 if (link_bw == DP_LINK_BW_1_62) {
688 pipe_config->dpll.n = 1;
689 pipe_config->dpll.p1 = 2;
690 pipe_config->dpll.p2 = 10;
691 pipe_config->dpll.m1 = 12;
692 pipe_config->dpll.m2 = 9;
693 } else {
694 pipe_config->dpll.n = 2;
695 pipe_config->dpll.p1 = 1;
696 pipe_config->dpll.p2 = 10;
697 pipe_config->dpll.m1 = 14;
698 pipe_config->dpll.m2 = 8;
699 }
700 pipe_config->clock_set = true;
701 } else if (IS_VALLEYVIEW(dev)) {
702 /* FIXME: Need to figure out optimized DP clocks for vlv. */
703 }
704 }
705
706 bool
707 intel_dp_compute_config(struct intel_encoder *encoder,
708 struct intel_crtc_config *pipe_config)
709 {
710 struct drm_device *dev = encoder->base.dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
712 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
713 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
714 struct intel_crtc *intel_crtc = encoder->new_crtc;
715 struct intel_connector *intel_connector = intel_dp->attached_connector;
716 int lane_count, clock;
717 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
718 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
719 int bpp, mode_rate;
720 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
721 int target_clock, link_avail, link_clock;
722
723 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
724 pipe_config->has_pch_encoder = true;
725
726 pipe_config->has_dp_encoder = true;
727
728 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
729 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
730 adjusted_mode);
731 if (!HAS_PCH_SPLIT(dev))
732 intel_gmch_panel_fitting(intel_crtc, pipe_config,
733 intel_connector->panel.fitting_mode);
734 else
735 intel_pch_panel_fitting(intel_crtc, pipe_config,
736 intel_connector->panel.fitting_mode);
737 }
738 /* We need to take the panel's fixed mode into account. */
739 target_clock = adjusted_mode->clock;
740
741 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
742 return false;
743
744 DRM_DEBUG_KMS("DP link computation with max lane count %i "
745 "max bw %02x pixel clock %iKHz\n",
746 max_lane_count, bws[max_clock], adjusted_mode->clock);
747
748 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
749 * bpc in between. */
750 bpp = pipe_config->pipe_bpp;
751
752 /*
753 * eDP panels are really fickle, try to enfore the bpp the firmware
754 * recomments. This means we'll up-dither 16bpp framebuffers on
755 * high-depth panels.
756 */
757 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
758 DRM_DEBUG_KMS("forcing bpp for eDP panel to BIOS-provided %i\n",
759 dev_priv->edp.bpp);
760 bpp = dev_priv->edp.bpp;
761 }
762
763 for (; bpp >= 6*3; bpp -= 2*3) {
764 mode_rate = intel_dp_link_required(target_clock, bpp);
765
766 for (clock = 0; clock <= max_clock; clock++) {
767 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
768 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
769 link_avail = intel_dp_max_data_rate(link_clock,
770 lane_count);
771
772 if (mode_rate <= link_avail) {
773 goto found;
774 }
775 }
776 }
777 }
778
779 return false;
780
781 found:
782 if (intel_dp->color_range_auto) {
783 /*
784 * See:
785 * CEA-861-E - 5.1 Default Encoding Parameters
786 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
787 */
788 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
789 intel_dp->color_range = DP_COLOR_RANGE_16_235;
790 else
791 intel_dp->color_range = 0;
792 }
793
794 if (intel_dp->color_range)
795 pipe_config->limited_color_range = true;
796
797 intel_dp->link_bw = bws[clock];
798 intel_dp->lane_count = lane_count;
799 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
800 pipe_config->pixel_target_clock = target_clock;
801
802 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
803 intel_dp->link_bw, intel_dp->lane_count,
804 adjusted_mode->clock, bpp);
805 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
806 mode_rate, link_avail);
807
808 intel_link_compute_m_n(bpp, lane_count,
809 target_clock, adjusted_mode->clock,
810 &pipe_config->dp_m_n);
811
812 pipe_config->pipe_bpp = bpp;
813
814 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
815
816 return true;
817 }
818
819 void intel_dp_init_link_config(struct intel_dp *intel_dp)
820 {
821 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
822 intel_dp->link_configuration[0] = intel_dp->link_bw;
823 intel_dp->link_configuration[1] = intel_dp->lane_count;
824 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
825 /*
826 * Check for DPCD version > 1.1 and enhanced framing support
827 */
828 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
829 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
830 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
831 }
832 }
833
834 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
835 {
836 struct drm_device *dev = crtc->dev;
837 struct drm_i915_private *dev_priv = dev->dev_private;
838 u32 dpa_ctl;
839
840 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
841 dpa_ctl = I915_READ(DP_A);
842 dpa_ctl &= ~DP_PLL_FREQ_MASK;
843
844 if (clock < 200000) {
845 /* For a long time we've carried around a ILK-DevA w/a for the
846 * 160MHz clock. If we're really unlucky, it's still required.
847 */
848 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
849 dpa_ctl |= DP_PLL_FREQ_160MHZ;
850 } else {
851 dpa_ctl |= DP_PLL_FREQ_270MHZ;
852 }
853
854 I915_WRITE(DP_A, dpa_ctl);
855
856 POSTING_READ(DP_A);
857 udelay(500);
858 }
859
860 static void
861 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
862 struct drm_display_mode *adjusted_mode)
863 {
864 struct drm_device *dev = encoder->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private;
866 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
867 struct drm_crtc *crtc = encoder->crtc;
868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
869
870 /*
871 * There are four kinds of DP registers:
872 *
873 * IBX PCH
874 * SNB CPU
875 * IVB CPU
876 * CPT PCH
877 *
878 * IBX PCH and CPU are the same for almost everything,
879 * except that the CPU DP PLL is configured in this
880 * register
881 *
882 * CPT PCH is quite different, having many bits moved
883 * to the TRANS_DP_CTL register instead. That
884 * configuration happens (oddly) in ironlake_pch_enable
885 */
886
887 /* Preserve the BIOS-computed detected bit. This is
888 * supposed to be read-only.
889 */
890 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
891
892 /* Handle DP bits in common between all three register formats */
893 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
894
895 switch (intel_dp->lane_count) {
896 case 1:
897 intel_dp->DP |= DP_PORT_WIDTH_1;
898 break;
899 case 2:
900 intel_dp->DP |= DP_PORT_WIDTH_2;
901 break;
902 case 4:
903 intel_dp->DP |= DP_PORT_WIDTH_4;
904 break;
905 }
906 if (intel_dp->has_audio) {
907 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
908 pipe_name(intel_crtc->pipe));
909 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
910 intel_write_eld(encoder, adjusted_mode);
911 }
912
913 intel_dp_init_link_config(intel_dp);
914
915 /* Split out the IBX/CPU vs CPT settings */
916
917 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
918 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
919 intel_dp->DP |= DP_SYNC_HS_HIGH;
920 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
921 intel_dp->DP |= DP_SYNC_VS_HIGH;
922 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
923
924 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
925 intel_dp->DP |= DP_ENHANCED_FRAMING;
926
927 intel_dp->DP |= intel_crtc->pipe << 29;
928
929 /* don't miss out required setting for eDP */
930 if (adjusted_mode->clock < 200000)
931 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
932 else
933 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
934 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
935 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
936 intel_dp->DP |= intel_dp->color_range;
937
938 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
939 intel_dp->DP |= DP_SYNC_HS_HIGH;
940 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
941 intel_dp->DP |= DP_SYNC_VS_HIGH;
942 intel_dp->DP |= DP_LINK_TRAIN_OFF;
943
944 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
945 intel_dp->DP |= DP_ENHANCED_FRAMING;
946
947 if (intel_crtc->pipe == 1)
948 intel_dp->DP |= DP_PIPEB_SELECT;
949
950 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
951 /* don't miss out required setting for eDP */
952 if (adjusted_mode->clock < 200000)
953 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
954 else
955 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
956 }
957 } else {
958 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
959 }
960
961 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
962 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
963 }
964
965 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
966 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
967
968 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
969 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
970
971 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
972 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
973
974 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
975 u32 mask,
976 u32 value)
977 {
978 struct drm_device *dev = intel_dp_to_dev(intel_dp);
979 struct drm_i915_private *dev_priv = dev->dev_private;
980 u32 pp_stat_reg, pp_ctrl_reg;
981
982 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
983 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
984
985 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
986 mask, value,
987 I915_READ(pp_stat_reg),
988 I915_READ(pp_ctrl_reg));
989
990 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
991 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
992 I915_READ(pp_stat_reg),
993 I915_READ(pp_ctrl_reg));
994 }
995 }
996
997 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
998 {
999 DRM_DEBUG_KMS("Wait for panel power on\n");
1000 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1001 }
1002
1003 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1004 {
1005 DRM_DEBUG_KMS("Wait for panel power off time\n");
1006 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1007 }
1008
1009 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1010 {
1011 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1012 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1013 }
1014
1015
1016 /* Read the current pp_control value, unlocking the register if it
1017 * is locked
1018 */
1019
1020 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1021 {
1022 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024 u32 control;
1025 u32 pp_ctrl_reg;
1026
1027 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1028 control = I915_READ(pp_ctrl_reg);
1029
1030 control &= ~PANEL_UNLOCK_MASK;
1031 control |= PANEL_UNLOCK_REGS;
1032 return control;
1033 }
1034
1035 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1036 {
1037 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 u32 pp;
1040 u32 pp_stat_reg, pp_ctrl_reg;
1041
1042 if (!is_edp(intel_dp))
1043 return;
1044 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1045
1046 WARN(intel_dp->want_panel_vdd,
1047 "eDP VDD already requested on\n");
1048
1049 intel_dp->want_panel_vdd = true;
1050
1051 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1052 DRM_DEBUG_KMS("eDP VDD already on\n");
1053 return;
1054 }
1055
1056 if (!ironlake_edp_have_panel_power(intel_dp))
1057 ironlake_wait_panel_power_cycle(intel_dp);
1058
1059 pp = ironlake_get_pp_control(intel_dp);
1060 pp |= EDP_FORCE_VDD;
1061
1062 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1063 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1064
1065 I915_WRITE(pp_ctrl_reg, pp);
1066 POSTING_READ(pp_ctrl_reg);
1067 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1068 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1069 /*
1070 * If the panel wasn't on, delay before accessing aux channel
1071 */
1072 if (!ironlake_edp_have_panel_power(intel_dp)) {
1073 DRM_DEBUG_KMS("eDP was not running\n");
1074 msleep(intel_dp->panel_power_up_delay);
1075 }
1076 }
1077
1078 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1079 {
1080 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 u32 pp;
1083 u32 pp_stat_reg, pp_ctrl_reg;
1084
1085 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1086
1087 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1088 pp = ironlake_get_pp_control(intel_dp);
1089 pp &= ~EDP_FORCE_VDD;
1090
1091 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1092 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1093
1094 I915_WRITE(pp_ctrl_reg, pp);
1095 POSTING_READ(pp_ctrl_reg);
1096
1097 /* Make sure sequencer is idle before allowing subsequent activity */
1098 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1099 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1100 msleep(intel_dp->panel_power_down_delay);
1101 }
1102 }
1103
1104 static void ironlake_panel_vdd_work(struct work_struct *__work)
1105 {
1106 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1107 struct intel_dp, panel_vdd_work);
1108 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1109
1110 mutex_lock(&dev->mode_config.mutex);
1111 ironlake_panel_vdd_off_sync(intel_dp);
1112 mutex_unlock(&dev->mode_config.mutex);
1113 }
1114
1115 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1116 {
1117 if (!is_edp(intel_dp))
1118 return;
1119
1120 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1121 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1122
1123 intel_dp->want_panel_vdd = false;
1124
1125 if (sync) {
1126 ironlake_panel_vdd_off_sync(intel_dp);
1127 } else {
1128 /*
1129 * Queue the timer to fire a long
1130 * time from now (relative to the power down delay)
1131 * to keep the panel power up across a sequence of operations
1132 */
1133 schedule_delayed_work(&intel_dp->panel_vdd_work,
1134 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1135 }
1136 }
1137
1138 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1139 {
1140 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1141 struct drm_i915_private *dev_priv = dev->dev_private;
1142 u32 pp;
1143 u32 pp_ctrl_reg;
1144
1145 if (!is_edp(intel_dp))
1146 return;
1147
1148 DRM_DEBUG_KMS("Turn eDP power on\n");
1149
1150 if (ironlake_edp_have_panel_power(intel_dp)) {
1151 DRM_DEBUG_KMS("eDP power already on\n");
1152 return;
1153 }
1154
1155 ironlake_wait_panel_power_cycle(intel_dp);
1156
1157 pp = ironlake_get_pp_control(intel_dp);
1158 if (IS_GEN5(dev)) {
1159 /* ILK workaround: disable reset around power sequence */
1160 pp &= ~PANEL_POWER_RESET;
1161 I915_WRITE(PCH_PP_CONTROL, pp);
1162 POSTING_READ(PCH_PP_CONTROL);
1163 }
1164
1165 pp |= POWER_TARGET_ON;
1166 if (!IS_GEN5(dev))
1167 pp |= PANEL_POWER_RESET;
1168
1169 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1170
1171 I915_WRITE(pp_ctrl_reg, pp);
1172 POSTING_READ(pp_ctrl_reg);
1173
1174 ironlake_wait_panel_on(intel_dp);
1175
1176 if (IS_GEN5(dev)) {
1177 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1178 I915_WRITE(PCH_PP_CONTROL, pp);
1179 POSTING_READ(PCH_PP_CONTROL);
1180 }
1181 }
1182
1183 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1184 {
1185 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 u32 pp;
1188 u32 pp_ctrl_reg;
1189
1190 if (!is_edp(intel_dp))
1191 return;
1192
1193 DRM_DEBUG_KMS("Turn eDP power off\n");
1194
1195 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1196
1197 pp = ironlake_get_pp_control(intel_dp);
1198 /* We need to switch off panel power _and_ force vdd, for otherwise some
1199 * panels get very unhappy and cease to work. */
1200 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1201
1202 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1203
1204 I915_WRITE(pp_ctrl_reg, pp);
1205 POSTING_READ(pp_ctrl_reg);
1206
1207 intel_dp->want_panel_vdd = false;
1208
1209 ironlake_wait_panel_off(intel_dp);
1210 }
1211
1212 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1213 {
1214 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1215 struct drm_device *dev = intel_dig_port->base.base.dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1218 u32 pp;
1219 u32 pp_ctrl_reg;
1220
1221 if (!is_edp(intel_dp))
1222 return;
1223
1224 DRM_DEBUG_KMS("\n");
1225 /*
1226 * If we enable the backlight right away following a panel power
1227 * on, we may see slight flicker as the panel syncs with the eDP
1228 * link. So delay a bit to make sure the image is solid before
1229 * allowing it to appear.
1230 */
1231 msleep(intel_dp->backlight_on_delay);
1232 pp = ironlake_get_pp_control(intel_dp);
1233 pp |= EDP_BLC_ENABLE;
1234
1235 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1236
1237 I915_WRITE(pp_ctrl_reg, pp);
1238 POSTING_READ(pp_ctrl_reg);
1239
1240 intel_panel_enable_backlight(dev, pipe);
1241 }
1242
1243 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1244 {
1245 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1246 struct drm_i915_private *dev_priv = dev->dev_private;
1247 u32 pp;
1248 u32 pp_ctrl_reg;
1249
1250 if (!is_edp(intel_dp))
1251 return;
1252
1253 intel_panel_disable_backlight(dev);
1254
1255 DRM_DEBUG_KMS("\n");
1256 pp = ironlake_get_pp_control(intel_dp);
1257 pp &= ~EDP_BLC_ENABLE;
1258
1259 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1260
1261 I915_WRITE(pp_ctrl_reg, pp);
1262 POSTING_READ(pp_ctrl_reg);
1263 msleep(intel_dp->backlight_off_delay);
1264 }
1265
1266 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1267 {
1268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1269 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1270 struct drm_device *dev = crtc->dev;
1271 struct drm_i915_private *dev_priv = dev->dev_private;
1272 u32 dpa_ctl;
1273
1274 assert_pipe_disabled(dev_priv,
1275 to_intel_crtc(crtc)->pipe);
1276
1277 DRM_DEBUG_KMS("\n");
1278 dpa_ctl = I915_READ(DP_A);
1279 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1280 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1281
1282 /* We don't adjust intel_dp->DP while tearing down the link, to
1283 * facilitate link retraining (e.g. after hotplug). Hence clear all
1284 * enable bits here to ensure that we don't enable too much. */
1285 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1286 intel_dp->DP |= DP_PLL_ENABLE;
1287 I915_WRITE(DP_A, intel_dp->DP);
1288 POSTING_READ(DP_A);
1289 udelay(200);
1290 }
1291
1292 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1293 {
1294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1296 struct drm_device *dev = crtc->dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 u32 dpa_ctl;
1299
1300 assert_pipe_disabled(dev_priv,
1301 to_intel_crtc(crtc)->pipe);
1302
1303 dpa_ctl = I915_READ(DP_A);
1304 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1305 "dp pll off, should be on\n");
1306 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1307
1308 /* We can't rely on the value tracked for the DP register in
1309 * intel_dp->DP because link_down must not change that (otherwise link
1310 * re-training will fail. */
1311 dpa_ctl &= ~DP_PLL_ENABLE;
1312 I915_WRITE(DP_A, dpa_ctl);
1313 POSTING_READ(DP_A);
1314 udelay(200);
1315 }
1316
1317 /* If the sink supports it, try to set the power state appropriately */
1318 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1319 {
1320 int ret, i;
1321
1322 /* Should have a valid DPCD by this point */
1323 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1324 return;
1325
1326 if (mode != DRM_MODE_DPMS_ON) {
1327 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1328 DP_SET_POWER_D3);
1329 if (ret != 1)
1330 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1331 } else {
1332 /*
1333 * When turning on, we need to retry for 1ms to give the sink
1334 * time to wake up.
1335 */
1336 for (i = 0; i < 3; i++) {
1337 ret = intel_dp_aux_native_write_1(intel_dp,
1338 DP_SET_POWER,
1339 DP_SET_POWER_D0);
1340 if (ret == 1)
1341 break;
1342 msleep(1);
1343 }
1344 }
1345 }
1346
1347 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1348 enum pipe *pipe)
1349 {
1350 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1351 struct drm_device *dev = encoder->base.dev;
1352 struct drm_i915_private *dev_priv = dev->dev_private;
1353 u32 tmp = I915_READ(intel_dp->output_reg);
1354
1355 if (!(tmp & DP_PORT_EN))
1356 return false;
1357
1358 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1359 *pipe = PORT_TO_PIPE_CPT(tmp);
1360 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1361 *pipe = PORT_TO_PIPE(tmp);
1362 } else {
1363 u32 trans_sel;
1364 u32 trans_dp;
1365 int i;
1366
1367 switch (intel_dp->output_reg) {
1368 case PCH_DP_B:
1369 trans_sel = TRANS_DP_PORT_SEL_B;
1370 break;
1371 case PCH_DP_C:
1372 trans_sel = TRANS_DP_PORT_SEL_C;
1373 break;
1374 case PCH_DP_D:
1375 trans_sel = TRANS_DP_PORT_SEL_D;
1376 break;
1377 default:
1378 return true;
1379 }
1380
1381 for_each_pipe(i) {
1382 trans_dp = I915_READ(TRANS_DP_CTL(i));
1383 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1384 *pipe = i;
1385 return true;
1386 }
1387 }
1388
1389 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1390 intel_dp->output_reg);
1391 }
1392
1393 return true;
1394 }
1395
1396 static void intel_disable_dp(struct intel_encoder *encoder)
1397 {
1398 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1399
1400 /* Make sure the panel is off before trying to change the mode. But also
1401 * ensure that we have vdd while we switch off the panel. */
1402 ironlake_edp_panel_vdd_on(intel_dp);
1403 ironlake_edp_backlight_off(intel_dp);
1404 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1405 ironlake_edp_panel_off(intel_dp);
1406
1407 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1408 if (!is_cpu_edp(intel_dp))
1409 intel_dp_link_down(intel_dp);
1410 }
1411
1412 static void intel_post_disable_dp(struct intel_encoder *encoder)
1413 {
1414 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1415 struct drm_device *dev = encoder->base.dev;
1416
1417 if (is_cpu_edp(intel_dp)) {
1418 intel_dp_link_down(intel_dp);
1419 if (!IS_VALLEYVIEW(dev))
1420 ironlake_edp_pll_off(intel_dp);
1421 }
1422 }
1423
1424 static void intel_enable_dp(struct intel_encoder *encoder)
1425 {
1426 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1427 struct drm_device *dev = encoder->base.dev;
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1430
1431 if (WARN_ON(dp_reg & DP_PORT_EN))
1432 return;
1433
1434 ironlake_edp_panel_vdd_on(intel_dp);
1435 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1436 intel_dp_start_link_train(intel_dp);
1437 ironlake_edp_panel_on(intel_dp);
1438 ironlake_edp_panel_vdd_off(intel_dp, true);
1439 intel_dp_complete_link_train(intel_dp);
1440 ironlake_edp_backlight_on(intel_dp);
1441
1442 if (IS_VALLEYVIEW(dev)) {
1443 struct intel_digital_port *dport =
1444 enc_to_dig_port(&encoder->base);
1445 int channel = vlv_dport_to_channel(dport);
1446
1447 vlv_wait_port_ready(dev_priv, channel);
1448 }
1449 }
1450
1451 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1452 {
1453 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1454 struct drm_device *dev = encoder->base.dev;
1455 struct drm_i915_private *dev_priv = dev->dev_private;
1456
1457 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1458 ironlake_edp_pll_on(intel_dp);
1459
1460 if (IS_VALLEYVIEW(dev)) {
1461 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1462 struct intel_crtc *intel_crtc =
1463 to_intel_crtc(encoder->base.crtc);
1464 int port = vlv_dport_to_channel(dport);
1465 int pipe = intel_crtc->pipe;
1466 u32 val;
1467
1468 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1469
1470 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1471 val = 0;
1472 if (pipe)
1473 val |= (1<<21);
1474 else
1475 val &= ~(1<<21);
1476 val |= 0x001000c4;
1477 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1478
1479 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1480 0x00760018);
1481 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1482 0x00400888);
1483 }
1484 }
1485
1486 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1487 {
1488 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1489 struct drm_device *dev = encoder->base.dev;
1490 struct drm_i915_private *dev_priv = dev->dev_private;
1491 int port = vlv_dport_to_channel(dport);
1492
1493 if (!IS_VALLEYVIEW(dev))
1494 return;
1495
1496 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1497
1498 /* Program Tx lane resets to default */
1499 intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1500 DPIO_PCS_TX_LANE2_RESET |
1501 DPIO_PCS_TX_LANE1_RESET);
1502 intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1503 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1504 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1505 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1506 DPIO_PCS_CLK_SOFT_RESET);
1507
1508 /* Fix up inter-pair skew failure */
1509 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1510 intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1511 intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1512 }
1513
1514 /*
1515 * Native read with retry for link status and receiver capability reads for
1516 * cases where the sink may still be asleep.
1517 */
1518 static bool
1519 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1520 uint8_t *recv, int recv_bytes)
1521 {
1522 int ret, i;
1523
1524 /*
1525 * Sinks are *supposed* to come up within 1ms from an off state,
1526 * but we're also supposed to retry 3 times per the spec.
1527 */
1528 for (i = 0; i < 3; i++) {
1529 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1530 recv_bytes);
1531 if (ret == recv_bytes)
1532 return true;
1533 msleep(1);
1534 }
1535
1536 return false;
1537 }
1538
1539 /*
1540 * Fetch AUX CH registers 0x202 - 0x207 which contain
1541 * link status information
1542 */
1543 static bool
1544 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1545 {
1546 return intel_dp_aux_native_read_retry(intel_dp,
1547 DP_LANE0_1_STATUS,
1548 link_status,
1549 DP_LINK_STATUS_SIZE);
1550 }
1551
1552 #if 0
1553 static char *voltage_names[] = {
1554 "0.4V", "0.6V", "0.8V", "1.2V"
1555 };
1556 static char *pre_emph_names[] = {
1557 "0dB", "3.5dB", "6dB", "9.5dB"
1558 };
1559 static char *link_train_names[] = {
1560 "pattern 1", "pattern 2", "idle", "off"
1561 };
1562 #endif
1563
1564 /*
1565 * These are source-specific values; current Intel hardware supports
1566 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1567 */
1568
1569 static uint8_t
1570 intel_dp_voltage_max(struct intel_dp *intel_dp)
1571 {
1572 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1573
1574 if (IS_VALLEYVIEW(dev))
1575 return DP_TRAIN_VOLTAGE_SWING_1200;
1576 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1577 return DP_TRAIN_VOLTAGE_SWING_800;
1578 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1579 return DP_TRAIN_VOLTAGE_SWING_1200;
1580 else
1581 return DP_TRAIN_VOLTAGE_SWING_800;
1582 }
1583
1584 static uint8_t
1585 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1586 {
1587 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1588
1589 if (HAS_DDI(dev)) {
1590 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1591 case DP_TRAIN_VOLTAGE_SWING_400:
1592 return DP_TRAIN_PRE_EMPHASIS_9_5;
1593 case DP_TRAIN_VOLTAGE_SWING_600:
1594 return DP_TRAIN_PRE_EMPHASIS_6;
1595 case DP_TRAIN_VOLTAGE_SWING_800:
1596 return DP_TRAIN_PRE_EMPHASIS_3_5;
1597 case DP_TRAIN_VOLTAGE_SWING_1200:
1598 default:
1599 return DP_TRAIN_PRE_EMPHASIS_0;
1600 }
1601 } else if (IS_VALLEYVIEW(dev)) {
1602 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1603 case DP_TRAIN_VOLTAGE_SWING_400:
1604 return DP_TRAIN_PRE_EMPHASIS_9_5;
1605 case DP_TRAIN_VOLTAGE_SWING_600:
1606 return DP_TRAIN_PRE_EMPHASIS_6;
1607 case DP_TRAIN_VOLTAGE_SWING_800:
1608 return DP_TRAIN_PRE_EMPHASIS_3_5;
1609 case DP_TRAIN_VOLTAGE_SWING_1200:
1610 default:
1611 return DP_TRAIN_PRE_EMPHASIS_0;
1612 }
1613 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1614 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1615 case DP_TRAIN_VOLTAGE_SWING_400:
1616 return DP_TRAIN_PRE_EMPHASIS_6;
1617 case DP_TRAIN_VOLTAGE_SWING_600:
1618 case DP_TRAIN_VOLTAGE_SWING_800:
1619 return DP_TRAIN_PRE_EMPHASIS_3_5;
1620 default:
1621 return DP_TRAIN_PRE_EMPHASIS_0;
1622 }
1623 } else {
1624 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1625 case DP_TRAIN_VOLTAGE_SWING_400:
1626 return DP_TRAIN_PRE_EMPHASIS_6;
1627 case DP_TRAIN_VOLTAGE_SWING_600:
1628 return DP_TRAIN_PRE_EMPHASIS_6;
1629 case DP_TRAIN_VOLTAGE_SWING_800:
1630 return DP_TRAIN_PRE_EMPHASIS_3_5;
1631 case DP_TRAIN_VOLTAGE_SWING_1200:
1632 default:
1633 return DP_TRAIN_PRE_EMPHASIS_0;
1634 }
1635 }
1636 }
1637
1638 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1639 {
1640 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1643 unsigned long demph_reg_value, preemph_reg_value,
1644 uniqtranscale_reg_value;
1645 uint8_t train_set = intel_dp->train_set[0];
1646 int port = vlv_dport_to_channel(dport);
1647
1648 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1649
1650 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1651 case DP_TRAIN_PRE_EMPHASIS_0:
1652 preemph_reg_value = 0x0004000;
1653 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1654 case DP_TRAIN_VOLTAGE_SWING_400:
1655 demph_reg_value = 0x2B405555;
1656 uniqtranscale_reg_value = 0x552AB83A;
1657 break;
1658 case DP_TRAIN_VOLTAGE_SWING_600:
1659 demph_reg_value = 0x2B404040;
1660 uniqtranscale_reg_value = 0x5548B83A;
1661 break;
1662 case DP_TRAIN_VOLTAGE_SWING_800:
1663 demph_reg_value = 0x2B245555;
1664 uniqtranscale_reg_value = 0x5560B83A;
1665 break;
1666 case DP_TRAIN_VOLTAGE_SWING_1200:
1667 demph_reg_value = 0x2B405555;
1668 uniqtranscale_reg_value = 0x5598DA3A;
1669 break;
1670 default:
1671 return 0;
1672 }
1673 break;
1674 case DP_TRAIN_PRE_EMPHASIS_3_5:
1675 preemph_reg_value = 0x0002000;
1676 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1677 case DP_TRAIN_VOLTAGE_SWING_400:
1678 demph_reg_value = 0x2B404040;
1679 uniqtranscale_reg_value = 0x5552B83A;
1680 break;
1681 case DP_TRAIN_VOLTAGE_SWING_600:
1682 demph_reg_value = 0x2B404848;
1683 uniqtranscale_reg_value = 0x5580B83A;
1684 break;
1685 case DP_TRAIN_VOLTAGE_SWING_800:
1686 demph_reg_value = 0x2B404040;
1687 uniqtranscale_reg_value = 0x55ADDA3A;
1688 break;
1689 default:
1690 return 0;
1691 }
1692 break;
1693 case DP_TRAIN_PRE_EMPHASIS_6:
1694 preemph_reg_value = 0x0000000;
1695 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1696 case DP_TRAIN_VOLTAGE_SWING_400:
1697 demph_reg_value = 0x2B305555;
1698 uniqtranscale_reg_value = 0x5570B83A;
1699 break;
1700 case DP_TRAIN_VOLTAGE_SWING_600:
1701 demph_reg_value = 0x2B2B4040;
1702 uniqtranscale_reg_value = 0x55ADDA3A;
1703 break;
1704 default:
1705 return 0;
1706 }
1707 break;
1708 case DP_TRAIN_PRE_EMPHASIS_9_5:
1709 preemph_reg_value = 0x0006000;
1710 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1711 case DP_TRAIN_VOLTAGE_SWING_400:
1712 demph_reg_value = 0x1B405555;
1713 uniqtranscale_reg_value = 0x55ADDA3A;
1714 break;
1715 default:
1716 return 0;
1717 }
1718 break;
1719 default:
1720 return 0;
1721 }
1722
1723 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1724 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1725 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1726 uniqtranscale_reg_value);
1727 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1728 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1729 intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1730 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1731
1732 return 0;
1733 }
1734
1735 static void
1736 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1737 {
1738 uint8_t v = 0;
1739 uint8_t p = 0;
1740 int lane;
1741 uint8_t voltage_max;
1742 uint8_t preemph_max;
1743
1744 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1745 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1746 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1747
1748 if (this_v > v)
1749 v = this_v;
1750 if (this_p > p)
1751 p = this_p;
1752 }
1753
1754 voltage_max = intel_dp_voltage_max(intel_dp);
1755 if (v >= voltage_max)
1756 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1757
1758 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1759 if (p >= preemph_max)
1760 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1761
1762 for (lane = 0; lane < 4; lane++)
1763 intel_dp->train_set[lane] = v | p;
1764 }
1765
1766 static uint32_t
1767 intel_gen4_signal_levels(uint8_t train_set)
1768 {
1769 uint32_t signal_levels = 0;
1770
1771 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1772 case DP_TRAIN_VOLTAGE_SWING_400:
1773 default:
1774 signal_levels |= DP_VOLTAGE_0_4;
1775 break;
1776 case DP_TRAIN_VOLTAGE_SWING_600:
1777 signal_levels |= DP_VOLTAGE_0_6;
1778 break;
1779 case DP_TRAIN_VOLTAGE_SWING_800:
1780 signal_levels |= DP_VOLTAGE_0_8;
1781 break;
1782 case DP_TRAIN_VOLTAGE_SWING_1200:
1783 signal_levels |= DP_VOLTAGE_1_2;
1784 break;
1785 }
1786 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1787 case DP_TRAIN_PRE_EMPHASIS_0:
1788 default:
1789 signal_levels |= DP_PRE_EMPHASIS_0;
1790 break;
1791 case DP_TRAIN_PRE_EMPHASIS_3_5:
1792 signal_levels |= DP_PRE_EMPHASIS_3_5;
1793 break;
1794 case DP_TRAIN_PRE_EMPHASIS_6:
1795 signal_levels |= DP_PRE_EMPHASIS_6;
1796 break;
1797 case DP_TRAIN_PRE_EMPHASIS_9_5:
1798 signal_levels |= DP_PRE_EMPHASIS_9_5;
1799 break;
1800 }
1801 return signal_levels;
1802 }
1803
1804 /* Gen6's DP voltage swing and pre-emphasis control */
1805 static uint32_t
1806 intel_gen6_edp_signal_levels(uint8_t train_set)
1807 {
1808 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1809 DP_TRAIN_PRE_EMPHASIS_MASK);
1810 switch (signal_levels) {
1811 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1812 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1813 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1814 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1815 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1816 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1817 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1818 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1819 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1820 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1821 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1822 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1823 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1824 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1825 default:
1826 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1827 "0x%x\n", signal_levels);
1828 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1829 }
1830 }
1831
1832 /* Gen7's DP voltage swing and pre-emphasis control */
1833 static uint32_t
1834 intel_gen7_edp_signal_levels(uint8_t train_set)
1835 {
1836 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1837 DP_TRAIN_PRE_EMPHASIS_MASK);
1838 switch (signal_levels) {
1839 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1840 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1841 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1842 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1843 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1844 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1845
1846 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1847 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1848 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1849 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1850
1851 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1852 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1853 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1854 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1855
1856 default:
1857 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1858 "0x%x\n", signal_levels);
1859 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1860 }
1861 }
1862
1863 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1864 static uint32_t
1865 intel_hsw_signal_levels(uint8_t train_set)
1866 {
1867 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1868 DP_TRAIN_PRE_EMPHASIS_MASK);
1869 switch (signal_levels) {
1870 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1871 return DDI_BUF_EMP_400MV_0DB_HSW;
1872 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1873 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1874 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1875 return DDI_BUF_EMP_400MV_6DB_HSW;
1876 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1877 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1878
1879 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1880 return DDI_BUF_EMP_600MV_0DB_HSW;
1881 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1882 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1883 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1884 return DDI_BUF_EMP_600MV_6DB_HSW;
1885
1886 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1887 return DDI_BUF_EMP_800MV_0DB_HSW;
1888 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1889 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1890 default:
1891 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1892 "0x%x\n", signal_levels);
1893 return DDI_BUF_EMP_400MV_0DB_HSW;
1894 }
1895 }
1896
1897 /* Properly updates "DP" with the correct signal levels. */
1898 static void
1899 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1900 {
1901 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1902 struct drm_device *dev = intel_dig_port->base.base.dev;
1903 uint32_t signal_levels, mask;
1904 uint8_t train_set = intel_dp->train_set[0];
1905
1906 if (HAS_DDI(dev)) {
1907 signal_levels = intel_hsw_signal_levels(train_set);
1908 mask = DDI_BUF_EMP_MASK;
1909 } else if (IS_VALLEYVIEW(dev)) {
1910 signal_levels = intel_vlv_signal_levels(intel_dp);
1911 mask = 0;
1912 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1913 signal_levels = intel_gen7_edp_signal_levels(train_set);
1914 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1915 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1916 signal_levels = intel_gen6_edp_signal_levels(train_set);
1917 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1918 } else {
1919 signal_levels = intel_gen4_signal_levels(train_set);
1920 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1921 }
1922
1923 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1924
1925 *DP = (*DP & ~mask) | signal_levels;
1926 }
1927
1928 static bool
1929 intel_dp_set_link_train(struct intel_dp *intel_dp,
1930 uint32_t dp_reg_value,
1931 uint8_t dp_train_pat)
1932 {
1933 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1934 struct drm_device *dev = intel_dig_port->base.base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 enum port port = intel_dig_port->port;
1937 int ret;
1938 uint32_t temp;
1939
1940 if (HAS_DDI(dev)) {
1941 temp = I915_READ(DP_TP_CTL(port));
1942
1943 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1944 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1945 else
1946 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1947
1948 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1949 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1950 case DP_TRAINING_PATTERN_DISABLE:
1951
1952 if (port != PORT_A) {
1953 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1954 I915_WRITE(DP_TP_CTL(port), temp);
1955
1956 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1957 DP_TP_STATUS_IDLE_DONE), 1))
1958 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1959
1960 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1961 }
1962
1963 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1964
1965 break;
1966 case DP_TRAINING_PATTERN_1:
1967 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1968 break;
1969 case DP_TRAINING_PATTERN_2:
1970 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1971 break;
1972 case DP_TRAINING_PATTERN_3:
1973 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1974 break;
1975 }
1976 I915_WRITE(DP_TP_CTL(port), temp);
1977
1978 } else if (HAS_PCH_CPT(dev) &&
1979 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1980 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1981
1982 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1983 case DP_TRAINING_PATTERN_DISABLE:
1984 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1985 break;
1986 case DP_TRAINING_PATTERN_1:
1987 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1988 break;
1989 case DP_TRAINING_PATTERN_2:
1990 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1991 break;
1992 case DP_TRAINING_PATTERN_3:
1993 DRM_ERROR("DP training pattern 3 not supported\n");
1994 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1995 break;
1996 }
1997
1998 } else {
1999 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2000
2001 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2002 case DP_TRAINING_PATTERN_DISABLE:
2003 dp_reg_value |= DP_LINK_TRAIN_OFF;
2004 break;
2005 case DP_TRAINING_PATTERN_1:
2006 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2007 break;
2008 case DP_TRAINING_PATTERN_2:
2009 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2010 break;
2011 case DP_TRAINING_PATTERN_3:
2012 DRM_ERROR("DP training pattern 3 not supported\n");
2013 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2014 break;
2015 }
2016 }
2017
2018 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2019 POSTING_READ(intel_dp->output_reg);
2020
2021 intel_dp_aux_native_write_1(intel_dp,
2022 DP_TRAINING_PATTERN_SET,
2023 dp_train_pat);
2024
2025 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2026 DP_TRAINING_PATTERN_DISABLE) {
2027 ret = intel_dp_aux_native_write(intel_dp,
2028 DP_TRAINING_LANE0_SET,
2029 intel_dp->train_set,
2030 intel_dp->lane_count);
2031 if (ret != intel_dp->lane_count)
2032 return false;
2033 }
2034
2035 return true;
2036 }
2037
2038 /* Enable corresponding port and start training pattern 1 */
2039 void
2040 intel_dp_start_link_train(struct intel_dp *intel_dp)
2041 {
2042 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2043 struct drm_device *dev = encoder->dev;
2044 int i;
2045 uint8_t voltage;
2046 bool clock_recovery = false;
2047 int voltage_tries, loop_tries;
2048 uint32_t DP = intel_dp->DP;
2049
2050 if (HAS_DDI(dev))
2051 intel_ddi_prepare_link_retrain(encoder);
2052
2053 /* Write the link configuration data */
2054 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2055 intel_dp->link_configuration,
2056 DP_LINK_CONFIGURATION_SIZE);
2057
2058 DP |= DP_PORT_EN;
2059
2060 memset(intel_dp->train_set, 0, 4);
2061 voltage = 0xff;
2062 voltage_tries = 0;
2063 loop_tries = 0;
2064 clock_recovery = false;
2065 for (;;) {
2066 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2067 uint8_t link_status[DP_LINK_STATUS_SIZE];
2068
2069 intel_dp_set_signal_levels(intel_dp, &DP);
2070
2071 /* Set training pattern 1 */
2072 if (!intel_dp_set_link_train(intel_dp, DP,
2073 DP_TRAINING_PATTERN_1 |
2074 DP_LINK_SCRAMBLING_DISABLE))
2075 break;
2076
2077 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2078 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2079 DRM_ERROR("failed to get link status\n");
2080 break;
2081 }
2082
2083 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2084 DRM_DEBUG_KMS("clock recovery OK\n");
2085 clock_recovery = true;
2086 break;
2087 }
2088
2089 /* Check to see if we've tried the max voltage */
2090 for (i = 0; i < intel_dp->lane_count; i++)
2091 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2092 break;
2093 if (i == intel_dp->lane_count) {
2094 ++loop_tries;
2095 if (loop_tries == 5) {
2096 DRM_DEBUG_KMS("too many full retries, give up\n");
2097 break;
2098 }
2099 memset(intel_dp->train_set, 0, 4);
2100 voltage_tries = 0;
2101 continue;
2102 }
2103
2104 /* Check to see if we've tried the same voltage 5 times */
2105 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2106 ++voltage_tries;
2107 if (voltage_tries == 5) {
2108 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2109 break;
2110 }
2111 } else
2112 voltage_tries = 0;
2113 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2114
2115 /* Compute new intel_dp->train_set as requested by target */
2116 intel_get_adjust_train(intel_dp, link_status);
2117 }
2118
2119 intel_dp->DP = DP;
2120 }
2121
2122 void
2123 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2124 {
2125 bool channel_eq = false;
2126 int tries, cr_tries;
2127 uint32_t DP = intel_dp->DP;
2128
2129 /* channel equalization */
2130 tries = 0;
2131 cr_tries = 0;
2132 channel_eq = false;
2133 for (;;) {
2134 uint8_t link_status[DP_LINK_STATUS_SIZE];
2135
2136 if (cr_tries > 5) {
2137 DRM_ERROR("failed to train DP, aborting\n");
2138 intel_dp_link_down(intel_dp);
2139 break;
2140 }
2141
2142 intel_dp_set_signal_levels(intel_dp, &DP);
2143
2144 /* channel eq pattern */
2145 if (!intel_dp_set_link_train(intel_dp, DP,
2146 DP_TRAINING_PATTERN_2 |
2147 DP_LINK_SCRAMBLING_DISABLE))
2148 break;
2149
2150 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2151 if (!intel_dp_get_link_status(intel_dp, link_status))
2152 break;
2153
2154 /* Make sure clock is still ok */
2155 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2156 intel_dp_start_link_train(intel_dp);
2157 cr_tries++;
2158 continue;
2159 }
2160
2161 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2162 channel_eq = true;
2163 break;
2164 }
2165
2166 /* Try 5 times, then try clock recovery if that fails */
2167 if (tries > 5) {
2168 intel_dp_link_down(intel_dp);
2169 intel_dp_start_link_train(intel_dp);
2170 tries = 0;
2171 cr_tries++;
2172 continue;
2173 }
2174
2175 /* Compute new intel_dp->train_set as requested by target */
2176 intel_get_adjust_train(intel_dp, link_status);
2177 ++tries;
2178 }
2179
2180 if (channel_eq)
2181 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2182
2183 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2184 }
2185
2186 static void
2187 intel_dp_link_down(struct intel_dp *intel_dp)
2188 {
2189 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2190 struct drm_device *dev = intel_dig_port->base.base.dev;
2191 struct drm_i915_private *dev_priv = dev->dev_private;
2192 struct intel_crtc *intel_crtc =
2193 to_intel_crtc(intel_dig_port->base.base.crtc);
2194 uint32_t DP = intel_dp->DP;
2195
2196 /*
2197 * DDI code has a strict mode set sequence and we should try to respect
2198 * it, otherwise we might hang the machine in many different ways. So we
2199 * really should be disabling the port only on a complete crtc_disable
2200 * sequence. This function is just called under two conditions on DDI
2201 * code:
2202 * - Link train failed while doing crtc_enable, and on this case we
2203 * really should respect the mode set sequence and wait for a
2204 * crtc_disable.
2205 * - Someone turned the monitor off and intel_dp_check_link_status
2206 * called us. We don't need to disable the whole port on this case, so
2207 * when someone turns the monitor on again,
2208 * intel_ddi_prepare_link_retrain will take care of redoing the link
2209 * train.
2210 */
2211 if (HAS_DDI(dev))
2212 return;
2213
2214 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2215 return;
2216
2217 DRM_DEBUG_KMS("\n");
2218
2219 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2220 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2221 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2222 } else {
2223 DP &= ~DP_LINK_TRAIN_MASK;
2224 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2225 }
2226 POSTING_READ(intel_dp->output_reg);
2227
2228 /* We don't really know why we're doing this */
2229 intel_wait_for_vblank(dev, intel_crtc->pipe);
2230
2231 if (HAS_PCH_IBX(dev) &&
2232 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2233 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2234
2235 /* Hardware workaround: leaving our transcoder select
2236 * set to transcoder B while it's off will prevent the
2237 * corresponding HDMI output on transcoder A.
2238 *
2239 * Combine this with another hardware workaround:
2240 * transcoder select bit can only be cleared while the
2241 * port is enabled.
2242 */
2243 DP &= ~DP_PIPEB_SELECT;
2244 I915_WRITE(intel_dp->output_reg, DP);
2245
2246 /* Changes to enable or select take place the vblank
2247 * after being written.
2248 */
2249 if (WARN_ON(crtc == NULL)) {
2250 /* We should never try to disable a port without a crtc
2251 * attached. For paranoia keep the code around for a
2252 * bit. */
2253 POSTING_READ(intel_dp->output_reg);
2254 msleep(50);
2255 } else
2256 intel_wait_for_vblank(dev, intel_crtc->pipe);
2257 }
2258
2259 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2260 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2261 POSTING_READ(intel_dp->output_reg);
2262 msleep(intel_dp->panel_power_down_delay);
2263 }
2264
2265 static bool
2266 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2267 {
2268 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2269
2270 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2271 sizeof(intel_dp->dpcd)) == 0)
2272 return false; /* aux transfer failed */
2273
2274 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2275 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2276 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2277
2278 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2279 return false; /* DPCD not present */
2280
2281 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2282 DP_DWN_STRM_PORT_PRESENT))
2283 return true; /* native DP sink */
2284
2285 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2286 return true; /* no per-port downstream info */
2287
2288 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2289 intel_dp->downstream_ports,
2290 DP_MAX_DOWNSTREAM_PORTS) == 0)
2291 return false; /* downstream port status fetch failed */
2292
2293 return true;
2294 }
2295
2296 static void
2297 intel_dp_probe_oui(struct intel_dp *intel_dp)
2298 {
2299 u8 buf[3];
2300
2301 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2302 return;
2303
2304 ironlake_edp_panel_vdd_on(intel_dp);
2305
2306 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2307 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2308 buf[0], buf[1], buf[2]);
2309
2310 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2311 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2312 buf[0], buf[1], buf[2]);
2313
2314 ironlake_edp_panel_vdd_off(intel_dp, false);
2315 }
2316
2317 static bool
2318 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2319 {
2320 int ret;
2321
2322 ret = intel_dp_aux_native_read_retry(intel_dp,
2323 DP_DEVICE_SERVICE_IRQ_VECTOR,
2324 sink_irq_vector, 1);
2325 if (!ret)
2326 return false;
2327
2328 return true;
2329 }
2330
2331 static void
2332 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2333 {
2334 /* NAK by default */
2335 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2336 }
2337
2338 /*
2339 * According to DP spec
2340 * 5.1.2:
2341 * 1. Read DPCD
2342 * 2. Configure link according to Receiver Capabilities
2343 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2344 * 4. Check link status on receipt of hot-plug interrupt
2345 */
2346
2347 void
2348 intel_dp_check_link_status(struct intel_dp *intel_dp)
2349 {
2350 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2351 u8 sink_irq_vector;
2352 u8 link_status[DP_LINK_STATUS_SIZE];
2353
2354 if (!intel_encoder->connectors_active)
2355 return;
2356
2357 if (WARN_ON(!intel_encoder->base.crtc))
2358 return;
2359
2360 /* Try to read receiver status if the link appears to be up */
2361 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2362 intel_dp_link_down(intel_dp);
2363 return;
2364 }
2365
2366 /* Now read the DPCD to see if it's actually running */
2367 if (!intel_dp_get_dpcd(intel_dp)) {
2368 intel_dp_link_down(intel_dp);
2369 return;
2370 }
2371
2372 /* Try to read the source of the interrupt */
2373 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2374 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2375 /* Clear interrupt source */
2376 intel_dp_aux_native_write_1(intel_dp,
2377 DP_DEVICE_SERVICE_IRQ_VECTOR,
2378 sink_irq_vector);
2379
2380 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2381 intel_dp_handle_test_request(intel_dp);
2382 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2383 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2384 }
2385
2386 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2387 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2388 drm_get_encoder_name(&intel_encoder->base));
2389 intel_dp_start_link_train(intel_dp);
2390 intel_dp_complete_link_train(intel_dp);
2391 }
2392 }
2393
2394 /* XXX this is probably wrong for multiple downstream ports */
2395 static enum drm_connector_status
2396 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2397 {
2398 uint8_t *dpcd = intel_dp->dpcd;
2399 bool hpd;
2400 uint8_t type;
2401
2402 if (!intel_dp_get_dpcd(intel_dp))
2403 return connector_status_disconnected;
2404
2405 /* if there's no downstream port, we're done */
2406 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2407 return connector_status_connected;
2408
2409 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2410 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2411 if (hpd) {
2412 uint8_t reg;
2413 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2414 &reg, 1))
2415 return connector_status_unknown;
2416 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2417 : connector_status_disconnected;
2418 }
2419
2420 /* If no HPD, poke DDC gently */
2421 if (drm_probe_ddc(&intel_dp->adapter))
2422 return connector_status_connected;
2423
2424 /* Well we tried, say unknown for unreliable port types */
2425 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2426 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2427 return connector_status_unknown;
2428
2429 /* Anything else is out of spec, warn and ignore */
2430 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2431 return connector_status_disconnected;
2432 }
2433
2434 static enum drm_connector_status
2435 ironlake_dp_detect(struct intel_dp *intel_dp)
2436 {
2437 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2438 struct drm_i915_private *dev_priv = dev->dev_private;
2439 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2440 enum drm_connector_status status;
2441
2442 /* Can't disconnect eDP, but you can close the lid... */
2443 if (is_edp(intel_dp)) {
2444 status = intel_panel_detect(dev);
2445 if (status == connector_status_unknown)
2446 status = connector_status_connected;
2447 return status;
2448 }
2449
2450 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2451 return connector_status_disconnected;
2452
2453 return intel_dp_detect_dpcd(intel_dp);
2454 }
2455
2456 static enum drm_connector_status
2457 g4x_dp_detect(struct intel_dp *intel_dp)
2458 {
2459 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2462 uint32_t bit;
2463
2464 /* Can't disconnect eDP, but you can close the lid... */
2465 if (is_edp(intel_dp)) {
2466 enum drm_connector_status status;
2467
2468 status = intel_panel_detect(dev);
2469 if (status == connector_status_unknown)
2470 status = connector_status_connected;
2471 return status;
2472 }
2473
2474 switch (intel_dig_port->port) {
2475 case PORT_B:
2476 bit = PORTB_HOTPLUG_LIVE_STATUS;
2477 break;
2478 case PORT_C:
2479 bit = PORTC_HOTPLUG_LIVE_STATUS;
2480 break;
2481 case PORT_D:
2482 bit = PORTD_HOTPLUG_LIVE_STATUS;
2483 break;
2484 default:
2485 return connector_status_unknown;
2486 }
2487
2488 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2489 return connector_status_disconnected;
2490
2491 return intel_dp_detect_dpcd(intel_dp);
2492 }
2493
2494 static struct edid *
2495 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2496 {
2497 struct intel_connector *intel_connector = to_intel_connector(connector);
2498
2499 /* use cached edid if we have one */
2500 if (intel_connector->edid) {
2501 struct edid *edid;
2502 int size;
2503
2504 /* invalid edid */
2505 if (IS_ERR(intel_connector->edid))
2506 return NULL;
2507
2508 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2509 edid = kmalloc(size, GFP_KERNEL);
2510 if (!edid)
2511 return NULL;
2512
2513 memcpy(edid, intel_connector->edid, size);
2514 return edid;
2515 }
2516
2517 return drm_get_edid(connector, adapter);
2518 }
2519
2520 static int
2521 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2522 {
2523 struct intel_connector *intel_connector = to_intel_connector(connector);
2524
2525 /* use cached edid if we have one */
2526 if (intel_connector->edid) {
2527 /* invalid edid */
2528 if (IS_ERR(intel_connector->edid))
2529 return 0;
2530
2531 return intel_connector_update_modes(connector,
2532 intel_connector->edid);
2533 }
2534
2535 return intel_ddc_get_modes(connector, adapter);
2536 }
2537
2538 static enum drm_connector_status
2539 intel_dp_detect(struct drm_connector *connector, bool force)
2540 {
2541 struct intel_dp *intel_dp = intel_attached_dp(connector);
2542 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2543 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2544 struct drm_device *dev = connector->dev;
2545 enum drm_connector_status status;
2546 struct edid *edid = NULL;
2547
2548 intel_dp->has_audio = false;
2549
2550 if (HAS_PCH_SPLIT(dev))
2551 status = ironlake_dp_detect(intel_dp);
2552 else
2553 status = g4x_dp_detect(intel_dp);
2554
2555 if (status != connector_status_connected)
2556 return status;
2557
2558 intel_dp_probe_oui(intel_dp);
2559
2560 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2561 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2562 } else {
2563 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2564 if (edid) {
2565 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2566 kfree(edid);
2567 }
2568 }
2569
2570 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2571 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2572 return connector_status_connected;
2573 }
2574
2575 static int intel_dp_get_modes(struct drm_connector *connector)
2576 {
2577 struct intel_dp *intel_dp = intel_attached_dp(connector);
2578 struct intel_connector *intel_connector = to_intel_connector(connector);
2579 struct drm_device *dev = connector->dev;
2580 int ret;
2581
2582 /* We should parse the EDID data and find out if it has an audio sink
2583 */
2584
2585 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2586 if (ret)
2587 return ret;
2588
2589 /* if eDP has no EDID, fall back to fixed mode */
2590 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2591 struct drm_display_mode *mode;
2592 mode = drm_mode_duplicate(dev,
2593 intel_connector->panel.fixed_mode);
2594 if (mode) {
2595 drm_mode_probed_add(connector, mode);
2596 return 1;
2597 }
2598 }
2599 return 0;
2600 }
2601
2602 static bool
2603 intel_dp_detect_audio(struct drm_connector *connector)
2604 {
2605 struct intel_dp *intel_dp = intel_attached_dp(connector);
2606 struct edid *edid;
2607 bool has_audio = false;
2608
2609 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2610 if (edid) {
2611 has_audio = drm_detect_monitor_audio(edid);
2612 kfree(edid);
2613 }
2614
2615 return has_audio;
2616 }
2617
2618 static int
2619 intel_dp_set_property(struct drm_connector *connector,
2620 struct drm_property *property,
2621 uint64_t val)
2622 {
2623 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2624 struct intel_connector *intel_connector = to_intel_connector(connector);
2625 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2626 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2627 int ret;
2628
2629 ret = drm_object_property_set_value(&connector->base, property, val);
2630 if (ret)
2631 return ret;
2632
2633 if (property == dev_priv->force_audio_property) {
2634 int i = val;
2635 bool has_audio;
2636
2637 if (i == intel_dp->force_audio)
2638 return 0;
2639
2640 intel_dp->force_audio = i;
2641
2642 if (i == HDMI_AUDIO_AUTO)
2643 has_audio = intel_dp_detect_audio(connector);
2644 else
2645 has_audio = (i == HDMI_AUDIO_ON);
2646
2647 if (has_audio == intel_dp->has_audio)
2648 return 0;
2649
2650 intel_dp->has_audio = has_audio;
2651 goto done;
2652 }
2653
2654 if (property == dev_priv->broadcast_rgb_property) {
2655 switch (val) {
2656 case INTEL_BROADCAST_RGB_AUTO:
2657 intel_dp->color_range_auto = true;
2658 break;
2659 case INTEL_BROADCAST_RGB_FULL:
2660 intel_dp->color_range_auto = false;
2661 intel_dp->color_range = 0;
2662 break;
2663 case INTEL_BROADCAST_RGB_LIMITED:
2664 intel_dp->color_range_auto = false;
2665 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2666 break;
2667 default:
2668 return -EINVAL;
2669 }
2670 goto done;
2671 }
2672
2673 if (is_edp(intel_dp) &&
2674 property == connector->dev->mode_config.scaling_mode_property) {
2675 if (val == DRM_MODE_SCALE_NONE) {
2676 DRM_DEBUG_KMS("no scaling not supported\n");
2677 return -EINVAL;
2678 }
2679
2680 if (intel_connector->panel.fitting_mode == val) {
2681 /* the eDP scaling property is not changed */
2682 return 0;
2683 }
2684 intel_connector->panel.fitting_mode = val;
2685
2686 goto done;
2687 }
2688
2689 return -EINVAL;
2690
2691 done:
2692 if (intel_encoder->base.crtc)
2693 intel_crtc_restore_mode(intel_encoder->base.crtc);
2694
2695 return 0;
2696 }
2697
2698 static void
2699 intel_dp_destroy(struct drm_connector *connector)
2700 {
2701 struct intel_dp *intel_dp = intel_attached_dp(connector);
2702 struct intel_connector *intel_connector = to_intel_connector(connector);
2703
2704 if (!IS_ERR_OR_NULL(intel_connector->edid))
2705 kfree(intel_connector->edid);
2706
2707 if (is_edp(intel_dp))
2708 intel_panel_fini(&intel_connector->panel);
2709
2710 drm_sysfs_connector_remove(connector);
2711 drm_connector_cleanup(connector);
2712 kfree(connector);
2713 }
2714
2715 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2716 {
2717 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2718 struct intel_dp *intel_dp = &intel_dig_port->dp;
2719
2720 i2c_del_adapter(&intel_dp->adapter);
2721 drm_encoder_cleanup(encoder);
2722 if (is_edp(intel_dp)) {
2723 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2724 ironlake_panel_vdd_off_sync(intel_dp);
2725 }
2726 kfree(intel_dig_port);
2727 }
2728
2729 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2730 .mode_set = intel_dp_mode_set,
2731 };
2732
2733 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2734 .dpms = intel_connector_dpms,
2735 .detect = intel_dp_detect,
2736 .fill_modes = drm_helper_probe_single_connector_modes,
2737 .set_property = intel_dp_set_property,
2738 .destroy = intel_dp_destroy,
2739 };
2740
2741 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2742 .get_modes = intel_dp_get_modes,
2743 .mode_valid = intel_dp_mode_valid,
2744 .best_encoder = intel_best_encoder,
2745 };
2746
2747 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2748 .destroy = intel_dp_encoder_destroy,
2749 };
2750
2751 static void
2752 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2753 {
2754 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2755
2756 intel_dp_check_link_status(intel_dp);
2757 }
2758
2759 /* Return which DP Port should be selected for Transcoder DP control */
2760 int
2761 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2762 {
2763 struct drm_device *dev = crtc->dev;
2764 struct intel_encoder *intel_encoder;
2765 struct intel_dp *intel_dp;
2766
2767 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2768 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2769
2770 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2771 intel_encoder->type == INTEL_OUTPUT_EDP)
2772 return intel_dp->output_reg;
2773 }
2774
2775 return -1;
2776 }
2777
2778 /* check the VBT to see whether the eDP is on DP-D port */
2779 bool intel_dpd_is_edp(struct drm_device *dev)
2780 {
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct child_device_config *p_child;
2783 int i;
2784
2785 if (!dev_priv->child_dev_num)
2786 return false;
2787
2788 for (i = 0; i < dev_priv->child_dev_num; i++) {
2789 p_child = dev_priv->child_dev + i;
2790
2791 if (p_child->dvo_port == PORT_IDPD &&
2792 p_child->device_type == DEVICE_TYPE_eDP)
2793 return true;
2794 }
2795 return false;
2796 }
2797
2798 static void
2799 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2800 {
2801 struct intel_connector *intel_connector = to_intel_connector(connector);
2802
2803 intel_attach_force_audio_property(connector);
2804 intel_attach_broadcast_rgb_property(connector);
2805 intel_dp->color_range_auto = true;
2806
2807 if (is_edp(intel_dp)) {
2808 drm_mode_create_scaling_mode_property(connector->dev);
2809 drm_object_attach_property(
2810 &connector->base,
2811 connector->dev->mode_config.scaling_mode_property,
2812 DRM_MODE_SCALE_ASPECT);
2813 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2814 }
2815 }
2816
2817 static void
2818 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2819 struct intel_dp *intel_dp,
2820 struct edp_power_seq *out)
2821 {
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 struct edp_power_seq cur, vbt, spec, final;
2824 u32 pp_on, pp_off, pp_div, pp;
2825 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2826
2827 if (HAS_PCH_SPLIT(dev)) {
2828 pp_control_reg = PCH_PP_CONTROL;
2829 pp_on_reg = PCH_PP_ON_DELAYS;
2830 pp_off_reg = PCH_PP_OFF_DELAYS;
2831 pp_div_reg = PCH_PP_DIVISOR;
2832 } else {
2833 pp_control_reg = PIPEA_PP_CONTROL;
2834 pp_on_reg = PIPEA_PP_ON_DELAYS;
2835 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2836 pp_div_reg = PIPEA_PP_DIVISOR;
2837 }
2838
2839 /* Workaround: Need to write PP_CONTROL with the unlock key as
2840 * the very first thing. */
2841 pp = ironlake_get_pp_control(intel_dp);
2842 I915_WRITE(pp_control_reg, pp);
2843
2844 pp_on = I915_READ(pp_on_reg);
2845 pp_off = I915_READ(pp_off_reg);
2846 pp_div = I915_READ(pp_div_reg);
2847
2848 /* Pull timing values out of registers */
2849 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2850 PANEL_POWER_UP_DELAY_SHIFT;
2851
2852 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2853 PANEL_LIGHT_ON_DELAY_SHIFT;
2854
2855 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2856 PANEL_LIGHT_OFF_DELAY_SHIFT;
2857
2858 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2859 PANEL_POWER_DOWN_DELAY_SHIFT;
2860
2861 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2862 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2863
2864 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2865 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2866
2867 vbt = dev_priv->edp.pps;
2868
2869 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2870 * our hw here, which are all in 100usec. */
2871 spec.t1_t3 = 210 * 10;
2872 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2873 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2874 spec.t10 = 500 * 10;
2875 /* This one is special and actually in units of 100ms, but zero
2876 * based in the hw (so we need to add 100 ms). But the sw vbt
2877 * table multiplies it with 1000 to make it in units of 100usec,
2878 * too. */
2879 spec.t11_t12 = (510 + 100) * 10;
2880
2881 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2882 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2883
2884 /* Use the max of the register settings and vbt. If both are
2885 * unset, fall back to the spec limits. */
2886 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2887 spec.field : \
2888 max(cur.field, vbt.field))
2889 assign_final(t1_t3);
2890 assign_final(t8);
2891 assign_final(t9);
2892 assign_final(t10);
2893 assign_final(t11_t12);
2894 #undef assign_final
2895
2896 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2897 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2898 intel_dp->backlight_on_delay = get_delay(t8);
2899 intel_dp->backlight_off_delay = get_delay(t9);
2900 intel_dp->panel_power_down_delay = get_delay(t10);
2901 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2902 #undef get_delay
2903
2904 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2905 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2906 intel_dp->panel_power_cycle_delay);
2907
2908 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2909 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2910
2911 if (out)
2912 *out = final;
2913 }
2914
2915 static void
2916 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2917 struct intel_dp *intel_dp,
2918 struct edp_power_seq *seq)
2919 {
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 u32 pp_on, pp_off, pp_div, port_sel = 0;
2922 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2923 int pp_on_reg, pp_off_reg, pp_div_reg;
2924
2925 if (HAS_PCH_SPLIT(dev)) {
2926 pp_on_reg = PCH_PP_ON_DELAYS;
2927 pp_off_reg = PCH_PP_OFF_DELAYS;
2928 pp_div_reg = PCH_PP_DIVISOR;
2929 } else {
2930 pp_on_reg = PIPEA_PP_ON_DELAYS;
2931 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2932 pp_div_reg = PIPEA_PP_DIVISOR;
2933 }
2934
2935 if (IS_VALLEYVIEW(dev))
2936 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2937
2938 /* And finally store the new values in the power sequencer. */
2939 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2940 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2941 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2942 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2943 /* Compute the divisor for the pp clock, simply match the Bspec
2944 * formula. */
2945 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2946 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2947 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2948
2949 /* Haswell doesn't have any port selection bits for the panel
2950 * power sequencer any more. */
2951 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2952 if (is_cpu_edp(intel_dp))
2953 port_sel = PANEL_POWER_PORT_DP_A;
2954 else
2955 port_sel = PANEL_POWER_PORT_DP_D;
2956 }
2957
2958 pp_on |= port_sel;
2959
2960 I915_WRITE(pp_on_reg, pp_on);
2961 I915_WRITE(pp_off_reg, pp_off);
2962 I915_WRITE(pp_div_reg, pp_div);
2963
2964 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2965 I915_READ(pp_on_reg),
2966 I915_READ(pp_off_reg),
2967 I915_READ(pp_div_reg));
2968 }
2969
2970 void
2971 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2972 struct intel_connector *intel_connector)
2973 {
2974 struct drm_connector *connector = &intel_connector->base;
2975 struct intel_dp *intel_dp = &intel_dig_port->dp;
2976 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2977 struct drm_device *dev = intel_encoder->base.dev;
2978 struct drm_i915_private *dev_priv = dev->dev_private;
2979 struct drm_display_mode *fixed_mode = NULL;
2980 struct edp_power_seq power_seq = { 0 };
2981 enum port port = intel_dig_port->port;
2982 const char *name = NULL;
2983 int type;
2984
2985 /* Preserve the current hw state. */
2986 intel_dp->DP = I915_READ(intel_dp->output_reg);
2987 intel_dp->attached_connector = intel_connector;
2988
2989 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2990 if (intel_dpd_is_edp(dev))
2991 intel_dp->is_pch_edp = true;
2992
2993 /*
2994 * FIXME : We need to initialize built-in panels before external panels.
2995 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2996 */
2997 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2998 type = DRM_MODE_CONNECTOR_eDP;
2999 intel_encoder->type = INTEL_OUTPUT_EDP;
3000 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
3001 type = DRM_MODE_CONNECTOR_eDP;
3002 intel_encoder->type = INTEL_OUTPUT_EDP;
3003 } else {
3004 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
3005 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
3006 * rewrite it.
3007 */
3008 type = DRM_MODE_CONNECTOR_DisplayPort;
3009 }
3010
3011 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3012 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3013
3014 connector->interlace_allowed = true;
3015 connector->doublescan_allowed = 0;
3016
3017 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3018 ironlake_panel_vdd_work);
3019
3020 intel_connector_attach_encoder(intel_connector, intel_encoder);
3021 drm_sysfs_connector_add(connector);
3022
3023 if (HAS_DDI(dev))
3024 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3025 else
3026 intel_connector->get_hw_state = intel_connector_get_hw_state;
3027
3028 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3029 if (HAS_DDI(dev)) {
3030 switch (intel_dig_port->port) {
3031 case PORT_A:
3032 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3033 break;
3034 case PORT_B:
3035 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3036 break;
3037 case PORT_C:
3038 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3039 break;
3040 case PORT_D:
3041 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3042 break;
3043 default:
3044 BUG();
3045 }
3046 }
3047
3048 /* Set up the DDC bus. */
3049 switch (port) {
3050 case PORT_A:
3051 intel_encoder->hpd_pin = HPD_PORT_A;
3052 name = "DPDDC-A";
3053 break;
3054 case PORT_B:
3055 intel_encoder->hpd_pin = HPD_PORT_B;
3056 name = "DPDDC-B";
3057 break;
3058 case PORT_C:
3059 intel_encoder->hpd_pin = HPD_PORT_C;
3060 name = "DPDDC-C";
3061 break;
3062 case PORT_D:
3063 intel_encoder->hpd_pin = HPD_PORT_D;
3064 name = "DPDDC-D";
3065 break;
3066 default:
3067 BUG();
3068 }
3069
3070 if (is_edp(intel_dp))
3071 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3072
3073 intel_dp_i2c_init(intel_dp, intel_connector, name);
3074
3075 /* Cache DPCD and EDID for edp. */
3076 if (is_edp(intel_dp)) {
3077 bool ret;
3078 struct drm_display_mode *scan;
3079 struct edid *edid;
3080
3081 ironlake_edp_panel_vdd_on(intel_dp);
3082 ret = intel_dp_get_dpcd(intel_dp);
3083 ironlake_edp_panel_vdd_off(intel_dp, false);
3084
3085 if (ret) {
3086 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3087 dev_priv->no_aux_handshake =
3088 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3089 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3090 } else {
3091 /* if this fails, presume the device is a ghost */
3092 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3093 intel_dp_encoder_destroy(&intel_encoder->base);
3094 intel_dp_destroy(connector);
3095 return;
3096 }
3097
3098 /* We now know it's not a ghost, init power sequence regs. */
3099 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3100 &power_seq);
3101
3102 ironlake_edp_panel_vdd_on(intel_dp);
3103 edid = drm_get_edid(connector, &intel_dp->adapter);
3104 if (edid) {
3105 if (drm_add_edid_modes(connector, edid)) {
3106 drm_mode_connector_update_edid_property(connector, edid);
3107 drm_edid_to_eld(connector, edid);
3108 } else {
3109 kfree(edid);
3110 edid = ERR_PTR(-EINVAL);
3111 }
3112 } else {
3113 edid = ERR_PTR(-ENOENT);
3114 }
3115 intel_connector->edid = edid;
3116
3117 /* prefer fixed mode from EDID if available */
3118 list_for_each_entry(scan, &connector->probed_modes, head) {
3119 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3120 fixed_mode = drm_mode_duplicate(dev, scan);
3121 break;
3122 }
3123 }
3124
3125 /* fallback to VBT if available for eDP */
3126 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3127 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3128 if (fixed_mode)
3129 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3130 }
3131
3132 ironlake_edp_panel_vdd_off(intel_dp, false);
3133 }
3134
3135 if (is_edp(intel_dp)) {
3136 intel_panel_init(&intel_connector->panel, fixed_mode);
3137 intel_panel_setup_backlight(connector);
3138 }
3139
3140 intel_dp_add_properties(intel_dp, connector);
3141
3142 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3143 * 0xd. Failure to do so will result in spurious interrupts being
3144 * generated on the port when a cable is not attached.
3145 */
3146 if (IS_G4X(dev) && !IS_GM45(dev)) {
3147 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3148 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3149 }
3150 }
3151
3152 void
3153 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3154 {
3155 struct intel_digital_port *intel_dig_port;
3156 struct intel_encoder *intel_encoder;
3157 struct drm_encoder *encoder;
3158 struct intel_connector *intel_connector;
3159
3160 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3161 if (!intel_dig_port)
3162 return;
3163
3164 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3165 if (!intel_connector) {
3166 kfree(intel_dig_port);
3167 return;
3168 }
3169
3170 intel_encoder = &intel_dig_port->base;
3171 encoder = &intel_encoder->base;
3172
3173 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3174 DRM_MODE_ENCODER_TMDS);
3175 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3176
3177 intel_encoder->compute_config = intel_dp_compute_config;
3178 intel_encoder->enable = intel_enable_dp;
3179 intel_encoder->pre_enable = intel_pre_enable_dp;
3180 intel_encoder->disable = intel_disable_dp;
3181 intel_encoder->post_disable = intel_post_disable_dp;
3182 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3183 if (IS_VALLEYVIEW(dev))
3184 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3185
3186 intel_dig_port->port = port;
3187 intel_dig_port->dp.output_reg = output_reg;
3188
3189 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3190 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3191 intel_encoder->cloneable = false;
3192 intel_encoder->hot_plug = intel_dp_hot_plug;
3193
3194 intel_dp_init_connector(intel_dig_port, intel_connector);
3195 }
Linux kernel - Deliverables
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