2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll
[] = {
48 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
50 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
53 static const struct dp_link_dpll pch_dpll
[] = {
55 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
57 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
60 static const struct dp_link_dpll vlv_dpll
[] = {
62 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
64 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp
*intel_dp
)
76 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
78 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
81 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
83 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
85 return intel_dig_port
->base
.base
.dev
;
88 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
90 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
93 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
94 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
);
95 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
98 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
100 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
101 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
103 switch (max_link_bw
) {
104 case DP_LINK_BW_1_62
:
107 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8) &&
109 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
110 max_link_bw
= DP_LINK_BW_5_4
;
112 max_link_bw
= DP_LINK_BW_2_7
;
115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw
= DP_LINK_BW_1_62
;
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
129 * 270000 * 1 * 8 / 10 == 216000
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
141 intel_dp_link_required(int pixel_clock
, int bpp
)
143 return (pixel_clock
* bpp
+ 9) / 10;
147 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
149 return (max_link_clock
* max_lanes
* 8) / 10;
152 static enum drm_mode_status
153 intel_dp_mode_valid(struct drm_connector
*connector
,
154 struct drm_display_mode
*mode
)
156 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
157 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
158 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
159 int target_clock
= mode
->clock
;
160 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
162 if (is_edp(intel_dp
) && fixed_mode
) {
163 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
166 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
169 target_clock
= fixed_mode
->clock
;
172 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
173 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
175 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
176 mode_rate
= intel_dp_link_required(target_clock
, 18);
178 if (mode_rate
> max_rate
)
179 return MODE_CLOCK_HIGH
;
181 if (mode
->clock
< 10000)
182 return MODE_CLOCK_LOW
;
184 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
185 return MODE_H_ILLEGAL
;
191 pack_aux(uint8_t *src
, int src_bytes
)
198 for (i
= 0; i
< src_bytes
; i
++)
199 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
204 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
209 for (i
= 0; i
< dst_bytes
; i
++)
210 dst
[i
] = src
>> ((3-i
) * 8);
213 /* hrawclock is 1/4 the FSB frequency */
215 intel_hrawclk(struct drm_device
*dev
)
217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev
))
224 clkcfg
= I915_READ(CLKCFG
);
225 switch (clkcfg
& CLKCFG_FSB_MASK
) {
234 case CLKCFG_FSB_1067
:
236 case CLKCFG_FSB_1333
:
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600
:
240 case CLKCFG_FSB_1600_ALT
:
248 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
249 struct intel_dp
*intel_dp
,
250 struct edp_power_seq
*out
);
252 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
253 struct intel_dp
*intel_dp
,
254 struct edp_power_seq
*out
);
257 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
259 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
260 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
261 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
263 enum port port
= intel_dig_port
->port
;
266 /* modeset should have pipe */
268 return to_intel_crtc(crtc
)->pipe
;
270 /* init time, try to find a pipe with this port selected */
271 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
272 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
273 PANEL_PORT_SELECT_MASK
;
274 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
276 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
284 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
286 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
288 if (HAS_PCH_SPLIT(dev
))
289 return PCH_PP_CONTROL
;
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
294 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
296 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
298 if (HAS_PCH_SPLIT(dev
))
299 return PCH_PP_STATUS
;
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
304 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
306 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
309 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
312 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
314 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 return (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
321 intel_dp_check_edp(struct intel_dp
*intel_dp
)
323 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
326 if (!is_edp(intel_dp
))
329 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
332 I915_READ(_pp_stat_reg(intel_dp
)),
333 I915_READ(_pp_ctrl_reg(intel_dp
)));
338 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
340 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
341 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
343 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
347 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
349 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
350 msecs_to_jiffies_timeout(10));
352 done
= wait_for_atomic(C
, 10) == 0;
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
361 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
363 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
364 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
367 * The clock divider is based off the hrawclk, and would like to run at
368 * 2MHz. So, take the hrawclk value and divide by 2 and use that
370 return index
? 0 : intel_hrawclk(dev
) / 2;
373 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
375 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
376 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
381 if (intel_dig_port
->port
== PORT_A
) {
382 if (IS_GEN6(dev
) || IS_GEN7(dev
))
383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
385 return 225; /* eDP input clock at 450Mhz */
387 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
391 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
393 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
394 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
397 if (intel_dig_port
->port
== PORT_A
) {
400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
401 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
402 /* Workaround for non-ULT HSW */
409 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
413 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
415 return index
? 0 : 100;
418 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
421 uint32_t aux_clock_divider
)
423 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
424 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
425 uint32_t precharge
, timeout
;
432 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
433 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
435 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
437 return DP_AUX_CH_CTL_SEND_BUSY
|
439 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
440 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
442 DP_AUX_CH_CTL_RECEIVE_ERROR
|
443 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
444 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
445 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
449 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
450 uint8_t *send
, int send_bytes
,
451 uint8_t *recv
, int recv_size
)
453 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
454 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
456 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
457 uint32_t ch_data
= ch_ctl
+ 4;
458 uint32_t aux_clock_divider
;
459 int i
, ret
, recv_bytes
;
462 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
465 vdd
= _edp_panel_vdd_on(intel_dp
);
467 /* dp aux is extremely sensitive to irq latency, hence request the
468 * lowest possible wakeup latency and so prevent the cpu from going into
471 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
473 intel_dp_check_edp(intel_dp
);
475 intel_aux_display_runtime_get(dev_priv
);
477 /* Try to wait for any previous AUX channel activity */
478 for (try = 0; try < 3; try++) {
479 status
= I915_READ_NOTRACE(ch_ctl
);
480 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
486 WARN(1, "dp_aux_ch not started status 0x%08x\n",
492 /* Only 5 data registers! */
493 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
498 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
499 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
504 /* Must try at least 3 times according to DP spec */
505 for (try = 0; try < 5; try++) {
506 /* Load the send data into the aux channel data registers */
507 for (i
= 0; i
< send_bytes
; i
+= 4)
508 I915_WRITE(ch_data
+ i
,
509 pack_aux(send
+ i
, send_bytes
- i
));
511 /* Send the command and wait for it to complete */
512 I915_WRITE(ch_ctl
, send_ctl
);
514 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
516 /* Clear done status and any errors */
520 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
521 DP_AUX_CH_CTL_RECEIVE_ERROR
);
523 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
524 DP_AUX_CH_CTL_RECEIVE_ERROR
))
526 if (status
& DP_AUX_CH_CTL_DONE
)
529 if (status
& DP_AUX_CH_CTL_DONE
)
533 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
534 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
539 /* Check for timeout or receive error.
540 * Timeouts occur when the sink is not connected
542 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
543 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
548 /* Timeouts occur when the device isn't connected, so they're
549 * "normal" -- don't fill the kernel log with these */
550 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
551 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
556 /* Unload any bytes sent back from the other side */
557 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
558 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
559 if (recv_bytes
> recv_size
)
560 recv_bytes
= recv_size
;
562 for (i
= 0; i
< recv_bytes
; i
+= 4)
563 unpack_aux(I915_READ(ch_data
+ i
),
564 recv
+ i
, recv_bytes
- i
);
568 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
569 intel_aux_display_runtime_put(dev_priv
);
572 edp_panel_vdd_off(intel_dp
, false);
577 #define HEADER_SIZE 4
579 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
581 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
582 uint8_t txbuf
[20], rxbuf
[20];
583 size_t txsize
, rxsize
;
586 txbuf
[0] = msg
->request
<< 4;
587 txbuf
[1] = msg
->address
>> 8;
588 txbuf
[2] = msg
->address
& 0xff;
589 txbuf
[3] = msg
->size
- 1;
591 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
592 case DP_AUX_NATIVE_WRITE
:
593 case DP_AUX_I2C_WRITE
:
594 txsize
= HEADER_SIZE
+ msg
->size
;
597 if (WARN_ON(txsize
> 20))
600 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
602 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
604 msg
->reply
= rxbuf
[0] >> 4;
606 /* Return payload size. */
611 case DP_AUX_NATIVE_READ
:
612 case DP_AUX_I2C_READ
:
613 txsize
= HEADER_SIZE
;
614 rxsize
= msg
->size
+ 1;
616 if (WARN_ON(rxsize
> 20))
619 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
621 msg
->reply
= rxbuf
[0] >> 4;
623 * Assume happy day, and copy the data. The caller is
624 * expected to check msg->reply before touching it.
626 * Return payload size.
629 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
642 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
644 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
645 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
646 enum port port
= intel_dig_port
->port
;
647 const char *name
= NULL
;
652 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
656 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
660 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
664 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
672 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
674 intel_dp
->aux
.name
= name
;
675 intel_dp
->aux
.dev
= dev
->dev
;
676 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
678 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
679 connector
->base
.kdev
->kobj
.name
);
681 ret
= drm_dp_aux_register_i2c_bus(&intel_dp
->aux
);
683 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
688 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
689 &intel_dp
->aux
.ddc
.dev
.kobj
,
690 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
692 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
693 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
698 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
700 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
702 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
703 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
704 intel_connector_unregister(intel_connector
);
708 intel_dp_set_clock(struct intel_encoder
*encoder
,
709 struct intel_crtc_config
*pipe_config
, int link_bw
)
711 struct drm_device
*dev
= encoder
->base
.dev
;
712 const struct dp_link_dpll
*divisor
= NULL
;
717 count
= ARRAY_SIZE(gen4_dpll
);
718 } else if (IS_HASWELL(dev
)) {
719 /* Haswell has special-purpose DP DDI clocks. */
720 } else if (HAS_PCH_SPLIT(dev
)) {
722 count
= ARRAY_SIZE(pch_dpll
);
723 } else if (IS_VALLEYVIEW(dev
)) {
725 count
= ARRAY_SIZE(vlv_dpll
);
728 if (divisor
&& count
) {
729 for (i
= 0; i
< count
; i
++) {
730 if (link_bw
== divisor
[i
].link_bw
) {
731 pipe_config
->dpll
= divisor
[i
].dpll
;
732 pipe_config
->clock_set
= true;
740 intel_dp_compute_config(struct intel_encoder
*encoder
,
741 struct intel_crtc_config
*pipe_config
)
743 struct drm_device
*dev
= encoder
->base
.dev
;
744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
745 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
746 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
747 enum port port
= dp_to_dig_port(intel_dp
)->port
;
748 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
749 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
750 int lane_count
, clock
;
751 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
752 /* Conveniently, the link BW constants become indices with a shift...*/
753 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
755 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
756 int link_avail
, link_clock
;
758 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
759 pipe_config
->has_pch_encoder
= true;
761 pipe_config
->has_dp_encoder
= true;
763 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
764 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
766 if (!HAS_PCH_SPLIT(dev
))
767 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
768 intel_connector
->panel
.fitting_mode
);
770 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
771 intel_connector
->panel
.fitting_mode
);
774 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
777 DRM_DEBUG_KMS("DP link computation with max lane count %i "
778 "max bw %02x pixel clock %iKHz\n",
779 max_lane_count
, bws
[max_clock
],
780 adjusted_mode
->crtc_clock
);
782 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
784 bpp
= pipe_config
->pipe_bpp
;
785 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
786 dev_priv
->vbt
.edp_bpp
< bpp
) {
787 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
788 dev_priv
->vbt
.edp_bpp
);
789 bpp
= dev_priv
->vbt
.edp_bpp
;
792 for (; bpp
>= 6*3; bpp
-= 2*3) {
793 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
796 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
797 for (clock
= 0; clock
<= max_clock
; clock
++) {
798 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
799 link_avail
= intel_dp_max_data_rate(link_clock
,
802 if (mode_rate
<= link_avail
) {
812 if (intel_dp
->color_range_auto
) {
815 * CEA-861-E - 5.1 Default Encoding Parameters
816 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
818 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
819 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
821 intel_dp
->color_range
= 0;
824 if (intel_dp
->color_range
)
825 pipe_config
->limited_color_range
= true;
827 intel_dp
->link_bw
= bws
[clock
];
828 intel_dp
->lane_count
= lane_count
;
829 pipe_config
->pipe_bpp
= bpp
;
830 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
832 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
833 intel_dp
->link_bw
, intel_dp
->lane_count
,
834 pipe_config
->port_clock
, bpp
);
835 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
836 mode_rate
, link_avail
);
838 intel_link_compute_m_n(bpp
, lane_count
,
839 adjusted_mode
->crtc_clock
,
840 pipe_config
->port_clock
,
841 &pipe_config
->dp_m_n
);
843 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
848 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
850 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
851 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
852 struct drm_device
*dev
= crtc
->base
.dev
;
853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
856 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
857 dpa_ctl
= I915_READ(DP_A
);
858 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
860 if (crtc
->config
.port_clock
== 162000) {
861 /* For a long time we've carried around a ILK-DevA w/a for the
862 * 160MHz clock. If we're really unlucky, it's still required.
864 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
865 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
866 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
868 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
869 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
872 I915_WRITE(DP_A
, dpa_ctl
);
878 static void intel_dp_mode_set(struct intel_encoder
*encoder
)
880 struct drm_device
*dev
= encoder
->base
.dev
;
881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
882 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
883 enum port port
= dp_to_dig_port(intel_dp
)->port
;
884 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
885 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
888 * There are four kinds of DP registers:
895 * IBX PCH and CPU are the same for almost everything,
896 * except that the CPU DP PLL is configured in this
899 * CPT PCH is quite different, having many bits moved
900 * to the TRANS_DP_CTL register instead. That
901 * configuration happens (oddly) in ironlake_pch_enable
904 /* Preserve the BIOS-computed detected bit. This is
905 * supposed to be read-only.
907 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
909 /* Handle DP bits in common between all three register formats */
910 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
911 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
913 if (intel_dp
->has_audio
) {
914 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
915 pipe_name(crtc
->pipe
));
916 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
917 intel_write_eld(&encoder
->base
, adjusted_mode
);
920 /* Split out the IBX/CPU vs CPT settings */
922 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
923 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
924 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
925 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
926 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
927 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
929 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
930 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
932 intel_dp
->DP
|= crtc
->pipe
<< 29;
933 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
934 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
935 intel_dp
->DP
|= intel_dp
->color_range
;
937 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
938 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
939 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
940 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
941 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
943 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
944 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
947 intel_dp
->DP
|= DP_PIPEB_SELECT
;
949 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
952 if (port
== PORT_A
&& !IS_VALLEYVIEW(dev
))
953 ironlake_set_pll_cpu_edp(intel_dp
);
956 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
957 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
959 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
960 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
962 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
963 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
965 static void wait_panel_status(struct intel_dp
*intel_dp
,
969 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
971 u32 pp_stat_reg
, pp_ctrl_reg
;
973 pp_stat_reg
= _pp_stat_reg(intel_dp
);
974 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
976 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
978 I915_READ(pp_stat_reg
),
979 I915_READ(pp_ctrl_reg
));
981 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
982 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
983 I915_READ(pp_stat_reg
),
984 I915_READ(pp_ctrl_reg
));
987 DRM_DEBUG_KMS("Wait complete\n");
990 static void wait_panel_on(struct intel_dp
*intel_dp
)
992 DRM_DEBUG_KMS("Wait for panel power on\n");
993 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
996 static void wait_panel_off(struct intel_dp
*intel_dp
)
998 DRM_DEBUG_KMS("Wait for panel power off time\n");
999 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1002 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1004 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1006 /* When we disable the VDD override bit last we have to do the manual
1008 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1009 intel_dp
->panel_power_cycle_delay
);
1011 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1014 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1016 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1017 intel_dp
->backlight_on_delay
);
1020 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1022 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1023 intel_dp
->backlight_off_delay
);
1026 /* Read the current pp_control value, unlocking the register if it
1030 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1032 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1036 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1037 control
&= ~PANEL_UNLOCK_MASK
;
1038 control
|= PANEL_UNLOCK_REGS
;
1042 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1044 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1047 u32 pp_stat_reg
, pp_ctrl_reg
;
1048 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1050 if (!is_edp(intel_dp
))
1053 intel_dp
->want_panel_vdd
= true;
1055 if (edp_have_panel_vdd(intel_dp
))
1056 return need_to_disable
;
1058 intel_runtime_pm_get(dev_priv
);
1060 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1062 if (!edp_have_panel_power(intel_dp
))
1063 wait_panel_power_cycle(intel_dp
);
1065 pp
= ironlake_get_pp_control(intel_dp
);
1066 pp
|= EDP_FORCE_VDD
;
1068 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1069 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1071 I915_WRITE(pp_ctrl_reg
, pp
);
1072 POSTING_READ(pp_ctrl_reg
);
1073 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1074 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1076 * If the panel wasn't on, delay before accessing aux channel
1078 if (!edp_have_panel_power(intel_dp
)) {
1079 DRM_DEBUG_KMS("eDP was not running\n");
1080 msleep(intel_dp
->panel_power_up_delay
);
1083 return need_to_disable
;
1086 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1088 if (is_edp(intel_dp
)) {
1089 bool vdd
= _edp_panel_vdd_on(intel_dp
);
1091 WARN(!vdd
, "eDP VDD already requested on\n");
1095 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1097 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1100 u32 pp_stat_reg
, pp_ctrl_reg
;
1102 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1104 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1105 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1107 pp
= ironlake_get_pp_control(intel_dp
);
1108 pp
&= ~EDP_FORCE_VDD
;
1110 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1111 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1113 I915_WRITE(pp_ctrl_reg
, pp
);
1114 POSTING_READ(pp_ctrl_reg
);
1116 /* Make sure sequencer is idle before allowing subsequent activity */
1117 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1118 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1120 if ((pp
& POWER_TARGET_ON
) == 0)
1121 intel_dp
->last_power_cycle
= jiffies
;
1123 intel_runtime_pm_put(dev_priv
);
1127 static void edp_panel_vdd_work(struct work_struct
*__work
)
1129 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1130 struct intel_dp
, panel_vdd_work
);
1131 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1133 mutex_lock(&dev
->mode_config
.mutex
);
1134 edp_panel_vdd_off_sync(intel_dp
);
1135 mutex_unlock(&dev
->mode_config
.mutex
);
1138 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1140 if (!is_edp(intel_dp
))
1143 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1145 intel_dp
->want_panel_vdd
= false;
1148 edp_panel_vdd_off_sync(intel_dp
);
1151 * Queue the timer to fire a long
1152 * time from now (relative to the power down delay)
1153 * to keep the panel power up across a sequence of operations
1155 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1156 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1160 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1162 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1167 if (!is_edp(intel_dp
))
1170 DRM_DEBUG_KMS("Turn eDP power on\n");
1172 if (edp_have_panel_power(intel_dp
)) {
1173 DRM_DEBUG_KMS("eDP power already on\n");
1177 wait_panel_power_cycle(intel_dp
);
1179 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1180 pp
= ironlake_get_pp_control(intel_dp
);
1182 /* ILK workaround: disable reset around power sequence */
1183 pp
&= ~PANEL_POWER_RESET
;
1184 I915_WRITE(pp_ctrl_reg
, pp
);
1185 POSTING_READ(pp_ctrl_reg
);
1188 pp
|= POWER_TARGET_ON
;
1190 pp
|= PANEL_POWER_RESET
;
1192 I915_WRITE(pp_ctrl_reg
, pp
);
1193 POSTING_READ(pp_ctrl_reg
);
1195 wait_panel_on(intel_dp
);
1196 intel_dp
->last_power_on
= jiffies
;
1199 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1200 I915_WRITE(pp_ctrl_reg
, pp
);
1201 POSTING_READ(pp_ctrl_reg
);
1205 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1207 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1212 if (!is_edp(intel_dp
))
1215 DRM_DEBUG_KMS("Turn eDP power off\n");
1217 edp_wait_backlight_off(intel_dp
);
1219 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1221 pp
= ironlake_get_pp_control(intel_dp
);
1222 /* We need to switch off panel power _and_ force vdd, for otherwise some
1223 * panels get very unhappy and cease to work. */
1224 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1227 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1229 intel_dp
->want_panel_vdd
= false;
1231 I915_WRITE(pp_ctrl_reg
, pp
);
1232 POSTING_READ(pp_ctrl_reg
);
1234 intel_dp
->last_power_cycle
= jiffies
;
1235 wait_panel_off(intel_dp
);
1237 /* We got a reference when we enabled the VDD. */
1238 intel_runtime_pm_put(dev_priv
);
1241 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1243 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1244 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1249 if (!is_edp(intel_dp
))
1252 DRM_DEBUG_KMS("\n");
1254 * If we enable the backlight right away following a panel power
1255 * on, we may see slight flicker as the panel syncs with the eDP
1256 * link. So delay a bit to make sure the image is solid before
1257 * allowing it to appear.
1259 wait_backlight_on(intel_dp
);
1260 pp
= ironlake_get_pp_control(intel_dp
);
1261 pp
|= EDP_BLC_ENABLE
;
1263 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1265 I915_WRITE(pp_ctrl_reg
, pp
);
1266 POSTING_READ(pp_ctrl_reg
);
1268 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1271 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1273 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1278 if (!is_edp(intel_dp
))
1281 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1283 DRM_DEBUG_KMS("\n");
1284 pp
= ironlake_get_pp_control(intel_dp
);
1285 pp
&= ~EDP_BLC_ENABLE
;
1287 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1289 I915_WRITE(pp_ctrl_reg
, pp
);
1290 POSTING_READ(pp_ctrl_reg
);
1291 intel_dp
->last_backlight_off
= jiffies
;
1294 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1297 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1298 struct drm_device
*dev
= crtc
->dev
;
1299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1302 assert_pipe_disabled(dev_priv
,
1303 to_intel_crtc(crtc
)->pipe
);
1305 DRM_DEBUG_KMS("\n");
1306 dpa_ctl
= I915_READ(DP_A
);
1307 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1308 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1310 /* We don't adjust intel_dp->DP while tearing down the link, to
1311 * facilitate link retraining (e.g. after hotplug). Hence clear all
1312 * enable bits here to ensure that we don't enable too much. */
1313 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1314 intel_dp
->DP
|= DP_PLL_ENABLE
;
1315 I915_WRITE(DP_A
, intel_dp
->DP
);
1320 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1323 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1324 struct drm_device
*dev
= crtc
->dev
;
1325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1328 assert_pipe_disabled(dev_priv
,
1329 to_intel_crtc(crtc
)->pipe
);
1331 dpa_ctl
= I915_READ(DP_A
);
1332 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1333 "dp pll off, should be on\n");
1334 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1336 /* We can't rely on the value tracked for the DP register in
1337 * intel_dp->DP because link_down must not change that (otherwise link
1338 * re-training will fail. */
1339 dpa_ctl
&= ~DP_PLL_ENABLE
;
1340 I915_WRITE(DP_A
, dpa_ctl
);
1345 /* If the sink supports it, try to set the power state appropriately */
1346 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1350 /* Should have a valid DPCD by this point */
1351 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1354 if (mode
!= DRM_MODE_DPMS_ON
) {
1355 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1358 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1361 * When turning on, we need to retry for 1ms to give the sink
1364 for (i
= 0; i
< 3; i
++) {
1365 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1374 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1377 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1378 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1379 struct drm_device
*dev
= encoder
->base
.dev
;
1380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1381 enum intel_display_power_domain power_domain
;
1384 power_domain
= intel_display_port_power_domain(encoder
);
1385 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1388 tmp
= I915_READ(intel_dp
->output_reg
);
1390 if (!(tmp
& DP_PORT_EN
))
1393 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1394 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1395 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1396 *pipe
= PORT_TO_PIPE(tmp
);
1402 switch (intel_dp
->output_reg
) {
1404 trans_sel
= TRANS_DP_PORT_SEL_B
;
1407 trans_sel
= TRANS_DP_PORT_SEL_C
;
1410 trans_sel
= TRANS_DP_PORT_SEL_D
;
1417 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1418 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1424 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1425 intel_dp
->output_reg
);
1431 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1432 struct intel_crtc_config
*pipe_config
)
1434 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1436 struct drm_device
*dev
= encoder
->base
.dev
;
1437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1438 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1439 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1442 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1443 tmp
= I915_READ(intel_dp
->output_reg
);
1444 if (tmp
& DP_SYNC_HS_HIGH
)
1445 flags
|= DRM_MODE_FLAG_PHSYNC
;
1447 flags
|= DRM_MODE_FLAG_NHSYNC
;
1449 if (tmp
& DP_SYNC_VS_HIGH
)
1450 flags
|= DRM_MODE_FLAG_PVSYNC
;
1452 flags
|= DRM_MODE_FLAG_NVSYNC
;
1454 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1455 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1456 flags
|= DRM_MODE_FLAG_PHSYNC
;
1458 flags
|= DRM_MODE_FLAG_NHSYNC
;
1460 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1461 flags
|= DRM_MODE_FLAG_PVSYNC
;
1463 flags
|= DRM_MODE_FLAG_NVSYNC
;
1466 pipe_config
->adjusted_mode
.flags
|= flags
;
1468 pipe_config
->has_dp_encoder
= true;
1470 intel_dp_get_m_n(crtc
, pipe_config
);
1472 if (port
== PORT_A
) {
1473 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1474 pipe_config
->port_clock
= 162000;
1476 pipe_config
->port_clock
= 270000;
1479 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1480 &pipe_config
->dp_m_n
);
1482 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1483 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1485 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1487 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1488 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1490 * This is a big fat ugly hack.
1492 * Some machines in UEFI boot mode provide us a VBT that has 18
1493 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1494 * unknown we fail to light up. Yet the same BIOS boots up with
1495 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1496 * max, not what it tells us to use.
1498 * Note: This will still be broken if the eDP panel is not lit
1499 * up by the BIOS, and thus we can't get the mode at module
1502 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1503 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1504 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1508 static bool is_edp_psr(struct drm_device
*dev
)
1510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 return dev_priv
->psr
.sink_support
;
1515 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1522 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1525 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1526 struct edp_vsc_psr
*vsc_psr
)
1528 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1529 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1531 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1532 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1533 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1534 uint32_t *data
= (uint32_t *) vsc_psr
;
1537 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1538 the video DIP being updated before program video DIP data buffer
1539 registers for DIP being updated. */
1540 I915_WRITE(ctl_reg
, 0);
1541 POSTING_READ(ctl_reg
);
1543 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1544 if (i
< sizeof(struct edp_vsc_psr
))
1545 I915_WRITE(data_reg
+ i
, *data
++);
1547 I915_WRITE(data_reg
+ i
, 0);
1550 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1551 POSTING_READ(ctl_reg
);
1554 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1556 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1558 struct edp_vsc_psr psr_vsc
;
1560 if (intel_dp
->psr_setup_done
)
1563 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1564 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1565 psr_vsc
.sdp_header
.HB0
= 0;
1566 psr_vsc
.sdp_header
.HB1
= 0x7;
1567 psr_vsc
.sdp_header
.HB2
= 0x2;
1568 psr_vsc
.sdp_header
.HB3
= 0x8;
1569 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1571 /* Avoid continuous PSR exit by masking memup and hpd */
1572 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1573 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1575 intel_dp
->psr_setup_done
= true;
1578 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1580 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1582 uint32_t aux_clock_divider
;
1583 int precharge
= 0x3;
1584 int msg_size
= 5; /* Header(4) + Message(1) */
1586 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1588 /* Enable PSR in sink */
1589 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
)
1590 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1591 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1593 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1594 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1596 /* Setup AUX registers */
1597 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1598 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1599 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1600 DP_AUX_CH_CTL_TIME_OUT_400us
|
1601 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1602 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1603 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1606 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1608 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1610 uint32_t max_sleep_time
= 0x1f;
1611 uint32_t idle_frames
= 1;
1613 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1615 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
1616 val
|= EDP_PSR_LINK_STANDBY
;
1617 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1618 val
|= EDP_PSR_TP1_TIME_0us
;
1619 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1621 val
|= EDP_PSR_LINK_DISABLE
;
1623 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1624 IS_BROADWELL(dev
) ? 0 : link_entry_time
|
1625 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1626 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1630 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1632 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1633 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1635 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1636 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1637 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1638 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
1640 dev_priv
->psr
.source_ok
= false;
1642 if (!HAS_PSR(dev
)) {
1643 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1647 if ((intel_encoder
->type
!= INTEL_OUTPUT_EDP
) ||
1648 (dig_port
->port
!= PORT_A
)) {
1649 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1653 if (!i915
.enable_psr
) {
1654 DRM_DEBUG_KMS("PSR disable by flag\n");
1658 crtc
= dig_port
->base
.base
.crtc
;
1660 DRM_DEBUG_KMS("crtc not active for PSR\n");
1664 intel_crtc
= to_intel_crtc(crtc
);
1665 if (!intel_crtc_active(crtc
)) {
1666 DRM_DEBUG_KMS("crtc not active for PSR\n");
1670 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1671 if (obj
->tiling_mode
!= I915_TILING_X
||
1672 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1673 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1677 if (I915_READ(SPRCTL(intel_crtc
->pipe
)) & SPRITE_ENABLE
) {
1678 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1682 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1684 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1688 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1689 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1693 dev_priv
->psr
.source_ok
= true;
1697 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1699 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1701 if (!intel_edp_psr_match_conditions(intel_dp
) ||
1702 intel_edp_is_psr_enabled(dev
))
1705 /* Setup PSR once */
1706 intel_edp_psr_setup(intel_dp
);
1708 /* Enable PSR on the panel */
1709 intel_edp_psr_enable_sink(intel_dp
);
1711 /* Enable PSR on the host */
1712 intel_edp_psr_enable_source(intel_dp
);
1715 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1717 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1719 if (intel_edp_psr_match_conditions(intel_dp
) &&
1720 !intel_edp_is_psr_enabled(dev
))
1721 intel_edp_psr_do_enable(intel_dp
);
1724 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1726 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1729 if (!intel_edp_is_psr_enabled(dev
))
1732 I915_WRITE(EDP_PSR_CTL(dev
),
1733 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1735 /* Wait till PSR is idle */
1736 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1737 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1738 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1741 void intel_edp_psr_update(struct drm_device
*dev
)
1743 struct intel_encoder
*encoder
;
1744 struct intel_dp
*intel_dp
= NULL
;
1746 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
)
1747 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
1748 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1750 if (!is_edp_psr(dev
))
1753 if (!intel_edp_psr_match_conditions(intel_dp
))
1754 intel_edp_psr_disable(intel_dp
);
1756 if (!intel_edp_is_psr_enabled(dev
))
1757 intel_edp_psr_do_enable(intel_dp
);
1761 static void intel_disable_dp(struct intel_encoder
*encoder
)
1763 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1764 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1765 struct drm_device
*dev
= encoder
->base
.dev
;
1767 /* Make sure the panel is off before trying to change the mode. But also
1768 * ensure that we have vdd while we switch off the panel. */
1769 intel_edp_panel_vdd_on(intel_dp
);
1770 intel_edp_backlight_off(intel_dp
);
1771 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1772 intel_edp_panel_off(intel_dp
);
1774 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1775 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1776 intel_dp_link_down(intel_dp
);
1779 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1781 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1782 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1783 struct drm_device
*dev
= encoder
->base
.dev
;
1785 if (port
== PORT_A
|| IS_VALLEYVIEW(dev
)) {
1786 intel_dp_link_down(intel_dp
);
1787 if (!IS_VALLEYVIEW(dev
))
1788 ironlake_edp_pll_off(intel_dp
);
1792 static void intel_enable_dp(struct intel_encoder
*encoder
)
1794 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1795 struct drm_device
*dev
= encoder
->base
.dev
;
1796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1797 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1799 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1802 intel_edp_panel_vdd_on(intel_dp
);
1803 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1804 intel_dp_start_link_train(intel_dp
);
1805 intel_edp_panel_on(intel_dp
);
1806 edp_panel_vdd_off(intel_dp
, true);
1807 intel_dp_complete_link_train(intel_dp
);
1808 intel_dp_stop_link_train(intel_dp
);
1811 static void g4x_enable_dp(struct intel_encoder
*encoder
)
1813 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1815 intel_enable_dp(encoder
);
1816 intel_edp_backlight_on(intel_dp
);
1819 static void vlv_enable_dp(struct intel_encoder
*encoder
)
1821 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1823 intel_edp_backlight_on(intel_dp
);
1826 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
1828 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1829 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1831 if (dport
->port
== PORT_A
)
1832 ironlake_edp_pll_on(intel_dp
);
1835 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
1837 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1838 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1839 struct drm_device
*dev
= encoder
->base
.dev
;
1840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1841 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1842 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1843 int pipe
= intel_crtc
->pipe
;
1844 struct edp_power_seq power_seq
;
1847 mutex_lock(&dev_priv
->dpio_lock
);
1849 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1856 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1857 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1858 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1860 mutex_unlock(&dev_priv
->dpio_lock
);
1862 if (is_edp(intel_dp
)) {
1863 /* init power sequencer on this pipe and port */
1864 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
1865 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
1869 intel_enable_dp(encoder
);
1871 vlv_wait_port_ready(dev_priv
, dport
);
1874 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
1876 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1877 struct drm_device
*dev
= encoder
->base
.dev
;
1878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1879 struct intel_crtc
*intel_crtc
=
1880 to_intel_crtc(encoder
->base
.crtc
);
1881 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1882 int pipe
= intel_crtc
->pipe
;
1884 /* Program Tx lane resets to default */
1885 mutex_lock(&dev_priv
->dpio_lock
);
1886 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
1887 DPIO_PCS_TX_LANE2_RESET
|
1888 DPIO_PCS_TX_LANE1_RESET
);
1889 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
1890 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1891 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1892 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1893 DPIO_PCS_CLK_SOFT_RESET
);
1895 /* Fix up inter-pair skew failure */
1896 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
1897 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
1898 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
1899 mutex_unlock(&dev_priv
->dpio_lock
);
1903 * Native read with retry for link status and receiver capability reads for
1904 * cases where the sink may still be asleep.
1906 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1907 * supposed to retry 3 times per the spec.
1910 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
1911 void *buffer
, size_t size
)
1916 for (i
= 0; i
< 3; i
++) {
1917 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
1927 * Fetch AUX CH registers 0x202 - 0x207 which contain
1928 * link status information
1931 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1933 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
1936 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
1940 * These are source-specific values; current Intel hardware supports
1941 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1945 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1947 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1948 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1950 if (IS_VALLEYVIEW(dev
) || IS_BROADWELL(dev
))
1951 return DP_TRAIN_VOLTAGE_SWING_1200
;
1952 else if (IS_GEN7(dev
) && port
== PORT_A
)
1953 return DP_TRAIN_VOLTAGE_SWING_800
;
1954 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
1955 return DP_TRAIN_VOLTAGE_SWING_1200
;
1957 return DP_TRAIN_VOLTAGE_SWING_800
;
1961 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1963 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1964 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1966 if (IS_BROADWELL(dev
)) {
1967 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1968 case DP_TRAIN_VOLTAGE_SWING_400
:
1969 case DP_TRAIN_VOLTAGE_SWING_600
:
1970 return DP_TRAIN_PRE_EMPHASIS_6
;
1971 case DP_TRAIN_VOLTAGE_SWING_800
:
1972 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1973 case DP_TRAIN_VOLTAGE_SWING_1200
:
1975 return DP_TRAIN_PRE_EMPHASIS_0
;
1977 } else if (IS_HASWELL(dev
)) {
1978 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1979 case DP_TRAIN_VOLTAGE_SWING_400
:
1980 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1981 case DP_TRAIN_VOLTAGE_SWING_600
:
1982 return DP_TRAIN_PRE_EMPHASIS_6
;
1983 case DP_TRAIN_VOLTAGE_SWING_800
:
1984 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1985 case DP_TRAIN_VOLTAGE_SWING_1200
:
1987 return DP_TRAIN_PRE_EMPHASIS_0
;
1989 } else if (IS_VALLEYVIEW(dev
)) {
1990 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1991 case DP_TRAIN_VOLTAGE_SWING_400
:
1992 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1993 case DP_TRAIN_VOLTAGE_SWING_600
:
1994 return DP_TRAIN_PRE_EMPHASIS_6
;
1995 case DP_TRAIN_VOLTAGE_SWING_800
:
1996 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1997 case DP_TRAIN_VOLTAGE_SWING_1200
:
1999 return DP_TRAIN_PRE_EMPHASIS_0
;
2001 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2002 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2003 case DP_TRAIN_VOLTAGE_SWING_400
:
2004 return DP_TRAIN_PRE_EMPHASIS_6
;
2005 case DP_TRAIN_VOLTAGE_SWING_600
:
2006 case DP_TRAIN_VOLTAGE_SWING_800
:
2007 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2009 return DP_TRAIN_PRE_EMPHASIS_0
;
2012 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2013 case DP_TRAIN_VOLTAGE_SWING_400
:
2014 return DP_TRAIN_PRE_EMPHASIS_6
;
2015 case DP_TRAIN_VOLTAGE_SWING_600
:
2016 return DP_TRAIN_PRE_EMPHASIS_6
;
2017 case DP_TRAIN_VOLTAGE_SWING_800
:
2018 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2019 case DP_TRAIN_VOLTAGE_SWING_1200
:
2021 return DP_TRAIN_PRE_EMPHASIS_0
;
2026 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2028 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2030 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2031 struct intel_crtc
*intel_crtc
=
2032 to_intel_crtc(dport
->base
.base
.crtc
);
2033 unsigned long demph_reg_value
, preemph_reg_value
,
2034 uniqtranscale_reg_value
;
2035 uint8_t train_set
= intel_dp
->train_set
[0];
2036 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2037 int pipe
= intel_crtc
->pipe
;
2039 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2040 case DP_TRAIN_PRE_EMPHASIS_0
:
2041 preemph_reg_value
= 0x0004000;
2042 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2043 case DP_TRAIN_VOLTAGE_SWING_400
:
2044 demph_reg_value
= 0x2B405555;
2045 uniqtranscale_reg_value
= 0x552AB83A;
2047 case DP_TRAIN_VOLTAGE_SWING_600
:
2048 demph_reg_value
= 0x2B404040;
2049 uniqtranscale_reg_value
= 0x5548B83A;
2051 case DP_TRAIN_VOLTAGE_SWING_800
:
2052 demph_reg_value
= 0x2B245555;
2053 uniqtranscale_reg_value
= 0x5560B83A;
2055 case DP_TRAIN_VOLTAGE_SWING_1200
:
2056 demph_reg_value
= 0x2B405555;
2057 uniqtranscale_reg_value
= 0x5598DA3A;
2063 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2064 preemph_reg_value
= 0x0002000;
2065 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2066 case DP_TRAIN_VOLTAGE_SWING_400
:
2067 demph_reg_value
= 0x2B404040;
2068 uniqtranscale_reg_value
= 0x5552B83A;
2070 case DP_TRAIN_VOLTAGE_SWING_600
:
2071 demph_reg_value
= 0x2B404848;
2072 uniqtranscale_reg_value
= 0x5580B83A;
2074 case DP_TRAIN_VOLTAGE_SWING_800
:
2075 demph_reg_value
= 0x2B404040;
2076 uniqtranscale_reg_value
= 0x55ADDA3A;
2082 case DP_TRAIN_PRE_EMPHASIS_6
:
2083 preemph_reg_value
= 0x0000000;
2084 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2085 case DP_TRAIN_VOLTAGE_SWING_400
:
2086 demph_reg_value
= 0x2B305555;
2087 uniqtranscale_reg_value
= 0x5570B83A;
2089 case DP_TRAIN_VOLTAGE_SWING_600
:
2090 demph_reg_value
= 0x2B2B4040;
2091 uniqtranscale_reg_value
= 0x55ADDA3A;
2097 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2098 preemph_reg_value
= 0x0006000;
2099 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2100 case DP_TRAIN_VOLTAGE_SWING_400
:
2101 demph_reg_value
= 0x1B405555;
2102 uniqtranscale_reg_value
= 0x55ADDA3A;
2112 mutex_lock(&dev_priv
->dpio_lock
);
2113 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2114 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2115 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2116 uniqtranscale_reg_value
);
2117 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2118 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2119 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2120 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2121 mutex_unlock(&dev_priv
->dpio_lock
);
2127 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2128 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2133 uint8_t voltage_max
;
2134 uint8_t preemph_max
;
2136 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2137 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2138 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2146 voltage_max
= intel_dp_voltage_max(intel_dp
);
2147 if (v
>= voltage_max
)
2148 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2150 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2151 if (p
>= preemph_max
)
2152 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2154 for (lane
= 0; lane
< 4; lane
++)
2155 intel_dp
->train_set
[lane
] = v
| p
;
2159 intel_gen4_signal_levels(uint8_t train_set
)
2161 uint32_t signal_levels
= 0;
2163 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2164 case DP_TRAIN_VOLTAGE_SWING_400
:
2166 signal_levels
|= DP_VOLTAGE_0_4
;
2168 case DP_TRAIN_VOLTAGE_SWING_600
:
2169 signal_levels
|= DP_VOLTAGE_0_6
;
2171 case DP_TRAIN_VOLTAGE_SWING_800
:
2172 signal_levels
|= DP_VOLTAGE_0_8
;
2174 case DP_TRAIN_VOLTAGE_SWING_1200
:
2175 signal_levels
|= DP_VOLTAGE_1_2
;
2178 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2179 case DP_TRAIN_PRE_EMPHASIS_0
:
2181 signal_levels
|= DP_PRE_EMPHASIS_0
;
2183 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2184 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2186 case DP_TRAIN_PRE_EMPHASIS_6
:
2187 signal_levels
|= DP_PRE_EMPHASIS_6
;
2189 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2190 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2193 return signal_levels
;
2196 /* Gen6's DP voltage swing and pre-emphasis control */
2198 intel_gen6_edp_signal_levels(uint8_t train_set
)
2200 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2201 DP_TRAIN_PRE_EMPHASIS_MASK
);
2202 switch (signal_levels
) {
2203 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2204 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2205 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2206 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2207 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2208 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2209 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2210 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2211 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2212 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2213 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2214 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2215 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2216 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2218 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2219 "0x%x\n", signal_levels
);
2220 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2224 /* Gen7's DP voltage swing and pre-emphasis control */
2226 intel_gen7_edp_signal_levels(uint8_t train_set
)
2228 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2229 DP_TRAIN_PRE_EMPHASIS_MASK
);
2230 switch (signal_levels
) {
2231 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2232 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2233 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2234 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2235 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2236 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2238 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2239 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2240 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2241 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2243 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2244 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2245 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2246 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2249 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2250 "0x%x\n", signal_levels
);
2251 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2255 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2257 intel_hsw_signal_levels(uint8_t train_set
)
2259 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2260 DP_TRAIN_PRE_EMPHASIS_MASK
);
2261 switch (signal_levels
) {
2262 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2263 return DDI_BUF_EMP_400MV_0DB_HSW
;
2264 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2265 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2266 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2267 return DDI_BUF_EMP_400MV_6DB_HSW
;
2268 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2269 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2271 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2272 return DDI_BUF_EMP_600MV_0DB_HSW
;
2273 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2274 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2275 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2276 return DDI_BUF_EMP_600MV_6DB_HSW
;
2278 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2279 return DDI_BUF_EMP_800MV_0DB_HSW
;
2280 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2281 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2283 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2284 "0x%x\n", signal_levels
);
2285 return DDI_BUF_EMP_400MV_0DB_HSW
;
2290 intel_bdw_signal_levels(uint8_t train_set
)
2292 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2293 DP_TRAIN_PRE_EMPHASIS_MASK
);
2294 switch (signal_levels
) {
2295 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2296 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2297 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2298 return DDI_BUF_EMP_400MV_3_5DB_BDW
; /* Sel1 */
2299 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2300 return DDI_BUF_EMP_400MV_6DB_BDW
; /* Sel2 */
2302 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2303 return DDI_BUF_EMP_600MV_0DB_BDW
; /* Sel3 */
2304 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2305 return DDI_BUF_EMP_600MV_3_5DB_BDW
; /* Sel4 */
2306 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2307 return DDI_BUF_EMP_600MV_6DB_BDW
; /* Sel5 */
2309 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2310 return DDI_BUF_EMP_800MV_0DB_BDW
; /* Sel6 */
2311 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2312 return DDI_BUF_EMP_800MV_3_5DB_BDW
; /* Sel7 */
2314 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2315 return DDI_BUF_EMP_1200MV_0DB_BDW
; /* Sel8 */
2318 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2319 "0x%x\n", signal_levels
);
2320 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2324 /* Properly updates "DP" with the correct signal levels. */
2326 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2328 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2329 enum port port
= intel_dig_port
->port
;
2330 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2331 uint32_t signal_levels
, mask
;
2332 uint8_t train_set
= intel_dp
->train_set
[0];
2334 if (IS_BROADWELL(dev
)) {
2335 signal_levels
= intel_bdw_signal_levels(train_set
);
2336 mask
= DDI_BUF_EMP_MASK
;
2337 } else if (IS_HASWELL(dev
)) {
2338 signal_levels
= intel_hsw_signal_levels(train_set
);
2339 mask
= DDI_BUF_EMP_MASK
;
2340 } else if (IS_VALLEYVIEW(dev
)) {
2341 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2343 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2344 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2345 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2346 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2347 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2348 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2350 signal_levels
= intel_gen4_signal_levels(train_set
);
2351 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2354 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2356 *DP
= (*DP
& ~mask
) | signal_levels
;
2360 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2362 uint8_t dp_train_pat
)
2364 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2365 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2367 enum port port
= intel_dig_port
->port
;
2368 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2372 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2374 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2375 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2377 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2379 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2380 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2381 case DP_TRAINING_PATTERN_DISABLE
:
2382 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2385 case DP_TRAINING_PATTERN_1
:
2386 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2388 case DP_TRAINING_PATTERN_2
:
2389 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2391 case DP_TRAINING_PATTERN_3
:
2392 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2395 I915_WRITE(DP_TP_CTL(port
), temp
);
2397 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2398 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2400 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2401 case DP_TRAINING_PATTERN_DISABLE
:
2402 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2404 case DP_TRAINING_PATTERN_1
:
2405 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2407 case DP_TRAINING_PATTERN_2
:
2408 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2410 case DP_TRAINING_PATTERN_3
:
2411 DRM_ERROR("DP training pattern 3 not supported\n");
2412 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2417 *DP
&= ~DP_LINK_TRAIN_MASK
;
2419 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2420 case DP_TRAINING_PATTERN_DISABLE
:
2421 *DP
|= DP_LINK_TRAIN_OFF
;
2423 case DP_TRAINING_PATTERN_1
:
2424 *DP
|= DP_LINK_TRAIN_PAT_1
;
2426 case DP_TRAINING_PATTERN_2
:
2427 *DP
|= DP_LINK_TRAIN_PAT_2
;
2429 case DP_TRAINING_PATTERN_3
:
2430 DRM_ERROR("DP training pattern 3 not supported\n");
2431 *DP
|= DP_LINK_TRAIN_PAT_2
;
2436 I915_WRITE(intel_dp
->output_reg
, *DP
);
2437 POSTING_READ(intel_dp
->output_reg
);
2439 buf
[0] = dp_train_pat
;
2440 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2441 DP_TRAINING_PATTERN_DISABLE
) {
2442 /* don't write DP_TRAINING_LANEx_SET on disable */
2445 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2446 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
2447 len
= intel_dp
->lane_count
+ 1;
2450 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
2457 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2458 uint8_t dp_train_pat
)
2460 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
2461 intel_dp_set_signal_levels(intel_dp
, DP
);
2462 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
2466 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2467 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2469 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2470 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2474 intel_get_adjust_train(intel_dp
, link_status
);
2475 intel_dp_set_signal_levels(intel_dp
, DP
);
2477 I915_WRITE(intel_dp
->output_reg
, *DP
);
2478 POSTING_READ(intel_dp
->output_reg
);
2480 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
2481 intel_dp
->train_set
, intel_dp
->lane_count
);
2483 return ret
== intel_dp
->lane_count
;
2486 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
2488 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2489 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2491 enum port port
= intel_dig_port
->port
;
2497 val
= I915_READ(DP_TP_CTL(port
));
2498 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2499 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2500 I915_WRITE(DP_TP_CTL(port
), val
);
2503 * On PORT_A we can have only eDP in SST mode. There the only reason
2504 * we need to set idle transmission mode is to work around a HW issue
2505 * where we enable the pipe while not in idle link-training mode.
2506 * In this case there is requirement to wait for a minimum number of
2507 * idle patterns to be sent.
2512 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2514 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2517 /* Enable corresponding port and start training pattern 1 */
2519 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2521 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2522 struct drm_device
*dev
= encoder
->dev
;
2525 int voltage_tries
, loop_tries
;
2526 uint32_t DP
= intel_dp
->DP
;
2527 uint8_t link_config
[2];
2530 intel_ddi_prepare_link_retrain(encoder
);
2532 /* Write the link configuration data */
2533 link_config
[0] = intel_dp
->link_bw
;
2534 link_config
[1] = intel_dp
->lane_count
;
2535 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2536 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
2537 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
2540 link_config
[1] = DP_SET_ANSI_8B10B
;
2541 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
2545 /* clock recovery */
2546 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
2547 DP_TRAINING_PATTERN_1
|
2548 DP_LINK_SCRAMBLING_DISABLE
)) {
2549 DRM_ERROR("failed to enable link training\n");
2557 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2559 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2560 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2561 DRM_ERROR("failed to get link status\n");
2565 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2566 DRM_DEBUG_KMS("clock recovery OK\n");
2570 /* Check to see if we've tried the max voltage */
2571 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2572 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2574 if (i
== intel_dp
->lane_count
) {
2576 if (loop_tries
== 5) {
2577 DRM_ERROR("too many full retries, give up\n");
2580 intel_dp_reset_link_train(intel_dp
, &DP
,
2581 DP_TRAINING_PATTERN_1
|
2582 DP_LINK_SCRAMBLING_DISABLE
);
2587 /* Check to see if we've tried the same voltage 5 times */
2588 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
2590 if (voltage_tries
== 5) {
2591 DRM_ERROR("too many voltage retries, give up\n");
2596 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
2598 /* Update training set as requested by target */
2599 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2600 DRM_ERROR("failed to update link training\n");
2609 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
2611 bool channel_eq
= false;
2612 int tries
, cr_tries
;
2613 uint32_t DP
= intel_dp
->DP
;
2614 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
2616 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2617 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
2618 training_pattern
= DP_TRAINING_PATTERN_3
;
2620 /* channel equalization */
2621 if (!intel_dp_set_link_train(intel_dp
, &DP
,
2623 DP_LINK_SCRAMBLING_DISABLE
)) {
2624 DRM_ERROR("failed to start channel equalization\n");
2632 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2635 DRM_ERROR("failed to train DP, aborting\n");
2639 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
2640 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2641 DRM_ERROR("failed to get link status\n");
2645 /* Make sure clock is still ok */
2646 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2647 intel_dp_start_link_train(intel_dp
);
2648 intel_dp_set_link_train(intel_dp
, &DP
,
2650 DP_LINK_SCRAMBLING_DISABLE
);
2655 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2660 /* Try 5 times, then try clock recovery if that fails */
2662 intel_dp_link_down(intel_dp
);
2663 intel_dp_start_link_train(intel_dp
);
2664 intel_dp_set_link_train(intel_dp
, &DP
,
2666 DP_LINK_SCRAMBLING_DISABLE
);
2672 /* Update training set as requested by target */
2673 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2674 DRM_ERROR("failed to update link training\n");
2680 intel_dp_set_idle_link_train(intel_dp
);
2685 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2689 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
2691 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2692 DP_TRAINING_PATTERN_DISABLE
);
2696 intel_dp_link_down(struct intel_dp
*intel_dp
)
2698 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2699 enum port port
= intel_dig_port
->port
;
2700 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2702 struct intel_crtc
*intel_crtc
=
2703 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2704 uint32_t DP
= intel_dp
->DP
;
2707 * DDI code has a strict mode set sequence and we should try to respect
2708 * it, otherwise we might hang the machine in many different ways. So we
2709 * really should be disabling the port only on a complete crtc_disable
2710 * sequence. This function is just called under two conditions on DDI
2712 * - Link train failed while doing crtc_enable, and on this case we
2713 * really should respect the mode set sequence and wait for a
2715 * - Someone turned the monitor off and intel_dp_check_link_status
2716 * called us. We don't need to disable the whole port on this case, so
2717 * when someone turns the monitor on again,
2718 * intel_ddi_prepare_link_retrain will take care of redoing the link
2724 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2727 DRM_DEBUG_KMS("\n");
2729 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2730 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2731 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2733 DP
&= ~DP_LINK_TRAIN_MASK
;
2734 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2736 POSTING_READ(intel_dp
->output_reg
);
2738 /* We don't really know why we're doing this */
2739 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2741 if (HAS_PCH_IBX(dev
) &&
2742 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2743 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2745 /* Hardware workaround: leaving our transcoder select
2746 * set to transcoder B while it's off will prevent the
2747 * corresponding HDMI output on transcoder A.
2749 * Combine this with another hardware workaround:
2750 * transcoder select bit can only be cleared while the
2753 DP
&= ~DP_PIPEB_SELECT
;
2754 I915_WRITE(intel_dp
->output_reg
, DP
);
2756 /* Changes to enable or select take place the vblank
2757 * after being written.
2759 if (WARN_ON(crtc
== NULL
)) {
2760 /* We should never try to disable a port without a crtc
2761 * attached. For paranoia keep the code around for a
2763 POSTING_READ(intel_dp
->output_reg
);
2766 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2769 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2770 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2771 POSTING_READ(intel_dp
->output_reg
);
2772 msleep(intel_dp
->panel_power_down_delay
);
2776 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2778 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2779 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2782 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2784 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
2785 sizeof(intel_dp
->dpcd
)) < 0)
2786 return false; /* aux transfer failed */
2788 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2789 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2790 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2792 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2793 return false; /* DPCD not present */
2795 /* Check if the panel supports PSR */
2796 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
2797 if (is_edp(intel_dp
)) {
2798 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
2800 sizeof(intel_dp
->psr_dpcd
));
2801 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
2802 dev_priv
->psr
.sink_support
= true;
2803 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2807 /* Training Pattern 3 support */
2808 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
2809 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
2810 intel_dp
->use_tps3
= true;
2811 DRM_DEBUG_KMS("Displayport TPS3 supported");
2813 intel_dp
->use_tps3
= false;
2815 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2816 DP_DWN_STRM_PORT_PRESENT
))
2817 return true; /* native DP sink */
2819 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2820 return true; /* no per-port downstream info */
2822 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
2823 intel_dp
->downstream_ports
,
2824 DP_MAX_DOWNSTREAM_PORTS
) < 0)
2825 return false; /* downstream port status fetch failed */
2831 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2835 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2838 intel_edp_panel_vdd_on(intel_dp
);
2840 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
2841 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2842 buf
[0], buf
[1], buf
[2]);
2844 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
2845 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2846 buf
[0], buf
[1], buf
[2]);
2848 edp_panel_vdd_off(intel_dp
, false);
2851 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
2853 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2854 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2855 struct intel_crtc
*intel_crtc
=
2856 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2859 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
2862 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
2865 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
2866 DP_TEST_SINK_START
) < 0)
2869 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2870 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2871 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2873 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
2876 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
2881 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2883 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2884 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2885 sink_irq_vector
, 1) == 1;
2889 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2891 /* NAK by default */
2892 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2896 * According to DP spec
2899 * 2. Configure link according to Receiver Capabilities
2900 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2901 * 4. Check link status on receipt of hot-plug interrupt
2905 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2907 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2909 u8 link_status
[DP_LINK_STATUS_SIZE
];
2911 if (!intel_encoder
->connectors_active
)
2914 if (WARN_ON(!intel_encoder
->base
.crtc
))
2917 /* Try to read receiver status if the link appears to be up */
2918 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2922 /* Now read the DPCD to see if it's actually running */
2923 if (!intel_dp_get_dpcd(intel_dp
)) {
2927 /* Try to read the source of the interrupt */
2928 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2929 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2930 /* Clear interrupt source */
2931 drm_dp_dpcd_writeb(&intel_dp
->aux
,
2932 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2935 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2936 intel_dp_handle_test_request(intel_dp
);
2937 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2938 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2941 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2942 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2943 drm_get_encoder_name(&intel_encoder
->base
));
2944 intel_dp_start_link_train(intel_dp
);
2945 intel_dp_complete_link_train(intel_dp
);
2946 intel_dp_stop_link_train(intel_dp
);
2950 /* XXX this is probably wrong for multiple downstream ports */
2951 static enum drm_connector_status
2952 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2954 uint8_t *dpcd
= intel_dp
->dpcd
;
2957 if (!intel_dp_get_dpcd(intel_dp
))
2958 return connector_status_disconnected
;
2960 /* if there's no downstream port, we're done */
2961 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2962 return connector_status_connected
;
2964 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2965 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2966 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
2969 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
2971 return connector_status_unknown
;
2973 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2974 : connector_status_disconnected
;
2977 /* If no HPD, poke DDC gently */
2978 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
2979 return connector_status_connected
;
2981 /* Well we tried, say unknown for unreliable port types */
2982 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
2983 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2984 if (type
== DP_DS_PORT_TYPE_VGA
||
2985 type
== DP_DS_PORT_TYPE_NON_EDID
)
2986 return connector_status_unknown
;
2988 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2989 DP_DWN_STRM_PORT_TYPE_MASK
;
2990 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
2991 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
2992 return connector_status_unknown
;
2995 /* Anything else is out of spec, warn and ignore */
2996 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2997 return connector_status_disconnected
;
3000 static enum drm_connector_status
3001 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3003 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3005 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3006 enum drm_connector_status status
;
3008 /* Can't disconnect eDP, but you can close the lid... */
3009 if (is_edp(intel_dp
)) {
3010 status
= intel_panel_detect(dev
);
3011 if (status
== connector_status_unknown
)
3012 status
= connector_status_connected
;
3016 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3017 return connector_status_disconnected
;
3019 return intel_dp_detect_dpcd(intel_dp
);
3022 static enum drm_connector_status
3023 g4x_dp_detect(struct intel_dp
*intel_dp
)
3025 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3027 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3030 /* Can't disconnect eDP, but you can close the lid... */
3031 if (is_edp(intel_dp
)) {
3032 enum drm_connector_status status
;
3034 status
= intel_panel_detect(dev
);
3035 if (status
== connector_status_unknown
)
3036 status
= connector_status_connected
;
3040 if (IS_VALLEYVIEW(dev
)) {
3041 switch (intel_dig_port
->port
) {
3043 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3046 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3049 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3052 return connector_status_unknown
;
3055 switch (intel_dig_port
->port
) {
3057 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3060 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3063 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3066 return connector_status_unknown
;
3070 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3071 return connector_status_disconnected
;
3073 return intel_dp_detect_dpcd(intel_dp
);
3076 static struct edid
*
3077 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3079 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3081 /* use cached edid if we have one */
3082 if (intel_connector
->edid
) {
3084 if (IS_ERR(intel_connector
->edid
))
3087 return drm_edid_duplicate(intel_connector
->edid
);
3090 return drm_get_edid(connector
, adapter
);
3094 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3096 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3098 /* use cached edid if we have one */
3099 if (intel_connector
->edid
) {
3101 if (IS_ERR(intel_connector
->edid
))
3104 return intel_connector_update_modes(connector
,
3105 intel_connector
->edid
);
3108 return intel_ddc_get_modes(connector
, adapter
);
3111 static enum drm_connector_status
3112 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3114 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3115 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3116 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3117 struct drm_device
*dev
= connector
->dev
;
3118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3119 enum drm_connector_status status
;
3120 enum intel_display_power_domain power_domain
;
3121 struct edid
*edid
= NULL
;
3123 intel_runtime_pm_get(dev_priv
);
3125 power_domain
= intel_display_port_power_domain(intel_encoder
);
3126 intel_display_power_get(dev_priv
, power_domain
);
3128 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3129 connector
->base
.id
, drm_get_connector_name(connector
));
3131 intel_dp
->has_audio
= false;
3133 if (HAS_PCH_SPLIT(dev
))
3134 status
= ironlake_dp_detect(intel_dp
);
3136 status
= g4x_dp_detect(intel_dp
);
3138 if (status
!= connector_status_connected
)
3141 intel_dp_probe_oui(intel_dp
);
3143 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3144 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3146 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3148 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3153 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3154 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3155 status
= connector_status_connected
;
3158 intel_display_power_put(dev_priv
, power_domain
);
3160 intel_runtime_pm_put(dev_priv
);
3165 static int intel_dp_get_modes(struct drm_connector
*connector
)
3167 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3168 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3169 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3170 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3171 struct drm_device
*dev
= connector
->dev
;
3172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3173 enum intel_display_power_domain power_domain
;
3176 /* We should parse the EDID data and find out if it has an audio sink
3179 power_domain
= intel_display_port_power_domain(intel_encoder
);
3180 intel_display_power_get(dev_priv
, power_domain
);
3182 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3183 intel_display_power_put(dev_priv
, power_domain
);
3187 /* if eDP has no EDID, fall back to fixed mode */
3188 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3189 struct drm_display_mode
*mode
;
3190 mode
= drm_mode_duplicate(dev
,
3191 intel_connector
->panel
.fixed_mode
);
3193 drm_mode_probed_add(connector
, mode
);
3201 intel_dp_detect_audio(struct drm_connector
*connector
)
3203 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3204 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3205 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3206 struct drm_device
*dev
= connector
->dev
;
3207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3208 enum intel_display_power_domain power_domain
;
3210 bool has_audio
= false;
3212 power_domain
= intel_display_port_power_domain(intel_encoder
);
3213 intel_display_power_get(dev_priv
, power_domain
);
3215 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3217 has_audio
= drm_detect_monitor_audio(edid
);
3221 intel_display_power_put(dev_priv
, power_domain
);
3227 intel_dp_set_property(struct drm_connector
*connector
,
3228 struct drm_property
*property
,
3231 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3232 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3233 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3234 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3237 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3241 if (property
== dev_priv
->force_audio_property
) {
3245 if (i
== intel_dp
->force_audio
)
3248 intel_dp
->force_audio
= i
;
3250 if (i
== HDMI_AUDIO_AUTO
)
3251 has_audio
= intel_dp_detect_audio(connector
);
3253 has_audio
= (i
== HDMI_AUDIO_ON
);
3255 if (has_audio
== intel_dp
->has_audio
)
3258 intel_dp
->has_audio
= has_audio
;
3262 if (property
== dev_priv
->broadcast_rgb_property
) {
3263 bool old_auto
= intel_dp
->color_range_auto
;
3264 uint32_t old_range
= intel_dp
->color_range
;
3267 case INTEL_BROADCAST_RGB_AUTO
:
3268 intel_dp
->color_range_auto
= true;
3270 case INTEL_BROADCAST_RGB_FULL
:
3271 intel_dp
->color_range_auto
= false;
3272 intel_dp
->color_range
= 0;
3274 case INTEL_BROADCAST_RGB_LIMITED
:
3275 intel_dp
->color_range_auto
= false;
3276 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3282 if (old_auto
== intel_dp
->color_range_auto
&&
3283 old_range
== intel_dp
->color_range
)
3289 if (is_edp(intel_dp
) &&
3290 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3291 if (val
== DRM_MODE_SCALE_NONE
) {
3292 DRM_DEBUG_KMS("no scaling not supported\n");
3296 if (intel_connector
->panel
.fitting_mode
== val
) {
3297 /* the eDP scaling property is not changed */
3300 intel_connector
->panel
.fitting_mode
= val
;
3308 if (intel_encoder
->base
.crtc
)
3309 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3315 intel_dp_connector_destroy(struct drm_connector
*connector
)
3317 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3319 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3320 kfree(intel_connector
->edid
);
3322 /* Can't call is_edp() since the encoder may have been destroyed
3324 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3325 intel_panel_fini(&intel_connector
->panel
);
3327 drm_connector_cleanup(connector
);
3331 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3333 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3334 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3335 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3337 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
3338 drm_encoder_cleanup(encoder
);
3339 if (is_edp(intel_dp
)) {
3340 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3341 mutex_lock(&dev
->mode_config
.mutex
);
3342 edp_panel_vdd_off_sync(intel_dp
);
3343 mutex_unlock(&dev
->mode_config
.mutex
);
3345 kfree(intel_dig_port
);
3348 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
3349 .dpms
= intel_connector_dpms
,
3350 .detect
= intel_dp_detect
,
3351 .fill_modes
= drm_helper_probe_single_connector_modes
,
3352 .set_property
= intel_dp_set_property
,
3353 .destroy
= intel_dp_connector_destroy
,
3356 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
3357 .get_modes
= intel_dp_get_modes
,
3358 .mode_valid
= intel_dp_mode_valid
,
3359 .best_encoder
= intel_best_encoder
,
3362 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
3363 .destroy
= intel_dp_encoder_destroy
,
3367 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
3369 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3371 intel_dp_check_link_status(intel_dp
);
3374 /* Return which DP Port should be selected for Transcoder DP control */
3376 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
3378 struct drm_device
*dev
= crtc
->dev
;
3379 struct intel_encoder
*intel_encoder
;
3380 struct intel_dp
*intel_dp
;
3382 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3383 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3385 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
3386 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
3387 return intel_dp
->output_reg
;
3393 /* check the VBT to see whether the eDP is on DP-D port */
3394 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
3396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3397 union child_device_config
*p_child
;
3399 static const short port_mapping
[] = {
3400 [PORT_B
] = PORT_IDPB
,
3401 [PORT_C
] = PORT_IDPC
,
3402 [PORT_D
] = PORT_IDPD
,
3408 if (!dev_priv
->vbt
.child_dev_num
)
3411 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
3412 p_child
= dev_priv
->vbt
.child_dev
+ i
;
3414 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
3415 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
3416 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
3423 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
3425 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3427 intel_attach_force_audio_property(connector
);
3428 intel_attach_broadcast_rgb_property(connector
);
3429 intel_dp
->color_range_auto
= true;
3431 if (is_edp(intel_dp
)) {
3432 drm_mode_create_scaling_mode_property(connector
->dev
);
3433 drm_object_attach_property(
3435 connector
->dev
->mode_config
.scaling_mode_property
,
3436 DRM_MODE_SCALE_ASPECT
);
3437 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
3441 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
3443 intel_dp
->last_power_cycle
= jiffies
;
3444 intel_dp
->last_power_on
= jiffies
;
3445 intel_dp
->last_backlight_off
= jiffies
;
3449 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
3450 struct intel_dp
*intel_dp
,
3451 struct edp_power_seq
*out
)
3453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3454 struct edp_power_seq cur
, vbt
, spec
, final
;
3455 u32 pp_on
, pp_off
, pp_div
, pp
;
3456 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
3458 if (HAS_PCH_SPLIT(dev
)) {
3459 pp_ctrl_reg
= PCH_PP_CONTROL
;
3460 pp_on_reg
= PCH_PP_ON_DELAYS
;
3461 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3462 pp_div_reg
= PCH_PP_DIVISOR
;
3464 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3466 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
3467 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3468 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3469 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3472 /* Workaround: Need to write PP_CONTROL with the unlock key as
3473 * the very first thing. */
3474 pp
= ironlake_get_pp_control(intel_dp
);
3475 I915_WRITE(pp_ctrl_reg
, pp
);
3477 pp_on
= I915_READ(pp_on_reg
);
3478 pp_off
= I915_READ(pp_off_reg
);
3479 pp_div
= I915_READ(pp_div_reg
);
3481 /* Pull timing values out of registers */
3482 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
3483 PANEL_POWER_UP_DELAY_SHIFT
;
3485 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
3486 PANEL_LIGHT_ON_DELAY_SHIFT
;
3488 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
3489 PANEL_LIGHT_OFF_DELAY_SHIFT
;
3491 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
3492 PANEL_POWER_DOWN_DELAY_SHIFT
;
3494 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
3495 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
3497 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3498 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
3500 vbt
= dev_priv
->vbt
.edp_pps
;
3502 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3503 * our hw here, which are all in 100usec. */
3504 spec
.t1_t3
= 210 * 10;
3505 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
3506 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
3507 spec
.t10
= 500 * 10;
3508 /* This one is special and actually in units of 100ms, but zero
3509 * based in the hw (so we need to add 100 ms). But the sw vbt
3510 * table multiplies it with 1000 to make it in units of 100usec,
3512 spec
.t11_t12
= (510 + 100) * 10;
3514 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3515 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
3517 /* Use the max of the register settings and vbt. If both are
3518 * unset, fall back to the spec limits. */
3519 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3521 max(cur.field, vbt.field))
3522 assign_final(t1_t3
);
3526 assign_final(t11_t12
);
3529 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3530 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
3531 intel_dp
->backlight_on_delay
= get_delay(t8
);
3532 intel_dp
->backlight_off_delay
= get_delay(t9
);
3533 intel_dp
->panel_power_down_delay
= get_delay(t10
);
3534 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
3537 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3538 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
3539 intel_dp
->panel_power_cycle_delay
);
3541 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3542 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
3549 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
3550 struct intel_dp
*intel_dp
,
3551 struct edp_power_seq
*seq
)
3553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3554 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
3555 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
3556 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
3558 if (HAS_PCH_SPLIT(dev
)) {
3559 pp_on_reg
= PCH_PP_ON_DELAYS
;
3560 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3561 pp_div_reg
= PCH_PP_DIVISOR
;
3563 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3565 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3566 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3567 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3571 * And finally store the new values in the power sequencer. The
3572 * backlight delays are set to 1 because we do manual waits on them. For
3573 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3574 * we'll end up waiting for the backlight off delay twice: once when we
3575 * do the manual sleep, and once when we disable the panel and wait for
3576 * the PP_STATUS bit to become zero.
3578 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
3579 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
3580 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
3581 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
3582 /* Compute the divisor for the pp clock, simply match the Bspec
3584 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
3585 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
3586 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
3588 /* Haswell doesn't have any port selection bits for the panel
3589 * power sequencer any more. */
3590 if (IS_VALLEYVIEW(dev
)) {
3591 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
3592 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
3594 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
3595 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
3596 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
3597 port_sel
= PANEL_PORT_SELECT_DPA
;
3599 port_sel
= PANEL_PORT_SELECT_DPD
;
3604 I915_WRITE(pp_on_reg
, pp_on
);
3605 I915_WRITE(pp_off_reg
, pp_off
);
3606 I915_WRITE(pp_div_reg
, pp_div
);
3608 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3609 I915_READ(pp_on_reg
),
3610 I915_READ(pp_off_reg
),
3611 I915_READ(pp_div_reg
));
3614 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
3615 struct intel_connector
*intel_connector
,
3616 struct edp_power_seq
*power_seq
)
3618 struct drm_connector
*connector
= &intel_connector
->base
;
3619 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3620 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3622 struct drm_display_mode
*fixed_mode
= NULL
;
3624 struct drm_display_mode
*scan
;
3627 if (!is_edp(intel_dp
))
3630 /* Cache DPCD and EDID for edp. */
3631 intel_edp_panel_vdd_on(intel_dp
);
3632 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
3633 edp_panel_vdd_off(intel_dp
, false);
3636 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3637 dev_priv
->no_aux_handshake
=
3638 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3639 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3641 /* if this fails, presume the device is a ghost */
3642 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3646 /* We now know it's not a ghost, init power sequence regs. */
3647 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
3649 mutex_lock(&dev
->mode_config
.mutex
);
3650 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
3652 if (drm_add_edid_modes(connector
, edid
)) {
3653 drm_mode_connector_update_edid_property(connector
,
3655 drm_edid_to_eld(connector
, edid
);
3658 edid
= ERR_PTR(-EINVAL
);
3661 edid
= ERR_PTR(-ENOENT
);
3663 intel_connector
->edid
= edid
;
3665 /* prefer fixed mode from EDID if available */
3666 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
3667 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
3668 fixed_mode
= drm_mode_duplicate(dev
, scan
);
3673 /* fallback to VBT if available for eDP */
3674 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
3675 fixed_mode
= drm_mode_duplicate(dev
,
3676 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
3678 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
3680 mutex_unlock(&dev
->mode_config
.mutex
);
3682 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
3683 intel_panel_setup_backlight(connector
);
3689 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
3690 struct intel_connector
*intel_connector
)
3692 struct drm_connector
*connector
= &intel_connector
->base
;
3693 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3694 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3695 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3697 enum port port
= intel_dig_port
->port
;
3698 struct edp_power_seq power_seq
= { 0 };
3701 /* intel_dp vfuncs */
3702 if (IS_VALLEYVIEW(dev
))
3703 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
3704 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3705 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
3706 else if (HAS_PCH_SPLIT(dev
))
3707 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
3709 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
3711 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
3713 /* Preserve the current hw state. */
3714 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
3715 intel_dp
->attached_connector
= intel_connector
;
3717 if (intel_dp_is_edp(dev
, port
))
3718 type
= DRM_MODE_CONNECTOR_eDP
;
3720 type
= DRM_MODE_CONNECTOR_DisplayPort
;
3723 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3724 * for DP the encoder type can be set by the caller to
3725 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3727 if (type
== DRM_MODE_CONNECTOR_eDP
)
3728 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
3730 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3731 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
3734 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
3735 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
3737 connector
->interlace_allowed
= true;
3738 connector
->doublescan_allowed
= 0;
3740 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
3741 edp_panel_vdd_work
);
3743 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3744 drm_sysfs_connector_add(connector
);
3747 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3749 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3750 intel_connector
->unregister
= intel_dp_connector_unregister
;
3752 /* Set up the hotplug pin. */
3755 intel_encoder
->hpd_pin
= HPD_PORT_A
;
3758 intel_encoder
->hpd_pin
= HPD_PORT_B
;
3761 intel_encoder
->hpd_pin
= HPD_PORT_C
;
3764 intel_encoder
->hpd_pin
= HPD_PORT_D
;
3770 if (is_edp(intel_dp
)) {
3771 intel_dp_init_panel_power_timestamps(intel_dp
);
3772 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
3775 intel_dp_aux_init(intel_dp
, intel_connector
);
3777 intel_dp
->psr_setup_done
= false;
3779 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
3780 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
3781 if (is_edp(intel_dp
)) {
3782 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3783 mutex_lock(&dev
->mode_config
.mutex
);
3784 edp_panel_vdd_off_sync(intel_dp
);
3785 mutex_unlock(&dev
->mode_config
.mutex
);
3787 drm_sysfs_connector_remove(connector
);
3788 drm_connector_cleanup(connector
);
3792 intel_dp_add_properties(intel_dp
, connector
);
3794 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3795 * 0xd. Failure to do so will result in spurious interrupts being
3796 * generated on the port when a cable is not attached.
3798 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
3799 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
3800 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
3807 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
3809 struct intel_digital_port
*intel_dig_port
;
3810 struct intel_encoder
*intel_encoder
;
3811 struct drm_encoder
*encoder
;
3812 struct intel_connector
*intel_connector
;
3814 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3815 if (!intel_dig_port
)
3818 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
3819 if (!intel_connector
) {
3820 kfree(intel_dig_port
);
3824 intel_encoder
= &intel_dig_port
->base
;
3825 encoder
= &intel_encoder
->base
;
3827 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
3828 DRM_MODE_ENCODER_TMDS
);
3830 intel_encoder
->compute_config
= intel_dp_compute_config
;
3831 intel_encoder
->mode_set
= intel_dp_mode_set
;
3832 intel_encoder
->disable
= intel_disable_dp
;
3833 intel_encoder
->post_disable
= intel_post_disable_dp
;
3834 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
3835 intel_encoder
->get_config
= intel_dp_get_config
;
3836 if (IS_VALLEYVIEW(dev
)) {
3837 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
3838 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
3839 intel_encoder
->enable
= vlv_enable_dp
;
3841 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
3842 intel_encoder
->enable
= g4x_enable_dp
;
3845 intel_dig_port
->port
= port
;
3846 intel_dig_port
->dp
.output_reg
= output_reg
;
3848 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3849 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3850 intel_encoder
->cloneable
= 0;
3851 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
3853 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
3854 drm_encoder_cleanup(encoder
);
3855 kfree(intel_dig_port
);
3856 kfree(intel_connector
);