2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll
[] = {
48 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
50 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
53 static const struct dp_link_dpll pch_dpll
[] = {
55 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
57 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
60 static const struct dp_link_dpll vlv_dpll
[] = {
62 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 5, .m2
= 3 } },
64 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp
*intel_dp
)
76 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
78 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
81 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
83 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
85 return intel_dig_port
->base
.base
.dev
;
88 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
90 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
93 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
96 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
98 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
100 switch (max_link_bw
) {
101 case DP_LINK_BW_1_62
:
104 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw
= DP_LINK_BW_2_7
;
108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
110 max_link_bw
= DP_LINK_BW_1_62
;
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
122 * 270000 * 1 * 8 / 10 == 216000
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
134 intel_dp_link_required(int pixel_clock
, int bpp
)
136 return (pixel_clock
* bpp
+ 9) / 10;
140 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
142 return (max_link_clock
* max_lanes
* 8) / 10;
146 intel_dp_mode_valid(struct drm_connector
*connector
,
147 struct drm_display_mode
*mode
)
149 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
150 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
151 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
152 int target_clock
= mode
->clock
;
153 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
155 if (is_edp(intel_dp
) && fixed_mode
) {
156 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
159 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
162 target_clock
= fixed_mode
->clock
;
165 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
166 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
168 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
169 mode_rate
= intel_dp_link_required(target_clock
, 18);
171 if (mode_rate
> max_rate
)
172 return MODE_CLOCK_HIGH
;
174 if (mode
->clock
< 10000)
175 return MODE_CLOCK_LOW
;
177 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
178 return MODE_H_ILLEGAL
;
184 pack_aux(uint8_t *src
, int src_bytes
)
191 for (i
= 0; i
< src_bytes
; i
++)
192 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
197 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
202 for (i
= 0; i
< dst_bytes
; i
++)
203 dst
[i
] = src
>> ((3-i
) * 8);
206 /* hrawclock is 1/4 the FSB frequency */
208 intel_hrawclk(struct drm_device
*dev
)
210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev
))
217 clkcfg
= I915_READ(CLKCFG
);
218 switch (clkcfg
& CLKCFG_FSB_MASK
) {
227 case CLKCFG_FSB_1067
:
229 case CLKCFG_FSB_1333
:
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600
:
233 case CLKCFG_FSB_1600_ALT
:
241 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
242 struct intel_dp
*intel_dp
,
243 struct edp_power_seq
*out
);
245 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
246 struct intel_dp
*intel_dp
,
247 struct edp_power_seq
*out
);
250 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
252 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
253 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
254 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
256 enum port port
= intel_dig_port
->port
;
259 /* modeset should have pipe */
261 return to_intel_crtc(crtc
)->pipe
;
263 /* init time, try to find a pipe with this port selected */
264 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
265 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
266 PANEL_PORT_SELECT_MASK
;
267 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
269 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
277 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
279 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
281 if (HAS_PCH_SPLIT(dev
))
282 return PCH_PP_CONTROL
;
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
287 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
289 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
291 if (HAS_PCH_SPLIT(dev
))
292 return PCH_PP_STATUS
;
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
297 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
299 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
302 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
305 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
307 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 return (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
314 intel_dp_check_edp(struct intel_dp
*intel_dp
)
316 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
319 if (!is_edp(intel_dp
))
322 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
325 I915_READ(_pp_stat_reg(intel_dp
)),
326 I915_READ(_pp_ctrl_reg(intel_dp
)));
331 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
333 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
334 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
336 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
342 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
343 msecs_to_jiffies_timeout(10));
345 done
= wait_for_atomic(C
, 10) == 0;
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
354 static uint32_t get_aux_clock_divider(struct intel_dp
*intel_dp
,
357 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
358 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
361 /* The clock divider is based off the hrawclk,
362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
365 * Note that PCH attached eDP panels should use a 125MHz input
368 if (IS_VALLEYVIEW(dev
)) {
369 return index
? 0 : 100;
370 } else if (intel_dig_port
->port
== PORT_A
) {
374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
375 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
378 return 225; /* eDP input clock at 450Mhz */
379 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
380 /* Workaround for non-ULT HSW */
386 } else if (HAS_PCH_SPLIT(dev
)) {
387 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
389 return index
? 0 :intel_hrawclk(dev
) / 2;
394 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
395 uint8_t *send
, int send_bytes
,
396 uint8_t *recv
, int recv_size
)
398 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
399 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
401 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
402 uint32_t ch_data
= ch_ctl
+ 4;
403 uint32_t aux_clock_divider
;
404 int i
, ret
, recv_bytes
;
406 int try, precharge
, clock
= 0;
407 bool has_aux_irq
= INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
);
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
413 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
415 intel_dp_check_edp(intel_dp
);
422 intel_aux_display_runtime_get(dev_priv
);
424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
426 status
= I915_READ_NOTRACE(ch_ctl
);
427 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
439 /* Only 5 data registers! */
440 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
445 while ((aux_clock_divider
= get_aux_clock_divider(intel_dp
, clock
++))) {
446 /* Must try at least 3 times according to DP spec */
447 for (try = 0; try < 5; try++) {
448 /* Load the send data into the aux channel data registers */
449 for (i
= 0; i
< send_bytes
; i
+= 4)
450 I915_WRITE(ch_data
+ i
,
451 pack_aux(send
+ i
, send_bytes
- i
));
453 /* Send the command and wait for it to complete */
455 DP_AUX_CH_CTL_SEND_BUSY
|
456 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
457 DP_AUX_CH_CTL_TIME_OUT_400us
|
458 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
459 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
460 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
462 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
463 DP_AUX_CH_CTL_RECEIVE_ERROR
);
465 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
467 /* Clear done status and any errors */
471 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
472 DP_AUX_CH_CTL_RECEIVE_ERROR
);
474 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
475 DP_AUX_CH_CTL_RECEIVE_ERROR
))
477 if (status
& DP_AUX_CH_CTL_DONE
)
480 if (status
& DP_AUX_CH_CTL_DONE
)
484 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
485 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
490 /* Check for timeout or receive error.
491 * Timeouts occur when the sink is not connected
493 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
494 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
499 /* Timeouts occur when the device isn't connected, so they're
500 * "normal" -- don't fill the kernel log with these */
501 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
502 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
507 /* Unload any bytes sent back from the other side */
508 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
509 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
510 if (recv_bytes
> recv_size
)
511 recv_bytes
= recv_size
;
513 for (i
= 0; i
< recv_bytes
; i
+= 4)
514 unpack_aux(I915_READ(ch_data
+ i
),
515 recv
+ i
, recv_bytes
- i
);
519 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
520 intel_aux_display_runtime_put(dev_priv
);
525 /* Write data to the aux channel in native mode */
527 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
528 uint16_t address
, uint8_t *send
, int send_bytes
)
535 if (WARN_ON(send_bytes
> 16))
538 intel_dp_check_edp(intel_dp
);
539 msg
[0] = AUX_NATIVE_WRITE
<< 4;
540 msg
[1] = address
>> 8;
541 msg
[2] = address
& 0xff;
542 msg
[3] = send_bytes
- 1;
543 memcpy(&msg
[4], send
, send_bytes
);
544 msg_bytes
= send_bytes
+ 4;
546 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
549 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
551 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
559 /* Write a single byte to the aux channel in native mode */
561 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
562 uint16_t address
, uint8_t byte
)
564 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
567 /* read bytes from a native aux channel */
569 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
570 uint16_t address
, uint8_t *recv
, int recv_bytes
)
579 if (WARN_ON(recv_bytes
> 19))
582 intel_dp_check_edp(intel_dp
);
583 msg
[0] = AUX_NATIVE_READ
<< 4;
584 msg
[1] = address
>> 8;
585 msg
[2] = address
& 0xff;
586 msg
[3] = recv_bytes
- 1;
589 reply_bytes
= recv_bytes
+ 1;
592 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
599 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
600 memcpy(recv
, reply
+ 1, ret
- 1);
603 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
611 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
612 uint8_t write_byte
, uint8_t *read_byte
)
614 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
615 struct intel_dp
*intel_dp
= container_of(adapter
,
618 uint16_t address
= algo_data
->address
;
626 intel_dp_check_edp(intel_dp
);
627 /* Set up the command byte */
628 if (mode
& MODE_I2C_READ
)
629 msg
[0] = AUX_I2C_READ
<< 4;
631 msg
[0] = AUX_I2C_WRITE
<< 4;
633 if (!(mode
& MODE_I2C_STOP
))
634 msg
[0] |= AUX_I2C_MOT
<< 4;
636 msg
[1] = address
>> 8;
657 for (retry
= 0; retry
< 5; retry
++) {
658 ret
= intel_dp_aux_ch(intel_dp
,
662 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
666 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
667 case AUX_NATIVE_REPLY_ACK
:
668 /* I2C-over-AUX Reply field is only valid
669 * when paired with AUX ACK.
672 case AUX_NATIVE_REPLY_NACK
:
673 DRM_DEBUG_KMS("aux_ch native nack\n");
675 case AUX_NATIVE_REPLY_DEFER
:
677 * For now, just give more slack to branch devices. We
678 * could check the DPCD for I2C bit rate capabilities,
679 * and if available, adjust the interval. We could also
680 * be more careful with DP-to-Legacy adapters where a
681 * long legacy cable may force very low I2C bit rates.
683 if (intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
684 DP_DWN_STRM_PORT_PRESENT
)
685 usleep_range(500, 600);
687 usleep_range(300, 400);
690 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
695 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
696 case AUX_I2C_REPLY_ACK
:
697 if (mode
== MODE_I2C_READ
) {
698 *read_byte
= reply
[1];
700 return reply_bytes
- 1;
701 case AUX_I2C_REPLY_NACK
:
702 DRM_DEBUG_KMS("aux_i2c nack\n");
704 case AUX_I2C_REPLY_DEFER
:
705 DRM_DEBUG_KMS("aux_i2c defer\n");
709 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
714 DRM_ERROR("too many retries, giving up\n");
719 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
720 struct intel_connector
*intel_connector
, const char *name
)
724 DRM_DEBUG_KMS("i2c_init %s\n", name
);
725 intel_dp
->algo
.running
= false;
726 intel_dp
->algo
.address
= 0;
727 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
729 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
730 intel_dp
->adapter
.owner
= THIS_MODULE
;
731 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
732 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
733 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
734 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
735 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
737 ironlake_edp_panel_vdd_on(intel_dp
);
738 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
739 ironlake_edp_panel_vdd_off(intel_dp
, false);
744 intel_dp_set_clock(struct intel_encoder
*encoder
,
745 struct intel_crtc_config
*pipe_config
, int link_bw
)
747 struct drm_device
*dev
= encoder
->base
.dev
;
748 const struct dp_link_dpll
*divisor
= NULL
;
753 count
= ARRAY_SIZE(gen4_dpll
);
754 } else if (IS_HASWELL(dev
)) {
755 /* Haswell has special-purpose DP DDI clocks. */
756 } else if (HAS_PCH_SPLIT(dev
)) {
758 count
= ARRAY_SIZE(pch_dpll
);
759 } else if (IS_VALLEYVIEW(dev
)) {
761 count
= ARRAY_SIZE(vlv_dpll
);
764 if (divisor
&& count
) {
765 for (i
= 0; i
< count
; i
++) {
766 if (link_bw
== divisor
[i
].link_bw
) {
767 pipe_config
->dpll
= divisor
[i
].dpll
;
768 pipe_config
->clock_set
= true;
776 intel_dp_compute_config(struct intel_encoder
*encoder
,
777 struct intel_crtc_config
*pipe_config
)
779 struct drm_device
*dev
= encoder
->base
.dev
;
780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
781 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
782 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
783 enum port port
= dp_to_dig_port(intel_dp
)->port
;
784 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
785 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
786 int lane_count
, clock
;
787 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
788 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
790 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
791 int link_avail
, link_clock
;
793 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
794 pipe_config
->has_pch_encoder
= true;
796 pipe_config
->has_dp_encoder
= true;
798 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
799 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
801 if (!HAS_PCH_SPLIT(dev
))
802 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
803 intel_connector
->panel
.fitting_mode
);
805 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
806 intel_connector
->panel
.fitting_mode
);
809 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
812 DRM_DEBUG_KMS("DP link computation with max lane count %i "
813 "max bw %02x pixel clock %iKHz\n",
814 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
816 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
818 bpp
= pipe_config
->pipe_bpp
;
819 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
) {
820 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
821 dev_priv
->vbt
.edp_bpp
);
822 bpp
= min_t(int, bpp
, dev_priv
->vbt
.edp_bpp
);
825 for (; bpp
>= 6*3; bpp
-= 2*3) {
826 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
828 for (clock
= 0; clock
<= max_clock
; clock
++) {
829 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
830 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
831 link_avail
= intel_dp_max_data_rate(link_clock
,
834 if (mode_rate
<= link_avail
) {
844 if (intel_dp
->color_range_auto
) {
847 * CEA-861-E - 5.1 Default Encoding Parameters
848 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
850 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
851 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
853 intel_dp
->color_range
= 0;
856 if (intel_dp
->color_range
)
857 pipe_config
->limited_color_range
= true;
859 intel_dp
->link_bw
= bws
[clock
];
860 intel_dp
->lane_count
= lane_count
;
861 pipe_config
->pipe_bpp
= bpp
;
862 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
864 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
865 intel_dp
->link_bw
, intel_dp
->lane_count
,
866 pipe_config
->port_clock
, bpp
);
867 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
868 mode_rate
, link_avail
);
870 intel_link_compute_m_n(bpp
, lane_count
,
871 adjusted_mode
->clock
, pipe_config
->port_clock
,
872 &pipe_config
->dp_m_n
);
874 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
879 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
881 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
882 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
883 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
884 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
886 * Check for DPCD version > 1.1 and enhanced framing support
888 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
889 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
890 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
894 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
896 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
897 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
898 struct drm_device
*dev
= crtc
->base
.dev
;
899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
902 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
903 dpa_ctl
= I915_READ(DP_A
);
904 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
906 if (crtc
->config
.port_clock
== 162000) {
907 /* For a long time we've carried around a ILK-DevA w/a for the
908 * 160MHz clock. If we're really unlucky, it's still required.
910 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
911 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
912 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
914 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
915 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
918 I915_WRITE(DP_A
, dpa_ctl
);
924 static void intel_dp_mode_set(struct intel_encoder
*encoder
)
926 struct drm_device
*dev
= encoder
->base
.dev
;
927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
928 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
929 enum port port
= dp_to_dig_port(intel_dp
)->port
;
930 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
931 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
934 * There are four kinds of DP registers:
941 * IBX PCH and CPU are the same for almost everything,
942 * except that the CPU DP PLL is configured in this
945 * CPT PCH is quite different, having many bits moved
946 * to the TRANS_DP_CTL register instead. That
947 * configuration happens (oddly) in ironlake_pch_enable
950 /* Preserve the BIOS-computed detected bit. This is
951 * supposed to be read-only.
953 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
955 /* Handle DP bits in common between all three register formats */
956 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
957 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
959 if (intel_dp
->has_audio
) {
960 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
961 pipe_name(crtc
->pipe
));
962 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
963 intel_write_eld(&encoder
->base
, adjusted_mode
);
966 intel_dp_init_link_config(intel_dp
);
968 /* Split out the IBX/CPU vs CPT settings */
970 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
971 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
972 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
973 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
974 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
975 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
977 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
978 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
980 intel_dp
->DP
|= crtc
->pipe
<< 29;
981 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
982 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
983 intel_dp
->DP
|= intel_dp
->color_range
;
985 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
986 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
987 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
988 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
989 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
991 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
992 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
995 intel_dp
->DP
|= DP_PIPEB_SELECT
;
997 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1000 if (port
== PORT_A
&& !IS_VALLEYVIEW(dev
))
1001 ironlake_set_pll_cpu_edp(intel_dp
);
1004 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1005 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1007 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1010 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1011 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1013 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
1017 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1019 u32 pp_stat_reg
, pp_ctrl_reg
;
1021 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1022 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1024 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1026 I915_READ(pp_stat_reg
),
1027 I915_READ(pp_ctrl_reg
));
1029 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1030 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1031 I915_READ(pp_stat_reg
),
1032 I915_READ(pp_ctrl_reg
));
1036 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
1038 DRM_DEBUG_KMS("Wait for panel power on\n");
1039 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1042 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
1044 DRM_DEBUG_KMS("Wait for panel power off time\n");
1045 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1048 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1050 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1051 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1055 /* Read the current pp_control value, unlocking the register if it
1059 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1061 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1065 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1066 control
&= ~PANEL_UNLOCK_MASK
;
1067 control
|= PANEL_UNLOCK_REGS
;
1071 void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1073 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1076 u32 pp_stat_reg
, pp_ctrl_reg
;
1078 if (!is_edp(intel_dp
))
1080 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1082 WARN(intel_dp
->want_panel_vdd
,
1083 "eDP VDD already requested on\n");
1085 intel_dp
->want_panel_vdd
= true;
1087 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1088 DRM_DEBUG_KMS("eDP VDD already on\n");
1092 if (!ironlake_edp_have_panel_power(intel_dp
))
1093 ironlake_wait_panel_power_cycle(intel_dp
);
1095 pp
= ironlake_get_pp_control(intel_dp
);
1096 pp
|= EDP_FORCE_VDD
;
1098 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1099 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1101 I915_WRITE(pp_ctrl_reg
, pp
);
1102 POSTING_READ(pp_ctrl_reg
);
1103 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1104 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1106 * If the panel wasn't on, delay before accessing aux channel
1108 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1109 DRM_DEBUG_KMS("eDP was not running\n");
1110 msleep(intel_dp
->panel_power_up_delay
);
1114 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1116 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1119 u32 pp_stat_reg
, pp_ctrl_reg
;
1121 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1123 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1124 pp
= ironlake_get_pp_control(intel_dp
);
1125 pp
&= ~EDP_FORCE_VDD
;
1127 pp_stat_reg
= _pp_ctrl_reg(intel_dp
);
1128 pp_ctrl_reg
= _pp_stat_reg(intel_dp
);
1130 I915_WRITE(pp_ctrl_reg
, pp
);
1131 POSTING_READ(pp_ctrl_reg
);
1133 /* Make sure sequencer is idle before allowing subsequent activity */
1134 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1135 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1136 msleep(intel_dp
->panel_power_down_delay
);
1140 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1142 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1143 struct intel_dp
, panel_vdd_work
);
1144 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1146 mutex_lock(&dev
->mode_config
.mutex
);
1147 ironlake_panel_vdd_off_sync(intel_dp
);
1148 mutex_unlock(&dev
->mode_config
.mutex
);
1151 void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1153 if (!is_edp(intel_dp
))
1156 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1157 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1159 intel_dp
->want_panel_vdd
= false;
1162 ironlake_panel_vdd_off_sync(intel_dp
);
1165 * Queue the timer to fire a long
1166 * time from now (relative to the power down delay)
1167 * to keep the panel power up across a sequence of operations
1169 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1170 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1174 void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1176 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1181 if (!is_edp(intel_dp
))
1184 DRM_DEBUG_KMS("Turn eDP power on\n");
1186 if (ironlake_edp_have_panel_power(intel_dp
)) {
1187 DRM_DEBUG_KMS("eDP power already on\n");
1191 ironlake_wait_panel_power_cycle(intel_dp
);
1193 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1194 pp
= ironlake_get_pp_control(intel_dp
);
1196 /* ILK workaround: disable reset around power sequence */
1197 pp
&= ~PANEL_POWER_RESET
;
1198 I915_WRITE(pp_ctrl_reg
, pp
);
1199 POSTING_READ(pp_ctrl_reg
);
1202 pp
|= POWER_TARGET_ON
;
1204 pp
|= PANEL_POWER_RESET
;
1206 I915_WRITE(pp_ctrl_reg
, pp
);
1207 POSTING_READ(pp_ctrl_reg
);
1209 ironlake_wait_panel_on(intel_dp
);
1212 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1213 I915_WRITE(pp_ctrl_reg
, pp
);
1214 POSTING_READ(pp_ctrl_reg
);
1218 void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1220 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1225 if (!is_edp(intel_dp
))
1228 DRM_DEBUG_KMS("Turn eDP power off\n");
1230 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1232 pp
= ironlake_get_pp_control(intel_dp
);
1233 /* We need to switch off panel power _and_ force vdd, for otherwise some
1234 * panels get very unhappy and cease to work. */
1235 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1237 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1239 I915_WRITE(pp_ctrl_reg
, pp
);
1240 POSTING_READ(pp_ctrl_reg
);
1242 intel_dp
->want_panel_vdd
= false;
1244 ironlake_wait_panel_off(intel_dp
);
1247 void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1249 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1250 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1252 int pipe
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
)->pipe
;
1256 if (!is_edp(intel_dp
))
1259 DRM_DEBUG_KMS("\n");
1261 * If we enable the backlight right away following a panel power
1262 * on, we may see slight flicker as the panel syncs with the eDP
1263 * link. So delay a bit to make sure the image is solid before
1264 * allowing it to appear.
1266 msleep(intel_dp
->backlight_on_delay
);
1267 pp
= ironlake_get_pp_control(intel_dp
);
1268 pp
|= EDP_BLC_ENABLE
;
1270 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1272 I915_WRITE(pp_ctrl_reg
, pp
);
1273 POSTING_READ(pp_ctrl_reg
);
1275 intel_panel_enable_backlight(dev
, pipe
);
1278 void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1280 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1285 if (!is_edp(intel_dp
))
1288 intel_panel_disable_backlight(dev
);
1290 DRM_DEBUG_KMS("\n");
1291 pp
= ironlake_get_pp_control(intel_dp
);
1292 pp
&= ~EDP_BLC_ENABLE
;
1294 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1296 I915_WRITE(pp_ctrl_reg
, pp
);
1297 POSTING_READ(pp_ctrl_reg
);
1298 msleep(intel_dp
->backlight_off_delay
);
1301 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1303 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1304 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1305 struct drm_device
*dev
= crtc
->dev
;
1306 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1309 assert_pipe_disabled(dev_priv
,
1310 to_intel_crtc(crtc
)->pipe
);
1312 DRM_DEBUG_KMS("\n");
1313 dpa_ctl
= I915_READ(DP_A
);
1314 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1315 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1317 /* We don't adjust intel_dp->DP while tearing down the link, to
1318 * facilitate link retraining (e.g. after hotplug). Hence clear all
1319 * enable bits here to ensure that we don't enable too much. */
1320 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1321 intel_dp
->DP
|= DP_PLL_ENABLE
;
1322 I915_WRITE(DP_A
, intel_dp
->DP
);
1327 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1329 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1330 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1331 struct drm_device
*dev
= crtc
->dev
;
1332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1335 assert_pipe_disabled(dev_priv
,
1336 to_intel_crtc(crtc
)->pipe
);
1338 dpa_ctl
= I915_READ(DP_A
);
1339 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1340 "dp pll off, should be on\n");
1341 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1343 /* We can't rely on the value tracked for the DP register in
1344 * intel_dp->DP because link_down must not change that (otherwise link
1345 * re-training will fail. */
1346 dpa_ctl
&= ~DP_PLL_ENABLE
;
1347 I915_WRITE(DP_A
, dpa_ctl
);
1352 /* If the sink supports it, try to set the power state appropriately */
1353 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1357 /* Should have a valid DPCD by this point */
1358 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1361 if (mode
!= DRM_MODE_DPMS_ON
) {
1362 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1365 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1368 * When turning on, we need to retry for 1ms to give the sink
1371 for (i
= 0; i
< 3; i
++) {
1372 ret
= intel_dp_aux_native_write_1(intel_dp
,
1382 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1385 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1386 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1387 struct drm_device
*dev
= encoder
->base
.dev
;
1388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1389 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1391 if (!(tmp
& DP_PORT_EN
))
1394 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1395 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1396 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1397 *pipe
= PORT_TO_PIPE(tmp
);
1403 switch (intel_dp
->output_reg
) {
1405 trans_sel
= TRANS_DP_PORT_SEL_B
;
1408 trans_sel
= TRANS_DP_PORT_SEL_C
;
1411 trans_sel
= TRANS_DP_PORT_SEL_D
;
1418 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1419 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1425 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1426 intel_dp
->output_reg
);
1432 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1433 struct intel_crtc_config
*pipe_config
)
1435 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1437 struct drm_device
*dev
= encoder
->base
.dev
;
1438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1439 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1440 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1443 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1444 tmp
= I915_READ(intel_dp
->output_reg
);
1445 if (tmp
& DP_SYNC_HS_HIGH
)
1446 flags
|= DRM_MODE_FLAG_PHSYNC
;
1448 flags
|= DRM_MODE_FLAG_NHSYNC
;
1450 if (tmp
& DP_SYNC_VS_HIGH
)
1451 flags
|= DRM_MODE_FLAG_PVSYNC
;
1453 flags
|= DRM_MODE_FLAG_NVSYNC
;
1455 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1456 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1457 flags
|= DRM_MODE_FLAG_PHSYNC
;
1459 flags
|= DRM_MODE_FLAG_NHSYNC
;
1461 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1462 flags
|= DRM_MODE_FLAG_PVSYNC
;
1464 flags
|= DRM_MODE_FLAG_NVSYNC
;
1467 pipe_config
->adjusted_mode
.flags
|= flags
;
1469 pipe_config
->has_dp_encoder
= true;
1471 intel_dp_get_m_n(crtc
, pipe_config
);
1473 if (port
== PORT_A
) {
1474 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1475 pipe_config
->port_clock
= 162000;
1477 pipe_config
->port_clock
= 270000;
1480 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1481 &pipe_config
->dp_m_n
);
1483 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1484 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1486 pipe_config
->adjusted_mode
.clock
= dotclock
;
1489 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1491 return is_edp(intel_dp
) &&
1492 intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1495 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1499 if (!IS_HASWELL(dev
))
1502 return I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
1505 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1506 struct edp_vsc_psr
*vsc_psr
)
1508 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1509 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1511 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1512 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1513 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1514 uint32_t *data
= (uint32_t *) vsc_psr
;
1517 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1518 the video DIP being updated before program video DIP data buffer
1519 registers for DIP being updated. */
1520 I915_WRITE(ctl_reg
, 0);
1521 POSTING_READ(ctl_reg
);
1523 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1524 if (i
< sizeof(struct edp_vsc_psr
))
1525 I915_WRITE(data_reg
+ i
, *data
++);
1527 I915_WRITE(data_reg
+ i
, 0);
1530 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1531 POSTING_READ(ctl_reg
);
1534 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1536 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1538 struct edp_vsc_psr psr_vsc
;
1540 if (intel_dp
->psr_setup_done
)
1543 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1544 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1545 psr_vsc
.sdp_header
.HB0
= 0;
1546 psr_vsc
.sdp_header
.HB1
= 0x7;
1547 psr_vsc
.sdp_header
.HB2
= 0x2;
1548 psr_vsc
.sdp_header
.HB3
= 0x8;
1549 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1551 /* Avoid continuous PSR exit by masking memup and hpd */
1552 I915_WRITE(EDP_PSR_DEBUG_CTL
, EDP_PSR_DEBUG_MASK_MEMUP
|
1553 EDP_PSR_DEBUG_MASK_HPD
);
1555 intel_dp
->psr_setup_done
= true;
1558 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1560 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1562 uint32_t aux_clock_divider
= get_aux_clock_divider(intel_dp
, 0);
1563 int precharge
= 0x3;
1564 int msg_size
= 5; /* Header(4) + Message(1) */
1566 /* Enable PSR in sink */
1567 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
)
1568 intel_dp_aux_native_write_1(intel_dp
, DP_PSR_EN_CFG
,
1570 ~DP_PSR_MAIN_LINK_ACTIVE
);
1572 intel_dp_aux_native_write_1(intel_dp
, DP_PSR_EN_CFG
,
1574 DP_PSR_MAIN_LINK_ACTIVE
);
1576 /* Setup AUX registers */
1577 I915_WRITE(EDP_PSR_AUX_DATA1
, EDP_PSR_DPCD_COMMAND
);
1578 I915_WRITE(EDP_PSR_AUX_DATA2
, EDP_PSR_DPCD_NORMAL_OPERATION
);
1579 I915_WRITE(EDP_PSR_AUX_CTL
,
1580 DP_AUX_CH_CTL_TIME_OUT_400us
|
1581 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1582 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1583 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1586 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1588 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1590 uint32_t max_sleep_time
= 0x1f;
1591 uint32_t idle_frames
= 1;
1594 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
1595 val
|= EDP_PSR_LINK_STANDBY
;
1596 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1597 val
|= EDP_PSR_TP1_TIME_0us
;
1598 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1600 val
|= EDP_PSR_LINK_DISABLE
;
1602 I915_WRITE(EDP_PSR_CTL
, val
|
1603 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
|
1604 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1605 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1609 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1611 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1612 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1614 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1615 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1616 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1617 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
1619 if (!IS_HASWELL(dev
)) {
1620 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1621 dev_priv
->no_psr_reason
= PSR_NO_SOURCE
;
1625 if ((intel_encoder
->type
!= INTEL_OUTPUT_EDP
) ||
1626 (dig_port
->port
!= PORT_A
)) {
1627 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1628 dev_priv
->no_psr_reason
= PSR_HSW_NOT_DDIA
;
1632 if (!is_edp_psr(intel_dp
)) {
1633 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1634 dev_priv
->no_psr_reason
= PSR_NO_SINK
;
1638 if (!i915_enable_psr
) {
1639 DRM_DEBUG_KMS("PSR disable by flag\n");
1640 dev_priv
->no_psr_reason
= PSR_MODULE_PARAM
;
1644 crtc
= dig_port
->base
.base
.crtc
;
1646 DRM_DEBUG_KMS("crtc not active for PSR\n");
1647 dev_priv
->no_psr_reason
= PSR_CRTC_NOT_ACTIVE
;
1651 intel_crtc
= to_intel_crtc(crtc
);
1652 if (!intel_crtc_active(crtc
)) {
1653 DRM_DEBUG_KMS("crtc not active for PSR\n");
1654 dev_priv
->no_psr_reason
= PSR_CRTC_NOT_ACTIVE
;
1658 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1659 if (obj
->tiling_mode
!= I915_TILING_X
||
1660 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1661 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1662 dev_priv
->no_psr_reason
= PSR_NOT_TILED
;
1666 if (I915_READ(SPRCTL(intel_crtc
->pipe
)) & SPRITE_ENABLE
) {
1667 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1668 dev_priv
->no_psr_reason
= PSR_SPRITE_ENABLED
;
1672 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1674 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1675 dev_priv
->no_psr_reason
= PSR_S3D_ENABLED
;
1679 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1680 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1681 dev_priv
->no_psr_reason
= PSR_INTERLACED_ENABLED
;
1688 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1690 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1692 if (!intel_edp_psr_match_conditions(intel_dp
) ||
1693 intel_edp_is_psr_enabled(dev
))
1696 /* Setup PSR once */
1697 intel_edp_psr_setup(intel_dp
);
1699 /* Enable PSR on the panel */
1700 intel_edp_psr_enable_sink(intel_dp
);
1702 /* Enable PSR on the host */
1703 intel_edp_psr_enable_source(intel_dp
);
1706 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1708 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1710 if (intel_edp_psr_match_conditions(intel_dp
) &&
1711 !intel_edp_is_psr_enabled(dev
))
1712 intel_edp_psr_do_enable(intel_dp
);
1715 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1717 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1720 if (!intel_edp_is_psr_enabled(dev
))
1723 I915_WRITE(EDP_PSR_CTL
, I915_READ(EDP_PSR_CTL
) & ~EDP_PSR_ENABLE
);
1725 /* Wait till PSR is idle */
1726 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL
) &
1727 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1728 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1731 void intel_edp_psr_update(struct drm_device
*dev
)
1733 struct intel_encoder
*encoder
;
1734 struct intel_dp
*intel_dp
= NULL
;
1736 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
)
1737 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
1738 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1740 if (!is_edp_psr(intel_dp
))
1743 if (!intel_edp_psr_match_conditions(intel_dp
))
1744 intel_edp_psr_disable(intel_dp
);
1746 if (!intel_edp_is_psr_enabled(dev
))
1747 intel_edp_psr_do_enable(intel_dp
);
1751 static void intel_disable_dp(struct intel_encoder
*encoder
)
1753 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1754 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1755 struct drm_device
*dev
= encoder
->base
.dev
;
1757 /* Make sure the panel is off before trying to change the mode. But also
1758 * ensure that we have vdd while we switch off the panel. */
1759 ironlake_edp_panel_vdd_on(intel_dp
);
1760 ironlake_edp_backlight_off(intel_dp
);
1761 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1762 ironlake_edp_panel_off(intel_dp
);
1764 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1765 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1766 intel_dp_link_down(intel_dp
);
1769 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1771 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1772 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1773 struct drm_device
*dev
= encoder
->base
.dev
;
1775 if (port
== PORT_A
|| IS_VALLEYVIEW(dev
)) {
1776 intel_dp_link_down(intel_dp
);
1777 if (!IS_VALLEYVIEW(dev
))
1778 ironlake_edp_pll_off(intel_dp
);
1782 static void intel_enable_dp(struct intel_encoder
*encoder
)
1784 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1785 struct drm_device
*dev
= encoder
->base
.dev
;
1786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1787 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1789 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1792 ironlake_edp_panel_vdd_on(intel_dp
);
1793 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1794 intel_dp_start_link_train(intel_dp
);
1795 ironlake_edp_panel_on(intel_dp
);
1796 ironlake_edp_panel_vdd_off(intel_dp
, true);
1797 intel_dp_complete_link_train(intel_dp
);
1798 intel_dp_stop_link_train(intel_dp
);
1801 static void g4x_enable_dp(struct intel_encoder
*encoder
)
1803 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1805 intel_enable_dp(encoder
);
1806 ironlake_edp_backlight_on(intel_dp
);
1809 static void vlv_enable_dp(struct intel_encoder
*encoder
)
1811 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1813 ironlake_edp_backlight_on(intel_dp
);
1816 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
1818 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1819 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1821 if (dport
->port
== PORT_A
)
1822 ironlake_edp_pll_on(intel_dp
);
1825 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
1827 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1828 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1829 struct drm_device
*dev
= encoder
->base
.dev
;
1830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1831 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1832 int port
= vlv_dport_to_channel(dport
);
1833 int pipe
= intel_crtc
->pipe
;
1834 struct edp_power_seq power_seq
;
1837 mutex_lock(&dev_priv
->dpio_lock
);
1839 val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_DATA_LANE_A(port
));
1846 vlv_dpio_write(dev_priv
, pipe
, DPIO_DATA_CHANNEL(port
), val
);
1847 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_CLOCKBUF0(port
), 0x00760018);
1848 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_CLOCKBUF8(port
), 0x00400888);
1850 mutex_unlock(&dev_priv
->dpio_lock
);
1852 /* init power sequencer on this pipe and port */
1853 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
1854 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
1857 intel_enable_dp(encoder
);
1859 vlv_wait_port_ready(dev_priv
, port
);
1862 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
1864 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1865 struct drm_device
*dev
= encoder
->base
.dev
;
1866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1867 struct intel_crtc
*intel_crtc
=
1868 to_intel_crtc(encoder
->base
.crtc
);
1869 int port
= vlv_dport_to_channel(dport
);
1870 int pipe
= intel_crtc
->pipe
;
1872 /* Program Tx lane resets to default */
1873 mutex_lock(&dev_priv
->dpio_lock
);
1874 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_TX(port
),
1875 DPIO_PCS_TX_LANE2_RESET
|
1876 DPIO_PCS_TX_LANE1_RESET
);
1877 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_CLK(port
),
1878 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1879 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1880 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1881 DPIO_PCS_CLK_SOFT_RESET
);
1883 /* Fix up inter-pair skew failure */
1884 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_STAGGER1(port
), 0x00750f00);
1885 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_CTL(port
), 0x00001500);
1886 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_LANE(port
), 0x40400000);
1887 mutex_unlock(&dev_priv
->dpio_lock
);
1891 * Native read with retry for link status and receiver capability reads for
1892 * cases where the sink may still be asleep.
1895 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1896 uint8_t *recv
, int recv_bytes
)
1901 * Sinks are *supposed* to come up within 1ms from an off state,
1902 * but we're also supposed to retry 3 times per the spec.
1904 for (i
= 0; i
< 3; i
++) {
1905 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1907 if (ret
== recv_bytes
)
1916 * Fetch AUX CH registers 0x202 - 0x207 which contain
1917 * link status information
1920 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1922 return intel_dp_aux_native_read_retry(intel_dp
,
1925 DP_LINK_STATUS_SIZE
);
1929 static char *voltage_names
[] = {
1930 "0.4V", "0.6V", "0.8V", "1.2V"
1932 static char *pre_emph_names
[] = {
1933 "0dB", "3.5dB", "6dB", "9.5dB"
1935 static char *link_train_names
[] = {
1936 "pattern 1", "pattern 2", "idle", "off"
1941 * These are source-specific values; current Intel hardware supports
1942 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1946 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1948 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1949 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1951 if (IS_VALLEYVIEW(dev
))
1952 return DP_TRAIN_VOLTAGE_SWING_1200
;
1953 else if (IS_GEN7(dev
) && port
== PORT_A
)
1954 return DP_TRAIN_VOLTAGE_SWING_800
;
1955 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
1956 return DP_TRAIN_VOLTAGE_SWING_1200
;
1958 return DP_TRAIN_VOLTAGE_SWING_800
;
1962 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1964 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1965 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1968 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1969 case DP_TRAIN_VOLTAGE_SWING_400
:
1970 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1971 case DP_TRAIN_VOLTAGE_SWING_600
:
1972 return DP_TRAIN_PRE_EMPHASIS_6
;
1973 case DP_TRAIN_VOLTAGE_SWING_800
:
1974 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1975 case DP_TRAIN_VOLTAGE_SWING_1200
:
1977 return DP_TRAIN_PRE_EMPHASIS_0
;
1979 } else if (IS_VALLEYVIEW(dev
)) {
1980 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1981 case DP_TRAIN_VOLTAGE_SWING_400
:
1982 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1983 case DP_TRAIN_VOLTAGE_SWING_600
:
1984 return DP_TRAIN_PRE_EMPHASIS_6
;
1985 case DP_TRAIN_VOLTAGE_SWING_800
:
1986 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1987 case DP_TRAIN_VOLTAGE_SWING_1200
:
1989 return DP_TRAIN_PRE_EMPHASIS_0
;
1991 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
1992 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1993 case DP_TRAIN_VOLTAGE_SWING_400
:
1994 return DP_TRAIN_PRE_EMPHASIS_6
;
1995 case DP_TRAIN_VOLTAGE_SWING_600
:
1996 case DP_TRAIN_VOLTAGE_SWING_800
:
1997 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1999 return DP_TRAIN_PRE_EMPHASIS_0
;
2002 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2003 case DP_TRAIN_VOLTAGE_SWING_400
:
2004 return DP_TRAIN_PRE_EMPHASIS_6
;
2005 case DP_TRAIN_VOLTAGE_SWING_600
:
2006 return DP_TRAIN_PRE_EMPHASIS_6
;
2007 case DP_TRAIN_VOLTAGE_SWING_800
:
2008 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2009 case DP_TRAIN_VOLTAGE_SWING_1200
:
2011 return DP_TRAIN_PRE_EMPHASIS_0
;
2016 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2018 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2020 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2021 struct intel_crtc
*intel_crtc
=
2022 to_intel_crtc(dport
->base
.base
.crtc
);
2023 unsigned long demph_reg_value
, preemph_reg_value
,
2024 uniqtranscale_reg_value
;
2025 uint8_t train_set
= intel_dp
->train_set
[0];
2026 int port
= vlv_dport_to_channel(dport
);
2027 int pipe
= intel_crtc
->pipe
;
2029 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2030 case DP_TRAIN_PRE_EMPHASIS_0
:
2031 preemph_reg_value
= 0x0004000;
2032 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2033 case DP_TRAIN_VOLTAGE_SWING_400
:
2034 demph_reg_value
= 0x2B405555;
2035 uniqtranscale_reg_value
= 0x552AB83A;
2037 case DP_TRAIN_VOLTAGE_SWING_600
:
2038 demph_reg_value
= 0x2B404040;
2039 uniqtranscale_reg_value
= 0x5548B83A;
2041 case DP_TRAIN_VOLTAGE_SWING_800
:
2042 demph_reg_value
= 0x2B245555;
2043 uniqtranscale_reg_value
= 0x5560B83A;
2045 case DP_TRAIN_VOLTAGE_SWING_1200
:
2046 demph_reg_value
= 0x2B405555;
2047 uniqtranscale_reg_value
= 0x5598DA3A;
2053 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2054 preemph_reg_value
= 0x0002000;
2055 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2056 case DP_TRAIN_VOLTAGE_SWING_400
:
2057 demph_reg_value
= 0x2B404040;
2058 uniqtranscale_reg_value
= 0x5552B83A;
2060 case DP_TRAIN_VOLTAGE_SWING_600
:
2061 demph_reg_value
= 0x2B404848;
2062 uniqtranscale_reg_value
= 0x5580B83A;
2064 case DP_TRAIN_VOLTAGE_SWING_800
:
2065 demph_reg_value
= 0x2B404040;
2066 uniqtranscale_reg_value
= 0x55ADDA3A;
2072 case DP_TRAIN_PRE_EMPHASIS_6
:
2073 preemph_reg_value
= 0x0000000;
2074 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2075 case DP_TRAIN_VOLTAGE_SWING_400
:
2076 demph_reg_value
= 0x2B305555;
2077 uniqtranscale_reg_value
= 0x5570B83A;
2079 case DP_TRAIN_VOLTAGE_SWING_600
:
2080 demph_reg_value
= 0x2B2B4040;
2081 uniqtranscale_reg_value
= 0x55ADDA3A;
2087 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2088 preemph_reg_value
= 0x0006000;
2089 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2090 case DP_TRAIN_VOLTAGE_SWING_400
:
2091 demph_reg_value
= 0x1B405555;
2092 uniqtranscale_reg_value
= 0x55ADDA3A;
2102 mutex_lock(&dev_priv
->dpio_lock
);
2103 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_OCALINIT(port
), 0x00000000);
2104 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_SWING_CTL4(port
), demph_reg_value
);
2105 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_SWING_CTL2(port
),
2106 uniqtranscale_reg_value
);
2107 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_SWING_CTL3(port
), 0x0C782040);
2108 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_STAGGER0(port
), 0x00030000);
2109 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_CTL_OVER1(port
), preemph_reg_value
);
2110 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_OCALINIT(port
), 0x80000000);
2111 mutex_unlock(&dev_priv
->dpio_lock
);
2117 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2122 uint8_t voltage_max
;
2123 uint8_t preemph_max
;
2125 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2126 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2127 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2135 voltage_max
= intel_dp_voltage_max(intel_dp
);
2136 if (v
>= voltage_max
)
2137 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2139 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2140 if (p
>= preemph_max
)
2141 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2143 for (lane
= 0; lane
< 4; lane
++)
2144 intel_dp
->train_set
[lane
] = v
| p
;
2148 intel_gen4_signal_levels(uint8_t train_set
)
2150 uint32_t signal_levels
= 0;
2152 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2153 case DP_TRAIN_VOLTAGE_SWING_400
:
2155 signal_levels
|= DP_VOLTAGE_0_4
;
2157 case DP_TRAIN_VOLTAGE_SWING_600
:
2158 signal_levels
|= DP_VOLTAGE_0_6
;
2160 case DP_TRAIN_VOLTAGE_SWING_800
:
2161 signal_levels
|= DP_VOLTAGE_0_8
;
2163 case DP_TRAIN_VOLTAGE_SWING_1200
:
2164 signal_levels
|= DP_VOLTAGE_1_2
;
2167 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2168 case DP_TRAIN_PRE_EMPHASIS_0
:
2170 signal_levels
|= DP_PRE_EMPHASIS_0
;
2172 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2173 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2175 case DP_TRAIN_PRE_EMPHASIS_6
:
2176 signal_levels
|= DP_PRE_EMPHASIS_6
;
2178 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2179 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2182 return signal_levels
;
2185 /* Gen6's DP voltage swing and pre-emphasis control */
2187 intel_gen6_edp_signal_levels(uint8_t train_set
)
2189 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2190 DP_TRAIN_PRE_EMPHASIS_MASK
);
2191 switch (signal_levels
) {
2192 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2193 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2194 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2195 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2196 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2197 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2198 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2199 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2200 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2201 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2202 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2203 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2204 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2205 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2207 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2208 "0x%x\n", signal_levels
);
2209 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2213 /* Gen7's DP voltage swing and pre-emphasis control */
2215 intel_gen7_edp_signal_levels(uint8_t train_set
)
2217 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2218 DP_TRAIN_PRE_EMPHASIS_MASK
);
2219 switch (signal_levels
) {
2220 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2221 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2222 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2223 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2224 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2225 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2227 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2228 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2229 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2230 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2232 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2233 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2234 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2235 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2238 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2239 "0x%x\n", signal_levels
);
2240 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2244 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2246 intel_hsw_signal_levels(uint8_t train_set
)
2248 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2249 DP_TRAIN_PRE_EMPHASIS_MASK
);
2250 switch (signal_levels
) {
2251 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2252 return DDI_BUF_EMP_400MV_0DB_HSW
;
2253 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2254 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2255 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2256 return DDI_BUF_EMP_400MV_6DB_HSW
;
2257 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2258 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2260 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2261 return DDI_BUF_EMP_600MV_0DB_HSW
;
2262 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2263 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2264 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2265 return DDI_BUF_EMP_600MV_6DB_HSW
;
2267 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2268 return DDI_BUF_EMP_800MV_0DB_HSW
;
2269 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2270 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2272 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2273 "0x%x\n", signal_levels
);
2274 return DDI_BUF_EMP_400MV_0DB_HSW
;
2278 /* Properly updates "DP" with the correct signal levels. */
2280 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2282 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2283 enum port port
= intel_dig_port
->port
;
2284 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2285 uint32_t signal_levels
, mask
;
2286 uint8_t train_set
= intel_dp
->train_set
[0];
2289 signal_levels
= intel_hsw_signal_levels(train_set
);
2290 mask
= DDI_BUF_EMP_MASK
;
2291 } else if (IS_VALLEYVIEW(dev
)) {
2292 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2294 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2295 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2296 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2297 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2298 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2299 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2301 signal_levels
= intel_gen4_signal_levels(train_set
);
2302 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2305 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2307 *DP
= (*DP
& ~mask
) | signal_levels
;
2311 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2312 uint32_t dp_reg_value
,
2313 uint8_t dp_train_pat
)
2315 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2316 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2318 enum port port
= intel_dig_port
->port
;
2322 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2324 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2325 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2327 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2329 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2330 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2331 case DP_TRAINING_PATTERN_DISABLE
:
2332 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2335 case DP_TRAINING_PATTERN_1
:
2336 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2338 case DP_TRAINING_PATTERN_2
:
2339 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2341 case DP_TRAINING_PATTERN_3
:
2342 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2345 I915_WRITE(DP_TP_CTL(port
), temp
);
2347 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2348 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
2350 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2351 case DP_TRAINING_PATTERN_DISABLE
:
2352 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
2354 case DP_TRAINING_PATTERN_1
:
2355 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
2357 case DP_TRAINING_PATTERN_2
:
2358 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
2360 case DP_TRAINING_PATTERN_3
:
2361 DRM_ERROR("DP training pattern 3 not supported\n");
2362 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
2367 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
2369 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2370 case DP_TRAINING_PATTERN_DISABLE
:
2371 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
2373 case DP_TRAINING_PATTERN_1
:
2374 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
2376 case DP_TRAINING_PATTERN_2
:
2377 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
2379 case DP_TRAINING_PATTERN_3
:
2380 DRM_ERROR("DP training pattern 3 not supported\n");
2381 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
2386 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
2387 POSTING_READ(intel_dp
->output_reg
);
2389 intel_dp_aux_native_write_1(intel_dp
,
2390 DP_TRAINING_PATTERN_SET
,
2393 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
2394 DP_TRAINING_PATTERN_DISABLE
) {
2395 ret
= intel_dp_aux_native_write(intel_dp
,
2396 DP_TRAINING_LANE0_SET
,
2397 intel_dp
->train_set
,
2398 intel_dp
->lane_count
);
2399 if (ret
!= intel_dp
->lane_count
)
2406 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
2408 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2409 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2411 enum port port
= intel_dig_port
->port
;
2417 val
= I915_READ(DP_TP_CTL(port
));
2418 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2419 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2420 I915_WRITE(DP_TP_CTL(port
), val
);
2423 * On PORT_A we can have only eDP in SST mode. There the only reason
2424 * we need to set idle transmission mode is to work around a HW issue
2425 * where we enable the pipe while not in idle link-training mode.
2426 * In this case there is requirement to wait for a minimum number of
2427 * idle patterns to be sent.
2432 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2434 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2437 /* Enable corresponding port and start training pattern 1 */
2439 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2441 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2442 struct drm_device
*dev
= encoder
->dev
;
2445 int voltage_tries
, loop_tries
;
2446 uint32_t DP
= intel_dp
->DP
;
2449 intel_ddi_prepare_link_retrain(encoder
);
2451 /* Write the link configuration data */
2452 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
2453 intel_dp
->link_configuration
,
2454 DP_LINK_CONFIGURATION_SIZE
);
2458 memset(intel_dp
->train_set
, 0, 4);
2463 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2464 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2466 intel_dp_set_signal_levels(intel_dp
, &DP
);
2468 /* Set training pattern 1 */
2469 if (!intel_dp_set_link_train(intel_dp
, DP
,
2470 DP_TRAINING_PATTERN_1
|
2471 DP_LINK_SCRAMBLING_DISABLE
))
2474 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2475 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2476 DRM_ERROR("failed to get link status\n");
2480 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2481 DRM_DEBUG_KMS("clock recovery OK\n");
2485 /* Check to see if we've tried the max voltage */
2486 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2487 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2489 if (i
== intel_dp
->lane_count
) {
2491 if (loop_tries
== 5) {
2492 DRM_DEBUG_KMS("too many full retries, give up\n");
2495 memset(intel_dp
->train_set
, 0, 4);
2500 /* Check to see if we've tried the same voltage 5 times */
2501 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
2503 if (voltage_tries
== 5) {
2504 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2509 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
2511 /* Compute new intel_dp->train_set as requested by target */
2512 intel_get_adjust_train(intel_dp
, link_status
);
2519 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
2521 bool channel_eq
= false;
2522 int tries
, cr_tries
;
2523 uint32_t DP
= intel_dp
->DP
;
2525 /* channel equalization */
2530 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2533 DRM_ERROR("failed to train DP, aborting\n");
2534 intel_dp_link_down(intel_dp
);
2538 intel_dp_set_signal_levels(intel_dp
, &DP
);
2540 /* channel eq pattern */
2541 if (!intel_dp_set_link_train(intel_dp
, DP
,
2542 DP_TRAINING_PATTERN_2
|
2543 DP_LINK_SCRAMBLING_DISABLE
))
2546 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
2547 if (!intel_dp_get_link_status(intel_dp
, link_status
))
2550 /* Make sure clock is still ok */
2551 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2552 intel_dp_start_link_train(intel_dp
);
2557 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2562 /* Try 5 times, then try clock recovery if that fails */
2564 intel_dp_link_down(intel_dp
);
2565 intel_dp_start_link_train(intel_dp
);
2571 /* Compute new intel_dp->train_set as requested by target */
2572 intel_get_adjust_train(intel_dp
, link_status
);
2576 intel_dp_set_idle_link_train(intel_dp
);
2581 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2585 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
2587 intel_dp_set_link_train(intel_dp
, intel_dp
->DP
,
2588 DP_TRAINING_PATTERN_DISABLE
);
2592 intel_dp_link_down(struct intel_dp
*intel_dp
)
2594 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2595 enum port port
= intel_dig_port
->port
;
2596 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2598 struct intel_crtc
*intel_crtc
=
2599 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2600 uint32_t DP
= intel_dp
->DP
;
2603 * DDI code has a strict mode set sequence and we should try to respect
2604 * it, otherwise we might hang the machine in many different ways. So we
2605 * really should be disabling the port only on a complete crtc_disable
2606 * sequence. This function is just called under two conditions on DDI
2608 * - Link train failed while doing crtc_enable, and on this case we
2609 * really should respect the mode set sequence and wait for a
2611 * - Someone turned the monitor off and intel_dp_check_link_status
2612 * called us. We don't need to disable the whole port on this case, so
2613 * when someone turns the monitor on again,
2614 * intel_ddi_prepare_link_retrain will take care of redoing the link
2620 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2623 DRM_DEBUG_KMS("\n");
2625 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2626 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2627 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2629 DP
&= ~DP_LINK_TRAIN_MASK
;
2630 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2632 POSTING_READ(intel_dp
->output_reg
);
2634 /* We don't really know why we're doing this */
2635 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2637 if (HAS_PCH_IBX(dev
) &&
2638 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2639 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2641 /* Hardware workaround: leaving our transcoder select
2642 * set to transcoder B while it's off will prevent the
2643 * corresponding HDMI output on transcoder A.
2645 * Combine this with another hardware workaround:
2646 * transcoder select bit can only be cleared while the
2649 DP
&= ~DP_PIPEB_SELECT
;
2650 I915_WRITE(intel_dp
->output_reg
, DP
);
2652 /* Changes to enable or select take place the vblank
2653 * after being written.
2655 if (WARN_ON(crtc
== NULL
)) {
2656 /* We should never try to disable a port without a crtc
2657 * attached. For paranoia keep the code around for a
2659 POSTING_READ(intel_dp
->output_reg
);
2662 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2665 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2666 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2667 POSTING_READ(intel_dp
->output_reg
);
2668 msleep(intel_dp
->panel_power_down_delay
);
2672 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2674 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2676 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2677 sizeof(intel_dp
->dpcd
)) == 0)
2678 return false; /* aux transfer failed */
2680 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2681 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2682 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2684 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2685 return false; /* DPCD not present */
2687 /* Check if the panel supports PSR */
2688 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
2689 intel_dp_aux_native_read_retry(intel_dp
, DP_PSR_SUPPORT
,
2691 sizeof(intel_dp
->psr_dpcd
));
2692 if (is_edp_psr(intel_dp
))
2693 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2694 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2695 DP_DWN_STRM_PORT_PRESENT
))
2696 return true; /* native DP sink */
2698 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2699 return true; /* no per-port downstream info */
2701 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2702 intel_dp
->downstream_ports
,
2703 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2704 return false; /* downstream port status fetch failed */
2710 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2714 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2717 ironlake_edp_panel_vdd_on(intel_dp
);
2719 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2720 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2721 buf
[0], buf
[1], buf
[2]);
2723 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2724 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2725 buf
[0], buf
[1], buf
[2]);
2727 ironlake_edp_panel_vdd_off(intel_dp
, false);
2731 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2735 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2736 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2737 sink_irq_vector
, 1);
2745 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2747 /* NAK by default */
2748 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2752 * According to DP spec
2755 * 2. Configure link according to Receiver Capabilities
2756 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2757 * 4. Check link status on receipt of hot-plug interrupt
2761 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2763 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2765 u8 link_status
[DP_LINK_STATUS_SIZE
];
2767 if (!intel_encoder
->connectors_active
)
2770 if (WARN_ON(!intel_encoder
->base
.crtc
))
2773 /* Try to read receiver status if the link appears to be up */
2774 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2775 intel_dp_link_down(intel_dp
);
2779 /* Now read the DPCD to see if it's actually running */
2780 if (!intel_dp_get_dpcd(intel_dp
)) {
2781 intel_dp_link_down(intel_dp
);
2785 /* Try to read the source of the interrupt */
2786 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2787 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2788 /* Clear interrupt source */
2789 intel_dp_aux_native_write_1(intel_dp
,
2790 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2793 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2794 intel_dp_handle_test_request(intel_dp
);
2795 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2796 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2799 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2800 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2801 drm_get_encoder_name(&intel_encoder
->base
));
2802 intel_dp_start_link_train(intel_dp
);
2803 intel_dp_complete_link_train(intel_dp
);
2804 intel_dp_stop_link_train(intel_dp
);
2808 /* XXX this is probably wrong for multiple downstream ports */
2809 static enum drm_connector_status
2810 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2812 uint8_t *dpcd
= intel_dp
->dpcd
;
2816 if (!intel_dp_get_dpcd(intel_dp
))
2817 return connector_status_disconnected
;
2819 /* if there's no downstream port, we're done */
2820 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2821 return connector_status_connected
;
2823 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2824 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2827 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2829 return connector_status_unknown
;
2830 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2831 : connector_status_disconnected
;
2834 /* If no HPD, poke DDC gently */
2835 if (drm_probe_ddc(&intel_dp
->adapter
))
2836 return connector_status_connected
;
2838 /* Well we tried, say unknown for unreliable port types */
2839 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2840 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2841 return connector_status_unknown
;
2843 /* Anything else is out of spec, warn and ignore */
2844 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2845 return connector_status_disconnected
;
2848 static enum drm_connector_status
2849 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2851 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2853 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2854 enum drm_connector_status status
;
2856 /* Can't disconnect eDP, but you can close the lid... */
2857 if (is_edp(intel_dp
)) {
2858 status
= intel_panel_detect(dev
);
2859 if (status
== connector_status_unknown
)
2860 status
= connector_status_connected
;
2864 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
2865 return connector_status_disconnected
;
2867 return intel_dp_detect_dpcd(intel_dp
);
2870 static enum drm_connector_status
2871 g4x_dp_detect(struct intel_dp
*intel_dp
)
2873 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2875 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2878 /* Can't disconnect eDP, but you can close the lid... */
2879 if (is_edp(intel_dp
)) {
2880 enum drm_connector_status status
;
2882 status
= intel_panel_detect(dev
);
2883 if (status
== connector_status_unknown
)
2884 status
= connector_status_connected
;
2888 switch (intel_dig_port
->port
) {
2890 bit
= PORTB_HOTPLUG_LIVE_STATUS
;
2893 bit
= PORTC_HOTPLUG_LIVE_STATUS
;
2896 bit
= PORTD_HOTPLUG_LIVE_STATUS
;
2899 return connector_status_unknown
;
2902 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2903 return connector_status_disconnected
;
2905 return intel_dp_detect_dpcd(intel_dp
);
2908 static struct edid
*
2909 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2911 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2913 /* use cached edid if we have one */
2914 if (intel_connector
->edid
) {
2919 if (IS_ERR(intel_connector
->edid
))
2922 size
= (intel_connector
->edid
->extensions
+ 1) * EDID_LENGTH
;
2923 edid
= kmemdup(intel_connector
->edid
, size
, GFP_KERNEL
);
2930 return drm_get_edid(connector
, adapter
);
2934 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2936 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2938 /* use cached edid if we have one */
2939 if (intel_connector
->edid
) {
2941 if (IS_ERR(intel_connector
->edid
))
2944 return intel_connector_update_modes(connector
,
2945 intel_connector
->edid
);
2948 return intel_ddc_get_modes(connector
, adapter
);
2951 static enum drm_connector_status
2952 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2954 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2955 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2956 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2957 struct drm_device
*dev
= connector
->dev
;
2958 enum drm_connector_status status
;
2959 struct edid
*edid
= NULL
;
2961 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2962 connector
->base
.id
, drm_get_connector_name(connector
));
2964 intel_dp
->has_audio
= false;
2966 if (HAS_PCH_SPLIT(dev
))
2967 status
= ironlake_dp_detect(intel_dp
);
2969 status
= g4x_dp_detect(intel_dp
);
2971 if (status
!= connector_status_connected
)
2974 intel_dp_probe_oui(intel_dp
);
2976 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2977 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2979 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2981 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2986 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
2987 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2988 return connector_status_connected
;
2991 static int intel_dp_get_modes(struct drm_connector
*connector
)
2993 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2994 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2995 struct drm_device
*dev
= connector
->dev
;
2998 /* We should parse the EDID data and find out if it has an audio sink
3001 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
3005 /* if eDP has no EDID, fall back to fixed mode */
3006 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3007 struct drm_display_mode
*mode
;
3008 mode
= drm_mode_duplicate(dev
,
3009 intel_connector
->panel
.fixed_mode
);
3011 drm_mode_probed_add(connector
, mode
);
3019 intel_dp_detect_audio(struct drm_connector
*connector
)
3021 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3023 bool has_audio
= false;
3025 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
3027 has_audio
= drm_detect_monitor_audio(edid
);
3035 intel_dp_set_property(struct drm_connector
*connector
,
3036 struct drm_property
*property
,
3039 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3040 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3041 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3042 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3045 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3049 if (property
== dev_priv
->force_audio_property
) {
3053 if (i
== intel_dp
->force_audio
)
3056 intel_dp
->force_audio
= i
;
3058 if (i
== HDMI_AUDIO_AUTO
)
3059 has_audio
= intel_dp_detect_audio(connector
);
3061 has_audio
= (i
== HDMI_AUDIO_ON
);
3063 if (has_audio
== intel_dp
->has_audio
)
3066 intel_dp
->has_audio
= has_audio
;
3070 if (property
== dev_priv
->broadcast_rgb_property
) {
3071 bool old_auto
= intel_dp
->color_range_auto
;
3072 uint32_t old_range
= intel_dp
->color_range
;
3075 case INTEL_BROADCAST_RGB_AUTO
:
3076 intel_dp
->color_range_auto
= true;
3078 case INTEL_BROADCAST_RGB_FULL
:
3079 intel_dp
->color_range_auto
= false;
3080 intel_dp
->color_range
= 0;
3082 case INTEL_BROADCAST_RGB_LIMITED
:
3083 intel_dp
->color_range_auto
= false;
3084 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3090 if (old_auto
== intel_dp
->color_range_auto
&&
3091 old_range
== intel_dp
->color_range
)
3097 if (is_edp(intel_dp
) &&
3098 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3099 if (val
== DRM_MODE_SCALE_NONE
) {
3100 DRM_DEBUG_KMS("no scaling not supported\n");
3104 if (intel_connector
->panel
.fitting_mode
== val
) {
3105 /* the eDP scaling property is not changed */
3108 intel_connector
->panel
.fitting_mode
= val
;
3116 if (intel_encoder
->base
.crtc
)
3117 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3123 intel_dp_connector_destroy(struct drm_connector
*connector
)
3125 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3127 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3128 kfree(intel_connector
->edid
);
3130 /* Can't call is_edp() since the encoder may have been destroyed
3132 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3133 intel_panel_fini(&intel_connector
->panel
);
3135 drm_sysfs_connector_remove(connector
);
3136 drm_connector_cleanup(connector
);
3140 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3142 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3143 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3144 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3146 i2c_del_adapter(&intel_dp
->adapter
);
3147 drm_encoder_cleanup(encoder
);
3148 if (is_edp(intel_dp
)) {
3149 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3150 mutex_lock(&dev
->mode_config
.mutex
);
3151 ironlake_panel_vdd_off_sync(intel_dp
);
3152 mutex_unlock(&dev
->mode_config
.mutex
);
3154 kfree(intel_dig_port
);
3157 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
3158 .dpms
= intel_connector_dpms
,
3159 .detect
= intel_dp_detect
,
3160 .fill_modes
= drm_helper_probe_single_connector_modes
,
3161 .set_property
= intel_dp_set_property
,
3162 .destroy
= intel_dp_connector_destroy
,
3165 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
3166 .get_modes
= intel_dp_get_modes
,
3167 .mode_valid
= intel_dp_mode_valid
,
3168 .best_encoder
= intel_best_encoder
,
3171 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
3172 .destroy
= intel_dp_encoder_destroy
,
3176 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
3178 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3180 intel_dp_check_link_status(intel_dp
);
3183 /* Return which DP Port should be selected for Transcoder DP control */
3185 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
3187 struct drm_device
*dev
= crtc
->dev
;
3188 struct intel_encoder
*intel_encoder
;
3189 struct intel_dp
*intel_dp
;
3191 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3192 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3194 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
3195 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
3196 return intel_dp
->output_reg
;
3202 /* check the VBT to see whether the eDP is on DP-D port */
3203 bool intel_dpd_is_edp(struct drm_device
*dev
)
3205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3206 struct child_device_config
*p_child
;
3209 if (!dev_priv
->vbt
.child_dev_num
)
3212 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
3213 p_child
= dev_priv
->vbt
.child_dev
+ i
;
3215 if (p_child
->dvo_port
== PORT_IDPD
&&
3216 p_child
->device_type
== DEVICE_TYPE_eDP
)
3223 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
3225 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3227 intel_attach_force_audio_property(connector
);
3228 intel_attach_broadcast_rgb_property(connector
);
3229 intel_dp
->color_range_auto
= true;
3231 if (is_edp(intel_dp
)) {
3232 drm_mode_create_scaling_mode_property(connector
->dev
);
3233 drm_object_attach_property(
3235 connector
->dev
->mode_config
.scaling_mode_property
,
3236 DRM_MODE_SCALE_ASPECT
);
3237 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
3242 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
3243 struct intel_dp
*intel_dp
,
3244 struct edp_power_seq
*out
)
3246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3247 struct edp_power_seq cur
, vbt
, spec
, final
;
3248 u32 pp_on
, pp_off
, pp_div
, pp
;
3249 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
3251 if (HAS_PCH_SPLIT(dev
)) {
3252 pp_ctrl_reg
= PCH_PP_CONTROL
;
3253 pp_on_reg
= PCH_PP_ON_DELAYS
;
3254 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3255 pp_div_reg
= PCH_PP_DIVISOR
;
3257 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3259 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
3260 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3261 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3262 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3265 /* Workaround: Need to write PP_CONTROL with the unlock key as
3266 * the very first thing. */
3267 pp
= ironlake_get_pp_control(intel_dp
);
3268 I915_WRITE(pp_ctrl_reg
, pp
);
3270 pp_on
= I915_READ(pp_on_reg
);
3271 pp_off
= I915_READ(pp_off_reg
);
3272 pp_div
= I915_READ(pp_div_reg
);
3274 /* Pull timing values out of registers */
3275 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
3276 PANEL_POWER_UP_DELAY_SHIFT
;
3278 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
3279 PANEL_LIGHT_ON_DELAY_SHIFT
;
3281 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
3282 PANEL_LIGHT_OFF_DELAY_SHIFT
;
3284 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
3285 PANEL_POWER_DOWN_DELAY_SHIFT
;
3287 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
3288 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
3290 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3291 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
3293 vbt
= dev_priv
->vbt
.edp_pps
;
3295 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3296 * our hw here, which are all in 100usec. */
3297 spec
.t1_t3
= 210 * 10;
3298 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
3299 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
3300 spec
.t10
= 500 * 10;
3301 /* This one is special and actually in units of 100ms, but zero
3302 * based in the hw (so we need to add 100 ms). But the sw vbt
3303 * table multiplies it with 1000 to make it in units of 100usec,
3305 spec
.t11_t12
= (510 + 100) * 10;
3307 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3308 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
3310 /* Use the max of the register settings and vbt. If both are
3311 * unset, fall back to the spec limits. */
3312 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3314 max(cur.field, vbt.field))
3315 assign_final(t1_t3
);
3319 assign_final(t11_t12
);
3322 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3323 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
3324 intel_dp
->backlight_on_delay
= get_delay(t8
);
3325 intel_dp
->backlight_off_delay
= get_delay(t9
);
3326 intel_dp
->panel_power_down_delay
= get_delay(t10
);
3327 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
3330 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3331 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
3332 intel_dp
->panel_power_cycle_delay
);
3334 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3335 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
3342 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
3343 struct intel_dp
*intel_dp
,
3344 struct edp_power_seq
*seq
)
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3347 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
3348 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
3349 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
3351 if (HAS_PCH_SPLIT(dev
)) {
3352 pp_on_reg
= PCH_PP_ON_DELAYS
;
3353 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3354 pp_div_reg
= PCH_PP_DIVISOR
;
3356 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3358 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3359 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3360 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3363 /* And finally store the new values in the power sequencer. */
3364 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
3365 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
3366 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
3367 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
3368 /* Compute the divisor for the pp clock, simply match the Bspec
3370 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
3371 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
3372 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
3374 /* Haswell doesn't have any port selection bits for the panel
3375 * power sequencer any more. */
3376 if (IS_VALLEYVIEW(dev
)) {
3377 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
3378 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
3380 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
3381 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
3382 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
3383 port_sel
= PANEL_PORT_SELECT_DPA
;
3385 port_sel
= PANEL_PORT_SELECT_DPD
;
3390 I915_WRITE(pp_on_reg
, pp_on
);
3391 I915_WRITE(pp_off_reg
, pp_off
);
3392 I915_WRITE(pp_div_reg
, pp_div
);
3394 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3395 I915_READ(pp_on_reg
),
3396 I915_READ(pp_off_reg
),
3397 I915_READ(pp_div_reg
));
3400 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
3401 struct intel_connector
*intel_connector
)
3403 struct drm_connector
*connector
= &intel_connector
->base
;
3404 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3405 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3407 struct drm_display_mode
*fixed_mode
= NULL
;
3408 struct edp_power_seq power_seq
= { 0 };
3410 struct drm_display_mode
*scan
;
3413 if (!is_edp(intel_dp
))
3416 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
3418 /* Cache DPCD and EDID for edp. */
3419 ironlake_edp_panel_vdd_on(intel_dp
);
3420 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
3421 ironlake_edp_panel_vdd_off(intel_dp
, false);
3424 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3425 dev_priv
->no_aux_handshake
=
3426 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3427 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3429 /* if this fails, presume the device is a ghost */
3430 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3434 /* We now know it's not a ghost, init power sequence regs. */
3435 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
3438 ironlake_edp_panel_vdd_on(intel_dp
);
3439 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
3441 if (drm_add_edid_modes(connector
, edid
)) {
3442 drm_mode_connector_update_edid_property(connector
,
3444 drm_edid_to_eld(connector
, edid
);
3447 edid
= ERR_PTR(-EINVAL
);
3450 edid
= ERR_PTR(-ENOENT
);
3452 intel_connector
->edid
= edid
;
3454 /* prefer fixed mode from EDID if available */
3455 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
3456 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
3457 fixed_mode
= drm_mode_duplicate(dev
, scan
);
3462 /* fallback to VBT if available for eDP */
3463 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
3464 fixed_mode
= drm_mode_duplicate(dev
,
3465 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
3467 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
3470 ironlake_edp_panel_vdd_off(intel_dp
, false);
3472 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
3473 intel_panel_setup_backlight(connector
);
3479 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
3480 struct intel_connector
*intel_connector
)
3482 struct drm_connector
*connector
= &intel_connector
->base
;
3483 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3484 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3485 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3487 enum port port
= intel_dig_port
->port
;
3488 const char *name
= NULL
;
3491 /* Preserve the current hw state. */
3492 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
3493 intel_dp
->attached_connector
= intel_connector
;
3495 type
= DRM_MODE_CONNECTOR_DisplayPort
;
3497 * FIXME : We need to initialize built-in panels before external panels.
3498 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3502 type
= DRM_MODE_CONNECTOR_eDP
;
3505 if (IS_VALLEYVIEW(dev
))
3506 type
= DRM_MODE_CONNECTOR_eDP
;
3509 if (HAS_PCH_SPLIT(dev
) && intel_dpd_is_edp(dev
))
3510 type
= DRM_MODE_CONNECTOR_eDP
;
3512 default: /* silence GCC warning */
3517 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3518 * for DP the encoder type can be set by the caller to
3519 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3521 if (type
== DRM_MODE_CONNECTOR_eDP
)
3522 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
3524 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3525 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
3528 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
3529 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
3531 connector
->interlace_allowed
= true;
3532 connector
->doublescan_allowed
= 0;
3534 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
3535 ironlake_panel_vdd_work
);
3537 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3538 drm_sysfs_connector_add(connector
);
3541 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3543 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3545 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
3547 switch (intel_dig_port
->port
) {
3549 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
3552 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
3555 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
3558 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
3565 /* Set up the DDC bus. */
3568 intel_encoder
->hpd_pin
= HPD_PORT_A
;
3572 intel_encoder
->hpd_pin
= HPD_PORT_B
;
3576 intel_encoder
->hpd_pin
= HPD_PORT_C
;
3580 intel_encoder
->hpd_pin
= HPD_PORT_D
;
3587 error
= intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
3588 WARN(error
, "intel_dp_i2c_init failed with error %d for port %c\n",
3589 error
, port_name(port
));
3591 intel_dp
->psr_setup_done
= false;
3593 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
3594 i2c_del_adapter(&intel_dp
->adapter
);
3595 if (is_edp(intel_dp
)) {
3596 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3597 mutex_lock(&dev
->mode_config
.mutex
);
3598 ironlake_panel_vdd_off_sync(intel_dp
);
3599 mutex_unlock(&dev
->mode_config
.mutex
);
3601 drm_sysfs_connector_remove(connector
);
3602 drm_connector_cleanup(connector
);
3606 intel_dp_add_properties(intel_dp
, connector
);
3608 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3609 * 0xd. Failure to do so will result in spurious interrupts being
3610 * generated on the port when a cable is not attached.
3612 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
3613 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
3614 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
3621 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
3623 struct intel_digital_port
*intel_dig_port
;
3624 struct intel_encoder
*intel_encoder
;
3625 struct drm_encoder
*encoder
;
3626 struct intel_connector
*intel_connector
;
3628 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3629 if (!intel_dig_port
)
3632 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
3633 if (!intel_connector
) {
3634 kfree(intel_dig_port
);
3638 intel_encoder
= &intel_dig_port
->base
;
3639 encoder
= &intel_encoder
->base
;
3641 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
3642 DRM_MODE_ENCODER_TMDS
);
3644 intel_encoder
->compute_config
= intel_dp_compute_config
;
3645 intel_encoder
->mode_set
= intel_dp_mode_set
;
3646 intel_encoder
->disable
= intel_disable_dp
;
3647 intel_encoder
->post_disable
= intel_post_disable_dp
;
3648 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
3649 intel_encoder
->get_config
= intel_dp_get_config
;
3650 if (IS_VALLEYVIEW(dev
)) {
3651 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
3652 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
3653 intel_encoder
->enable
= vlv_enable_dp
;
3655 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
3656 intel_encoder
->enable
= g4x_enable_dp
;
3659 intel_dig_port
->port
= port
;
3660 intel_dig_port
->dp
.output_reg
= output_reg
;
3662 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3663 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3664 intel_encoder
->cloneable
= false;
3665 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
3667 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
3668 drm_encoder_cleanup(encoder
);
3669 kfree(intel_dig_port
);
3670 kfree(intel_connector
);