2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll
[] = {
48 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
50 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
53 static const struct dp_link_dpll pch_dpll
[] = {
55 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
57 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
60 static const struct dp_link_dpll vlv_dpll
[] = {
62 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
64 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
71 static const struct dp_link_dpll chv_dpll
[] = {
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
77 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
79 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
80 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
81 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
92 static bool is_edp(struct intel_dp
*intel_dp
)
94 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
96 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
99 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
101 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
103 return intel_dig_port
->base
.base
.dev
;
106 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
108 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
111 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
112 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
);
113 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
116 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
118 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
119 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
121 switch (max_link_bw
) {
122 case DP_LINK_BW_1_62
:
125 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
126 if ((IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8) &&
127 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
128 max_link_bw
= DP_LINK_BW_5_4
;
130 max_link_bw
= DP_LINK_BW_2_7
;
133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw
= DP_LINK_BW_1_62
;
142 * The units on the numbers in the next two are... bizarre. Examples will
143 * make it clearer; this one parallels an example in the eDP spec.
145 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
147 * 270000 * 1 * 8 / 10 == 216000
149 * The actual data capacity of that configuration is 2.16Gbit/s, so the
150 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
151 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
152 * 119000. At 18bpp that's 2142000 kilobits per second.
154 * Thus the strange-looking division by 10 in intel_dp_link_required, to
155 * get the result in decakilobits instead of kilobits.
159 intel_dp_link_required(int pixel_clock
, int bpp
)
161 return (pixel_clock
* bpp
+ 9) / 10;
165 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
167 return (max_link_clock
* max_lanes
* 8) / 10;
170 static enum drm_mode_status
171 intel_dp_mode_valid(struct drm_connector
*connector
,
172 struct drm_display_mode
*mode
)
174 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
175 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
176 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
177 int target_clock
= mode
->clock
;
178 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
180 if (is_edp(intel_dp
) && fixed_mode
) {
181 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
184 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
187 target_clock
= fixed_mode
->clock
;
190 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
191 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
193 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
194 mode_rate
= intel_dp_link_required(target_clock
, 18);
196 if (mode_rate
> max_rate
)
197 return MODE_CLOCK_HIGH
;
199 if (mode
->clock
< 10000)
200 return MODE_CLOCK_LOW
;
202 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
203 return MODE_H_ILLEGAL
;
209 pack_aux(uint8_t *src
, int src_bytes
)
216 for (i
= 0; i
< src_bytes
; i
++)
217 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
222 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
227 for (i
= 0; i
< dst_bytes
; i
++)
228 dst
[i
] = src
>> ((3-i
) * 8);
231 /* hrawclock is 1/4 the FSB frequency */
233 intel_hrawclk(struct drm_device
*dev
)
235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
238 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
239 if (IS_VALLEYVIEW(dev
))
242 clkcfg
= I915_READ(CLKCFG
);
243 switch (clkcfg
& CLKCFG_FSB_MASK
) {
252 case CLKCFG_FSB_1067
:
254 case CLKCFG_FSB_1333
:
256 /* these two are just a guess; one of them might be right */
257 case CLKCFG_FSB_1600
:
258 case CLKCFG_FSB_1600_ALT
:
266 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
267 struct intel_dp
*intel_dp
,
268 struct edp_power_seq
*out
);
270 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
271 struct intel_dp
*intel_dp
,
272 struct edp_power_seq
*out
);
275 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
277 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
278 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
279 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
281 enum port port
= intel_dig_port
->port
;
284 /* modeset should have pipe */
286 return to_intel_crtc(crtc
)->pipe
;
288 /* init time, try to find a pipe with this port selected */
289 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
290 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
291 PANEL_PORT_SELECT_MASK
;
292 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
294 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
302 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
304 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
306 if (HAS_PCH_SPLIT(dev
))
307 return PCH_PP_CONTROL
;
309 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
312 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
314 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
316 if (HAS_PCH_SPLIT(dev
))
317 return PCH_PP_STATUS
;
319 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
322 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
324 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
327 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
330 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
332 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
334 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
335 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
336 enum intel_display_power_domain power_domain
;
338 power_domain
= intel_display_port_power_domain(intel_encoder
);
339 return intel_display_power_enabled(dev_priv
, power_domain
) &&
340 (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
344 intel_dp_check_edp(struct intel_dp
*intel_dp
)
346 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
349 if (!is_edp(intel_dp
))
352 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
353 WARN(1, "eDP powered off while attempting aux channel communication.\n");
354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
355 I915_READ(_pp_stat_reg(intel_dp
)),
356 I915_READ(_pp_ctrl_reg(intel_dp
)));
361 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
363 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
364 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
366 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
370 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
372 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
373 msecs_to_jiffies_timeout(10));
375 done
= wait_for_atomic(C
, 10) == 0;
377 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
384 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
386 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
387 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
390 * The clock divider is based off the hrawclk, and would like to run at
391 * 2MHz. So, take the hrawclk value and divide by 2 and use that
393 return index
? 0 : intel_hrawclk(dev
) / 2;
396 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
398 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
399 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
404 if (intel_dig_port
->port
== PORT_A
) {
405 if (IS_GEN6(dev
) || IS_GEN7(dev
))
406 return 200; /* SNB & IVB eDP input clock at 400Mhz */
408 return 225; /* eDP input clock at 450Mhz */
410 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
414 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
416 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
417 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
420 if (intel_dig_port
->port
== PORT_A
) {
423 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
424 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
425 /* Workaround for non-ULT HSW */
432 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
436 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
438 return index
? 0 : 100;
441 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
444 uint32_t aux_clock_divider
)
446 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
447 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
448 uint32_t precharge
, timeout
;
455 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
456 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
458 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
460 return DP_AUX_CH_CTL_SEND_BUSY
|
462 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
463 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
465 DP_AUX_CH_CTL_RECEIVE_ERROR
|
466 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
467 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
468 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
472 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
473 uint8_t *send
, int send_bytes
,
474 uint8_t *recv
, int recv_size
)
476 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
477 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
479 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
480 uint32_t ch_data
= ch_ctl
+ 4;
481 uint32_t aux_clock_divider
;
482 int i
, ret
, recv_bytes
;
485 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
488 vdd
= _edp_panel_vdd_on(intel_dp
);
490 /* dp aux is extremely sensitive to irq latency, hence request the
491 * lowest possible wakeup latency and so prevent the cpu from going into
494 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
496 intel_dp_check_edp(intel_dp
);
498 intel_aux_display_runtime_get(dev_priv
);
500 /* Try to wait for any previous AUX channel activity */
501 for (try = 0; try < 3; try++) {
502 status
= I915_READ_NOTRACE(ch_ctl
);
503 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
509 WARN(1, "dp_aux_ch not started status 0x%08x\n",
515 /* Only 5 data registers! */
516 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
521 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
522 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
527 /* Must try at least 3 times according to DP spec */
528 for (try = 0; try < 5; try++) {
529 /* Load the send data into the aux channel data registers */
530 for (i
= 0; i
< send_bytes
; i
+= 4)
531 I915_WRITE(ch_data
+ i
,
532 pack_aux(send
+ i
, send_bytes
- i
));
534 /* Send the command and wait for it to complete */
535 I915_WRITE(ch_ctl
, send_ctl
);
537 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
539 /* Clear done status and any errors */
543 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
544 DP_AUX_CH_CTL_RECEIVE_ERROR
);
546 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
547 DP_AUX_CH_CTL_RECEIVE_ERROR
))
549 if (status
& DP_AUX_CH_CTL_DONE
)
552 if (status
& DP_AUX_CH_CTL_DONE
)
556 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
557 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
562 /* Check for timeout or receive error.
563 * Timeouts occur when the sink is not connected
565 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
566 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
571 /* Timeouts occur when the device isn't connected, so they're
572 * "normal" -- don't fill the kernel log with these */
573 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
574 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
579 /* Unload any bytes sent back from the other side */
580 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
581 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
582 if (recv_bytes
> recv_size
)
583 recv_bytes
= recv_size
;
585 for (i
= 0; i
< recv_bytes
; i
+= 4)
586 unpack_aux(I915_READ(ch_data
+ i
),
587 recv
+ i
, recv_bytes
- i
);
591 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
592 intel_aux_display_runtime_put(dev_priv
);
595 edp_panel_vdd_off(intel_dp
, false);
600 #define BARE_ADDRESS_SIZE 3
601 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
603 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
605 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
606 uint8_t txbuf
[20], rxbuf
[20];
607 size_t txsize
, rxsize
;
610 txbuf
[0] = msg
->request
<< 4;
611 txbuf
[1] = msg
->address
>> 8;
612 txbuf
[2] = msg
->address
& 0xff;
613 txbuf
[3] = msg
->size
- 1;
615 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
616 case DP_AUX_NATIVE_WRITE
:
617 case DP_AUX_I2C_WRITE
:
618 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
621 if (WARN_ON(txsize
> 20))
624 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
626 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
628 msg
->reply
= rxbuf
[0] >> 4;
630 /* Return payload size. */
635 case DP_AUX_NATIVE_READ
:
636 case DP_AUX_I2C_READ
:
637 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
638 rxsize
= msg
->size
+ 1;
640 if (WARN_ON(rxsize
> 20))
643 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
645 msg
->reply
= rxbuf
[0] >> 4;
647 * Assume happy day, and copy the data. The caller is
648 * expected to check msg->reply before touching it.
650 * Return payload size.
653 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
666 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
668 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
669 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
670 enum port port
= intel_dig_port
->port
;
671 const char *name
= NULL
;
676 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
680 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
684 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
688 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
696 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
698 intel_dp
->aux
.name
= name
;
699 intel_dp
->aux
.dev
= dev
->dev
;
700 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
702 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
703 connector
->base
.kdev
->kobj
.name
);
705 ret
= drm_dp_aux_register_i2c_bus(&intel_dp
->aux
);
707 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
712 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
713 &intel_dp
->aux
.ddc
.dev
.kobj
,
714 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
716 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
717 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
722 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
724 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
726 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
727 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
728 intel_connector_unregister(intel_connector
);
732 intel_dp_set_clock(struct intel_encoder
*encoder
,
733 struct intel_crtc_config
*pipe_config
, int link_bw
)
735 struct drm_device
*dev
= encoder
->base
.dev
;
736 const struct dp_link_dpll
*divisor
= NULL
;
741 count
= ARRAY_SIZE(gen4_dpll
);
742 } else if (IS_HASWELL(dev
)) {
743 /* Haswell has special-purpose DP DDI clocks. */
744 } else if (HAS_PCH_SPLIT(dev
)) {
746 count
= ARRAY_SIZE(pch_dpll
);
747 } else if (IS_CHERRYVIEW(dev
)) {
749 count
= ARRAY_SIZE(chv_dpll
);
750 } else if (IS_VALLEYVIEW(dev
)) {
752 count
= ARRAY_SIZE(vlv_dpll
);
755 if (divisor
&& count
) {
756 for (i
= 0; i
< count
; i
++) {
757 if (link_bw
== divisor
[i
].link_bw
) {
758 pipe_config
->dpll
= divisor
[i
].dpll
;
759 pipe_config
->clock_set
= true;
767 intel_dp_set_m2_n2(struct intel_crtc
*crtc
, struct intel_link_m_n
*m_n
)
769 struct drm_device
*dev
= crtc
->base
.dev
;
770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
771 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
773 I915_WRITE(PIPE_DATA_M2(transcoder
),
774 TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
775 I915_WRITE(PIPE_DATA_N2(transcoder
), m_n
->gmch_n
);
776 I915_WRITE(PIPE_LINK_M2(transcoder
), m_n
->link_m
);
777 I915_WRITE(PIPE_LINK_N2(transcoder
), m_n
->link_n
);
781 intel_dp_compute_config(struct intel_encoder
*encoder
,
782 struct intel_crtc_config
*pipe_config
)
784 struct drm_device
*dev
= encoder
->base
.dev
;
785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
786 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
787 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
788 enum port port
= dp_to_dig_port(intel_dp
)->port
;
789 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
790 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
791 int lane_count
, clock
;
792 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
793 /* Conveniently, the link BW constants become indices with a shift...*/
794 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
796 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
797 int link_avail
, link_clock
;
799 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
800 pipe_config
->has_pch_encoder
= true;
802 pipe_config
->has_dp_encoder
= true;
803 pipe_config
->has_audio
= intel_dp
->has_audio
;
805 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
806 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
808 if (!HAS_PCH_SPLIT(dev
))
809 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
810 intel_connector
->panel
.fitting_mode
);
812 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
813 intel_connector
->panel
.fitting_mode
);
816 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
819 DRM_DEBUG_KMS("DP link computation with max lane count %i "
820 "max bw %02x pixel clock %iKHz\n",
821 max_lane_count
, bws
[max_clock
],
822 adjusted_mode
->crtc_clock
);
824 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
826 bpp
= pipe_config
->pipe_bpp
;
827 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
828 dev_priv
->vbt
.edp_bpp
< bpp
) {
829 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
830 dev_priv
->vbt
.edp_bpp
);
831 bpp
= dev_priv
->vbt
.edp_bpp
;
834 for (; bpp
>= 6*3; bpp
-= 2*3) {
835 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
838 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
839 for (clock
= 0; clock
<= max_clock
; clock
++) {
840 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
841 link_avail
= intel_dp_max_data_rate(link_clock
,
844 if (mode_rate
<= link_avail
) {
854 if (intel_dp
->color_range_auto
) {
857 * CEA-861-E - 5.1 Default Encoding Parameters
858 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
860 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
861 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
863 intel_dp
->color_range
= 0;
866 if (intel_dp
->color_range
)
867 pipe_config
->limited_color_range
= true;
869 intel_dp
->link_bw
= bws
[clock
];
870 intel_dp
->lane_count
= lane_count
;
871 pipe_config
->pipe_bpp
= bpp
;
872 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
874 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
875 intel_dp
->link_bw
, intel_dp
->lane_count
,
876 pipe_config
->port_clock
, bpp
);
877 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
878 mode_rate
, link_avail
);
880 intel_link_compute_m_n(bpp
, lane_count
,
881 adjusted_mode
->crtc_clock
,
882 pipe_config
->port_clock
,
883 &pipe_config
->dp_m_n
);
885 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
886 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
887 intel_link_compute_m_n(bpp
, lane_count
,
888 intel_connector
->panel
.downclock_mode
->clock
,
889 pipe_config
->port_clock
,
890 &pipe_config
->dp_m2_n2
);
893 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
898 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
900 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
901 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
902 struct drm_device
*dev
= crtc
->base
.dev
;
903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
906 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
907 dpa_ctl
= I915_READ(DP_A
);
908 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
910 if (crtc
->config
.port_clock
== 162000) {
911 /* For a long time we've carried around a ILK-DevA w/a for the
912 * 160MHz clock. If we're really unlucky, it's still required.
914 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
915 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
916 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
918 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
919 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
922 I915_WRITE(DP_A
, dpa_ctl
);
928 static void intel_dp_prepare(struct intel_encoder
*encoder
)
930 struct drm_device
*dev
= encoder
->base
.dev
;
931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
932 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
933 enum port port
= dp_to_dig_port(intel_dp
)->port
;
934 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
935 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
938 * There are four kinds of DP registers:
945 * IBX PCH and CPU are the same for almost everything,
946 * except that the CPU DP PLL is configured in this
949 * CPT PCH is quite different, having many bits moved
950 * to the TRANS_DP_CTL register instead. That
951 * configuration happens (oddly) in ironlake_pch_enable
954 /* Preserve the BIOS-computed detected bit. This is
955 * supposed to be read-only.
957 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
959 /* Handle DP bits in common between all three register formats */
960 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
961 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
963 if (crtc
->config
.has_audio
) {
964 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
965 pipe_name(crtc
->pipe
));
966 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
967 intel_write_eld(&encoder
->base
, adjusted_mode
);
970 /* Split out the IBX/CPU vs CPT settings */
972 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
973 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
974 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
975 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
976 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
977 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
979 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
980 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
982 intel_dp
->DP
|= crtc
->pipe
<< 29;
983 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
984 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
985 intel_dp
->DP
|= intel_dp
->color_range
;
987 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
988 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
989 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
990 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
991 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
993 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
994 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
996 if (!IS_CHERRYVIEW(dev
)) {
998 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1000 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1003 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1007 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1010 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1011 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1013 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1014 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1016 static void wait_panel_status(struct intel_dp
*intel_dp
,
1020 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1022 u32 pp_stat_reg
, pp_ctrl_reg
;
1024 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1025 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1027 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1029 I915_READ(pp_stat_reg
),
1030 I915_READ(pp_ctrl_reg
));
1032 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1033 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1034 I915_READ(pp_stat_reg
),
1035 I915_READ(pp_ctrl_reg
));
1038 DRM_DEBUG_KMS("Wait complete\n");
1041 static void wait_panel_on(struct intel_dp
*intel_dp
)
1043 DRM_DEBUG_KMS("Wait for panel power on\n");
1044 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1047 static void wait_panel_off(struct intel_dp
*intel_dp
)
1049 DRM_DEBUG_KMS("Wait for panel power off time\n");
1050 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1053 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1055 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1057 /* When we disable the VDD override bit last we have to do the manual
1059 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1060 intel_dp
->panel_power_cycle_delay
);
1062 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1065 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1067 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1068 intel_dp
->backlight_on_delay
);
1071 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1073 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1074 intel_dp
->backlight_off_delay
);
1077 /* Read the current pp_control value, unlocking the register if it
1081 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1083 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1087 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1088 control
&= ~PANEL_UNLOCK_MASK
;
1089 control
|= PANEL_UNLOCK_REGS
;
1093 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1095 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1096 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1097 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1099 enum intel_display_power_domain power_domain
;
1101 u32 pp_stat_reg
, pp_ctrl_reg
;
1102 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1104 if (!is_edp(intel_dp
))
1107 intel_dp
->want_panel_vdd
= true;
1109 if (edp_have_panel_vdd(intel_dp
))
1110 return need_to_disable
;
1112 power_domain
= intel_display_port_power_domain(intel_encoder
);
1113 intel_display_power_get(dev_priv
, power_domain
);
1115 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1117 if (!edp_have_panel_power(intel_dp
))
1118 wait_panel_power_cycle(intel_dp
);
1120 pp
= ironlake_get_pp_control(intel_dp
);
1121 pp
|= EDP_FORCE_VDD
;
1123 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1124 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1126 I915_WRITE(pp_ctrl_reg
, pp
);
1127 POSTING_READ(pp_ctrl_reg
);
1128 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1129 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1131 * If the panel wasn't on, delay before accessing aux channel
1133 if (!edp_have_panel_power(intel_dp
)) {
1134 DRM_DEBUG_KMS("eDP was not running\n");
1135 msleep(intel_dp
->panel_power_up_delay
);
1138 return need_to_disable
;
1141 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1143 if (is_edp(intel_dp
)) {
1144 bool vdd
= _edp_panel_vdd_on(intel_dp
);
1146 WARN(!vdd
, "eDP VDD already requested on\n");
1150 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1152 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1155 u32 pp_stat_reg
, pp_ctrl_reg
;
1157 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1159 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1160 struct intel_digital_port
*intel_dig_port
=
1161 dp_to_dig_port(intel_dp
);
1162 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1163 enum intel_display_power_domain power_domain
;
1165 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1167 pp
= ironlake_get_pp_control(intel_dp
);
1168 pp
&= ~EDP_FORCE_VDD
;
1170 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1171 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1173 I915_WRITE(pp_ctrl_reg
, pp
);
1174 POSTING_READ(pp_ctrl_reg
);
1176 /* Make sure sequencer is idle before allowing subsequent activity */
1177 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1178 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1180 if ((pp
& POWER_TARGET_ON
) == 0)
1181 intel_dp
->last_power_cycle
= jiffies
;
1183 power_domain
= intel_display_port_power_domain(intel_encoder
);
1184 intel_display_power_put(dev_priv
, power_domain
);
1188 static void edp_panel_vdd_work(struct work_struct
*__work
)
1190 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1191 struct intel_dp
, panel_vdd_work
);
1192 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1194 mutex_lock(&dev
->mode_config
.mutex
);
1195 edp_panel_vdd_off_sync(intel_dp
);
1196 mutex_unlock(&dev
->mode_config
.mutex
);
1199 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1201 if (!is_edp(intel_dp
))
1204 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1206 intel_dp
->want_panel_vdd
= false;
1209 edp_panel_vdd_off_sync(intel_dp
);
1212 * Queue the timer to fire a long
1213 * time from now (relative to the power down delay)
1214 * to keep the panel power up across a sequence of operations
1216 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1217 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1221 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1223 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1228 if (!is_edp(intel_dp
))
1231 DRM_DEBUG_KMS("Turn eDP power on\n");
1233 if (edp_have_panel_power(intel_dp
)) {
1234 DRM_DEBUG_KMS("eDP power already on\n");
1238 wait_panel_power_cycle(intel_dp
);
1240 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1241 pp
= ironlake_get_pp_control(intel_dp
);
1243 /* ILK workaround: disable reset around power sequence */
1244 pp
&= ~PANEL_POWER_RESET
;
1245 I915_WRITE(pp_ctrl_reg
, pp
);
1246 POSTING_READ(pp_ctrl_reg
);
1249 pp
|= POWER_TARGET_ON
;
1251 pp
|= PANEL_POWER_RESET
;
1253 I915_WRITE(pp_ctrl_reg
, pp
);
1254 POSTING_READ(pp_ctrl_reg
);
1256 wait_panel_on(intel_dp
);
1257 intel_dp
->last_power_on
= jiffies
;
1260 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1261 I915_WRITE(pp_ctrl_reg
, pp
);
1262 POSTING_READ(pp_ctrl_reg
);
1266 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1268 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1269 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1270 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1272 enum intel_display_power_domain power_domain
;
1276 if (!is_edp(intel_dp
))
1279 DRM_DEBUG_KMS("Turn eDP power off\n");
1281 edp_wait_backlight_off(intel_dp
);
1283 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1285 pp
= ironlake_get_pp_control(intel_dp
);
1286 /* We need to switch off panel power _and_ force vdd, for otherwise some
1287 * panels get very unhappy and cease to work. */
1288 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1291 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1293 intel_dp
->want_panel_vdd
= false;
1295 I915_WRITE(pp_ctrl_reg
, pp
);
1296 POSTING_READ(pp_ctrl_reg
);
1298 intel_dp
->last_power_cycle
= jiffies
;
1299 wait_panel_off(intel_dp
);
1301 /* We got a reference when we enabled the VDD. */
1302 power_domain
= intel_display_port_power_domain(intel_encoder
);
1303 intel_display_power_put(dev_priv
, power_domain
);
1306 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1308 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1309 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1314 if (!is_edp(intel_dp
))
1317 DRM_DEBUG_KMS("\n");
1319 * If we enable the backlight right away following a panel power
1320 * on, we may see slight flicker as the panel syncs with the eDP
1321 * link. So delay a bit to make sure the image is solid before
1322 * allowing it to appear.
1324 wait_backlight_on(intel_dp
);
1325 pp
= ironlake_get_pp_control(intel_dp
);
1326 pp
|= EDP_BLC_ENABLE
;
1328 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1330 I915_WRITE(pp_ctrl_reg
, pp
);
1331 POSTING_READ(pp_ctrl_reg
);
1333 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1336 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1338 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1343 if (!is_edp(intel_dp
))
1346 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1348 DRM_DEBUG_KMS("\n");
1349 pp
= ironlake_get_pp_control(intel_dp
);
1350 pp
&= ~EDP_BLC_ENABLE
;
1352 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1354 I915_WRITE(pp_ctrl_reg
, pp
);
1355 POSTING_READ(pp_ctrl_reg
);
1356 intel_dp
->last_backlight_off
= jiffies
;
1359 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1361 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1362 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1363 struct drm_device
*dev
= crtc
->dev
;
1364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1367 assert_pipe_disabled(dev_priv
,
1368 to_intel_crtc(crtc
)->pipe
);
1370 DRM_DEBUG_KMS("\n");
1371 dpa_ctl
= I915_READ(DP_A
);
1372 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1373 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1375 /* We don't adjust intel_dp->DP while tearing down the link, to
1376 * facilitate link retraining (e.g. after hotplug). Hence clear all
1377 * enable bits here to ensure that we don't enable too much. */
1378 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1379 intel_dp
->DP
|= DP_PLL_ENABLE
;
1380 I915_WRITE(DP_A
, intel_dp
->DP
);
1385 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1387 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1388 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1389 struct drm_device
*dev
= crtc
->dev
;
1390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1393 assert_pipe_disabled(dev_priv
,
1394 to_intel_crtc(crtc
)->pipe
);
1396 dpa_ctl
= I915_READ(DP_A
);
1397 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1398 "dp pll off, should be on\n");
1399 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1401 /* We can't rely on the value tracked for the DP register in
1402 * intel_dp->DP because link_down must not change that (otherwise link
1403 * re-training will fail. */
1404 dpa_ctl
&= ~DP_PLL_ENABLE
;
1405 I915_WRITE(DP_A
, dpa_ctl
);
1410 /* If the sink supports it, try to set the power state appropriately */
1411 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1415 /* Should have a valid DPCD by this point */
1416 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1419 if (mode
!= DRM_MODE_DPMS_ON
) {
1420 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1423 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1426 * When turning on, we need to retry for 1ms to give the sink
1429 for (i
= 0; i
< 3; i
++) {
1430 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1439 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1442 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1443 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1444 struct drm_device
*dev
= encoder
->base
.dev
;
1445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1446 enum intel_display_power_domain power_domain
;
1449 power_domain
= intel_display_port_power_domain(encoder
);
1450 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1453 tmp
= I915_READ(intel_dp
->output_reg
);
1455 if (!(tmp
& DP_PORT_EN
))
1458 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1459 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1460 } else if (IS_CHERRYVIEW(dev
)) {
1461 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1462 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1463 *pipe
= PORT_TO_PIPE(tmp
);
1469 switch (intel_dp
->output_reg
) {
1471 trans_sel
= TRANS_DP_PORT_SEL_B
;
1474 trans_sel
= TRANS_DP_PORT_SEL_C
;
1477 trans_sel
= TRANS_DP_PORT_SEL_D
;
1484 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1485 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1491 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1492 intel_dp
->output_reg
);
1498 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1499 struct intel_crtc_config
*pipe_config
)
1501 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1503 struct drm_device
*dev
= encoder
->base
.dev
;
1504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1505 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1506 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1509 tmp
= I915_READ(intel_dp
->output_reg
);
1510 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1511 pipe_config
->has_audio
= true;
1513 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1514 if (tmp
& DP_SYNC_HS_HIGH
)
1515 flags
|= DRM_MODE_FLAG_PHSYNC
;
1517 flags
|= DRM_MODE_FLAG_NHSYNC
;
1519 if (tmp
& DP_SYNC_VS_HIGH
)
1520 flags
|= DRM_MODE_FLAG_PVSYNC
;
1522 flags
|= DRM_MODE_FLAG_NVSYNC
;
1524 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1525 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1526 flags
|= DRM_MODE_FLAG_PHSYNC
;
1528 flags
|= DRM_MODE_FLAG_NHSYNC
;
1530 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1531 flags
|= DRM_MODE_FLAG_PVSYNC
;
1533 flags
|= DRM_MODE_FLAG_NVSYNC
;
1536 pipe_config
->adjusted_mode
.flags
|= flags
;
1538 pipe_config
->has_dp_encoder
= true;
1540 intel_dp_get_m_n(crtc
, pipe_config
);
1542 if (port
== PORT_A
) {
1543 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1544 pipe_config
->port_clock
= 162000;
1546 pipe_config
->port_clock
= 270000;
1549 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1550 &pipe_config
->dp_m_n
);
1552 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1553 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1555 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1557 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1558 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1560 * This is a big fat ugly hack.
1562 * Some machines in UEFI boot mode provide us a VBT that has 18
1563 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1564 * unknown we fail to light up. Yet the same BIOS boots up with
1565 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1566 * max, not what it tells us to use.
1568 * Note: This will still be broken if the eDP panel is not lit
1569 * up by the BIOS, and thus we can't get the mode at module
1572 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1573 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1574 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1578 static bool is_edp_psr(struct drm_device
*dev
)
1580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1582 return dev_priv
->psr
.sink_support
;
1585 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1592 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1595 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1596 struct edp_vsc_psr
*vsc_psr
)
1598 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1599 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1602 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1603 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1604 uint32_t *data
= (uint32_t *) vsc_psr
;
1607 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1608 the video DIP being updated before program video DIP data buffer
1609 registers for DIP being updated. */
1610 I915_WRITE(ctl_reg
, 0);
1611 POSTING_READ(ctl_reg
);
1613 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1614 if (i
< sizeof(struct edp_vsc_psr
))
1615 I915_WRITE(data_reg
+ i
, *data
++);
1617 I915_WRITE(data_reg
+ i
, 0);
1620 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1621 POSTING_READ(ctl_reg
);
1624 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1626 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1628 struct edp_vsc_psr psr_vsc
;
1630 if (intel_dp
->psr_setup_done
)
1633 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1634 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1635 psr_vsc
.sdp_header
.HB0
= 0;
1636 psr_vsc
.sdp_header
.HB1
= 0x7;
1637 psr_vsc
.sdp_header
.HB2
= 0x2;
1638 psr_vsc
.sdp_header
.HB3
= 0x8;
1639 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1641 /* Avoid continuous PSR exit by masking memup and hpd */
1642 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1643 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1645 intel_dp
->psr_setup_done
= true;
1648 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1650 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1652 uint32_t aux_clock_divider
;
1653 int precharge
= 0x3;
1654 int msg_size
= 5; /* Header(4) + Message(1) */
1656 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1658 /* Enable PSR in sink */
1659 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
)
1660 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1661 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1663 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1664 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1666 /* Setup AUX registers */
1667 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1668 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1669 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1670 DP_AUX_CH_CTL_TIME_OUT_400us
|
1671 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1672 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1673 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1676 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1678 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1680 uint32_t max_sleep_time
= 0x1f;
1681 uint32_t idle_frames
= 1;
1683 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1685 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
1686 val
|= EDP_PSR_LINK_STANDBY
;
1687 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1688 val
|= EDP_PSR_TP1_TIME_0us
;
1689 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1691 val
|= EDP_PSR_LINK_DISABLE
;
1693 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1694 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
1695 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1696 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1700 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1702 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1703 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1705 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1706 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1707 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(crtc
->primary
->fb
)->obj
;
1708 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
1710 dev_priv
->psr
.source_ok
= false;
1712 if (!HAS_PSR(dev
)) {
1713 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1717 if ((intel_encoder
->type
!= INTEL_OUTPUT_EDP
) ||
1718 (dig_port
->port
!= PORT_A
)) {
1719 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1723 if (!i915
.enable_psr
) {
1724 DRM_DEBUG_KMS("PSR disable by flag\n");
1728 crtc
= dig_port
->base
.base
.crtc
;
1730 DRM_DEBUG_KMS("crtc not active for PSR\n");
1734 intel_crtc
= to_intel_crtc(crtc
);
1735 if (!intel_crtc_active(crtc
)) {
1736 DRM_DEBUG_KMS("crtc not active for PSR\n");
1740 obj
= to_intel_framebuffer(crtc
->primary
->fb
)->obj
;
1741 if (obj
->tiling_mode
!= I915_TILING_X
||
1742 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1743 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1747 if (I915_READ(SPRCTL(intel_crtc
->pipe
)) & SPRITE_ENABLE
) {
1748 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1752 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1754 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1758 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1759 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1763 dev_priv
->psr
.source_ok
= true;
1767 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1769 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1771 if (!intel_edp_psr_match_conditions(intel_dp
) ||
1772 intel_edp_is_psr_enabled(dev
))
1775 /* Setup PSR once */
1776 intel_edp_psr_setup(intel_dp
);
1778 /* Enable PSR on the panel */
1779 intel_edp_psr_enable_sink(intel_dp
);
1781 /* Enable PSR on the host */
1782 intel_edp_psr_enable_source(intel_dp
);
1785 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1787 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1789 if (intel_edp_psr_match_conditions(intel_dp
) &&
1790 !intel_edp_is_psr_enabled(dev
))
1791 intel_edp_psr_do_enable(intel_dp
);
1794 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1796 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1799 if (!intel_edp_is_psr_enabled(dev
))
1802 I915_WRITE(EDP_PSR_CTL(dev
),
1803 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1805 /* Wait till PSR is idle */
1806 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1807 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1808 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1811 void intel_edp_psr_update(struct drm_device
*dev
)
1813 struct intel_encoder
*encoder
;
1814 struct intel_dp
*intel_dp
= NULL
;
1816 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
)
1817 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
1818 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1820 if (!is_edp_psr(dev
))
1823 if (!intel_edp_psr_match_conditions(intel_dp
))
1824 intel_edp_psr_disable(intel_dp
);
1826 if (!intel_edp_is_psr_enabled(dev
))
1827 intel_edp_psr_do_enable(intel_dp
);
1831 static void intel_disable_dp(struct intel_encoder
*encoder
)
1833 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1834 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1835 struct drm_device
*dev
= encoder
->base
.dev
;
1837 /* Make sure the panel is off before trying to change the mode. But also
1838 * ensure that we have vdd while we switch off the panel. */
1839 intel_edp_panel_vdd_on(intel_dp
);
1840 intel_edp_backlight_off(intel_dp
);
1841 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1842 intel_edp_panel_off(intel_dp
);
1844 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1845 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1846 intel_dp_link_down(intel_dp
);
1849 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
1851 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1852 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1857 intel_dp_link_down(intel_dp
);
1858 ironlake_edp_pll_off(intel_dp
);
1861 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
1863 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1865 intel_dp_link_down(intel_dp
);
1868 static void intel_enable_dp(struct intel_encoder
*encoder
)
1870 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1871 struct drm_device
*dev
= encoder
->base
.dev
;
1872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1873 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1875 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1878 intel_edp_panel_vdd_on(intel_dp
);
1879 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1880 intel_dp_start_link_train(intel_dp
);
1881 intel_edp_panel_on(intel_dp
);
1882 edp_panel_vdd_off(intel_dp
, true);
1883 intel_dp_complete_link_train(intel_dp
);
1884 intel_dp_stop_link_train(intel_dp
);
1887 static void g4x_enable_dp(struct intel_encoder
*encoder
)
1889 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1891 intel_enable_dp(encoder
);
1892 intel_edp_backlight_on(intel_dp
);
1895 static void vlv_enable_dp(struct intel_encoder
*encoder
)
1897 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1899 intel_edp_backlight_on(intel_dp
);
1902 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
1904 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1905 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1907 intel_dp_prepare(encoder
);
1909 /* Only ilk+ has port A */
1910 if (dport
->port
== PORT_A
) {
1911 ironlake_set_pll_cpu_edp(intel_dp
);
1912 ironlake_edp_pll_on(intel_dp
);
1916 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
1918 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1919 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1920 struct drm_device
*dev
= encoder
->base
.dev
;
1921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1922 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1923 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1924 int pipe
= intel_crtc
->pipe
;
1925 struct edp_power_seq power_seq
;
1928 mutex_lock(&dev_priv
->dpio_lock
);
1930 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1937 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1938 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1939 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1941 mutex_unlock(&dev_priv
->dpio_lock
);
1943 if (is_edp(intel_dp
)) {
1944 /* init power sequencer on this pipe and port */
1945 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
1946 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
1950 intel_enable_dp(encoder
);
1952 vlv_wait_port_ready(dev_priv
, dport
);
1955 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
1957 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1958 struct drm_device
*dev
= encoder
->base
.dev
;
1959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1960 struct intel_crtc
*intel_crtc
=
1961 to_intel_crtc(encoder
->base
.crtc
);
1962 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1963 int pipe
= intel_crtc
->pipe
;
1965 intel_dp_prepare(encoder
);
1967 /* Program Tx lane resets to default */
1968 mutex_lock(&dev_priv
->dpio_lock
);
1969 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
1970 DPIO_PCS_TX_LANE2_RESET
|
1971 DPIO_PCS_TX_LANE1_RESET
);
1972 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
1973 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1974 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1975 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1976 DPIO_PCS_CLK_SOFT_RESET
);
1978 /* Fix up inter-pair skew failure */
1979 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
1980 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
1981 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
1982 mutex_unlock(&dev_priv
->dpio_lock
);
1985 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
1987 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1988 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1989 struct drm_device
*dev
= encoder
->base
.dev
;
1990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1991 struct edp_power_seq power_seq
;
1992 struct intel_crtc
*intel_crtc
=
1993 to_intel_crtc(encoder
->base
.crtc
);
1994 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1995 int pipe
= intel_crtc
->pipe
;
1998 /* Program Tx lane latency optimal setting*/
1999 mutex_lock(&dev_priv
->dpio_lock
);
2000 for (i
= 0; i
< 4; i
++) {
2001 /* Set the latency optimal bit */
2002 data
= (i
== 1) ? 0x0 : 0x6;
2003 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2004 data
<< DPIO_FRC_LATENCY_SHFIT
);
2006 /* Set the upar bit */
2007 data
= (i
== 1) ? 0x0 : 0x1;
2008 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2009 data
<< DPIO_UPAR_SHIFT
);
2012 /* Data lane stagger programming */
2013 /* FIXME: Fix up value only after power analysis */
2015 mutex_unlock(&dev_priv
->dpio_lock
);
2017 if (is_edp(intel_dp
)) {
2018 /* init power sequencer on this pipe and port */
2019 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2020 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2024 intel_enable_dp(encoder
);
2026 vlv_wait_port_ready(dev_priv
, dport
);
2030 * Native read with retry for link status and receiver capability reads for
2031 * cases where the sink may still be asleep.
2033 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2034 * supposed to retry 3 times per the spec.
2037 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2038 void *buffer
, size_t size
)
2043 for (i
= 0; i
< 3; i
++) {
2044 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2054 * Fetch AUX CH registers 0x202 - 0x207 which contain
2055 * link status information
2058 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2060 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2063 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2067 * These are source-specific values; current Intel hardware supports
2068 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2072 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2074 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2075 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2077 if (IS_VALLEYVIEW(dev
) || IS_BROADWELL(dev
))
2078 return DP_TRAIN_VOLTAGE_SWING_1200
;
2079 else if (IS_GEN7(dev
) && port
== PORT_A
)
2080 return DP_TRAIN_VOLTAGE_SWING_800
;
2081 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2082 return DP_TRAIN_VOLTAGE_SWING_1200
;
2084 return DP_TRAIN_VOLTAGE_SWING_800
;
2088 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2090 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2091 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2093 if (IS_BROADWELL(dev
)) {
2094 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2095 case DP_TRAIN_VOLTAGE_SWING_400
:
2096 case DP_TRAIN_VOLTAGE_SWING_600
:
2097 return DP_TRAIN_PRE_EMPHASIS_6
;
2098 case DP_TRAIN_VOLTAGE_SWING_800
:
2099 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2100 case DP_TRAIN_VOLTAGE_SWING_1200
:
2102 return DP_TRAIN_PRE_EMPHASIS_0
;
2104 } else if (IS_HASWELL(dev
)) {
2105 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2106 case DP_TRAIN_VOLTAGE_SWING_400
:
2107 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2108 case DP_TRAIN_VOLTAGE_SWING_600
:
2109 return DP_TRAIN_PRE_EMPHASIS_6
;
2110 case DP_TRAIN_VOLTAGE_SWING_800
:
2111 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2112 case DP_TRAIN_VOLTAGE_SWING_1200
:
2114 return DP_TRAIN_PRE_EMPHASIS_0
;
2116 } else if (IS_VALLEYVIEW(dev
)) {
2117 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2118 case DP_TRAIN_VOLTAGE_SWING_400
:
2119 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2120 case DP_TRAIN_VOLTAGE_SWING_600
:
2121 return DP_TRAIN_PRE_EMPHASIS_6
;
2122 case DP_TRAIN_VOLTAGE_SWING_800
:
2123 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2124 case DP_TRAIN_VOLTAGE_SWING_1200
:
2126 return DP_TRAIN_PRE_EMPHASIS_0
;
2128 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2129 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2130 case DP_TRAIN_VOLTAGE_SWING_400
:
2131 return DP_TRAIN_PRE_EMPHASIS_6
;
2132 case DP_TRAIN_VOLTAGE_SWING_600
:
2133 case DP_TRAIN_VOLTAGE_SWING_800
:
2134 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2136 return DP_TRAIN_PRE_EMPHASIS_0
;
2139 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2140 case DP_TRAIN_VOLTAGE_SWING_400
:
2141 return DP_TRAIN_PRE_EMPHASIS_6
;
2142 case DP_TRAIN_VOLTAGE_SWING_600
:
2143 return DP_TRAIN_PRE_EMPHASIS_6
;
2144 case DP_TRAIN_VOLTAGE_SWING_800
:
2145 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2146 case DP_TRAIN_VOLTAGE_SWING_1200
:
2148 return DP_TRAIN_PRE_EMPHASIS_0
;
2153 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2155 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2157 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2158 struct intel_crtc
*intel_crtc
=
2159 to_intel_crtc(dport
->base
.base
.crtc
);
2160 unsigned long demph_reg_value
, preemph_reg_value
,
2161 uniqtranscale_reg_value
;
2162 uint8_t train_set
= intel_dp
->train_set
[0];
2163 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2164 int pipe
= intel_crtc
->pipe
;
2166 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2167 case DP_TRAIN_PRE_EMPHASIS_0
:
2168 preemph_reg_value
= 0x0004000;
2169 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2170 case DP_TRAIN_VOLTAGE_SWING_400
:
2171 demph_reg_value
= 0x2B405555;
2172 uniqtranscale_reg_value
= 0x552AB83A;
2174 case DP_TRAIN_VOLTAGE_SWING_600
:
2175 demph_reg_value
= 0x2B404040;
2176 uniqtranscale_reg_value
= 0x5548B83A;
2178 case DP_TRAIN_VOLTAGE_SWING_800
:
2179 demph_reg_value
= 0x2B245555;
2180 uniqtranscale_reg_value
= 0x5560B83A;
2182 case DP_TRAIN_VOLTAGE_SWING_1200
:
2183 demph_reg_value
= 0x2B405555;
2184 uniqtranscale_reg_value
= 0x5598DA3A;
2190 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2191 preemph_reg_value
= 0x0002000;
2192 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2193 case DP_TRAIN_VOLTAGE_SWING_400
:
2194 demph_reg_value
= 0x2B404040;
2195 uniqtranscale_reg_value
= 0x5552B83A;
2197 case DP_TRAIN_VOLTAGE_SWING_600
:
2198 demph_reg_value
= 0x2B404848;
2199 uniqtranscale_reg_value
= 0x5580B83A;
2201 case DP_TRAIN_VOLTAGE_SWING_800
:
2202 demph_reg_value
= 0x2B404040;
2203 uniqtranscale_reg_value
= 0x55ADDA3A;
2209 case DP_TRAIN_PRE_EMPHASIS_6
:
2210 preemph_reg_value
= 0x0000000;
2211 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2212 case DP_TRAIN_VOLTAGE_SWING_400
:
2213 demph_reg_value
= 0x2B305555;
2214 uniqtranscale_reg_value
= 0x5570B83A;
2216 case DP_TRAIN_VOLTAGE_SWING_600
:
2217 demph_reg_value
= 0x2B2B4040;
2218 uniqtranscale_reg_value
= 0x55ADDA3A;
2224 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2225 preemph_reg_value
= 0x0006000;
2226 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2227 case DP_TRAIN_VOLTAGE_SWING_400
:
2228 demph_reg_value
= 0x1B405555;
2229 uniqtranscale_reg_value
= 0x55ADDA3A;
2239 mutex_lock(&dev_priv
->dpio_lock
);
2240 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2241 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2242 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2243 uniqtranscale_reg_value
);
2244 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2245 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2246 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2247 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2248 mutex_unlock(&dev_priv
->dpio_lock
);
2253 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2255 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2257 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2258 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2259 u32 deemph_reg_value
, margin_reg_value
, val
, tx_dw2
;
2260 uint8_t train_set
= intel_dp
->train_set
[0];
2261 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2262 int pipe
= intel_crtc
->pipe
;
2264 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2265 case DP_TRAIN_PRE_EMPHASIS_0
:
2266 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2267 case DP_TRAIN_VOLTAGE_SWING_400
:
2268 deemph_reg_value
= 128;
2269 margin_reg_value
= 52;
2271 case DP_TRAIN_VOLTAGE_SWING_600
:
2272 deemph_reg_value
= 128;
2273 margin_reg_value
= 77;
2275 case DP_TRAIN_VOLTAGE_SWING_800
:
2276 deemph_reg_value
= 128;
2277 margin_reg_value
= 102;
2279 case DP_TRAIN_VOLTAGE_SWING_1200
:
2280 deemph_reg_value
= 128;
2281 margin_reg_value
= 154;
2282 /* FIXME extra to set for 1200 */
2288 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2289 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2290 case DP_TRAIN_VOLTAGE_SWING_400
:
2291 deemph_reg_value
= 85;
2292 margin_reg_value
= 78;
2294 case DP_TRAIN_VOLTAGE_SWING_600
:
2295 deemph_reg_value
= 85;
2296 margin_reg_value
= 116;
2298 case DP_TRAIN_VOLTAGE_SWING_800
:
2299 deemph_reg_value
= 85;
2300 margin_reg_value
= 154;
2306 case DP_TRAIN_PRE_EMPHASIS_6
:
2307 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2308 case DP_TRAIN_VOLTAGE_SWING_400
:
2309 deemph_reg_value
= 64;
2310 margin_reg_value
= 104;
2312 case DP_TRAIN_VOLTAGE_SWING_600
:
2313 deemph_reg_value
= 64;
2314 margin_reg_value
= 154;
2320 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2321 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2322 case DP_TRAIN_VOLTAGE_SWING_400
:
2323 deemph_reg_value
= 43;
2324 margin_reg_value
= 154;
2334 mutex_lock(&dev_priv
->dpio_lock
);
2336 /* Clear calc init */
2337 vlv_dpio_write(dev_priv
, pipe
, CHV_PCS_DW10(ch
), 0);
2339 /* Program swing deemph */
2340 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_TX_DW4(ch
));
2341 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2342 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2343 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(ch
), val
);
2345 /* Program swing margin */
2346 tx_dw2
= vlv_dpio_read(dev_priv
, pipe
, VLV_TX_DW2(ch
));
2347 tx_dw2
&= ~DPIO_SWING_MARGIN_MASK
;
2348 tx_dw2
|= margin_reg_value
<< DPIO_SWING_MARGIN_SHIFT
;
2349 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(ch
), tx_dw2
);
2351 /* Disable unique transition scale */
2352 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_TX_DW3(ch
));
2353 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2354 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(ch
), val
);
2356 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
2357 == DP_TRAIN_PRE_EMPHASIS_0
) &&
2358 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
2359 == DP_TRAIN_VOLTAGE_SWING_1200
)) {
2362 * The document said it needs to set bit 27 for ch0 and bit 26
2363 * for ch1. Might be a typo in the doc.
2364 * For now, for this unique transition scale selection, set bit
2365 * 27 for ch0 and ch1.
2367 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_TX_DW3(ch
));
2368 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2369 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(ch
), val
);
2371 tx_dw2
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2372 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(ch
), tx_dw2
);
2375 /* Start swing calculation */
2376 vlv_dpio_write(dev_priv
, pipe
, CHV_PCS_DW10(ch
),
2377 (DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
));
2380 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
2381 val
|= DPIO_LRC_BYPASS
;
2382 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
2384 mutex_unlock(&dev_priv
->dpio_lock
);
2390 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2391 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2396 uint8_t voltage_max
;
2397 uint8_t preemph_max
;
2399 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2400 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2401 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2409 voltage_max
= intel_dp_voltage_max(intel_dp
);
2410 if (v
>= voltage_max
)
2411 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2413 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2414 if (p
>= preemph_max
)
2415 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2417 for (lane
= 0; lane
< 4; lane
++)
2418 intel_dp
->train_set
[lane
] = v
| p
;
2422 intel_gen4_signal_levels(uint8_t train_set
)
2424 uint32_t signal_levels
= 0;
2426 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2427 case DP_TRAIN_VOLTAGE_SWING_400
:
2429 signal_levels
|= DP_VOLTAGE_0_4
;
2431 case DP_TRAIN_VOLTAGE_SWING_600
:
2432 signal_levels
|= DP_VOLTAGE_0_6
;
2434 case DP_TRAIN_VOLTAGE_SWING_800
:
2435 signal_levels
|= DP_VOLTAGE_0_8
;
2437 case DP_TRAIN_VOLTAGE_SWING_1200
:
2438 signal_levels
|= DP_VOLTAGE_1_2
;
2441 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2442 case DP_TRAIN_PRE_EMPHASIS_0
:
2444 signal_levels
|= DP_PRE_EMPHASIS_0
;
2446 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2447 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2449 case DP_TRAIN_PRE_EMPHASIS_6
:
2450 signal_levels
|= DP_PRE_EMPHASIS_6
;
2452 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2453 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2456 return signal_levels
;
2459 /* Gen6's DP voltage swing and pre-emphasis control */
2461 intel_gen6_edp_signal_levels(uint8_t train_set
)
2463 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2464 DP_TRAIN_PRE_EMPHASIS_MASK
);
2465 switch (signal_levels
) {
2466 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2467 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2468 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2469 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2470 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2471 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2472 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2473 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2474 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2475 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2476 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2477 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2478 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2479 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2481 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2482 "0x%x\n", signal_levels
);
2483 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2487 /* Gen7's DP voltage swing and pre-emphasis control */
2489 intel_gen7_edp_signal_levels(uint8_t train_set
)
2491 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2492 DP_TRAIN_PRE_EMPHASIS_MASK
);
2493 switch (signal_levels
) {
2494 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2495 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2496 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2497 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2498 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2499 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2501 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2502 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2503 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2504 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2506 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2507 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2508 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2509 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2512 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2513 "0x%x\n", signal_levels
);
2514 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2518 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2520 intel_hsw_signal_levels(uint8_t train_set
)
2522 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2523 DP_TRAIN_PRE_EMPHASIS_MASK
);
2524 switch (signal_levels
) {
2525 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2526 return DDI_BUF_EMP_400MV_0DB_HSW
;
2527 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2528 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2529 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2530 return DDI_BUF_EMP_400MV_6DB_HSW
;
2531 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2532 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2534 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2535 return DDI_BUF_EMP_600MV_0DB_HSW
;
2536 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2537 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2538 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2539 return DDI_BUF_EMP_600MV_6DB_HSW
;
2541 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2542 return DDI_BUF_EMP_800MV_0DB_HSW
;
2543 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2544 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2546 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2547 "0x%x\n", signal_levels
);
2548 return DDI_BUF_EMP_400MV_0DB_HSW
;
2553 intel_bdw_signal_levels(uint8_t train_set
)
2555 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2556 DP_TRAIN_PRE_EMPHASIS_MASK
);
2557 switch (signal_levels
) {
2558 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2559 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2560 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2561 return DDI_BUF_EMP_400MV_3_5DB_BDW
; /* Sel1 */
2562 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2563 return DDI_BUF_EMP_400MV_6DB_BDW
; /* Sel2 */
2565 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2566 return DDI_BUF_EMP_600MV_0DB_BDW
; /* Sel3 */
2567 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2568 return DDI_BUF_EMP_600MV_3_5DB_BDW
; /* Sel4 */
2569 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2570 return DDI_BUF_EMP_600MV_6DB_BDW
; /* Sel5 */
2572 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2573 return DDI_BUF_EMP_800MV_0DB_BDW
; /* Sel6 */
2574 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2575 return DDI_BUF_EMP_800MV_3_5DB_BDW
; /* Sel7 */
2577 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2578 return DDI_BUF_EMP_1200MV_0DB_BDW
; /* Sel8 */
2581 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2582 "0x%x\n", signal_levels
);
2583 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2587 /* Properly updates "DP" with the correct signal levels. */
2589 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2591 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2592 enum port port
= intel_dig_port
->port
;
2593 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2594 uint32_t signal_levels
, mask
;
2595 uint8_t train_set
= intel_dp
->train_set
[0];
2597 if (IS_BROADWELL(dev
)) {
2598 signal_levels
= intel_bdw_signal_levels(train_set
);
2599 mask
= DDI_BUF_EMP_MASK
;
2600 } else if (IS_HASWELL(dev
)) {
2601 signal_levels
= intel_hsw_signal_levels(train_set
);
2602 mask
= DDI_BUF_EMP_MASK
;
2603 } else if (IS_CHERRYVIEW(dev
)) {
2604 signal_levels
= intel_chv_signal_levels(intel_dp
);
2606 } else if (IS_VALLEYVIEW(dev
)) {
2607 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2609 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2610 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2611 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2612 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2613 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2614 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2616 signal_levels
= intel_gen4_signal_levels(train_set
);
2617 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2620 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2622 *DP
= (*DP
& ~mask
) | signal_levels
;
2626 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2628 uint8_t dp_train_pat
)
2630 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2631 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2633 enum port port
= intel_dig_port
->port
;
2634 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2638 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2640 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2641 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2643 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2645 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2646 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2647 case DP_TRAINING_PATTERN_DISABLE
:
2648 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2651 case DP_TRAINING_PATTERN_1
:
2652 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2654 case DP_TRAINING_PATTERN_2
:
2655 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2657 case DP_TRAINING_PATTERN_3
:
2658 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2661 I915_WRITE(DP_TP_CTL(port
), temp
);
2663 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2664 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2666 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2667 case DP_TRAINING_PATTERN_DISABLE
:
2668 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2670 case DP_TRAINING_PATTERN_1
:
2671 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2673 case DP_TRAINING_PATTERN_2
:
2674 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2676 case DP_TRAINING_PATTERN_3
:
2677 DRM_ERROR("DP training pattern 3 not supported\n");
2678 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2683 *DP
&= ~DP_LINK_TRAIN_MASK
;
2685 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2686 case DP_TRAINING_PATTERN_DISABLE
:
2687 *DP
|= DP_LINK_TRAIN_OFF
;
2689 case DP_TRAINING_PATTERN_1
:
2690 *DP
|= DP_LINK_TRAIN_PAT_1
;
2692 case DP_TRAINING_PATTERN_2
:
2693 *DP
|= DP_LINK_TRAIN_PAT_2
;
2695 case DP_TRAINING_PATTERN_3
:
2696 DRM_ERROR("DP training pattern 3 not supported\n");
2697 *DP
|= DP_LINK_TRAIN_PAT_2
;
2702 I915_WRITE(intel_dp
->output_reg
, *DP
);
2703 POSTING_READ(intel_dp
->output_reg
);
2705 buf
[0] = dp_train_pat
;
2706 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2707 DP_TRAINING_PATTERN_DISABLE
) {
2708 /* don't write DP_TRAINING_LANEx_SET on disable */
2711 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2712 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
2713 len
= intel_dp
->lane_count
+ 1;
2716 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
2723 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2724 uint8_t dp_train_pat
)
2726 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
2727 intel_dp_set_signal_levels(intel_dp
, DP
);
2728 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
2732 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2733 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2735 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2736 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2740 intel_get_adjust_train(intel_dp
, link_status
);
2741 intel_dp_set_signal_levels(intel_dp
, DP
);
2743 I915_WRITE(intel_dp
->output_reg
, *DP
);
2744 POSTING_READ(intel_dp
->output_reg
);
2746 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
2747 intel_dp
->train_set
, intel_dp
->lane_count
);
2749 return ret
== intel_dp
->lane_count
;
2752 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
2754 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2755 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2757 enum port port
= intel_dig_port
->port
;
2763 val
= I915_READ(DP_TP_CTL(port
));
2764 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2765 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2766 I915_WRITE(DP_TP_CTL(port
), val
);
2769 * On PORT_A we can have only eDP in SST mode. There the only reason
2770 * we need to set idle transmission mode is to work around a HW issue
2771 * where we enable the pipe while not in idle link-training mode.
2772 * In this case there is requirement to wait for a minimum number of
2773 * idle patterns to be sent.
2778 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2780 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2783 /* Enable corresponding port and start training pattern 1 */
2785 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2787 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2788 struct drm_device
*dev
= encoder
->dev
;
2791 int voltage_tries
, loop_tries
;
2792 uint32_t DP
= intel_dp
->DP
;
2793 uint8_t link_config
[2];
2796 intel_ddi_prepare_link_retrain(encoder
);
2798 /* Write the link configuration data */
2799 link_config
[0] = intel_dp
->link_bw
;
2800 link_config
[1] = intel_dp
->lane_count
;
2801 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2802 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
2803 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
2806 link_config
[1] = DP_SET_ANSI_8B10B
;
2807 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
2811 /* clock recovery */
2812 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
2813 DP_TRAINING_PATTERN_1
|
2814 DP_LINK_SCRAMBLING_DISABLE
)) {
2815 DRM_ERROR("failed to enable link training\n");
2823 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2825 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2826 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2827 DRM_ERROR("failed to get link status\n");
2831 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2832 DRM_DEBUG_KMS("clock recovery OK\n");
2836 /* Check to see if we've tried the max voltage */
2837 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2838 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2840 if (i
== intel_dp
->lane_count
) {
2842 if (loop_tries
== 5) {
2843 DRM_ERROR("too many full retries, give up\n");
2846 intel_dp_reset_link_train(intel_dp
, &DP
,
2847 DP_TRAINING_PATTERN_1
|
2848 DP_LINK_SCRAMBLING_DISABLE
);
2853 /* Check to see if we've tried the same voltage 5 times */
2854 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
2856 if (voltage_tries
== 5) {
2857 DRM_ERROR("too many voltage retries, give up\n");
2862 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
2864 /* Update training set as requested by target */
2865 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2866 DRM_ERROR("failed to update link training\n");
2875 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
2877 bool channel_eq
= false;
2878 int tries
, cr_tries
;
2879 uint32_t DP
= intel_dp
->DP
;
2880 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
2882 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2883 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
2884 training_pattern
= DP_TRAINING_PATTERN_3
;
2886 /* channel equalization */
2887 if (!intel_dp_set_link_train(intel_dp
, &DP
,
2889 DP_LINK_SCRAMBLING_DISABLE
)) {
2890 DRM_ERROR("failed to start channel equalization\n");
2898 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2901 DRM_ERROR("failed to train DP, aborting\n");
2905 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
2906 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2907 DRM_ERROR("failed to get link status\n");
2911 /* Make sure clock is still ok */
2912 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2913 intel_dp_start_link_train(intel_dp
);
2914 intel_dp_set_link_train(intel_dp
, &DP
,
2916 DP_LINK_SCRAMBLING_DISABLE
);
2921 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2926 /* Try 5 times, then try clock recovery if that fails */
2928 intel_dp_link_down(intel_dp
);
2929 intel_dp_start_link_train(intel_dp
);
2930 intel_dp_set_link_train(intel_dp
, &DP
,
2932 DP_LINK_SCRAMBLING_DISABLE
);
2938 /* Update training set as requested by target */
2939 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2940 DRM_ERROR("failed to update link training\n");
2946 intel_dp_set_idle_link_train(intel_dp
);
2951 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2955 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
2957 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2958 DP_TRAINING_PATTERN_DISABLE
);
2962 intel_dp_link_down(struct intel_dp
*intel_dp
)
2964 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2965 enum port port
= intel_dig_port
->port
;
2966 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2968 struct intel_crtc
*intel_crtc
=
2969 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2970 uint32_t DP
= intel_dp
->DP
;
2973 * DDI code has a strict mode set sequence and we should try to respect
2974 * it, otherwise we might hang the machine in many different ways. So we
2975 * really should be disabling the port only on a complete crtc_disable
2976 * sequence. This function is just called under two conditions on DDI
2978 * - Link train failed while doing crtc_enable, and on this case we
2979 * really should respect the mode set sequence and wait for a
2981 * - Someone turned the monitor off and intel_dp_check_link_status
2982 * called us. We don't need to disable the whole port on this case, so
2983 * when someone turns the monitor on again,
2984 * intel_ddi_prepare_link_retrain will take care of redoing the link
2990 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2993 DRM_DEBUG_KMS("\n");
2995 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2996 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2997 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2999 DP
&= ~DP_LINK_TRAIN_MASK
;
3000 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3002 POSTING_READ(intel_dp
->output_reg
);
3004 if (HAS_PCH_IBX(dev
) &&
3005 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3006 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3008 /* Hardware workaround: leaving our transcoder select
3009 * set to transcoder B while it's off will prevent the
3010 * corresponding HDMI output on transcoder A.
3012 * Combine this with another hardware workaround:
3013 * transcoder select bit can only be cleared while the
3016 DP
&= ~DP_PIPEB_SELECT
;
3017 I915_WRITE(intel_dp
->output_reg
, DP
);
3019 /* Changes to enable or select take place the vblank
3020 * after being written.
3022 if (WARN_ON(crtc
== NULL
)) {
3023 /* We should never try to disable a port without a crtc
3024 * attached. For paranoia keep the code around for a
3026 POSTING_READ(intel_dp
->output_reg
);
3029 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3032 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3033 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3034 POSTING_READ(intel_dp
->output_reg
);
3035 msleep(intel_dp
->panel_power_down_delay
);
3039 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3041 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3042 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3045 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
3047 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3048 sizeof(intel_dp
->dpcd
)) < 0)
3049 return false; /* aux transfer failed */
3051 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
3052 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
3053 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
3055 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3056 return false; /* DPCD not present */
3058 /* Check if the panel supports PSR */
3059 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3060 if (is_edp(intel_dp
)) {
3061 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3063 sizeof(intel_dp
->psr_dpcd
));
3064 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3065 dev_priv
->psr
.sink_support
= true;
3066 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3070 /* Training Pattern 3 support */
3071 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3072 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3073 intel_dp
->use_tps3
= true;
3074 DRM_DEBUG_KMS("Displayport TPS3 supported");
3076 intel_dp
->use_tps3
= false;
3078 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3079 DP_DWN_STRM_PORT_PRESENT
))
3080 return true; /* native DP sink */
3082 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3083 return true; /* no per-port downstream info */
3085 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3086 intel_dp
->downstream_ports
,
3087 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3088 return false; /* downstream port status fetch failed */
3094 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3098 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3101 intel_edp_panel_vdd_on(intel_dp
);
3103 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3104 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3105 buf
[0], buf
[1], buf
[2]);
3107 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3108 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3109 buf
[0], buf
[1], buf
[2]);
3111 edp_panel_vdd_off(intel_dp
, false);
3114 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3117 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3118 struct intel_crtc
*intel_crtc
=
3119 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3122 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3125 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3128 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3129 DP_TEST_SINK_START
) < 0)
3132 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3133 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3134 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3136 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3139 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3144 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3146 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3147 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3148 sink_irq_vector
, 1) == 1;
3152 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3154 /* NAK by default */
3155 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3159 * According to DP spec
3162 * 2. Configure link according to Receiver Capabilities
3163 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3164 * 4. Check link status on receipt of hot-plug interrupt
3168 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3170 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3172 u8 link_status
[DP_LINK_STATUS_SIZE
];
3174 if (!intel_encoder
->connectors_active
)
3177 if (WARN_ON(!intel_encoder
->base
.crtc
))
3180 /* Try to read receiver status if the link appears to be up */
3181 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3185 /* Now read the DPCD to see if it's actually running */
3186 if (!intel_dp_get_dpcd(intel_dp
)) {
3190 /* Try to read the source of the interrupt */
3191 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3192 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3193 /* Clear interrupt source */
3194 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3195 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3198 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3199 intel_dp_handle_test_request(intel_dp
);
3200 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3201 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3204 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3205 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3206 drm_get_encoder_name(&intel_encoder
->base
));
3207 intel_dp_start_link_train(intel_dp
);
3208 intel_dp_complete_link_train(intel_dp
);
3209 intel_dp_stop_link_train(intel_dp
);
3213 /* XXX this is probably wrong for multiple downstream ports */
3214 static enum drm_connector_status
3215 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3217 uint8_t *dpcd
= intel_dp
->dpcd
;
3220 if (!intel_dp_get_dpcd(intel_dp
))
3221 return connector_status_disconnected
;
3223 /* if there's no downstream port, we're done */
3224 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3225 return connector_status_connected
;
3227 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3228 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3229 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3232 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3234 return connector_status_unknown
;
3236 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3237 : connector_status_disconnected
;
3240 /* If no HPD, poke DDC gently */
3241 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3242 return connector_status_connected
;
3244 /* Well we tried, say unknown for unreliable port types */
3245 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3246 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3247 if (type
== DP_DS_PORT_TYPE_VGA
||
3248 type
== DP_DS_PORT_TYPE_NON_EDID
)
3249 return connector_status_unknown
;
3251 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3252 DP_DWN_STRM_PORT_TYPE_MASK
;
3253 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3254 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3255 return connector_status_unknown
;
3258 /* Anything else is out of spec, warn and ignore */
3259 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3260 return connector_status_disconnected
;
3263 static enum drm_connector_status
3264 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3266 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3268 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3269 enum drm_connector_status status
;
3271 /* Can't disconnect eDP, but you can close the lid... */
3272 if (is_edp(intel_dp
)) {
3273 status
= intel_panel_detect(dev
);
3274 if (status
== connector_status_unknown
)
3275 status
= connector_status_connected
;
3279 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3280 return connector_status_disconnected
;
3282 return intel_dp_detect_dpcd(intel_dp
);
3285 static enum drm_connector_status
3286 g4x_dp_detect(struct intel_dp
*intel_dp
)
3288 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3290 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3293 /* Can't disconnect eDP, but you can close the lid... */
3294 if (is_edp(intel_dp
)) {
3295 enum drm_connector_status status
;
3297 status
= intel_panel_detect(dev
);
3298 if (status
== connector_status_unknown
)
3299 status
= connector_status_connected
;
3303 if (IS_VALLEYVIEW(dev
)) {
3304 switch (intel_dig_port
->port
) {
3306 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3309 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3312 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3315 return connector_status_unknown
;
3318 switch (intel_dig_port
->port
) {
3320 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3323 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3326 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3329 return connector_status_unknown
;
3333 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3334 return connector_status_disconnected
;
3336 return intel_dp_detect_dpcd(intel_dp
);
3339 static struct edid
*
3340 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3342 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3344 /* use cached edid if we have one */
3345 if (intel_connector
->edid
) {
3347 if (IS_ERR(intel_connector
->edid
))
3350 return drm_edid_duplicate(intel_connector
->edid
);
3353 return drm_get_edid(connector
, adapter
);
3357 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3359 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3361 /* use cached edid if we have one */
3362 if (intel_connector
->edid
) {
3364 if (IS_ERR(intel_connector
->edid
))
3367 return intel_connector_update_modes(connector
,
3368 intel_connector
->edid
);
3371 return intel_ddc_get_modes(connector
, adapter
);
3374 static enum drm_connector_status
3375 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3377 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3378 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3379 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3380 struct drm_device
*dev
= connector
->dev
;
3381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3382 enum drm_connector_status status
;
3383 enum intel_display_power_domain power_domain
;
3384 struct edid
*edid
= NULL
;
3386 intel_runtime_pm_get(dev_priv
);
3388 power_domain
= intel_display_port_power_domain(intel_encoder
);
3389 intel_display_power_get(dev_priv
, power_domain
);
3391 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3392 connector
->base
.id
, drm_get_connector_name(connector
));
3394 intel_dp
->has_audio
= false;
3396 if (HAS_PCH_SPLIT(dev
))
3397 status
= ironlake_dp_detect(intel_dp
);
3399 status
= g4x_dp_detect(intel_dp
);
3401 if (status
!= connector_status_connected
)
3404 intel_dp_probe_oui(intel_dp
);
3406 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3407 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3409 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3411 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3416 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3417 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3418 status
= connector_status_connected
;
3421 intel_display_power_put(dev_priv
, power_domain
);
3423 intel_runtime_pm_put(dev_priv
);
3428 static int intel_dp_get_modes(struct drm_connector
*connector
)
3430 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3431 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3432 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3433 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3434 struct drm_device
*dev
= connector
->dev
;
3435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3436 enum intel_display_power_domain power_domain
;
3439 /* We should parse the EDID data and find out if it has an audio sink
3442 power_domain
= intel_display_port_power_domain(intel_encoder
);
3443 intel_display_power_get(dev_priv
, power_domain
);
3445 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3446 intel_display_power_put(dev_priv
, power_domain
);
3450 /* if eDP has no EDID, fall back to fixed mode */
3451 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3452 struct drm_display_mode
*mode
;
3453 mode
= drm_mode_duplicate(dev
,
3454 intel_connector
->panel
.fixed_mode
);
3456 drm_mode_probed_add(connector
, mode
);
3464 intel_dp_detect_audio(struct drm_connector
*connector
)
3466 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3467 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3468 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3469 struct drm_device
*dev
= connector
->dev
;
3470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3471 enum intel_display_power_domain power_domain
;
3473 bool has_audio
= false;
3475 power_domain
= intel_display_port_power_domain(intel_encoder
);
3476 intel_display_power_get(dev_priv
, power_domain
);
3478 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3480 has_audio
= drm_detect_monitor_audio(edid
);
3484 intel_display_power_put(dev_priv
, power_domain
);
3490 intel_dp_set_property(struct drm_connector
*connector
,
3491 struct drm_property
*property
,
3494 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3495 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3496 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3497 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3500 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3504 if (property
== dev_priv
->force_audio_property
) {
3508 if (i
== intel_dp
->force_audio
)
3511 intel_dp
->force_audio
= i
;
3513 if (i
== HDMI_AUDIO_AUTO
)
3514 has_audio
= intel_dp_detect_audio(connector
);
3516 has_audio
= (i
== HDMI_AUDIO_ON
);
3518 if (has_audio
== intel_dp
->has_audio
)
3521 intel_dp
->has_audio
= has_audio
;
3525 if (property
== dev_priv
->broadcast_rgb_property
) {
3526 bool old_auto
= intel_dp
->color_range_auto
;
3527 uint32_t old_range
= intel_dp
->color_range
;
3530 case INTEL_BROADCAST_RGB_AUTO
:
3531 intel_dp
->color_range_auto
= true;
3533 case INTEL_BROADCAST_RGB_FULL
:
3534 intel_dp
->color_range_auto
= false;
3535 intel_dp
->color_range
= 0;
3537 case INTEL_BROADCAST_RGB_LIMITED
:
3538 intel_dp
->color_range_auto
= false;
3539 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3545 if (old_auto
== intel_dp
->color_range_auto
&&
3546 old_range
== intel_dp
->color_range
)
3552 if (is_edp(intel_dp
) &&
3553 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3554 if (val
== DRM_MODE_SCALE_NONE
) {
3555 DRM_DEBUG_KMS("no scaling not supported\n");
3559 if (intel_connector
->panel
.fitting_mode
== val
) {
3560 /* the eDP scaling property is not changed */
3563 intel_connector
->panel
.fitting_mode
= val
;
3571 if (intel_encoder
->base
.crtc
)
3572 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3578 intel_dp_connector_destroy(struct drm_connector
*connector
)
3580 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3582 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3583 kfree(intel_connector
->edid
);
3585 /* Can't call is_edp() since the encoder may have been destroyed
3587 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3588 intel_panel_fini(&intel_connector
->panel
);
3590 drm_connector_cleanup(connector
);
3594 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3596 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3597 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3598 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3600 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
3601 drm_encoder_cleanup(encoder
);
3602 if (is_edp(intel_dp
)) {
3603 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3604 mutex_lock(&dev
->mode_config
.mutex
);
3605 edp_panel_vdd_off_sync(intel_dp
);
3606 mutex_unlock(&dev
->mode_config
.mutex
);
3608 kfree(intel_dig_port
);
3611 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
3612 .dpms
= intel_connector_dpms
,
3613 .detect
= intel_dp_detect
,
3614 .fill_modes
= drm_helper_probe_single_connector_modes
,
3615 .set_property
= intel_dp_set_property
,
3616 .destroy
= intel_dp_connector_destroy
,
3619 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
3620 .get_modes
= intel_dp_get_modes
,
3621 .mode_valid
= intel_dp_mode_valid
,
3622 .best_encoder
= intel_best_encoder
,
3625 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
3626 .destroy
= intel_dp_encoder_destroy
,
3630 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
3632 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3634 intel_dp_check_link_status(intel_dp
);
3637 /* Return which DP Port should be selected for Transcoder DP control */
3639 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
3641 struct drm_device
*dev
= crtc
->dev
;
3642 struct intel_encoder
*intel_encoder
;
3643 struct intel_dp
*intel_dp
;
3645 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3646 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3648 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
3649 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
3650 return intel_dp
->output_reg
;
3656 /* check the VBT to see whether the eDP is on DP-D port */
3657 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
3659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3660 union child_device_config
*p_child
;
3662 static const short port_mapping
[] = {
3663 [PORT_B
] = PORT_IDPB
,
3664 [PORT_C
] = PORT_IDPC
,
3665 [PORT_D
] = PORT_IDPD
,
3671 if (!dev_priv
->vbt
.child_dev_num
)
3674 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
3675 p_child
= dev_priv
->vbt
.child_dev
+ i
;
3677 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
3678 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
3679 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
3686 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
3688 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3690 intel_attach_force_audio_property(connector
);
3691 intel_attach_broadcast_rgb_property(connector
);
3692 intel_dp
->color_range_auto
= true;
3694 if (is_edp(intel_dp
)) {
3695 drm_mode_create_scaling_mode_property(connector
->dev
);
3696 drm_object_attach_property(
3698 connector
->dev
->mode_config
.scaling_mode_property
,
3699 DRM_MODE_SCALE_ASPECT
);
3700 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
3704 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
3706 intel_dp
->last_power_cycle
= jiffies
;
3707 intel_dp
->last_power_on
= jiffies
;
3708 intel_dp
->last_backlight_off
= jiffies
;
3712 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
3713 struct intel_dp
*intel_dp
,
3714 struct edp_power_seq
*out
)
3716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3717 struct edp_power_seq cur
, vbt
, spec
, final
;
3718 u32 pp_on
, pp_off
, pp_div
, pp
;
3719 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
3721 if (HAS_PCH_SPLIT(dev
)) {
3722 pp_ctrl_reg
= PCH_PP_CONTROL
;
3723 pp_on_reg
= PCH_PP_ON_DELAYS
;
3724 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3725 pp_div_reg
= PCH_PP_DIVISOR
;
3727 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3729 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
3730 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3731 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3732 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3735 /* Workaround: Need to write PP_CONTROL with the unlock key as
3736 * the very first thing. */
3737 pp
= ironlake_get_pp_control(intel_dp
);
3738 I915_WRITE(pp_ctrl_reg
, pp
);
3740 pp_on
= I915_READ(pp_on_reg
);
3741 pp_off
= I915_READ(pp_off_reg
);
3742 pp_div
= I915_READ(pp_div_reg
);
3744 /* Pull timing values out of registers */
3745 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
3746 PANEL_POWER_UP_DELAY_SHIFT
;
3748 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
3749 PANEL_LIGHT_ON_DELAY_SHIFT
;
3751 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
3752 PANEL_LIGHT_OFF_DELAY_SHIFT
;
3754 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
3755 PANEL_POWER_DOWN_DELAY_SHIFT
;
3757 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
3758 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
3760 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3761 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
3763 vbt
= dev_priv
->vbt
.edp_pps
;
3765 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3766 * our hw here, which are all in 100usec. */
3767 spec
.t1_t3
= 210 * 10;
3768 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
3769 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
3770 spec
.t10
= 500 * 10;
3771 /* This one is special and actually in units of 100ms, but zero
3772 * based in the hw (so we need to add 100 ms). But the sw vbt
3773 * table multiplies it with 1000 to make it in units of 100usec,
3775 spec
.t11_t12
= (510 + 100) * 10;
3777 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3778 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
3780 /* Use the max of the register settings and vbt. If both are
3781 * unset, fall back to the spec limits. */
3782 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3784 max(cur.field, vbt.field))
3785 assign_final(t1_t3
);
3789 assign_final(t11_t12
);
3792 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3793 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
3794 intel_dp
->backlight_on_delay
= get_delay(t8
);
3795 intel_dp
->backlight_off_delay
= get_delay(t9
);
3796 intel_dp
->panel_power_down_delay
= get_delay(t10
);
3797 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
3800 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3801 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
3802 intel_dp
->panel_power_cycle_delay
);
3804 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3805 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
3812 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
3813 struct intel_dp
*intel_dp
,
3814 struct edp_power_seq
*seq
)
3816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3817 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
3818 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
3819 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
3821 if (HAS_PCH_SPLIT(dev
)) {
3822 pp_on_reg
= PCH_PP_ON_DELAYS
;
3823 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3824 pp_div_reg
= PCH_PP_DIVISOR
;
3826 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3828 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3829 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3830 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3834 * And finally store the new values in the power sequencer. The
3835 * backlight delays are set to 1 because we do manual waits on them. For
3836 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3837 * we'll end up waiting for the backlight off delay twice: once when we
3838 * do the manual sleep, and once when we disable the panel and wait for
3839 * the PP_STATUS bit to become zero.
3841 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
3842 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
3843 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
3844 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
3845 /* Compute the divisor for the pp clock, simply match the Bspec
3847 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
3848 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
3849 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
3851 /* Haswell doesn't have any port selection bits for the panel
3852 * power sequencer any more. */
3853 if (IS_VALLEYVIEW(dev
)) {
3854 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
3855 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
3857 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
3858 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
3859 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
3860 port_sel
= PANEL_PORT_SELECT_DPA
;
3862 port_sel
= PANEL_PORT_SELECT_DPD
;
3867 I915_WRITE(pp_on_reg
, pp_on
);
3868 I915_WRITE(pp_off_reg
, pp_off
);
3869 I915_WRITE(pp_div_reg
, pp_div
);
3871 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3872 I915_READ(pp_on_reg
),
3873 I915_READ(pp_off_reg
),
3874 I915_READ(pp_div_reg
));
3877 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
3879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3880 struct intel_encoder
*encoder
;
3881 struct intel_dp
*intel_dp
= NULL
;
3882 struct intel_crtc_config
*config
= NULL
;
3883 struct intel_crtc
*intel_crtc
= NULL
;
3884 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
3886 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
3888 if (refresh_rate
<= 0) {
3889 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3893 if (intel_connector
== NULL
) {
3894 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3898 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
3899 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3903 encoder
= intel_attached_encoder(&intel_connector
->base
);
3904 intel_dp
= enc_to_intel_dp(&encoder
->base
);
3905 intel_crtc
= encoder
->new_crtc
;
3908 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3912 config
= &intel_crtc
->config
;
3914 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
3915 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3919 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
3920 index
= DRRS_LOW_RR
;
3922 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
3924 "DRRS requested for previously set RR...ignoring\n");
3928 if (!intel_crtc
->active
) {
3929 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3933 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
3934 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
3935 val
= I915_READ(reg
);
3936 if (index
> DRRS_HIGH_RR
) {
3937 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
3938 intel_dp_set_m2_n2(intel_crtc
, &config
->dp_m2_n2
);
3940 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
3942 I915_WRITE(reg
, val
);
3946 * mutex taken to ensure that there is no race between differnt
3947 * drrs calls trying to update refresh rate. This scenario may occur
3948 * in future when idleness detection based DRRS in kernel and
3949 * possible calls from user space to set differnt RR are made.
3952 mutex_lock(&intel_dp
->drrs_state
.mutex
);
3954 intel_dp
->drrs_state
.refresh_rate_type
= index
;
3956 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
3958 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
3961 static struct drm_display_mode
*
3962 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
3963 struct intel_connector
*intel_connector
,
3964 struct drm_display_mode
*fixed_mode
)
3966 struct drm_connector
*connector
= &intel_connector
->base
;
3967 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3968 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3970 struct drm_display_mode
*downclock_mode
= NULL
;
3972 if (INTEL_INFO(dev
)->gen
<= 6) {
3973 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3977 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
3978 DRM_INFO("VBT doesn't support DRRS\n");
3982 downclock_mode
= intel_find_panel_downclock
3983 (dev
, fixed_mode
, connector
);
3985 if (!downclock_mode
) {
3986 DRM_INFO("DRRS not supported\n");
3990 dev_priv
->drrs
.connector
= intel_connector
;
3992 mutex_init(&intel_dp
->drrs_state
.mutex
);
3994 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
3996 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
3997 DRM_INFO("seamless DRRS supported for eDP panel.\n");
3998 return downclock_mode
;
4001 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4002 struct intel_connector
*intel_connector
,
4003 struct edp_power_seq
*power_seq
)
4005 struct drm_connector
*connector
= &intel_connector
->base
;
4006 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4007 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4008 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4010 struct drm_display_mode
*fixed_mode
= NULL
;
4011 struct drm_display_mode
*downclock_mode
= NULL
;
4013 struct drm_display_mode
*scan
;
4016 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4018 if (!is_edp(intel_dp
))
4021 /* The VDD bit needs a power domain reference, so if the bit is already
4022 * enabled when we boot, grab this reference. */
4023 if (edp_have_panel_vdd(intel_dp
)) {
4024 enum intel_display_power_domain power_domain
;
4025 power_domain
= intel_display_port_power_domain(intel_encoder
);
4026 intel_display_power_get(dev_priv
, power_domain
);
4029 /* Cache DPCD and EDID for edp. */
4030 intel_edp_panel_vdd_on(intel_dp
);
4031 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4032 edp_panel_vdd_off(intel_dp
, false);
4035 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4036 dev_priv
->no_aux_handshake
=
4037 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4038 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4040 /* if this fails, presume the device is a ghost */
4041 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4045 /* We now know it's not a ghost, init power sequence regs. */
4046 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4048 mutex_lock(&dev
->mode_config
.mutex
);
4049 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4051 if (drm_add_edid_modes(connector
, edid
)) {
4052 drm_mode_connector_update_edid_property(connector
,
4054 drm_edid_to_eld(connector
, edid
);
4057 edid
= ERR_PTR(-EINVAL
);
4060 edid
= ERR_PTR(-ENOENT
);
4062 intel_connector
->edid
= edid
;
4064 /* prefer fixed mode from EDID if available */
4065 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4066 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4067 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4068 downclock_mode
= intel_dp_drrs_init(
4070 intel_connector
, fixed_mode
);
4075 /* fallback to VBT if available for eDP */
4076 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4077 fixed_mode
= drm_mode_duplicate(dev
,
4078 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4080 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4082 mutex_unlock(&dev
->mode_config
.mutex
);
4084 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4085 intel_panel_setup_backlight(connector
);
4091 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4092 struct intel_connector
*intel_connector
)
4094 struct drm_connector
*connector
= &intel_connector
->base
;
4095 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4096 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4097 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4099 enum port port
= intel_dig_port
->port
;
4100 struct edp_power_seq power_seq
= { 0 };
4103 /* intel_dp vfuncs */
4104 if (IS_VALLEYVIEW(dev
))
4105 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
4106 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4107 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
4108 else if (HAS_PCH_SPLIT(dev
))
4109 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
4111 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
4113 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
4115 /* Preserve the current hw state. */
4116 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4117 intel_dp
->attached_connector
= intel_connector
;
4119 if (intel_dp_is_edp(dev
, port
))
4120 type
= DRM_MODE_CONNECTOR_eDP
;
4122 type
= DRM_MODE_CONNECTOR_DisplayPort
;
4125 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4126 * for DP the encoder type can be set by the caller to
4127 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4129 if (type
== DRM_MODE_CONNECTOR_eDP
)
4130 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
4132 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4133 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
4136 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
4137 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
4139 connector
->interlace_allowed
= true;
4140 connector
->doublescan_allowed
= 0;
4142 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
4143 edp_panel_vdd_work
);
4145 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
4146 drm_sysfs_connector_add(connector
);
4149 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
4151 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
4152 intel_connector
->unregister
= intel_dp_connector_unregister
;
4154 /* Set up the hotplug pin. */
4157 intel_encoder
->hpd_pin
= HPD_PORT_A
;
4160 intel_encoder
->hpd_pin
= HPD_PORT_B
;
4163 intel_encoder
->hpd_pin
= HPD_PORT_C
;
4166 intel_encoder
->hpd_pin
= HPD_PORT_D
;
4172 if (is_edp(intel_dp
)) {
4173 intel_dp_init_panel_power_timestamps(intel_dp
);
4174 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
4177 intel_dp_aux_init(intel_dp
, intel_connector
);
4179 intel_dp
->psr_setup_done
= false;
4181 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
4182 drm_dp_aux_unregister_i2c_bus(&intel_dp
->aux
);
4183 if (is_edp(intel_dp
)) {
4184 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4185 mutex_lock(&dev
->mode_config
.mutex
);
4186 edp_panel_vdd_off_sync(intel_dp
);
4187 mutex_unlock(&dev
->mode_config
.mutex
);
4189 drm_sysfs_connector_remove(connector
);
4190 drm_connector_cleanup(connector
);
4194 intel_dp_add_properties(intel_dp
, connector
);
4196 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4197 * 0xd. Failure to do so will result in spurious interrupts being
4198 * generated on the port when a cable is not attached.
4200 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
4201 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
4202 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
4209 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
4211 struct intel_digital_port
*intel_dig_port
;
4212 struct intel_encoder
*intel_encoder
;
4213 struct drm_encoder
*encoder
;
4214 struct intel_connector
*intel_connector
;
4216 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
4217 if (!intel_dig_port
)
4220 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
4221 if (!intel_connector
) {
4222 kfree(intel_dig_port
);
4226 intel_encoder
= &intel_dig_port
->base
;
4227 encoder
= &intel_encoder
->base
;
4229 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
4230 DRM_MODE_ENCODER_TMDS
);
4232 intel_encoder
->compute_config
= intel_dp_compute_config
;
4233 intel_encoder
->disable
= intel_disable_dp
;
4234 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
4235 intel_encoder
->get_config
= intel_dp_get_config
;
4236 if (IS_CHERRYVIEW(dev
)) {
4237 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
4238 intel_encoder
->enable
= vlv_enable_dp
;
4239 } else if (IS_VALLEYVIEW(dev
)) {
4240 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
4241 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
4242 intel_encoder
->enable
= vlv_enable_dp
;
4243 intel_encoder
->post_disable
= vlv_post_disable_dp
;
4245 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
4246 intel_encoder
->enable
= g4x_enable_dp
;
4247 intel_encoder
->post_disable
= g4x_post_disable_dp
;
4250 intel_dig_port
->port
= port
;
4251 intel_dig_port
->dp
.output_reg
= output_reg
;
4253 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4254 if (IS_CHERRYVIEW(dev
)) {
4256 intel_encoder
->crtc_mask
= 1 << 2;
4258 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
4260 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
4262 intel_encoder
->cloneable
= 0;
4263 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4265 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4266 drm_encoder_cleanup(encoder
);
4267 kfree(intel_dig_port
);
4268 kfree(intel_connector
);