2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
193 static enum drm_mode_status
194 intel_dp_mode_valid(struct drm_connector
*connector
,
195 struct drm_display_mode
*mode
)
197 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
198 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
199 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
200 int target_clock
= mode
->clock
;
201 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
202 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
204 if (is_edp(intel_dp
) && fixed_mode
) {
205 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
208 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
211 target_clock
= fixed_mode
->clock
;
214 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
215 max_lanes
= intel_dp_max_lane_count(intel_dp
);
217 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
218 mode_rate
= intel_dp_link_required(target_clock
, 18);
220 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
221 return MODE_CLOCK_HIGH
;
223 if (mode
->clock
< 10000)
224 return MODE_CLOCK_LOW
;
226 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
227 return MODE_H_ILLEGAL
;
232 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
239 for (i
= 0; i
< src_bytes
; i
++)
240 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
244 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
249 for (i
= 0; i
< dst_bytes
; i
++)
250 dst
[i
] = src
>> ((3-i
) * 8);
254 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
255 struct intel_dp
*intel_dp
);
257 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
258 struct intel_dp
*intel_dp
);
260 static void pps_lock(struct intel_dp
*intel_dp
)
262 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
263 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
264 struct drm_device
*dev
= encoder
->base
.dev
;
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 enum intel_display_power_domain power_domain
;
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
272 power_domain
= intel_display_port_aux_power_domain(encoder
);
273 intel_display_power_get(dev_priv
, power_domain
);
275 mutex_lock(&dev_priv
->pps_mutex
);
278 static void pps_unlock(struct intel_dp
*intel_dp
)
280 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
281 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
282 struct drm_device
*dev
= encoder
->base
.dev
;
283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
284 enum intel_display_power_domain power_domain
;
286 mutex_unlock(&dev_priv
->pps_mutex
);
288 power_domain
= intel_display_port_aux_power_domain(encoder
);
289 intel_display_power_put(dev_priv
, power_domain
);
293 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
296 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 enum pipe pipe
= intel_dp
->pps_pipe
;
299 bool pll_enabled
, release_cl_override
= false;
300 enum dpio_phy phy
= DPIO_PHY(pipe
);
301 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
304 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe
), port_name(intel_dig_port
->port
));
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
315 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
316 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
317 DP
|= DP_PORT_WIDTH(1);
318 DP
|= DP_LINK_TRAIN_PAT_1
;
320 if (IS_CHERRYVIEW(dev
))
321 DP
|= DP_PIPE_SELECT_CHV(pipe
);
322 else if (pipe
== PIPE_B
)
323 DP
|= DP_PIPEB_SELECT
;
325 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
332 release_cl_override
= IS_CHERRYVIEW(dev
) &&
333 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
335 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
336 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
349 I915_WRITE(intel_dp
->output_reg
, DP
);
350 POSTING_READ(intel_dp
->output_reg
);
352 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
353 POSTING_READ(intel_dp
->output_reg
);
355 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
356 POSTING_READ(intel_dp
->output_reg
);
359 vlv_force_pll_off(dev
, pipe
);
361 if (release_cl_override
)
362 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
367 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
369 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
370 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
372 struct intel_encoder
*encoder
;
373 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
376 lockdep_assert_held(&dev_priv
->pps_mutex
);
378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp
));
381 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
382 return intel_dp
->pps_pipe
;
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
388 for_each_intel_encoder(dev
, encoder
) {
389 struct intel_dp
*tmp
;
391 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
394 tmp
= enc_to_intel_dp(&encoder
->base
);
396 if (tmp
->pps_pipe
!= INVALID_PIPE
)
397 pipes
&= ~(1 << tmp
->pps_pipe
);
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
404 if (WARN_ON(pipes
== 0))
407 pipe
= ffs(pipes
) - 1;
409 vlv_steal_power_sequencer(dev
, pipe
);
410 intel_dp
->pps_pipe
= pipe
;
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp
->pps_pipe
),
414 port_name(intel_dig_port
->port
));
416 /* init power sequencer on this pipe and port */
417 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
418 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
424 vlv_power_sequencer_kick(intel_dp
);
426 return intel_dp
->pps_pipe
;
429 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
432 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
435 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
438 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
441 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
444 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
451 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
453 vlv_pipe_check pipe_check
)
457 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
458 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
459 PANEL_PORT_SELECT_MASK
;
461 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
464 if (!pipe_check(dev_priv
, pipe
))
474 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
476 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
477 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
479 enum port port
= intel_dig_port
->port
;
481 lockdep_assert_held(&dev_priv
->pps_mutex
);
483 /* try to find a pipe with this port selected */
484 /* first pick one where the panel is on */
485 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
487 /* didn't find one? pick one where vdd is on */
488 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
489 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
490 vlv_pipe_has_vdd_on
);
491 /* didn't find one? pick one with just the correct port */
492 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
493 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
496 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
497 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
498 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
503 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
504 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
506 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
507 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
510 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
512 struct drm_device
*dev
= dev_priv
->dev
;
513 struct intel_encoder
*encoder
;
515 if (WARN_ON(!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)))
519 * We can't grab pps_mutex here due to deadlock with power_domain
520 * mutex when power_domain functions are called while holding pps_mutex.
521 * That also means that in order to use pps_pipe the code needs to
522 * hold both a power domain reference and pps_mutex, and the power domain
523 * reference get/put must be done while _not_ holding pps_mutex.
524 * pps_{lock,unlock}() do these steps in the correct order, so one
525 * should use them always.
528 for_each_intel_encoder(dev
, encoder
) {
529 struct intel_dp
*intel_dp
;
531 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
534 intel_dp
= enc_to_intel_dp(&encoder
->base
);
535 intel_dp
->pps_pipe
= INVALID_PIPE
;
540 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
542 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
545 return BXT_PP_CONTROL(0);
546 else if (HAS_PCH_SPLIT(dev
))
547 return PCH_PP_CONTROL
;
549 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
553 _pp_stat_reg(struct intel_dp
*intel_dp
)
555 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
558 return BXT_PP_STATUS(0);
559 else if (HAS_PCH_SPLIT(dev
))
560 return PCH_PP_STATUS
;
562 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
565 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
566 This function only applicable when panel PM state is not to be tracked */
567 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
570 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
572 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
575 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
580 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
581 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
582 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
585 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
586 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
587 pp_div
= I915_READ(pp_div_reg
);
588 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
590 /* 0x1F write to PP_DIV_REG sets max cycle delay */
591 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
592 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
593 msleep(intel_dp
->panel_power_cycle_delay
);
596 pps_unlock(intel_dp
);
601 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
603 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
606 lockdep_assert_held(&dev_priv
->pps_mutex
);
608 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
609 intel_dp
->pps_pipe
== INVALID_PIPE
)
612 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
615 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
617 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
620 lockdep_assert_held(&dev_priv
->pps_mutex
);
622 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
623 intel_dp
->pps_pipe
== INVALID_PIPE
)
626 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
630 intel_dp_check_edp(struct intel_dp
*intel_dp
)
632 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
635 if (!is_edp(intel_dp
))
638 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
639 WARN(1, "eDP powered off while attempting aux channel communication.\n");
640 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
641 I915_READ(_pp_stat_reg(intel_dp
)),
642 I915_READ(_pp_ctrl_reg(intel_dp
)));
647 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
649 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
650 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
652 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
656 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
658 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
659 msecs_to_jiffies_timeout(10));
661 done
= wait_for_atomic(C
, 10) == 0;
663 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
670 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
672 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
673 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
679 * The clock divider is based off the hrawclk, and would like to run at
680 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
682 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
685 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
687 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
688 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
694 * The clock divider is based off the cdclk or PCH rawclk, and would
695 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
696 * divide by 2000 and use that
698 if (intel_dig_port
->port
== PORT_A
)
699 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
701 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
704 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
706 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
707 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
709 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
710 /* Workaround for non-ULT HSW */
718 return ilk_get_aux_clock_divider(intel_dp
, index
);
721 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
724 * SKL doesn't need us to program the AUX clock divider (Hardware will
725 * derive the clock from CDCLK automatically). We still implement the
726 * get_aux_clock_divider vfunc to plug-in into the existing code.
728 return index
? 0 : 1;
731 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
734 uint32_t aux_clock_divider
)
736 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
737 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
738 uint32_t precharge
, timeout
;
745 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
746 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
748 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
750 return DP_AUX_CH_CTL_SEND_BUSY
|
752 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
753 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
755 DP_AUX_CH_CTL_RECEIVE_ERROR
|
756 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
757 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
758 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
761 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
766 return DP_AUX_CH_CTL_SEND_BUSY
|
768 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
769 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
770 DP_AUX_CH_CTL_TIME_OUT_1600us
|
771 DP_AUX_CH_CTL_RECEIVE_ERROR
|
772 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
773 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
777 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
778 const uint8_t *send
, int send_bytes
,
779 uint8_t *recv
, int recv_size
)
781 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
782 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
784 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
785 uint32_t aux_clock_divider
;
786 int i
, ret
, recv_bytes
;
789 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
795 * We will be called with VDD already enabled for dpcd/edid/oui reads.
796 * In such cases we want to leave VDD enabled and it's up to upper layers
797 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
800 vdd
= edp_panel_vdd_on(intel_dp
);
802 /* dp aux is extremely sensitive to irq latency, hence request the
803 * lowest possible wakeup latency and so prevent the cpu from going into
806 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
808 intel_dp_check_edp(intel_dp
);
810 /* Try to wait for any previous AUX channel activity */
811 for (try = 0; try < 3; try++) {
812 status
= I915_READ_NOTRACE(ch_ctl
);
813 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
819 static u32 last_status
= -1;
820 const u32 status
= I915_READ(ch_ctl
);
822 if (status
!= last_status
) {
823 WARN(1, "dp_aux_ch not started status 0x%08x\n",
825 last_status
= status
;
832 /* Only 5 data registers! */
833 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
838 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
839 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
844 /* Must try at least 3 times according to DP spec */
845 for (try = 0; try < 5; try++) {
846 /* Load the send data into the aux channel data registers */
847 for (i
= 0; i
< send_bytes
; i
+= 4)
848 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
849 intel_dp_pack_aux(send
+ i
,
852 /* Send the command and wait for it to complete */
853 I915_WRITE(ch_ctl
, send_ctl
);
855 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
857 /* Clear done status and any errors */
861 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
862 DP_AUX_CH_CTL_RECEIVE_ERROR
);
864 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
867 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
868 * 400us delay required for errors and timeouts
869 * Timeout errors from the HW already meet this
870 * requirement so skip to next iteration
872 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
873 usleep_range(400, 500);
876 if (status
& DP_AUX_CH_CTL_DONE
)
881 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
882 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
888 /* Check for timeout or receive error.
889 * Timeouts occur when the sink is not connected
891 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
892 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
897 /* Timeouts occur when the device isn't connected, so they're
898 * "normal" -- don't fill the kernel log with these */
899 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
900 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
905 /* Unload any bytes sent back from the other side */
906 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
907 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
910 * By BSpec: "Message sizes of 0 or >20 are not allowed."
911 * We have no idea of what happened so we return -EBUSY so
912 * drm layer takes care for the necessary retries.
914 if (recv_bytes
== 0 || recv_bytes
> 20) {
915 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
918 * FIXME: This patch was created on top of a series that
919 * organize the retries at drm level. There EBUSY should
920 * also take care for 1ms wait before retrying.
921 * That aux retries re-org is still needed and after that is
922 * merged we remove this sleep from here.
924 usleep_range(1000, 1500);
929 if (recv_bytes
> recv_size
)
930 recv_bytes
= recv_size
;
932 for (i
= 0; i
< recv_bytes
; i
+= 4)
933 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
934 recv
+ i
, recv_bytes
- i
);
938 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
941 edp_panel_vdd_off(intel_dp
, false);
943 pps_unlock(intel_dp
);
948 #define BARE_ADDRESS_SIZE 3
949 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
951 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
953 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
954 uint8_t txbuf
[20], rxbuf
[20];
955 size_t txsize
, rxsize
;
958 txbuf
[0] = (msg
->request
<< 4) |
959 ((msg
->address
>> 16) & 0xf);
960 txbuf
[1] = (msg
->address
>> 8) & 0xff;
961 txbuf
[2] = msg
->address
& 0xff;
962 txbuf
[3] = msg
->size
- 1;
964 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
965 case DP_AUX_NATIVE_WRITE
:
966 case DP_AUX_I2C_WRITE
:
967 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
968 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
969 rxsize
= 2; /* 0 or 1 data bytes */
971 if (WARN_ON(txsize
> 20))
975 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
979 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
981 msg
->reply
= rxbuf
[0] >> 4;
984 /* Number of bytes written in a short write. */
985 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
987 /* Return payload size. */
993 case DP_AUX_NATIVE_READ
:
994 case DP_AUX_I2C_READ
:
995 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
996 rxsize
= msg
->size
+ 1;
998 if (WARN_ON(rxsize
> 20))
1001 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1003 msg
->reply
= rxbuf
[0] >> 4;
1005 * Assume happy day, and copy the data. The caller is
1006 * expected to check msg->reply before touching it.
1008 * Return payload size.
1011 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1023 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1030 return DP_AUX_CH_CTL(port
);
1033 return DP_AUX_CH_CTL(PORT_B
);
1037 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1038 enum port port
, int index
)
1044 return DP_AUX_CH_DATA(port
, index
);
1047 return DP_AUX_CH_DATA(PORT_B
, index
);
1051 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1056 return DP_AUX_CH_CTL(port
);
1060 return PCH_DP_AUX_CH_CTL(port
);
1063 return DP_AUX_CH_CTL(PORT_A
);
1067 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1068 enum port port
, int index
)
1072 return DP_AUX_CH_DATA(port
, index
);
1076 return PCH_DP_AUX_CH_DATA(port
, index
);
1079 return DP_AUX_CH_DATA(PORT_A
, index
);
1084 * On SKL we don't have Aux for port E so we rely
1085 * on VBT to set a proper alternate aux channel.
1087 static enum port
skl_porte_aux_port(struct drm_i915_private
*dev_priv
)
1089 const struct ddi_vbt_port_info
*info
=
1090 &dev_priv
->vbt
.ddi_port_info
[PORT_E
];
1092 switch (info
->alternate_aux_channel
) {
1102 MISSING_CASE(info
->alternate_aux_channel
);
1107 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1111 port
= skl_porte_aux_port(dev_priv
);
1118 return DP_AUX_CH_CTL(port
);
1121 return DP_AUX_CH_CTL(PORT_A
);
1125 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1126 enum port port
, int index
)
1129 port
= skl_porte_aux_port(dev_priv
);
1136 return DP_AUX_CH_DATA(port
, index
);
1139 return DP_AUX_CH_DATA(PORT_A
, index
);
1143 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1146 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1147 return skl_aux_ctl_reg(dev_priv
, port
);
1148 else if (HAS_PCH_SPLIT(dev_priv
))
1149 return ilk_aux_ctl_reg(dev_priv
, port
);
1151 return g4x_aux_ctl_reg(dev_priv
, port
);
1154 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1155 enum port port
, int index
)
1157 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1158 return skl_aux_data_reg(dev_priv
, port
, index
);
1159 else if (HAS_PCH_SPLIT(dev_priv
))
1160 return ilk_aux_data_reg(dev_priv
, port
, index
);
1162 return g4x_aux_data_reg(dev_priv
, port
, index
);
1165 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1167 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1168 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1171 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1172 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1173 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1177 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1179 drm_dp_aux_unregister(&intel_dp
->aux
);
1180 kfree(intel_dp
->aux
.name
);
1184 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1186 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1187 enum port port
= intel_dig_port
->port
;
1190 intel_aux_reg_init(intel_dp
);
1192 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1193 if (!intel_dp
->aux
.name
)
1196 intel_dp
->aux
.dev
= connector
->base
.kdev
;
1197 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1199 DRM_DEBUG_KMS("registering %s bus for %s\n",
1201 connector
->base
.kdev
->kobj
.name
);
1203 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1205 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1206 intel_dp
->aux
.name
, ret
);
1207 kfree(intel_dp
->aux
.name
);
1215 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1217 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1219 intel_dp_aux_fini(intel_dp
);
1220 intel_connector_unregister(intel_connector
);
1224 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1226 if (intel_dp
->num_sink_rates
) {
1227 *sink_rates
= intel_dp
->sink_rates
;
1228 return intel_dp
->num_sink_rates
;
1231 *sink_rates
= default_rates
;
1233 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1236 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1238 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1239 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1241 /* WaDisableHBR2:skl */
1242 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
))
1245 if ((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) || IS_BROADWELL(dev
) ||
1246 (INTEL_INFO(dev
)->gen
>= 9))
1253 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1255 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1256 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1259 if (IS_BROXTON(dev
)) {
1260 *source_rates
= bxt_rates
;
1261 size
= ARRAY_SIZE(bxt_rates
);
1262 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1263 *source_rates
= skl_rates
;
1264 size
= ARRAY_SIZE(skl_rates
);
1266 *source_rates
= default_rates
;
1267 size
= ARRAY_SIZE(default_rates
);
1270 /* This depends on the fact that 5.4 is last value in the array */
1271 if (!intel_dp_source_supports_hbr2(intel_dp
))
1278 intel_dp_set_clock(struct intel_encoder
*encoder
,
1279 struct intel_crtc_state
*pipe_config
)
1281 struct drm_device
*dev
= encoder
->base
.dev
;
1282 const struct dp_link_dpll
*divisor
= NULL
;
1286 divisor
= gen4_dpll
;
1287 count
= ARRAY_SIZE(gen4_dpll
);
1288 } else if (HAS_PCH_SPLIT(dev
)) {
1290 count
= ARRAY_SIZE(pch_dpll
);
1291 } else if (IS_CHERRYVIEW(dev
)) {
1293 count
= ARRAY_SIZE(chv_dpll
);
1294 } else if (IS_VALLEYVIEW(dev
)) {
1296 count
= ARRAY_SIZE(vlv_dpll
);
1299 if (divisor
&& count
) {
1300 for (i
= 0; i
< count
; i
++) {
1301 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1302 pipe_config
->dpll
= divisor
[i
].dpll
;
1303 pipe_config
->clock_set
= true;
1310 static int intersect_rates(const int *source_rates
, int source_len
,
1311 const int *sink_rates
, int sink_len
,
1314 int i
= 0, j
= 0, k
= 0;
1316 while (i
< source_len
&& j
< sink_len
) {
1317 if (source_rates
[i
] == sink_rates
[j
]) {
1318 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1320 common_rates
[k
] = source_rates
[i
];
1324 } else if (source_rates
[i
] < sink_rates
[j
]) {
1333 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1336 const int *source_rates
, *sink_rates
;
1337 int source_len
, sink_len
;
1339 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1340 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1342 return intersect_rates(source_rates
, source_len
,
1343 sink_rates
, sink_len
,
1347 static void snprintf_int_array(char *str
, size_t len
,
1348 const int *array
, int nelem
)
1354 for (i
= 0; i
< nelem
; i
++) {
1355 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1363 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1365 const int *source_rates
, *sink_rates
;
1366 int source_len
, sink_len
, common_len
;
1367 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1368 char str
[128]; /* FIXME: too big for stack? */
1370 if ((drm_debug
& DRM_UT_KMS
) == 0)
1373 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1374 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1375 DRM_DEBUG_KMS("source rates: %s\n", str
);
1377 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1378 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1379 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1381 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1382 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1383 DRM_DEBUG_KMS("common rates: %s\n", str
);
1386 static int rate_to_index(int find
, const int *rates
)
1390 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1391 if (find
== rates
[i
])
1398 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1400 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1403 len
= intel_dp_common_rates(intel_dp
, rates
);
1404 if (WARN_ON(len
<= 0))
1407 return rates
[rate_to_index(0, rates
) - 1];
1410 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1412 return rate_to_index(rate
, intel_dp
->sink_rates
);
1415 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1416 uint8_t *link_bw
, uint8_t *rate_select
)
1418 if (intel_dp
->num_sink_rates
) {
1421 intel_dp_rate_select(intel_dp
, port_clock
);
1423 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1429 intel_dp_compute_config(struct intel_encoder
*encoder
,
1430 struct intel_crtc_state
*pipe_config
)
1432 struct drm_device
*dev
= encoder
->base
.dev
;
1433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1434 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1435 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1436 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1437 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1438 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1439 int lane_count
, clock
;
1440 int min_lane_count
= 1;
1441 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1442 /* Conveniently, the link BW constants become indices with a shift...*/
1446 int link_avail
, link_clock
;
1447 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1449 uint8_t link_bw
, rate_select
;
1451 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1453 /* No common link rates between source and sink */
1454 WARN_ON(common_len
<= 0);
1456 max_clock
= common_len
- 1;
1458 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1459 pipe_config
->has_pch_encoder
= true;
1461 pipe_config
->has_dp_encoder
= true;
1462 pipe_config
->has_drrs
= false;
1463 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1465 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1466 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1469 if (INTEL_INFO(dev
)->gen
>= 9) {
1471 ret
= skl_update_scaler_crtc(pipe_config
);
1476 if (HAS_GMCH_DISPLAY(dev
))
1477 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1478 intel_connector
->panel
.fitting_mode
);
1480 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1481 intel_connector
->panel
.fitting_mode
);
1484 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1487 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1488 "max bw %d pixel clock %iKHz\n",
1489 max_lane_count
, common_rates
[max_clock
],
1490 adjusted_mode
->crtc_clock
);
1492 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1493 * bpc in between. */
1494 bpp
= pipe_config
->pipe_bpp
;
1495 if (is_edp(intel_dp
)) {
1497 /* Get bpp from vbt only for panels that dont have bpp in edid */
1498 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1499 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1500 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1501 dev_priv
->vbt
.edp
.bpp
);
1502 bpp
= dev_priv
->vbt
.edp
.bpp
;
1506 * Use the maximum clock and number of lanes the eDP panel
1507 * advertizes being capable of. The panels are generally
1508 * designed to support only a single clock and lane
1509 * configuration, and typically these values correspond to the
1510 * native resolution of the panel.
1512 min_lane_count
= max_lane_count
;
1513 min_clock
= max_clock
;
1516 for (; bpp
>= 6*3; bpp
-= 2*3) {
1517 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1520 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1521 for (lane_count
= min_lane_count
;
1522 lane_count
<= max_lane_count
;
1525 link_clock
= common_rates
[clock
];
1526 link_avail
= intel_dp_max_data_rate(link_clock
,
1529 if (mode_rate
<= link_avail
) {
1539 if (intel_dp
->color_range_auto
) {
1542 * CEA-861-E - 5.1 Default Encoding Parameters
1543 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1545 pipe_config
->limited_color_range
=
1546 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1548 pipe_config
->limited_color_range
=
1549 intel_dp
->limited_color_range
;
1552 pipe_config
->lane_count
= lane_count
;
1554 pipe_config
->pipe_bpp
= bpp
;
1555 pipe_config
->port_clock
= common_rates
[clock
];
1557 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1558 &link_bw
, &rate_select
);
1560 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1561 link_bw
, rate_select
, pipe_config
->lane_count
,
1562 pipe_config
->port_clock
, bpp
);
1563 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1564 mode_rate
, link_avail
);
1566 intel_link_compute_m_n(bpp
, lane_count
,
1567 adjusted_mode
->crtc_clock
,
1568 pipe_config
->port_clock
,
1569 &pipe_config
->dp_m_n
);
1571 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1572 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1573 pipe_config
->has_drrs
= true;
1574 intel_link_compute_m_n(bpp
, lane_count
,
1575 intel_connector
->panel
.downclock_mode
->clock
,
1576 pipe_config
->port_clock
,
1577 &pipe_config
->dp_m2_n2
);
1581 intel_dp_set_clock(encoder
, pipe_config
);
1586 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1587 const struct intel_crtc_state
*pipe_config
)
1589 intel_dp
->link_rate
= pipe_config
->port_clock
;
1590 intel_dp
->lane_count
= pipe_config
->lane_count
;
1593 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1595 struct drm_device
*dev
= encoder
->base
.dev
;
1596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1597 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1598 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1599 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1600 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1602 intel_dp_set_link_params(intel_dp
, crtc
->config
);
1605 * There are four kinds of DP registers:
1612 * IBX PCH and CPU are the same for almost everything,
1613 * except that the CPU DP PLL is configured in this
1616 * CPT PCH is quite different, having many bits moved
1617 * to the TRANS_DP_CTL register instead. That
1618 * configuration happens (oddly) in ironlake_pch_enable
1621 /* Preserve the BIOS-computed detected bit. This is
1622 * supposed to be read-only.
1624 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1626 /* Handle DP bits in common between all three register formats */
1627 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1628 intel_dp
->DP
|= DP_PORT_WIDTH(crtc
->config
->lane_count
);
1630 /* Split out the IBX/CPU vs CPT settings */
1632 if (IS_GEN7(dev
) && port
== PORT_A
) {
1633 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1634 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1635 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1636 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1637 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1639 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1640 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1642 intel_dp
->DP
|= crtc
->pipe
<< 29;
1643 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1646 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1648 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1649 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1650 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1652 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1653 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1655 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1656 !IS_CHERRYVIEW(dev
) && crtc
->config
->limited_color_range
)
1657 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1659 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1660 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1661 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1662 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1663 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1665 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1666 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1668 if (IS_CHERRYVIEW(dev
))
1669 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1670 else if (crtc
->pipe
== PIPE_B
)
1671 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1675 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1676 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1678 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1679 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1681 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1682 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1684 static void wait_panel_status(struct intel_dp
*intel_dp
,
1688 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1690 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1692 lockdep_assert_held(&dev_priv
->pps_mutex
);
1694 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1695 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1697 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1699 I915_READ(pp_stat_reg
),
1700 I915_READ(pp_ctrl_reg
));
1702 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
,
1703 5 * USEC_PER_SEC
, 10 * USEC_PER_MSEC
))
1704 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1705 I915_READ(pp_stat_reg
),
1706 I915_READ(pp_ctrl_reg
));
1708 DRM_DEBUG_KMS("Wait complete\n");
1711 static void wait_panel_on(struct intel_dp
*intel_dp
)
1713 DRM_DEBUG_KMS("Wait for panel power on\n");
1714 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1717 static void wait_panel_off(struct intel_dp
*intel_dp
)
1719 DRM_DEBUG_KMS("Wait for panel power off time\n");
1720 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1723 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1725 ktime_t panel_power_on_time
;
1726 s64 panel_power_off_duration
;
1728 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1730 /* take the difference of currrent time and panel power off time
1731 * and then make panel wait for t11_t12 if needed. */
1732 panel_power_on_time
= ktime_get_boottime();
1733 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1735 /* When we disable the VDD override bit last we have to do the manual
1737 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1738 wait_remaining_ms_from_jiffies(jiffies
,
1739 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1741 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1744 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1746 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1747 intel_dp
->backlight_on_delay
);
1750 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1752 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1753 intel_dp
->backlight_off_delay
);
1756 /* Read the current pp_control value, unlocking the register if it
1760 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1762 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 lockdep_assert_held(&dev_priv
->pps_mutex
);
1768 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1769 if (!IS_BROXTON(dev
)) {
1770 control
&= ~PANEL_UNLOCK_MASK
;
1771 control
|= PANEL_UNLOCK_REGS
;
1777 * Must be paired with edp_panel_vdd_off().
1778 * Must hold pps_mutex around the whole on/off sequence.
1779 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1781 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1783 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1784 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1785 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1787 enum intel_display_power_domain power_domain
;
1789 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1790 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1792 lockdep_assert_held(&dev_priv
->pps_mutex
);
1794 if (!is_edp(intel_dp
))
1797 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1798 intel_dp
->want_panel_vdd
= true;
1800 if (edp_have_panel_vdd(intel_dp
))
1801 return need_to_disable
;
1803 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1804 intel_display_power_get(dev_priv
, power_domain
);
1806 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1807 port_name(intel_dig_port
->port
));
1809 if (!edp_have_panel_power(intel_dp
))
1810 wait_panel_power_cycle(intel_dp
);
1812 pp
= ironlake_get_pp_control(intel_dp
);
1813 pp
|= EDP_FORCE_VDD
;
1815 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1816 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1818 I915_WRITE(pp_ctrl_reg
, pp
);
1819 POSTING_READ(pp_ctrl_reg
);
1820 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1821 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1823 * If the panel wasn't on, delay before accessing aux channel
1825 if (!edp_have_panel_power(intel_dp
)) {
1826 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1827 port_name(intel_dig_port
->port
));
1828 msleep(intel_dp
->panel_power_up_delay
);
1831 return need_to_disable
;
1835 * Must be paired with intel_edp_panel_vdd_off() or
1836 * intel_edp_panel_off().
1837 * Nested calls to these functions are not allowed since
1838 * we drop the lock. Caller must use some higher level
1839 * locking to prevent nested calls from other threads.
1841 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1845 if (!is_edp(intel_dp
))
1849 vdd
= edp_panel_vdd_on(intel_dp
);
1850 pps_unlock(intel_dp
);
1852 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1853 port_name(dp_to_dig_port(intel_dp
)->port
));
1856 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1858 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1860 struct intel_digital_port
*intel_dig_port
=
1861 dp_to_dig_port(intel_dp
);
1862 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1863 enum intel_display_power_domain power_domain
;
1865 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1867 lockdep_assert_held(&dev_priv
->pps_mutex
);
1869 WARN_ON(intel_dp
->want_panel_vdd
);
1871 if (!edp_have_panel_vdd(intel_dp
))
1874 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1875 port_name(intel_dig_port
->port
));
1877 pp
= ironlake_get_pp_control(intel_dp
);
1878 pp
&= ~EDP_FORCE_VDD
;
1880 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1881 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1883 I915_WRITE(pp_ctrl_reg
, pp
);
1884 POSTING_READ(pp_ctrl_reg
);
1886 /* Make sure sequencer is idle before allowing subsequent activity */
1887 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1888 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1890 if ((pp
& POWER_TARGET_ON
) == 0)
1891 intel_dp
->panel_power_off_time
= ktime_get_boottime();
1893 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1894 intel_display_power_put(dev_priv
, power_domain
);
1897 static void edp_panel_vdd_work(struct work_struct
*__work
)
1899 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1900 struct intel_dp
, panel_vdd_work
);
1903 if (!intel_dp
->want_panel_vdd
)
1904 edp_panel_vdd_off_sync(intel_dp
);
1905 pps_unlock(intel_dp
);
1908 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1910 unsigned long delay
;
1913 * Queue the timer to fire a long time from now (relative to the power
1914 * down delay) to keep the panel power up across a sequence of
1917 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1918 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1922 * Must be paired with edp_panel_vdd_on().
1923 * Must hold pps_mutex around the whole on/off sequence.
1924 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1926 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1928 struct drm_i915_private
*dev_priv
=
1929 intel_dp_to_dev(intel_dp
)->dev_private
;
1931 lockdep_assert_held(&dev_priv
->pps_mutex
);
1933 if (!is_edp(intel_dp
))
1936 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1937 port_name(dp_to_dig_port(intel_dp
)->port
));
1939 intel_dp
->want_panel_vdd
= false;
1942 edp_panel_vdd_off_sync(intel_dp
);
1944 edp_panel_vdd_schedule_off(intel_dp
);
1947 static void edp_panel_on(struct intel_dp
*intel_dp
)
1949 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1952 i915_reg_t pp_ctrl_reg
;
1954 lockdep_assert_held(&dev_priv
->pps_mutex
);
1956 if (!is_edp(intel_dp
))
1959 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1960 port_name(dp_to_dig_port(intel_dp
)->port
));
1962 if (WARN(edp_have_panel_power(intel_dp
),
1963 "eDP port %c panel power already on\n",
1964 port_name(dp_to_dig_port(intel_dp
)->port
)))
1967 wait_panel_power_cycle(intel_dp
);
1969 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1970 pp
= ironlake_get_pp_control(intel_dp
);
1972 /* ILK workaround: disable reset around power sequence */
1973 pp
&= ~PANEL_POWER_RESET
;
1974 I915_WRITE(pp_ctrl_reg
, pp
);
1975 POSTING_READ(pp_ctrl_reg
);
1978 pp
|= POWER_TARGET_ON
;
1980 pp
|= PANEL_POWER_RESET
;
1982 I915_WRITE(pp_ctrl_reg
, pp
);
1983 POSTING_READ(pp_ctrl_reg
);
1985 wait_panel_on(intel_dp
);
1986 intel_dp
->last_power_on
= jiffies
;
1989 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1990 I915_WRITE(pp_ctrl_reg
, pp
);
1991 POSTING_READ(pp_ctrl_reg
);
1995 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1997 if (!is_edp(intel_dp
))
2001 edp_panel_on(intel_dp
);
2002 pps_unlock(intel_dp
);
2006 static void edp_panel_off(struct intel_dp
*intel_dp
)
2008 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2009 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2010 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 enum intel_display_power_domain power_domain
;
2014 i915_reg_t pp_ctrl_reg
;
2016 lockdep_assert_held(&dev_priv
->pps_mutex
);
2018 if (!is_edp(intel_dp
))
2021 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2022 port_name(dp_to_dig_port(intel_dp
)->port
));
2024 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2025 port_name(dp_to_dig_port(intel_dp
)->port
));
2027 pp
= ironlake_get_pp_control(intel_dp
);
2028 /* We need to switch off panel power _and_ force vdd, for otherwise some
2029 * panels get very unhappy and cease to work. */
2030 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2033 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2035 intel_dp
->want_panel_vdd
= false;
2037 I915_WRITE(pp_ctrl_reg
, pp
);
2038 POSTING_READ(pp_ctrl_reg
);
2040 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2041 wait_panel_off(intel_dp
);
2043 /* We got a reference when we enabled the VDD. */
2044 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2045 intel_display_power_put(dev_priv
, power_domain
);
2048 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2050 if (!is_edp(intel_dp
))
2054 edp_panel_off(intel_dp
);
2055 pps_unlock(intel_dp
);
2058 /* Enable backlight in the panel power control. */
2059 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2061 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2062 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2065 i915_reg_t pp_ctrl_reg
;
2068 * If we enable the backlight right away following a panel power
2069 * on, we may see slight flicker as the panel syncs with the eDP
2070 * link. So delay a bit to make sure the image is solid before
2071 * allowing it to appear.
2073 wait_backlight_on(intel_dp
);
2077 pp
= ironlake_get_pp_control(intel_dp
);
2078 pp
|= EDP_BLC_ENABLE
;
2080 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2082 I915_WRITE(pp_ctrl_reg
, pp
);
2083 POSTING_READ(pp_ctrl_reg
);
2085 pps_unlock(intel_dp
);
2088 /* Enable backlight PWM and backlight PP control. */
2089 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2091 if (!is_edp(intel_dp
))
2094 DRM_DEBUG_KMS("\n");
2096 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2097 _intel_edp_backlight_on(intel_dp
);
2100 /* Disable backlight in the panel power control. */
2101 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2103 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2106 i915_reg_t pp_ctrl_reg
;
2108 if (!is_edp(intel_dp
))
2113 pp
= ironlake_get_pp_control(intel_dp
);
2114 pp
&= ~EDP_BLC_ENABLE
;
2116 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2118 I915_WRITE(pp_ctrl_reg
, pp
);
2119 POSTING_READ(pp_ctrl_reg
);
2121 pps_unlock(intel_dp
);
2123 intel_dp
->last_backlight_off
= jiffies
;
2124 edp_wait_backlight_off(intel_dp
);
2127 /* Disable backlight PP control and backlight PWM. */
2128 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2130 if (!is_edp(intel_dp
))
2133 DRM_DEBUG_KMS("\n");
2135 _intel_edp_backlight_off(intel_dp
);
2136 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2140 * Hook for controlling the panel power control backlight through the bl_power
2141 * sysfs attribute. Take care to handle multiple calls.
2143 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2146 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2150 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2151 pps_unlock(intel_dp
);
2153 if (is_enabled
== enable
)
2156 DRM_DEBUG_KMS("panel power control backlight %s\n",
2157 enable
? "enable" : "disable");
2160 _intel_edp_backlight_on(intel_dp
);
2162 _intel_edp_backlight_off(intel_dp
);
2165 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2167 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2168 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2169 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2171 I915_STATE_WARN(cur_state
!= state
,
2172 "DP port %c state assertion failure (expected %s, current %s)\n",
2173 port_name(dig_port
->port
),
2174 onoff(state
), onoff(cur_state
));
2176 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2178 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2180 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2182 I915_STATE_WARN(cur_state
!= state
,
2183 "eDP PLL state assertion failure (expected %s, current %s)\n",
2184 onoff(state
), onoff(cur_state
));
2186 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2187 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2189 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2191 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2192 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2193 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2195 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2196 assert_dp_port_disabled(intel_dp
);
2197 assert_edp_pll_disabled(dev_priv
);
2199 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2200 crtc
->config
->port_clock
);
2202 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2204 if (crtc
->config
->port_clock
== 162000)
2205 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2207 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2209 I915_WRITE(DP_A
, intel_dp
->DP
);
2214 * [DevILK] Work around required when enabling DP PLL
2215 * while a pipe is enabled going to FDI:
2216 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2217 * 2. Program DP PLL enable
2219 if (IS_GEN5(dev_priv
))
2220 intel_wait_for_vblank_if_active(dev_priv
->dev
, !crtc
->pipe
);
2222 intel_dp
->DP
|= DP_PLL_ENABLE
;
2224 I915_WRITE(DP_A
, intel_dp
->DP
);
2229 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2231 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2232 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2233 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2235 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2236 assert_dp_port_disabled(intel_dp
);
2237 assert_edp_pll_enabled(dev_priv
);
2239 DRM_DEBUG_KMS("disabling eDP PLL\n");
2241 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2243 I915_WRITE(DP_A
, intel_dp
->DP
);
2248 /* If the sink supports it, try to set the power state appropriately */
2249 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2253 /* Should have a valid DPCD by this point */
2254 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2257 if (mode
!= DRM_MODE_DPMS_ON
) {
2258 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2262 * When turning on, we need to retry for 1ms to give the sink
2265 for (i
= 0; i
< 3; i
++) {
2266 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2275 DRM_DEBUG_KMS("failed to %s sink power state\n",
2276 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2279 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2282 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2283 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2284 struct drm_device
*dev
= encoder
->base
.dev
;
2285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2286 enum intel_display_power_domain power_domain
;
2290 power_domain
= intel_display_port_power_domain(encoder
);
2291 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2296 tmp
= I915_READ(intel_dp
->output_reg
);
2298 if (!(tmp
& DP_PORT_EN
))
2301 if (IS_GEN7(dev
) && port
== PORT_A
) {
2302 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2303 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2306 for_each_pipe(dev_priv
, p
) {
2307 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2308 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2316 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2317 i915_mmio_reg_offset(intel_dp
->output_reg
));
2318 } else if (IS_CHERRYVIEW(dev
)) {
2319 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2321 *pipe
= PORT_TO_PIPE(tmp
);
2327 intel_display_power_put(dev_priv
, power_domain
);
2332 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2333 struct intel_crtc_state
*pipe_config
)
2335 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2337 struct drm_device
*dev
= encoder
->base
.dev
;
2338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2339 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2340 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2342 tmp
= I915_READ(intel_dp
->output_reg
);
2344 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2346 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2347 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2349 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2350 flags
|= DRM_MODE_FLAG_PHSYNC
;
2352 flags
|= DRM_MODE_FLAG_NHSYNC
;
2354 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2355 flags
|= DRM_MODE_FLAG_PVSYNC
;
2357 flags
|= DRM_MODE_FLAG_NVSYNC
;
2359 if (tmp
& DP_SYNC_HS_HIGH
)
2360 flags
|= DRM_MODE_FLAG_PHSYNC
;
2362 flags
|= DRM_MODE_FLAG_NHSYNC
;
2364 if (tmp
& DP_SYNC_VS_HIGH
)
2365 flags
|= DRM_MODE_FLAG_PVSYNC
;
2367 flags
|= DRM_MODE_FLAG_NVSYNC
;
2370 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2372 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2373 !IS_CHERRYVIEW(dev
) && tmp
& DP_COLOR_RANGE_16_235
)
2374 pipe_config
->limited_color_range
= true;
2376 pipe_config
->has_dp_encoder
= true;
2378 pipe_config
->lane_count
=
2379 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2381 intel_dp_get_m_n(crtc
, pipe_config
);
2383 if (port
== PORT_A
) {
2384 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2385 pipe_config
->port_clock
= 162000;
2387 pipe_config
->port_clock
= 270000;
2390 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2391 intel_dotclock_calculate(pipe_config
->port_clock
,
2392 &pipe_config
->dp_m_n
);
2394 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2395 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2397 * This is a big fat ugly hack.
2399 * Some machines in UEFI boot mode provide us a VBT that has 18
2400 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2401 * unknown we fail to light up. Yet the same BIOS boots up with
2402 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2403 * max, not what it tells us to use.
2405 * Note: This will still be broken if the eDP panel is not lit
2406 * up by the BIOS, and thus we can't get the mode at module
2409 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2410 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2411 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2415 static void intel_disable_dp(struct intel_encoder
*encoder
)
2417 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2418 struct drm_device
*dev
= encoder
->base
.dev
;
2419 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2421 if (crtc
->config
->has_audio
)
2422 intel_audio_codec_disable(encoder
);
2424 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2425 intel_psr_disable(intel_dp
);
2427 /* Make sure the panel is off before trying to change the mode. But also
2428 * ensure that we have vdd while we switch off the panel. */
2429 intel_edp_panel_vdd_on(intel_dp
);
2430 intel_edp_backlight_off(intel_dp
);
2431 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2432 intel_edp_panel_off(intel_dp
);
2434 /* disable the port before the pipe on g4x */
2435 if (INTEL_INFO(dev
)->gen
< 5)
2436 intel_dp_link_down(intel_dp
);
2439 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2441 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2442 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2444 intel_dp_link_down(intel_dp
);
2446 /* Only ilk+ has port A */
2448 ironlake_edp_pll_off(intel_dp
);
2451 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2453 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2455 intel_dp_link_down(intel_dp
);
2458 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2460 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2461 struct drm_device
*dev
= encoder
->base
.dev
;
2462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2464 intel_dp_link_down(intel_dp
);
2466 mutex_lock(&dev_priv
->sb_lock
);
2468 /* Assert data lane reset */
2469 chv_data_lane_soft_reset(encoder
, true);
2471 mutex_unlock(&dev_priv
->sb_lock
);
2475 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2477 uint8_t dp_train_pat
)
2479 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2480 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2482 enum port port
= intel_dig_port
->port
;
2485 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2487 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2488 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2490 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2492 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2493 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2494 case DP_TRAINING_PATTERN_DISABLE
:
2495 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2498 case DP_TRAINING_PATTERN_1
:
2499 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2501 case DP_TRAINING_PATTERN_2
:
2502 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2504 case DP_TRAINING_PATTERN_3
:
2505 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2508 I915_WRITE(DP_TP_CTL(port
), temp
);
2510 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2511 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2512 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2514 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2515 case DP_TRAINING_PATTERN_DISABLE
:
2516 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2518 case DP_TRAINING_PATTERN_1
:
2519 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2521 case DP_TRAINING_PATTERN_2
:
2522 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2524 case DP_TRAINING_PATTERN_3
:
2525 DRM_ERROR("DP training pattern 3 not supported\n");
2526 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2531 if (IS_CHERRYVIEW(dev
))
2532 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2534 *DP
&= ~DP_LINK_TRAIN_MASK
;
2536 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2537 case DP_TRAINING_PATTERN_DISABLE
:
2538 *DP
|= DP_LINK_TRAIN_OFF
;
2540 case DP_TRAINING_PATTERN_1
:
2541 *DP
|= DP_LINK_TRAIN_PAT_1
;
2543 case DP_TRAINING_PATTERN_2
:
2544 *DP
|= DP_LINK_TRAIN_PAT_2
;
2546 case DP_TRAINING_PATTERN_3
:
2547 if (IS_CHERRYVIEW(dev
)) {
2548 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2550 DRM_ERROR("DP training pattern 3 not supported\n");
2551 *DP
|= DP_LINK_TRAIN_PAT_2
;
2558 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2560 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2562 struct intel_crtc
*crtc
=
2563 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
2565 /* enable with pattern 1 (as per spec) */
2566 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2567 DP_TRAINING_PATTERN_1
);
2569 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2570 POSTING_READ(intel_dp
->output_reg
);
2573 * Magic for VLV/CHV. We _must_ first set up the register
2574 * without actually enabling the port, and then do another
2575 * write to enable the port. Otherwise link training will
2576 * fail when the power sequencer is freshly used for this port.
2578 intel_dp
->DP
|= DP_PORT_EN
;
2579 if (crtc
->config
->has_audio
)
2580 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2582 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2583 POSTING_READ(intel_dp
->output_reg
);
2586 static void intel_enable_dp(struct intel_encoder
*encoder
)
2588 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2589 struct drm_device
*dev
= encoder
->base
.dev
;
2590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2591 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2592 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2593 enum pipe pipe
= crtc
->pipe
;
2595 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2600 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2601 vlv_init_panel_power_sequencer(intel_dp
);
2603 intel_dp_enable_port(intel_dp
);
2605 edp_panel_vdd_on(intel_dp
);
2606 edp_panel_on(intel_dp
);
2607 edp_panel_vdd_off(intel_dp
, true);
2609 pps_unlock(intel_dp
);
2611 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2612 unsigned int lane_mask
= 0x0;
2614 if (IS_CHERRYVIEW(dev
))
2615 lane_mask
= intel_dp_unused_lane_mask(crtc
->config
->lane_count
);
2617 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2621 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2622 intel_dp_start_link_train(intel_dp
);
2623 intel_dp_stop_link_train(intel_dp
);
2625 if (crtc
->config
->has_audio
) {
2626 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2628 intel_audio_codec_enable(encoder
);
2632 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2634 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2636 intel_enable_dp(encoder
);
2637 intel_edp_backlight_on(intel_dp
);
2640 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2642 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2644 intel_edp_backlight_on(intel_dp
);
2645 intel_psr_enable(intel_dp
);
2648 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2650 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2651 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2653 intel_dp_prepare(encoder
);
2655 /* Only ilk+ has port A */
2657 ironlake_edp_pll_on(intel_dp
);
2660 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2662 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2663 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2664 enum pipe pipe
= intel_dp
->pps_pipe
;
2665 i915_reg_t pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2667 edp_panel_vdd_off_sync(intel_dp
);
2670 * VLV seems to get confused when multiple power seqeuencers
2671 * have the same port selected (even if only one has power/vdd
2672 * enabled). The failure manifests as vlv_wait_port_ready() failing
2673 * CHV on the other hand doesn't seem to mind having the same port
2674 * selected in multiple power seqeuencers, but let's clear the
2675 * port select always when logically disconnecting a power sequencer
2678 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2679 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2680 I915_WRITE(pp_on_reg
, 0);
2681 POSTING_READ(pp_on_reg
);
2683 intel_dp
->pps_pipe
= INVALID_PIPE
;
2686 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2690 struct intel_encoder
*encoder
;
2692 lockdep_assert_held(&dev_priv
->pps_mutex
);
2694 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2697 for_each_intel_encoder(dev
, encoder
) {
2698 struct intel_dp
*intel_dp
;
2701 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2704 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2705 port
= dp_to_dig_port(intel_dp
)->port
;
2707 if (intel_dp
->pps_pipe
!= pipe
)
2710 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2711 pipe_name(pipe
), port_name(port
));
2713 WARN(encoder
->base
.crtc
,
2714 "stealing pipe %c power sequencer from active eDP port %c\n",
2715 pipe_name(pipe
), port_name(port
));
2717 /* make sure vdd is off before we steal it */
2718 vlv_detach_power_sequencer(intel_dp
);
2722 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2724 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2725 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2726 struct drm_device
*dev
= encoder
->base
.dev
;
2727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2728 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2730 lockdep_assert_held(&dev_priv
->pps_mutex
);
2732 if (!is_edp(intel_dp
))
2735 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2739 * If another power sequencer was being used on this
2740 * port previously make sure to turn off vdd there while
2741 * we still have control of it.
2743 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2744 vlv_detach_power_sequencer(intel_dp
);
2747 * We may be stealing the power
2748 * sequencer from another port.
2750 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2752 /* now it's all ours */
2753 intel_dp
->pps_pipe
= crtc
->pipe
;
2755 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2756 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2758 /* init power sequencer on this pipe and port */
2759 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2760 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2763 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2765 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2766 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2767 struct drm_device
*dev
= encoder
->base
.dev
;
2768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2769 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2770 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2771 int pipe
= intel_crtc
->pipe
;
2774 mutex_lock(&dev_priv
->sb_lock
);
2776 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2783 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2784 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2785 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2787 mutex_unlock(&dev_priv
->sb_lock
);
2789 intel_enable_dp(encoder
);
2792 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2794 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2795 struct drm_device
*dev
= encoder
->base
.dev
;
2796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2797 struct intel_crtc
*intel_crtc
=
2798 to_intel_crtc(encoder
->base
.crtc
);
2799 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2800 int pipe
= intel_crtc
->pipe
;
2802 intel_dp_prepare(encoder
);
2804 /* Program Tx lane resets to default */
2805 mutex_lock(&dev_priv
->sb_lock
);
2806 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2807 DPIO_PCS_TX_LANE2_RESET
|
2808 DPIO_PCS_TX_LANE1_RESET
);
2809 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2810 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2811 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2812 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2813 DPIO_PCS_CLK_SOFT_RESET
);
2815 /* Fix up inter-pair skew failure */
2816 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2817 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2818 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2819 mutex_unlock(&dev_priv
->sb_lock
);
2822 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2824 chv_phy_pre_encoder_enable(encoder
);
2826 intel_enable_dp(encoder
);
2828 /* Second common lane will stay alive on its own now */
2829 chv_phy_release_cl2_override(encoder
);
2832 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2834 intel_dp_prepare(encoder
);
2836 chv_phy_pre_pll_enable(encoder
);
2839 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
)
2841 chv_phy_post_pll_disable(encoder
);
2845 * Native read with retry for link status and receiver capability reads for
2846 * cases where the sink may still be asleep.
2848 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2849 * supposed to retry 3 times per the spec.
2852 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2853 void *buffer
, size_t size
)
2859 * Sometime we just get the same incorrect byte repeated
2860 * over the entire buffer. Doing just one throw away read
2861 * initially seems to "solve" it.
2863 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2865 for (i
= 0; i
< 3; i
++) {
2866 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2876 * Fetch AUX CH registers 0x202 - 0x207 which contain
2877 * link status information
2880 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2882 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2885 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2888 /* These are source-specific values. */
2890 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2892 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2894 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2896 if (IS_BROXTON(dev
))
2897 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2898 else if (INTEL_INFO(dev
)->gen
>= 9) {
2899 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2900 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2902 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2903 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2904 else if (IS_GEN7(dev
) && port
== PORT_A
)
2905 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2906 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2907 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2909 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2913 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2915 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2916 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2918 if (INTEL_INFO(dev
)->gen
>= 9) {
2919 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2921 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2923 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2925 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2927 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2929 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2931 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2932 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2941 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2943 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2944 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2946 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2948 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2950 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2953 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2955 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2956 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2958 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2963 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2966 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2968 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2970 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2972 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2975 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2980 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
2982 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
2983 unsigned long demph_reg_value
, preemph_reg_value
,
2984 uniqtranscale_reg_value
;
2985 uint8_t train_set
= intel_dp
->train_set
[0];
2987 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2988 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2989 preemph_reg_value
= 0x0004000;
2990 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2992 demph_reg_value
= 0x2B405555;
2993 uniqtranscale_reg_value
= 0x552AB83A;
2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2996 demph_reg_value
= 0x2B404040;
2997 uniqtranscale_reg_value
= 0x5548B83A;
2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3000 demph_reg_value
= 0x2B245555;
3001 uniqtranscale_reg_value
= 0x5560B83A;
3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3004 demph_reg_value
= 0x2B405555;
3005 uniqtranscale_reg_value
= 0x5598DA3A;
3011 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3012 preemph_reg_value
= 0x0002000;
3013 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3015 demph_reg_value
= 0x2B404040;
3016 uniqtranscale_reg_value
= 0x5552B83A;
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3019 demph_reg_value
= 0x2B404848;
3020 uniqtranscale_reg_value
= 0x5580B83A;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3023 demph_reg_value
= 0x2B404040;
3024 uniqtranscale_reg_value
= 0x55ADDA3A;
3030 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3031 preemph_reg_value
= 0x0000000;
3032 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3034 demph_reg_value
= 0x2B305555;
3035 uniqtranscale_reg_value
= 0x5570B83A;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3038 demph_reg_value
= 0x2B2B4040;
3039 uniqtranscale_reg_value
= 0x55ADDA3A;
3045 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3046 preemph_reg_value
= 0x0006000;
3047 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3049 demph_reg_value
= 0x1B405555;
3050 uniqtranscale_reg_value
= 0x55ADDA3A;
3060 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3061 uniqtranscale_reg_value
, 0);
3066 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3068 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3069 u32 deemph_reg_value
, margin_reg_value
;
3070 bool uniq_trans_scale
= false;
3071 uint8_t train_set
= intel_dp
->train_set
[0];
3073 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3074 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3075 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3077 deemph_reg_value
= 128;
3078 margin_reg_value
= 52;
3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3081 deemph_reg_value
= 128;
3082 margin_reg_value
= 77;
3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3085 deemph_reg_value
= 128;
3086 margin_reg_value
= 102;
3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3089 deemph_reg_value
= 128;
3090 margin_reg_value
= 154;
3091 uniq_trans_scale
= true;
3097 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3098 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3100 deemph_reg_value
= 85;
3101 margin_reg_value
= 78;
3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3104 deemph_reg_value
= 85;
3105 margin_reg_value
= 116;
3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3108 deemph_reg_value
= 85;
3109 margin_reg_value
= 154;
3115 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3116 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3118 deemph_reg_value
= 64;
3119 margin_reg_value
= 104;
3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3122 deemph_reg_value
= 64;
3123 margin_reg_value
= 154;
3129 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3130 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3132 deemph_reg_value
= 43;
3133 margin_reg_value
= 154;
3143 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3144 margin_reg_value
, uniq_trans_scale
);
3150 gen4_signal_levels(uint8_t train_set
)
3152 uint32_t signal_levels
= 0;
3154 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3157 signal_levels
|= DP_VOLTAGE_0_4
;
3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3160 signal_levels
|= DP_VOLTAGE_0_6
;
3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3163 signal_levels
|= DP_VOLTAGE_0_8
;
3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3166 signal_levels
|= DP_VOLTAGE_1_2
;
3169 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3170 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3172 signal_levels
|= DP_PRE_EMPHASIS_0
;
3174 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3175 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3177 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3178 signal_levels
|= DP_PRE_EMPHASIS_6
;
3180 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3181 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3184 return signal_levels
;
3187 /* Gen6's DP voltage swing and pre-emphasis control */
3189 gen6_edp_signal_levels(uint8_t train_set
)
3191 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3192 DP_TRAIN_PRE_EMPHASIS_MASK
);
3193 switch (signal_levels
) {
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3196 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3198 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3201 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3204 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3207 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3209 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3210 "0x%x\n", signal_levels
);
3211 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3215 /* Gen7's DP voltage swing and pre-emphasis control */
3217 gen7_edp_signal_levels(uint8_t train_set
)
3219 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3220 DP_TRAIN_PRE_EMPHASIS_MASK
);
3221 switch (signal_levels
) {
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3223 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3225 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3227 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3230 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3232 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3235 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3237 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3240 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3241 "0x%x\n", signal_levels
);
3242 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3247 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3249 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3250 enum port port
= intel_dig_port
->port
;
3251 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3252 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3253 uint32_t signal_levels
, mask
= 0;
3254 uint8_t train_set
= intel_dp
->train_set
[0];
3257 signal_levels
= ddi_signal_levels(intel_dp
);
3259 if (IS_BROXTON(dev
))
3262 mask
= DDI_BUF_EMP_MASK
;
3263 } else if (IS_CHERRYVIEW(dev
)) {
3264 signal_levels
= chv_signal_levels(intel_dp
);
3265 } else if (IS_VALLEYVIEW(dev
)) {
3266 signal_levels
= vlv_signal_levels(intel_dp
);
3267 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3268 signal_levels
= gen7_edp_signal_levels(train_set
);
3269 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3270 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3271 signal_levels
= gen6_edp_signal_levels(train_set
);
3272 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3274 signal_levels
= gen4_signal_levels(train_set
);
3275 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3279 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3281 DRM_DEBUG_KMS("Using vswing level %d\n",
3282 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3283 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3284 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3285 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3287 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3289 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3290 POSTING_READ(intel_dp
->output_reg
);
3294 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3295 uint8_t dp_train_pat
)
3297 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3298 struct drm_i915_private
*dev_priv
=
3299 to_i915(intel_dig_port
->base
.base
.dev
);
3301 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3303 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3304 POSTING_READ(intel_dp
->output_reg
);
3307 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3309 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3310 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3312 enum port port
= intel_dig_port
->port
;
3318 val
= I915_READ(DP_TP_CTL(port
));
3319 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3320 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3321 I915_WRITE(DP_TP_CTL(port
), val
);
3324 * On PORT_A we can have only eDP in SST mode. There the only reason
3325 * we need to set idle transmission mode is to work around a HW issue
3326 * where we enable the pipe while not in idle link-training mode.
3327 * In this case there is requirement to wait for a minimum number of
3328 * idle patterns to be sent.
3333 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3335 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3339 intel_dp_link_down(struct intel_dp
*intel_dp
)
3341 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3342 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3343 enum port port
= intel_dig_port
->port
;
3344 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3346 uint32_t DP
= intel_dp
->DP
;
3348 if (WARN_ON(HAS_DDI(dev
)))
3351 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3354 DRM_DEBUG_KMS("\n");
3356 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3357 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3358 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3359 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3361 if (IS_CHERRYVIEW(dev
))
3362 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3364 DP
&= ~DP_LINK_TRAIN_MASK
;
3365 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3367 I915_WRITE(intel_dp
->output_reg
, DP
);
3368 POSTING_READ(intel_dp
->output_reg
);
3370 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3371 I915_WRITE(intel_dp
->output_reg
, DP
);
3372 POSTING_READ(intel_dp
->output_reg
);
3375 * HW workaround for IBX, we need to move the port
3376 * to transcoder A after disabling it to allow the
3377 * matching HDMI port to be enabled on transcoder A.
3379 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3381 * We get CPU/PCH FIFO underruns on the other pipe when
3382 * doing the workaround. Sweep them under the rug.
3384 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3385 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3387 /* always enable with pattern 1 (as per spec) */
3388 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3389 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3390 I915_WRITE(intel_dp
->output_reg
, DP
);
3391 POSTING_READ(intel_dp
->output_reg
);
3394 I915_WRITE(intel_dp
->output_reg
, DP
);
3395 POSTING_READ(intel_dp
->output_reg
);
3397 intel_wait_for_vblank_if_active(dev_priv
->dev
, PIPE_A
);
3398 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3399 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3402 msleep(intel_dp
->panel_power_down_delay
);
3408 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3410 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3411 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3414 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3415 sizeof(intel_dp
->dpcd
)) < 0)
3416 return false; /* aux transfer failed */
3418 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3420 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3421 return false; /* DPCD not present */
3423 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3424 &intel_dp
->sink_count
, 1) < 0)
3428 * Sink count can change between short pulse hpd hence
3429 * a member variable in intel_dp will track any changes
3430 * between short pulse interrupts.
3432 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3435 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3436 * a dongle is present but no display. Unless we require to know
3437 * if a dongle is present or not, we don't need to update
3438 * downstream port information. So, an early return here saves
3439 * time from performing other operations which are not required.
3441 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3444 /* Check if the panel supports PSR */
3445 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3446 if (is_edp(intel_dp
)) {
3447 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3449 sizeof(intel_dp
->psr_dpcd
));
3450 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3451 dev_priv
->psr
.sink_support
= true;
3452 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3455 if (INTEL_INFO(dev
)->gen
>= 9 &&
3456 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3457 uint8_t frame_sync_cap
;
3459 dev_priv
->psr
.sink_support
= true;
3460 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3461 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3462 &frame_sync_cap
, 1);
3463 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3464 /* PSR2 needs frame sync as well */
3465 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3466 DRM_DEBUG_KMS("PSR2 %s on sink",
3467 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3470 /* Read the eDP Display control capabilities registers */
3471 memset(intel_dp
->edp_dpcd
, 0, sizeof(intel_dp
->edp_dpcd
));
3472 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3473 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3474 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3475 sizeof(intel_dp
->edp_dpcd
)))
3476 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3477 intel_dp
->edp_dpcd
);
3480 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3481 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
3482 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
3484 /* Intermediate frequency support */
3485 if (is_edp(intel_dp
) && (intel_dp
->edp_dpcd
[0] >= 0x03)) { /* eDp v1.4 or higher */
3486 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3489 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3490 DP_SUPPORTED_LINK_RATES
,
3492 sizeof(sink_rates
));
3494 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3495 int val
= le16_to_cpu(sink_rates
[i
]);
3500 /* Value read is in kHz while drm clock is saved in deca-kHz */
3501 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3503 intel_dp
->num_sink_rates
= i
;
3506 intel_dp_print_rates(intel_dp
);
3508 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3509 DP_DWN_STRM_PORT_PRESENT
))
3510 return true; /* native DP sink */
3512 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3513 return true; /* no per-port downstream info */
3515 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3516 intel_dp
->downstream_ports
,
3517 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3518 return false; /* downstream port status fetch failed */
3524 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3528 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3531 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3532 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3533 buf
[0], buf
[1], buf
[2]);
3535 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3536 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3537 buf
[0], buf
[1], buf
[2]);
3541 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3545 if (!i915
.enable_dp_mst
)
3548 if (!intel_dp
->can_mst
)
3551 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3554 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3555 if (buf
[0] & DP_MST_CAP
) {
3556 DRM_DEBUG_KMS("Sink is MST capable\n");
3557 intel_dp
->is_mst
= true;
3559 DRM_DEBUG_KMS("Sink is not MST capable\n");
3560 intel_dp
->is_mst
= false;
3564 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3565 return intel_dp
->is_mst
;
3568 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3570 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3571 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3572 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3578 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3579 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3584 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3585 buf
& ~DP_TEST_SINK_START
) < 0) {
3586 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3592 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3594 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3595 DP_TEST_SINK_MISC
, &buf
) < 0) {
3599 count
= buf
& DP_TEST_COUNT_MASK
;
3600 } while (--attempts
&& count
);
3602 if (attempts
== 0) {
3603 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3608 hsw_enable_ips(intel_crtc
);
3612 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3614 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3615 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3616 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3620 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3623 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3626 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3629 if (buf
& DP_TEST_SINK_START
) {
3630 ret
= intel_dp_sink_crc_stop(intel_dp
);
3635 hsw_disable_ips(intel_crtc
);
3637 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3638 buf
| DP_TEST_SINK_START
) < 0) {
3639 hsw_enable_ips(intel_crtc
);
3643 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3647 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3649 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3650 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3651 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3656 ret
= intel_dp_sink_crc_start(intel_dp
);
3661 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3663 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3664 DP_TEST_SINK_MISC
, &buf
) < 0) {
3668 count
= buf
& DP_TEST_COUNT_MASK
;
3670 } while (--attempts
&& count
== 0);
3672 if (attempts
== 0) {
3673 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3678 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3684 intel_dp_sink_crc_stop(intel_dp
);
3689 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3691 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3692 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3693 sink_irq_vector
, 1) == 1;
3697 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3701 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3703 sink_irq_vector
, 14);
3710 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3712 uint8_t test_result
= DP_TEST_ACK
;
3716 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3718 uint8_t test_result
= DP_TEST_NAK
;
3722 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3724 uint8_t test_result
= DP_TEST_NAK
;
3725 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3726 struct drm_connector
*connector
= &intel_connector
->base
;
3728 if (intel_connector
->detect_edid
== NULL
||
3729 connector
->edid_corrupt
||
3730 intel_dp
->aux
.i2c_defer_count
> 6) {
3731 /* Check EDID read for NACKs, DEFERs and corruption
3732 * (DP CTS 1.2 Core r1.1)
3733 * 4.2.2.4 : Failed EDID read, I2C_NAK
3734 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3735 * 4.2.2.6 : EDID corruption detected
3736 * Use failsafe mode for all cases
3738 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3739 intel_dp
->aux
.i2c_defer_count
> 0)
3740 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3741 intel_dp
->aux
.i2c_nack_count
,
3742 intel_dp
->aux
.i2c_defer_count
);
3743 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3745 struct edid
*block
= intel_connector
->detect_edid
;
3747 /* We have to write the checksum
3748 * of the last block read
3750 block
+= intel_connector
->detect_edid
->extensions
;
3752 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3753 DP_TEST_EDID_CHECKSUM
,
3756 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3758 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3759 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3762 /* Set test active flag here so userspace doesn't interrupt things */
3763 intel_dp
->compliance_test_active
= 1;
3768 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3770 uint8_t test_result
= DP_TEST_NAK
;
3774 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3776 uint8_t response
= DP_TEST_NAK
;
3780 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3782 DRM_DEBUG_KMS("Could not read test request from sink\n");
3787 case DP_TEST_LINK_TRAINING
:
3788 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3789 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3790 response
= intel_dp_autotest_link_training(intel_dp
);
3792 case DP_TEST_LINK_VIDEO_PATTERN
:
3793 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3794 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3795 response
= intel_dp_autotest_video_pattern(intel_dp
);
3797 case DP_TEST_LINK_EDID_READ
:
3798 DRM_DEBUG_KMS("EDID test requested\n");
3799 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3800 response
= intel_dp_autotest_edid(intel_dp
);
3802 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3803 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3804 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3805 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3808 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3813 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3817 DRM_DEBUG_KMS("Could not write test response to sink\n");
3821 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3825 if (intel_dp
->is_mst
) {
3830 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3834 /* check link status - esi[10] = 0x200c */
3835 if (intel_dp
->active_mst_links
&&
3836 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3837 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3838 intel_dp_start_link_train(intel_dp
);
3839 intel_dp_stop_link_train(intel_dp
);
3842 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3843 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3846 for (retry
= 0; retry
< 3; retry
++) {
3848 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3849 DP_SINK_COUNT_ESI
+1,
3856 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3858 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3866 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3867 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3868 intel_dp
->is_mst
= false;
3869 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3870 /* send a hotplug event */
3871 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3878 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3880 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3881 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3882 u8 link_status
[DP_LINK_STATUS_SIZE
];
3884 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3886 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3887 DRM_ERROR("Failed to get link status\n");
3891 if (!intel_encoder
->base
.crtc
)
3894 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3897 /* if link training is requested we should perform it always */
3898 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
3899 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
3900 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3901 intel_encoder
->base
.name
);
3902 intel_dp_start_link_train(intel_dp
);
3903 intel_dp_stop_link_train(intel_dp
);
3908 * According to DP spec
3911 * 2. Configure link according to Receiver Capabilities
3912 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3913 * 4. Check link status on receipt of hot-plug interrupt
3915 * intel_dp_short_pulse - handles short pulse interrupts
3916 * when full detection is not required.
3917 * Returns %true if short pulse is handled and full detection
3918 * is NOT required and %false otherwise.
3921 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
3923 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3925 u8 old_sink_count
= intel_dp
->sink_count
;
3929 * Clearing compliance test variables to allow capturing
3930 * of values for next automated test request.
3932 intel_dp
->compliance_test_active
= 0;
3933 intel_dp
->compliance_test_type
= 0;
3934 intel_dp
->compliance_test_data
= 0;
3937 * Now read the DPCD to see if it's actually running
3938 * If the current value of sink count doesn't match with
3939 * the value that was stored earlier or dpcd read failed
3940 * we need to do full detection
3942 ret
= intel_dp_get_dpcd(intel_dp
);
3944 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
3945 /* No need to proceed if we are going to do full detect */
3949 /* Try to read the source of the interrupt */
3950 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3951 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3952 /* Clear interrupt source */
3953 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3954 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3957 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3958 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3959 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3960 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3963 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
3964 intel_dp_check_link_status(intel_dp
);
3965 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
3970 /* XXX this is probably wrong for multiple downstream ports */
3971 static enum drm_connector_status
3972 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3974 uint8_t *dpcd
= intel_dp
->dpcd
;
3977 if (!intel_dp_get_dpcd(intel_dp
))
3978 return connector_status_disconnected
;
3980 if (is_edp(intel_dp
))
3981 return connector_status_connected
;
3983 /* if there's no downstream port, we're done */
3984 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3985 return connector_status_connected
;
3987 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3988 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3989 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3991 return intel_dp
->sink_count
?
3992 connector_status_connected
: connector_status_disconnected
;
3995 /* If no HPD, poke DDC gently */
3996 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3997 return connector_status_connected
;
3999 /* Well we tried, say unknown for unreliable port types */
4000 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4001 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4002 if (type
== DP_DS_PORT_TYPE_VGA
||
4003 type
== DP_DS_PORT_TYPE_NON_EDID
)
4004 return connector_status_unknown
;
4006 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4007 DP_DWN_STRM_PORT_TYPE_MASK
;
4008 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4009 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4010 return connector_status_unknown
;
4013 /* Anything else is out of spec, warn and ignore */
4014 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4015 return connector_status_disconnected
;
4018 static enum drm_connector_status
4019 edp_detect(struct intel_dp
*intel_dp
)
4021 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4022 enum drm_connector_status status
;
4024 status
= intel_panel_detect(dev
);
4025 if (status
== connector_status_unknown
)
4026 status
= connector_status_connected
;
4031 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4032 struct intel_digital_port
*port
)
4036 switch (port
->port
) {
4040 bit
= SDE_PORTB_HOTPLUG
;
4043 bit
= SDE_PORTC_HOTPLUG
;
4046 bit
= SDE_PORTD_HOTPLUG
;
4049 MISSING_CASE(port
->port
);
4053 return I915_READ(SDEISR
) & bit
;
4056 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4057 struct intel_digital_port
*port
)
4061 switch (port
->port
) {
4065 bit
= SDE_PORTB_HOTPLUG_CPT
;
4068 bit
= SDE_PORTC_HOTPLUG_CPT
;
4071 bit
= SDE_PORTD_HOTPLUG_CPT
;
4074 bit
= SDE_PORTE_HOTPLUG_SPT
;
4077 MISSING_CASE(port
->port
);
4081 return I915_READ(SDEISR
) & bit
;
4084 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4085 struct intel_digital_port
*port
)
4089 switch (port
->port
) {
4091 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4094 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4097 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4100 MISSING_CASE(port
->port
);
4104 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4107 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4108 struct intel_digital_port
*port
)
4112 switch (port
->port
) {
4114 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4117 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4120 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4123 MISSING_CASE(port
->port
);
4127 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4130 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4131 struct intel_digital_port
*intel_dig_port
)
4133 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4137 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4140 bit
= BXT_DE_PORT_HP_DDIA
;
4143 bit
= BXT_DE_PORT_HP_DDIB
;
4146 bit
= BXT_DE_PORT_HP_DDIC
;
4153 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4157 * intel_digital_port_connected - is the specified port connected?
4158 * @dev_priv: i915 private structure
4159 * @port: the port to test
4161 * Return %true if @port is connected, %false otherwise.
4163 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4164 struct intel_digital_port
*port
)
4166 if (HAS_PCH_IBX(dev_priv
))
4167 return ibx_digital_port_connected(dev_priv
, port
);
4168 else if (HAS_PCH_SPLIT(dev_priv
))
4169 return cpt_digital_port_connected(dev_priv
, port
);
4170 else if (IS_BROXTON(dev_priv
))
4171 return bxt_digital_port_connected(dev_priv
, port
);
4172 else if (IS_GM45(dev_priv
))
4173 return gm45_digital_port_connected(dev_priv
, port
);
4175 return g4x_digital_port_connected(dev_priv
, port
);
4178 static struct edid
*
4179 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4181 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4183 /* use cached edid if we have one */
4184 if (intel_connector
->edid
) {
4186 if (IS_ERR(intel_connector
->edid
))
4189 return drm_edid_duplicate(intel_connector
->edid
);
4191 return drm_get_edid(&intel_connector
->base
,
4192 &intel_dp
->aux
.ddc
);
4196 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4198 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4201 intel_dp_unset_edid(intel_dp
);
4202 edid
= intel_dp_get_edid(intel_dp
);
4203 intel_connector
->detect_edid
= edid
;
4205 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4206 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4208 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4212 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4214 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4216 kfree(intel_connector
->detect_edid
);
4217 intel_connector
->detect_edid
= NULL
;
4219 intel_dp
->has_audio
= false;
4223 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4225 struct drm_connector
*connector
= &intel_connector
->base
;
4226 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4227 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4228 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4229 struct drm_device
*dev
= connector
->dev
;
4230 enum drm_connector_status status
;
4231 enum intel_display_power_domain power_domain
;
4235 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4236 intel_display_power_get(to_i915(dev
), power_domain
);
4238 /* Can't disconnect eDP, but you can close the lid... */
4239 if (is_edp(intel_dp
))
4240 status
= edp_detect(intel_dp
);
4241 else if (intel_digital_port_connected(to_i915(dev
),
4242 dp_to_dig_port(intel_dp
)))
4243 status
= intel_dp_detect_dpcd(intel_dp
);
4245 status
= connector_status_disconnected
;
4247 if (status
!= connector_status_connected
) {
4248 intel_dp
->compliance_test_active
= 0;
4249 intel_dp
->compliance_test_type
= 0;
4250 intel_dp
->compliance_test_data
= 0;
4252 if (intel_dp
->is_mst
) {
4253 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4255 intel_dp
->mst_mgr
.mst_state
);
4256 intel_dp
->is_mst
= false;
4257 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4264 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4265 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4267 intel_dp_probe_oui(intel_dp
);
4269 ret
= intel_dp_probe_mst(intel_dp
);
4272 * If we are in MST mode then this connector
4273 * won't appear connected or have anything
4276 status
= connector_status_disconnected
;
4278 } else if (connector
->status
== connector_status_connected
) {
4280 * If display was connected already and is still connected
4281 * check links status, there has been known issues of
4282 * link loss triggerring long pulse!!!!
4284 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4285 intel_dp_check_link_status(intel_dp
);
4286 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4291 * Clearing NACK and defer counts to get their exact values
4292 * while reading EDID which are required by Compliance tests
4293 * 4.2.2.4 and 4.2.2.5
4295 intel_dp
->aux
.i2c_nack_count
= 0;
4296 intel_dp
->aux
.i2c_defer_count
= 0;
4298 intel_dp_set_edid(intel_dp
);
4300 status
= connector_status_connected
;
4301 intel_dp
->detect_done
= true;
4303 /* Try to read the source of the interrupt */
4304 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4305 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4306 /* Clear interrupt source */
4307 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4308 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4311 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4312 intel_dp_handle_test_request(intel_dp
);
4313 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4314 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4318 if ((status
!= connector_status_connected
) &&
4319 (intel_dp
->is_mst
== false))
4320 intel_dp_unset_edid(intel_dp
);
4322 intel_display_power_put(to_i915(dev
), power_domain
);
4326 static enum drm_connector_status
4327 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4329 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4330 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4331 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4332 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4334 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4335 connector
->base
.id
, connector
->name
);
4337 if (intel_dp
->is_mst
) {
4338 /* MST devices are disconnected from a monitor POV */
4339 intel_dp_unset_edid(intel_dp
);
4340 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4341 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4342 return connector_status_disconnected
;
4345 /* If full detect is not performed yet, do a full detect */
4346 if (!intel_dp
->detect_done
)
4347 intel_dp_long_pulse(intel_dp
->attached_connector
);
4349 intel_dp
->detect_done
= false;
4351 if (intel_connector
->detect_edid
)
4352 return connector_status_connected
;
4354 return connector_status_disconnected
;
4358 intel_dp_force(struct drm_connector
*connector
)
4360 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4361 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4362 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4363 enum intel_display_power_domain power_domain
;
4365 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4366 connector
->base
.id
, connector
->name
);
4367 intel_dp_unset_edid(intel_dp
);
4369 if (connector
->status
!= connector_status_connected
)
4372 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4373 intel_display_power_get(dev_priv
, power_domain
);
4375 intel_dp_set_edid(intel_dp
);
4377 intel_display_power_put(dev_priv
, power_domain
);
4379 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4380 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4383 static int intel_dp_get_modes(struct drm_connector
*connector
)
4385 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4388 edid
= intel_connector
->detect_edid
;
4390 int ret
= intel_connector_update_modes(connector
, edid
);
4395 /* if eDP has no EDID, fall back to fixed mode */
4396 if (is_edp(intel_attached_dp(connector
)) &&
4397 intel_connector
->panel
.fixed_mode
) {
4398 struct drm_display_mode
*mode
;
4400 mode
= drm_mode_duplicate(connector
->dev
,
4401 intel_connector
->panel
.fixed_mode
);
4403 drm_mode_probed_add(connector
, mode
);
4412 intel_dp_detect_audio(struct drm_connector
*connector
)
4414 bool has_audio
= false;
4417 edid
= to_intel_connector(connector
)->detect_edid
;
4419 has_audio
= drm_detect_monitor_audio(edid
);
4425 intel_dp_set_property(struct drm_connector
*connector
,
4426 struct drm_property
*property
,
4429 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4430 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4431 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4432 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4435 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4439 if (property
== dev_priv
->force_audio_property
) {
4443 if (i
== intel_dp
->force_audio
)
4446 intel_dp
->force_audio
= i
;
4448 if (i
== HDMI_AUDIO_AUTO
)
4449 has_audio
= intel_dp_detect_audio(connector
);
4451 has_audio
= (i
== HDMI_AUDIO_ON
);
4453 if (has_audio
== intel_dp
->has_audio
)
4456 intel_dp
->has_audio
= has_audio
;
4460 if (property
== dev_priv
->broadcast_rgb_property
) {
4461 bool old_auto
= intel_dp
->color_range_auto
;
4462 bool old_range
= intel_dp
->limited_color_range
;
4465 case INTEL_BROADCAST_RGB_AUTO
:
4466 intel_dp
->color_range_auto
= true;
4468 case INTEL_BROADCAST_RGB_FULL
:
4469 intel_dp
->color_range_auto
= false;
4470 intel_dp
->limited_color_range
= false;
4472 case INTEL_BROADCAST_RGB_LIMITED
:
4473 intel_dp
->color_range_auto
= false;
4474 intel_dp
->limited_color_range
= true;
4480 if (old_auto
== intel_dp
->color_range_auto
&&
4481 old_range
== intel_dp
->limited_color_range
)
4487 if (is_edp(intel_dp
) &&
4488 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4489 if (val
== DRM_MODE_SCALE_NONE
) {
4490 DRM_DEBUG_KMS("no scaling not supported\n");
4493 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4494 val
== DRM_MODE_SCALE_CENTER
) {
4495 DRM_DEBUG_KMS("centering not supported\n");
4499 if (intel_connector
->panel
.fitting_mode
== val
) {
4500 /* the eDP scaling property is not changed */
4503 intel_connector
->panel
.fitting_mode
= val
;
4511 if (intel_encoder
->base
.crtc
)
4512 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4518 intel_dp_connector_destroy(struct drm_connector
*connector
)
4520 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4522 kfree(intel_connector
->detect_edid
);
4524 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4525 kfree(intel_connector
->edid
);
4527 /* Can't call is_edp() since the encoder may have been destroyed
4529 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4530 intel_panel_fini(&intel_connector
->panel
);
4532 drm_connector_cleanup(connector
);
4536 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4538 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4539 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4541 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4542 if (is_edp(intel_dp
)) {
4543 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4545 * vdd might still be enabled do to the delayed vdd off.
4546 * Make sure vdd is actually turned off here.
4549 edp_panel_vdd_off_sync(intel_dp
);
4550 pps_unlock(intel_dp
);
4552 if (intel_dp
->edp_notifier
.notifier_call
) {
4553 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4554 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4557 drm_encoder_cleanup(encoder
);
4558 kfree(intel_dig_port
);
4561 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4563 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4565 if (!is_edp(intel_dp
))
4569 * vdd might still be enabled do to the delayed vdd off.
4570 * Make sure vdd is actually turned off here.
4572 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4574 edp_panel_vdd_off_sync(intel_dp
);
4575 pps_unlock(intel_dp
);
4578 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4580 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4581 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4583 enum intel_display_power_domain power_domain
;
4585 lockdep_assert_held(&dev_priv
->pps_mutex
);
4587 if (!edp_have_panel_vdd(intel_dp
))
4591 * The VDD bit needs a power domain reference, so if the bit is
4592 * already enabled when we boot or resume, grab this reference and
4593 * schedule a vdd off, so we don't hold on to the reference
4596 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4597 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4598 intel_display_power_get(dev_priv
, power_domain
);
4600 edp_panel_vdd_schedule_off(intel_dp
);
4603 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4605 struct intel_dp
*intel_dp
;
4607 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4610 intel_dp
= enc_to_intel_dp(encoder
);
4615 * Read out the current power sequencer assignment,
4616 * in case the BIOS did something with it.
4618 if (IS_VALLEYVIEW(encoder
->dev
) || IS_CHERRYVIEW(encoder
->dev
))
4619 vlv_initial_power_sequencer_setup(intel_dp
);
4621 intel_edp_panel_vdd_sanitize(intel_dp
);
4623 pps_unlock(intel_dp
);
4626 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4627 .dpms
= drm_atomic_helper_connector_dpms
,
4628 .detect
= intel_dp_detect
,
4629 .force
= intel_dp_force
,
4630 .fill_modes
= drm_helper_probe_single_connector_modes
,
4631 .set_property
= intel_dp_set_property
,
4632 .atomic_get_property
= intel_connector_atomic_get_property
,
4633 .destroy
= intel_dp_connector_destroy
,
4634 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4635 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4638 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4639 .get_modes
= intel_dp_get_modes
,
4640 .mode_valid
= intel_dp_mode_valid
,
4641 .best_encoder
= intel_best_encoder
,
4644 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4645 .reset
= intel_dp_encoder_reset
,
4646 .destroy
= intel_dp_encoder_destroy
,
4650 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4652 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4653 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4654 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4656 enum intel_display_power_domain power_domain
;
4657 enum irqreturn ret
= IRQ_NONE
;
4659 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4660 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4661 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4663 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4665 * vdd off can generate a long pulse on eDP which
4666 * would require vdd on to handle it, and thus we
4667 * would end up in an endless cycle of
4668 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4670 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4671 port_name(intel_dig_port
->port
));
4675 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4676 port_name(intel_dig_port
->port
),
4677 long_hpd
? "long" : "short");
4679 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4680 intel_display_power_get(dev_priv
, power_domain
);
4683 /* indicate that we need to restart link training */
4684 intel_dp
->train_set_valid
= false;
4686 intel_dp_long_pulse(intel_dp
->attached_connector
);
4687 if (intel_dp
->is_mst
)
4692 if (intel_dp
->is_mst
) {
4693 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4695 * If we were in MST mode, and device is not
4696 * there, get out of MST mode
4698 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4699 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4700 intel_dp
->is_mst
= false;
4701 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4707 if (!intel_dp
->is_mst
) {
4708 if (!intel_dp_short_pulse(intel_dp
)) {
4709 intel_dp_long_pulse(intel_dp
->attached_connector
);
4718 intel_display_power_put(dev_priv
, power_domain
);
4723 /* check the VBT to see whether the eDP is on another port */
4724 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4729 * eDP not supported on g4x. so bail out early just
4730 * for a bit extra safety in case the VBT is bonkers.
4732 if (INTEL_INFO(dev
)->gen
< 5)
4738 return intel_bios_is_port_edp(dev_priv
, port
);
4742 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4744 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4746 intel_attach_force_audio_property(connector
);
4747 intel_attach_broadcast_rgb_property(connector
);
4748 intel_dp
->color_range_auto
= true;
4750 if (is_edp(intel_dp
)) {
4751 drm_mode_create_scaling_mode_property(connector
->dev
);
4752 drm_object_attach_property(
4754 connector
->dev
->mode_config
.scaling_mode_property
,
4755 DRM_MODE_SCALE_ASPECT
);
4756 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4760 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4762 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4763 intel_dp
->last_power_on
= jiffies
;
4764 intel_dp
->last_backlight_off
= jiffies
;
4768 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4769 struct intel_dp
*intel_dp
)
4771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4772 struct edp_power_seq cur
, vbt
, spec
,
4773 *final
= &intel_dp
->pps_delays
;
4774 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4775 i915_reg_t pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4777 lockdep_assert_held(&dev_priv
->pps_mutex
);
4779 /* already initialized? */
4780 if (final
->t11_t12
!= 0)
4783 if (IS_BROXTON(dev
)) {
4785 * TODO: BXT has 2 sets of PPS registers.
4786 * Correct Register for Broxton need to be identified
4787 * using VBT. hardcoding for now
4789 pp_ctrl_reg
= BXT_PP_CONTROL(0);
4790 pp_on_reg
= BXT_PP_ON_DELAYS(0);
4791 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
4792 } else if (HAS_PCH_SPLIT(dev
)) {
4793 pp_ctrl_reg
= PCH_PP_CONTROL
;
4794 pp_on_reg
= PCH_PP_ON_DELAYS
;
4795 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4796 pp_div_reg
= PCH_PP_DIVISOR
;
4798 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4800 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4801 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4802 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4803 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4806 /* Workaround: Need to write PP_CONTROL with the unlock key as
4807 * the very first thing. */
4808 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4810 pp_on
= I915_READ(pp_on_reg
);
4811 pp_off
= I915_READ(pp_off_reg
);
4812 if (!IS_BROXTON(dev
)) {
4813 I915_WRITE(pp_ctrl_reg
, pp_ctl
);
4814 pp_div
= I915_READ(pp_div_reg
);
4817 /* Pull timing values out of registers */
4818 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4819 PANEL_POWER_UP_DELAY_SHIFT
;
4821 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4822 PANEL_LIGHT_ON_DELAY_SHIFT
;
4824 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4825 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4827 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4828 PANEL_POWER_DOWN_DELAY_SHIFT
;
4830 if (IS_BROXTON(dev
)) {
4831 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4832 BXT_POWER_CYCLE_DELAY_SHIFT
;
4834 cur
.t11_t12
= (tmp
- 1) * 1000;
4838 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4839 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4842 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4843 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4845 vbt
= dev_priv
->vbt
.edp
.pps
;
4847 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4848 * our hw here, which are all in 100usec. */
4849 spec
.t1_t3
= 210 * 10;
4850 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4851 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4852 spec
.t10
= 500 * 10;
4853 /* This one is special and actually in units of 100ms, but zero
4854 * based in the hw (so we need to add 100 ms). But the sw vbt
4855 * table multiplies it with 1000 to make it in units of 100usec,
4857 spec
.t11_t12
= (510 + 100) * 10;
4859 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4860 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4862 /* Use the max of the register settings and vbt. If both are
4863 * unset, fall back to the spec limits. */
4864 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4866 max(cur.field, vbt.field))
4867 assign_final(t1_t3
);
4871 assign_final(t11_t12
);
4874 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4875 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4876 intel_dp
->backlight_on_delay
= get_delay(t8
);
4877 intel_dp
->backlight_off_delay
= get_delay(t9
);
4878 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4879 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4882 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4883 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4884 intel_dp
->panel_power_cycle_delay
);
4886 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4887 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4891 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4892 struct intel_dp
*intel_dp
)
4894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4895 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4896 int div
= dev_priv
->rawclk_freq
/ 1000;
4897 i915_reg_t pp_on_reg
, pp_off_reg
, pp_div_reg
, pp_ctrl_reg
;
4898 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4899 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4901 lockdep_assert_held(&dev_priv
->pps_mutex
);
4903 if (IS_BROXTON(dev
)) {
4905 * TODO: BXT has 2 sets of PPS registers.
4906 * Correct Register for Broxton need to be identified
4907 * using VBT. hardcoding for now
4909 pp_ctrl_reg
= BXT_PP_CONTROL(0);
4910 pp_on_reg
= BXT_PP_ON_DELAYS(0);
4911 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
4913 } else if (HAS_PCH_SPLIT(dev
)) {
4914 pp_on_reg
= PCH_PP_ON_DELAYS
;
4915 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4916 pp_div_reg
= PCH_PP_DIVISOR
;
4918 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4920 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4921 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4922 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4926 * And finally store the new values in the power sequencer. The
4927 * backlight delays are set to 1 because we do manual waits on them. For
4928 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4929 * we'll end up waiting for the backlight off delay twice: once when we
4930 * do the manual sleep, and once when we disable the panel and wait for
4931 * the PP_STATUS bit to become zero.
4933 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4934 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4935 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4936 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4937 /* Compute the divisor for the pp clock, simply match the Bspec
4939 if (IS_BROXTON(dev
)) {
4940 pp_div
= I915_READ(pp_ctrl_reg
);
4941 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
4942 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
4943 << BXT_POWER_CYCLE_DELAY_SHIFT
);
4945 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4946 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4947 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4950 /* Haswell doesn't have any port selection bits for the panel
4951 * power sequencer any more. */
4952 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
4953 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4954 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4956 port_sel
= PANEL_PORT_SELECT_DPA
;
4958 port_sel
= PANEL_PORT_SELECT_DPD
;
4963 I915_WRITE(pp_on_reg
, pp_on
);
4964 I915_WRITE(pp_off_reg
, pp_off
);
4965 if (IS_BROXTON(dev
))
4966 I915_WRITE(pp_ctrl_reg
, pp_div
);
4968 I915_WRITE(pp_div_reg
, pp_div
);
4970 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4971 I915_READ(pp_on_reg
),
4972 I915_READ(pp_off_reg
),
4974 (I915_READ(pp_ctrl_reg
) & BXT_POWER_CYCLE_DELAY_MASK
) :
4975 I915_READ(pp_div_reg
));
4979 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4981 * @refresh_rate: RR to be programmed
4983 * This function gets called when refresh rate (RR) has to be changed from
4984 * one frequency to another. Switches can be between high and low RR
4985 * supported by the panel or to any other RR based on media playback (in
4986 * this case, RR value needs to be passed from user space).
4988 * The caller of this function needs to take a lock on dev_priv->drrs.
4990 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4993 struct intel_encoder
*encoder
;
4994 struct intel_digital_port
*dig_port
= NULL
;
4995 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
4996 struct intel_crtc_state
*config
= NULL
;
4997 struct intel_crtc
*intel_crtc
= NULL
;
4998 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5000 if (refresh_rate
<= 0) {
5001 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5005 if (intel_dp
== NULL
) {
5006 DRM_DEBUG_KMS("DRRS not supported.\n");
5011 * FIXME: This needs proper synchronization with psr state for some
5012 * platforms that cannot have PSR and DRRS enabled at the same time.
5015 dig_port
= dp_to_dig_port(intel_dp
);
5016 encoder
= &dig_port
->base
;
5017 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5020 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5024 config
= intel_crtc
->config
;
5026 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5027 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5031 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5033 index
= DRRS_LOW_RR
;
5035 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5037 "DRRS requested for previously set RR...ignoring\n");
5041 if (!intel_crtc
->active
) {
5042 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5046 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5049 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5052 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5056 DRM_ERROR("Unsupported refreshrate type\n");
5058 } else if (INTEL_INFO(dev
)->gen
> 6) {
5059 i915_reg_t reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5062 val
= I915_READ(reg
);
5063 if (index
> DRRS_HIGH_RR
) {
5064 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5065 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5067 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5069 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5070 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5072 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5074 I915_WRITE(reg
, val
);
5077 dev_priv
->drrs
.refresh_rate_type
= index
;
5079 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5083 * intel_edp_drrs_enable - init drrs struct if supported
5084 * @intel_dp: DP struct
5086 * Initializes frontbuffer_bits and drrs.dp
5088 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5090 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5092 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5093 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5096 if (!intel_crtc
->config
->has_drrs
) {
5097 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5101 mutex_lock(&dev_priv
->drrs
.mutex
);
5102 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5103 DRM_ERROR("DRRS already enabled\n");
5107 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5109 dev_priv
->drrs
.dp
= intel_dp
;
5112 mutex_unlock(&dev_priv
->drrs
.mutex
);
5116 * intel_edp_drrs_disable - Disable DRRS
5117 * @intel_dp: DP struct
5120 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5122 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5124 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5125 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5128 if (!intel_crtc
->config
->has_drrs
)
5131 mutex_lock(&dev_priv
->drrs
.mutex
);
5132 if (!dev_priv
->drrs
.dp
) {
5133 mutex_unlock(&dev_priv
->drrs
.mutex
);
5137 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5138 intel_dp_set_drrs_state(dev_priv
->dev
,
5139 intel_dp
->attached_connector
->panel
.
5140 fixed_mode
->vrefresh
);
5142 dev_priv
->drrs
.dp
= NULL
;
5143 mutex_unlock(&dev_priv
->drrs
.mutex
);
5145 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5148 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5150 struct drm_i915_private
*dev_priv
=
5151 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5152 struct intel_dp
*intel_dp
;
5154 mutex_lock(&dev_priv
->drrs
.mutex
);
5156 intel_dp
= dev_priv
->drrs
.dp
;
5162 * The delayed work can race with an invalidate hence we need to
5166 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5169 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5170 intel_dp_set_drrs_state(dev_priv
->dev
,
5171 intel_dp
->attached_connector
->panel
.
5172 downclock_mode
->vrefresh
);
5175 mutex_unlock(&dev_priv
->drrs
.mutex
);
5179 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5181 * @frontbuffer_bits: frontbuffer plane tracking bits
5183 * This function gets called everytime rendering on the given planes start.
5184 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5186 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5188 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5189 unsigned frontbuffer_bits
)
5191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5192 struct drm_crtc
*crtc
;
5195 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5198 cancel_delayed_work(&dev_priv
->drrs
.work
);
5200 mutex_lock(&dev_priv
->drrs
.mutex
);
5201 if (!dev_priv
->drrs
.dp
) {
5202 mutex_unlock(&dev_priv
->drrs
.mutex
);
5206 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5207 pipe
= to_intel_crtc(crtc
)->pipe
;
5209 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5210 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5212 /* invalidate means busy screen hence upclock */
5213 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5214 intel_dp_set_drrs_state(dev_priv
->dev
,
5215 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5216 fixed_mode
->vrefresh
);
5218 mutex_unlock(&dev_priv
->drrs
.mutex
);
5222 * intel_edp_drrs_flush - Restart Idleness DRRS
5224 * @frontbuffer_bits: frontbuffer plane tracking bits
5226 * This function gets called every time rendering on the given planes has
5227 * completed or flip on a crtc is completed. So DRRS should be upclocked
5228 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5229 * if no other planes are dirty.
5231 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5233 void intel_edp_drrs_flush(struct drm_device
*dev
,
5234 unsigned frontbuffer_bits
)
5236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5237 struct drm_crtc
*crtc
;
5240 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5243 cancel_delayed_work(&dev_priv
->drrs
.work
);
5245 mutex_lock(&dev_priv
->drrs
.mutex
);
5246 if (!dev_priv
->drrs
.dp
) {
5247 mutex_unlock(&dev_priv
->drrs
.mutex
);
5251 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5252 pipe
= to_intel_crtc(crtc
)->pipe
;
5254 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5255 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5257 /* flush means busy screen hence upclock */
5258 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5259 intel_dp_set_drrs_state(dev_priv
->dev
,
5260 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5261 fixed_mode
->vrefresh
);
5264 * flush also means no more activity hence schedule downclock, if all
5265 * other fbs are quiescent too
5267 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5268 schedule_delayed_work(&dev_priv
->drrs
.work
,
5269 msecs_to_jiffies(1000));
5270 mutex_unlock(&dev_priv
->drrs
.mutex
);
5274 * DOC: Display Refresh Rate Switching (DRRS)
5276 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5277 * which enables swtching between low and high refresh rates,
5278 * dynamically, based on the usage scenario. This feature is applicable
5279 * for internal panels.
5281 * Indication that the panel supports DRRS is given by the panel EDID, which
5282 * would list multiple refresh rates for one resolution.
5284 * DRRS is of 2 types - static and seamless.
5285 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5286 * (may appear as a blink on screen) and is used in dock-undock scenario.
5287 * Seamless DRRS involves changing RR without any visual effect to the user
5288 * and can be used during normal system usage. This is done by programming
5289 * certain registers.
5291 * Support for static/seamless DRRS may be indicated in the VBT based on
5292 * inputs from the panel spec.
5294 * DRRS saves power by switching to low RR based on usage scenarios.
5297 * The implementation is based on frontbuffer tracking implementation.
5298 * When there is a disturbance on the screen triggered by user activity or a
5299 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5300 * When there is no movement on screen, after a timeout of 1 second, a switch
5301 * to low RR is made.
5302 * For integration with frontbuffer tracking code,
5303 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5305 * DRRS can be further extended to support other internal panels and also
5306 * the scenario of video playback wherein RR is set based on the rate
5307 * requested by userspace.
5311 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5312 * @intel_connector: eDP connector
5313 * @fixed_mode: preferred mode of panel
5315 * This function is called only once at driver load to initialize basic
5319 * Downclock mode if panel supports it, else return NULL.
5320 * DRRS support is determined by the presence of downclock mode (apart
5321 * from VBT setting).
5323 static struct drm_display_mode
*
5324 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5325 struct drm_display_mode
*fixed_mode
)
5327 struct drm_connector
*connector
= &intel_connector
->base
;
5328 struct drm_device
*dev
= connector
->dev
;
5329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5330 struct drm_display_mode
*downclock_mode
= NULL
;
5332 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5333 mutex_init(&dev_priv
->drrs
.mutex
);
5335 if (INTEL_INFO(dev
)->gen
<= 6) {
5336 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5340 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5341 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5345 downclock_mode
= intel_find_panel_downclock
5346 (dev
, fixed_mode
, connector
);
5348 if (!downclock_mode
) {
5349 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5353 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5355 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5356 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5357 return downclock_mode
;
5360 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5361 struct intel_connector
*intel_connector
)
5363 struct drm_connector
*connector
= &intel_connector
->base
;
5364 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5365 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5366 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5368 struct drm_display_mode
*fixed_mode
= NULL
;
5369 struct drm_display_mode
*downclock_mode
= NULL
;
5371 struct drm_display_mode
*scan
;
5373 enum pipe pipe
= INVALID_PIPE
;
5375 if (!is_edp(intel_dp
))
5379 intel_edp_panel_vdd_sanitize(intel_dp
);
5380 pps_unlock(intel_dp
);
5382 /* Cache DPCD and EDID for edp. */
5383 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5386 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5387 dev_priv
->no_aux_handshake
=
5388 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5389 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5391 /* if this fails, presume the device is a ghost */
5392 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5396 /* We now know it's not a ghost, init power sequence regs. */
5398 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5399 pps_unlock(intel_dp
);
5401 mutex_lock(&dev
->mode_config
.mutex
);
5402 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5404 if (drm_add_edid_modes(connector
, edid
)) {
5405 drm_mode_connector_update_edid_property(connector
,
5407 drm_edid_to_eld(connector
, edid
);
5410 edid
= ERR_PTR(-EINVAL
);
5413 edid
= ERR_PTR(-ENOENT
);
5415 intel_connector
->edid
= edid
;
5417 /* prefer fixed mode from EDID if available */
5418 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5419 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5420 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5421 downclock_mode
= intel_dp_drrs_init(
5422 intel_connector
, fixed_mode
);
5427 /* fallback to VBT if available for eDP */
5428 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5429 fixed_mode
= drm_mode_duplicate(dev
,
5430 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5432 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5434 mutex_unlock(&dev
->mode_config
.mutex
);
5436 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5437 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5438 register_reboot_notifier(&intel_dp
->edp_notifier
);
5441 * Figure out the current pipe for the initial backlight setup.
5442 * If the current pipe isn't valid, try the PPS pipe, and if that
5443 * fails just assume pipe A.
5445 if (IS_CHERRYVIEW(dev
))
5446 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5448 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5450 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5451 pipe
= intel_dp
->pps_pipe
;
5453 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5456 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5460 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5461 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5462 intel_panel_setup_backlight(connector
, pipe
);
5468 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5469 struct intel_connector
*intel_connector
)
5471 struct drm_connector
*connector
= &intel_connector
->base
;
5472 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5473 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5474 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5476 enum port port
= intel_dig_port
->port
;
5479 if (WARN(intel_dig_port
->max_lanes
< 1,
5480 "Not enough lanes (%d) for DP on port %c\n",
5481 intel_dig_port
->max_lanes
, port_name(port
)))
5484 intel_dp
->pps_pipe
= INVALID_PIPE
;
5486 /* intel_dp vfuncs */
5487 if (INTEL_INFO(dev
)->gen
>= 9)
5488 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5489 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5490 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5491 else if (HAS_PCH_SPLIT(dev
))
5492 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5494 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5496 if (INTEL_INFO(dev
)->gen
>= 9)
5497 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5499 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5502 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5504 /* Preserve the current hw state. */
5505 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5506 intel_dp
->attached_connector
= intel_connector
;
5508 if (intel_dp_is_edp(dev
, port
))
5509 type
= DRM_MODE_CONNECTOR_eDP
;
5511 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5514 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5515 * for DP the encoder type can be set by the caller to
5516 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5518 if (type
== DRM_MODE_CONNECTOR_eDP
)
5519 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5521 /* eDP only on port B and/or C on vlv/chv */
5522 if (WARN_ON((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
5523 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5526 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5527 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5530 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5531 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5533 connector
->interlace_allowed
= true;
5534 connector
->doublescan_allowed
= 0;
5536 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5537 edp_panel_vdd_work
);
5539 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5540 drm_connector_register(connector
);
5543 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5545 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5546 intel_connector
->unregister
= intel_dp_connector_unregister
;
5548 /* Set up the hotplug pin. */
5551 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5554 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5555 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5556 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5559 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5562 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5565 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5571 if (is_edp(intel_dp
)) {
5573 intel_dp_init_panel_power_timestamps(intel_dp
);
5574 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5575 vlv_initial_power_sequencer_setup(intel_dp
);
5577 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5578 pps_unlock(intel_dp
);
5581 ret
= intel_dp_aux_init(intel_dp
, intel_connector
);
5585 /* init MST on ports that can support it */
5586 if (HAS_DP_MST(dev
) &&
5587 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5588 intel_dp_mst_encoder_init(intel_dig_port
,
5589 intel_connector
->base
.base
.id
);
5591 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5592 intel_dp_aux_fini(intel_dp
);
5593 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5597 intel_dp_add_properties(intel_dp
, connector
);
5599 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5600 * 0xd. Failure to do so will result in spurious interrupts being
5601 * generated on the port when a cable is not attached.
5603 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5604 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5605 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5608 i915_debugfs_connector_add(connector
);
5613 if (is_edp(intel_dp
)) {
5614 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5616 * vdd might still be enabled do to the delayed vdd off.
5617 * Make sure vdd is actually turned off here.
5620 edp_panel_vdd_off_sync(intel_dp
);
5621 pps_unlock(intel_dp
);
5623 drm_connector_unregister(connector
);
5624 drm_connector_cleanup(connector
);
5630 intel_dp_init(struct drm_device
*dev
,
5631 i915_reg_t output_reg
, enum port port
)
5633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5634 struct intel_digital_port
*intel_dig_port
;
5635 struct intel_encoder
*intel_encoder
;
5636 struct drm_encoder
*encoder
;
5637 struct intel_connector
*intel_connector
;
5639 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5640 if (!intel_dig_port
)
5643 intel_connector
= intel_connector_alloc();
5644 if (!intel_connector
)
5645 goto err_connector_alloc
;
5647 intel_encoder
= &intel_dig_port
->base
;
5648 encoder
= &intel_encoder
->base
;
5650 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5651 DRM_MODE_ENCODER_TMDS
, NULL
))
5652 goto err_encoder_init
;
5654 intel_encoder
->compute_config
= intel_dp_compute_config
;
5655 intel_encoder
->disable
= intel_disable_dp
;
5656 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5657 intel_encoder
->get_config
= intel_dp_get_config
;
5658 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5659 if (IS_CHERRYVIEW(dev
)) {
5660 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5661 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5662 intel_encoder
->enable
= vlv_enable_dp
;
5663 intel_encoder
->post_disable
= chv_post_disable_dp
;
5664 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5665 } else if (IS_VALLEYVIEW(dev
)) {
5666 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5667 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5668 intel_encoder
->enable
= vlv_enable_dp
;
5669 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5671 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5672 intel_encoder
->enable
= g4x_enable_dp
;
5673 if (INTEL_INFO(dev
)->gen
>= 5)
5674 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5677 intel_dig_port
->port
= port
;
5678 intel_dig_port
->dp
.output_reg
= output_reg
;
5679 intel_dig_port
->max_lanes
= 4;
5681 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5682 if (IS_CHERRYVIEW(dev
)) {
5684 intel_encoder
->crtc_mask
= 1 << 2;
5686 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5688 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5690 intel_encoder
->cloneable
= 0;
5692 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5693 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5695 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5696 goto err_init_connector
;
5701 drm_encoder_cleanup(encoder
);
5703 kfree(intel_connector
);
5704 err_connector_alloc
:
5705 kfree(intel_dig_port
);
5710 void intel_dp_mst_suspend(struct drm_device
*dev
)
5712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5716 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5717 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5718 if (!intel_dig_port
)
5721 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5722 if (!intel_dig_port
->dp
.can_mst
)
5724 if (intel_dig_port
->dp
.is_mst
)
5725 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5730 void intel_dp_mst_resume(struct drm_device
*dev
)
5732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5735 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5736 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5737 if (!intel_dig_port
)
5739 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5742 if (!intel_dig_port
->dp
.can_mst
)
5745 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5747 intel_dp_check_mst_status(&intel_dig_port
->dp
);