2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp
*intel_dp
)
50 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
54 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
55 * @intel_dp: DP struct
57 * Returns true if the given DP struct corresponds to a PCH DP port attached
58 * to an eDP panel, false otherwise. Helpful for determining whether we
59 * may need FDI resources for a given DP output or not.
61 static bool is_pch_edp(struct intel_dp
*intel_dp
)
63 return intel_dp
->is_pch_edp
;
67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
68 * @intel_dp: DP struct
70 * Returns true if the given DP struct corresponds to a CPU eDP port.
72 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
74 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
77 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
79 return container_of(intel_attached_encoder(connector
),
80 struct intel_dp
, base
);
84 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
85 * @encoder: DRM encoder
87 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
90 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
92 struct intel_dp
*intel_dp
;
97 intel_dp
= enc_to_intel_dp(encoder
);
99 return is_pch_edp(intel_dp
);
102 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
105 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
106 int *lane_num
, int *link_bw
)
108 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
110 *lane_num
= intel_dp
->lane_count
;
111 *link_bw
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
115 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
116 struct drm_display_mode
*mode
)
118 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
119 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
121 if (intel_connector
->panel
.fixed_mode
)
122 return intel_connector
->panel
.fixed_mode
->clock
;
128 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
130 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
132 switch (max_link_bw
) {
133 case DP_LINK_BW_1_62
:
137 max_link_bw
= DP_LINK_BW_1_62
;
144 intel_dp_link_clock(uint8_t link_bw
)
146 if (link_bw
== DP_LINK_BW_2_7
)
153 * The units on the numbers in the next two are... bizarre. Examples will
154 * make it clearer; this one parallels an example in the eDP spec.
156 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
158 * 270000 * 1 * 8 / 10 == 216000
160 * The actual data capacity of that configuration is 2.16Gbit/s, so the
161 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
162 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
163 * 119000. At 18bpp that's 2142000 kilobits per second.
165 * Thus the strange-looking division by 10 in intel_dp_link_required, to
166 * get the result in decakilobits instead of kilobits.
170 intel_dp_link_required(int pixel_clock
, int bpp
)
172 return (pixel_clock
* bpp
+ 9) / 10;
176 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
178 return (max_link_clock
* max_lanes
* 8) / 10;
182 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
183 struct drm_display_mode
*mode
,
186 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
187 int max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
188 int max_rate
, mode_rate
;
190 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
191 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
193 if (mode_rate
> max_rate
) {
194 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
195 if (mode_rate
> max_rate
)
200 |= INTEL_MODE_DP_FORCE_6BPC
;
209 intel_dp_mode_valid(struct drm_connector
*connector
,
210 struct drm_display_mode
*mode
)
212 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
213 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
214 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
216 if (is_edp(intel_dp
) && fixed_mode
) {
217 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
220 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
224 if (!intel_dp_adjust_dithering(intel_dp
, mode
, false))
225 return MODE_CLOCK_HIGH
;
227 if (mode
->clock
< 10000)
228 return MODE_CLOCK_LOW
;
230 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
231 return MODE_H_ILLEGAL
;
237 pack_aux(uint8_t *src
, int src_bytes
)
244 for (i
= 0; i
< src_bytes
; i
++)
245 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
250 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
255 for (i
= 0; i
< dst_bytes
; i
++)
256 dst
[i
] = src
>> ((3-i
) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev
))
270 clkcfg
= I915_READ(CLKCFG
);
271 switch (clkcfg
& CLKCFG_FSB_MASK
) {
280 case CLKCFG_FSB_1067
:
282 case CLKCFG_FSB_1333
:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600
:
286 case CLKCFG_FSB_1600_ALT
:
293 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
295 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
301 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
303 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
310 intel_dp_check_edp(struct intel_dp
*intel_dp
)
312 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
315 if (!is_edp(intel_dp
))
317 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
320 I915_READ(PCH_PP_STATUS
),
321 I915_READ(PCH_PP_CONTROL
));
326 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
327 uint8_t *send
, int send_bytes
,
328 uint8_t *recv
, int recv_size
)
330 uint32_t output_reg
= intel_dp
->output_reg
;
331 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 uint32_t ch_ctl
= output_reg
+ 0x10;
334 uint32_t ch_data
= ch_ctl
+ 4;
338 uint32_t aux_clock_divider
;
341 if (IS_HASWELL(dev
)) {
342 switch (intel_dp
->port
) {
344 ch_ctl
= DPA_AUX_CH_CTL
;
345 ch_data
= DPA_AUX_CH_DATA1
;
348 ch_ctl
= PCH_DPB_AUX_CH_CTL
;
349 ch_data
= PCH_DPB_AUX_CH_DATA1
;
352 ch_ctl
= PCH_DPC_AUX_CH_CTL
;
353 ch_data
= PCH_DPC_AUX_CH_DATA1
;
356 ch_ctl
= PCH_DPD_AUX_CH_CTL
;
357 ch_data
= PCH_DPD_AUX_CH_DATA1
;
364 intel_dp_check_edp(intel_dp
);
365 /* The clock divider is based off the hrawclk,
366 * and would like to run at 2MHz. So, take the
367 * hrawclk value and divide by 2 and use that
369 * Note that PCH attached eDP panels should use a 125MHz input
372 if (is_cpu_edp(intel_dp
)) {
374 aux_clock_divider
= intel_ddi_get_cdclk_freq(dev_priv
) >> 1;
375 else if (IS_VALLEYVIEW(dev
))
376 aux_clock_divider
= 100;
377 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
378 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
380 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
381 } else if (HAS_PCH_SPLIT(dev
))
382 aux_clock_divider
= DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
384 aux_clock_divider
= intel_hrawclk(dev
) / 2;
391 /* Try to wait for any previous AUX channel activity */
392 for (try = 0; try < 3; try++) {
393 status
= I915_READ(ch_ctl
);
394 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
400 WARN(1, "dp_aux_ch not started status 0x%08x\n",
405 /* Must try at least 3 times according to DP spec */
406 for (try = 0; try < 5; try++) {
407 /* Load the send data into the aux channel data registers */
408 for (i
= 0; i
< send_bytes
; i
+= 4)
409 I915_WRITE(ch_data
+ i
,
410 pack_aux(send
+ i
, send_bytes
- i
));
412 /* Send the command and wait for it to complete */
414 DP_AUX_CH_CTL_SEND_BUSY
|
415 DP_AUX_CH_CTL_TIME_OUT_400us
|
416 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
417 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
418 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
420 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
421 DP_AUX_CH_CTL_RECEIVE_ERROR
);
423 status
= I915_READ(ch_ctl
);
424 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
429 /* Clear done status and any errors */
433 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
434 DP_AUX_CH_CTL_RECEIVE_ERROR
);
436 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
437 DP_AUX_CH_CTL_RECEIVE_ERROR
))
439 if (status
& DP_AUX_CH_CTL_DONE
)
443 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
444 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
448 /* Check for timeout or receive error.
449 * Timeouts occur when the sink is not connected
451 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
452 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
456 /* Timeouts occur when the device isn't connected, so they're
457 * "normal" -- don't fill the kernel log with these */
458 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
459 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
463 /* Unload any bytes sent back from the other side */
464 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
465 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
466 if (recv_bytes
> recv_size
)
467 recv_bytes
= recv_size
;
469 for (i
= 0; i
< recv_bytes
; i
+= 4)
470 unpack_aux(I915_READ(ch_data
+ i
),
471 recv
+ i
, recv_bytes
- i
);
476 /* Write data to the aux channel in native mode */
478 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
479 uint16_t address
, uint8_t *send
, int send_bytes
)
486 intel_dp_check_edp(intel_dp
);
489 msg
[0] = AUX_NATIVE_WRITE
<< 4;
490 msg
[1] = address
>> 8;
491 msg
[2] = address
& 0xff;
492 msg
[3] = send_bytes
- 1;
493 memcpy(&msg
[4], send
, send_bytes
);
494 msg_bytes
= send_bytes
+ 4;
496 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
499 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
501 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
509 /* Write a single byte to the aux channel in native mode */
511 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
512 uint16_t address
, uint8_t byte
)
514 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
517 /* read bytes from a native aux channel */
519 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
520 uint16_t address
, uint8_t *recv
, int recv_bytes
)
529 intel_dp_check_edp(intel_dp
);
530 msg
[0] = AUX_NATIVE_READ
<< 4;
531 msg
[1] = address
>> 8;
532 msg
[2] = address
& 0xff;
533 msg
[3] = recv_bytes
- 1;
536 reply_bytes
= recv_bytes
+ 1;
539 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
546 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
547 memcpy(recv
, reply
+ 1, ret
- 1);
550 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
558 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
559 uint8_t write_byte
, uint8_t *read_byte
)
561 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
562 struct intel_dp
*intel_dp
= container_of(adapter
,
565 uint16_t address
= algo_data
->address
;
573 intel_dp_check_edp(intel_dp
);
574 /* Set up the command byte */
575 if (mode
& MODE_I2C_READ
)
576 msg
[0] = AUX_I2C_READ
<< 4;
578 msg
[0] = AUX_I2C_WRITE
<< 4;
580 if (!(mode
& MODE_I2C_STOP
))
581 msg
[0] |= AUX_I2C_MOT
<< 4;
583 msg
[1] = address
>> 8;
604 for (retry
= 0; retry
< 5; retry
++) {
605 ret
= intel_dp_aux_ch(intel_dp
,
609 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
613 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
614 case AUX_NATIVE_REPLY_ACK
:
615 /* I2C-over-AUX Reply field is only valid
616 * when paired with AUX ACK.
619 case AUX_NATIVE_REPLY_NACK
:
620 DRM_DEBUG_KMS("aux_ch native nack\n");
622 case AUX_NATIVE_REPLY_DEFER
:
626 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
631 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
632 case AUX_I2C_REPLY_ACK
:
633 if (mode
== MODE_I2C_READ
) {
634 *read_byte
= reply
[1];
636 return reply_bytes
- 1;
637 case AUX_I2C_REPLY_NACK
:
638 DRM_DEBUG_KMS("aux_i2c nack\n");
640 case AUX_I2C_REPLY_DEFER
:
641 DRM_DEBUG_KMS("aux_i2c defer\n");
645 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
650 DRM_ERROR("too many retries, giving up\n");
654 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
655 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
658 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
659 struct intel_connector
*intel_connector
, const char *name
)
663 DRM_DEBUG_KMS("i2c_init %s\n", name
);
664 intel_dp
->algo
.running
= false;
665 intel_dp
->algo
.address
= 0;
666 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
668 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
669 intel_dp
->adapter
.owner
= THIS_MODULE
;
670 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
671 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
672 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
673 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
674 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
676 ironlake_edp_panel_vdd_on(intel_dp
);
677 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
678 ironlake_edp_panel_vdd_off(intel_dp
, false);
683 intel_dp_mode_fixup(struct drm_encoder
*encoder
,
684 const struct drm_display_mode
*mode
,
685 struct drm_display_mode
*adjusted_mode
)
687 struct drm_device
*dev
= encoder
->dev
;
688 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
689 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
690 int lane_count
, clock
;
691 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
692 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
694 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
696 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
697 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
699 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
700 mode
, adjusted_mode
);
703 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
706 DRM_DEBUG_KMS("DP link computation with max lane count %i "
707 "max bw %02x pixel clock %iKHz\n",
708 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
710 if (!intel_dp_adjust_dithering(intel_dp
, adjusted_mode
, true))
713 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
714 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
716 for (clock
= 0; clock
<= max_clock
; clock
++) {
717 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
718 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
720 if (mode_rate
<= link_avail
) {
721 intel_dp
->link_bw
= bws
[clock
];
722 intel_dp
->lane_count
= lane_count
;
723 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
724 DRM_DEBUG_KMS("DP link bw %02x lane "
725 "count %d clock %d bpp %d\n",
726 intel_dp
->link_bw
, intel_dp
->lane_count
,
727 adjusted_mode
->clock
, bpp
);
728 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
729 mode_rate
, link_avail
);
738 struct intel_dp_m_n
{
747 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
749 while (*num
> 0xffffff || *den
> 0xffffff) {
756 intel_dp_compute_m_n(int bpp
,
760 struct intel_dp_m_n
*m_n
)
763 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
764 m_n
->gmch_n
= link_clock
* nlanes
;
765 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
766 m_n
->link_m
= pixel_clock
;
767 m_n
->link_n
= link_clock
;
768 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
772 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
773 struct drm_display_mode
*adjusted_mode
)
775 struct drm_device
*dev
= crtc
->dev
;
776 struct intel_encoder
*encoder
;
777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
778 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
780 struct intel_dp_m_n m_n
;
781 int pipe
= intel_crtc
->pipe
;
782 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
785 * Find the lane count in the intel_encoder private
787 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
788 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
790 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
791 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
793 lane_count
= intel_dp
->lane_count
;
799 * Compute the GMCH and Link ratios. The '3' here is
800 * the number of bytes_per_pixel post-LUT, which we always
801 * set up for 8-bits of R/G/B, or 3 bytes total.
803 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
804 mode
->clock
, adjusted_mode
->clock
, &m_n
);
806 if (IS_HASWELL(dev
)) {
807 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
),
808 TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
809 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
810 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
811 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
812 } else if (HAS_PCH_SPLIT(dev
)) {
813 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
814 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
815 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
816 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
817 } else if (IS_VALLEYVIEW(dev
)) {
818 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
819 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
820 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
821 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
823 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
824 TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
825 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
826 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
827 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
831 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
833 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
834 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
835 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
836 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
838 * Check for DPCD version > 1.1 and enhanced framing support
840 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
841 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
842 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
847 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
848 struct drm_display_mode
*adjusted_mode
)
850 struct drm_device
*dev
= encoder
->dev
;
851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
852 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
853 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
854 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
857 * There are four kinds of DP registers:
864 * IBX PCH and CPU are the same for almost everything,
865 * except that the CPU DP PLL is configured in this
868 * CPT PCH is quite different, having many bits moved
869 * to the TRANS_DP_CTL register instead. That
870 * configuration happens (oddly) in ironlake_pch_enable
873 /* Preserve the BIOS-computed detected bit. This is
874 * supposed to be read-only.
876 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
878 /* Handle DP bits in common between all three register formats */
879 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
881 switch (intel_dp
->lane_count
) {
883 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
886 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
889 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
892 if (intel_dp
->has_audio
) {
893 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
894 pipe_name(intel_crtc
->pipe
));
895 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
896 intel_write_eld(encoder
, adjusted_mode
);
899 intel_dp_init_link_config(intel_dp
);
901 /* Split out the IBX/CPU vs CPT settings */
903 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
904 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
905 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
906 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
907 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
908 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
910 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
911 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
913 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
915 /* don't miss out required setting for eDP */
916 if (adjusted_mode
->clock
< 200000)
917 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
919 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
920 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
921 intel_dp
->DP
|= intel_dp
->color_range
;
923 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
924 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
925 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
926 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
927 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
929 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
930 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
932 if (intel_crtc
->pipe
== 1)
933 intel_dp
->DP
|= DP_PIPEB_SELECT
;
935 if (is_cpu_edp(intel_dp
)) {
936 /* don't miss out required setting for eDP */
937 if (adjusted_mode
->clock
< 200000)
938 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
940 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
943 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
947 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
948 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
950 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
951 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
953 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
954 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
956 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
960 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
963 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
965 I915_READ(PCH_PP_STATUS
),
966 I915_READ(PCH_PP_CONTROL
));
968 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
969 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
970 I915_READ(PCH_PP_STATUS
),
971 I915_READ(PCH_PP_CONTROL
));
975 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
977 DRM_DEBUG_KMS("Wait for panel power on\n");
978 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
981 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
983 DRM_DEBUG_KMS("Wait for panel power off time\n");
984 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
987 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
989 DRM_DEBUG_KMS("Wait for panel power cycle\n");
990 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
994 /* Read the current pp_control value, unlocking the register if it
998 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
1000 u32 control
= I915_READ(PCH_PP_CONTROL
);
1002 control
&= ~PANEL_UNLOCK_MASK
;
1003 control
|= PANEL_UNLOCK_REGS
;
1007 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1009 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1013 if (!is_edp(intel_dp
))
1015 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1017 WARN(intel_dp
->want_panel_vdd
,
1018 "eDP VDD already requested on\n");
1020 intel_dp
->want_panel_vdd
= true;
1022 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1023 DRM_DEBUG_KMS("eDP VDD already on\n");
1027 if (!ironlake_edp_have_panel_power(intel_dp
))
1028 ironlake_wait_panel_power_cycle(intel_dp
);
1030 pp
= ironlake_get_pp_control(dev_priv
);
1031 pp
|= EDP_FORCE_VDD
;
1032 I915_WRITE(PCH_PP_CONTROL
, pp
);
1033 POSTING_READ(PCH_PP_CONTROL
);
1034 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1035 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1038 * If the panel wasn't on, delay before accessing aux channel
1040 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1041 DRM_DEBUG_KMS("eDP was not running\n");
1042 msleep(intel_dp
->panel_power_up_delay
);
1046 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1048 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1052 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1053 pp
= ironlake_get_pp_control(dev_priv
);
1054 pp
&= ~EDP_FORCE_VDD
;
1055 I915_WRITE(PCH_PP_CONTROL
, pp
);
1056 POSTING_READ(PCH_PP_CONTROL
);
1058 /* Make sure sequencer is idle before allowing subsequent activity */
1059 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1060 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1062 msleep(intel_dp
->panel_power_down_delay
);
1066 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1068 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1069 struct intel_dp
, panel_vdd_work
);
1070 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1072 mutex_lock(&dev
->mode_config
.mutex
);
1073 ironlake_panel_vdd_off_sync(intel_dp
);
1074 mutex_unlock(&dev
->mode_config
.mutex
);
1077 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1079 if (!is_edp(intel_dp
))
1082 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1083 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1085 intel_dp
->want_panel_vdd
= false;
1088 ironlake_panel_vdd_off_sync(intel_dp
);
1091 * Queue the timer to fire a long
1092 * time from now (relative to the power down delay)
1093 * to keep the panel power up across a sequence of operations
1095 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1096 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1100 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1102 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1106 if (!is_edp(intel_dp
))
1109 DRM_DEBUG_KMS("Turn eDP power on\n");
1111 if (ironlake_edp_have_panel_power(intel_dp
)) {
1112 DRM_DEBUG_KMS("eDP power already on\n");
1116 ironlake_wait_panel_power_cycle(intel_dp
);
1118 pp
= ironlake_get_pp_control(dev_priv
);
1120 /* ILK workaround: disable reset around power sequence */
1121 pp
&= ~PANEL_POWER_RESET
;
1122 I915_WRITE(PCH_PP_CONTROL
, pp
);
1123 POSTING_READ(PCH_PP_CONTROL
);
1126 pp
|= POWER_TARGET_ON
;
1128 pp
|= PANEL_POWER_RESET
;
1130 I915_WRITE(PCH_PP_CONTROL
, pp
);
1131 POSTING_READ(PCH_PP_CONTROL
);
1133 ironlake_wait_panel_on(intel_dp
);
1136 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1137 I915_WRITE(PCH_PP_CONTROL
, pp
);
1138 POSTING_READ(PCH_PP_CONTROL
);
1142 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1144 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1148 if (!is_edp(intel_dp
))
1151 DRM_DEBUG_KMS("Turn eDP power off\n");
1153 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1155 pp
= ironlake_get_pp_control(dev_priv
);
1156 /* We need to switch off panel power _and_ force vdd, for otherwise some
1157 * panels get very unhappy and cease to work. */
1158 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1159 I915_WRITE(PCH_PP_CONTROL
, pp
);
1160 POSTING_READ(PCH_PP_CONTROL
);
1162 intel_dp
->want_panel_vdd
= false;
1164 ironlake_wait_panel_off(intel_dp
);
1167 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1169 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1171 int pipe
= to_intel_crtc(intel_dp
->base
.base
.crtc
)->pipe
;
1174 if (!is_edp(intel_dp
))
1177 DRM_DEBUG_KMS("\n");
1179 * If we enable the backlight right away following a panel power
1180 * on, we may see slight flicker as the panel syncs with the eDP
1181 * link. So delay a bit to make sure the image is solid before
1182 * allowing it to appear.
1184 msleep(intel_dp
->backlight_on_delay
);
1185 pp
= ironlake_get_pp_control(dev_priv
);
1186 pp
|= EDP_BLC_ENABLE
;
1187 I915_WRITE(PCH_PP_CONTROL
, pp
);
1188 POSTING_READ(PCH_PP_CONTROL
);
1190 intel_panel_enable_backlight(dev
, pipe
);
1193 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1195 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1199 if (!is_edp(intel_dp
))
1202 intel_panel_disable_backlight(dev
);
1204 DRM_DEBUG_KMS("\n");
1205 pp
= ironlake_get_pp_control(dev_priv
);
1206 pp
&= ~EDP_BLC_ENABLE
;
1207 I915_WRITE(PCH_PP_CONTROL
, pp
);
1208 POSTING_READ(PCH_PP_CONTROL
);
1209 msleep(intel_dp
->backlight_off_delay
);
1212 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1214 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1215 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1219 assert_pipe_disabled(dev_priv
,
1220 to_intel_crtc(crtc
)->pipe
);
1222 DRM_DEBUG_KMS("\n");
1223 dpa_ctl
= I915_READ(DP_A
);
1224 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1225 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1227 /* We don't adjust intel_dp->DP while tearing down the link, to
1228 * facilitate link retraining (e.g. after hotplug). Hence clear all
1229 * enable bits here to ensure that we don't enable too much. */
1230 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1231 intel_dp
->DP
|= DP_PLL_ENABLE
;
1232 I915_WRITE(DP_A
, intel_dp
->DP
);
1237 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1239 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1240 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1244 assert_pipe_disabled(dev_priv
,
1245 to_intel_crtc(crtc
)->pipe
);
1247 dpa_ctl
= I915_READ(DP_A
);
1248 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1249 "dp pll off, should be on\n");
1250 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1252 /* We can't rely on the value tracked for the DP register in
1253 * intel_dp->DP because link_down must not change that (otherwise link
1254 * re-training will fail. */
1255 dpa_ctl
&= ~DP_PLL_ENABLE
;
1256 I915_WRITE(DP_A
, dpa_ctl
);
1261 /* If the sink supports it, try to set the power state appropriately */
1262 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1266 /* Should have a valid DPCD by this point */
1267 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1270 if (mode
!= DRM_MODE_DPMS_ON
) {
1271 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1274 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1277 * When turning on, we need to retry for 1ms to give the sink
1280 for (i
= 0; i
< 3; i
++) {
1281 ret
= intel_dp_aux_native_write_1(intel_dp
,
1291 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1294 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1295 struct drm_device
*dev
= encoder
->base
.dev
;
1296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1297 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1299 if (!(tmp
& DP_PORT_EN
))
1302 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
1303 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1304 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1305 *pipe
= PORT_TO_PIPE(tmp
);
1311 switch (intel_dp
->output_reg
) {
1313 trans_sel
= TRANS_DP_PORT_SEL_B
;
1316 trans_sel
= TRANS_DP_PORT_SEL_C
;
1319 trans_sel
= TRANS_DP_PORT_SEL_D
;
1326 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1327 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1334 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp
->output_reg
);
1339 static void intel_disable_dp(struct intel_encoder
*encoder
)
1341 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1343 /* Make sure the panel is off before trying to change the mode. But also
1344 * ensure that we have vdd while we switch off the panel. */
1345 ironlake_edp_panel_vdd_on(intel_dp
);
1346 ironlake_edp_backlight_off(intel_dp
);
1347 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1348 ironlake_edp_panel_off(intel_dp
);
1350 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1351 if (!is_cpu_edp(intel_dp
))
1352 intel_dp_link_down(intel_dp
);
1355 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1357 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1359 if (is_cpu_edp(intel_dp
)) {
1360 intel_dp_link_down(intel_dp
);
1361 ironlake_edp_pll_off(intel_dp
);
1365 static void intel_enable_dp(struct intel_encoder
*encoder
)
1367 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1368 struct drm_device
*dev
= encoder
->base
.dev
;
1369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1370 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1372 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1375 ironlake_edp_panel_vdd_on(intel_dp
);
1376 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1377 intel_dp_start_link_train(intel_dp
);
1378 ironlake_edp_panel_on(intel_dp
);
1379 ironlake_edp_panel_vdd_off(intel_dp
, true);
1380 intel_dp_complete_link_train(intel_dp
);
1381 ironlake_edp_backlight_on(intel_dp
);
1384 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1386 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1388 if (is_cpu_edp(intel_dp
))
1389 ironlake_edp_pll_on(intel_dp
);
1393 * Native read with retry for link status and receiver capability reads for
1394 * cases where the sink may still be asleep.
1397 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1398 uint8_t *recv
, int recv_bytes
)
1403 * Sinks are *supposed* to come up within 1ms from an off state,
1404 * but we're also supposed to retry 3 times per the spec.
1406 for (i
= 0; i
< 3; i
++) {
1407 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1409 if (ret
== recv_bytes
)
1418 * Fetch AUX CH registers 0x202 - 0x207 which contain
1419 * link status information
1422 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1424 return intel_dp_aux_native_read_retry(intel_dp
,
1427 DP_LINK_STATUS_SIZE
);
1431 static char *voltage_names
[] = {
1432 "0.4V", "0.6V", "0.8V", "1.2V"
1434 static char *pre_emph_names
[] = {
1435 "0dB", "3.5dB", "6dB", "9.5dB"
1437 static char *link_train_names
[] = {
1438 "pattern 1", "pattern 2", "idle", "off"
1443 * These are source-specific values; current Intel hardware supports
1444 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1448 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1450 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1452 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1453 return DP_TRAIN_VOLTAGE_SWING_800
;
1454 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1455 return DP_TRAIN_VOLTAGE_SWING_1200
;
1457 return DP_TRAIN_VOLTAGE_SWING_800
;
1461 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1463 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1465 if (IS_HASWELL(dev
)) {
1466 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1467 case DP_TRAIN_VOLTAGE_SWING_400
:
1468 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1469 case DP_TRAIN_VOLTAGE_SWING_600
:
1470 return DP_TRAIN_PRE_EMPHASIS_6
;
1471 case DP_TRAIN_VOLTAGE_SWING_800
:
1472 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1473 case DP_TRAIN_VOLTAGE_SWING_1200
:
1475 return DP_TRAIN_PRE_EMPHASIS_0
;
1477 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1478 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1479 case DP_TRAIN_VOLTAGE_SWING_400
:
1480 return DP_TRAIN_PRE_EMPHASIS_6
;
1481 case DP_TRAIN_VOLTAGE_SWING_600
:
1482 case DP_TRAIN_VOLTAGE_SWING_800
:
1483 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1485 return DP_TRAIN_PRE_EMPHASIS_0
;
1488 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1489 case DP_TRAIN_VOLTAGE_SWING_400
:
1490 return DP_TRAIN_PRE_EMPHASIS_6
;
1491 case DP_TRAIN_VOLTAGE_SWING_600
:
1492 return DP_TRAIN_PRE_EMPHASIS_6
;
1493 case DP_TRAIN_VOLTAGE_SWING_800
:
1494 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1495 case DP_TRAIN_VOLTAGE_SWING_1200
:
1497 return DP_TRAIN_PRE_EMPHASIS_0
;
1503 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1508 uint8_t voltage_max
;
1509 uint8_t preemph_max
;
1511 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1512 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
1513 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
1521 voltage_max
= intel_dp_voltage_max(intel_dp
);
1522 if (v
>= voltage_max
)
1523 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1525 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1526 if (p
>= preemph_max
)
1527 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1529 for (lane
= 0; lane
< 4; lane
++)
1530 intel_dp
->train_set
[lane
] = v
| p
;
1534 intel_dp_signal_levels(uint8_t train_set
)
1536 uint32_t signal_levels
= 0;
1538 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1539 case DP_TRAIN_VOLTAGE_SWING_400
:
1541 signal_levels
|= DP_VOLTAGE_0_4
;
1543 case DP_TRAIN_VOLTAGE_SWING_600
:
1544 signal_levels
|= DP_VOLTAGE_0_6
;
1546 case DP_TRAIN_VOLTAGE_SWING_800
:
1547 signal_levels
|= DP_VOLTAGE_0_8
;
1549 case DP_TRAIN_VOLTAGE_SWING_1200
:
1550 signal_levels
|= DP_VOLTAGE_1_2
;
1553 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1554 case DP_TRAIN_PRE_EMPHASIS_0
:
1556 signal_levels
|= DP_PRE_EMPHASIS_0
;
1558 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1559 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1561 case DP_TRAIN_PRE_EMPHASIS_6
:
1562 signal_levels
|= DP_PRE_EMPHASIS_6
;
1564 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1565 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1568 return signal_levels
;
1571 /* Gen6's DP voltage swing and pre-emphasis control */
1573 intel_gen6_edp_signal_levels(uint8_t train_set
)
1575 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1576 DP_TRAIN_PRE_EMPHASIS_MASK
);
1577 switch (signal_levels
) {
1578 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1579 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1580 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1581 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1582 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1583 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1584 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1585 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1586 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1587 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1588 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1589 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1590 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1591 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1593 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1594 "0x%x\n", signal_levels
);
1595 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1599 /* Gen7's DP voltage swing and pre-emphasis control */
1601 intel_gen7_edp_signal_levels(uint8_t train_set
)
1603 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1604 DP_TRAIN_PRE_EMPHASIS_MASK
);
1605 switch (signal_levels
) {
1606 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1607 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1608 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1609 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1610 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1611 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1613 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1614 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1615 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1616 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1618 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1619 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1620 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1621 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1624 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1625 "0x%x\n", signal_levels
);
1626 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1630 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1632 intel_dp_signal_levels_hsw(uint8_t train_set
)
1634 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1635 DP_TRAIN_PRE_EMPHASIS_MASK
);
1636 switch (signal_levels
) {
1637 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1638 return DDI_BUF_EMP_400MV_0DB_HSW
;
1639 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1640 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1641 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1642 return DDI_BUF_EMP_400MV_6DB_HSW
;
1643 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1644 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1646 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1647 return DDI_BUF_EMP_600MV_0DB_HSW
;
1648 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1649 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1650 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1651 return DDI_BUF_EMP_600MV_6DB_HSW
;
1653 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1654 return DDI_BUF_EMP_800MV_0DB_HSW
;
1655 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1656 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1658 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1659 "0x%x\n", signal_levels
);
1660 return DDI_BUF_EMP_400MV_0DB_HSW
;
1665 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1666 uint32_t dp_reg_value
,
1667 uint8_t dp_train_pat
)
1669 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1674 if (IS_HASWELL(dev
)) {
1675 temp
= I915_READ(DP_TP_CTL(intel_dp
->port
));
1677 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1678 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1680 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1682 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1683 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1684 case DP_TRAINING_PATTERN_DISABLE
:
1685 temp
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
1686 I915_WRITE(DP_TP_CTL(intel_dp
->port
), temp
);
1688 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp
->port
)) &
1689 DP_TP_STATUS_IDLE_DONE
), 1))
1690 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1692 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1693 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1696 case DP_TRAINING_PATTERN_1
:
1697 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1699 case DP_TRAINING_PATTERN_2
:
1700 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1702 case DP_TRAINING_PATTERN_3
:
1703 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1706 I915_WRITE(DP_TP_CTL(intel_dp
->port
), temp
);
1708 } else if (HAS_PCH_CPT(dev
) &&
1709 (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1710 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1712 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1713 case DP_TRAINING_PATTERN_DISABLE
:
1714 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1716 case DP_TRAINING_PATTERN_1
:
1717 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1719 case DP_TRAINING_PATTERN_2
:
1720 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1722 case DP_TRAINING_PATTERN_3
:
1723 DRM_ERROR("DP training pattern 3 not supported\n");
1724 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1729 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1731 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1732 case DP_TRAINING_PATTERN_DISABLE
:
1733 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1735 case DP_TRAINING_PATTERN_1
:
1736 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1738 case DP_TRAINING_PATTERN_2
:
1739 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1741 case DP_TRAINING_PATTERN_3
:
1742 DRM_ERROR("DP training pattern 3 not supported\n");
1743 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1748 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1749 POSTING_READ(intel_dp
->output_reg
);
1751 intel_dp_aux_native_write_1(intel_dp
,
1752 DP_TRAINING_PATTERN_SET
,
1755 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1756 DP_TRAINING_PATTERN_DISABLE
) {
1757 ret
= intel_dp_aux_native_write(intel_dp
,
1758 DP_TRAINING_LANE0_SET
,
1759 intel_dp
->train_set
,
1760 intel_dp
->lane_count
);
1761 if (ret
!= intel_dp
->lane_count
)
1768 /* Enable corresponding port and start training pattern 1 */
1770 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1772 struct drm_encoder
*encoder
= &intel_dp
->base
.base
;
1773 struct drm_device
*dev
= encoder
->dev
;
1776 bool clock_recovery
= false;
1777 int voltage_tries
, loop_tries
;
1778 uint32_t DP
= intel_dp
->DP
;
1780 if (IS_HASWELL(dev
))
1781 intel_ddi_prepare_link_retrain(encoder
);
1783 /* Write the link configuration data */
1784 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1785 intel_dp
->link_configuration
,
1786 DP_LINK_CONFIGURATION_SIZE
);
1790 memset(intel_dp
->train_set
, 0, 4);
1794 clock_recovery
= false;
1796 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1797 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1798 uint32_t signal_levels
;
1800 if (IS_HASWELL(dev
)) {
1801 signal_levels
= intel_dp_signal_levels_hsw(
1802 intel_dp
->train_set
[0]);
1803 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1804 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1805 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1806 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1807 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1808 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1809 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1811 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1812 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1814 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1817 /* Set training pattern 1 */
1818 if (!intel_dp_set_link_train(intel_dp
, DP
,
1819 DP_TRAINING_PATTERN_1
|
1820 DP_LINK_SCRAMBLING_DISABLE
))
1823 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
1824 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1825 DRM_ERROR("failed to get link status\n");
1829 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1830 DRM_DEBUG_KMS("clock recovery OK\n");
1831 clock_recovery
= true;
1835 /* Check to see if we've tried the max voltage */
1836 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1837 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1839 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1840 if (++loop_tries
== 5) {
1841 DRM_DEBUG_KMS("too many full retries, give up\n");
1844 memset(intel_dp
->train_set
, 0, 4);
1849 /* Check to see if we've tried the same voltage 5 times */
1850 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) != voltage
) {
1851 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1856 /* Compute new intel_dp->train_set as requested by target */
1857 intel_get_adjust_train(intel_dp
, link_status
);
1864 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1866 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1867 bool channel_eq
= false;
1868 int tries
, cr_tries
;
1869 uint32_t DP
= intel_dp
->DP
;
1871 /* channel equalization */
1876 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1877 uint32_t signal_levels
;
1878 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1881 DRM_ERROR("failed to train DP, aborting\n");
1882 intel_dp_link_down(intel_dp
);
1886 if (IS_HASWELL(dev
)) {
1887 signal_levels
= intel_dp_signal_levels_hsw(intel_dp
->train_set
[0]);
1888 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1889 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1890 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1891 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1892 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1893 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1894 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1896 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1897 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1900 /* channel eq pattern */
1901 if (!intel_dp_set_link_train(intel_dp
, DP
,
1902 DP_TRAINING_PATTERN_2
|
1903 DP_LINK_SCRAMBLING_DISABLE
))
1906 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
1907 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1910 /* Make sure clock is still ok */
1911 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1912 intel_dp_start_link_train(intel_dp
);
1917 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
1922 /* Try 5 times, then try clock recovery if that fails */
1924 intel_dp_link_down(intel_dp
);
1925 intel_dp_start_link_train(intel_dp
);
1931 /* Compute new intel_dp->train_set as requested by target */
1932 intel_get_adjust_train(intel_dp
, link_status
);
1937 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1939 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
1943 intel_dp_link_down(struct intel_dp
*intel_dp
)
1945 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1947 uint32_t DP
= intel_dp
->DP
;
1950 * DDI code has a strict mode set sequence and we should try to respect
1951 * it, otherwise we might hang the machine in many different ways. So we
1952 * really should be disabling the port only on a complete crtc_disable
1953 * sequence. This function is just called under two conditions on DDI
1955 * - Link train failed while doing crtc_enable, and on this case we
1956 * really should respect the mode set sequence and wait for a
1958 * - Someone turned the monitor off and intel_dp_check_link_status
1959 * called us. We don't need to disable the whole port on this case, so
1960 * when someone turns the monitor on again,
1961 * intel_ddi_prepare_link_retrain will take care of redoing the link
1964 if (IS_HASWELL(dev
))
1967 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
1970 DRM_DEBUG_KMS("\n");
1972 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1973 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1974 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1976 DP
&= ~DP_LINK_TRAIN_MASK
;
1977 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1979 POSTING_READ(intel_dp
->output_reg
);
1983 if (HAS_PCH_IBX(dev
) &&
1984 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1985 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1987 /* Hardware workaround: leaving our transcoder select
1988 * set to transcoder B while it's off will prevent the
1989 * corresponding HDMI output on transcoder A.
1991 * Combine this with another hardware workaround:
1992 * transcoder select bit can only be cleared while the
1995 DP
&= ~DP_PIPEB_SELECT
;
1996 I915_WRITE(intel_dp
->output_reg
, DP
);
1998 /* Changes to enable or select take place the vblank
1999 * after being written.
2002 /* We can arrive here never having been attached
2003 * to a CRTC, for instance, due to inheriting
2004 * random state from the BIOS.
2006 * If the pipe is not running, play safe and
2007 * wait for the clocks to stabilise before
2010 POSTING_READ(intel_dp
->output_reg
);
2013 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
2016 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2017 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2018 POSTING_READ(intel_dp
->output_reg
);
2019 msleep(intel_dp
->panel_power_down_delay
);
2023 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2025 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2026 sizeof(intel_dp
->dpcd
)) == 0)
2027 return false; /* aux transfer failed */
2029 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2030 return false; /* DPCD not present */
2032 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2033 DP_DWN_STRM_PORT_PRESENT
))
2034 return true; /* native DP sink */
2036 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2037 return true; /* no per-port downstream info */
2039 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2040 intel_dp
->downstream_ports
,
2041 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2042 return false; /* downstream port status fetch failed */
2048 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2052 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2055 ironlake_edp_panel_vdd_on(intel_dp
);
2057 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2058 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2059 buf
[0], buf
[1], buf
[2]);
2061 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2062 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2063 buf
[0], buf
[1], buf
[2]);
2065 ironlake_edp_panel_vdd_off(intel_dp
, false);
2069 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2073 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2074 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2075 sink_irq_vector
, 1);
2083 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2085 /* NAK by default */
2086 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2090 * According to DP spec
2093 * 2. Configure link according to Receiver Capabilities
2094 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2095 * 4. Check link status on receipt of hot-plug interrupt
2099 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2102 u8 link_status
[DP_LINK_STATUS_SIZE
];
2104 if (!intel_dp
->base
.connectors_active
)
2107 if (WARN_ON(!intel_dp
->base
.base
.crtc
))
2110 /* Try to read receiver status if the link appears to be up */
2111 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2112 intel_dp_link_down(intel_dp
);
2116 /* Now read the DPCD to see if it's actually running */
2117 if (!intel_dp_get_dpcd(intel_dp
)) {
2118 intel_dp_link_down(intel_dp
);
2122 /* Try to read the source of the interrupt */
2123 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2124 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2125 /* Clear interrupt source */
2126 intel_dp_aux_native_write_1(intel_dp
,
2127 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2130 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2131 intel_dp_handle_test_request(intel_dp
);
2132 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2133 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2136 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2137 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2138 drm_get_encoder_name(&intel_dp
->base
.base
));
2139 intel_dp_start_link_train(intel_dp
);
2140 intel_dp_complete_link_train(intel_dp
);
2144 /* XXX this is probably wrong for multiple downstream ports */
2145 static enum drm_connector_status
2146 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2148 uint8_t *dpcd
= intel_dp
->dpcd
;
2152 if (!intel_dp_get_dpcd(intel_dp
))
2153 return connector_status_disconnected
;
2155 /* if there's no downstream port, we're done */
2156 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2157 return connector_status_connected
;
2159 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2160 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2163 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2165 return connector_status_unknown
;
2166 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2167 : connector_status_disconnected
;
2170 /* If no HPD, poke DDC gently */
2171 if (drm_probe_ddc(&intel_dp
->adapter
))
2172 return connector_status_connected
;
2174 /* Well we tried, say unknown for unreliable port types */
2175 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2176 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2177 return connector_status_unknown
;
2179 /* Anything else is out of spec, warn and ignore */
2180 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2181 return connector_status_disconnected
;
2184 static enum drm_connector_status
2185 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2187 enum drm_connector_status status
;
2189 /* Can't disconnect eDP, but you can close the lid... */
2190 if (is_edp(intel_dp
)) {
2191 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2192 if (status
== connector_status_unknown
)
2193 status
= connector_status_connected
;
2197 return intel_dp_detect_dpcd(intel_dp
);
2200 static enum drm_connector_status
2201 g4x_dp_detect(struct intel_dp
*intel_dp
)
2203 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2207 switch (intel_dp
->output_reg
) {
2209 bit
= DPB_HOTPLUG_LIVE_STATUS
;
2212 bit
= DPC_HOTPLUG_LIVE_STATUS
;
2215 bit
= DPD_HOTPLUG_LIVE_STATUS
;
2218 return connector_status_unknown
;
2221 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2222 return connector_status_disconnected
;
2224 return intel_dp_detect_dpcd(intel_dp
);
2227 static struct edid
*
2228 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2230 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2232 /* use cached edid if we have one */
2233 if (intel_connector
->edid
) {
2238 if (IS_ERR(intel_connector
->edid
))
2241 size
= (intel_connector
->edid
->extensions
+ 1) * EDID_LENGTH
;
2242 edid
= kmalloc(size
, GFP_KERNEL
);
2246 memcpy(edid
, intel_connector
->edid
, size
);
2250 return drm_get_edid(connector
, adapter
);
2254 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2256 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2258 /* use cached edid if we have one */
2259 if (intel_connector
->edid
) {
2261 if (IS_ERR(intel_connector
->edid
))
2264 return intel_connector_update_modes(connector
,
2265 intel_connector
->edid
);
2268 return intel_ddc_get_modes(connector
, adapter
);
2273 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2275 * \return true if DP port is connected.
2276 * \return false if DP port is disconnected.
2278 static enum drm_connector_status
2279 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2281 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2282 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2283 enum drm_connector_status status
;
2284 struct edid
*edid
= NULL
;
2286 intel_dp
->has_audio
= false;
2288 if (HAS_PCH_SPLIT(dev
))
2289 status
= ironlake_dp_detect(intel_dp
);
2291 status
= g4x_dp_detect(intel_dp
);
2293 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2294 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2295 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2296 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2298 if (status
!= connector_status_connected
)
2301 intel_dp_probe_oui(intel_dp
);
2303 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2304 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2306 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2308 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2313 return connector_status_connected
;
2316 static int intel_dp_get_modes(struct drm_connector
*connector
)
2318 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2319 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2320 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2323 /* We should parse the EDID data and find out if it has an audio sink
2326 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2330 /* if eDP has no EDID, fall back to fixed mode */
2331 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2332 struct drm_display_mode
*mode
;
2333 mode
= drm_mode_duplicate(dev
,
2334 intel_connector
->panel
.fixed_mode
);
2336 drm_mode_probed_add(connector
, mode
);
2344 intel_dp_detect_audio(struct drm_connector
*connector
)
2346 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2348 bool has_audio
= false;
2350 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2352 has_audio
= drm_detect_monitor_audio(edid
);
2360 intel_dp_set_property(struct drm_connector
*connector
,
2361 struct drm_property
*property
,
2364 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2365 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2368 ret
= drm_connector_property_set_value(connector
, property
, val
);
2372 if (property
== dev_priv
->force_audio_property
) {
2376 if (i
== intel_dp
->force_audio
)
2379 intel_dp
->force_audio
= i
;
2381 if (i
== HDMI_AUDIO_AUTO
)
2382 has_audio
= intel_dp_detect_audio(connector
);
2384 has_audio
= (i
== HDMI_AUDIO_ON
);
2386 if (has_audio
== intel_dp
->has_audio
)
2389 intel_dp
->has_audio
= has_audio
;
2393 if (property
== dev_priv
->broadcast_rgb_property
) {
2394 if (val
== !!intel_dp
->color_range
)
2397 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2404 if (intel_dp
->base
.base
.crtc
) {
2405 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2406 intel_set_mode(crtc
, &crtc
->mode
,
2407 crtc
->x
, crtc
->y
, crtc
->fb
);
2414 intel_dp_destroy(struct drm_connector
*connector
)
2416 struct drm_device
*dev
= connector
->dev
;
2417 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2418 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2420 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
2421 kfree(intel_connector
->edid
);
2423 if (is_edp(intel_dp
)) {
2424 intel_panel_destroy_backlight(dev
);
2425 intel_panel_fini(&intel_connector
->panel
);
2428 drm_sysfs_connector_remove(connector
);
2429 drm_connector_cleanup(connector
);
2433 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2435 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2437 i2c_del_adapter(&intel_dp
->adapter
);
2438 drm_encoder_cleanup(encoder
);
2439 if (is_edp(intel_dp
)) {
2440 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2441 ironlake_panel_vdd_off_sync(intel_dp
);
2446 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2447 .mode_fixup
= intel_dp_mode_fixup
,
2448 .mode_set
= intel_dp_mode_set
,
2449 .disable
= intel_encoder_noop
,
2452 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw
= {
2453 .mode_fixup
= intel_dp_mode_fixup
,
2454 .mode_set
= intel_ddi_mode_set
,
2455 .disable
= intel_encoder_noop
,
2458 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2459 .dpms
= intel_connector_dpms
,
2460 .detect
= intel_dp_detect
,
2461 .fill_modes
= drm_helper_probe_single_connector_modes
,
2462 .set_property
= intel_dp_set_property
,
2463 .destroy
= intel_dp_destroy
,
2466 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2467 .get_modes
= intel_dp_get_modes
,
2468 .mode_valid
= intel_dp_mode_valid
,
2469 .best_encoder
= intel_best_encoder
,
2472 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2473 .destroy
= intel_dp_encoder_destroy
,
2477 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2479 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2481 intel_dp_check_link_status(intel_dp
);
2484 /* Return which DP Port should be selected for Transcoder DP control */
2486 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2488 struct drm_device
*dev
= crtc
->dev
;
2489 struct intel_encoder
*encoder
;
2491 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2492 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2494 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2495 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2496 return intel_dp
->output_reg
;
2502 /* check the VBT to see whether the eDP is on DP-D port */
2503 bool intel_dpd_is_edp(struct drm_device
*dev
)
2505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2506 struct child_device_config
*p_child
;
2509 if (!dev_priv
->child_dev_num
)
2512 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2513 p_child
= dev_priv
->child_dev
+ i
;
2515 if (p_child
->dvo_port
== PORT_IDPD
&&
2516 p_child
->device_type
== DEVICE_TYPE_eDP
)
2523 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2525 intel_attach_force_audio_property(connector
);
2526 intel_attach_broadcast_rgb_property(connector
);
2530 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
2531 struct intel_dp
*intel_dp
)
2533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2534 struct edp_power_seq cur
, vbt
, spec
, final
;
2535 u32 pp_on
, pp_off
, pp_div
, pp
;
2537 /* Workaround: Need to write PP_CONTROL with the unlock key as
2538 * the very first thing. */
2539 pp
= ironlake_get_pp_control(dev_priv
);
2540 I915_WRITE(PCH_PP_CONTROL
, pp
);
2542 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2543 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2544 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2546 /* Pull timing values out of registers */
2547 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2548 PANEL_POWER_UP_DELAY_SHIFT
;
2550 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2551 PANEL_LIGHT_ON_DELAY_SHIFT
;
2553 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2554 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2556 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2557 PANEL_POWER_DOWN_DELAY_SHIFT
;
2559 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2560 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2562 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2563 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2565 vbt
= dev_priv
->edp
.pps
;
2567 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2568 * our hw here, which are all in 100usec. */
2569 spec
.t1_t3
= 210 * 10;
2570 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
2571 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
2572 spec
.t10
= 500 * 10;
2573 /* This one is special and actually in units of 100ms, but zero
2574 * based in the hw (so we need to add 100 ms). But the sw vbt
2575 * table multiplies it with 1000 to make it in units of 100usec,
2577 spec
.t11_t12
= (510 + 100) * 10;
2579 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2580 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2582 /* Use the max of the register settings and vbt. If both are
2583 * unset, fall back to the spec limits. */
2584 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2586 max(cur.field, vbt.field))
2587 assign_final(t1_t3
);
2591 assign_final(t11_t12
);
2594 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2595 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2596 intel_dp
->backlight_on_delay
= get_delay(t8
);
2597 intel_dp
->backlight_off_delay
= get_delay(t9
);
2598 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2599 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2602 /* And finally store the new values in the power sequencer. */
2603 pp_on
= (final
.t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
2604 (final
.t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
2605 pp_off
= (final
.t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
2606 (final
.t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
2607 /* Compute the divisor for the pp clock, simply match the Bspec
2609 pp_div
= ((100 * intel_pch_rawclk(dev
))/2 - 1)
2610 << PP_REFERENCE_DIVIDER_SHIFT
;
2611 pp_div
|= (DIV_ROUND_UP(final
.t11_t12
, 1000)
2612 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
2614 /* Haswell doesn't have any port selection bits for the panel
2615 * power sequencer any more. */
2616 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
2617 if (is_cpu_edp(intel_dp
))
2618 pp_on
|= PANEL_POWER_PORT_DP_A
;
2620 pp_on
|= PANEL_POWER_PORT_DP_D
;
2623 I915_WRITE(PCH_PP_ON_DELAYS
, pp_on
);
2624 I915_WRITE(PCH_PP_OFF_DELAYS
, pp_off
);
2625 I915_WRITE(PCH_PP_DIVISOR
, pp_div
);
2628 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2629 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2630 intel_dp
->panel_power_cycle_delay
);
2632 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2633 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2635 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2636 I915_READ(PCH_PP_ON_DELAYS
),
2637 I915_READ(PCH_PP_OFF_DELAYS
),
2638 I915_READ(PCH_PP_DIVISOR
));
2642 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2645 struct drm_connector
*connector
;
2646 struct intel_dp
*intel_dp
;
2647 struct intel_encoder
*intel_encoder
;
2648 struct intel_connector
*intel_connector
;
2649 struct drm_display_mode
*fixed_mode
= NULL
;
2650 const char *name
= NULL
;
2653 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2657 intel_dp
->output_reg
= output_reg
;
2658 intel_dp
->port
= port
;
2659 /* Preserve the current hw state. */
2660 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2662 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2663 if (!intel_connector
) {
2667 intel_encoder
= &intel_dp
->base
;
2668 intel_dp
->attached_connector
= intel_connector
;
2670 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2671 if (intel_dpd_is_edp(dev
))
2672 intel_dp
->is_pch_edp
= true;
2675 * FIXME : We need to initialize built-in panels before external panels.
2676 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2678 if (IS_VALLEYVIEW(dev
) && output_reg
== DP_C
) {
2679 type
= DRM_MODE_CONNECTOR_eDP
;
2680 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2681 } else if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2682 type
= DRM_MODE_CONNECTOR_eDP
;
2683 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2685 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2686 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2689 connector
= &intel_connector
->base
;
2690 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2691 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2693 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2695 intel_encoder
->cloneable
= false;
2697 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2698 ironlake_panel_vdd_work
);
2700 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2702 connector
->interlace_allowed
= true;
2703 connector
->doublescan_allowed
= 0;
2705 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2706 DRM_MODE_ENCODER_TMDS
);
2708 if (IS_HASWELL(dev
))
2709 drm_encoder_helper_add(&intel_encoder
->base
,
2710 &intel_dp_helper_funcs_hsw
);
2712 drm_encoder_helper_add(&intel_encoder
->base
,
2713 &intel_dp_helper_funcs
);
2715 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2716 drm_sysfs_connector_add(connector
);
2718 if (IS_HASWELL(dev
)) {
2719 intel_encoder
->enable
= intel_enable_ddi
;
2720 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
2721 intel_encoder
->disable
= intel_disable_ddi
;
2722 intel_encoder
->post_disable
= intel_ddi_post_disable
;
2723 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
2725 intel_encoder
->enable
= intel_enable_dp
;
2726 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2727 intel_encoder
->disable
= intel_disable_dp
;
2728 intel_encoder
->post_disable
= intel_post_disable_dp
;
2729 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2731 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2733 /* Set up the DDC bus. */
2739 dev_priv
->hotplug_supported_mask
|= DPB_HOTPLUG_INT_STATUS
;
2743 dev_priv
->hotplug_supported_mask
|= DPC_HOTPLUG_INT_STATUS
;
2747 dev_priv
->hotplug_supported_mask
|= DPD_HOTPLUG_INT_STATUS
;
2751 WARN(1, "Invalid port %c\n", port_name(port
));
2755 if (is_edp(intel_dp
))
2756 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2758 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2760 /* Cache DPCD and EDID for edp. */
2761 if (is_edp(intel_dp
)) {
2763 struct drm_display_mode
*scan
;
2766 ironlake_edp_panel_vdd_on(intel_dp
);
2767 ret
= intel_dp_get_dpcd(intel_dp
);
2768 ironlake_edp_panel_vdd_off(intel_dp
, false);
2771 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2772 dev_priv
->no_aux_handshake
=
2773 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2774 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2776 /* if this fails, presume the device is a ghost */
2777 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2778 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2779 intel_dp_destroy(&intel_connector
->base
);
2783 ironlake_edp_panel_vdd_on(intel_dp
);
2784 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2786 if (drm_add_edid_modes(connector
, edid
)) {
2787 drm_mode_connector_update_edid_property(connector
, edid
);
2788 drm_edid_to_eld(connector
, edid
);
2791 edid
= ERR_PTR(-EINVAL
);
2794 edid
= ERR_PTR(-ENOENT
);
2796 intel_connector
->edid
= edid
;
2798 /* prefer fixed mode from EDID if available */
2799 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
2800 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2801 fixed_mode
= drm_mode_duplicate(dev
, scan
);
2806 /* fallback to VBT if available for eDP */
2807 if (!fixed_mode
&& dev_priv
->lfp_lvds_vbt_mode
) {
2808 fixed_mode
= drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2810 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
2813 ironlake_edp_panel_vdd_off(intel_dp
, false);
2816 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2818 if (is_edp(intel_dp
)) {
2819 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
2820 intel_panel_setup_backlight(connector
);
2823 intel_dp_add_properties(intel_dp
, connector
);
2825 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2826 * 0xd. Failure to do so will result in spurious interrupts being
2827 * generated on the port when a cable is not attached.
2829 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2830 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2831 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);