2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
133 static unsigned int intel_dp_unused_lane_mask(int lane_count
)
135 return ~((1 << lane_count
) - 1) & 0xf;
139 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
141 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
143 switch (max_link_bw
) {
144 case DP_LINK_BW_1_62
:
149 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
151 max_link_bw
= DP_LINK_BW_1_62
;
157 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
159 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
160 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
161 u8 source_max
, sink_max
;
164 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
165 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
168 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
170 return min(source_max
, sink_max
);
174 * The units on the numbers in the next two are... bizarre. Examples will
175 * make it clearer; this one parallels an example in the eDP spec.
177 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
179 * 270000 * 1 * 8 / 10 == 216000
181 * The actual data capacity of that configuration is 2.16Gbit/s, so the
182 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
183 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
184 * 119000. At 18bpp that's 2142000 kilobits per second.
186 * Thus the strange-looking division by 10 in intel_dp_link_required, to
187 * get the result in decakilobits instead of kilobits.
191 intel_dp_link_required(int pixel_clock
, int bpp
)
193 return (pixel_clock
* bpp
+ 9) / 10;
197 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
199 return (max_link_clock
* max_lanes
* 8) / 10;
202 static enum drm_mode_status
203 intel_dp_mode_valid(struct drm_connector
*connector
,
204 struct drm_display_mode
*mode
)
206 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
207 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
208 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
209 int target_clock
= mode
->clock
;
210 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
212 if (is_edp(intel_dp
) && fixed_mode
) {
213 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
216 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
219 target_clock
= fixed_mode
->clock
;
222 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
223 max_lanes
= intel_dp_max_lane_count(intel_dp
);
225 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
226 mode_rate
= intel_dp_link_required(target_clock
, 18);
228 if (mode_rate
> max_rate
)
229 return MODE_CLOCK_HIGH
;
231 if (mode
->clock
< 10000)
232 return MODE_CLOCK_LOW
;
234 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
235 return MODE_H_ILLEGAL
;
240 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
247 for (i
= 0; i
< src_bytes
; i
++)
248 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
252 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
257 for (i
= 0; i
< dst_bytes
; i
++)
258 dst
[i
] = src
>> ((3-i
) * 8);
262 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
263 struct intel_dp
*intel_dp
);
265 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
266 struct intel_dp
*intel_dp
);
268 static void pps_lock(struct intel_dp
*intel_dp
)
270 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
271 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
272 struct drm_device
*dev
= encoder
->base
.dev
;
273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
274 enum intel_display_power_domain power_domain
;
277 * See vlv_power_sequencer_reset() why we need
278 * a power domain reference here.
280 power_domain
= intel_display_port_aux_power_domain(encoder
);
281 intel_display_power_get(dev_priv
, power_domain
);
283 mutex_lock(&dev_priv
->pps_mutex
);
286 static void pps_unlock(struct intel_dp
*intel_dp
)
288 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
289 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
290 struct drm_device
*dev
= encoder
->base
.dev
;
291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
292 enum intel_display_power_domain power_domain
;
294 mutex_unlock(&dev_priv
->pps_mutex
);
296 power_domain
= intel_display_port_aux_power_domain(encoder
);
297 intel_display_power_put(dev_priv
, power_domain
);
301 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
303 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
304 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 enum pipe pipe
= intel_dp
->pps_pipe
;
307 bool pll_enabled
, release_cl_override
= false;
308 enum dpio_phy phy
= DPIO_PHY(pipe
);
309 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
312 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
313 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
314 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
317 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
318 pipe_name(pipe
), port_name(intel_dig_port
->port
));
320 /* Preserve the BIOS-computed detected bit. This is
321 * supposed to be read-only.
323 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
324 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
325 DP
|= DP_PORT_WIDTH(1);
326 DP
|= DP_LINK_TRAIN_PAT_1
;
328 if (IS_CHERRYVIEW(dev
))
329 DP
|= DP_PIPE_SELECT_CHV(pipe
);
330 else if (pipe
== PIPE_B
)
331 DP
|= DP_PIPEB_SELECT
;
333 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
336 * The DPLL for the pipe must be enabled for this to work.
337 * So enable temporarily it if it's not already enabled.
340 release_cl_override
= IS_CHERRYVIEW(dev
) &&
341 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
343 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
344 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
348 * Similar magic as in intel_dp_enable_port().
349 * We _must_ do this port enable + disable trick
350 * to make this power seqeuencer lock onto the port.
351 * Otherwise even VDD force bit won't work.
353 I915_WRITE(intel_dp
->output_reg
, DP
);
354 POSTING_READ(intel_dp
->output_reg
);
356 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
357 POSTING_READ(intel_dp
->output_reg
);
359 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
360 POSTING_READ(intel_dp
->output_reg
);
363 vlv_force_pll_off(dev
, pipe
);
365 if (release_cl_override
)
366 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
371 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
373 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
374 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
376 struct intel_encoder
*encoder
;
377 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
380 lockdep_assert_held(&dev_priv
->pps_mutex
);
382 /* We should never land here with regular DP ports */
383 WARN_ON(!is_edp(intel_dp
));
385 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
386 return intel_dp
->pps_pipe
;
389 * We don't have power sequencer currently.
390 * Pick one that's not used by other ports.
392 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
394 struct intel_dp
*tmp
;
396 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
399 tmp
= enc_to_intel_dp(&encoder
->base
);
401 if (tmp
->pps_pipe
!= INVALID_PIPE
)
402 pipes
&= ~(1 << tmp
->pps_pipe
);
406 * Didn't find one. This should not happen since there
407 * are two power sequencers and up to two eDP ports.
409 if (WARN_ON(pipes
== 0))
412 pipe
= ffs(pipes
) - 1;
414 vlv_steal_power_sequencer(dev
, pipe
);
415 intel_dp
->pps_pipe
= pipe
;
417 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
418 pipe_name(intel_dp
->pps_pipe
),
419 port_name(intel_dig_port
->port
));
421 /* init power sequencer on this pipe and port */
422 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
423 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
426 * Even vdd force doesn't work until we've made
427 * the power sequencer lock in on the port.
429 vlv_power_sequencer_kick(intel_dp
);
431 return intel_dp
->pps_pipe
;
434 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
437 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
443 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
449 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
456 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
458 vlv_pipe_check pipe_check
)
462 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
463 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
464 PANEL_PORT_SELECT_MASK
;
466 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
469 if (!pipe_check(dev_priv
, pipe
))
479 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
481 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
482 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
484 enum port port
= intel_dig_port
->port
;
486 lockdep_assert_held(&dev_priv
->pps_mutex
);
488 /* try to find a pipe with this port selected */
489 /* first pick one where the panel is on */
490 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
492 /* didn't find one? pick one where vdd is on */
493 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
494 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
495 vlv_pipe_has_vdd_on
);
496 /* didn't find one? pick one with just the correct port */
497 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
498 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
501 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
502 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
503 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
508 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
509 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
511 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
512 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
515 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
517 struct drm_device
*dev
= dev_priv
->dev
;
518 struct intel_encoder
*encoder
;
520 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
524 * We can't grab pps_mutex here due to deadlock with power_domain
525 * mutex when power_domain functions are called while holding pps_mutex.
526 * That also means that in order to use pps_pipe the code needs to
527 * hold both a power domain reference and pps_mutex, and the power domain
528 * reference get/put must be done while _not_ holding pps_mutex.
529 * pps_{lock,unlock}() do these steps in the correct order, so one
530 * should use them always.
533 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
534 struct intel_dp
*intel_dp
;
536 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
539 intel_dp
= enc_to_intel_dp(&encoder
->base
);
540 intel_dp
->pps_pipe
= INVALID_PIPE
;
544 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
546 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
549 return BXT_PP_CONTROL(0);
550 else if (HAS_PCH_SPLIT(dev
))
551 return PCH_PP_CONTROL
;
553 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
556 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
558 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
561 return BXT_PP_STATUS(0);
562 else if (HAS_PCH_SPLIT(dev
))
563 return PCH_PP_STATUS
;
565 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
568 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
569 This function only applicable when panel PM state is not to be tracked */
570 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
573 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
575 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
578 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
583 if (IS_VALLEYVIEW(dev
)) {
584 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
585 u32 pp_ctrl_reg
, pp_div_reg
;
588 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
589 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
590 pp_div
= I915_READ(pp_div_reg
);
591 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
593 /* 0x1F write to PP_DIV_REG sets max cycle delay */
594 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
595 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
596 msleep(intel_dp
->panel_power_cycle_delay
);
599 pps_unlock(intel_dp
);
604 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
606 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
609 lockdep_assert_held(&dev_priv
->pps_mutex
);
611 if (IS_VALLEYVIEW(dev
) &&
612 intel_dp
->pps_pipe
== INVALID_PIPE
)
615 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
618 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
620 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
623 lockdep_assert_held(&dev_priv
->pps_mutex
);
625 if (IS_VALLEYVIEW(dev
) &&
626 intel_dp
->pps_pipe
== INVALID_PIPE
)
629 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
633 intel_dp_check_edp(struct intel_dp
*intel_dp
)
635 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
638 if (!is_edp(intel_dp
))
641 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
642 WARN(1, "eDP powered off while attempting aux channel communication.\n");
643 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
644 I915_READ(_pp_stat_reg(intel_dp
)),
645 I915_READ(_pp_ctrl_reg(intel_dp
)));
650 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
652 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
653 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
655 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
659 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
661 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
662 msecs_to_jiffies_timeout(10));
664 done
= wait_for_atomic(C
, 10) == 0;
666 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
673 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
675 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
676 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
679 * The clock divider is based off the hrawclk, and would like to run at
680 * 2MHz. So, take the hrawclk value and divide by 2 and use that
682 return index
? 0 : intel_hrawclk(dev
) / 2;
685 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
687 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
688 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
694 if (intel_dig_port
->port
== PORT_A
) {
695 return DIV_ROUND_UP(dev_priv
->cdclk_freq
, 2000);
698 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
702 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
704 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
705 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
708 if (intel_dig_port
->port
== PORT_A
) {
711 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
712 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
713 /* Workaround for non-ULT HSW */
720 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
724 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
726 return index
? 0 : 100;
729 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
732 * SKL doesn't need us to program the AUX clock divider (Hardware will
733 * derive the clock from CDCLK automatically). We still implement the
734 * get_aux_clock_divider vfunc to plug-in into the existing code.
736 return index
? 0 : 1;
739 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
742 uint32_t aux_clock_divider
)
744 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
745 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
746 uint32_t precharge
, timeout
;
753 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
754 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
756 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
758 return DP_AUX_CH_CTL_SEND_BUSY
|
760 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
761 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
763 DP_AUX_CH_CTL_RECEIVE_ERROR
|
764 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
765 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
766 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
769 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
774 return DP_AUX_CH_CTL_SEND_BUSY
|
776 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
777 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
778 DP_AUX_CH_CTL_TIME_OUT_1600us
|
779 DP_AUX_CH_CTL_RECEIVE_ERROR
|
780 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
781 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
785 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
786 const uint8_t *send
, int send_bytes
,
787 uint8_t *recv
, int recv_size
)
789 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
790 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
792 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
793 uint32_t aux_clock_divider
;
794 int i
, ret
, recv_bytes
;
797 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
803 * We will be called with VDD already enabled for dpcd/edid/oui reads.
804 * In such cases we want to leave VDD enabled and it's up to upper layers
805 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
808 vdd
= edp_panel_vdd_on(intel_dp
);
810 /* dp aux is extremely sensitive to irq latency, hence request the
811 * lowest possible wakeup latency and so prevent the cpu from going into
814 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
816 intel_dp_check_edp(intel_dp
);
818 /* Try to wait for any previous AUX channel activity */
819 for (try = 0; try < 3; try++) {
820 status
= I915_READ_NOTRACE(ch_ctl
);
821 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
827 static u32 last_status
= -1;
828 const u32 status
= I915_READ(ch_ctl
);
830 if (status
!= last_status
) {
831 WARN(1, "dp_aux_ch not started status 0x%08x\n",
833 last_status
= status
;
840 /* Only 5 data registers! */
841 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
846 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
847 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
852 /* Must try at least 3 times according to DP spec */
853 for (try = 0; try < 5; try++) {
854 /* Load the send data into the aux channel data registers */
855 for (i
= 0; i
< send_bytes
; i
+= 4)
856 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
857 intel_dp_pack_aux(send
+ i
,
860 /* Send the command and wait for it to complete */
861 I915_WRITE(ch_ctl
, send_ctl
);
863 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
865 /* Clear done status and any errors */
869 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
870 DP_AUX_CH_CTL_RECEIVE_ERROR
);
872 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
875 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
876 * 400us delay required for errors and timeouts
877 * Timeout errors from the HW already meet this
878 * requirement so skip to next iteration
880 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
881 usleep_range(400, 500);
884 if (status
& DP_AUX_CH_CTL_DONE
)
889 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
890 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
899 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
907 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
913 /* Unload any bytes sent back from the other side */
914 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
916 if (recv_bytes
> recv_size
)
917 recv_bytes
= recv_size
;
919 for (i
= 0; i
< recv_bytes
; i
+= 4)
920 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
921 recv
+ i
, recv_bytes
- i
);
925 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
928 edp_panel_vdd_off(intel_dp
, false);
930 pps_unlock(intel_dp
);
935 #define BARE_ADDRESS_SIZE 3
936 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
938 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
940 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
941 uint8_t txbuf
[20], rxbuf
[20];
942 size_t txsize
, rxsize
;
945 txbuf
[0] = (msg
->request
<< 4) |
946 ((msg
->address
>> 16) & 0xf);
947 txbuf
[1] = (msg
->address
>> 8) & 0xff;
948 txbuf
[2] = msg
->address
& 0xff;
949 txbuf
[3] = msg
->size
- 1;
951 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
952 case DP_AUX_NATIVE_WRITE
:
953 case DP_AUX_I2C_WRITE
:
954 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
955 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
956 rxsize
= 2; /* 0 or 1 data bytes */
958 if (WARN_ON(txsize
> 20))
961 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
963 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
965 msg
->reply
= rxbuf
[0] >> 4;
968 /* Number of bytes written in a short write. */
969 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
971 /* Return payload size. */
977 case DP_AUX_NATIVE_READ
:
978 case DP_AUX_I2C_READ
:
979 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
980 rxsize
= msg
->size
+ 1;
982 if (WARN_ON(rxsize
> 20))
985 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
987 msg
->reply
= rxbuf
[0] >> 4;
989 * Assume happy day, and copy the data. The caller is
990 * expected to check msg->reply before touching it.
992 * Return payload size.
995 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1007 static uint32_t g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1014 return DP_AUX_CH_CTL(port
);
1017 return DP_AUX_CH_CTL(PORT_B
);
1021 static uint32_t g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1022 enum port port
, int index
)
1028 return DP_AUX_CH_DATA(port
, index
);
1031 return DP_AUX_CH_DATA(PORT_B
, index
);
1035 static uint32_t ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1040 return DP_AUX_CH_CTL(port
);
1044 return PCH_DP_AUX_CH_CTL(port
);
1047 return DP_AUX_CH_CTL(PORT_A
);
1051 static uint32_t ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1052 enum port port
, int index
)
1056 return DP_AUX_CH_DATA(port
, index
);
1060 return PCH_DP_AUX_CH_DATA(port
, index
);
1063 return DP_AUX_CH_DATA(PORT_A
, index
);
1068 * On SKL we don't have Aux for port E so we rely
1069 * on VBT to set a proper alternate aux channel.
1071 static enum port
skl_porte_aux_port(struct drm_i915_private
*dev_priv
)
1073 const struct ddi_vbt_port_info
*info
=
1074 &dev_priv
->vbt
.ddi_port_info
[PORT_E
];
1076 switch (info
->alternate_aux_channel
) {
1086 MISSING_CASE(info
->alternate_aux_channel
);
1091 static uint32_t skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1095 port
= skl_porte_aux_port(dev_priv
);
1102 return DP_AUX_CH_CTL(port
);
1105 return DP_AUX_CH_CTL(PORT_A
);
1109 static uint32_t skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1110 enum port port
, int index
)
1113 port
= skl_porte_aux_port(dev_priv
);
1120 return DP_AUX_CH_DATA(port
, index
);
1123 return DP_AUX_CH_DATA(PORT_A
, index
);
1127 static uint32_t intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1130 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1131 return skl_aux_ctl_reg(dev_priv
, port
);
1132 else if (HAS_PCH_SPLIT(dev_priv
))
1133 return ilk_aux_ctl_reg(dev_priv
, port
);
1135 return g4x_aux_ctl_reg(dev_priv
, port
);
1138 static uint32_t intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1139 enum port port
, int index
)
1141 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1142 return skl_aux_data_reg(dev_priv
, port
, index
);
1143 else if (HAS_PCH_SPLIT(dev_priv
))
1144 return ilk_aux_data_reg(dev_priv
, port
, index
);
1146 return g4x_aux_data_reg(dev_priv
, port
, index
);
1149 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1151 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1152 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1155 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1156 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1157 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1161 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1163 drm_dp_aux_unregister(&intel_dp
->aux
);
1164 kfree(intel_dp
->aux
.name
);
1168 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1170 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1171 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1172 enum port port
= intel_dig_port
->port
;
1175 intel_aux_reg_init(intel_dp
);
1177 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1178 if (!intel_dp
->aux
.name
)
1181 intel_dp
->aux
.dev
= dev
->dev
;
1182 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1184 DRM_DEBUG_KMS("registering %s bus for %s\n",
1186 connector
->base
.kdev
->kobj
.name
);
1188 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1190 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1191 intel_dp
->aux
.name
, ret
);
1192 kfree(intel_dp
->aux
.name
);
1196 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1197 &intel_dp
->aux
.ddc
.dev
.kobj
,
1198 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1200 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
1201 intel_dp
->aux
.name
, ret
);
1202 intel_dp_aux_fini(intel_dp
);
1210 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1212 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1214 if (!intel_connector
->mst_port
)
1215 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1216 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1217 intel_connector_unregister(intel_connector
);
1221 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
)
1225 memset(&pipe_config
->dpll_hw_state
, 0,
1226 sizeof(pipe_config
->dpll_hw_state
));
1228 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1229 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1230 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1232 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1233 switch (pipe_config
->port_clock
/ 2) {
1235 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
1239 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
,
1243 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
,
1247 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
,
1250 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1251 results in CDCLK change. Need to handle the change of CDCLK by
1252 disabling pipes and re-enabling them */
1254 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
1258 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
,
1263 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1267 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
)
1269 memset(&pipe_config
->dpll_hw_state
, 0,
1270 sizeof(pipe_config
->dpll_hw_state
));
1272 switch (pipe_config
->port_clock
/ 2) {
1274 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1277 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1280 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1286 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1288 if (intel_dp
->num_sink_rates
) {
1289 *sink_rates
= intel_dp
->sink_rates
;
1290 return intel_dp
->num_sink_rates
;
1293 *sink_rates
= default_rates
;
1295 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1298 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1300 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1301 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1303 /* WaDisableHBR2:skl */
1304 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
))
1307 if ((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) || IS_BROADWELL(dev
) ||
1308 (INTEL_INFO(dev
)->gen
>= 9))
1315 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1317 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1318 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1321 if (IS_BROXTON(dev
)) {
1322 *source_rates
= bxt_rates
;
1323 size
= ARRAY_SIZE(bxt_rates
);
1324 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1325 *source_rates
= skl_rates
;
1326 size
= ARRAY_SIZE(skl_rates
);
1328 *source_rates
= default_rates
;
1329 size
= ARRAY_SIZE(default_rates
);
1332 /* This depends on the fact that 5.4 is last value in the array */
1333 if (!intel_dp_source_supports_hbr2(intel_dp
))
1340 intel_dp_set_clock(struct intel_encoder
*encoder
,
1341 struct intel_crtc_state
*pipe_config
)
1343 struct drm_device
*dev
= encoder
->base
.dev
;
1344 const struct dp_link_dpll
*divisor
= NULL
;
1348 divisor
= gen4_dpll
;
1349 count
= ARRAY_SIZE(gen4_dpll
);
1350 } else if (HAS_PCH_SPLIT(dev
)) {
1352 count
= ARRAY_SIZE(pch_dpll
);
1353 } else if (IS_CHERRYVIEW(dev
)) {
1355 count
= ARRAY_SIZE(chv_dpll
);
1356 } else if (IS_VALLEYVIEW(dev
)) {
1358 count
= ARRAY_SIZE(vlv_dpll
);
1361 if (divisor
&& count
) {
1362 for (i
= 0; i
< count
; i
++) {
1363 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1364 pipe_config
->dpll
= divisor
[i
].dpll
;
1365 pipe_config
->clock_set
= true;
1372 static int intersect_rates(const int *source_rates
, int source_len
,
1373 const int *sink_rates
, int sink_len
,
1376 int i
= 0, j
= 0, k
= 0;
1378 while (i
< source_len
&& j
< sink_len
) {
1379 if (source_rates
[i
] == sink_rates
[j
]) {
1380 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1382 common_rates
[k
] = source_rates
[i
];
1386 } else if (source_rates
[i
] < sink_rates
[j
]) {
1395 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1398 const int *source_rates
, *sink_rates
;
1399 int source_len
, sink_len
;
1401 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1402 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1404 return intersect_rates(source_rates
, source_len
,
1405 sink_rates
, sink_len
,
1409 static void snprintf_int_array(char *str
, size_t len
,
1410 const int *array
, int nelem
)
1416 for (i
= 0; i
< nelem
; i
++) {
1417 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1425 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1427 const int *source_rates
, *sink_rates
;
1428 int source_len
, sink_len
, common_len
;
1429 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1430 char str
[128]; /* FIXME: too big for stack? */
1432 if ((drm_debug
& DRM_UT_KMS
) == 0)
1435 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1436 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1437 DRM_DEBUG_KMS("source rates: %s\n", str
);
1439 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1440 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1441 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1443 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1444 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1445 DRM_DEBUG_KMS("common rates: %s\n", str
);
1448 static int rate_to_index(int find
, const int *rates
)
1452 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1453 if (find
== rates
[i
])
1460 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1462 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1465 len
= intel_dp_common_rates(intel_dp
, rates
);
1466 if (WARN_ON(len
<= 0))
1469 return rates
[rate_to_index(0, rates
) - 1];
1472 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1474 return rate_to_index(rate
, intel_dp
->sink_rates
);
1477 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1478 uint8_t *link_bw
, uint8_t *rate_select
)
1480 if (intel_dp
->num_sink_rates
) {
1483 intel_dp_rate_select(intel_dp
, port_clock
);
1485 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1491 intel_dp_compute_config(struct intel_encoder
*encoder
,
1492 struct intel_crtc_state
*pipe_config
)
1494 struct drm_device
*dev
= encoder
->base
.dev
;
1495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1496 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1497 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1498 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1499 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1500 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1501 int lane_count
, clock
;
1502 int min_lane_count
= 1;
1503 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1504 /* Conveniently, the link BW constants become indices with a shift...*/
1508 int link_avail
, link_clock
;
1509 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1511 uint8_t link_bw
, rate_select
;
1513 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1515 /* No common link rates between source and sink */
1516 WARN_ON(common_len
<= 0);
1518 max_clock
= common_len
- 1;
1520 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1521 pipe_config
->has_pch_encoder
= true;
1523 pipe_config
->has_dp_encoder
= true;
1524 pipe_config
->has_drrs
= false;
1525 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1527 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1528 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1531 if (INTEL_INFO(dev
)->gen
>= 9) {
1533 ret
= skl_update_scaler_crtc(pipe_config
);
1538 if (HAS_GMCH_DISPLAY(dev
))
1539 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1540 intel_connector
->panel
.fitting_mode
);
1542 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1543 intel_connector
->panel
.fitting_mode
);
1546 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1549 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1550 "max bw %d pixel clock %iKHz\n",
1551 max_lane_count
, common_rates
[max_clock
],
1552 adjusted_mode
->crtc_clock
);
1554 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1555 * bpc in between. */
1556 bpp
= pipe_config
->pipe_bpp
;
1557 if (is_edp(intel_dp
)) {
1559 /* Get bpp from vbt only for panels that dont have bpp in edid */
1560 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1561 (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
)) {
1562 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1563 dev_priv
->vbt
.edp_bpp
);
1564 bpp
= dev_priv
->vbt
.edp_bpp
;
1568 * Use the maximum clock and number of lanes the eDP panel
1569 * advertizes being capable of. The panels are generally
1570 * designed to support only a single clock and lane
1571 * configuration, and typically these values correspond to the
1572 * native resolution of the panel.
1574 min_lane_count
= max_lane_count
;
1575 min_clock
= max_clock
;
1578 for (; bpp
>= 6*3; bpp
-= 2*3) {
1579 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1582 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1583 for (lane_count
= min_lane_count
;
1584 lane_count
<= max_lane_count
;
1587 link_clock
= common_rates
[clock
];
1588 link_avail
= intel_dp_max_data_rate(link_clock
,
1591 if (mode_rate
<= link_avail
) {
1601 if (intel_dp
->color_range_auto
) {
1604 * CEA-861-E - 5.1 Default Encoding Parameters
1605 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1607 pipe_config
->limited_color_range
=
1608 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1610 pipe_config
->limited_color_range
=
1611 intel_dp
->limited_color_range
;
1614 pipe_config
->lane_count
= lane_count
;
1616 pipe_config
->pipe_bpp
= bpp
;
1617 pipe_config
->port_clock
= common_rates
[clock
];
1619 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1620 &link_bw
, &rate_select
);
1622 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1623 link_bw
, rate_select
, pipe_config
->lane_count
,
1624 pipe_config
->port_clock
, bpp
);
1625 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1626 mode_rate
, link_avail
);
1628 intel_link_compute_m_n(bpp
, lane_count
,
1629 adjusted_mode
->crtc_clock
,
1630 pipe_config
->port_clock
,
1631 &pipe_config
->dp_m_n
);
1633 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1634 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1635 pipe_config
->has_drrs
= true;
1636 intel_link_compute_m_n(bpp
, lane_count
,
1637 intel_connector
->panel
.downclock_mode
->clock
,
1638 pipe_config
->port_clock
,
1639 &pipe_config
->dp_m2_n2
);
1642 if ((IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) && is_edp(intel_dp
))
1643 skl_edp_set_pll_config(pipe_config
);
1644 else if (IS_BROXTON(dev
))
1645 /* handled in ddi */;
1646 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1647 hsw_dp_set_ddi_pll_sel(pipe_config
);
1649 intel_dp_set_clock(encoder
, pipe_config
);
1654 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1655 const struct intel_crtc_state
*pipe_config
)
1657 intel_dp
->link_rate
= pipe_config
->port_clock
;
1658 intel_dp
->lane_count
= pipe_config
->lane_count
;
1661 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1663 struct drm_device
*dev
= encoder
->base
.dev
;
1664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1665 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1666 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1667 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1668 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1670 intel_dp_set_link_params(intel_dp
, crtc
->config
);
1673 * There are four kinds of DP registers:
1680 * IBX PCH and CPU are the same for almost everything,
1681 * except that the CPU DP PLL is configured in this
1684 * CPT PCH is quite different, having many bits moved
1685 * to the TRANS_DP_CTL register instead. That
1686 * configuration happens (oddly) in ironlake_pch_enable
1689 /* Preserve the BIOS-computed detected bit. This is
1690 * supposed to be read-only.
1692 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1694 /* Handle DP bits in common between all three register formats */
1695 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1696 intel_dp
->DP
|= DP_PORT_WIDTH(crtc
->config
->lane_count
);
1698 /* Split out the IBX/CPU vs CPT settings */
1700 if (IS_GEN7(dev
) && port
== PORT_A
) {
1701 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1702 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1703 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1704 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1705 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1707 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1708 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1710 intel_dp
->DP
|= crtc
->pipe
<< 29;
1711 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1714 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1716 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1717 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1718 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1720 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1721 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1723 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1724 crtc
->config
->limited_color_range
)
1725 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1727 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1728 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1729 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1730 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1731 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1733 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1734 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1736 if (IS_CHERRYVIEW(dev
))
1737 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1738 else if (crtc
->pipe
== PIPE_B
)
1739 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1743 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1744 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1746 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1747 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1749 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1750 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1752 static void wait_panel_status(struct intel_dp
*intel_dp
,
1756 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1758 u32 pp_stat_reg
, pp_ctrl_reg
;
1760 lockdep_assert_held(&dev_priv
->pps_mutex
);
1762 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1763 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1765 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1767 I915_READ(pp_stat_reg
),
1768 I915_READ(pp_ctrl_reg
));
1770 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1771 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1772 I915_READ(pp_stat_reg
),
1773 I915_READ(pp_ctrl_reg
));
1776 DRM_DEBUG_KMS("Wait complete\n");
1779 static void wait_panel_on(struct intel_dp
*intel_dp
)
1781 DRM_DEBUG_KMS("Wait for panel power on\n");
1782 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1785 static void wait_panel_off(struct intel_dp
*intel_dp
)
1787 DRM_DEBUG_KMS("Wait for panel power off time\n");
1788 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1791 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1793 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1795 /* When we disable the VDD override bit last we have to do the manual
1797 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1798 intel_dp
->panel_power_cycle_delay
);
1800 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1803 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1805 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1806 intel_dp
->backlight_on_delay
);
1809 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1811 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1812 intel_dp
->backlight_off_delay
);
1815 /* Read the current pp_control value, unlocking the register if it
1819 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1821 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1825 lockdep_assert_held(&dev_priv
->pps_mutex
);
1827 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1828 if (!IS_BROXTON(dev
)) {
1829 control
&= ~PANEL_UNLOCK_MASK
;
1830 control
|= PANEL_UNLOCK_REGS
;
1836 * Must be paired with edp_panel_vdd_off().
1837 * Must hold pps_mutex around the whole on/off sequence.
1838 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1840 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1842 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1843 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1844 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1846 enum intel_display_power_domain power_domain
;
1848 u32 pp_stat_reg
, pp_ctrl_reg
;
1849 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1851 lockdep_assert_held(&dev_priv
->pps_mutex
);
1853 if (!is_edp(intel_dp
))
1856 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1857 intel_dp
->want_panel_vdd
= true;
1859 if (edp_have_panel_vdd(intel_dp
))
1860 return need_to_disable
;
1862 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1863 intel_display_power_get(dev_priv
, power_domain
);
1865 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1866 port_name(intel_dig_port
->port
));
1868 if (!edp_have_panel_power(intel_dp
))
1869 wait_panel_power_cycle(intel_dp
);
1871 pp
= ironlake_get_pp_control(intel_dp
);
1872 pp
|= EDP_FORCE_VDD
;
1874 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1875 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1877 I915_WRITE(pp_ctrl_reg
, pp
);
1878 POSTING_READ(pp_ctrl_reg
);
1879 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1880 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1882 * If the panel wasn't on, delay before accessing aux channel
1884 if (!edp_have_panel_power(intel_dp
)) {
1885 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1886 port_name(intel_dig_port
->port
));
1887 msleep(intel_dp
->panel_power_up_delay
);
1890 return need_to_disable
;
1894 * Must be paired with intel_edp_panel_vdd_off() or
1895 * intel_edp_panel_off().
1896 * Nested calls to these functions are not allowed since
1897 * we drop the lock. Caller must use some higher level
1898 * locking to prevent nested calls from other threads.
1900 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1904 if (!is_edp(intel_dp
))
1908 vdd
= edp_panel_vdd_on(intel_dp
);
1909 pps_unlock(intel_dp
);
1911 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1912 port_name(dp_to_dig_port(intel_dp
)->port
));
1915 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1917 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1919 struct intel_digital_port
*intel_dig_port
=
1920 dp_to_dig_port(intel_dp
);
1921 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1922 enum intel_display_power_domain power_domain
;
1924 u32 pp_stat_reg
, pp_ctrl_reg
;
1926 lockdep_assert_held(&dev_priv
->pps_mutex
);
1928 WARN_ON(intel_dp
->want_panel_vdd
);
1930 if (!edp_have_panel_vdd(intel_dp
))
1933 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1934 port_name(intel_dig_port
->port
));
1936 pp
= ironlake_get_pp_control(intel_dp
);
1937 pp
&= ~EDP_FORCE_VDD
;
1939 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1940 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1942 I915_WRITE(pp_ctrl_reg
, pp
);
1943 POSTING_READ(pp_ctrl_reg
);
1945 /* Make sure sequencer is idle before allowing subsequent activity */
1946 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1947 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1949 if ((pp
& POWER_TARGET_ON
) == 0)
1950 intel_dp
->last_power_cycle
= jiffies
;
1952 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1953 intel_display_power_put(dev_priv
, power_domain
);
1956 static void edp_panel_vdd_work(struct work_struct
*__work
)
1958 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1959 struct intel_dp
, panel_vdd_work
);
1962 if (!intel_dp
->want_panel_vdd
)
1963 edp_panel_vdd_off_sync(intel_dp
);
1964 pps_unlock(intel_dp
);
1967 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1969 unsigned long delay
;
1972 * Queue the timer to fire a long time from now (relative to the power
1973 * down delay) to keep the panel power up across a sequence of
1976 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1977 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1981 * Must be paired with edp_panel_vdd_on().
1982 * Must hold pps_mutex around the whole on/off sequence.
1983 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1985 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1987 struct drm_i915_private
*dev_priv
=
1988 intel_dp_to_dev(intel_dp
)->dev_private
;
1990 lockdep_assert_held(&dev_priv
->pps_mutex
);
1992 if (!is_edp(intel_dp
))
1995 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1996 port_name(dp_to_dig_port(intel_dp
)->port
));
1998 intel_dp
->want_panel_vdd
= false;
2001 edp_panel_vdd_off_sync(intel_dp
);
2003 edp_panel_vdd_schedule_off(intel_dp
);
2006 static void edp_panel_on(struct intel_dp
*intel_dp
)
2008 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2013 lockdep_assert_held(&dev_priv
->pps_mutex
);
2015 if (!is_edp(intel_dp
))
2018 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2019 port_name(dp_to_dig_port(intel_dp
)->port
));
2021 if (WARN(edp_have_panel_power(intel_dp
),
2022 "eDP port %c panel power already on\n",
2023 port_name(dp_to_dig_port(intel_dp
)->port
)))
2026 wait_panel_power_cycle(intel_dp
);
2028 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2029 pp
= ironlake_get_pp_control(intel_dp
);
2031 /* ILK workaround: disable reset around power sequence */
2032 pp
&= ~PANEL_POWER_RESET
;
2033 I915_WRITE(pp_ctrl_reg
, pp
);
2034 POSTING_READ(pp_ctrl_reg
);
2037 pp
|= POWER_TARGET_ON
;
2039 pp
|= PANEL_POWER_RESET
;
2041 I915_WRITE(pp_ctrl_reg
, pp
);
2042 POSTING_READ(pp_ctrl_reg
);
2044 wait_panel_on(intel_dp
);
2045 intel_dp
->last_power_on
= jiffies
;
2048 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2049 I915_WRITE(pp_ctrl_reg
, pp
);
2050 POSTING_READ(pp_ctrl_reg
);
2054 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2056 if (!is_edp(intel_dp
))
2060 edp_panel_on(intel_dp
);
2061 pps_unlock(intel_dp
);
2065 static void edp_panel_off(struct intel_dp
*intel_dp
)
2067 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2068 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2069 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2071 enum intel_display_power_domain power_domain
;
2075 lockdep_assert_held(&dev_priv
->pps_mutex
);
2077 if (!is_edp(intel_dp
))
2080 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2081 port_name(dp_to_dig_port(intel_dp
)->port
));
2083 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2084 port_name(dp_to_dig_port(intel_dp
)->port
));
2086 pp
= ironlake_get_pp_control(intel_dp
);
2087 /* We need to switch off panel power _and_ force vdd, for otherwise some
2088 * panels get very unhappy and cease to work. */
2089 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2092 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2094 intel_dp
->want_panel_vdd
= false;
2096 I915_WRITE(pp_ctrl_reg
, pp
);
2097 POSTING_READ(pp_ctrl_reg
);
2099 intel_dp
->last_power_cycle
= jiffies
;
2100 wait_panel_off(intel_dp
);
2102 /* We got a reference when we enabled the VDD. */
2103 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2104 intel_display_power_put(dev_priv
, power_domain
);
2107 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2109 if (!is_edp(intel_dp
))
2113 edp_panel_off(intel_dp
);
2114 pps_unlock(intel_dp
);
2117 /* Enable backlight in the panel power control. */
2118 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2120 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2121 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2127 * If we enable the backlight right away following a panel power
2128 * on, we may see slight flicker as the panel syncs with the eDP
2129 * link. So delay a bit to make sure the image is solid before
2130 * allowing it to appear.
2132 wait_backlight_on(intel_dp
);
2136 pp
= ironlake_get_pp_control(intel_dp
);
2137 pp
|= EDP_BLC_ENABLE
;
2139 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2141 I915_WRITE(pp_ctrl_reg
, pp
);
2142 POSTING_READ(pp_ctrl_reg
);
2144 pps_unlock(intel_dp
);
2147 /* Enable backlight PWM and backlight PP control. */
2148 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2150 if (!is_edp(intel_dp
))
2153 DRM_DEBUG_KMS("\n");
2155 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2156 _intel_edp_backlight_on(intel_dp
);
2159 /* Disable backlight in the panel power control. */
2160 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2162 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2167 if (!is_edp(intel_dp
))
2172 pp
= ironlake_get_pp_control(intel_dp
);
2173 pp
&= ~EDP_BLC_ENABLE
;
2175 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2177 I915_WRITE(pp_ctrl_reg
, pp
);
2178 POSTING_READ(pp_ctrl_reg
);
2180 pps_unlock(intel_dp
);
2182 intel_dp
->last_backlight_off
= jiffies
;
2183 edp_wait_backlight_off(intel_dp
);
2186 /* Disable backlight PP control and backlight PWM. */
2187 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2189 if (!is_edp(intel_dp
))
2192 DRM_DEBUG_KMS("\n");
2194 _intel_edp_backlight_off(intel_dp
);
2195 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2199 * Hook for controlling the panel power control backlight through the bl_power
2200 * sysfs attribute. Take care to handle multiple calls.
2202 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2205 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2209 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2210 pps_unlock(intel_dp
);
2212 if (is_enabled
== enable
)
2215 DRM_DEBUG_KMS("panel power control backlight %s\n",
2216 enable
? "enable" : "disable");
2219 _intel_edp_backlight_on(intel_dp
);
2221 _intel_edp_backlight_off(intel_dp
);
2224 static const char *state_string(bool enabled
)
2226 return enabled
? "on" : "off";
2229 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2231 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2232 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2233 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2235 I915_STATE_WARN(cur_state
!= state
,
2236 "DP port %c state assertion failure (expected %s, current %s)\n",
2237 port_name(dig_port
->port
),
2238 state_string(state
), state_string(cur_state
));
2240 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2242 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2244 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2246 I915_STATE_WARN(cur_state
!= state
,
2247 "eDP PLL state assertion failure (expected %s, current %s)\n",
2248 state_string(state
), state_string(cur_state
));
2250 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2251 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2253 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2255 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2256 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2257 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2259 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2260 assert_dp_port_disabled(intel_dp
);
2261 assert_edp_pll_disabled(dev_priv
);
2263 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2264 crtc
->config
->port_clock
);
2266 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2268 if (crtc
->config
->port_clock
== 162000)
2269 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2271 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2273 I915_WRITE(DP_A
, intel_dp
->DP
);
2277 intel_dp
->DP
|= DP_PLL_ENABLE
;
2279 I915_WRITE(DP_A
, intel_dp
->DP
);
2284 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2286 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2287 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2288 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2290 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2291 assert_dp_port_disabled(intel_dp
);
2292 assert_edp_pll_enabled(dev_priv
);
2294 DRM_DEBUG_KMS("disabling eDP PLL\n");
2296 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2298 I915_WRITE(DP_A
, intel_dp
->DP
);
2303 /* If the sink supports it, try to set the power state appropriately */
2304 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2308 /* Should have a valid DPCD by this point */
2309 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2312 if (mode
!= DRM_MODE_DPMS_ON
) {
2313 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2317 * When turning on, we need to retry for 1ms to give the sink
2320 for (i
= 0; i
< 3; i
++) {
2321 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2330 DRM_DEBUG_KMS("failed to %s sink power state\n",
2331 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2334 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2337 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2338 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2339 struct drm_device
*dev
= encoder
->base
.dev
;
2340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2341 enum intel_display_power_domain power_domain
;
2344 power_domain
= intel_display_port_power_domain(encoder
);
2345 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2348 tmp
= I915_READ(intel_dp
->output_reg
);
2350 if (!(tmp
& DP_PORT_EN
))
2353 if (IS_GEN7(dev
) && port
== PORT_A
) {
2354 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2355 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2358 for_each_pipe(dev_priv
, p
) {
2359 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2360 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2366 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2367 intel_dp
->output_reg
);
2368 } else if (IS_CHERRYVIEW(dev
)) {
2369 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2371 *pipe
= PORT_TO_PIPE(tmp
);
2377 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2378 struct intel_crtc_state
*pipe_config
)
2380 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2382 struct drm_device
*dev
= encoder
->base
.dev
;
2383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2384 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2385 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2388 tmp
= I915_READ(intel_dp
->output_reg
);
2390 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2392 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2393 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2395 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2396 flags
|= DRM_MODE_FLAG_PHSYNC
;
2398 flags
|= DRM_MODE_FLAG_NHSYNC
;
2400 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2401 flags
|= DRM_MODE_FLAG_PVSYNC
;
2403 flags
|= DRM_MODE_FLAG_NVSYNC
;
2405 if (tmp
& DP_SYNC_HS_HIGH
)
2406 flags
|= DRM_MODE_FLAG_PHSYNC
;
2408 flags
|= DRM_MODE_FLAG_NHSYNC
;
2410 if (tmp
& DP_SYNC_VS_HIGH
)
2411 flags
|= DRM_MODE_FLAG_PVSYNC
;
2413 flags
|= DRM_MODE_FLAG_NVSYNC
;
2416 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2418 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2419 tmp
& DP_COLOR_RANGE_16_235
)
2420 pipe_config
->limited_color_range
= true;
2422 pipe_config
->has_dp_encoder
= true;
2424 pipe_config
->lane_count
=
2425 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2427 intel_dp_get_m_n(crtc
, pipe_config
);
2429 if (port
== PORT_A
) {
2430 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2431 pipe_config
->port_clock
= 162000;
2433 pipe_config
->port_clock
= 270000;
2436 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2437 &pipe_config
->dp_m_n
);
2439 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2440 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2442 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2444 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2445 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2447 * This is a big fat ugly hack.
2449 * Some machines in UEFI boot mode provide us a VBT that has 18
2450 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2451 * unknown we fail to light up. Yet the same BIOS boots up with
2452 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2453 * max, not what it tells us to use.
2455 * Note: This will still be broken if the eDP panel is not lit
2456 * up by the BIOS, and thus we can't get the mode at module
2459 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2460 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2461 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2465 static void intel_disable_dp(struct intel_encoder
*encoder
)
2467 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2468 struct drm_device
*dev
= encoder
->base
.dev
;
2469 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2471 if (crtc
->config
->has_audio
)
2472 intel_audio_codec_disable(encoder
);
2474 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2475 intel_psr_disable(intel_dp
);
2477 /* Make sure the panel is off before trying to change the mode. But also
2478 * ensure that we have vdd while we switch off the panel. */
2479 intel_edp_panel_vdd_on(intel_dp
);
2480 intel_edp_backlight_off(intel_dp
);
2481 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2482 intel_edp_panel_off(intel_dp
);
2484 /* disable the port before the pipe on g4x */
2485 if (INTEL_INFO(dev
)->gen
< 5)
2486 intel_dp_link_down(intel_dp
);
2489 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2491 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2492 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2494 intel_dp_link_down(intel_dp
);
2496 /* Only ilk+ has port A */
2498 ironlake_edp_pll_off(intel_dp
);
2501 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2503 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2505 intel_dp_link_down(intel_dp
);
2508 static void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
2511 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2512 enum dpio_channel ch
= vlv_dport_to_channel(enc_to_dig_port(&encoder
->base
));
2513 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2514 enum pipe pipe
= crtc
->pipe
;
2517 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2519 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2521 val
|= DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
;
2522 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2524 if (crtc
->config
->lane_count
> 2) {
2525 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2527 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2529 val
|= DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
;
2530 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2533 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2534 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2536 val
&= ~DPIO_PCS_CLK_SOFT_RESET
;
2538 val
|= DPIO_PCS_CLK_SOFT_RESET
;
2539 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2541 if (crtc
->config
->lane_count
> 2) {
2542 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2543 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2545 val
&= ~DPIO_PCS_CLK_SOFT_RESET
;
2547 val
|= DPIO_PCS_CLK_SOFT_RESET
;
2548 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2552 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2554 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2555 struct drm_device
*dev
= encoder
->base
.dev
;
2556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2558 intel_dp_link_down(intel_dp
);
2560 mutex_lock(&dev_priv
->sb_lock
);
2562 /* Assert data lane reset */
2563 chv_data_lane_soft_reset(encoder
, true);
2565 mutex_unlock(&dev_priv
->sb_lock
);
2569 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2571 uint8_t dp_train_pat
)
2573 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2574 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2576 enum port port
= intel_dig_port
->port
;
2579 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2581 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2582 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2584 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2586 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2587 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2588 case DP_TRAINING_PATTERN_DISABLE
:
2589 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2592 case DP_TRAINING_PATTERN_1
:
2593 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2595 case DP_TRAINING_PATTERN_2
:
2596 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2598 case DP_TRAINING_PATTERN_3
:
2599 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2602 I915_WRITE(DP_TP_CTL(port
), temp
);
2604 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2605 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2606 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2608 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2609 case DP_TRAINING_PATTERN_DISABLE
:
2610 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2612 case DP_TRAINING_PATTERN_1
:
2613 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2615 case DP_TRAINING_PATTERN_2
:
2616 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2618 case DP_TRAINING_PATTERN_3
:
2619 DRM_ERROR("DP training pattern 3 not supported\n");
2620 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2625 if (IS_CHERRYVIEW(dev
))
2626 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2628 *DP
&= ~DP_LINK_TRAIN_MASK
;
2630 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2631 case DP_TRAINING_PATTERN_DISABLE
:
2632 *DP
|= DP_LINK_TRAIN_OFF
;
2634 case DP_TRAINING_PATTERN_1
:
2635 *DP
|= DP_LINK_TRAIN_PAT_1
;
2637 case DP_TRAINING_PATTERN_2
:
2638 *DP
|= DP_LINK_TRAIN_PAT_2
;
2640 case DP_TRAINING_PATTERN_3
:
2641 if (IS_CHERRYVIEW(dev
)) {
2642 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2644 DRM_ERROR("DP training pattern 3 not supported\n");
2645 *DP
|= DP_LINK_TRAIN_PAT_2
;
2652 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2654 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2656 struct intel_crtc
*crtc
=
2657 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
2659 /* enable with pattern 1 (as per spec) */
2660 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2661 DP_TRAINING_PATTERN_1
);
2663 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2664 POSTING_READ(intel_dp
->output_reg
);
2667 * Magic for VLV/CHV. We _must_ first set up the register
2668 * without actually enabling the port, and then do another
2669 * write to enable the port. Otherwise link training will
2670 * fail when the power sequencer is freshly used for this port.
2672 intel_dp
->DP
|= DP_PORT_EN
;
2673 if (crtc
->config
->has_audio
)
2674 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2676 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2677 POSTING_READ(intel_dp
->output_reg
);
2680 static void intel_enable_dp(struct intel_encoder
*encoder
)
2682 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2683 struct drm_device
*dev
= encoder
->base
.dev
;
2684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2685 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2686 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2687 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2688 enum pipe pipe
= crtc
->pipe
;
2690 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2695 if (IS_VALLEYVIEW(dev
))
2696 vlv_init_panel_power_sequencer(intel_dp
);
2698 intel_dp_enable_port(intel_dp
);
2700 if (port
== PORT_A
&& IS_GEN5(dev_priv
)) {
2702 * Underrun reporting for the other pipe was disabled in
2703 * g4x_pre_enable_dp(). The eDP PLL and port have now been
2704 * enabled, so it's now safe to re-enable underrun reporting.
2706 intel_wait_for_vblank_if_active(dev_priv
->dev
, !pipe
);
2707 intel_set_cpu_fifo_underrun_reporting(dev_priv
, !pipe
, true);
2708 intel_set_pch_fifo_underrun_reporting(dev_priv
, !pipe
, true);
2711 edp_panel_vdd_on(intel_dp
);
2712 edp_panel_on(intel_dp
);
2713 edp_panel_vdd_off(intel_dp
, true);
2715 pps_unlock(intel_dp
);
2717 if (IS_VALLEYVIEW(dev
)) {
2718 unsigned int lane_mask
= 0x0;
2720 if (IS_CHERRYVIEW(dev
))
2721 lane_mask
= intel_dp_unused_lane_mask(crtc
->config
->lane_count
);
2723 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2727 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2728 intel_dp_start_link_train(intel_dp
);
2729 intel_dp_stop_link_train(intel_dp
);
2731 if (crtc
->config
->has_audio
) {
2732 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2734 intel_audio_codec_enable(encoder
);
2738 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2740 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2742 intel_enable_dp(encoder
);
2743 intel_edp_backlight_on(intel_dp
);
2746 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2748 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2750 intel_edp_backlight_on(intel_dp
);
2751 intel_psr_enable(intel_dp
);
2754 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2756 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2757 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2758 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2759 enum pipe pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
2761 intel_dp_prepare(encoder
);
2763 if (port
== PORT_A
&& IS_GEN5(dev_priv
)) {
2765 * We get FIFO underruns on the other pipe when
2766 * enabling the CPU eDP PLL, and when enabling CPU
2767 * eDP port. We could potentially avoid the PLL
2768 * underrun with a vblank wait just prior to enabling
2769 * the PLL, but that doesn't appear to help the port
2770 * enable case. Just sweep it all under the rug.
2772 intel_set_cpu_fifo_underrun_reporting(dev_priv
, !pipe
, false);
2773 intel_set_pch_fifo_underrun_reporting(dev_priv
, !pipe
, false);
2776 /* Only ilk+ has port A */
2778 ironlake_edp_pll_on(intel_dp
);
2781 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2783 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2784 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2785 enum pipe pipe
= intel_dp
->pps_pipe
;
2786 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2788 edp_panel_vdd_off_sync(intel_dp
);
2791 * VLV seems to get confused when multiple power seqeuencers
2792 * have the same port selected (even if only one has power/vdd
2793 * enabled). The failure manifests as vlv_wait_port_ready() failing
2794 * CHV on the other hand doesn't seem to mind having the same port
2795 * selected in multiple power seqeuencers, but let's clear the
2796 * port select always when logically disconnecting a power sequencer
2799 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2800 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2801 I915_WRITE(pp_on_reg
, 0);
2802 POSTING_READ(pp_on_reg
);
2804 intel_dp
->pps_pipe
= INVALID_PIPE
;
2807 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2811 struct intel_encoder
*encoder
;
2813 lockdep_assert_held(&dev_priv
->pps_mutex
);
2815 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2818 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2820 struct intel_dp
*intel_dp
;
2823 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2826 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2827 port
= dp_to_dig_port(intel_dp
)->port
;
2829 if (intel_dp
->pps_pipe
!= pipe
)
2832 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2833 pipe_name(pipe
), port_name(port
));
2835 WARN(encoder
->base
.crtc
,
2836 "stealing pipe %c power sequencer from active eDP port %c\n",
2837 pipe_name(pipe
), port_name(port
));
2839 /* make sure vdd is off before we steal it */
2840 vlv_detach_power_sequencer(intel_dp
);
2844 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2846 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2847 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2848 struct drm_device
*dev
= encoder
->base
.dev
;
2849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2850 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2852 lockdep_assert_held(&dev_priv
->pps_mutex
);
2854 if (!is_edp(intel_dp
))
2857 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2861 * If another power sequencer was being used on this
2862 * port previously make sure to turn off vdd there while
2863 * we still have control of it.
2865 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2866 vlv_detach_power_sequencer(intel_dp
);
2869 * We may be stealing the power
2870 * sequencer from another port.
2872 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2874 /* now it's all ours */
2875 intel_dp
->pps_pipe
= crtc
->pipe
;
2877 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2878 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2880 /* init power sequencer on this pipe and port */
2881 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2882 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2885 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2887 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2888 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2889 struct drm_device
*dev
= encoder
->base
.dev
;
2890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2891 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2892 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2893 int pipe
= intel_crtc
->pipe
;
2896 mutex_lock(&dev_priv
->sb_lock
);
2898 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2905 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2906 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2907 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2909 mutex_unlock(&dev_priv
->sb_lock
);
2911 intel_enable_dp(encoder
);
2914 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2916 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2917 struct drm_device
*dev
= encoder
->base
.dev
;
2918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2919 struct intel_crtc
*intel_crtc
=
2920 to_intel_crtc(encoder
->base
.crtc
);
2921 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2922 int pipe
= intel_crtc
->pipe
;
2924 intel_dp_prepare(encoder
);
2926 /* Program Tx lane resets to default */
2927 mutex_lock(&dev_priv
->sb_lock
);
2928 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2929 DPIO_PCS_TX_LANE2_RESET
|
2930 DPIO_PCS_TX_LANE1_RESET
);
2931 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2932 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2933 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2934 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2935 DPIO_PCS_CLK_SOFT_RESET
);
2937 /* Fix up inter-pair skew failure */
2938 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2939 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2940 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2941 mutex_unlock(&dev_priv
->sb_lock
);
2944 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2946 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2947 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2948 struct drm_device
*dev
= encoder
->base
.dev
;
2949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2950 struct intel_crtc
*intel_crtc
=
2951 to_intel_crtc(encoder
->base
.crtc
);
2952 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2953 int pipe
= intel_crtc
->pipe
;
2954 int data
, i
, stagger
;
2957 mutex_lock(&dev_priv
->sb_lock
);
2959 /* allow hardware to manage TX FIFO reset source */
2960 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2961 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2962 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2964 if (intel_crtc
->config
->lane_count
> 2) {
2965 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2966 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2967 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2970 /* Program Tx lane latency optimal setting*/
2971 for (i
= 0; i
< intel_crtc
->config
->lane_count
; i
++) {
2972 /* Set the upar bit */
2973 if (intel_crtc
->config
->lane_count
== 1)
2976 data
= (i
== 1) ? 0x0 : 0x1;
2977 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2978 data
<< DPIO_UPAR_SHIFT
);
2981 /* Data lane stagger programming */
2982 if (intel_crtc
->config
->port_clock
> 270000)
2984 else if (intel_crtc
->config
->port_clock
> 135000)
2986 else if (intel_crtc
->config
->port_clock
> 67500)
2988 else if (intel_crtc
->config
->port_clock
> 33750)
2993 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2994 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2995 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2997 if (intel_crtc
->config
->lane_count
> 2) {
2998 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2999 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
3000 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
3003 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
3004 DPIO_LANESTAGGER_STRAP(stagger
) |
3005 DPIO_LANESTAGGER_STRAP_OVRD
|
3006 DPIO_TX1_STAGGER_MASK(0x1f) |
3007 DPIO_TX1_STAGGER_MULT(6) |
3008 DPIO_TX2_STAGGER_MULT(0));
3010 if (intel_crtc
->config
->lane_count
> 2) {
3011 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
3012 DPIO_LANESTAGGER_STRAP(stagger
) |
3013 DPIO_LANESTAGGER_STRAP_OVRD
|
3014 DPIO_TX1_STAGGER_MASK(0x1f) |
3015 DPIO_TX1_STAGGER_MULT(7) |
3016 DPIO_TX2_STAGGER_MULT(5));
3019 /* Deassert data lane reset */
3020 chv_data_lane_soft_reset(encoder
, false);
3022 mutex_unlock(&dev_priv
->sb_lock
);
3024 intel_enable_dp(encoder
);
3026 /* Second common lane will stay alive on its own now */
3027 if (dport
->release_cl2_override
) {
3028 chv_phy_powergate_ch(dev_priv
, DPIO_PHY0
, DPIO_CH1
, false);
3029 dport
->release_cl2_override
= false;
3033 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
3035 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
3036 struct drm_device
*dev
= encoder
->base
.dev
;
3037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 struct intel_crtc
*intel_crtc
=
3039 to_intel_crtc(encoder
->base
.crtc
);
3040 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3041 enum pipe pipe
= intel_crtc
->pipe
;
3042 unsigned int lane_mask
=
3043 intel_dp_unused_lane_mask(intel_crtc
->config
->lane_count
);
3046 intel_dp_prepare(encoder
);
3049 * Must trick the second common lane into life.
3050 * Otherwise we can't even access the PLL.
3052 if (ch
== DPIO_CH0
&& pipe
== PIPE_B
)
3053 dport
->release_cl2_override
=
3054 !chv_phy_powergate_ch(dev_priv
, DPIO_PHY0
, DPIO_CH1
, true);
3056 chv_phy_powergate_lanes(encoder
, true, lane_mask
);
3058 mutex_lock(&dev_priv
->sb_lock
);
3060 /* Assert data lane reset */
3061 chv_data_lane_soft_reset(encoder
, true);
3063 /* program left/right clock distribution */
3064 if (pipe
!= PIPE_B
) {
3065 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
3066 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
3068 val
|= CHV_BUFLEFTENA1_FORCE
;
3070 val
|= CHV_BUFRIGHTENA1_FORCE
;
3071 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
3073 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
3074 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
3076 val
|= CHV_BUFLEFTENA2_FORCE
;
3078 val
|= CHV_BUFRIGHTENA2_FORCE
;
3079 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
3082 /* program clock channel usage */
3083 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
3084 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
3086 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
3088 val
|= CHV_PCS_USEDCLKCHANNEL
;
3089 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
3091 if (intel_crtc
->config
->lane_count
> 2) {
3092 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
3093 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
3095 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
3097 val
|= CHV_PCS_USEDCLKCHANNEL
;
3098 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
3102 * This a a bit weird since generally CL
3103 * matches the pipe, but here we need to
3104 * pick the CL based on the port.
3106 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
3108 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
3110 val
|= CHV_CMN_USEDCLKCHANNEL
;
3111 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
3113 mutex_unlock(&dev_priv
->sb_lock
);
3116 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
)
3118 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3119 enum pipe pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
3122 mutex_lock(&dev_priv
->sb_lock
);
3124 /* disable left/right clock distribution */
3125 if (pipe
!= PIPE_B
) {
3126 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
3127 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
3128 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
3130 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
3131 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
3132 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
3135 mutex_unlock(&dev_priv
->sb_lock
);
3138 * Leave the power down bit cleared for at least one
3139 * lane so that chv_powergate_phy_ch() will power
3140 * on something when the channel is otherwise unused.
3141 * When the port is off and the override is removed
3142 * the lanes power down anyway, so otherwise it doesn't
3143 * really matter what the state of power down bits is
3146 chv_phy_powergate_lanes(encoder
, false, 0x0);
3150 * Native read with retry for link status and receiver capability reads for
3151 * cases where the sink may still be asleep.
3153 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3154 * supposed to retry 3 times per the spec.
3157 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
3158 void *buffer
, size_t size
)
3164 * Sometime we just get the same incorrect byte repeated
3165 * over the entire buffer. Doing just one throw away read
3166 * initially seems to "solve" it.
3168 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
3170 for (i
= 0; i
< 3; i
++) {
3171 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
3181 * Fetch AUX CH registers 0x202 - 0x207 which contain
3182 * link status information
3185 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3187 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3190 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
3193 /* These are source-specific values. */
3195 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
3197 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3199 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3201 if (IS_BROXTON(dev
))
3202 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3203 else if (INTEL_INFO(dev
)->gen
>= 9) {
3204 if (dev_priv
->edp_low_vswing
&& port
== PORT_A
)
3205 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3206 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3207 } else if (IS_VALLEYVIEW(dev
))
3208 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3209 else if (IS_GEN7(dev
) && port
== PORT_A
)
3210 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3211 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
3212 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3214 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
3218 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
3220 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3221 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3223 if (INTEL_INFO(dev
)->gen
>= 9) {
3224 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3226 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3228 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3230 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3232 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3234 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3236 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3237 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3239 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3240 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3241 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3243 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3246 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3248 } else if (IS_VALLEYVIEW(dev
)) {
3249 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3251 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3253 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3255 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3258 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3260 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3261 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3263 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3266 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3268 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3271 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3273 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3275 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3277 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3280 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3285 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3287 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3289 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3290 struct intel_crtc
*intel_crtc
=
3291 to_intel_crtc(dport
->base
.base
.crtc
);
3292 unsigned long demph_reg_value
, preemph_reg_value
,
3293 uniqtranscale_reg_value
;
3294 uint8_t train_set
= intel_dp
->train_set
[0];
3295 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3296 int pipe
= intel_crtc
->pipe
;
3298 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3299 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3300 preemph_reg_value
= 0x0004000;
3301 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3303 demph_reg_value
= 0x2B405555;
3304 uniqtranscale_reg_value
= 0x552AB83A;
3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3307 demph_reg_value
= 0x2B404040;
3308 uniqtranscale_reg_value
= 0x5548B83A;
3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3311 demph_reg_value
= 0x2B245555;
3312 uniqtranscale_reg_value
= 0x5560B83A;
3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3315 demph_reg_value
= 0x2B405555;
3316 uniqtranscale_reg_value
= 0x5598DA3A;
3322 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3323 preemph_reg_value
= 0x0002000;
3324 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3326 demph_reg_value
= 0x2B404040;
3327 uniqtranscale_reg_value
= 0x5552B83A;
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3330 demph_reg_value
= 0x2B404848;
3331 uniqtranscale_reg_value
= 0x5580B83A;
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3334 demph_reg_value
= 0x2B404040;
3335 uniqtranscale_reg_value
= 0x55ADDA3A;
3341 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3342 preemph_reg_value
= 0x0000000;
3343 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3344 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3345 demph_reg_value
= 0x2B305555;
3346 uniqtranscale_reg_value
= 0x5570B83A;
3348 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3349 demph_reg_value
= 0x2B2B4040;
3350 uniqtranscale_reg_value
= 0x55ADDA3A;
3356 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3357 preemph_reg_value
= 0x0006000;
3358 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3360 demph_reg_value
= 0x1B405555;
3361 uniqtranscale_reg_value
= 0x55ADDA3A;
3371 mutex_lock(&dev_priv
->sb_lock
);
3372 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3373 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3374 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3375 uniqtranscale_reg_value
);
3376 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3377 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3378 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3379 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3380 mutex_unlock(&dev_priv
->sb_lock
);
3385 static bool chv_need_uniq_trans_scale(uint8_t train_set
)
3387 return (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) == DP_TRAIN_PRE_EMPH_LEVEL_0
&&
3388 (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
3391 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3393 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3395 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3396 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3397 u32 deemph_reg_value
, margin_reg_value
, val
;
3398 uint8_t train_set
= intel_dp
->train_set
[0];
3399 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3400 enum pipe pipe
= intel_crtc
->pipe
;
3403 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3404 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3405 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3406 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3407 deemph_reg_value
= 128;
3408 margin_reg_value
= 52;
3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3411 deemph_reg_value
= 128;
3412 margin_reg_value
= 77;
3414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3415 deemph_reg_value
= 128;
3416 margin_reg_value
= 102;
3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3419 deemph_reg_value
= 128;
3420 margin_reg_value
= 154;
3421 /* FIXME extra to set for 1200 */
3427 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3428 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3430 deemph_reg_value
= 85;
3431 margin_reg_value
= 78;
3433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3434 deemph_reg_value
= 85;
3435 margin_reg_value
= 116;
3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3438 deemph_reg_value
= 85;
3439 margin_reg_value
= 154;
3445 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3446 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3448 deemph_reg_value
= 64;
3449 margin_reg_value
= 104;
3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3452 deemph_reg_value
= 64;
3453 margin_reg_value
= 154;
3459 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3460 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3462 deemph_reg_value
= 43;
3463 margin_reg_value
= 154;
3473 mutex_lock(&dev_priv
->sb_lock
);
3475 /* Clear calc init */
3476 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3477 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3478 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3479 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3480 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3482 if (intel_crtc
->config
->lane_count
> 2) {
3483 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3484 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3485 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3486 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3487 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3490 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3491 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3492 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3493 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3495 if (intel_crtc
->config
->lane_count
> 2) {
3496 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3497 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3498 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3499 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3502 /* Program swing deemph */
3503 for (i
= 0; i
< intel_crtc
->config
->lane_count
; i
++) {
3504 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3505 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3506 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3507 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3510 /* Program swing margin */
3511 for (i
= 0; i
< intel_crtc
->config
->lane_count
; i
++) {
3512 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3514 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3515 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3518 * Supposedly this value shouldn't matter when unique transition
3519 * scale is disabled, but in fact it does matter. Let's just
3520 * always program the same value and hope it's OK.
3522 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3523 val
|= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
;
3525 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3529 * The document said it needs to set bit 27 for ch0 and bit 26
3530 * for ch1. Might be a typo in the doc.
3531 * For now, for this unique transition scale selection, set bit
3532 * 27 for ch0 and ch1.
3534 for (i
= 0; i
< intel_crtc
->config
->lane_count
; i
++) {
3535 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3536 if (chv_need_uniq_trans_scale(train_set
))
3537 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3539 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3540 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3543 /* Start swing calculation */
3544 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3545 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3546 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3548 if (intel_crtc
->config
->lane_count
> 2) {
3549 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3550 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3551 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3554 mutex_unlock(&dev_priv
->sb_lock
);
3560 gen4_signal_levels(uint8_t train_set
)
3562 uint32_t signal_levels
= 0;
3564 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3565 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3567 signal_levels
|= DP_VOLTAGE_0_4
;
3569 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3570 signal_levels
|= DP_VOLTAGE_0_6
;
3572 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3573 signal_levels
|= DP_VOLTAGE_0_8
;
3575 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3576 signal_levels
|= DP_VOLTAGE_1_2
;
3579 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3580 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3582 signal_levels
|= DP_PRE_EMPHASIS_0
;
3584 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3585 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3587 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3588 signal_levels
|= DP_PRE_EMPHASIS_6
;
3590 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3591 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3594 return signal_levels
;
3597 /* Gen6's DP voltage swing and pre-emphasis control */
3599 gen6_edp_signal_levels(uint8_t train_set
)
3601 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3602 DP_TRAIN_PRE_EMPHASIS_MASK
);
3603 switch (signal_levels
) {
3604 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3605 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3606 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3607 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3608 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3609 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3610 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3611 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3612 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3613 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3614 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3615 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3616 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3617 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3619 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3620 "0x%x\n", signal_levels
);
3621 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3625 /* Gen7's DP voltage swing and pre-emphasis control */
3627 gen7_edp_signal_levels(uint8_t train_set
)
3629 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3630 DP_TRAIN_PRE_EMPHASIS_MASK
);
3631 switch (signal_levels
) {
3632 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3633 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3634 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3635 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3636 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3637 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3639 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3640 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3641 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3642 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3644 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3645 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3646 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3647 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3650 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3651 "0x%x\n", signal_levels
);
3652 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3657 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3659 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3660 enum port port
= intel_dig_port
->port
;
3661 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3662 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3663 uint32_t signal_levels
, mask
= 0;
3664 uint8_t train_set
= intel_dp
->train_set
[0];
3667 signal_levels
= ddi_signal_levels(intel_dp
);
3669 if (IS_BROXTON(dev
))
3672 mask
= DDI_BUF_EMP_MASK
;
3673 } else if (IS_CHERRYVIEW(dev
)) {
3674 signal_levels
= chv_signal_levels(intel_dp
);
3675 } else if (IS_VALLEYVIEW(dev
)) {
3676 signal_levels
= vlv_signal_levels(intel_dp
);
3677 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3678 signal_levels
= gen7_edp_signal_levels(train_set
);
3679 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3680 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3681 signal_levels
= gen6_edp_signal_levels(train_set
);
3682 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3684 signal_levels
= gen4_signal_levels(train_set
);
3685 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3689 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3691 DRM_DEBUG_KMS("Using vswing level %d\n",
3692 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3693 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3694 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3695 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3697 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3699 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3700 POSTING_READ(intel_dp
->output_reg
);
3704 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3705 uint8_t dp_train_pat
)
3707 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3708 struct drm_i915_private
*dev_priv
=
3709 to_i915(intel_dig_port
->base
.base
.dev
);
3711 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3713 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3714 POSTING_READ(intel_dp
->output_reg
);
3717 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3720 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3722 enum port port
= intel_dig_port
->port
;
3728 val
= I915_READ(DP_TP_CTL(port
));
3729 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3730 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3731 I915_WRITE(DP_TP_CTL(port
), val
);
3734 * On PORT_A we can have only eDP in SST mode. There the only reason
3735 * we need to set idle transmission mode is to work around a HW issue
3736 * where we enable the pipe while not in idle link-training mode.
3737 * In this case there is requirement to wait for a minimum number of
3738 * idle patterns to be sent.
3743 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3745 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3749 intel_dp_link_down(struct intel_dp
*intel_dp
)
3751 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3752 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3753 enum port port
= intel_dig_port
->port
;
3754 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3755 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3756 uint32_t DP
= intel_dp
->DP
;
3758 if (WARN_ON(HAS_DDI(dev
)))
3761 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3764 DRM_DEBUG_KMS("\n");
3766 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3767 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3768 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3769 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3771 if (IS_CHERRYVIEW(dev
))
3772 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3774 DP
&= ~DP_LINK_TRAIN_MASK
;
3775 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3777 I915_WRITE(intel_dp
->output_reg
, DP
);
3778 POSTING_READ(intel_dp
->output_reg
);
3780 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3781 I915_WRITE(intel_dp
->output_reg
, DP
);
3782 POSTING_READ(intel_dp
->output_reg
);
3785 * HW workaround for IBX, we need to move the port
3786 * to transcoder A after disabling it to allow the
3787 * matching HDMI port to be enabled on transcoder A.
3789 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3791 * We get CPU/PCH FIFO underruns on the other pipe when
3792 * doing the workaround. Sweep them under the rug.
3794 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3795 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3797 /* always enable with pattern 1 (as per spec) */
3798 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3799 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3800 I915_WRITE(intel_dp
->output_reg
, DP
);
3801 POSTING_READ(intel_dp
->output_reg
);
3804 I915_WRITE(intel_dp
->output_reg
, DP
);
3805 POSTING_READ(intel_dp
->output_reg
);
3807 intel_wait_for_vblank_if_active(dev_priv
->dev
, PIPE_A
);
3808 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3809 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3812 msleep(intel_dp
->panel_power_down_delay
);
3818 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3820 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3821 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3825 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3826 sizeof(intel_dp
->dpcd
)) < 0)
3827 return false; /* aux transfer failed */
3829 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3831 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3832 return false; /* DPCD not present */
3834 /* Check if the panel supports PSR */
3835 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3836 if (is_edp(intel_dp
)) {
3837 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3839 sizeof(intel_dp
->psr_dpcd
));
3840 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3841 dev_priv
->psr
.sink_support
= true;
3842 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3845 if (INTEL_INFO(dev
)->gen
>= 9 &&
3846 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3847 uint8_t frame_sync_cap
;
3849 dev_priv
->psr
.sink_support
= true;
3850 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3851 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3852 &frame_sync_cap
, 1);
3853 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3854 /* PSR2 needs frame sync as well */
3855 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3856 DRM_DEBUG_KMS("PSR2 %s on sink",
3857 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3861 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3862 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
3863 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
3865 /* Intermediate frequency support */
3866 if (is_edp(intel_dp
) &&
3867 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3868 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3869 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3870 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3873 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3874 DP_SUPPORTED_LINK_RATES
,
3876 sizeof(sink_rates
));
3878 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3879 int val
= le16_to_cpu(sink_rates
[i
]);
3884 /* Value read is in kHz while drm clock is saved in deca-kHz */
3885 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3887 intel_dp
->num_sink_rates
= i
;
3890 intel_dp_print_rates(intel_dp
);
3892 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3893 DP_DWN_STRM_PORT_PRESENT
))
3894 return true; /* native DP sink */
3896 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3897 return true; /* no per-port downstream info */
3899 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3900 intel_dp
->downstream_ports
,
3901 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3902 return false; /* downstream port status fetch failed */
3908 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3912 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3915 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3916 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3917 buf
[0], buf
[1], buf
[2]);
3919 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3920 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3921 buf
[0], buf
[1], buf
[2]);
3925 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3929 if (!intel_dp
->can_mst
)
3932 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3935 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3936 if (buf
[0] & DP_MST_CAP
) {
3937 DRM_DEBUG_KMS("Sink is MST capable\n");
3938 intel_dp
->is_mst
= true;
3940 DRM_DEBUG_KMS("Sink is not MST capable\n");
3941 intel_dp
->is_mst
= false;
3945 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3946 return intel_dp
->is_mst
;
3949 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3951 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3952 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3953 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3959 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3960 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3965 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3966 buf
& ~DP_TEST_SINK_START
) < 0) {
3967 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3973 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3975 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3976 DP_TEST_SINK_MISC
, &buf
) < 0) {
3980 count
= buf
& DP_TEST_COUNT_MASK
;
3981 } while (--attempts
&& count
);
3983 if (attempts
== 0) {
3984 DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
3989 hsw_enable_ips(intel_crtc
);
3993 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3995 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3996 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3997 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
4001 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
4004 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
4007 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4010 if (buf
& DP_TEST_SINK_START
) {
4011 ret
= intel_dp_sink_crc_stop(intel_dp
);
4016 hsw_disable_ips(intel_crtc
);
4018 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4019 buf
| DP_TEST_SINK_START
) < 0) {
4020 hsw_enable_ips(intel_crtc
);
4024 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4028 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
4030 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4031 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
4032 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
4037 ret
= intel_dp_sink_crc_start(intel_dp
);
4042 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4044 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4045 DP_TEST_SINK_MISC
, &buf
) < 0) {
4049 count
= buf
& DP_TEST_COUNT_MASK
;
4051 } while (--attempts
&& count
== 0);
4053 if (attempts
== 0) {
4054 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4059 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4065 intel_dp_sink_crc_stop(intel_dp
);
4070 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4072 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4073 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4074 sink_irq_vector
, 1) == 1;
4078 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4082 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4084 sink_irq_vector
, 14);
4091 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4093 uint8_t test_result
= DP_TEST_ACK
;
4097 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4099 uint8_t test_result
= DP_TEST_NAK
;
4103 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4105 uint8_t test_result
= DP_TEST_NAK
;
4106 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4107 struct drm_connector
*connector
= &intel_connector
->base
;
4109 if (intel_connector
->detect_edid
== NULL
||
4110 connector
->edid_corrupt
||
4111 intel_dp
->aux
.i2c_defer_count
> 6) {
4112 /* Check EDID read for NACKs, DEFERs and corruption
4113 * (DP CTS 1.2 Core r1.1)
4114 * 4.2.2.4 : Failed EDID read, I2C_NAK
4115 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4116 * 4.2.2.6 : EDID corruption detected
4117 * Use failsafe mode for all cases
4119 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4120 intel_dp
->aux
.i2c_defer_count
> 0)
4121 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4122 intel_dp
->aux
.i2c_nack_count
,
4123 intel_dp
->aux
.i2c_defer_count
);
4124 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
4126 struct edid
*block
= intel_connector
->detect_edid
;
4128 /* We have to write the checksum
4129 * of the last block read
4131 block
+= intel_connector
->detect_edid
->extensions
;
4133 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4134 DP_TEST_EDID_CHECKSUM
,
4137 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4139 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4140 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
4143 /* Set test active flag here so userspace doesn't interrupt things */
4144 intel_dp
->compliance_test_active
= 1;
4149 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4151 uint8_t test_result
= DP_TEST_NAK
;
4155 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4157 uint8_t response
= DP_TEST_NAK
;
4161 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4163 DRM_DEBUG_KMS("Could not read test request from sink\n");
4168 case DP_TEST_LINK_TRAINING
:
4169 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4170 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4171 response
= intel_dp_autotest_link_training(intel_dp
);
4173 case DP_TEST_LINK_VIDEO_PATTERN
:
4174 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4175 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4176 response
= intel_dp_autotest_video_pattern(intel_dp
);
4178 case DP_TEST_LINK_EDID_READ
:
4179 DRM_DEBUG_KMS("EDID test requested\n");
4180 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4181 response
= intel_dp_autotest_edid(intel_dp
);
4183 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4184 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4185 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4186 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4189 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4194 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4198 DRM_DEBUG_KMS("Could not write test response to sink\n");
4202 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4206 if (intel_dp
->is_mst
) {
4211 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4215 /* check link status - esi[10] = 0x200c */
4216 if (intel_dp
->active_mst_links
&&
4217 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4218 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4219 intel_dp_start_link_train(intel_dp
);
4220 intel_dp_stop_link_train(intel_dp
);
4223 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4224 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4227 for (retry
= 0; retry
< 3; retry
++) {
4229 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4230 DP_SINK_COUNT_ESI
+1,
4237 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4239 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4247 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4248 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4249 intel_dp
->is_mst
= false;
4250 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4251 /* send a hotplug event */
4252 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4259 * According to DP spec
4262 * 2. Configure link according to Receiver Capabilities
4263 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4264 * 4. Check link status on receipt of hot-plug interrupt
4267 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4269 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4270 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4272 u8 link_status
[DP_LINK_STATUS_SIZE
];
4274 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4277 * Clearing compliance test variables to allow capturing
4278 * of values for next automated test request.
4280 intel_dp
->compliance_test_active
= 0;
4281 intel_dp
->compliance_test_type
= 0;
4282 intel_dp
->compliance_test_data
= 0;
4284 if (!intel_encoder
->base
.crtc
)
4287 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4290 /* Try to read receiver status if the link appears to be up */
4291 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4295 /* Now read the DPCD to see if it's actually running */
4296 if (!intel_dp_get_dpcd(intel_dp
)) {
4300 /* Try to read the source of the interrupt */
4301 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4302 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4303 /* Clear interrupt source */
4304 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4305 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4308 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4309 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4310 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4311 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4314 /* if link training is requested we should perform it always */
4315 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
4316 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
4317 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4318 intel_encoder
->base
.name
);
4319 intel_dp_start_link_train(intel_dp
);
4320 intel_dp_stop_link_train(intel_dp
);
4324 /* XXX this is probably wrong for multiple downstream ports */
4325 static enum drm_connector_status
4326 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4328 uint8_t *dpcd
= intel_dp
->dpcd
;
4331 if (!intel_dp_get_dpcd(intel_dp
))
4332 return connector_status_disconnected
;
4334 /* if there's no downstream port, we're done */
4335 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4336 return connector_status_connected
;
4338 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4339 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4340 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4343 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4345 return connector_status_unknown
;
4347 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4348 : connector_status_disconnected
;
4351 /* If no HPD, poke DDC gently */
4352 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4353 return connector_status_connected
;
4355 /* Well we tried, say unknown for unreliable port types */
4356 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4357 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4358 if (type
== DP_DS_PORT_TYPE_VGA
||
4359 type
== DP_DS_PORT_TYPE_NON_EDID
)
4360 return connector_status_unknown
;
4362 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4363 DP_DWN_STRM_PORT_TYPE_MASK
;
4364 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4365 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4366 return connector_status_unknown
;
4369 /* Anything else is out of spec, warn and ignore */
4370 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4371 return connector_status_disconnected
;
4374 static enum drm_connector_status
4375 edp_detect(struct intel_dp
*intel_dp
)
4377 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4378 enum drm_connector_status status
;
4380 status
= intel_panel_detect(dev
);
4381 if (status
== connector_status_unknown
)
4382 status
= connector_status_connected
;
4387 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4388 struct intel_digital_port
*port
)
4392 switch (port
->port
) {
4396 bit
= SDE_PORTB_HOTPLUG
;
4399 bit
= SDE_PORTC_HOTPLUG
;
4402 bit
= SDE_PORTD_HOTPLUG
;
4405 MISSING_CASE(port
->port
);
4409 return I915_READ(SDEISR
) & bit
;
4412 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4413 struct intel_digital_port
*port
)
4417 switch (port
->port
) {
4421 bit
= SDE_PORTB_HOTPLUG_CPT
;
4424 bit
= SDE_PORTC_HOTPLUG_CPT
;
4427 bit
= SDE_PORTD_HOTPLUG_CPT
;
4430 bit
= SDE_PORTE_HOTPLUG_SPT
;
4433 MISSING_CASE(port
->port
);
4437 return I915_READ(SDEISR
) & bit
;
4440 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4441 struct intel_digital_port
*port
)
4445 switch (port
->port
) {
4447 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4450 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4453 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4456 MISSING_CASE(port
->port
);
4460 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4463 static bool vlv_digital_port_connected(struct drm_i915_private
*dev_priv
,
4464 struct intel_digital_port
*port
)
4468 switch (port
->port
) {
4470 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4473 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4476 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4479 MISSING_CASE(port
->port
);
4483 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4486 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4487 struct intel_digital_port
*intel_dig_port
)
4489 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4493 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4496 bit
= BXT_DE_PORT_HP_DDIA
;
4499 bit
= BXT_DE_PORT_HP_DDIB
;
4502 bit
= BXT_DE_PORT_HP_DDIC
;
4509 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4513 * intel_digital_port_connected - is the specified port connected?
4514 * @dev_priv: i915 private structure
4515 * @port: the port to test
4517 * Return %true if @port is connected, %false otherwise.
4519 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4520 struct intel_digital_port
*port
)
4522 if (HAS_PCH_IBX(dev_priv
))
4523 return ibx_digital_port_connected(dev_priv
, port
);
4524 if (HAS_PCH_SPLIT(dev_priv
))
4525 return cpt_digital_port_connected(dev_priv
, port
);
4526 else if (IS_BROXTON(dev_priv
))
4527 return bxt_digital_port_connected(dev_priv
, port
);
4528 else if (IS_VALLEYVIEW(dev_priv
))
4529 return vlv_digital_port_connected(dev_priv
, port
);
4531 return g4x_digital_port_connected(dev_priv
, port
);
4534 static enum drm_connector_status
4535 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4537 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4538 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4539 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4541 if (!intel_digital_port_connected(dev_priv
, intel_dig_port
))
4542 return connector_status_disconnected
;
4544 return intel_dp_detect_dpcd(intel_dp
);
4547 static enum drm_connector_status
4548 g4x_dp_detect(struct intel_dp
*intel_dp
)
4550 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4551 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4553 /* Can't disconnect eDP, but you can close the lid... */
4554 if (is_edp(intel_dp
)) {
4555 enum drm_connector_status status
;
4557 status
= intel_panel_detect(dev
);
4558 if (status
== connector_status_unknown
)
4559 status
= connector_status_connected
;
4563 if (!intel_digital_port_connected(dev
->dev_private
, intel_dig_port
))
4564 return connector_status_disconnected
;
4566 return intel_dp_detect_dpcd(intel_dp
);
4569 static struct edid
*
4570 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4572 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4574 /* use cached edid if we have one */
4575 if (intel_connector
->edid
) {
4577 if (IS_ERR(intel_connector
->edid
))
4580 return drm_edid_duplicate(intel_connector
->edid
);
4582 return drm_get_edid(&intel_connector
->base
,
4583 &intel_dp
->aux
.ddc
);
4587 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4589 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4592 edid
= intel_dp_get_edid(intel_dp
);
4593 intel_connector
->detect_edid
= edid
;
4595 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4596 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4598 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4602 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4604 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4606 kfree(intel_connector
->detect_edid
);
4607 intel_connector
->detect_edid
= NULL
;
4609 intel_dp
->has_audio
= false;
4612 static enum drm_connector_status
4613 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4615 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4616 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4617 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4618 struct drm_device
*dev
= connector
->dev
;
4619 enum drm_connector_status status
;
4620 enum intel_display_power_domain power_domain
;
4624 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4625 connector
->base
.id
, connector
->name
);
4626 intel_dp_unset_edid(intel_dp
);
4628 if (intel_dp
->is_mst
) {
4629 /* MST devices are disconnected from a monitor POV */
4630 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4631 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4632 return connector_status_disconnected
;
4635 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4636 intel_display_power_get(to_i915(dev
), power_domain
);
4638 /* Can't disconnect eDP, but you can close the lid... */
4639 if (is_edp(intel_dp
))
4640 status
= edp_detect(intel_dp
);
4641 else if (HAS_PCH_SPLIT(dev
))
4642 status
= ironlake_dp_detect(intel_dp
);
4644 status
= g4x_dp_detect(intel_dp
);
4645 if (status
!= connector_status_connected
) {
4646 intel_dp
->compliance_test_active
= 0;
4647 intel_dp
->compliance_test_type
= 0;
4648 intel_dp
->compliance_test_data
= 0;
4653 intel_dp_probe_oui(intel_dp
);
4655 ret
= intel_dp_probe_mst(intel_dp
);
4657 /* if we are in MST mode then this connector
4658 won't appear connected or have anything with EDID on it */
4659 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4660 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4661 status
= connector_status_disconnected
;
4666 * Clearing NACK and defer counts to get their exact values
4667 * while reading EDID which are required by Compliance tests
4668 * 4.2.2.4 and 4.2.2.5
4670 intel_dp
->aux
.i2c_nack_count
= 0;
4671 intel_dp
->aux
.i2c_defer_count
= 0;
4673 intel_dp_set_edid(intel_dp
);
4675 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4676 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4677 status
= connector_status_connected
;
4679 /* Try to read the source of the interrupt */
4680 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4681 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4682 /* Clear interrupt source */
4683 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4684 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4687 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4688 intel_dp_handle_test_request(intel_dp
);
4689 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4690 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4694 intel_display_power_put(to_i915(dev
), power_domain
);
4699 intel_dp_force(struct drm_connector
*connector
)
4701 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4702 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4703 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4704 enum intel_display_power_domain power_domain
;
4706 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4707 connector
->base
.id
, connector
->name
);
4708 intel_dp_unset_edid(intel_dp
);
4710 if (connector
->status
!= connector_status_connected
)
4713 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4714 intel_display_power_get(dev_priv
, power_domain
);
4716 intel_dp_set_edid(intel_dp
);
4718 intel_display_power_put(dev_priv
, power_domain
);
4720 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4721 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4724 static int intel_dp_get_modes(struct drm_connector
*connector
)
4726 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4729 edid
= intel_connector
->detect_edid
;
4731 int ret
= intel_connector_update_modes(connector
, edid
);
4736 /* if eDP has no EDID, fall back to fixed mode */
4737 if (is_edp(intel_attached_dp(connector
)) &&
4738 intel_connector
->panel
.fixed_mode
) {
4739 struct drm_display_mode
*mode
;
4741 mode
= drm_mode_duplicate(connector
->dev
,
4742 intel_connector
->panel
.fixed_mode
);
4744 drm_mode_probed_add(connector
, mode
);
4753 intel_dp_detect_audio(struct drm_connector
*connector
)
4755 bool has_audio
= false;
4758 edid
= to_intel_connector(connector
)->detect_edid
;
4760 has_audio
= drm_detect_monitor_audio(edid
);
4766 intel_dp_set_property(struct drm_connector
*connector
,
4767 struct drm_property
*property
,
4770 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4771 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4772 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4773 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4776 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4780 if (property
== dev_priv
->force_audio_property
) {
4784 if (i
== intel_dp
->force_audio
)
4787 intel_dp
->force_audio
= i
;
4789 if (i
== HDMI_AUDIO_AUTO
)
4790 has_audio
= intel_dp_detect_audio(connector
);
4792 has_audio
= (i
== HDMI_AUDIO_ON
);
4794 if (has_audio
== intel_dp
->has_audio
)
4797 intel_dp
->has_audio
= has_audio
;
4801 if (property
== dev_priv
->broadcast_rgb_property
) {
4802 bool old_auto
= intel_dp
->color_range_auto
;
4803 bool old_range
= intel_dp
->limited_color_range
;
4806 case INTEL_BROADCAST_RGB_AUTO
:
4807 intel_dp
->color_range_auto
= true;
4809 case INTEL_BROADCAST_RGB_FULL
:
4810 intel_dp
->color_range_auto
= false;
4811 intel_dp
->limited_color_range
= false;
4813 case INTEL_BROADCAST_RGB_LIMITED
:
4814 intel_dp
->color_range_auto
= false;
4815 intel_dp
->limited_color_range
= true;
4821 if (old_auto
== intel_dp
->color_range_auto
&&
4822 old_range
== intel_dp
->limited_color_range
)
4828 if (is_edp(intel_dp
) &&
4829 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4830 if (val
== DRM_MODE_SCALE_NONE
) {
4831 DRM_DEBUG_KMS("no scaling not supported\n");
4835 if (intel_connector
->panel
.fitting_mode
== val
) {
4836 /* the eDP scaling property is not changed */
4839 intel_connector
->panel
.fitting_mode
= val
;
4847 if (intel_encoder
->base
.crtc
)
4848 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4854 intel_dp_connector_destroy(struct drm_connector
*connector
)
4856 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4858 kfree(intel_connector
->detect_edid
);
4860 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4861 kfree(intel_connector
->edid
);
4863 /* Can't call is_edp() since the encoder may have been destroyed
4865 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4866 intel_panel_fini(&intel_connector
->panel
);
4868 drm_connector_cleanup(connector
);
4872 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4874 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4875 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4877 intel_dp_aux_fini(intel_dp
);
4878 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4879 if (is_edp(intel_dp
)) {
4880 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4882 * vdd might still be enabled do to the delayed vdd off.
4883 * Make sure vdd is actually turned off here.
4886 edp_panel_vdd_off_sync(intel_dp
);
4887 pps_unlock(intel_dp
);
4889 if (intel_dp
->edp_notifier
.notifier_call
) {
4890 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4891 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4894 drm_encoder_cleanup(encoder
);
4895 kfree(intel_dig_port
);
4898 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4900 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4902 if (!is_edp(intel_dp
))
4906 * vdd might still be enabled do to the delayed vdd off.
4907 * Make sure vdd is actually turned off here.
4909 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4911 edp_panel_vdd_off_sync(intel_dp
);
4912 pps_unlock(intel_dp
);
4915 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4917 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4918 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4920 enum intel_display_power_domain power_domain
;
4922 lockdep_assert_held(&dev_priv
->pps_mutex
);
4924 if (!edp_have_panel_vdd(intel_dp
))
4928 * The VDD bit needs a power domain reference, so if the bit is
4929 * already enabled when we boot or resume, grab this reference and
4930 * schedule a vdd off, so we don't hold on to the reference
4933 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4934 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4935 intel_display_power_get(dev_priv
, power_domain
);
4937 edp_panel_vdd_schedule_off(intel_dp
);
4940 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4942 struct intel_dp
*intel_dp
;
4944 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4947 intel_dp
= enc_to_intel_dp(encoder
);
4952 * Read out the current power sequencer assignment,
4953 * in case the BIOS did something with it.
4955 if (IS_VALLEYVIEW(encoder
->dev
))
4956 vlv_initial_power_sequencer_setup(intel_dp
);
4958 intel_edp_panel_vdd_sanitize(intel_dp
);
4960 pps_unlock(intel_dp
);
4963 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4964 .dpms
= drm_atomic_helper_connector_dpms
,
4965 .detect
= intel_dp_detect
,
4966 .force
= intel_dp_force
,
4967 .fill_modes
= drm_helper_probe_single_connector_modes
,
4968 .set_property
= intel_dp_set_property
,
4969 .atomic_get_property
= intel_connector_atomic_get_property
,
4970 .destroy
= intel_dp_connector_destroy
,
4971 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4972 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4975 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4976 .get_modes
= intel_dp_get_modes
,
4977 .mode_valid
= intel_dp_mode_valid
,
4978 .best_encoder
= intel_best_encoder
,
4981 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4982 .reset
= intel_dp_encoder_reset
,
4983 .destroy
= intel_dp_encoder_destroy
,
4987 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4989 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4990 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4991 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4993 enum intel_display_power_domain power_domain
;
4994 enum irqreturn ret
= IRQ_NONE
;
4996 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4997 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4999 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
5001 * vdd off can generate a long pulse on eDP which
5002 * would require vdd on to handle it, and thus we
5003 * would end up in an endless cycle of
5004 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5006 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5007 port_name(intel_dig_port
->port
));
5011 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5012 port_name(intel_dig_port
->port
),
5013 long_hpd
? "long" : "short");
5015 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
5016 intel_display_power_get(dev_priv
, power_domain
);
5019 /* indicate that we need to restart link training */
5020 intel_dp
->train_set_valid
= false;
5022 if (!intel_digital_port_connected(dev_priv
, intel_dig_port
))
5025 if (!intel_dp_get_dpcd(intel_dp
)) {
5029 intel_dp_probe_oui(intel_dp
);
5031 if (!intel_dp_probe_mst(intel_dp
)) {
5032 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
5033 intel_dp_check_link_status(intel_dp
);
5034 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
5038 if (intel_dp
->is_mst
) {
5039 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
5043 if (!intel_dp
->is_mst
) {
5044 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
5045 intel_dp_check_link_status(intel_dp
);
5046 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
5054 /* if we were in MST mode, and device is not there get out of MST mode */
5055 if (intel_dp
->is_mst
) {
5056 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5057 intel_dp
->is_mst
= false;
5058 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
5061 intel_display_power_put(dev_priv
, power_domain
);
5066 /* check the VBT to see whether the eDP is on another port */
5067 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
5069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5070 union child_device_config
*p_child
;
5072 static const short port_mapping
[] = {
5073 [PORT_B
] = DVO_PORT_DPB
,
5074 [PORT_C
] = DVO_PORT_DPC
,
5075 [PORT_D
] = DVO_PORT_DPD
,
5076 [PORT_E
] = DVO_PORT_DPE
,
5080 * eDP not supported on g4x. so bail out early just
5081 * for a bit extra safety in case the VBT is bonkers.
5083 if (INTEL_INFO(dev
)->gen
< 5)
5089 if (!dev_priv
->vbt
.child_dev_num
)
5092 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
5093 p_child
= dev_priv
->vbt
.child_dev
+ i
;
5095 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
5096 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
5097 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
5104 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5106 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5108 intel_attach_force_audio_property(connector
);
5109 intel_attach_broadcast_rgb_property(connector
);
5110 intel_dp
->color_range_auto
= true;
5112 if (is_edp(intel_dp
)) {
5113 drm_mode_create_scaling_mode_property(connector
->dev
);
5114 drm_object_attach_property(
5116 connector
->dev
->mode_config
.scaling_mode_property
,
5117 DRM_MODE_SCALE_ASPECT
);
5118 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5122 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5124 intel_dp
->last_power_cycle
= jiffies
;
5125 intel_dp
->last_power_on
= jiffies
;
5126 intel_dp
->last_backlight_off
= jiffies
;
5130 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5131 struct intel_dp
*intel_dp
)
5133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5134 struct edp_power_seq cur
, vbt
, spec
,
5135 *final
= &intel_dp
->pps_delays
;
5136 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5137 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
= 0;
5139 lockdep_assert_held(&dev_priv
->pps_mutex
);
5141 /* already initialized? */
5142 if (final
->t11_t12
!= 0)
5145 if (IS_BROXTON(dev
)) {
5147 * TODO: BXT has 2 sets of PPS registers.
5148 * Correct Register for Broxton need to be identified
5149 * using VBT. hardcoding for now
5151 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5152 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5153 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5154 } else if (HAS_PCH_SPLIT(dev
)) {
5155 pp_ctrl_reg
= PCH_PP_CONTROL
;
5156 pp_on_reg
= PCH_PP_ON_DELAYS
;
5157 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5158 pp_div_reg
= PCH_PP_DIVISOR
;
5160 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5162 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
5163 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5164 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5165 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5168 /* Workaround: Need to write PP_CONTROL with the unlock key as
5169 * the very first thing. */
5170 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5172 pp_on
= I915_READ(pp_on_reg
);
5173 pp_off
= I915_READ(pp_off_reg
);
5174 if (!IS_BROXTON(dev
)) {
5175 I915_WRITE(pp_ctrl_reg
, pp_ctl
);
5176 pp_div
= I915_READ(pp_div_reg
);
5179 /* Pull timing values out of registers */
5180 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5181 PANEL_POWER_UP_DELAY_SHIFT
;
5183 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5184 PANEL_LIGHT_ON_DELAY_SHIFT
;
5186 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5187 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5189 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5190 PANEL_POWER_DOWN_DELAY_SHIFT
;
5192 if (IS_BROXTON(dev
)) {
5193 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5194 BXT_POWER_CYCLE_DELAY_SHIFT
;
5196 cur
.t11_t12
= (tmp
- 1) * 1000;
5200 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5201 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5204 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5205 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5207 vbt
= dev_priv
->vbt
.edp_pps
;
5209 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5210 * our hw here, which are all in 100usec. */
5211 spec
.t1_t3
= 210 * 10;
5212 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5213 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5214 spec
.t10
= 500 * 10;
5215 /* This one is special and actually in units of 100ms, but zero
5216 * based in the hw (so we need to add 100 ms). But the sw vbt
5217 * table multiplies it with 1000 to make it in units of 100usec,
5219 spec
.t11_t12
= (510 + 100) * 10;
5221 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5222 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5224 /* Use the max of the register settings and vbt. If both are
5225 * unset, fall back to the spec limits. */
5226 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5228 max(cur.field, vbt.field))
5229 assign_final(t1_t3
);
5233 assign_final(t11_t12
);
5236 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5237 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5238 intel_dp
->backlight_on_delay
= get_delay(t8
);
5239 intel_dp
->backlight_off_delay
= get_delay(t9
);
5240 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5241 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5244 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5245 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5246 intel_dp
->panel_power_cycle_delay
);
5248 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5249 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5253 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5254 struct intel_dp
*intel_dp
)
5256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5257 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5258 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5259 int pp_on_reg
, pp_off_reg
, pp_div_reg
= 0, pp_ctrl_reg
;
5260 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5261 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5263 lockdep_assert_held(&dev_priv
->pps_mutex
);
5265 if (IS_BROXTON(dev
)) {
5267 * TODO: BXT has 2 sets of PPS registers.
5268 * Correct Register for Broxton need to be identified
5269 * using VBT. hardcoding for now
5271 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5272 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5273 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5275 } else if (HAS_PCH_SPLIT(dev
)) {
5276 pp_on_reg
= PCH_PP_ON_DELAYS
;
5277 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5278 pp_div_reg
= PCH_PP_DIVISOR
;
5280 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5282 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5283 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5284 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5288 * And finally store the new values in the power sequencer. The
5289 * backlight delays are set to 1 because we do manual waits on them. For
5290 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5291 * we'll end up waiting for the backlight off delay twice: once when we
5292 * do the manual sleep, and once when we disable the panel and wait for
5293 * the PP_STATUS bit to become zero.
5295 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5296 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5297 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5298 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5299 /* Compute the divisor for the pp clock, simply match the Bspec
5301 if (IS_BROXTON(dev
)) {
5302 pp_div
= I915_READ(pp_ctrl_reg
);
5303 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5304 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5305 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5307 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5308 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5309 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5312 /* Haswell doesn't have any port selection bits for the panel
5313 * power sequencer any more. */
5314 if (IS_VALLEYVIEW(dev
)) {
5315 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5316 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5318 port_sel
= PANEL_PORT_SELECT_DPA
;
5320 port_sel
= PANEL_PORT_SELECT_DPD
;
5325 I915_WRITE(pp_on_reg
, pp_on
);
5326 I915_WRITE(pp_off_reg
, pp_off
);
5327 if (IS_BROXTON(dev
))
5328 I915_WRITE(pp_ctrl_reg
, pp_div
);
5330 I915_WRITE(pp_div_reg
, pp_div
);
5332 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5333 I915_READ(pp_on_reg
),
5334 I915_READ(pp_off_reg
),
5336 (I915_READ(pp_ctrl_reg
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5337 I915_READ(pp_div_reg
));
5341 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5343 * @refresh_rate: RR to be programmed
5345 * This function gets called when refresh rate (RR) has to be changed from
5346 * one frequency to another. Switches can be between high and low RR
5347 * supported by the panel or to any other RR based on media playback (in
5348 * this case, RR value needs to be passed from user space).
5350 * The caller of this function needs to take a lock on dev_priv->drrs.
5352 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5355 struct intel_encoder
*encoder
;
5356 struct intel_digital_port
*dig_port
= NULL
;
5357 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5358 struct intel_crtc_state
*config
= NULL
;
5359 struct intel_crtc
*intel_crtc
= NULL
;
5360 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5362 if (refresh_rate
<= 0) {
5363 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5367 if (intel_dp
== NULL
) {
5368 DRM_DEBUG_KMS("DRRS not supported.\n");
5373 * FIXME: This needs proper synchronization with psr state for some
5374 * platforms that cannot have PSR and DRRS enabled at the same time.
5377 dig_port
= dp_to_dig_port(intel_dp
);
5378 encoder
= &dig_port
->base
;
5379 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5382 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5386 config
= intel_crtc
->config
;
5388 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5389 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5393 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5395 index
= DRRS_LOW_RR
;
5397 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5399 "DRRS requested for previously set RR...ignoring\n");
5403 if (!intel_crtc
->active
) {
5404 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5408 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5411 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5414 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5418 DRM_ERROR("Unsupported refreshrate type\n");
5420 } else if (INTEL_INFO(dev
)->gen
> 6) {
5421 u32 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5424 val
= I915_READ(reg
);
5425 if (index
> DRRS_HIGH_RR
) {
5426 if (IS_VALLEYVIEW(dev
))
5427 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5429 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5431 if (IS_VALLEYVIEW(dev
))
5432 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5434 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5436 I915_WRITE(reg
, val
);
5439 dev_priv
->drrs
.refresh_rate_type
= index
;
5441 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5445 * intel_edp_drrs_enable - init drrs struct if supported
5446 * @intel_dp: DP struct
5448 * Initializes frontbuffer_bits and drrs.dp
5450 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5452 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5454 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5455 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5456 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5458 if (!intel_crtc
->config
->has_drrs
) {
5459 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5463 mutex_lock(&dev_priv
->drrs
.mutex
);
5464 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5465 DRM_ERROR("DRRS already enabled\n");
5469 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5471 dev_priv
->drrs
.dp
= intel_dp
;
5474 mutex_unlock(&dev_priv
->drrs
.mutex
);
5478 * intel_edp_drrs_disable - Disable DRRS
5479 * @intel_dp: DP struct
5482 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5484 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5486 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5487 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5488 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5490 if (!intel_crtc
->config
->has_drrs
)
5493 mutex_lock(&dev_priv
->drrs
.mutex
);
5494 if (!dev_priv
->drrs
.dp
) {
5495 mutex_unlock(&dev_priv
->drrs
.mutex
);
5499 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5500 intel_dp_set_drrs_state(dev_priv
->dev
,
5501 intel_dp
->attached_connector
->panel
.
5502 fixed_mode
->vrefresh
);
5504 dev_priv
->drrs
.dp
= NULL
;
5505 mutex_unlock(&dev_priv
->drrs
.mutex
);
5507 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5510 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5512 struct drm_i915_private
*dev_priv
=
5513 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5514 struct intel_dp
*intel_dp
;
5516 mutex_lock(&dev_priv
->drrs
.mutex
);
5518 intel_dp
= dev_priv
->drrs
.dp
;
5524 * The delayed work can race with an invalidate hence we need to
5528 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5531 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5532 intel_dp_set_drrs_state(dev_priv
->dev
,
5533 intel_dp
->attached_connector
->panel
.
5534 downclock_mode
->vrefresh
);
5537 mutex_unlock(&dev_priv
->drrs
.mutex
);
5541 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5543 * @frontbuffer_bits: frontbuffer plane tracking bits
5545 * This function gets called everytime rendering on the given planes start.
5546 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5548 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5550 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5551 unsigned frontbuffer_bits
)
5553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5554 struct drm_crtc
*crtc
;
5557 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5560 cancel_delayed_work(&dev_priv
->drrs
.work
);
5562 mutex_lock(&dev_priv
->drrs
.mutex
);
5563 if (!dev_priv
->drrs
.dp
) {
5564 mutex_unlock(&dev_priv
->drrs
.mutex
);
5568 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5569 pipe
= to_intel_crtc(crtc
)->pipe
;
5571 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5572 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5574 /* invalidate means busy screen hence upclock */
5575 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5576 intel_dp_set_drrs_state(dev_priv
->dev
,
5577 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5578 fixed_mode
->vrefresh
);
5580 mutex_unlock(&dev_priv
->drrs
.mutex
);
5584 * intel_edp_drrs_flush - Restart Idleness DRRS
5586 * @frontbuffer_bits: frontbuffer plane tracking bits
5588 * This function gets called every time rendering on the given planes has
5589 * completed or flip on a crtc is completed. So DRRS should be upclocked
5590 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5591 * if no other planes are dirty.
5593 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5595 void intel_edp_drrs_flush(struct drm_device
*dev
,
5596 unsigned frontbuffer_bits
)
5598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5599 struct drm_crtc
*crtc
;
5602 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5605 cancel_delayed_work(&dev_priv
->drrs
.work
);
5607 mutex_lock(&dev_priv
->drrs
.mutex
);
5608 if (!dev_priv
->drrs
.dp
) {
5609 mutex_unlock(&dev_priv
->drrs
.mutex
);
5613 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5614 pipe
= to_intel_crtc(crtc
)->pipe
;
5616 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5617 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5619 /* flush means busy screen hence upclock */
5620 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5621 intel_dp_set_drrs_state(dev_priv
->dev
,
5622 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5623 fixed_mode
->vrefresh
);
5626 * flush also means no more activity hence schedule downclock, if all
5627 * other fbs are quiescent too
5629 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5630 schedule_delayed_work(&dev_priv
->drrs
.work
,
5631 msecs_to_jiffies(1000));
5632 mutex_unlock(&dev_priv
->drrs
.mutex
);
5636 * DOC: Display Refresh Rate Switching (DRRS)
5638 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5639 * which enables swtching between low and high refresh rates,
5640 * dynamically, based on the usage scenario. This feature is applicable
5641 * for internal panels.
5643 * Indication that the panel supports DRRS is given by the panel EDID, which
5644 * would list multiple refresh rates for one resolution.
5646 * DRRS is of 2 types - static and seamless.
5647 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5648 * (may appear as a blink on screen) and is used in dock-undock scenario.
5649 * Seamless DRRS involves changing RR without any visual effect to the user
5650 * and can be used during normal system usage. This is done by programming
5651 * certain registers.
5653 * Support for static/seamless DRRS may be indicated in the VBT based on
5654 * inputs from the panel spec.
5656 * DRRS saves power by switching to low RR based on usage scenarios.
5659 * The implementation is based on frontbuffer tracking implementation.
5660 * When there is a disturbance on the screen triggered by user activity or a
5661 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5662 * When there is no movement on screen, after a timeout of 1 second, a switch
5663 * to low RR is made.
5664 * For integration with frontbuffer tracking code,
5665 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5667 * DRRS can be further extended to support other internal panels and also
5668 * the scenario of video playback wherein RR is set based on the rate
5669 * requested by userspace.
5673 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5674 * @intel_connector: eDP connector
5675 * @fixed_mode: preferred mode of panel
5677 * This function is called only once at driver load to initialize basic
5681 * Downclock mode if panel supports it, else return NULL.
5682 * DRRS support is determined by the presence of downclock mode (apart
5683 * from VBT setting).
5685 static struct drm_display_mode
*
5686 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5687 struct drm_display_mode
*fixed_mode
)
5689 struct drm_connector
*connector
= &intel_connector
->base
;
5690 struct drm_device
*dev
= connector
->dev
;
5691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5692 struct drm_display_mode
*downclock_mode
= NULL
;
5694 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5695 mutex_init(&dev_priv
->drrs
.mutex
);
5697 if (INTEL_INFO(dev
)->gen
<= 6) {
5698 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5702 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5703 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5707 downclock_mode
= intel_find_panel_downclock
5708 (dev
, fixed_mode
, connector
);
5710 if (!downclock_mode
) {
5711 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5715 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5717 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5718 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5719 return downclock_mode
;
5722 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5723 struct intel_connector
*intel_connector
)
5725 struct drm_connector
*connector
= &intel_connector
->base
;
5726 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5727 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5728 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5730 struct drm_display_mode
*fixed_mode
= NULL
;
5731 struct drm_display_mode
*downclock_mode
= NULL
;
5733 struct drm_display_mode
*scan
;
5735 enum pipe pipe
= INVALID_PIPE
;
5737 if (!is_edp(intel_dp
))
5741 intel_edp_panel_vdd_sanitize(intel_dp
);
5742 pps_unlock(intel_dp
);
5744 /* Cache DPCD and EDID for edp. */
5745 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5748 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5749 dev_priv
->no_aux_handshake
=
5750 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5751 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5753 /* if this fails, presume the device is a ghost */
5754 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5758 /* We now know it's not a ghost, init power sequence regs. */
5760 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5761 pps_unlock(intel_dp
);
5763 mutex_lock(&dev
->mode_config
.mutex
);
5764 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5766 if (drm_add_edid_modes(connector
, edid
)) {
5767 drm_mode_connector_update_edid_property(connector
,
5769 drm_edid_to_eld(connector
, edid
);
5772 edid
= ERR_PTR(-EINVAL
);
5775 edid
= ERR_PTR(-ENOENT
);
5777 intel_connector
->edid
= edid
;
5779 /* prefer fixed mode from EDID if available */
5780 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5781 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5782 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5783 downclock_mode
= intel_dp_drrs_init(
5784 intel_connector
, fixed_mode
);
5789 /* fallback to VBT if available for eDP */
5790 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5791 fixed_mode
= drm_mode_duplicate(dev
,
5792 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5794 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5796 mutex_unlock(&dev
->mode_config
.mutex
);
5798 if (IS_VALLEYVIEW(dev
)) {
5799 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5800 register_reboot_notifier(&intel_dp
->edp_notifier
);
5803 * Figure out the current pipe for the initial backlight setup.
5804 * If the current pipe isn't valid, try the PPS pipe, and if that
5805 * fails just assume pipe A.
5807 if (IS_CHERRYVIEW(dev
))
5808 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5810 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5812 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5813 pipe
= intel_dp
->pps_pipe
;
5815 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5818 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5822 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5823 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5824 intel_panel_setup_backlight(connector
, pipe
);
5830 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5831 struct intel_connector
*intel_connector
)
5833 struct drm_connector
*connector
= &intel_connector
->base
;
5834 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5835 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5836 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5838 enum port port
= intel_dig_port
->port
;
5841 intel_dp
->pps_pipe
= INVALID_PIPE
;
5843 /* intel_dp vfuncs */
5844 if (INTEL_INFO(dev
)->gen
>= 9)
5845 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5846 else if (IS_VALLEYVIEW(dev
))
5847 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5848 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5849 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5850 else if (HAS_PCH_SPLIT(dev
))
5851 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5853 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5855 if (INTEL_INFO(dev
)->gen
>= 9)
5856 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5858 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5861 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5863 /* Preserve the current hw state. */
5864 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5865 intel_dp
->attached_connector
= intel_connector
;
5867 if (intel_dp_is_edp(dev
, port
))
5868 type
= DRM_MODE_CONNECTOR_eDP
;
5870 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5873 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5874 * for DP the encoder type can be set by the caller to
5875 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5877 if (type
== DRM_MODE_CONNECTOR_eDP
)
5878 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5880 /* eDP only on port B and/or C on vlv/chv */
5881 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5882 port
!= PORT_B
&& port
!= PORT_C
))
5885 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5886 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5889 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5890 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5892 connector
->interlace_allowed
= true;
5893 connector
->doublescan_allowed
= 0;
5895 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5896 edp_panel_vdd_work
);
5898 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5899 drm_connector_register(connector
);
5902 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5904 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5905 intel_connector
->unregister
= intel_dp_connector_unregister
;
5907 /* Set up the hotplug pin. */
5910 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5913 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5914 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5915 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5918 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5921 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5924 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5930 if (is_edp(intel_dp
)) {
5932 intel_dp_init_panel_power_timestamps(intel_dp
);
5933 if (IS_VALLEYVIEW(dev
))
5934 vlv_initial_power_sequencer_setup(intel_dp
);
5936 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5937 pps_unlock(intel_dp
);
5940 ret
= intel_dp_aux_init(intel_dp
, intel_connector
);
5944 /* init MST on ports that can support it */
5945 if (HAS_DP_MST(dev
) &&
5946 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5947 intel_dp_mst_encoder_init(intel_dig_port
,
5948 intel_connector
->base
.base
.id
);
5950 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5951 intel_dp_aux_fini(intel_dp
);
5952 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5956 intel_dp_add_properties(intel_dp
, connector
);
5958 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5959 * 0xd. Failure to do so will result in spurious interrupts being
5960 * generated on the port when a cable is not attached.
5962 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5963 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5964 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5967 i915_debugfs_connector_add(connector
);
5972 if (is_edp(intel_dp
)) {
5973 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5975 * vdd might still be enabled do to the delayed vdd off.
5976 * Make sure vdd is actually turned off here.
5979 edp_panel_vdd_off_sync(intel_dp
);
5980 pps_unlock(intel_dp
);
5982 drm_connector_unregister(connector
);
5983 drm_connector_cleanup(connector
);
5989 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5992 struct intel_digital_port
*intel_dig_port
;
5993 struct intel_encoder
*intel_encoder
;
5994 struct drm_encoder
*encoder
;
5995 struct intel_connector
*intel_connector
;
5997 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5998 if (!intel_dig_port
)
6001 intel_connector
= intel_connector_alloc();
6002 if (!intel_connector
)
6003 goto err_connector_alloc
;
6005 intel_encoder
= &intel_dig_port
->base
;
6006 encoder
= &intel_encoder
->base
;
6008 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
6009 DRM_MODE_ENCODER_TMDS
);
6011 intel_encoder
->compute_config
= intel_dp_compute_config
;
6012 intel_encoder
->disable
= intel_disable_dp
;
6013 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
6014 intel_encoder
->get_config
= intel_dp_get_config
;
6015 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
6016 if (IS_CHERRYVIEW(dev
)) {
6017 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
6018 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
6019 intel_encoder
->enable
= vlv_enable_dp
;
6020 intel_encoder
->post_disable
= chv_post_disable_dp
;
6021 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
6022 } else if (IS_VALLEYVIEW(dev
)) {
6023 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
6024 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
6025 intel_encoder
->enable
= vlv_enable_dp
;
6026 intel_encoder
->post_disable
= vlv_post_disable_dp
;
6028 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
6029 intel_encoder
->enable
= g4x_enable_dp
;
6030 if (INTEL_INFO(dev
)->gen
>= 5)
6031 intel_encoder
->post_disable
= ilk_post_disable_dp
;
6034 intel_dig_port
->port
= port
;
6035 intel_dig_port
->dp
.output_reg
= output_reg
;
6037 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
6038 if (IS_CHERRYVIEW(dev
)) {
6040 intel_encoder
->crtc_mask
= 1 << 2;
6042 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
6044 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
6046 intel_encoder
->cloneable
= 0;
6048 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
6049 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
6051 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
6052 goto err_init_connector
;
6057 drm_encoder_cleanup(encoder
);
6058 kfree(intel_connector
);
6059 err_connector_alloc
:
6060 kfree(intel_dig_port
);
6065 void intel_dp_mst_suspend(struct drm_device
*dev
)
6067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6071 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6072 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6073 if (!intel_dig_port
)
6076 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
6077 if (!intel_dig_port
->dp
.can_mst
)
6079 if (intel_dig_port
->dp
.is_mst
)
6080 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
6085 void intel_dp_mst_resume(struct drm_device
*dev
)
6087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6090 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
6091 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
6092 if (!intel_dig_port
)
6094 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
6097 if (!intel_dig_port
->dp
.can_mst
)
6100 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6102 intel_dp_check_mst_status(&intel_dig_port
->dp
);