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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44 };
45
46 static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51 };
52
53 static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58 };
59
60 static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65 };
66
67 /**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74 static bool is_edp(struct intel_dp *intel_dp)
75 {
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
79 }
80
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
82 {
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
86 }
87
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89 {
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
91 }
92
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
95
96 static int
97 intel_dp_max_link_bw(struct intel_dp *intel_dp)
98 {
99 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
100 struct drm_device *dev = intel_dp->attached_connector->base.dev;
101
102 switch (max_link_bw) {
103 case DP_LINK_BW_1_62:
104 case DP_LINK_BW_2_7:
105 break;
106 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
107 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
108 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
109 max_link_bw = DP_LINK_BW_5_4;
110 else
111 max_link_bw = DP_LINK_BW_2_7;
112 break;
113 default:
114 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
115 max_link_bw);
116 max_link_bw = DP_LINK_BW_1_62;
117 break;
118 }
119 return max_link_bw;
120 }
121
122 /*
123 * The units on the numbers in the next two are... bizarre. Examples will
124 * make it clearer; this one parallels an example in the eDP spec.
125 *
126 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
127 *
128 * 270000 * 1 * 8 / 10 == 216000
129 *
130 * The actual data capacity of that configuration is 2.16Gbit/s, so the
131 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
132 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
133 * 119000. At 18bpp that's 2142000 kilobits per second.
134 *
135 * Thus the strange-looking division by 10 in intel_dp_link_required, to
136 * get the result in decakilobits instead of kilobits.
137 */
138
139 static int
140 intel_dp_link_required(int pixel_clock, int bpp)
141 {
142 return (pixel_clock * bpp + 9) / 10;
143 }
144
145 static int
146 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
147 {
148 return (max_link_clock * max_lanes * 8) / 10;
149 }
150
151 static enum drm_mode_status
152 intel_dp_mode_valid(struct drm_connector *connector,
153 struct drm_display_mode *mode)
154 {
155 struct intel_dp *intel_dp = intel_attached_dp(connector);
156 struct intel_connector *intel_connector = to_intel_connector(connector);
157 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
158 int target_clock = mode->clock;
159 int max_rate, mode_rate, max_lanes, max_link_clock;
160
161 if (is_edp(intel_dp) && fixed_mode) {
162 if (mode->hdisplay > fixed_mode->hdisplay)
163 return MODE_PANEL;
164
165 if (mode->vdisplay > fixed_mode->vdisplay)
166 return MODE_PANEL;
167
168 target_clock = fixed_mode->clock;
169 }
170
171 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
172 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
173
174 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
175 mode_rate = intel_dp_link_required(target_clock, 18);
176
177 if (mode_rate > max_rate)
178 return MODE_CLOCK_HIGH;
179
180 if (mode->clock < 10000)
181 return MODE_CLOCK_LOW;
182
183 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
184 return MODE_H_ILLEGAL;
185
186 return MODE_OK;
187 }
188
189 static uint32_t
190 pack_aux(uint8_t *src, int src_bytes)
191 {
192 int i;
193 uint32_t v = 0;
194
195 if (src_bytes > 4)
196 src_bytes = 4;
197 for (i = 0; i < src_bytes; i++)
198 v |= ((uint32_t) src[i]) << ((3-i) * 8);
199 return v;
200 }
201
202 static void
203 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
204 {
205 int i;
206 if (dst_bytes > 4)
207 dst_bytes = 4;
208 for (i = 0; i < dst_bytes; i++)
209 dst[i] = src >> ((3-i) * 8);
210 }
211
212 /* hrawclock is 1/4 the FSB frequency */
213 static int
214 intel_hrawclk(struct drm_device *dev)
215 {
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 uint32_t clkcfg;
218
219 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
220 if (IS_VALLEYVIEW(dev))
221 return 200;
222
223 clkcfg = I915_READ(CLKCFG);
224 switch (clkcfg & CLKCFG_FSB_MASK) {
225 case CLKCFG_FSB_400:
226 return 100;
227 case CLKCFG_FSB_533:
228 return 133;
229 case CLKCFG_FSB_667:
230 return 166;
231 case CLKCFG_FSB_800:
232 return 200;
233 case CLKCFG_FSB_1067:
234 return 266;
235 case CLKCFG_FSB_1333:
236 return 333;
237 /* these two are just a guess; one of them might be right */
238 case CLKCFG_FSB_1600:
239 case CLKCFG_FSB_1600_ALT:
240 return 400;
241 default:
242 return 133;
243 }
244 }
245
246 static void
247 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
248 struct intel_dp *intel_dp,
249 struct edp_power_seq *out);
250 static void
251 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
252 struct intel_dp *intel_dp,
253 struct edp_power_seq *out);
254
255 static enum pipe
256 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
257 {
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
260 struct drm_device *dev = intel_dig_port->base.base.dev;
261 struct drm_i915_private *dev_priv = dev->dev_private;
262 enum port port = intel_dig_port->port;
263 enum pipe pipe;
264
265 /* modeset should have pipe */
266 if (crtc)
267 return to_intel_crtc(crtc)->pipe;
268
269 /* init time, try to find a pipe with this port selected */
270 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
271 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
272 PANEL_PORT_SELECT_MASK;
273 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
274 return pipe;
275 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
276 return pipe;
277 }
278
279 /* shrug */
280 return PIPE_A;
281 }
282
283 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
284 {
285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
286
287 if (HAS_PCH_SPLIT(dev))
288 return PCH_PP_CONTROL;
289 else
290 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
291 }
292
293 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
294 {
295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
296
297 if (HAS_PCH_SPLIT(dev))
298 return PCH_PP_STATUS;
299 else
300 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
301 }
302
303 static bool edp_have_panel_power(struct intel_dp *intel_dp)
304 {
305 struct drm_device *dev = intel_dp_to_dev(intel_dp);
306 struct drm_i915_private *dev_priv = dev->dev_private;
307
308 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
309 }
310
311 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
312 {
313 struct drm_device *dev = intel_dp_to_dev(intel_dp);
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
317 }
318
319 static void
320 intel_dp_check_edp(struct intel_dp *intel_dp)
321 {
322 struct drm_device *dev = intel_dp_to_dev(intel_dp);
323 struct drm_i915_private *dev_priv = dev->dev_private;
324
325 if (!is_edp(intel_dp))
326 return;
327
328 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
329 WARN(1, "eDP powered off while attempting aux channel communication.\n");
330 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
331 I915_READ(_pp_stat_reg(intel_dp)),
332 I915_READ(_pp_ctrl_reg(intel_dp)));
333 }
334 }
335
336 static uint32_t
337 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
338 {
339 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
340 struct drm_device *dev = intel_dig_port->base.base.dev;
341 struct drm_i915_private *dev_priv = dev->dev_private;
342 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
343 uint32_t status;
344 bool done;
345
346 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
347 if (has_aux_irq)
348 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
349 msecs_to_jiffies_timeout(10));
350 else
351 done = wait_for_atomic(C, 10) == 0;
352 if (!done)
353 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
354 has_aux_irq);
355 #undef C
356
357 return status;
358 }
359
360 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
361 {
362 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
363 struct drm_device *dev = intel_dig_port->base.base.dev;
364
365 /*
366 * The clock divider is based off the hrawclk, and would like to run at
367 * 2MHz. So, take the hrawclk value and divide by 2 and use that
368 */
369 return index ? 0 : intel_hrawclk(dev) / 2;
370 }
371
372 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
373 {
374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
375 struct drm_device *dev = intel_dig_port->base.base.dev;
376
377 if (index)
378 return 0;
379
380 if (intel_dig_port->port == PORT_A) {
381 if (IS_GEN6(dev) || IS_GEN7(dev))
382 return 200; /* SNB & IVB eDP input clock at 400Mhz */
383 else
384 return 225; /* eDP input clock at 450Mhz */
385 } else {
386 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
387 }
388 }
389
390 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
391 {
392 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
393 struct drm_device *dev = intel_dig_port->base.base.dev;
394 struct drm_i915_private *dev_priv = dev->dev_private;
395
396 if (intel_dig_port->port == PORT_A) {
397 if (index)
398 return 0;
399 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
400 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
401 /* Workaround for non-ULT HSW */
402 switch (index) {
403 case 0: return 63;
404 case 1: return 72;
405 default: return 0;
406 }
407 } else {
408 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
409 }
410 }
411
412 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
413 {
414 return index ? 0 : 100;
415 }
416
417 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
418 bool has_aux_irq,
419 int send_bytes,
420 uint32_t aux_clock_divider)
421 {
422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
423 struct drm_device *dev = intel_dig_port->base.base.dev;
424 uint32_t precharge, timeout;
425
426 if (IS_GEN6(dev))
427 precharge = 3;
428 else
429 precharge = 5;
430
431 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
432 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
433 else
434 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
435
436 return DP_AUX_CH_CTL_SEND_BUSY |
437 DP_AUX_CH_CTL_DONE |
438 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
439 DP_AUX_CH_CTL_TIME_OUT_ERROR |
440 timeout |
441 DP_AUX_CH_CTL_RECEIVE_ERROR |
442 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
443 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
444 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
445 }
446
447 static int
448 intel_dp_aux_ch(struct intel_dp *intel_dp,
449 uint8_t *send, int send_bytes,
450 uint8_t *recv, int recv_size)
451 {
452 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
453 struct drm_device *dev = intel_dig_port->base.base.dev;
454 struct drm_i915_private *dev_priv = dev->dev_private;
455 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
456 uint32_t ch_data = ch_ctl + 4;
457 uint32_t aux_clock_divider;
458 int i, ret, recv_bytes;
459 uint32_t status;
460 int try, clock = 0;
461 bool has_aux_irq = HAS_AUX_IRQ(dev);
462
463 /* dp aux is extremely sensitive to irq latency, hence request the
464 * lowest possible wakeup latency and so prevent the cpu from going into
465 * deep sleep states.
466 */
467 pm_qos_update_request(&dev_priv->pm_qos, 0);
468
469 intel_dp_check_edp(intel_dp);
470
471 intel_aux_display_runtime_get(dev_priv);
472
473 /* Try to wait for any previous AUX channel activity */
474 for (try = 0; try < 3; try++) {
475 status = I915_READ_NOTRACE(ch_ctl);
476 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
477 break;
478 msleep(1);
479 }
480
481 if (try == 3) {
482 WARN(1, "dp_aux_ch not started status 0x%08x\n",
483 I915_READ(ch_ctl));
484 ret = -EBUSY;
485 goto out;
486 }
487
488 /* Only 5 data registers! */
489 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
490 ret = -E2BIG;
491 goto out;
492 }
493
494 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
495 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
496 has_aux_irq,
497 send_bytes,
498 aux_clock_divider);
499
500 /* Must try at least 3 times according to DP spec */
501 for (try = 0; try < 5; try++) {
502 /* Load the send data into the aux channel data registers */
503 for (i = 0; i < send_bytes; i += 4)
504 I915_WRITE(ch_data + i,
505 pack_aux(send + i, send_bytes - i));
506
507 /* Send the command and wait for it to complete */
508 I915_WRITE(ch_ctl, send_ctl);
509
510 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
511
512 /* Clear done status and any errors */
513 I915_WRITE(ch_ctl,
514 status |
515 DP_AUX_CH_CTL_DONE |
516 DP_AUX_CH_CTL_TIME_OUT_ERROR |
517 DP_AUX_CH_CTL_RECEIVE_ERROR);
518
519 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
520 DP_AUX_CH_CTL_RECEIVE_ERROR))
521 continue;
522 if (status & DP_AUX_CH_CTL_DONE)
523 break;
524 }
525 if (status & DP_AUX_CH_CTL_DONE)
526 break;
527 }
528
529 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
530 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
531 ret = -EBUSY;
532 goto out;
533 }
534
535 /* Check for timeout or receive error.
536 * Timeouts occur when the sink is not connected
537 */
538 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
539 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
540 ret = -EIO;
541 goto out;
542 }
543
544 /* Timeouts occur when the device isn't connected, so they're
545 * "normal" -- don't fill the kernel log with these */
546 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
547 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
548 ret = -ETIMEDOUT;
549 goto out;
550 }
551
552 /* Unload any bytes sent back from the other side */
553 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
554 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
555 if (recv_bytes > recv_size)
556 recv_bytes = recv_size;
557
558 for (i = 0; i < recv_bytes; i += 4)
559 unpack_aux(I915_READ(ch_data + i),
560 recv + i, recv_bytes - i);
561
562 ret = recv_bytes;
563 out:
564 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
565 intel_aux_display_runtime_put(dev_priv);
566
567 return ret;
568 }
569
570 /* Write data to the aux channel in native mode */
571 static int
572 intel_dp_aux_native_write(struct intel_dp *intel_dp,
573 uint16_t address, uint8_t *send, int send_bytes)
574 {
575 int ret;
576 uint8_t msg[20];
577 int msg_bytes;
578 uint8_t ack;
579 int retry;
580
581 if (WARN_ON(send_bytes > 16))
582 return -E2BIG;
583
584 intel_dp_check_edp(intel_dp);
585 msg[0] = DP_AUX_NATIVE_WRITE << 4;
586 msg[1] = address >> 8;
587 msg[2] = address & 0xff;
588 msg[3] = send_bytes - 1;
589 memcpy(&msg[4], send, send_bytes);
590 msg_bytes = send_bytes + 4;
591 for (retry = 0; retry < 7; retry++) {
592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
593 if (ret < 0)
594 return ret;
595 ack >>= 4;
596 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
597 return send_bytes;
598 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
599 usleep_range(400, 500);
600 else
601 return -EIO;
602 }
603
604 DRM_ERROR("too many retries, giving up\n");
605 return -EIO;
606 }
607
608 /* Write a single byte to the aux channel in native mode */
609 static int
610 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
611 uint16_t address, uint8_t byte)
612 {
613 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
614 }
615
616 /* read bytes from a native aux channel */
617 static int
618 intel_dp_aux_native_read(struct intel_dp *intel_dp,
619 uint16_t address, uint8_t *recv, int recv_bytes)
620 {
621 uint8_t msg[4];
622 int msg_bytes;
623 uint8_t reply[20];
624 int reply_bytes;
625 uint8_t ack;
626 int ret;
627 int retry;
628
629 if (WARN_ON(recv_bytes > 19))
630 return -E2BIG;
631
632 intel_dp_check_edp(intel_dp);
633 msg[0] = DP_AUX_NATIVE_READ << 4;
634 msg[1] = address >> 8;
635 msg[2] = address & 0xff;
636 msg[3] = recv_bytes - 1;
637
638 msg_bytes = 4;
639 reply_bytes = recv_bytes + 1;
640
641 for (retry = 0; retry < 7; retry++) {
642 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
643 reply, reply_bytes);
644 if (ret == 0)
645 return -EPROTO;
646 if (ret < 0)
647 return ret;
648 ack = reply[0] >> 4;
649 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
650 memcpy(recv, reply + 1, ret - 1);
651 return ret - 1;
652 }
653 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
654 usleep_range(400, 500);
655 else
656 return -EIO;
657 }
658
659 DRM_ERROR("too many retries, giving up\n");
660 return -EIO;
661 }
662
663 static int
664 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
665 uint8_t write_byte, uint8_t *read_byte)
666 {
667 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
668 struct intel_dp *intel_dp = container_of(adapter,
669 struct intel_dp,
670 adapter);
671 uint16_t address = algo_data->address;
672 uint8_t msg[5];
673 uint8_t reply[2];
674 unsigned retry;
675 int msg_bytes;
676 int reply_bytes;
677 int ret;
678
679 edp_panel_vdd_on(intel_dp);
680 intel_dp_check_edp(intel_dp);
681 /* Set up the command byte */
682 if (mode & MODE_I2C_READ)
683 msg[0] = DP_AUX_I2C_READ << 4;
684 else
685 msg[0] = DP_AUX_I2C_WRITE << 4;
686
687 if (!(mode & MODE_I2C_STOP))
688 msg[0] |= DP_AUX_I2C_MOT << 4;
689
690 msg[1] = address >> 8;
691 msg[2] = address;
692
693 switch (mode) {
694 case MODE_I2C_WRITE:
695 msg[3] = 0;
696 msg[4] = write_byte;
697 msg_bytes = 5;
698 reply_bytes = 1;
699 break;
700 case MODE_I2C_READ:
701 msg[3] = 0;
702 msg_bytes = 4;
703 reply_bytes = 2;
704 break;
705 default:
706 msg_bytes = 3;
707 reply_bytes = 1;
708 break;
709 }
710
711 /*
712 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
713 * required to retry at least seven times upon receiving AUX_DEFER
714 * before giving up the AUX transaction.
715 */
716 for (retry = 0; retry < 7; retry++) {
717 ret = intel_dp_aux_ch(intel_dp,
718 msg, msg_bytes,
719 reply, reply_bytes);
720 if (ret < 0) {
721 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
722 goto out;
723 }
724
725 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
726 case DP_AUX_NATIVE_REPLY_ACK:
727 /* I2C-over-AUX Reply field is only valid
728 * when paired with AUX ACK.
729 */
730 break;
731 case DP_AUX_NATIVE_REPLY_NACK:
732 DRM_DEBUG_KMS("aux_ch native nack\n");
733 ret = -EREMOTEIO;
734 goto out;
735 case DP_AUX_NATIVE_REPLY_DEFER:
736 /*
737 * For now, just give more slack to branch devices. We
738 * could check the DPCD for I2C bit rate capabilities,
739 * and if available, adjust the interval. We could also
740 * be more careful with DP-to-Legacy adapters where a
741 * long legacy cable may force very low I2C bit rates.
742 */
743 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
744 DP_DWN_STRM_PORT_PRESENT)
745 usleep_range(500, 600);
746 else
747 usleep_range(300, 400);
748 continue;
749 default:
750 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
751 reply[0]);
752 ret = -EREMOTEIO;
753 goto out;
754 }
755
756 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
757 case DP_AUX_I2C_REPLY_ACK:
758 if (mode == MODE_I2C_READ) {
759 *read_byte = reply[1];
760 }
761 ret = reply_bytes - 1;
762 goto out;
763 case DP_AUX_I2C_REPLY_NACK:
764 DRM_DEBUG_KMS("aux_i2c nack\n");
765 ret = -EREMOTEIO;
766 goto out;
767 case DP_AUX_I2C_REPLY_DEFER:
768 DRM_DEBUG_KMS("aux_i2c defer\n");
769 udelay(100);
770 break;
771 default:
772 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
773 ret = -EREMOTEIO;
774 goto out;
775 }
776 }
777
778 DRM_ERROR("too many retries, giving up\n");
779 ret = -EREMOTEIO;
780
781 out:
782 edp_panel_vdd_off(intel_dp, false);
783 return ret;
784 }
785
786 static void
787 intel_dp_connector_unregister(struct intel_connector *intel_connector)
788 {
789 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
790
791 sysfs_remove_link(&intel_connector->base.kdev->kobj,
792 intel_dp->adapter.dev.kobj.name);
793 intel_connector_unregister(intel_connector);
794 }
795
796 static int
797 intel_dp_i2c_init(struct intel_dp *intel_dp,
798 struct intel_connector *intel_connector, const char *name)
799 {
800 int ret;
801
802 DRM_DEBUG_KMS("i2c_init %s\n", name);
803 intel_dp->algo.running = false;
804 intel_dp->algo.address = 0;
805 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
806
807 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
808 intel_dp->adapter.owner = THIS_MODULE;
809 intel_dp->adapter.class = I2C_CLASS_DDC;
810 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
811 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
812 intel_dp->adapter.algo_data = &intel_dp->algo;
813 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
814
815 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
816 if (ret < 0)
817 return ret;
818
819 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
820 &intel_dp->adapter.dev.kobj,
821 intel_dp->adapter.dev.kobj.name);
822
823 if (ret < 0)
824 i2c_del_adapter(&intel_dp->adapter);
825
826 return ret;
827 }
828
829 static void
830 intel_dp_set_clock(struct intel_encoder *encoder,
831 struct intel_crtc_config *pipe_config, int link_bw)
832 {
833 struct drm_device *dev = encoder->base.dev;
834 const struct dp_link_dpll *divisor = NULL;
835 int i, count = 0;
836
837 if (IS_G4X(dev)) {
838 divisor = gen4_dpll;
839 count = ARRAY_SIZE(gen4_dpll);
840 } else if (IS_HASWELL(dev)) {
841 /* Haswell has special-purpose DP DDI clocks. */
842 } else if (HAS_PCH_SPLIT(dev)) {
843 divisor = pch_dpll;
844 count = ARRAY_SIZE(pch_dpll);
845 } else if (IS_VALLEYVIEW(dev)) {
846 divisor = vlv_dpll;
847 count = ARRAY_SIZE(vlv_dpll);
848 }
849
850 if (divisor && count) {
851 for (i = 0; i < count; i++) {
852 if (link_bw == divisor[i].link_bw) {
853 pipe_config->dpll = divisor[i].dpll;
854 pipe_config->clock_set = true;
855 break;
856 }
857 }
858 }
859 }
860
861 bool
862 intel_dp_compute_config(struct intel_encoder *encoder,
863 struct intel_crtc_config *pipe_config)
864 {
865 struct drm_device *dev = encoder->base.dev;
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
868 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
869 enum port port = dp_to_dig_port(intel_dp)->port;
870 struct intel_crtc *intel_crtc = encoder->new_crtc;
871 struct intel_connector *intel_connector = intel_dp->attached_connector;
872 int lane_count, clock;
873 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
874 /* Conveniently, the link BW constants become indices with a shift...*/
875 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
876 int bpp, mode_rate;
877 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
878 int link_avail, link_clock;
879
880 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
881 pipe_config->has_pch_encoder = true;
882
883 pipe_config->has_dp_encoder = true;
884
885 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
886 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
887 adjusted_mode);
888 if (!HAS_PCH_SPLIT(dev))
889 intel_gmch_panel_fitting(intel_crtc, pipe_config,
890 intel_connector->panel.fitting_mode);
891 else
892 intel_pch_panel_fitting(intel_crtc, pipe_config,
893 intel_connector->panel.fitting_mode);
894 }
895
896 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
897 return false;
898
899 DRM_DEBUG_KMS("DP link computation with max lane count %i "
900 "max bw %02x pixel clock %iKHz\n",
901 max_lane_count, bws[max_clock],
902 adjusted_mode->crtc_clock);
903
904 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
905 * bpc in between. */
906 bpp = pipe_config->pipe_bpp;
907 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
908 dev_priv->vbt.edp_bpp < bpp) {
909 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
910 dev_priv->vbt.edp_bpp);
911 bpp = dev_priv->vbt.edp_bpp;
912 }
913
914 for (; bpp >= 6*3; bpp -= 2*3) {
915 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
916 bpp);
917
918 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
919 for (clock = 0; clock <= max_clock; clock++) {
920 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
921 link_avail = intel_dp_max_data_rate(link_clock,
922 lane_count);
923
924 if (mode_rate <= link_avail) {
925 goto found;
926 }
927 }
928 }
929 }
930
931 return false;
932
933 found:
934 if (intel_dp->color_range_auto) {
935 /*
936 * See:
937 * CEA-861-E - 5.1 Default Encoding Parameters
938 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
939 */
940 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
941 intel_dp->color_range = DP_COLOR_RANGE_16_235;
942 else
943 intel_dp->color_range = 0;
944 }
945
946 if (intel_dp->color_range)
947 pipe_config->limited_color_range = true;
948
949 intel_dp->link_bw = bws[clock];
950 intel_dp->lane_count = lane_count;
951 pipe_config->pipe_bpp = bpp;
952 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
953
954 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
955 intel_dp->link_bw, intel_dp->lane_count,
956 pipe_config->port_clock, bpp);
957 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
958 mode_rate, link_avail);
959
960 intel_link_compute_m_n(bpp, lane_count,
961 adjusted_mode->crtc_clock,
962 pipe_config->port_clock,
963 &pipe_config->dp_m_n);
964
965 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
966
967 return true;
968 }
969
970 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
971 {
972 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
973 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
974 struct drm_device *dev = crtc->base.dev;
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 u32 dpa_ctl;
977
978 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
979 dpa_ctl = I915_READ(DP_A);
980 dpa_ctl &= ~DP_PLL_FREQ_MASK;
981
982 if (crtc->config.port_clock == 162000) {
983 /* For a long time we've carried around a ILK-DevA w/a for the
984 * 160MHz clock. If we're really unlucky, it's still required.
985 */
986 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
987 dpa_ctl |= DP_PLL_FREQ_160MHZ;
988 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
989 } else {
990 dpa_ctl |= DP_PLL_FREQ_270MHZ;
991 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
992 }
993
994 I915_WRITE(DP_A, dpa_ctl);
995
996 POSTING_READ(DP_A);
997 udelay(500);
998 }
999
1000 static void intel_dp_mode_set(struct intel_encoder *encoder)
1001 {
1002 struct drm_device *dev = encoder->base.dev;
1003 struct drm_i915_private *dev_priv = dev->dev_private;
1004 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1005 enum port port = dp_to_dig_port(intel_dp)->port;
1006 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1007 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1008
1009 /*
1010 * There are four kinds of DP registers:
1011 *
1012 * IBX PCH
1013 * SNB CPU
1014 * IVB CPU
1015 * CPT PCH
1016 *
1017 * IBX PCH and CPU are the same for almost everything,
1018 * except that the CPU DP PLL is configured in this
1019 * register
1020 *
1021 * CPT PCH is quite different, having many bits moved
1022 * to the TRANS_DP_CTL register instead. That
1023 * configuration happens (oddly) in ironlake_pch_enable
1024 */
1025
1026 /* Preserve the BIOS-computed detected bit. This is
1027 * supposed to be read-only.
1028 */
1029 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1030
1031 /* Handle DP bits in common between all three register formats */
1032 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1033 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1034
1035 if (intel_dp->has_audio) {
1036 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1037 pipe_name(crtc->pipe));
1038 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1039 intel_write_eld(&encoder->base, adjusted_mode);
1040 }
1041
1042 /* Split out the IBX/CPU vs CPT settings */
1043
1044 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1045 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1046 intel_dp->DP |= DP_SYNC_HS_HIGH;
1047 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1048 intel_dp->DP |= DP_SYNC_VS_HIGH;
1049 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1050
1051 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1052 intel_dp->DP |= DP_ENHANCED_FRAMING;
1053
1054 intel_dp->DP |= crtc->pipe << 29;
1055 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1056 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1057 intel_dp->DP |= intel_dp->color_range;
1058
1059 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1060 intel_dp->DP |= DP_SYNC_HS_HIGH;
1061 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1062 intel_dp->DP |= DP_SYNC_VS_HIGH;
1063 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1064
1065 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1066 intel_dp->DP |= DP_ENHANCED_FRAMING;
1067
1068 if (crtc->pipe == 1)
1069 intel_dp->DP |= DP_PIPEB_SELECT;
1070 } else {
1071 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1072 }
1073
1074 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1075 ironlake_set_pll_cpu_edp(intel_dp);
1076 }
1077
1078 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1079 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1080
1081 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1082 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1083
1084 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1085 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1086
1087 static void wait_panel_status(struct intel_dp *intel_dp,
1088 u32 mask,
1089 u32 value)
1090 {
1091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 u32 pp_stat_reg, pp_ctrl_reg;
1094
1095 pp_stat_reg = _pp_stat_reg(intel_dp);
1096 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1097
1098 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1099 mask, value,
1100 I915_READ(pp_stat_reg),
1101 I915_READ(pp_ctrl_reg));
1102
1103 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1104 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1105 I915_READ(pp_stat_reg),
1106 I915_READ(pp_ctrl_reg));
1107 }
1108
1109 DRM_DEBUG_KMS("Wait complete\n");
1110 }
1111
1112 static void wait_panel_on(struct intel_dp *intel_dp)
1113 {
1114 DRM_DEBUG_KMS("Wait for panel power on\n");
1115 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1116 }
1117
1118 static void wait_panel_off(struct intel_dp *intel_dp)
1119 {
1120 DRM_DEBUG_KMS("Wait for panel power off time\n");
1121 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1122 }
1123
1124 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1125 {
1126 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1127
1128 /* When we disable the VDD override bit last we have to do the manual
1129 * wait. */
1130 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1131 intel_dp->panel_power_cycle_delay);
1132
1133 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1134 }
1135
1136 static void wait_backlight_on(struct intel_dp *intel_dp)
1137 {
1138 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1139 intel_dp->backlight_on_delay);
1140 }
1141
1142 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1143 {
1144 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1145 intel_dp->backlight_off_delay);
1146 }
1147
1148 /* Read the current pp_control value, unlocking the register if it
1149 * is locked
1150 */
1151
1152 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1153 {
1154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 control;
1157
1158 control = I915_READ(_pp_ctrl_reg(intel_dp));
1159 control &= ~PANEL_UNLOCK_MASK;
1160 control |= PANEL_UNLOCK_REGS;
1161 return control;
1162 }
1163
1164 void edp_panel_vdd_on(struct intel_dp *intel_dp)
1165 {
1166 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 u32 pp;
1169 u32 pp_stat_reg, pp_ctrl_reg;
1170
1171 if (!is_edp(intel_dp))
1172 return;
1173
1174 WARN(intel_dp->want_panel_vdd,
1175 "eDP VDD already requested on\n");
1176
1177 intel_dp->want_panel_vdd = true;
1178
1179 if (edp_have_panel_vdd(intel_dp))
1180 return;
1181
1182 intel_runtime_pm_get(dev_priv);
1183
1184 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1185
1186 if (!edp_have_panel_power(intel_dp))
1187 wait_panel_power_cycle(intel_dp);
1188
1189 pp = ironlake_get_pp_control(intel_dp);
1190 pp |= EDP_FORCE_VDD;
1191
1192 pp_stat_reg = _pp_stat_reg(intel_dp);
1193 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1194
1195 I915_WRITE(pp_ctrl_reg, pp);
1196 POSTING_READ(pp_ctrl_reg);
1197 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1198 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1199 /*
1200 * If the panel wasn't on, delay before accessing aux channel
1201 */
1202 if (!edp_have_panel_power(intel_dp)) {
1203 DRM_DEBUG_KMS("eDP was not running\n");
1204 msleep(intel_dp->panel_power_up_delay);
1205 }
1206 }
1207
1208 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1209 {
1210 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 u32 pp;
1213 u32 pp_stat_reg, pp_ctrl_reg;
1214
1215 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1216
1217 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1218 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1219
1220 pp = ironlake_get_pp_control(intel_dp);
1221 pp &= ~EDP_FORCE_VDD;
1222
1223 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1224 pp_stat_reg = _pp_stat_reg(intel_dp);
1225
1226 I915_WRITE(pp_ctrl_reg, pp);
1227 POSTING_READ(pp_ctrl_reg);
1228
1229 /* Make sure sequencer is idle before allowing subsequent activity */
1230 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1231 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1232
1233 if ((pp & POWER_TARGET_ON) == 0)
1234 intel_dp->last_power_cycle = jiffies;
1235
1236 intel_runtime_pm_put(dev_priv);
1237 }
1238 }
1239
1240 static void edp_panel_vdd_work(struct work_struct *__work)
1241 {
1242 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1243 struct intel_dp, panel_vdd_work);
1244 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1245
1246 mutex_lock(&dev->mode_config.mutex);
1247 edp_panel_vdd_off_sync(intel_dp);
1248 mutex_unlock(&dev->mode_config.mutex);
1249 }
1250
1251 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1252 {
1253 if (!is_edp(intel_dp))
1254 return;
1255
1256 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1257
1258 intel_dp->want_panel_vdd = false;
1259
1260 if (sync) {
1261 edp_panel_vdd_off_sync(intel_dp);
1262 } else {
1263 /*
1264 * Queue the timer to fire a long
1265 * time from now (relative to the power down delay)
1266 * to keep the panel power up across a sequence of operations
1267 */
1268 schedule_delayed_work(&intel_dp->panel_vdd_work,
1269 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1270 }
1271 }
1272
1273 void intel_edp_panel_on(struct intel_dp *intel_dp)
1274 {
1275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 u32 pp;
1278 u32 pp_ctrl_reg;
1279
1280 if (!is_edp(intel_dp))
1281 return;
1282
1283 DRM_DEBUG_KMS("Turn eDP power on\n");
1284
1285 if (edp_have_panel_power(intel_dp)) {
1286 DRM_DEBUG_KMS("eDP power already on\n");
1287 return;
1288 }
1289
1290 wait_panel_power_cycle(intel_dp);
1291
1292 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1293 pp = ironlake_get_pp_control(intel_dp);
1294 if (IS_GEN5(dev)) {
1295 /* ILK workaround: disable reset around power sequence */
1296 pp &= ~PANEL_POWER_RESET;
1297 I915_WRITE(pp_ctrl_reg, pp);
1298 POSTING_READ(pp_ctrl_reg);
1299 }
1300
1301 pp |= POWER_TARGET_ON;
1302 if (!IS_GEN5(dev))
1303 pp |= PANEL_POWER_RESET;
1304
1305 I915_WRITE(pp_ctrl_reg, pp);
1306 POSTING_READ(pp_ctrl_reg);
1307
1308 wait_panel_on(intel_dp);
1309 intel_dp->last_power_on = jiffies;
1310
1311 if (IS_GEN5(dev)) {
1312 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1313 I915_WRITE(pp_ctrl_reg, pp);
1314 POSTING_READ(pp_ctrl_reg);
1315 }
1316 }
1317
1318 void intel_edp_panel_off(struct intel_dp *intel_dp)
1319 {
1320 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1321 struct drm_i915_private *dev_priv = dev->dev_private;
1322 u32 pp;
1323 u32 pp_ctrl_reg;
1324
1325 if (!is_edp(intel_dp))
1326 return;
1327
1328 DRM_DEBUG_KMS("Turn eDP power off\n");
1329
1330 edp_wait_backlight_off(intel_dp);
1331
1332 pp = ironlake_get_pp_control(intel_dp);
1333 /* We need to switch off panel power _and_ force vdd, for otherwise some
1334 * panels get very unhappy and cease to work. */
1335 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1336 EDP_BLC_ENABLE);
1337
1338 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1339
1340 intel_dp->want_panel_vdd = false;
1341
1342 I915_WRITE(pp_ctrl_reg, pp);
1343 POSTING_READ(pp_ctrl_reg);
1344
1345 intel_dp->last_power_cycle = jiffies;
1346 wait_panel_off(intel_dp);
1347
1348 /* We got a reference when we enabled the VDD. */
1349 intel_runtime_pm_put(dev_priv);
1350 }
1351
1352 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1353 {
1354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1355 struct drm_device *dev = intel_dig_port->base.base.dev;
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 u32 pp;
1358 u32 pp_ctrl_reg;
1359
1360 if (!is_edp(intel_dp))
1361 return;
1362
1363 DRM_DEBUG_KMS("\n");
1364 /*
1365 * If we enable the backlight right away following a panel power
1366 * on, we may see slight flicker as the panel syncs with the eDP
1367 * link. So delay a bit to make sure the image is solid before
1368 * allowing it to appear.
1369 */
1370 wait_backlight_on(intel_dp);
1371 pp = ironlake_get_pp_control(intel_dp);
1372 pp |= EDP_BLC_ENABLE;
1373
1374 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1375
1376 I915_WRITE(pp_ctrl_reg, pp);
1377 POSTING_READ(pp_ctrl_reg);
1378
1379 intel_panel_enable_backlight(intel_dp->attached_connector);
1380 }
1381
1382 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1383 {
1384 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 u32 pp;
1387 u32 pp_ctrl_reg;
1388
1389 if (!is_edp(intel_dp))
1390 return;
1391
1392 intel_panel_disable_backlight(intel_dp->attached_connector);
1393
1394 DRM_DEBUG_KMS("\n");
1395 pp = ironlake_get_pp_control(intel_dp);
1396 pp &= ~EDP_BLC_ENABLE;
1397
1398 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1399
1400 I915_WRITE(pp_ctrl_reg, pp);
1401 POSTING_READ(pp_ctrl_reg);
1402 intel_dp->last_backlight_off = jiffies;
1403 }
1404
1405 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1406 {
1407 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1408 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1409 struct drm_device *dev = crtc->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411 u32 dpa_ctl;
1412
1413 assert_pipe_disabled(dev_priv,
1414 to_intel_crtc(crtc)->pipe);
1415
1416 DRM_DEBUG_KMS("\n");
1417 dpa_ctl = I915_READ(DP_A);
1418 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1419 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1420
1421 /* We don't adjust intel_dp->DP while tearing down the link, to
1422 * facilitate link retraining (e.g. after hotplug). Hence clear all
1423 * enable bits here to ensure that we don't enable too much. */
1424 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1425 intel_dp->DP |= DP_PLL_ENABLE;
1426 I915_WRITE(DP_A, intel_dp->DP);
1427 POSTING_READ(DP_A);
1428 udelay(200);
1429 }
1430
1431 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1432 {
1433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1434 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1435 struct drm_device *dev = crtc->dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 u32 dpa_ctl;
1438
1439 assert_pipe_disabled(dev_priv,
1440 to_intel_crtc(crtc)->pipe);
1441
1442 dpa_ctl = I915_READ(DP_A);
1443 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1444 "dp pll off, should be on\n");
1445 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1446
1447 /* We can't rely on the value tracked for the DP register in
1448 * intel_dp->DP because link_down must not change that (otherwise link
1449 * re-training will fail. */
1450 dpa_ctl &= ~DP_PLL_ENABLE;
1451 I915_WRITE(DP_A, dpa_ctl);
1452 POSTING_READ(DP_A);
1453 udelay(200);
1454 }
1455
1456 /* If the sink supports it, try to set the power state appropriately */
1457 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1458 {
1459 int ret, i;
1460
1461 /* Should have a valid DPCD by this point */
1462 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1463 return;
1464
1465 if (mode != DRM_MODE_DPMS_ON) {
1466 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1467 DP_SET_POWER_D3);
1468 if (ret != 1)
1469 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1470 } else {
1471 /*
1472 * When turning on, we need to retry for 1ms to give the sink
1473 * time to wake up.
1474 */
1475 for (i = 0; i < 3; i++) {
1476 ret = intel_dp_aux_native_write_1(intel_dp,
1477 DP_SET_POWER,
1478 DP_SET_POWER_D0);
1479 if (ret == 1)
1480 break;
1481 msleep(1);
1482 }
1483 }
1484 }
1485
1486 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1487 enum pipe *pipe)
1488 {
1489 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1490 enum port port = dp_to_dig_port(intel_dp)->port;
1491 struct drm_device *dev = encoder->base.dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 enum intel_display_power_domain power_domain;
1494 u32 tmp;
1495
1496 power_domain = intel_display_port_power_domain(encoder);
1497 if (!intel_display_power_enabled(dev_priv, power_domain))
1498 return false;
1499
1500 tmp = I915_READ(intel_dp->output_reg);
1501
1502 if (!(tmp & DP_PORT_EN))
1503 return false;
1504
1505 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1506 *pipe = PORT_TO_PIPE_CPT(tmp);
1507 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1508 *pipe = PORT_TO_PIPE(tmp);
1509 } else {
1510 u32 trans_sel;
1511 u32 trans_dp;
1512 int i;
1513
1514 switch (intel_dp->output_reg) {
1515 case PCH_DP_B:
1516 trans_sel = TRANS_DP_PORT_SEL_B;
1517 break;
1518 case PCH_DP_C:
1519 trans_sel = TRANS_DP_PORT_SEL_C;
1520 break;
1521 case PCH_DP_D:
1522 trans_sel = TRANS_DP_PORT_SEL_D;
1523 break;
1524 default:
1525 return true;
1526 }
1527
1528 for_each_pipe(i) {
1529 trans_dp = I915_READ(TRANS_DP_CTL(i));
1530 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1531 *pipe = i;
1532 return true;
1533 }
1534 }
1535
1536 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1537 intel_dp->output_reg);
1538 }
1539
1540 return true;
1541 }
1542
1543 static void intel_dp_get_config(struct intel_encoder *encoder,
1544 struct intel_crtc_config *pipe_config)
1545 {
1546 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1547 u32 tmp, flags = 0;
1548 struct drm_device *dev = encoder->base.dev;
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 enum port port = dp_to_dig_port(intel_dp)->port;
1551 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1552 int dotclock;
1553
1554 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1555 tmp = I915_READ(intel_dp->output_reg);
1556 if (tmp & DP_SYNC_HS_HIGH)
1557 flags |= DRM_MODE_FLAG_PHSYNC;
1558 else
1559 flags |= DRM_MODE_FLAG_NHSYNC;
1560
1561 if (tmp & DP_SYNC_VS_HIGH)
1562 flags |= DRM_MODE_FLAG_PVSYNC;
1563 else
1564 flags |= DRM_MODE_FLAG_NVSYNC;
1565 } else {
1566 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1567 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1568 flags |= DRM_MODE_FLAG_PHSYNC;
1569 else
1570 flags |= DRM_MODE_FLAG_NHSYNC;
1571
1572 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1573 flags |= DRM_MODE_FLAG_PVSYNC;
1574 else
1575 flags |= DRM_MODE_FLAG_NVSYNC;
1576 }
1577
1578 pipe_config->adjusted_mode.flags |= flags;
1579
1580 pipe_config->has_dp_encoder = true;
1581
1582 intel_dp_get_m_n(crtc, pipe_config);
1583
1584 if (port == PORT_A) {
1585 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1586 pipe_config->port_clock = 162000;
1587 else
1588 pipe_config->port_clock = 270000;
1589 }
1590
1591 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1592 &pipe_config->dp_m_n);
1593
1594 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1595 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1596
1597 pipe_config->adjusted_mode.crtc_clock = dotclock;
1598
1599 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1600 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1601 /*
1602 * This is a big fat ugly hack.
1603 *
1604 * Some machines in UEFI boot mode provide us a VBT that has 18
1605 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1606 * unknown we fail to light up. Yet the same BIOS boots up with
1607 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1608 * max, not what it tells us to use.
1609 *
1610 * Note: This will still be broken if the eDP panel is not lit
1611 * up by the BIOS, and thus we can't get the mode at module
1612 * load.
1613 */
1614 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1615 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1616 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1617 }
1618 }
1619
1620 static bool is_edp_psr(struct drm_device *dev)
1621 {
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623
1624 return dev_priv->psr.sink_support;
1625 }
1626
1627 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1628 {
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630
1631 if (!HAS_PSR(dev))
1632 return false;
1633
1634 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1635 }
1636
1637 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1638 struct edp_vsc_psr *vsc_psr)
1639 {
1640 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1641 struct drm_device *dev = dig_port->base.base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1644 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1645 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1646 uint32_t *data = (uint32_t *) vsc_psr;
1647 unsigned int i;
1648
1649 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1650 the video DIP being updated before program video DIP data buffer
1651 registers for DIP being updated. */
1652 I915_WRITE(ctl_reg, 0);
1653 POSTING_READ(ctl_reg);
1654
1655 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1656 if (i < sizeof(struct edp_vsc_psr))
1657 I915_WRITE(data_reg + i, *data++);
1658 else
1659 I915_WRITE(data_reg + i, 0);
1660 }
1661
1662 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1663 POSTING_READ(ctl_reg);
1664 }
1665
1666 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1667 {
1668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 struct edp_vsc_psr psr_vsc;
1671
1672 if (intel_dp->psr_setup_done)
1673 return;
1674
1675 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1676 memset(&psr_vsc, 0, sizeof(psr_vsc));
1677 psr_vsc.sdp_header.HB0 = 0;
1678 psr_vsc.sdp_header.HB1 = 0x7;
1679 psr_vsc.sdp_header.HB2 = 0x2;
1680 psr_vsc.sdp_header.HB3 = 0x8;
1681 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1682
1683 /* Avoid continuous PSR exit by masking memup and hpd */
1684 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1685 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1686
1687 intel_dp->psr_setup_done = true;
1688 }
1689
1690 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1691 {
1692 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 uint32_t aux_clock_divider;
1695 int precharge = 0x3;
1696 int msg_size = 5; /* Header(4) + Message(1) */
1697
1698 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1699
1700 /* Enable PSR in sink */
1701 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1702 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1703 DP_PSR_ENABLE &
1704 ~DP_PSR_MAIN_LINK_ACTIVE);
1705 else
1706 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1707 DP_PSR_ENABLE |
1708 DP_PSR_MAIN_LINK_ACTIVE);
1709
1710 /* Setup AUX registers */
1711 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1712 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1713 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1714 DP_AUX_CH_CTL_TIME_OUT_400us |
1715 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1716 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1717 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1718 }
1719
1720 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1721 {
1722 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724 uint32_t max_sleep_time = 0x1f;
1725 uint32_t idle_frames = 1;
1726 uint32_t val = 0x0;
1727 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1728
1729 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1730 val |= EDP_PSR_LINK_STANDBY;
1731 val |= EDP_PSR_TP2_TP3_TIME_0us;
1732 val |= EDP_PSR_TP1_TIME_0us;
1733 val |= EDP_PSR_SKIP_AUX_EXIT;
1734 } else
1735 val |= EDP_PSR_LINK_DISABLE;
1736
1737 I915_WRITE(EDP_PSR_CTL(dev), val |
1738 IS_BROADWELL(dev) ? 0 : link_entry_time |
1739 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1740 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1741 EDP_PSR_ENABLE);
1742 }
1743
1744 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1745 {
1746 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1747 struct drm_device *dev = dig_port->base.base.dev;
1748 struct drm_i915_private *dev_priv = dev->dev_private;
1749 struct drm_crtc *crtc = dig_port->base.base.crtc;
1750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1751 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1752 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1753
1754 dev_priv->psr.source_ok = false;
1755
1756 if (!HAS_PSR(dev)) {
1757 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1758 return false;
1759 }
1760
1761 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1762 (dig_port->port != PORT_A)) {
1763 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1764 return false;
1765 }
1766
1767 if (!i915.enable_psr) {
1768 DRM_DEBUG_KMS("PSR disable by flag\n");
1769 return false;
1770 }
1771
1772 crtc = dig_port->base.base.crtc;
1773 if (crtc == NULL) {
1774 DRM_DEBUG_KMS("crtc not active for PSR\n");
1775 return false;
1776 }
1777
1778 intel_crtc = to_intel_crtc(crtc);
1779 if (!intel_crtc_active(crtc)) {
1780 DRM_DEBUG_KMS("crtc not active for PSR\n");
1781 return false;
1782 }
1783
1784 obj = to_intel_framebuffer(crtc->fb)->obj;
1785 if (obj->tiling_mode != I915_TILING_X ||
1786 obj->fence_reg == I915_FENCE_REG_NONE) {
1787 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1788 return false;
1789 }
1790
1791 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1792 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1793 return false;
1794 }
1795
1796 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1797 S3D_ENABLE) {
1798 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1799 return false;
1800 }
1801
1802 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1803 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1804 return false;
1805 }
1806
1807 dev_priv->psr.source_ok = true;
1808 return true;
1809 }
1810
1811 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1812 {
1813 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1814
1815 if (!intel_edp_psr_match_conditions(intel_dp) ||
1816 intel_edp_is_psr_enabled(dev))
1817 return;
1818
1819 /* Setup PSR once */
1820 intel_edp_psr_setup(intel_dp);
1821
1822 /* Enable PSR on the panel */
1823 intel_edp_psr_enable_sink(intel_dp);
1824
1825 /* Enable PSR on the host */
1826 intel_edp_psr_enable_source(intel_dp);
1827 }
1828
1829 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1830 {
1831 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1832
1833 if (intel_edp_psr_match_conditions(intel_dp) &&
1834 !intel_edp_is_psr_enabled(dev))
1835 intel_edp_psr_do_enable(intel_dp);
1836 }
1837
1838 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1839 {
1840 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842
1843 if (!intel_edp_is_psr_enabled(dev))
1844 return;
1845
1846 I915_WRITE(EDP_PSR_CTL(dev),
1847 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1848
1849 /* Wait till PSR is idle */
1850 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1851 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1852 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1853 }
1854
1855 void intel_edp_psr_update(struct drm_device *dev)
1856 {
1857 struct intel_encoder *encoder;
1858 struct intel_dp *intel_dp = NULL;
1859
1860 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1861 if (encoder->type == INTEL_OUTPUT_EDP) {
1862 intel_dp = enc_to_intel_dp(&encoder->base);
1863
1864 if (!is_edp_psr(dev))
1865 return;
1866
1867 if (!intel_edp_psr_match_conditions(intel_dp))
1868 intel_edp_psr_disable(intel_dp);
1869 else
1870 if (!intel_edp_is_psr_enabled(dev))
1871 intel_edp_psr_do_enable(intel_dp);
1872 }
1873 }
1874
1875 static void intel_disable_dp(struct intel_encoder *encoder)
1876 {
1877 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1878 enum port port = dp_to_dig_port(intel_dp)->port;
1879 struct drm_device *dev = encoder->base.dev;
1880
1881 /* Make sure the panel is off before trying to change the mode. But also
1882 * ensure that we have vdd while we switch off the panel. */
1883 edp_panel_vdd_on(intel_dp);
1884 intel_edp_backlight_off(intel_dp);
1885 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1886 intel_edp_panel_off(intel_dp);
1887
1888 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1889 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1890 intel_dp_link_down(intel_dp);
1891 }
1892
1893 static void intel_post_disable_dp(struct intel_encoder *encoder)
1894 {
1895 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1896 enum port port = dp_to_dig_port(intel_dp)->port;
1897 struct drm_device *dev = encoder->base.dev;
1898
1899 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1900 intel_dp_link_down(intel_dp);
1901 if (!IS_VALLEYVIEW(dev))
1902 ironlake_edp_pll_off(intel_dp);
1903 }
1904 }
1905
1906 static void intel_enable_dp(struct intel_encoder *encoder)
1907 {
1908 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1909 struct drm_device *dev = encoder->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1912
1913 if (WARN_ON(dp_reg & DP_PORT_EN))
1914 return;
1915
1916 edp_panel_vdd_on(intel_dp);
1917 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1918 intel_dp_start_link_train(intel_dp);
1919 intel_edp_panel_on(intel_dp);
1920 edp_panel_vdd_off(intel_dp, true);
1921 intel_dp_complete_link_train(intel_dp);
1922 intel_dp_stop_link_train(intel_dp);
1923 }
1924
1925 static void g4x_enable_dp(struct intel_encoder *encoder)
1926 {
1927 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1928
1929 intel_enable_dp(encoder);
1930 intel_edp_backlight_on(intel_dp);
1931 }
1932
1933 static void vlv_enable_dp(struct intel_encoder *encoder)
1934 {
1935 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1936
1937 intel_edp_backlight_on(intel_dp);
1938 }
1939
1940 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1941 {
1942 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1943 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1944
1945 if (dport->port == PORT_A)
1946 ironlake_edp_pll_on(intel_dp);
1947 }
1948
1949 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1950 {
1951 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1952 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1953 struct drm_device *dev = encoder->base.dev;
1954 struct drm_i915_private *dev_priv = dev->dev_private;
1955 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1956 enum dpio_channel port = vlv_dport_to_channel(dport);
1957 int pipe = intel_crtc->pipe;
1958 struct edp_power_seq power_seq;
1959 u32 val;
1960
1961 mutex_lock(&dev_priv->dpio_lock);
1962
1963 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1964 val = 0;
1965 if (pipe)
1966 val |= (1<<21);
1967 else
1968 val &= ~(1<<21);
1969 val |= 0x001000c4;
1970 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1971 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1972 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1973
1974 mutex_unlock(&dev_priv->dpio_lock);
1975
1976 if (is_edp(intel_dp)) {
1977 /* init power sequencer on this pipe and port */
1978 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1979 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1980 &power_seq);
1981 }
1982
1983 intel_enable_dp(encoder);
1984
1985 vlv_wait_port_ready(dev_priv, dport);
1986 }
1987
1988 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1989 {
1990 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1991 struct drm_device *dev = encoder->base.dev;
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1993 struct intel_crtc *intel_crtc =
1994 to_intel_crtc(encoder->base.crtc);
1995 enum dpio_channel port = vlv_dport_to_channel(dport);
1996 int pipe = intel_crtc->pipe;
1997
1998 /* Program Tx lane resets to default */
1999 mutex_lock(&dev_priv->dpio_lock);
2000 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2001 DPIO_PCS_TX_LANE2_RESET |
2002 DPIO_PCS_TX_LANE1_RESET);
2003 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2004 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2005 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2006 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2007 DPIO_PCS_CLK_SOFT_RESET);
2008
2009 /* Fix up inter-pair skew failure */
2010 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2011 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2012 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2013 mutex_unlock(&dev_priv->dpio_lock);
2014 }
2015
2016 /*
2017 * Native read with retry for link status and receiver capability reads for
2018 * cases where the sink may still be asleep.
2019 */
2020 static bool
2021 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
2022 uint8_t *recv, int recv_bytes)
2023 {
2024 int ret, i;
2025
2026 /*
2027 * Sinks are *supposed* to come up within 1ms from an off state,
2028 * but we're also supposed to retry 3 times per the spec.
2029 */
2030 for (i = 0; i < 3; i++) {
2031 ret = intel_dp_aux_native_read(intel_dp, address, recv,
2032 recv_bytes);
2033 if (ret == recv_bytes)
2034 return true;
2035 msleep(1);
2036 }
2037
2038 return false;
2039 }
2040
2041 /*
2042 * Fetch AUX CH registers 0x202 - 0x207 which contain
2043 * link status information
2044 */
2045 static bool
2046 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2047 {
2048 return intel_dp_aux_native_read_retry(intel_dp,
2049 DP_LANE0_1_STATUS,
2050 link_status,
2051 DP_LINK_STATUS_SIZE);
2052 }
2053
2054 /*
2055 * These are source-specific values; current Intel hardware supports
2056 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2057 */
2058
2059 static uint8_t
2060 intel_dp_voltage_max(struct intel_dp *intel_dp)
2061 {
2062 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2063 enum port port = dp_to_dig_port(intel_dp)->port;
2064
2065 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
2066 return DP_TRAIN_VOLTAGE_SWING_1200;
2067 else if (IS_GEN7(dev) && port == PORT_A)
2068 return DP_TRAIN_VOLTAGE_SWING_800;
2069 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2070 return DP_TRAIN_VOLTAGE_SWING_1200;
2071 else
2072 return DP_TRAIN_VOLTAGE_SWING_800;
2073 }
2074
2075 static uint8_t
2076 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2077 {
2078 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2079 enum port port = dp_to_dig_port(intel_dp)->port;
2080
2081 if (IS_BROADWELL(dev)) {
2082 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2083 case DP_TRAIN_VOLTAGE_SWING_400:
2084 case DP_TRAIN_VOLTAGE_SWING_600:
2085 return DP_TRAIN_PRE_EMPHASIS_6;
2086 case DP_TRAIN_VOLTAGE_SWING_800:
2087 return DP_TRAIN_PRE_EMPHASIS_3_5;
2088 case DP_TRAIN_VOLTAGE_SWING_1200:
2089 default:
2090 return DP_TRAIN_PRE_EMPHASIS_0;
2091 }
2092 } else if (IS_HASWELL(dev)) {
2093 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2094 case DP_TRAIN_VOLTAGE_SWING_400:
2095 return DP_TRAIN_PRE_EMPHASIS_9_5;
2096 case DP_TRAIN_VOLTAGE_SWING_600:
2097 return DP_TRAIN_PRE_EMPHASIS_6;
2098 case DP_TRAIN_VOLTAGE_SWING_800:
2099 return DP_TRAIN_PRE_EMPHASIS_3_5;
2100 case DP_TRAIN_VOLTAGE_SWING_1200:
2101 default:
2102 return DP_TRAIN_PRE_EMPHASIS_0;
2103 }
2104 } else if (IS_VALLEYVIEW(dev)) {
2105 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2106 case DP_TRAIN_VOLTAGE_SWING_400:
2107 return DP_TRAIN_PRE_EMPHASIS_9_5;
2108 case DP_TRAIN_VOLTAGE_SWING_600:
2109 return DP_TRAIN_PRE_EMPHASIS_6;
2110 case DP_TRAIN_VOLTAGE_SWING_800:
2111 return DP_TRAIN_PRE_EMPHASIS_3_5;
2112 case DP_TRAIN_VOLTAGE_SWING_1200:
2113 default:
2114 return DP_TRAIN_PRE_EMPHASIS_0;
2115 }
2116 } else if (IS_GEN7(dev) && port == PORT_A) {
2117 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2118 case DP_TRAIN_VOLTAGE_SWING_400:
2119 return DP_TRAIN_PRE_EMPHASIS_6;
2120 case DP_TRAIN_VOLTAGE_SWING_600:
2121 case DP_TRAIN_VOLTAGE_SWING_800:
2122 return DP_TRAIN_PRE_EMPHASIS_3_5;
2123 default:
2124 return DP_TRAIN_PRE_EMPHASIS_0;
2125 }
2126 } else {
2127 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2128 case DP_TRAIN_VOLTAGE_SWING_400:
2129 return DP_TRAIN_PRE_EMPHASIS_6;
2130 case DP_TRAIN_VOLTAGE_SWING_600:
2131 return DP_TRAIN_PRE_EMPHASIS_6;
2132 case DP_TRAIN_VOLTAGE_SWING_800:
2133 return DP_TRAIN_PRE_EMPHASIS_3_5;
2134 case DP_TRAIN_VOLTAGE_SWING_1200:
2135 default:
2136 return DP_TRAIN_PRE_EMPHASIS_0;
2137 }
2138 }
2139 }
2140
2141 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2142 {
2143 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2146 struct intel_crtc *intel_crtc =
2147 to_intel_crtc(dport->base.base.crtc);
2148 unsigned long demph_reg_value, preemph_reg_value,
2149 uniqtranscale_reg_value;
2150 uint8_t train_set = intel_dp->train_set[0];
2151 enum dpio_channel port = vlv_dport_to_channel(dport);
2152 int pipe = intel_crtc->pipe;
2153
2154 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2155 case DP_TRAIN_PRE_EMPHASIS_0:
2156 preemph_reg_value = 0x0004000;
2157 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2158 case DP_TRAIN_VOLTAGE_SWING_400:
2159 demph_reg_value = 0x2B405555;
2160 uniqtranscale_reg_value = 0x552AB83A;
2161 break;
2162 case DP_TRAIN_VOLTAGE_SWING_600:
2163 demph_reg_value = 0x2B404040;
2164 uniqtranscale_reg_value = 0x5548B83A;
2165 break;
2166 case DP_TRAIN_VOLTAGE_SWING_800:
2167 demph_reg_value = 0x2B245555;
2168 uniqtranscale_reg_value = 0x5560B83A;
2169 break;
2170 case DP_TRAIN_VOLTAGE_SWING_1200:
2171 demph_reg_value = 0x2B405555;
2172 uniqtranscale_reg_value = 0x5598DA3A;
2173 break;
2174 default:
2175 return 0;
2176 }
2177 break;
2178 case DP_TRAIN_PRE_EMPHASIS_3_5:
2179 preemph_reg_value = 0x0002000;
2180 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2181 case DP_TRAIN_VOLTAGE_SWING_400:
2182 demph_reg_value = 0x2B404040;
2183 uniqtranscale_reg_value = 0x5552B83A;
2184 break;
2185 case DP_TRAIN_VOLTAGE_SWING_600:
2186 demph_reg_value = 0x2B404848;
2187 uniqtranscale_reg_value = 0x5580B83A;
2188 break;
2189 case DP_TRAIN_VOLTAGE_SWING_800:
2190 demph_reg_value = 0x2B404040;
2191 uniqtranscale_reg_value = 0x55ADDA3A;
2192 break;
2193 default:
2194 return 0;
2195 }
2196 break;
2197 case DP_TRAIN_PRE_EMPHASIS_6:
2198 preemph_reg_value = 0x0000000;
2199 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2200 case DP_TRAIN_VOLTAGE_SWING_400:
2201 demph_reg_value = 0x2B305555;
2202 uniqtranscale_reg_value = 0x5570B83A;
2203 break;
2204 case DP_TRAIN_VOLTAGE_SWING_600:
2205 demph_reg_value = 0x2B2B4040;
2206 uniqtranscale_reg_value = 0x55ADDA3A;
2207 break;
2208 default:
2209 return 0;
2210 }
2211 break;
2212 case DP_TRAIN_PRE_EMPHASIS_9_5:
2213 preemph_reg_value = 0x0006000;
2214 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2215 case DP_TRAIN_VOLTAGE_SWING_400:
2216 demph_reg_value = 0x1B405555;
2217 uniqtranscale_reg_value = 0x55ADDA3A;
2218 break;
2219 default:
2220 return 0;
2221 }
2222 break;
2223 default:
2224 return 0;
2225 }
2226
2227 mutex_lock(&dev_priv->dpio_lock);
2228 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2229 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2230 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2231 uniqtranscale_reg_value);
2232 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2233 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2234 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2235 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2236 mutex_unlock(&dev_priv->dpio_lock);
2237
2238 return 0;
2239 }
2240
2241 static void
2242 intel_get_adjust_train(struct intel_dp *intel_dp,
2243 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2244 {
2245 uint8_t v = 0;
2246 uint8_t p = 0;
2247 int lane;
2248 uint8_t voltage_max;
2249 uint8_t preemph_max;
2250
2251 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2252 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2253 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2254
2255 if (this_v > v)
2256 v = this_v;
2257 if (this_p > p)
2258 p = this_p;
2259 }
2260
2261 voltage_max = intel_dp_voltage_max(intel_dp);
2262 if (v >= voltage_max)
2263 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2264
2265 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2266 if (p >= preemph_max)
2267 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2268
2269 for (lane = 0; lane < 4; lane++)
2270 intel_dp->train_set[lane] = v | p;
2271 }
2272
2273 static uint32_t
2274 intel_gen4_signal_levels(uint8_t train_set)
2275 {
2276 uint32_t signal_levels = 0;
2277
2278 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2279 case DP_TRAIN_VOLTAGE_SWING_400:
2280 default:
2281 signal_levels |= DP_VOLTAGE_0_4;
2282 break;
2283 case DP_TRAIN_VOLTAGE_SWING_600:
2284 signal_levels |= DP_VOLTAGE_0_6;
2285 break;
2286 case DP_TRAIN_VOLTAGE_SWING_800:
2287 signal_levels |= DP_VOLTAGE_0_8;
2288 break;
2289 case DP_TRAIN_VOLTAGE_SWING_1200:
2290 signal_levels |= DP_VOLTAGE_1_2;
2291 break;
2292 }
2293 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2294 case DP_TRAIN_PRE_EMPHASIS_0:
2295 default:
2296 signal_levels |= DP_PRE_EMPHASIS_0;
2297 break;
2298 case DP_TRAIN_PRE_EMPHASIS_3_5:
2299 signal_levels |= DP_PRE_EMPHASIS_3_5;
2300 break;
2301 case DP_TRAIN_PRE_EMPHASIS_6:
2302 signal_levels |= DP_PRE_EMPHASIS_6;
2303 break;
2304 case DP_TRAIN_PRE_EMPHASIS_9_5:
2305 signal_levels |= DP_PRE_EMPHASIS_9_5;
2306 break;
2307 }
2308 return signal_levels;
2309 }
2310
2311 /* Gen6's DP voltage swing and pre-emphasis control */
2312 static uint32_t
2313 intel_gen6_edp_signal_levels(uint8_t train_set)
2314 {
2315 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2316 DP_TRAIN_PRE_EMPHASIS_MASK);
2317 switch (signal_levels) {
2318 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2319 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2320 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2321 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2322 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2323 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2324 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2325 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2326 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2327 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2328 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2329 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2330 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2331 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2332 default:
2333 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2334 "0x%x\n", signal_levels);
2335 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2336 }
2337 }
2338
2339 /* Gen7's DP voltage swing and pre-emphasis control */
2340 static uint32_t
2341 intel_gen7_edp_signal_levels(uint8_t train_set)
2342 {
2343 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2344 DP_TRAIN_PRE_EMPHASIS_MASK);
2345 switch (signal_levels) {
2346 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2347 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2348 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2349 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2350 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2351 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2352
2353 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2354 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2355 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2356 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2357
2358 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2359 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2360 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2361 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2362
2363 default:
2364 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2365 "0x%x\n", signal_levels);
2366 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2367 }
2368 }
2369
2370 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2371 static uint32_t
2372 intel_hsw_signal_levels(uint8_t train_set)
2373 {
2374 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2375 DP_TRAIN_PRE_EMPHASIS_MASK);
2376 switch (signal_levels) {
2377 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2378 return DDI_BUF_EMP_400MV_0DB_HSW;
2379 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2380 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2381 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2382 return DDI_BUF_EMP_400MV_6DB_HSW;
2383 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2384 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2385
2386 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2387 return DDI_BUF_EMP_600MV_0DB_HSW;
2388 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2389 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2390 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2391 return DDI_BUF_EMP_600MV_6DB_HSW;
2392
2393 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2394 return DDI_BUF_EMP_800MV_0DB_HSW;
2395 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2396 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2397 default:
2398 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2399 "0x%x\n", signal_levels);
2400 return DDI_BUF_EMP_400MV_0DB_HSW;
2401 }
2402 }
2403
2404 static uint32_t
2405 intel_bdw_signal_levels(uint8_t train_set)
2406 {
2407 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2408 DP_TRAIN_PRE_EMPHASIS_MASK);
2409 switch (signal_levels) {
2410 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2411 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2412 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2413 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2414 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2415 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2416
2417 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2418 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2419 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2420 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2421 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2422 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2423
2424 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2425 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2426 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2427 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2428
2429 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2430 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2431
2432 default:
2433 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2434 "0x%x\n", signal_levels);
2435 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2436 }
2437 }
2438
2439 /* Properly updates "DP" with the correct signal levels. */
2440 static void
2441 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2442 {
2443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2444 enum port port = intel_dig_port->port;
2445 struct drm_device *dev = intel_dig_port->base.base.dev;
2446 uint32_t signal_levels, mask;
2447 uint8_t train_set = intel_dp->train_set[0];
2448
2449 if (IS_BROADWELL(dev)) {
2450 signal_levels = intel_bdw_signal_levels(train_set);
2451 mask = DDI_BUF_EMP_MASK;
2452 } else if (IS_HASWELL(dev)) {
2453 signal_levels = intel_hsw_signal_levels(train_set);
2454 mask = DDI_BUF_EMP_MASK;
2455 } else if (IS_VALLEYVIEW(dev)) {
2456 signal_levels = intel_vlv_signal_levels(intel_dp);
2457 mask = 0;
2458 } else if (IS_GEN7(dev) && port == PORT_A) {
2459 signal_levels = intel_gen7_edp_signal_levels(train_set);
2460 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2461 } else if (IS_GEN6(dev) && port == PORT_A) {
2462 signal_levels = intel_gen6_edp_signal_levels(train_set);
2463 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2464 } else {
2465 signal_levels = intel_gen4_signal_levels(train_set);
2466 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2467 }
2468
2469 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2470
2471 *DP = (*DP & ~mask) | signal_levels;
2472 }
2473
2474 static bool
2475 intel_dp_set_link_train(struct intel_dp *intel_dp,
2476 uint32_t *DP,
2477 uint8_t dp_train_pat)
2478 {
2479 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2480 struct drm_device *dev = intel_dig_port->base.base.dev;
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482 enum port port = intel_dig_port->port;
2483 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2484 int ret, len;
2485
2486 if (HAS_DDI(dev)) {
2487 uint32_t temp = I915_READ(DP_TP_CTL(port));
2488
2489 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2490 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2491 else
2492 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2493
2494 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2495 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2496 case DP_TRAINING_PATTERN_DISABLE:
2497 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2498
2499 break;
2500 case DP_TRAINING_PATTERN_1:
2501 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2502 break;
2503 case DP_TRAINING_PATTERN_2:
2504 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2505 break;
2506 case DP_TRAINING_PATTERN_3:
2507 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2508 break;
2509 }
2510 I915_WRITE(DP_TP_CTL(port), temp);
2511
2512 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2513 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2514
2515 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2516 case DP_TRAINING_PATTERN_DISABLE:
2517 *DP |= DP_LINK_TRAIN_OFF_CPT;
2518 break;
2519 case DP_TRAINING_PATTERN_1:
2520 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2521 break;
2522 case DP_TRAINING_PATTERN_2:
2523 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2524 break;
2525 case DP_TRAINING_PATTERN_3:
2526 DRM_ERROR("DP training pattern 3 not supported\n");
2527 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2528 break;
2529 }
2530
2531 } else {
2532 *DP &= ~DP_LINK_TRAIN_MASK;
2533
2534 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2535 case DP_TRAINING_PATTERN_DISABLE:
2536 *DP |= DP_LINK_TRAIN_OFF;
2537 break;
2538 case DP_TRAINING_PATTERN_1:
2539 *DP |= DP_LINK_TRAIN_PAT_1;
2540 break;
2541 case DP_TRAINING_PATTERN_2:
2542 *DP |= DP_LINK_TRAIN_PAT_2;
2543 break;
2544 case DP_TRAINING_PATTERN_3:
2545 DRM_ERROR("DP training pattern 3 not supported\n");
2546 *DP |= DP_LINK_TRAIN_PAT_2;
2547 break;
2548 }
2549 }
2550
2551 I915_WRITE(intel_dp->output_reg, *DP);
2552 POSTING_READ(intel_dp->output_reg);
2553
2554 buf[0] = dp_train_pat;
2555 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2556 DP_TRAINING_PATTERN_DISABLE) {
2557 /* don't write DP_TRAINING_LANEx_SET on disable */
2558 len = 1;
2559 } else {
2560 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2561 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2562 len = intel_dp->lane_count + 1;
2563 }
2564
2565 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2566 buf, len);
2567
2568 return ret == len;
2569 }
2570
2571 static bool
2572 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2573 uint8_t dp_train_pat)
2574 {
2575 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2576 intel_dp_set_signal_levels(intel_dp, DP);
2577 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2578 }
2579
2580 static bool
2581 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2582 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2583 {
2584 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2585 struct drm_device *dev = intel_dig_port->base.base.dev;
2586 struct drm_i915_private *dev_priv = dev->dev_private;
2587 int ret;
2588
2589 intel_get_adjust_train(intel_dp, link_status);
2590 intel_dp_set_signal_levels(intel_dp, DP);
2591
2592 I915_WRITE(intel_dp->output_reg, *DP);
2593 POSTING_READ(intel_dp->output_reg);
2594
2595 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2596 intel_dp->train_set,
2597 intel_dp->lane_count);
2598
2599 return ret == intel_dp->lane_count;
2600 }
2601
2602 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2603 {
2604 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2605 struct drm_device *dev = intel_dig_port->base.base.dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 enum port port = intel_dig_port->port;
2608 uint32_t val;
2609
2610 if (!HAS_DDI(dev))
2611 return;
2612
2613 val = I915_READ(DP_TP_CTL(port));
2614 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2615 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2616 I915_WRITE(DP_TP_CTL(port), val);
2617
2618 /*
2619 * On PORT_A we can have only eDP in SST mode. There the only reason
2620 * we need to set idle transmission mode is to work around a HW issue
2621 * where we enable the pipe while not in idle link-training mode.
2622 * In this case there is requirement to wait for a minimum number of
2623 * idle patterns to be sent.
2624 */
2625 if (port == PORT_A)
2626 return;
2627
2628 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2629 1))
2630 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2631 }
2632
2633 /* Enable corresponding port and start training pattern 1 */
2634 void
2635 intel_dp_start_link_train(struct intel_dp *intel_dp)
2636 {
2637 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2638 struct drm_device *dev = encoder->dev;
2639 int i;
2640 uint8_t voltage;
2641 int voltage_tries, loop_tries;
2642 uint32_t DP = intel_dp->DP;
2643 uint8_t link_config[2];
2644
2645 if (HAS_DDI(dev))
2646 intel_ddi_prepare_link_retrain(encoder);
2647
2648 /* Write the link configuration data */
2649 link_config[0] = intel_dp->link_bw;
2650 link_config[1] = intel_dp->lane_count;
2651 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2652 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2653 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2654
2655 link_config[0] = 0;
2656 link_config[1] = DP_SET_ANSI_8B10B;
2657 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2658
2659 DP |= DP_PORT_EN;
2660
2661 /* clock recovery */
2662 if (!intel_dp_reset_link_train(intel_dp, &DP,
2663 DP_TRAINING_PATTERN_1 |
2664 DP_LINK_SCRAMBLING_DISABLE)) {
2665 DRM_ERROR("failed to enable link training\n");
2666 return;
2667 }
2668
2669 voltage = 0xff;
2670 voltage_tries = 0;
2671 loop_tries = 0;
2672 for (;;) {
2673 uint8_t link_status[DP_LINK_STATUS_SIZE];
2674
2675 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2676 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2677 DRM_ERROR("failed to get link status\n");
2678 break;
2679 }
2680
2681 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2682 DRM_DEBUG_KMS("clock recovery OK\n");
2683 break;
2684 }
2685
2686 /* Check to see if we've tried the max voltage */
2687 for (i = 0; i < intel_dp->lane_count; i++)
2688 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2689 break;
2690 if (i == intel_dp->lane_count) {
2691 ++loop_tries;
2692 if (loop_tries == 5) {
2693 DRM_ERROR("too many full retries, give up\n");
2694 break;
2695 }
2696 intel_dp_reset_link_train(intel_dp, &DP,
2697 DP_TRAINING_PATTERN_1 |
2698 DP_LINK_SCRAMBLING_DISABLE);
2699 voltage_tries = 0;
2700 continue;
2701 }
2702
2703 /* Check to see if we've tried the same voltage 5 times */
2704 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2705 ++voltage_tries;
2706 if (voltage_tries == 5) {
2707 DRM_ERROR("too many voltage retries, give up\n");
2708 break;
2709 }
2710 } else
2711 voltage_tries = 0;
2712 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2713
2714 /* Update training set as requested by target */
2715 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2716 DRM_ERROR("failed to update link training\n");
2717 break;
2718 }
2719 }
2720
2721 intel_dp->DP = DP;
2722 }
2723
2724 void
2725 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2726 {
2727 bool channel_eq = false;
2728 int tries, cr_tries;
2729 uint32_t DP = intel_dp->DP;
2730 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2731
2732 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2733 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2734 training_pattern = DP_TRAINING_PATTERN_3;
2735
2736 /* channel equalization */
2737 if (!intel_dp_set_link_train(intel_dp, &DP,
2738 training_pattern |
2739 DP_LINK_SCRAMBLING_DISABLE)) {
2740 DRM_ERROR("failed to start channel equalization\n");
2741 return;
2742 }
2743
2744 tries = 0;
2745 cr_tries = 0;
2746 channel_eq = false;
2747 for (;;) {
2748 uint8_t link_status[DP_LINK_STATUS_SIZE];
2749
2750 if (cr_tries > 5) {
2751 DRM_ERROR("failed to train DP, aborting\n");
2752 break;
2753 }
2754
2755 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2756 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2757 DRM_ERROR("failed to get link status\n");
2758 break;
2759 }
2760
2761 /* Make sure clock is still ok */
2762 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2763 intel_dp_start_link_train(intel_dp);
2764 intel_dp_set_link_train(intel_dp, &DP,
2765 training_pattern |
2766 DP_LINK_SCRAMBLING_DISABLE);
2767 cr_tries++;
2768 continue;
2769 }
2770
2771 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2772 channel_eq = true;
2773 break;
2774 }
2775
2776 /* Try 5 times, then try clock recovery if that fails */
2777 if (tries > 5) {
2778 intel_dp_link_down(intel_dp);
2779 intel_dp_start_link_train(intel_dp);
2780 intel_dp_set_link_train(intel_dp, &DP,
2781 training_pattern |
2782 DP_LINK_SCRAMBLING_DISABLE);
2783 tries = 0;
2784 cr_tries++;
2785 continue;
2786 }
2787
2788 /* Update training set as requested by target */
2789 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2790 DRM_ERROR("failed to update link training\n");
2791 break;
2792 }
2793 ++tries;
2794 }
2795
2796 intel_dp_set_idle_link_train(intel_dp);
2797
2798 intel_dp->DP = DP;
2799
2800 if (channel_eq)
2801 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2802
2803 }
2804
2805 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2806 {
2807 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2808 DP_TRAINING_PATTERN_DISABLE);
2809 }
2810
2811 static void
2812 intel_dp_link_down(struct intel_dp *intel_dp)
2813 {
2814 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2815 enum port port = intel_dig_port->port;
2816 struct drm_device *dev = intel_dig_port->base.base.dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc =
2819 to_intel_crtc(intel_dig_port->base.base.crtc);
2820 uint32_t DP = intel_dp->DP;
2821
2822 /*
2823 * DDI code has a strict mode set sequence and we should try to respect
2824 * it, otherwise we might hang the machine in many different ways. So we
2825 * really should be disabling the port only on a complete crtc_disable
2826 * sequence. This function is just called under two conditions on DDI
2827 * code:
2828 * - Link train failed while doing crtc_enable, and on this case we
2829 * really should respect the mode set sequence and wait for a
2830 * crtc_disable.
2831 * - Someone turned the monitor off and intel_dp_check_link_status
2832 * called us. We don't need to disable the whole port on this case, so
2833 * when someone turns the monitor on again,
2834 * intel_ddi_prepare_link_retrain will take care of redoing the link
2835 * train.
2836 */
2837 if (HAS_DDI(dev))
2838 return;
2839
2840 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2841 return;
2842
2843 DRM_DEBUG_KMS("\n");
2844
2845 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2846 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2847 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2848 } else {
2849 DP &= ~DP_LINK_TRAIN_MASK;
2850 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2851 }
2852 POSTING_READ(intel_dp->output_reg);
2853
2854 /* We don't really know why we're doing this */
2855 intel_wait_for_vblank(dev, intel_crtc->pipe);
2856
2857 if (HAS_PCH_IBX(dev) &&
2858 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2859 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2860
2861 /* Hardware workaround: leaving our transcoder select
2862 * set to transcoder B while it's off will prevent the
2863 * corresponding HDMI output on transcoder A.
2864 *
2865 * Combine this with another hardware workaround:
2866 * transcoder select bit can only be cleared while the
2867 * port is enabled.
2868 */
2869 DP &= ~DP_PIPEB_SELECT;
2870 I915_WRITE(intel_dp->output_reg, DP);
2871
2872 /* Changes to enable or select take place the vblank
2873 * after being written.
2874 */
2875 if (WARN_ON(crtc == NULL)) {
2876 /* We should never try to disable a port without a crtc
2877 * attached. For paranoia keep the code around for a
2878 * bit. */
2879 POSTING_READ(intel_dp->output_reg);
2880 msleep(50);
2881 } else
2882 intel_wait_for_vblank(dev, intel_crtc->pipe);
2883 }
2884
2885 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2886 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2887 POSTING_READ(intel_dp->output_reg);
2888 msleep(intel_dp->panel_power_down_delay);
2889 }
2890
2891 static bool
2892 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2893 {
2894 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2895 struct drm_device *dev = dig_port->base.base.dev;
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897
2898 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2899
2900 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2901 sizeof(intel_dp->dpcd)) == 0)
2902 return false; /* aux transfer failed */
2903
2904 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2905 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2906 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2907
2908 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2909 return false; /* DPCD not present */
2910
2911 /* Check if the panel supports PSR */
2912 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2913 if (is_edp(intel_dp)) {
2914 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2915 intel_dp->psr_dpcd,
2916 sizeof(intel_dp->psr_dpcd));
2917 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2918 dev_priv->psr.sink_support = true;
2919 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2920 }
2921 }
2922
2923 /* Training Pattern 3 support */
2924 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2925 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2926 intel_dp->use_tps3 = true;
2927 DRM_DEBUG_KMS("Displayport TPS3 supported");
2928 } else
2929 intel_dp->use_tps3 = false;
2930
2931 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2932 DP_DWN_STRM_PORT_PRESENT))
2933 return true; /* native DP sink */
2934
2935 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2936 return true; /* no per-port downstream info */
2937
2938 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2939 intel_dp->downstream_ports,
2940 DP_MAX_DOWNSTREAM_PORTS) == 0)
2941 return false; /* downstream port status fetch failed */
2942
2943 return true;
2944 }
2945
2946 static void
2947 intel_dp_probe_oui(struct intel_dp *intel_dp)
2948 {
2949 u8 buf[3];
2950
2951 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2952 return;
2953
2954 edp_panel_vdd_on(intel_dp);
2955
2956 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2957 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2958 buf[0], buf[1], buf[2]);
2959
2960 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2961 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2962 buf[0], buf[1], buf[2]);
2963
2964 edp_panel_vdd_off(intel_dp, false);
2965 }
2966
2967 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2968 {
2969 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2970 struct drm_device *dev = intel_dig_port->base.base.dev;
2971 struct intel_crtc *intel_crtc =
2972 to_intel_crtc(intel_dig_port->base.base.crtc);
2973 u8 buf[1];
2974
2975 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2976 return -EAGAIN;
2977
2978 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2979 return -ENOTTY;
2980
2981 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2982 DP_TEST_SINK_START))
2983 return -EAGAIN;
2984
2985 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2986 intel_wait_for_vblank(dev, intel_crtc->pipe);
2987 intel_wait_for_vblank(dev, intel_crtc->pipe);
2988
2989 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2990 return -EAGAIN;
2991
2992 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
2993 return 0;
2994 }
2995
2996 static bool
2997 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2998 {
2999 int ret;
3000
3001 ret = intel_dp_aux_native_read_retry(intel_dp,
3002 DP_DEVICE_SERVICE_IRQ_VECTOR,
3003 sink_irq_vector, 1);
3004 if (!ret)
3005 return false;
3006
3007 return true;
3008 }
3009
3010 static void
3011 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3012 {
3013 /* NAK by default */
3014 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
3015 }
3016
3017 /*
3018 * According to DP spec
3019 * 5.1.2:
3020 * 1. Read DPCD
3021 * 2. Configure link according to Receiver Capabilities
3022 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3023 * 4. Check link status on receipt of hot-plug interrupt
3024 */
3025
3026 void
3027 intel_dp_check_link_status(struct intel_dp *intel_dp)
3028 {
3029 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3030 u8 sink_irq_vector;
3031 u8 link_status[DP_LINK_STATUS_SIZE];
3032
3033 if (!intel_encoder->connectors_active)
3034 return;
3035
3036 if (WARN_ON(!intel_encoder->base.crtc))
3037 return;
3038
3039 /* Try to read receiver status if the link appears to be up */
3040 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3041 return;
3042 }
3043
3044 /* Now read the DPCD to see if it's actually running */
3045 if (!intel_dp_get_dpcd(intel_dp)) {
3046 return;
3047 }
3048
3049 /* Try to read the source of the interrupt */
3050 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3051 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3052 /* Clear interrupt source */
3053 intel_dp_aux_native_write_1(intel_dp,
3054 DP_DEVICE_SERVICE_IRQ_VECTOR,
3055 sink_irq_vector);
3056
3057 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3058 intel_dp_handle_test_request(intel_dp);
3059 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3060 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3061 }
3062
3063 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3064 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3065 drm_get_encoder_name(&intel_encoder->base));
3066 intel_dp_start_link_train(intel_dp);
3067 intel_dp_complete_link_train(intel_dp);
3068 intel_dp_stop_link_train(intel_dp);
3069 }
3070 }
3071
3072 /* XXX this is probably wrong for multiple downstream ports */
3073 static enum drm_connector_status
3074 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3075 {
3076 uint8_t *dpcd = intel_dp->dpcd;
3077 uint8_t type;
3078
3079 if (!intel_dp_get_dpcd(intel_dp))
3080 return connector_status_disconnected;
3081
3082 /* if there's no downstream port, we're done */
3083 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3084 return connector_status_connected;
3085
3086 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3087 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3088 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3089 uint8_t reg;
3090 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
3091 &reg, 1))
3092 return connector_status_unknown;
3093 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3094 : connector_status_disconnected;
3095 }
3096
3097 /* If no HPD, poke DDC gently */
3098 if (drm_probe_ddc(&intel_dp->adapter))
3099 return connector_status_connected;
3100
3101 /* Well we tried, say unknown for unreliable port types */
3102 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3103 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3104 if (type == DP_DS_PORT_TYPE_VGA ||
3105 type == DP_DS_PORT_TYPE_NON_EDID)
3106 return connector_status_unknown;
3107 } else {
3108 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3109 DP_DWN_STRM_PORT_TYPE_MASK;
3110 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3111 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3112 return connector_status_unknown;
3113 }
3114
3115 /* Anything else is out of spec, warn and ignore */
3116 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3117 return connector_status_disconnected;
3118 }
3119
3120 static enum drm_connector_status
3121 ironlake_dp_detect(struct intel_dp *intel_dp)
3122 {
3123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3124 struct drm_i915_private *dev_priv = dev->dev_private;
3125 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3126 enum drm_connector_status status;
3127
3128 /* Can't disconnect eDP, but you can close the lid... */
3129 if (is_edp(intel_dp)) {
3130 status = intel_panel_detect(dev);
3131 if (status == connector_status_unknown)
3132 status = connector_status_connected;
3133 return status;
3134 }
3135
3136 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3137 return connector_status_disconnected;
3138
3139 return intel_dp_detect_dpcd(intel_dp);
3140 }
3141
3142 static enum drm_connector_status
3143 g4x_dp_detect(struct intel_dp *intel_dp)
3144 {
3145 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3148 uint32_t bit;
3149
3150 /* Can't disconnect eDP, but you can close the lid... */
3151 if (is_edp(intel_dp)) {
3152 enum drm_connector_status status;
3153
3154 status = intel_panel_detect(dev);
3155 if (status == connector_status_unknown)
3156 status = connector_status_connected;
3157 return status;
3158 }
3159
3160 if (IS_VALLEYVIEW(dev)) {
3161 switch (intel_dig_port->port) {
3162 case PORT_B:
3163 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3164 break;
3165 case PORT_C:
3166 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3167 break;
3168 case PORT_D:
3169 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3170 break;
3171 default:
3172 return connector_status_unknown;
3173 }
3174 } else {
3175 switch (intel_dig_port->port) {
3176 case PORT_B:
3177 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3178 break;
3179 case PORT_C:
3180 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3181 break;
3182 case PORT_D:
3183 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3184 break;
3185 default:
3186 return connector_status_unknown;
3187 }
3188 }
3189
3190 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3191 return connector_status_disconnected;
3192
3193 return intel_dp_detect_dpcd(intel_dp);
3194 }
3195
3196 static struct edid *
3197 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3198 {
3199 struct intel_connector *intel_connector = to_intel_connector(connector);
3200
3201 /* use cached edid if we have one */
3202 if (intel_connector->edid) {
3203 /* invalid edid */
3204 if (IS_ERR(intel_connector->edid))
3205 return NULL;
3206
3207 return drm_edid_duplicate(intel_connector->edid);
3208 }
3209
3210 return drm_get_edid(connector, adapter);
3211 }
3212
3213 static int
3214 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3215 {
3216 struct intel_connector *intel_connector = to_intel_connector(connector);
3217
3218 /* use cached edid if we have one */
3219 if (intel_connector->edid) {
3220 /* invalid edid */
3221 if (IS_ERR(intel_connector->edid))
3222 return 0;
3223
3224 return intel_connector_update_modes(connector,
3225 intel_connector->edid);
3226 }
3227
3228 return intel_ddc_get_modes(connector, adapter);
3229 }
3230
3231 static enum drm_connector_status
3232 intel_dp_detect(struct drm_connector *connector, bool force)
3233 {
3234 struct intel_dp *intel_dp = intel_attached_dp(connector);
3235 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3236 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3237 struct drm_device *dev = connector->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 enum drm_connector_status status;
3240 enum intel_display_power_domain power_domain;
3241 struct edid *edid = NULL;
3242
3243 intel_runtime_pm_get(dev_priv);
3244
3245 power_domain = intel_display_port_power_domain(intel_encoder);
3246 intel_display_power_get(dev_priv, power_domain);
3247
3248 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3249 connector->base.id, drm_get_connector_name(connector));
3250
3251 intel_dp->has_audio = false;
3252
3253 if (HAS_PCH_SPLIT(dev))
3254 status = ironlake_dp_detect(intel_dp);
3255 else
3256 status = g4x_dp_detect(intel_dp);
3257
3258 if (status != connector_status_connected)
3259 goto out;
3260
3261 intel_dp_probe_oui(intel_dp);
3262
3263 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3264 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3265 } else {
3266 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3267 if (edid) {
3268 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3269 kfree(edid);
3270 }
3271 }
3272
3273 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3274 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3275 status = connector_status_connected;
3276
3277 out:
3278 intel_display_power_put(dev_priv, power_domain);
3279
3280 intel_runtime_pm_put(dev_priv);
3281
3282 return status;
3283 }
3284
3285 static int intel_dp_get_modes(struct drm_connector *connector)
3286 {
3287 struct intel_dp *intel_dp = intel_attached_dp(connector);
3288 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3289 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3290 struct intel_connector *intel_connector = to_intel_connector(connector);
3291 struct drm_device *dev = connector->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 enum intel_display_power_domain power_domain;
3294 int ret;
3295
3296 /* We should parse the EDID data and find out if it has an audio sink
3297 */
3298
3299 power_domain = intel_display_port_power_domain(intel_encoder);
3300 intel_display_power_get(dev_priv, power_domain);
3301
3302 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3303 intel_display_power_put(dev_priv, power_domain);
3304 if (ret)
3305 return ret;
3306
3307 /* if eDP has no EDID, fall back to fixed mode */
3308 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3309 struct drm_display_mode *mode;
3310 mode = drm_mode_duplicate(dev,
3311 intel_connector->panel.fixed_mode);
3312 if (mode) {
3313 drm_mode_probed_add(connector, mode);
3314 return 1;
3315 }
3316 }
3317 return 0;
3318 }
3319
3320 static bool
3321 intel_dp_detect_audio(struct drm_connector *connector)
3322 {
3323 struct intel_dp *intel_dp = intel_attached_dp(connector);
3324 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3325 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3326 struct drm_device *dev = connector->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 enum intel_display_power_domain power_domain;
3329 struct edid *edid;
3330 bool has_audio = false;
3331
3332 power_domain = intel_display_port_power_domain(intel_encoder);
3333 intel_display_power_get(dev_priv, power_domain);
3334
3335 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3336 if (edid) {
3337 has_audio = drm_detect_monitor_audio(edid);
3338 kfree(edid);
3339 }
3340
3341 intel_display_power_put(dev_priv, power_domain);
3342
3343 return has_audio;
3344 }
3345
3346 static int
3347 intel_dp_set_property(struct drm_connector *connector,
3348 struct drm_property *property,
3349 uint64_t val)
3350 {
3351 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3352 struct intel_connector *intel_connector = to_intel_connector(connector);
3353 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3354 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3355 int ret;
3356
3357 ret = drm_object_property_set_value(&connector->base, property, val);
3358 if (ret)
3359 return ret;
3360
3361 if (property == dev_priv->force_audio_property) {
3362 int i = val;
3363 bool has_audio;
3364
3365 if (i == intel_dp->force_audio)
3366 return 0;
3367
3368 intel_dp->force_audio = i;
3369
3370 if (i == HDMI_AUDIO_AUTO)
3371 has_audio = intel_dp_detect_audio(connector);
3372 else
3373 has_audio = (i == HDMI_AUDIO_ON);
3374
3375 if (has_audio == intel_dp->has_audio)
3376 return 0;
3377
3378 intel_dp->has_audio = has_audio;
3379 goto done;
3380 }
3381
3382 if (property == dev_priv->broadcast_rgb_property) {
3383 bool old_auto = intel_dp->color_range_auto;
3384 uint32_t old_range = intel_dp->color_range;
3385
3386 switch (val) {
3387 case INTEL_BROADCAST_RGB_AUTO:
3388 intel_dp->color_range_auto = true;
3389 break;
3390 case INTEL_BROADCAST_RGB_FULL:
3391 intel_dp->color_range_auto = false;
3392 intel_dp->color_range = 0;
3393 break;
3394 case INTEL_BROADCAST_RGB_LIMITED:
3395 intel_dp->color_range_auto = false;
3396 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3397 break;
3398 default:
3399 return -EINVAL;
3400 }
3401
3402 if (old_auto == intel_dp->color_range_auto &&
3403 old_range == intel_dp->color_range)
3404 return 0;
3405
3406 goto done;
3407 }
3408
3409 if (is_edp(intel_dp) &&
3410 property == connector->dev->mode_config.scaling_mode_property) {
3411 if (val == DRM_MODE_SCALE_NONE) {
3412 DRM_DEBUG_KMS("no scaling not supported\n");
3413 return -EINVAL;
3414 }
3415
3416 if (intel_connector->panel.fitting_mode == val) {
3417 /* the eDP scaling property is not changed */
3418 return 0;
3419 }
3420 intel_connector->panel.fitting_mode = val;
3421
3422 goto done;
3423 }
3424
3425 return -EINVAL;
3426
3427 done:
3428 if (intel_encoder->base.crtc)
3429 intel_crtc_restore_mode(intel_encoder->base.crtc);
3430
3431 return 0;
3432 }
3433
3434 static void
3435 intel_dp_connector_destroy(struct drm_connector *connector)
3436 {
3437 struct intel_connector *intel_connector = to_intel_connector(connector);
3438
3439 if (!IS_ERR_OR_NULL(intel_connector->edid))
3440 kfree(intel_connector->edid);
3441
3442 /* Can't call is_edp() since the encoder may have been destroyed
3443 * already. */
3444 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3445 intel_panel_fini(&intel_connector->panel);
3446
3447 drm_connector_cleanup(connector);
3448 kfree(connector);
3449 }
3450
3451 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3452 {
3453 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3454 struct intel_dp *intel_dp = &intel_dig_port->dp;
3455 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3456
3457 i2c_del_adapter(&intel_dp->adapter);
3458 drm_encoder_cleanup(encoder);
3459 if (is_edp(intel_dp)) {
3460 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3461 mutex_lock(&dev->mode_config.mutex);
3462 edp_panel_vdd_off_sync(intel_dp);
3463 mutex_unlock(&dev->mode_config.mutex);
3464 }
3465 kfree(intel_dig_port);
3466 }
3467
3468 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3469 .dpms = intel_connector_dpms,
3470 .detect = intel_dp_detect,
3471 .fill_modes = drm_helper_probe_single_connector_modes,
3472 .set_property = intel_dp_set_property,
3473 .destroy = intel_dp_connector_destroy,
3474 };
3475
3476 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3477 .get_modes = intel_dp_get_modes,
3478 .mode_valid = intel_dp_mode_valid,
3479 .best_encoder = intel_best_encoder,
3480 };
3481
3482 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3483 .destroy = intel_dp_encoder_destroy,
3484 };
3485
3486 static void
3487 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3488 {
3489 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3490
3491 intel_dp_check_link_status(intel_dp);
3492 }
3493
3494 /* Return which DP Port should be selected for Transcoder DP control */
3495 int
3496 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3497 {
3498 struct drm_device *dev = crtc->dev;
3499 struct intel_encoder *intel_encoder;
3500 struct intel_dp *intel_dp;
3501
3502 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3503 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3504
3505 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3506 intel_encoder->type == INTEL_OUTPUT_EDP)
3507 return intel_dp->output_reg;
3508 }
3509
3510 return -1;
3511 }
3512
3513 /* check the VBT to see whether the eDP is on DP-D port */
3514 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3515 {
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517 union child_device_config *p_child;
3518 int i;
3519 static const short port_mapping[] = {
3520 [PORT_B] = PORT_IDPB,
3521 [PORT_C] = PORT_IDPC,
3522 [PORT_D] = PORT_IDPD,
3523 };
3524
3525 if (port == PORT_A)
3526 return true;
3527
3528 if (!dev_priv->vbt.child_dev_num)
3529 return false;
3530
3531 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3532 p_child = dev_priv->vbt.child_dev + i;
3533
3534 if (p_child->common.dvo_port == port_mapping[port] &&
3535 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3536 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3537 return true;
3538 }
3539 return false;
3540 }
3541
3542 static void
3543 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3544 {
3545 struct intel_connector *intel_connector = to_intel_connector(connector);
3546
3547 intel_attach_force_audio_property(connector);
3548 intel_attach_broadcast_rgb_property(connector);
3549 intel_dp->color_range_auto = true;
3550
3551 if (is_edp(intel_dp)) {
3552 drm_mode_create_scaling_mode_property(connector->dev);
3553 drm_object_attach_property(
3554 &connector->base,
3555 connector->dev->mode_config.scaling_mode_property,
3556 DRM_MODE_SCALE_ASPECT);
3557 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3558 }
3559 }
3560
3561 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3562 {
3563 intel_dp->last_power_cycle = jiffies;
3564 intel_dp->last_power_on = jiffies;
3565 intel_dp->last_backlight_off = jiffies;
3566 }
3567
3568 static void
3569 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3570 struct intel_dp *intel_dp,
3571 struct edp_power_seq *out)
3572 {
3573 struct drm_i915_private *dev_priv = dev->dev_private;
3574 struct edp_power_seq cur, vbt, spec, final;
3575 u32 pp_on, pp_off, pp_div, pp;
3576 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3577
3578 if (HAS_PCH_SPLIT(dev)) {
3579 pp_ctrl_reg = PCH_PP_CONTROL;
3580 pp_on_reg = PCH_PP_ON_DELAYS;
3581 pp_off_reg = PCH_PP_OFF_DELAYS;
3582 pp_div_reg = PCH_PP_DIVISOR;
3583 } else {
3584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3585
3586 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3587 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3588 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3589 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3590 }
3591
3592 /* Workaround: Need to write PP_CONTROL with the unlock key as
3593 * the very first thing. */
3594 pp = ironlake_get_pp_control(intel_dp);
3595 I915_WRITE(pp_ctrl_reg, pp);
3596
3597 pp_on = I915_READ(pp_on_reg);
3598 pp_off = I915_READ(pp_off_reg);
3599 pp_div = I915_READ(pp_div_reg);
3600
3601 /* Pull timing values out of registers */
3602 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3603 PANEL_POWER_UP_DELAY_SHIFT;
3604
3605 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3606 PANEL_LIGHT_ON_DELAY_SHIFT;
3607
3608 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3609 PANEL_LIGHT_OFF_DELAY_SHIFT;
3610
3611 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3612 PANEL_POWER_DOWN_DELAY_SHIFT;
3613
3614 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3615 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3616
3617 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3618 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3619
3620 vbt = dev_priv->vbt.edp_pps;
3621
3622 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3623 * our hw here, which are all in 100usec. */
3624 spec.t1_t3 = 210 * 10;
3625 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3626 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3627 spec.t10 = 500 * 10;
3628 /* This one is special and actually in units of 100ms, but zero
3629 * based in the hw (so we need to add 100 ms). But the sw vbt
3630 * table multiplies it with 1000 to make it in units of 100usec,
3631 * too. */
3632 spec.t11_t12 = (510 + 100) * 10;
3633
3634 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3635 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3636
3637 /* Use the max of the register settings and vbt. If both are
3638 * unset, fall back to the spec limits. */
3639 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3640 spec.field : \
3641 max(cur.field, vbt.field))
3642 assign_final(t1_t3);
3643 assign_final(t8);
3644 assign_final(t9);
3645 assign_final(t10);
3646 assign_final(t11_t12);
3647 #undef assign_final
3648
3649 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3650 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3651 intel_dp->backlight_on_delay = get_delay(t8);
3652 intel_dp->backlight_off_delay = get_delay(t9);
3653 intel_dp->panel_power_down_delay = get_delay(t10);
3654 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3655 #undef get_delay
3656
3657 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3658 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3659 intel_dp->panel_power_cycle_delay);
3660
3661 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3662 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3663
3664 if (out)
3665 *out = final;
3666 }
3667
3668 static void
3669 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3670 struct intel_dp *intel_dp,
3671 struct edp_power_seq *seq)
3672 {
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 u32 pp_on, pp_off, pp_div, port_sel = 0;
3675 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3676 int pp_on_reg, pp_off_reg, pp_div_reg;
3677
3678 if (HAS_PCH_SPLIT(dev)) {
3679 pp_on_reg = PCH_PP_ON_DELAYS;
3680 pp_off_reg = PCH_PP_OFF_DELAYS;
3681 pp_div_reg = PCH_PP_DIVISOR;
3682 } else {
3683 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3684
3685 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3686 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3687 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3688 }
3689
3690 /*
3691 * And finally store the new values in the power sequencer. The
3692 * backlight delays are set to 1 because we do manual waits on them. For
3693 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3694 * we'll end up waiting for the backlight off delay twice: once when we
3695 * do the manual sleep, and once when we disable the panel and wait for
3696 * the PP_STATUS bit to become zero.
3697 */
3698 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3699 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3700 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3701 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3702 /* Compute the divisor for the pp clock, simply match the Bspec
3703 * formula. */
3704 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3705 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3706 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3707
3708 /* Haswell doesn't have any port selection bits for the panel
3709 * power sequencer any more. */
3710 if (IS_VALLEYVIEW(dev)) {
3711 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3712 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3713 else
3714 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3715 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3716 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3717 port_sel = PANEL_PORT_SELECT_DPA;
3718 else
3719 port_sel = PANEL_PORT_SELECT_DPD;
3720 }
3721
3722 pp_on |= port_sel;
3723
3724 I915_WRITE(pp_on_reg, pp_on);
3725 I915_WRITE(pp_off_reg, pp_off);
3726 I915_WRITE(pp_div_reg, pp_div);
3727
3728 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3729 I915_READ(pp_on_reg),
3730 I915_READ(pp_off_reg),
3731 I915_READ(pp_div_reg));
3732 }
3733
3734 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3735 struct intel_connector *intel_connector,
3736 struct edp_power_seq *power_seq)
3737 {
3738 struct drm_connector *connector = &intel_connector->base;
3739 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3740 struct drm_device *dev = intel_dig_port->base.base.dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct drm_display_mode *fixed_mode = NULL;
3743 bool has_dpcd;
3744 struct drm_display_mode *scan;
3745 struct edid *edid;
3746
3747 if (!is_edp(intel_dp))
3748 return true;
3749
3750 /* Cache DPCD and EDID for edp. */
3751 edp_panel_vdd_on(intel_dp);
3752 has_dpcd = intel_dp_get_dpcd(intel_dp);
3753 edp_panel_vdd_off(intel_dp, false);
3754
3755 if (has_dpcd) {
3756 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3757 dev_priv->no_aux_handshake =
3758 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3759 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3760 } else {
3761 /* if this fails, presume the device is a ghost */
3762 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3763 return false;
3764 }
3765
3766 /* We now know it's not a ghost, init power sequence regs. */
3767 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3768
3769 edid = drm_get_edid(connector, &intel_dp->adapter);
3770 if (edid) {
3771 if (drm_add_edid_modes(connector, edid)) {
3772 drm_mode_connector_update_edid_property(connector,
3773 edid);
3774 drm_edid_to_eld(connector, edid);
3775 } else {
3776 kfree(edid);
3777 edid = ERR_PTR(-EINVAL);
3778 }
3779 } else {
3780 edid = ERR_PTR(-ENOENT);
3781 }
3782 intel_connector->edid = edid;
3783
3784 /* prefer fixed mode from EDID if available */
3785 list_for_each_entry(scan, &connector->probed_modes, head) {
3786 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3787 fixed_mode = drm_mode_duplicate(dev, scan);
3788 break;
3789 }
3790 }
3791
3792 /* fallback to VBT if available for eDP */
3793 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3794 fixed_mode = drm_mode_duplicate(dev,
3795 dev_priv->vbt.lfp_lvds_vbt_mode);
3796 if (fixed_mode)
3797 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3798 }
3799
3800 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3801 intel_panel_setup_backlight(connector);
3802
3803 return true;
3804 }
3805
3806 bool
3807 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3808 struct intel_connector *intel_connector)
3809 {
3810 struct drm_connector *connector = &intel_connector->base;
3811 struct intel_dp *intel_dp = &intel_dig_port->dp;
3812 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3813 struct drm_device *dev = intel_encoder->base.dev;
3814 struct drm_i915_private *dev_priv = dev->dev_private;
3815 enum port port = intel_dig_port->port;
3816 struct edp_power_seq power_seq = { 0 };
3817 const char *name = NULL;
3818 int type, error;
3819
3820 /* intel_dp vfuncs */
3821 if (IS_VALLEYVIEW(dev))
3822 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3823 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3824 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3825 else if (HAS_PCH_SPLIT(dev))
3826 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3827 else
3828 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3829
3830 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3831
3832 /* Preserve the current hw state. */
3833 intel_dp->DP = I915_READ(intel_dp->output_reg);
3834 intel_dp->attached_connector = intel_connector;
3835
3836 if (intel_dp_is_edp(dev, port))
3837 type = DRM_MODE_CONNECTOR_eDP;
3838 else
3839 type = DRM_MODE_CONNECTOR_DisplayPort;
3840
3841 /*
3842 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3843 * for DP the encoder type can be set by the caller to
3844 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3845 */
3846 if (type == DRM_MODE_CONNECTOR_eDP)
3847 intel_encoder->type = INTEL_OUTPUT_EDP;
3848
3849 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3850 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3851 port_name(port));
3852
3853 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3854 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3855
3856 connector->interlace_allowed = true;
3857 connector->doublescan_allowed = 0;
3858
3859 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3860 edp_panel_vdd_work);
3861
3862 intel_connector_attach_encoder(intel_connector, intel_encoder);
3863 drm_sysfs_connector_add(connector);
3864
3865 if (HAS_DDI(dev))
3866 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3867 else
3868 intel_connector->get_hw_state = intel_connector_get_hw_state;
3869 intel_connector->unregister = intel_dp_connector_unregister;
3870
3871 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3872 if (HAS_DDI(dev)) {
3873 switch (intel_dig_port->port) {
3874 case PORT_A:
3875 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3876 break;
3877 case PORT_B:
3878 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3879 break;
3880 case PORT_C:
3881 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3882 break;
3883 case PORT_D:
3884 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3885 break;
3886 default:
3887 BUG();
3888 }
3889 }
3890
3891 /* Set up the DDC bus. */
3892 switch (port) {
3893 case PORT_A:
3894 intel_encoder->hpd_pin = HPD_PORT_A;
3895 name = "DPDDC-A";
3896 break;
3897 case PORT_B:
3898 intel_encoder->hpd_pin = HPD_PORT_B;
3899 name = "DPDDC-B";
3900 break;
3901 case PORT_C:
3902 intel_encoder->hpd_pin = HPD_PORT_C;
3903 name = "DPDDC-C";
3904 break;
3905 case PORT_D:
3906 intel_encoder->hpd_pin = HPD_PORT_D;
3907 name = "DPDDC-D";
3908 break;
3909 default:
3910 BUG();
3911 }
3912
3913 if (is_edp(intel_dp)) {
3914 intel_dp_init_panel_power_timestamps(intel_dp);
3915 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3916 }
3917
3918 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3919 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3920 error, port_name(port));
3921
3922 intel_dp->psr_setup_done = false;
3923
3924 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3925 i2c_del_adapter(&intel_dp->adapter);
3926 if (is_edp(intel_dp)) {
3927 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3928 mutex_lock(&dev->mode_config.mutex);
3929 edp_panel_vdd_off_sync(intel_dp);
3930 mutex_unlock(&dev->mode_config.mutex);
3931 }
3932 drm_sysfs_connector_remove(connector);
3933 drm_connector_cleanup(connector);
3934 return false;
3935 }
3936
3937 intel_dp_add_properties(intel_dp, connector);
3938
3939 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3940 * 0xd. Failure to do so will result in spurious interrupts being
3941 * generated on the port when a cable is not attached.
3942 */
3943 if (IS_G4X(dev) && !IS_GM45(dev)) {
3944 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3945 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3946 }
3947
3948 return true;
3949 }
3950
3951 void
3952 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3953 {
3954 struct intel_digital_port *intel_dig_port;
3955 struct intel_encoder *intel_encoder;
3956 struct drm_encoder *encoder;
3957 struct intel_connector *intel_connector;
3958
3959 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3960 if (!intel_dig_port)
3961 return;
3962
3963 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3964 if (!intel_connector) {
3965 kfree(intel_dig_port);
3966 return;
3967 }
3968
3969 intel_encoder = &intel_dig_port->base;
3970 encoder = &intel_encoder->base;
3971
3972 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3973 DRM_MODE_ENCODER_TMDS);
3974
3975 intel_encoder->compute_config = intel_dp_compute_config;
3976 intel_encoder->mode_set = intel_dp_mode_set;
3977 intel_encoder->disable = intel_disable_dp;
3978 intel_encoder->post_disable = intel_post_disable_dp;
3979 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3980 intel_encoder->get_config = intel_dp_get_config;
3981 if (IS_VALLEYVIEW(dev)) {
3982 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3983 intel_encoder->pre_enable = vlv_pre_enable_dp;
3984 intel_encoder->enable = vlv_enable_dp;
3985 } else {
3986 intel_encoder->pre_enable = g4x_pre_enable_dp;
3987 intel_encoder->enable = g4x_enable_dp;
3988 }
3989
3990 intel_dig_port->port = port;
3991 intel_dig_port->dp.output_reg = output_reg;
3992
3993 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3994 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3995 intel_encoder->cloneable = 0;
3996 intel_encoder->hot_plug = intel_dp_hot_plug;
3997
3998 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3999 drm_encoder_cleanup(encoder);
4000 kfree(intel_dig_port);
4001 kfree(intel_connector);
4002 }
4003 }
Linux kernel - Deliverables
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