2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll
[] = {
48 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
50 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
53 static const struct dp_link_dpll pch_dpll
[] = {
55 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
57 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
60 static const struct dp_link_dpll vlv_dpll
[] = {
62 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 5, .m2
= 3 } },
64 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp
*intel_dp
)
76 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
78 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
81 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
83 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
85 return intel_dig_port
->base
.base
.dev
;
88 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
90 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
93 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
96 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
98 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
100 switch (max_link_bw
) {
101 case DP_LINK_BW_1_62
:
104 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw
= DP_LINK_BW_2_7
;
108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
110 max_link_bw
= DP_LINK_BW_1_62
;
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
122 * 270000 * 1 * 8 / 10 == 216000
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
134 intel_dp_link_required(int pixel_clock
, int bpp
)
136 return (pixel_clock
* bpp
+ 9) / 10;
140 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
142 return (max_link_clock
* max_lanes
* 8) / 10;
146 intel_dp_mode_valid(struct drm_connector
*connector
,
147 struct drm_display_mode
*mode
)
149 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
150 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
151 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
152 int target_clock
= mode
->clock
;
153 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
155 if (is_edp(intel_dp
) && fixed_mode
) {
156 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
159 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
162 target_clock
= fixed_mode
->clock
;
165 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
166 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
168 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
169 mode_rate
= intel_dp_link_required(target_clock
, 18);
171 if (mode_rate
> max_rate
)
172 return MODE_CLOCK_HIGH
;
174 if (mode
->clock
< 10000)
175 return MODE_CLOCK_LOW
;
177 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
178 return MODE_H_ILLEGAL
;
184 pack_aux(uint8_t *src
, int src_bytes
)
191 for (i
= 0; i
< src_bytes
; i
++)
192 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
197 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
202 for (i
= 0; i
< dst_bytes
; i
++)
203 dst
[i
] = src
>> ((3-i
) * 8);
206 /* hrawclock is 1/4 the FSB frequency */
208 intel_hrawclk(struct drm_device
*dev
)
210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev
))
217 clkcfg
= I915_READ(CLKCFG
);
218 switch (clkcfg
& CLKCFG_FSB_MASK
) {
227 case CLKCFG_FSB_1067
:
229 case CLKCFG_FSB_1333
:
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600
:
233 case CLKCFG_FSB_1600_ALT
:
241 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
242 struct intel_dp
*intel_dp
,
243 struct edp_power_seq
*out
);
245 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
246 struct intel_dp
*intel_dp
,
247 struct edp_power_seq
*out
);
250 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
252 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
253 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
254 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
256 enum port port
= intel_dig_port
->port
;
259 /* modeset should have pipe */
261 return to_intel_crtc(crtc
)->pipe
;
263 /* init time, try to find a pipe with this port selected */
264 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
265 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
266 PANEL_PORT_SELECT_MASK
;
267 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
269 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
277 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
279 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
281 if (HAS_PCH_SPLIT(dev
))
282 return PCH_PP_CONTROL
;
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
287 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
289 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
291 if (HAS_PCH_SPLIT(dev
))
292 return PCH_PP_STATUS
;
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
297 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
299 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
302 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
305 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
307 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
310 return (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
314 intel_dp_check_edp(struct intel_dp
*intel_dp
)
316 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
319 if (!is_edp(intel_dp
))
322 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
325 I915_READ(_pp_stat_reg(intel_dp
)),
326 I915_READ(_pp_ctrl_reg(intel_dp
)));
331 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
333 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
334 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
336 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
342 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
343 msecs_to_jiffies_timeout(10));
345 done
= wait_for_atomic(C
, 10) == 0;
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
354 static uint32_t get_aux_clock_divider(struct intel_dp
*intel_dp
,
357 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
358 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
361 /* The clock divider is based off the hrawclk,
362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
365 * Note that PCH attached eDP panels should use a 125MHz input
368 if (IS_VALLEYVIEW(dev
)) {
369 return index
? 0 : 100;
370 } else if (intel_dig_port
->port
== PORT_A
) {
374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
375 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
378 return 225; /* eDP input clock at 450Mhz */
379 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
380 /* Workaround for non-ULT HSW */
386 } else if (HAS_PCH_SPLIT(dev
)) {
387 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
389 return index
? 0 :intel_hrawclk(dev
) / 2;
394 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
395 uint8_t *send
, int send_bytes
,
396 uint8_t *recv
, int recv_size
)
398 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
399 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
401 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
402 uint32_t ch_data
= ch_ctl
+ 4;
403 uint32_t aux_clock_divider
;
404 int i
, ret
, recv_bytes
;
406 int try, precharge
, clock
= 0;
407 bool has_aux_irq
= INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
);
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
413 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
415 intel_dp_check_edp(intel_dp
);
422 intel_aux_display_runtime_get(dev_priv
);
424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
426 status
= I915_READ_NOTRACE(ch_ctl
);
427 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
439 while ((aux_clock_divider
= get_aux_clock_divider(intel_dp
, clock
++))) {
440 /* Must try at least 3 times according to DP spec */
441 for (try = 0; try < 5; try++) {
442 /* Load the send data into the aux channel data registers */
443 for (i
= 0; i
< send_bytes
; i
+= 4)
444 I915_WRITE(ch_data
+ i
,
445 pack_aux(send
+ i
, send_bytes
- i
));
447 /* Send the command and wait for it to complete */
449 DP_AUX_CH_CTL_SEND_BUSY
|
450 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
451 DP_AUX_CH_CTL_TIME_OUT_400us
|
452 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
453 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
454 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
456 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
457 DP_AUX_CH_CTL_RECEIVE_ERROR
);
459 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
461 /* Clear done status and any errors */
465 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
466 DP_AUX_CH_CTL_RECEIVE_ERROR
);
468 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
469 DP_AUX_CH_CTL_RECEIVE_ERROR
))
471 if (status
& DP_AUX_CH_CTL_DONE
)
474 if (status
& DP_AUX_CH_CTL_DONE
)
478 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
479 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
484 /* Check for timeout or receive error.
485 * Timeouts occur when the sink is not connected
487 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
488 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
493 /* Timeouts occur when the device isn't connected, so they're
494 * "normal" -- don't fill the kernel log with these */
495 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
496 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
501 /* Unload any bytes sent back from the other side */
502 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
503 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
504 if (recv_bytes
> recv_size
)
505 recv_bytes
= recv_size
;
507 for (i
= 0; i
< recv_bytes
; i
+= 4)
508 unpack_aux(I915_READ(ch_data
+ i
),
509 recv
+ i
, recv_bytes
- i
);
513 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
514 intel_aux_display_runtime_put(dev_priv
);
519 /* Write data to the aux channel in native mode */
521 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
522 uint16_t address
, uint8_t *send
, int send_bytes
)
529 intel_dp_check_edp(intel_dp
);
532 msg
[0] = AUX_NATIVE_WRITE
<< 4;
533 msg
[1] = address
>> 8;
534 msg
[2] = address
& 0xff;
535 msg
[3] = send_bytes
- 1;
536 memcpy(&msg
[4], send
, send_bytes
);
537 msg_bytes
= send_bytes
+ 4;
539 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
542 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
544 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
552 /* Write a single byte to the aux channel in native mode */
554 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
555 uint16_t address
, uint8_t byte
)
557 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
560 /* read bytes from a native aux channel */
562 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
563 uint16_t address
, uint8_t *recv
, int recv_bytes
)
572 intel_dp_check_edp(intel_dp
);
573 msg
[0] = AUX_NATIVE_READ
<< 4;
574 msg
[1] = address
>> 8;
575 msg
[2] = address
& 0xff;
576 msg
[3] = recv_bytes
- 1;
579 reply_bytes
= recv_bytes
+ 1;
582 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
589 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
590 memcpy(recv
, reply
+ 1, ret
- 1);
593 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
601 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
602 uint8_t write_byte
, uint8_t *read_byte
)
604 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
605 struct intel_dp
*intel_dp
= container_of(adapter
,
608 uint16_t address
= algo_data
->address
;
616 intel_dp_check_edp(intel_dp
);
617 /* Set up the command byte */
618 if (mode
& MODE_I2C_READ
)
619 msg
[0] = AUX_I2C_READ
<< 4;
621 msg
[0] = AUX_I2C_WRITE
<< 4;
623 if (!(mode
& MODE_I2C_STOP
))
624 msg
[0] |= AUX_I2C_MOT
<< 4;
626 msg
[1] = address
>> 8;
647 for (retry
= 0; retry
< 5; retry
++) {
648 ret
= intel_dp_aux_ch(intel_dp
,
652 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
656 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
657 case AUX_NATIVE_REPLY_ACK
:
658 /* I2C-over-AUX Reply field is only valid
659 * when paired with AUX ACK.
662 case AUX_NATIVE_REPLY_NACK
:
663 DRM_DEBUG_KMS("aux_ch native nack\n");
665 case AUX_NATIVE_REPLY_DEFER
:
669 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
674 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
675 case AUX_I2C_REPLY_ACK
:
676 if (mode
== MODE_I2C_READ
) {
677 *read_byte
= reply
[1];
679 return reply_bytes
- 1;
680 case AUX_I2C_REPLY_NACK
:
681 DRM_DEBUG_KMS("aux_i2c nack\n");
683 case AUX_I2C_REPLY_DEFER
:
684 DRM_DEBUG_KMS("aux_i2c defer\n");
688 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
693 DRM_ERROR("too many retries, giving up\n");
698 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
699 struct intel_connector
*intel_connector
, const char *name
)
703 DRM_DEBUG_KMS("i2c_init %s\n", name
);
704 intel_dp
->algo
.running
= false;
705 intel_dp
->algo
.address
= 0;
706 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
708 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
709 intel_dp
->adapter
.owner
= THIS_MODULE
;
710 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
711 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
712 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
713 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
714 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
716 ironlake_edp_panel_vdd_on(intel_dp
);
717 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
718 ironlake_edp_panel_vdd_off(intel_dp
, false);
723 intel_dp_set_clock(struct intel_encoder
*encoder
,
724 struct intel_crtc_config
*pipe_config
, int link_bw
)
726 struct drm_device
*dev
= encoder
->base
.dev
;
727 const struct dp_link_dpll
*divisor
= NULL
;
732 count
= ARRAY_SIZE(gen4_dpll
);
733 } else if (IS_HASWELL(dev
)) {
734 /* Haswell has special-purpose DP DDI clocks. */
735 } else if (HAS_PCH_SPLIT(dev
)) {
737 count
= ARRAY_SIZE(pch_dpll
);
738 } else if (IS_VALLEYVIEW(dev
)) {
740 count
= ARRAY_SIZE(vlv_dpll
);
743 if (divisor
&& count
) {
744 for (i
= 0; i
< count
; i
++) {
745 if (link_bw
== divisor
[i
].link_bw
) {
746 pipe_config
->dpll
= divisor
[i
].dpll
;
747 pipe_config
->clock_set
= true;
755 intel_dp_compute_config(struct intel_encoder
*encoder
,
756 struct intel_crtc_config
*pipe_config
)
758 struct drm_device
*dev
= encoder
->base
.dev
;
759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
760 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
761 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
762 enum port port
= dp_to_dig_port(intel_dp
)->port
;
763 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
764 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
765 int lane_count
, clock
;
766 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
767 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
769 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
770 int link_avail
, link_clock
;
772 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
773 pipe_config
->has_pch_encoder
= true;
775 pipe_config
->has_dp_encoder
= true;
777 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
778 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
780 if (!HAS_PCH_SPLIT(dev
))
781 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
782 intel_connector
->panel
.fitting_mode
);
784 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
785 intel_connector
->panel
.fitting_mode
);
788 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
791 DRM_DEBUG_KMS("DP link computation with max lane count %i "
792 "max bw %02x pixel clock %iKHz\n",
793 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
795 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
797 bpp
= pipe_config
->pipe_bpp
;
798 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
) {
799 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
800 dev_priv
->vbt
.edp_bpp
);
801 bpp
= min_t(int, bpp
, dev_priv
->vbt
.edp_bpp
);
804 for (; bpp
>= 6*3; bpp
-= 2*3) {
805 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
807 for (clock
= 0; clock
<= max_clock
; clock
++) {
808 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
809 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
810 link_avail
= intel_dp_max_data_rate(link_clock
,
813 if (mode_rate
<= link_avail
) {
823 if (intel_dp
->color_range_auto
) {
826 * CEA-861-E - 5.1 Default Encoding Parameters
827 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
829 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
830 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
832 intel_dp
->color_range
= 0;
835 if (intel_dp
->color_range
)
836 pipe_config
->limited_color_range
= true;
838 intel_dp
->link_bw
= bws
[clock
];
839 intel_dp
->lane_count
= lane_count
;
840 pipe_config
->pipe_bpp
= bpp
;
841 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
843 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
844 intel_dp
->link_bw
, intel_dp
->lane_count
,
845 pipe_config
->port_clock
, bpp
);
846 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
847 mode_rate
, link_avail
);
849 intel_link_compute_m_n(bpp
, lane_count
,
850 adjusted_mode
->clock
, pipe_config
->port_clock
,
851 &pipe_config
->dp_m_n
);
853 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
858 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
860 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
861 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
862 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
863 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
865 * Check for DPCD version > 1.1 and enhanced framing support
867 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
868 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
869 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
873 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
875 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
876 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
877 struct drm_device
*dev
= crtc
->base
.dev
;
878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
881 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
882 dpa_ctl
= I915_READ(DP_A
);
883 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
885 if (crtc
->config
.port_clock
== 162000) {
886 /* For a long time we've carried around a ILK-DevA w/a for the
887 * 160MHz clock. If we're really unlucky, it's still required.
889 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
890 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
891 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
893 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
894 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
897 I915_WRITE(DP_A
, dpa_ctl
);
903 static void intel_dp_mode_set(struct intel_encoder
*encoder
)
905 struct drm_device
*dev
= encoder
->base
.dev
;
906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
907 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
908 enum port port
= dp_to_dig_port(intel_dp
)->port
;
909 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
910 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
913 * There are four kinds of DP registers:
920 * IBX PCH and CPU are the same for almost everything,
921 * except that the CPU DP PLL is configured in this
924 * CPT PCH is quite different, having many bits moved
925 * to the TRANS_DP_CTL register instead. That
926 * configuration happens (oddly) in ironlake_pch_enable
929 /* Preserve the BIOS-computed detected bit. This is
930 * supposed to be read-only.
932 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
934 /* Handle DP bits in common between all three register formats */
935 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
936 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
938 if (intel_dp
->has_audio
) {
939 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
940 pipe_name(crtc
->pipe
));
941 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
942 intel_write_eld(&encoder
->base
, adjusted_mode
);
945 intel_dp_init_link_config(intel_dp
);
947 /* Split out the IBX/CPU vs CPT settings */
949 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
950 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
951 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
952 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
953 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
954 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
956 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
957 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
959 intel_dp
->DP
|= crtc
->pipe
<< 29;
960 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
961 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
962 intel_dp
->DP
|= intel_dp
->color_range
;
964 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
965 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
966 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
967 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
968 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
970 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
971 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
974 intel_dp
->DP
|= DP_PIPEB_SELECT
;
976 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
979 if (port
== PORT_A
&& !IS_VALLEYVIEW(dev
))
980 ironlake_set_pll_cpu_edp(intel_dp
);
983 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
984 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
986 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
987 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
989 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
990 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
992 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
996 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
998 u32 pp_stat_reg
, pp_ctrl_reg
;
1000 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1001 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1003 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1005 I915_READ(pp_stat_reg
),
1006 I915_READ(pp_ctrl_reg
));
1008 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1009 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1010 I915_READ(pp_stat_reg
),
1011 I915_READ(pp_ctrl_reg
));
1015 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
1017 DRM_DEBUG_KMS("Wait for panel power on\n");
1018 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1021 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
1023 DRM_DEBUG_KMS("Wait for panel power off time\n");
1024 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1027 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1029 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1030 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1034 /* Read the current pp_control value, unlocking the register if it
1038 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1040 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1044 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1045 control
&= ~PANEL_UNLOCK_MASK
;
1046 control
|= PANEL_UNLOCK_REGS
;
1050 void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1052 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1055 u32 pp_stat_reg
, pp_ctrl_reg
;
1057 if (!is_edp(intel_dp
))
1059 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1061 WARN(intel_dp
->want_panel_vdd
,
1062 "eDP VDD already requested on\n");
1064 intel_dp
->want_panel_vdd
= true;
1066 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1067 DRM_DEBUG_KMS("eDP VDD already on\n");
1071 if (!ironlake_edp_have_panel_power(intel_dp
))
1072 ironlake_wait_panel_power_cycle(intel_dp
);
1074 pp
= ironlake_get_pp_control(intel_dp
);
1075 pp
|= EDP_FORCE_VDD
;
1077 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1078 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1080 I915_WRITE(pp_ctrl_reg
, pp
);
1081 POSTING_READ(pp_ctrl_reg
);
1082 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1083 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1085 * If the panel wasn't on, delay before accessing aux channel
1087 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1088 DRM_DEBUG_KMS("eDP was not running\n");
1089 msleep(intel_dp
->panel_power_up_delay
);
1093 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1095 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1098 u32 pp_stat_reg
, pp_ctrl_reg
;
1100 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1102 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1103 pp
= ironlake_get_pp_control(intel_dp
);
1104 pp
&= ~EDP_FORCE_VDD
;
1106 pp_stat_reg
= _pp_ctrl_reg(intel_dp
);
1107 pp_ctrl_reg
= _pp_stat_reg(intel_dp
);
1109 I915_WRITE(pp_ctrl_reg
, pp
);
1110 POSTING_READ(pp_ctrl_reg
);
1112 /* Make sure sequencer is idle before allowing subsequent activity */
1113 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1114 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1115 msleep(intel_dp
->panel_power_down_delay
);
1119 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1121 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1122 struct intel_dp
, panel_vdd_work
);
1123 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1125 mutex_lock(&dev
->mode_config
.mutex
);
1126 ironlake_panel_vdd_off_sync(intel_dp
);
1127 mutex_unlock(&dev
->mode_config
.mutex
);
1130 void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1132 if (!is_edp(intel_dp
))
1135 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1136 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1138 intel_dp
->want_panel_vdd
= false;
1141 ironlake_panel_vdd_off_sync(intel_dp
);
1144 * Queue the timer to fire a long
1145 * time from now (relative to the power down delay)
1146 * to keep the panel power up across a sequence of operations
1148 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1149 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1153 void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1155 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1160 if (!is_edp(intel_dp
))
1163 DRM_DEBUG_KMS("Turn eDP power on\n");
1165 if (ironlake_edp_have_panel_power(intel_dp
)) {
1166 DRM_DEBUG_KMS("eDP power already on\n");
1170 ironlake_wait_panel_power_cycle(intel_dp
);
1172 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1173 pp
= ironlake_get_pp_control(intel_dp
);
1175 /* ILK workaround: disable reset around power sequence */
1176 pp
&= ~PANEL_POWER_RESET
;
1177 I915_WRITE(pp_ctrl_reg
, pp
);
1178 POSTING_READ(pp_ctrl_reg
);
1181 pp
|= POWER_TARGET_ON
;
1183 pp
|= PANEL_POWER_RESET
;
1185 I915_WRITE(pp_ctrl_reg
, pp
);
1186 POSTING_READ(pp_ctrl_reg
);
1188 ironlake_wait_panel_on(intel_dp
);
1191 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1192 I915_WRITE(pp_ctrl_reg
, pp
);
1193 POSTING_READ(pp_ctrl_reg
);
1197 void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1199 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1204 if (!is_edp(intel_dp
))
1207 DRM_DEBUG_KMS("Turn eDP power off\n");
1209 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1211 pp
= ironlake_get_pp_control(intel_dp
);
1212 /* We need to switch off panel power _and_ force vdd, for otherwise some
1213 * panels get very unhappy and cease to work. */
1214 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1216 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1218 I915_WRITE(pp_ctrl_reg
, pp
);
1219 POSTING_READ(pp_ctrl_reg
);
1221 intel_dp
->want_panel_vdd
= false;
1223 ironlake_wait_panel_off(intel_dp
);
1226 void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1228 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1229 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1231 int pipe
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
)->pipe
;
1235 if (!is_edp(intel_dp
))
1238 DRM_DEBUG_KMS("\n");
1240 * If we enable the backlight right away following a panel power
1241 * on, we may see slight flicker as the panel syncs with the eDP
1242 * link. So delay a bit to make sure the image is solid before
1243 * allowing it to appear.
1245 msleep(intel_dp
->backlight_on_delay
);
1246 pp
= ironlake_get_pp_control(intel_dp
);
1247 pp
|= EDP_BLC_ENABLE
;
1249 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1251 I915_WRITE(pp_ctrl_reg
, pp
);
1252 POSTING_READ(pp_ctrl_reg
);
1254 intel_panel_enable_backlight(dev
, pipe
);
1257 void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1259 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1264 if (!is_edp(intel_dp
))
1267 intel_panel_disable_backlight(dev
);
1269 DRM_DEBUG_KMS("\n");
1270 pp
= ironlake_get_pp_control(intel_dp
);
1271 pp
&= ~EDP_BLC_ENABLE
;
1273 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1275 I915_WRITE(pp_ctrl_reg
, pp
);
1276 POSTING_READ(pp_ctrl_reg
);
1277 msleep(intel_dp
->backlight_off_delay
);
1280 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1282 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1283 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1284 struct drm_device
*dev
= crtc
->dev
;
1285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1288 assert_pipe_disabled(dev_priv
,
1289 to_intel_crtc(crtc
)->pipe
);
1291 DRM_DEBUG_KMS("\n");
1292 dpa_ctl
= I915_READ(DP_A
);
1293 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1294 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1296 /* We don't adjust intel_dp->DP while tearing down the link, to
1297 * facilitate link retraining (e.g. after hotplug). Hence clear all
1298 * enable bits here to ensure that we don't enable too much. */
1299 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1300 intel_dp
->DP
|= DP_PLL_ENABLE
;
1301 I915_WRITE(DP_A
, intel_dp
->DP
);
1306 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1308 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1309 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1310 struct drm_device
*dev
= crtc
->dev
;
1311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1314 assert_pipe_disabled(dev_priv
,
1315 to_intel_crtc(crtc
)->pipe
);
1317 dpa_ctl
= I915_READ(DP_A
);
1318 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1319 "dp pll off, should be on\n");
1320 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1322 /* We can't rely on the value tracked for the DP register in
1323 * intel_dp->DP because link_down must not change that (otherwise link
1324 * re-training will fail. */
1325 dpa_ctl
&= ~DP_PLL_ENABLE
;
1326 I915_WRITE(DP_A
, dpa_ctl
);
1331 /* If the sink supports it, try to set the power state appropriately */
1332 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1336 /* Should have a valid DPCD by this point */
1337 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1340 if (mode
!= DRM_MODE_DPMS_ON
) {
1341 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1344 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1347 * When turning on, we need to retry for 1ms to give the sink
1350 for (i
= 0; i
< 3; i
++) {
1351 ret
= intel_dp_aux_native_write_1(intel_dp
,
1361 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1364 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1365 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1366 struct drm_device
*dev
= encoder
->base
.dev
;
1367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1368 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1370 if (!(tmp
& DP_PORT_EN
))
1373 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1374 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1375 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1376 *pipe
= PORT_TO_PIPE(tmp
);
1382 switch (intel_dp
->output_reg
) {
1384 trans_sel
= TRANS_DP_PORT_SEL_B
;
1387 trans_sel
= TRANS_DP_PORT_SEL_C
;
1390 trans_sel
= TRANS_DP_PORT_SEL_D
;
1397 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1398 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1404 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1405 intel_dp
->output_reg
);
1411 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1412 struct intel_crtc_config
*pipe_config
)
1414 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1416 struct drm_device
*dev
= encoder
->base
.dev
;
1417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1418 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1419 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1422 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1423 tmp
= I915_READ(intel_dp
->output_reg
);
1424 if (tmp
& DP_SYNC_HS_HIGH
)
1425 flags
|= DRM_MODE_FLAG_PHSYNC
;
1427 flags
|= DRM_MODE_FLAG_NHSYNC
;
1429 if (tmp
& DP_SYNC_VS_HIGH
)
1430 flags
|= DRM_MODE_FLAG_PVSYNC
;
1432 flags
|= DRM_MODE_FLAG_NVSYNC
;
1434 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1435 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1436 flags
|= DRM_MODE_FLAG_PHSYNC
;
1438 flags
|= DRM_MODE_FLAG_NHSYNC
;
1440 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1441 flags
|= DRM_MODE_FLAG_PVSYNC
;
1443 flags
|= DRM_MODE_FLAG_NVSYNC
;
1446 pipe_config
->adjusted_mode
.flags
|= flags
;
1448 pipe_config
->has_dp_encoder
= true;
1450 intel_dp_get_m_n(crtc
, pipe_config
);
1452 if (port
== PORT_A
) {
1453 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1454 pipe_config
->port_clock
= 162000;
1456 pipe_config
->port_clock
= 270000;
1459 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1460 &pipe_config
->dp_m_n
);
1462 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1463 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1465 pipe_config
->adjusted_mode
.clock
= dotclock
;
1468 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1470 return is_edp(intel_dp
) &&
1471 intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1474 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1478 if (!IS_HASWELL(dev
))
1481 return I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
1484 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1485 struct edp_vsc_psr
*vsc_psr
)
1487 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1488 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1490 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1491 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1492 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1493 uint32_t *data
= (uint32_t *) vsc_psr
;
1496 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1497 the video DIP being updated before program video DIP data buffer
1498 registers for DIP being updated. */
1499 I915_WRITE(ctl_reg
, 0);
1500 POSTING_READ(ctl_reg
);
1502 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1503 if (i
< sizeof(struct edp_vsc_psr
))
1504 I915_WRITE(data_reg
+ i
, *data
++);
1506 I915_WRITE(data_reg
+ i
, 0);
1509 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1510 POSTING_READ(ctl_reg
);
1513 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1515 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1517 struct edp_vsc_psr psr_vsc
;
1519 if (intel_dp
->psr_setup_done
)
1522 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1523 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1524 psr_vsc
.sdp_header
.HB0
= 0;
1525 psr_vsc
.sdp_header
.HB1
= 0x7;
1526 psr_vsc
.sdp_header
.HB2
= 0x2;
1527 psr_vsc
.sdp_header
.HB3
= 0x8;
1528 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1530 /* Avoid continuous PSR exit by masking memup and hpd */
1531 I915_WRITE(EDP_PSR_DEBUG_CTL
, EDP_PSR_DEBUG_MASK_MEMUP
|
1532 EDP_PSR_DEBUG_MASK_HPD
);
1534 intel_dp
->psr_setup_done
= true;
1537 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1539 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1541 uint32_t aux_clock_divider
= get_aux_clock_divider(intel_dp
, 0);
1542 int precharge
= 0x3;
1543 int msg_size
= 5; /* Header(4) + Message(1) */
1545 /* Enable PSR in sink */
1546 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
)
1547 intel_dp_aux_native_write_1(intel_dp
, DP_PSR_EN_CFG
,
1549 ~DP_PSR_MAIN_LINK_ACTIVE
);
1551 intel_dp_aux_native_write_1(intel_dp
, DP_PSR_EN_CFG
,
1553 DP_PSR_MAIN_LINK_ACTIVE
);
1555 /* Setup AUX registers */
1556 I915_WRITE(EDP_PSR_AUX_DATA1
, EDP_PSR_DPCD_COMMAND
);
1557 I915_WRITE(EDP_PSR_AUX_DATA2
, EDP_PSR_DPCD_NORMAL_OPERATION
);
1558 I915_WRITE(EDP_PSR_AUX_CTL
,
1559 DP_AUX_CH_CTL_TIME_OUT_400us
|
1560 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1561 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1562 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1565 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1567 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1569 uint32_t max_sleep_time
= 0x1f;
1570 uint32_t idle_frames
= 1;
1573 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
1574 val
|= EDP_PSR_LINK_STANDBY
;
1575 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1576 val
|= EDP_PSR_TP1_TIME_0us
;
1577 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1579 val
|= EDP_PSR_LINK_DISABLE
;
1581 I915_WRITE(EDP_PSR_CTL
, val
|
1582 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
|
1583 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1584 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1588 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1590 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1591 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1593 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1594 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1595 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1596 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
1598 if (!IS_HASWELL(dev
)) {
1599 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1600 dev_priv
->no_psr_reason
= PSR_NO_SOURCE
;
1604 if ((intel_encoder
->type
!= INTEL_OUTPUT_EDP
) ||
1605 (dig_port
->port
!= PORT_A
)) {
1606 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1607 dev_priv
->no_psr_reason
= PSR_HSW_NOT_DDIA
;
1611 if (!is_edp_psr(intel_dp
)) {
1612 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1613 dev_priv
->no_psr_reason
= PSR_NO_SINK
;
1617 if (!i915_enable_psr
) {
1618 DRM_DEBUG_KMS("PSR disable by flag\n");
1619 dev_priv
->no_psr_reason
= PSR_MODULE_PARAM
;
1623 crtc
= dig_port
->base
.base
.crtc
;
1625 DRM_DEBUG_KMS("crtc not active for PSR\n");
1626 dev_priv
->no_psr_reason
= PSR_CRTC_NOT_ACTIVE
;
1630 intel_crtc
= to_intel_crtc(crtc
);
1631 if (!intel_crtc
->active
|| !crtc
->fb
|| !crtc
->mode
.clock
) {
1632 DRM_DEBUG_KMS("crtc not active for PSR\n");
1633 dev_priv
->no_psr_reason
= PSR_CRTC_NOT_ACTIVE
;
1637 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1638 if (obj
->tiling_mode
!= I915_TILING_X
||
1639 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1640 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1641 dev_priv
->no_psr_reason
= PSR_NOT_TILED
;
1645 if (I915_READ(SPRCTL(intel_crtc
->pipe
)) & SPRITE_ENABLE
) {
1646 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1647 dev_priv
->no_psr_reason
= PSR_SPRITE_ENABLED
;
1651 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1653 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1654 dev_priv
->no_psr_reason
= PSR_S3D_ENABLED
;
1658 if (crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1659 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1660 dev_priv
->no_psr_reason
= PSR_INTERLACED_ENABLED
;
1667 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1669 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1671 if (!intel_edp_psr_match_conditions(intel_dp
) ||
1672 intel_edp_is_psr_enabled(dev
))
1675 /* Setup PSR once */
1676 intel_edp_psr_setup(intel_dp
);
1678 /* Enable PSR on the panel */
1679 intel_edp_psr_enable_sink(intel_dp
);
1681 /* Enable PSR on the host */
1682 intel_edp_psr_enable_source(intel_dp
);
1685 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1687 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1689 if (intel_edp_psr_match_conditions(intel_dp
) &&
1690 !intel_edp_is_psr_enabled(dev
))
1691 intel_edp_psr_do_enable(intel_dp
);
1694 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1696 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1699 if (!intel_edp_is_psr_enabled(dev
))
1702 I915_WRITE(EDP_PSR_CTL
, I915_READ(EDP_PSR_CTL
) & ~EDP_PSR_ENABLE
);
1704 /* Wait till PSR is idle */
1705 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL
) &
1706 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1707 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1710 void intel_edp_psr_update(struct drm_device
*dev
)
1712 struct intel_encoder
*encoder
;
1713 struct intel_dp
*intel_dp
= NULL
;
1715 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
)
1716 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
1717 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1719 if (!is_edp_psr(intel_dp
))
1722 if (!intel_edp_psr_match_conditions(intel_dp
))
1723 intel_edp_psr_disable(intel_dp
);
1725 if (!intel_edp_is_psr_enabled(dev
))
1726 intel_edp_psr_do_enable(intel_dp
);
1730 static void intel_disable_dp(struct intel_encoder
*encoder
)
1732 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1733 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1734 struct drm_device
*dev
= encoder
->base
.dev
;
1736 /* Make sure the panel is off before trying to change the mode. But also
1737 * ensure that we have vdd while we switch off the panel. */
1738 ironlake_edp_panel_vdd_on(intel_dp
);
1739 ironlake_edp_backlight_off(intel_dp
);
1740 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1741 ironlake_edp_panel_off(intel_dp
);
1743 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1744 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1745 intel_dp_link_down(intel_dp
);
1748 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1750 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1751 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1752 struct drm_device
*dev
= encoder
->base
.dev
;
1754 if (port
== PORT_A
|| IS_VALLEYVIEW(dev
)) {
1755 intel_dp_link_down(intel_dp
);
1756 if (!IS_VALLEYVIEW(dev
))
1757 ironlake_edp_pll_off(intel_dp
);
1761 static void intel_enable_dp(struct intel_encoder
*encoder
)
1763 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1764 struct drm_device
*dev
= encoder
->base
.dev
;
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1768 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1771 ironlake_edp_panel_vdd_on(intel_dp
);
1772 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1773 intel_dp_start_link_train(intel_dp
);
1774 ironlake_edp_panel_on(intel_dp
);
1775 ironlake_edp_panel_vdd_off(intel_dp
, true);
1776 intel_dp_complete_link_train(intel_dp
);
1777 intel_dp_stop_link_train(intel_dp
);
1780 static void g4x_enable_dp(struct intel_encoder
*encoder
)
1782 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1784 intel_enable_dp(encoder
);
1785 ironlake_edp_backlight_on(intel_dp
);
1788 static void vlv_enable_dp(struct intel_encoder
*encoder
)
1790 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1792 ironlake_edp_backlight_on(intel_dp
);
1795 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
1797 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1798 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1800 if (dport
->port
== PORT_A
)
1801 ironlake_edp_pll_on(intel_dp
);
1804 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
1806 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1807 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1808 struct drm_device
*dev
= encoder
->base
.dev
;
1809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1810 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1811 int port
= vlv_dport_to_channel(dport
);
1812 int pipe
= intel_crtc
->pipe
;
1813 struct edp_power_seq power_seq
;
1816 mutex_lock(&dev_priv
->dpio_lock
);
1818 val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_DATA_LANE_A(port
));
1825 vlv_dpio_write(dev_priv
, pipe
, DPIO_DATA_CHANNEL(port
), val
);
1826 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_CLOCKBUF0(port
), 0x00760018);
1827 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_CLOCKBUF8(port
), 0x00400888);
1829 mutex_unlock(&dev_priv
->dpio_lock
);
1831 /* init power sequencer on this pipe and port */
1832 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
1833 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
1836 intel_enable_dp(encoder
);
1838 vlv_wait_port_ready(dev_priv
, port
);
1841 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
1843 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1844 struct drm_device
*dev
= encoder
->base
.dev
;
1845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1846 struct intel_crtc
*intel_crtc
=
1847 to_intel_crtc(encoder
->base
.crtc
);
1848 int port
= vlv_dport_to_channel(dport
);
1849 int pipe
= intel_crtc
->pipe
;
1851 /* Program Tx lane resets to default */
1852 mutex_lock(&dev_priv
->dpio_lock
);
1853 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_TX(port
),
1854 DPIO_PCS_TX_LANE2_RESET
|
1855 DPIO_PCS_TX_LANE1_RESET
);
1856 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_CLK(port
),
1857 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1858 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1859 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1860 DPIO_PCS_CLK_SOFT_RESET
);
1862 /* Fix up inter-pair skew failure */
1863 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_STAGGER1(port
), 0x00750f00);
1864 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_CTL(port
), 0x00001500);
1865 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_LANE(port
), 0x40400000);
1866 mutex_unlock(&dev_priv
->dpio_lock
);
1870 * Native read with retry for link status and receiver capability reads for
1871 * cases where the sink may still be asleep.
1874 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1875 uint8_t *recv
, int recv_bytes
)
1880 * Sinks are *supposed* to come up within 1ms from an off state,
1881 * but we're also supposed to retry 3 times per the spec.
1883 for (i
= 0; i
< 3; i
++) {
1884 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1886 if (ret
== recv_bytes
)
1895 * Fetch AUX CH registers 0x202 - 0x207 which contain
1896 * link status information
1899 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1901 return intel_dp_aux_native_read_retry(intel_dp
,
1904 DP_LINK_STATUS_SIZE
);
1908 static char *voltage_names
[] = {
1909 "0.4V", "0.6V", "0.8V", "1.2V"
1911 static char *pre_emph_names
[] = {
1912 "0dB", "3.5dB", "6dB", "9.5dB"
1914 static char *link_train_names
[] = {
1915 "pattern 1", "pattern 2", "idle", "off"
1920 * These are source-specific values; current Intel hardware supports
1921 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1925 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1927 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1928 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1930 if (IS_VALLEYVIEW(dev
))
1931 return DP_TRAIN_VOLTAGE_SWING_1200
;
1932 else if (IS_GEN7(dev
) && port
== PORT_A
)
1933 return DP_TRAIN_VOLTAGE_SWING_800
;
1934 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
1935 return DP_TRAIN_VOLTAGE_SWING_1200
;
1937 return DP_TRAIN_VOLTAGE_SWING_800
;
1941 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1943 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1944 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1947 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1948 case DP_TRAIN_VOLTAGE_SWING_400
:
1949 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1950 case DP_TRAIN_VOLTAGE_SWING_600
:
1951 return DP_TRAIN_PRE_EMPHASIS_6
;
1952 case DP_TRAIN_VOLTAGE_SWING_800
:
1953 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1954 case DP_TRAIN_VOLTAGE_SWING_1200
:
1956 return DP_TRAIN_PRE_EMPHASIS_0
;
1958 } else if (IS_VALLEYVIEW(dev
)) {
1959 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1960 case DP_TRAIN_VOLTAGE_SWING_400
:
1961 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1962 case DP_TRAIN_VOLTAGE_SWING_600
:
1963 return DP_TRAIN_PRE_EMPHASIS_6
;
1964 case DP_TRAIN_VOLTAGE_SWING_800
:
1965 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1966 case DP_TRAIN_VOLTAGE_SWING_1200
:
1968 return DP_TRAIN_PRE_EMPHASIS_0
;
1970 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
1971 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1972 case DP_TRAIN_VOLTAGE_SWING_400
:
1973 return DP_TRAIN_PRE_EMPHASIS_6
;
1974 case DP_TRAIN_VOLTAGE_SWING_600
:
1975 case DP_TRAIN_VOLTAGE_SWING_800
:
1976 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1978 return DP_TRAIN_PRE_EMPHASIS_0
;
1981 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1982 case DP_TRAIN_VOLTAGE_SWING_400
:
1983 return DP_TRAIN_PRE_EMPHASIS_6
;
1984 case DP_TRAIN_VOLTAGE_SWING_600
:
1985 return DP_TRAIN_PRE_EMPHASIS_6
;
1986 case DP_TRAIN_VOLTAGE_SWING_800
:
1987 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1988 case DP_TRAIN_VOLTAGE_SWING_1200
:
1990 return DP_TRAIN_PRE_EMPHASIS_0
;
1995 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
1997 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1999 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2000 struct intel_crtc
*intel_crtc
=
2001 to_intel_crtc(dport
->base
.base
.crtc
);
2002 unsigned long demph_reg_value
, preemph_reg_value
,
2003 uniqtranscale_reg_value
;
2004 uint8_t train_set
= intel_dp
->train_set
[0];
2005 int port
= vlv_dport_to_channel(dport
);
2006 int pipe
= intel_crtc
->pipe
;
2008 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2009 case DP_TRAIN_PRE_EMPHASIS_0
:
2010 preemph_reg_value
= 0x0004000;
2011 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2012 case DP_TRAIN_VOLTAGE_SWING_400
:
2013 demph_reg_value
= 0x2B405555;
2014 uniqtranscale_reg_value
= 0x552AB83A;
2016 case DP_TRAIN_VOLTAGE_SWING_600
:
2017 demph_reg_value
= 0x2B404040;
2018 uniqtranscale_reg_value
= 0x5548B83A;
2020 case DP_TRAIN_VOLTAGE_SWING_800
:
2021 demph_reg_value
= 0x2B245555;
2022 uniqtranscale_reg_value
= 0x5560B83A;
2024 case DP_TRAIN_VOLTAGE_SWING_1200
:
2025 demph_reg_value
= 0x2B405555;
2026 uniqtranscale_reg_value
= 0x5598DA3A;
2032 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2033 preemph_reg_value
= 0x0002000;
2034 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2035 case DP_TRAIN_VOLTAGE_SWING_400
:
2036 demph_reg_value
= 0x2B404040;
2037 uniqtranscale_reg_value
= 0x5552B83A;
2039 case DP_TRAIN_VOLTAGE_SWING_600
:
2040 demph_reg_value
= 0x2B404848;
2041 uniqtranscale_reg_value
= 0x5580B83A;
2043 case DP_TRAIN_VOLTAGE_SWING_800
:
2044 demph_reg_value
= 0x2B404040;
2045 uniqtranscale_reg_value
= 0x55ADDA3A;
2051 case DP_TRAIN_PRE_EMPHASIS_6
:
2052 preemph_reg_value
= 0x0000000;
2053 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2054 case DP_TRAIN_VOLTAGE_SWING_400
:
2055 demph_reg_value
= 0x2B305555;
2056 uniqtranscale_reg_value
= 0x5570B83A;
2058 case DP_TRAIN_VOLTAGE_SWING_600
:
2059 demph_reg_value
= 0x2B2B4040;
2060 uniqtranscale_reg_value
= 0x55ADDA3A;
2066 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2067 preemph_reg_value
= 0x0006000;
2068 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2069 case DP_TRAIN_VOLTAGE_SWING_400
:
2070 demph_reg_value
= 0x1B405555;
2071 uniqtranscale_reg_value
= 0x55ADDA3A;
2081 mutex_lock(&dev_priv
->dpio_lock
);
2082 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_OCALINIT(port
), 0x00000000);
2083 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_SWING_CTL4(port
), demph_reg_value
);
2084 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_SWING_CTL2(port
),
2085 uniqtranscale_reg_value
);
2086 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_SWING_CTL3(port
), 0x0C782040);
2087 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_STAGGER0(port
), 0x00030000);
2088 vlv_dpio_write(dev_priv
, pipe
, DPIO_PCS_CTL_OVER1(port
), preemph_reg_value
);
2089 vlv_dpio_write(dev_priv
, pipe
, DPIO_TX_OCALINIT(port
), 0x80000000);
2090 mutex_unlock(&dev_priv
->dpio_lock
);
2096 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2101 uint8_t voltage_max
;
2102 uint8_t preemph_max
;
2104 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2105 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2106 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2114 voltage_max
= intel_dp_voltage_max(intel_dp
);
2115 if (v
>= voltage_max
)
2116 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2118 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2119 if (p
>= preemph_max
)
2120 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2122 for (lane
= 0; lane
< 4; lane
++)
2123 intel_dp
->train_set
[lane
] = v
| p
;
2127 intel_gen4_signal_levels(uint8_t train_set
)
2129 uint32_t signal_levels
= 0;
2131 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2132 case DP_TRAIN_VOLTAGE_SWING_400
:
2134 signal_levels
|= DP_VOLTAGE_0_4
;
2136 case DP_TRAIN_VOLTAGE_SWING_600
:
2137 signal_levels
|= DP_VOLTAGE_0_6
;
2139 case DP_TRAIN_VOLTAGE_SWING_800
:
2140 signal_levels
|= DP_VOLTAGE_0_8
;
2142 case DP_TRAIN_VOLTAGE_SWING_1200
:
2143 signal_levels
|= DP_VOLTAGE_1_2
;
2146 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2147 case DP_TRAIN_PRE_EMPHASIS_0
:
2149 signal_levels
|= DP_PRE_EMPHASIS_0
;
2151 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2152 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2154 case DP_TRAIN_PRE_EMPHASIS_6
:
2155 signal_levels
|= DP_PRE_EMPHASIS_6
;
2157 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2158 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2161 return signal_levels
;
2164 /* Gen6's DP voltage swing and pre-emphasis control */
2166 intel_gen6_edp_signal_levels(uint8_t train_set
)
2168 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2169 DP_TRAIN_PRE_EMPHASIS_MASK
);
2170 switch (signal_levels
) {
2171 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2172 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2173 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2174 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2175 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2176 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2177 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2178 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2179 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2180 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2181 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2182 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2183 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2184 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2186 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2187 "0x%x\n", signal_levels
);
2188 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2192 /* Gen7's DP voltage swing and pre-emphasis control */
2194 intel_gen7_edp_signal_levels(uint8_t train_set
)
2196 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2197 DP_TRAIN_PRE_EMPHASIS_MASK
);
2198 switch (signal_levels
) {
2199 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2200 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2201 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2202 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2203 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2204 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2206 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2207 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2208 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2209 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2211 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2212 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2213 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2214 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2217 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2218 "0x%x\n", signal_levels
);
2219 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2223 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2225 intel_hsw_signal_levels(uint8_t train_set
)
2227 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2228 DP_TRAIN_PRE_EMPHASIS_MASK
);
2229 switch (signal_levels
) {
2230 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2231 return DDI_BUF_EMP_400MV_0DB_HSW
;
2232 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2233 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2234 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2235 return DDI_BUF_EMP_400MV_6DB_HSW
;
2236 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2237 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2239 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2240 return DDI_BUF_EMP_600MV_0DB_HSW
;
2241 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2242 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2243 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2244 return DDI_BUF_EMP_600MV_6DB_HSW
;
2246 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2247 return DDI_BUF_EMP_800MV_0DB_HSW
;
2248 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2249 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2251 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2252 "0x%x\n", signal_levels
);
2253 return DDI_BUF_EMP_400MV_0DB_HSW
;
2257 /* Properly updates "DP" with the correct signal levels. */
2259 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2261 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2262 enum port port
= intel_dig_port
->port
;
2263 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2264 uint32_t signal_levels
, mask
;
2265 uint8_t train_set
= intel_dp
->train_set
[0];
2268 signal_levels
= intel_hsw_signal_levels(train_set
);
2269 mask
= DDI_BUF_EMP_MASK
;
2270 } else if (IS_VALLEYVIEW(dev
)) {
2271 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2273 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2274 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2275 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2276 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2277 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2278 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2280 signal_levels
= intel_gen4_signal_levels(train_set
);
2281 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2284 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2286 *DP
= (*DP
& ~mask
) | signal_levels
;
2290 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2291 uint32_t dp_reg_value
,
2292 uint8_t dp_train_pat
)
2294 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2295 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2297 enum port port
= intel_dig_port
->port
;
2301 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2303 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2304 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2306 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2308 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2309 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2310 case DP_TRAINING_PATTERN_DISABLE
:
2311 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2314 case DP_TRAINING_PATTERN_1
:
2315 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2317 case DP_TRAINING_PATTERN_2
:
2318 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2320 case DP_TRAINING_PATTERN_3
:
2321 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2324 I915_WRITE(DP_TP_CTL(port
), temp
);
2326 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2327 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
2329 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2330 case DP_TRAINING_PATTERN_DISABLE
:
2331 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
2333 case DP_TRAINING_PATTERN_1
:
2334 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
2336 case DP_TRAINING_PATTERN_2
:
2337 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
2339 case DP_TRAINING_PATTERN_3
:
2340 DRM_ERROR("DP training pattern 3 not supported\n");
2341 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
2346 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
2348 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2349 case DP_TRAINING_PATTERN_DISABLE
:
2350 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
2352 case DP_TRAINING_PATTERN_1
:
2353 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
2355 case DP_TRAINING_PATTERN_2
:
2356 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
2358 case DP_TRAINING_PATTERN_3
:
2359 DRM_ERROR("DP training pattern 3 not supported\n");
2360 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
2365 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
2366 POSTING_READ(intel_dp
->output_reg
);
2368 intel_dp_aux_native_write_1(intel_dp
,
2369 DP_TRAINING_PATTERN_SET
,
2372 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
2373 DP_TRAINING_PATTERN_DISABLE
) {
2374 ret
= intel_dp_aux_native_write(intel_dp
,
2375 DP_TRAINING_LANE0_SET
,
2376 intel_dp
->train_set
,
2377 intel_dp
->lane_count
);
2378 if (ret
!= intel_dp
->lane_count
)
2385 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
2387 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2388 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2390 enum port port
= intel_dig_port
->port
;
2396 val
= I915_READ(DP_TP_CTL(port
));
2397 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2398 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2399 I915_WRITE(DP_TP_CTL(port
), val
);
2402 * On PORT_A we can have only eDP in SST mode. There the only reason
2403 * we need to set idle transmission mode is to work around a HW issue
2404 * where we enable the pipe while not in idle link-training mode.
2405 * In this case there is requirement to wait for a minimum number of
2406 * idle patterns to be sent.
2411 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2413 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2416 /* Enable corresponding port and start training pattern 1 */
2418 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2420 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2421 struct drm_device
*dev
= encoder
->dev
;
2424 int voltage_tries
, loop_tries
;
2425 uint32_t DP
= intel_dp
->DP
;
2428 intel_ddi_prepare_link_retrain(encoder
);
2430 /* Write the link configuration data */
2431 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
2432 intel_dp
->link_configuration
,
2433 DP_LINK_CONFIGURATION_SIZE
);
2437 memset(intel_dp
->train_set
, 0, 4);
2442 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2443 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2445 intel_dp_set_signal_levels(intel_dp
, &DP
);
2447 /* Set training pattern 1 */
2448 if (!intel_dp_set_link_train(intel_dp
, DP
,
2449 DP_TRAINING_PATTERN_1
|
2450 DP_LINK_SCRAMBLING_DISABLE
))
2453 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2454 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2455 DRM_ERROR("failed to get link status\n");
2459 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2460 DRM_DEBUG_KMS("clock recovery OK\n");
2464 /* Check to see if we've tried the max voltage */
2465 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2466 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2468 if (i
== intel_dp
->lane_count
) {
2470 if (loop_tries
== 5) {
2471 DRM_DEBUG_KMS("too many full retries, give up\n");
2474 memset(intel_dp
->train_set
, 0, 4);
2479 /* Check to see if we've tried the same voltage 5 times */
2480 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
2482 if (voltage_tries
== 5) {
2483 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2488 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
2490 /* Compute new intel_dp->train_set as requested by target */
2491 intel_get_adjust_train(intel_dp
, link_status
);
2498 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
2500 bool channel_eq
= false;
2501 int tries
, cr_tries
;
2502 uint32_t DP
= intel_dp
->DP
;
2504 /* channel equalization */
2509 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2512 DRM_ERROR("failed to train DP, aborting\n");
2513 intel_dp_link_down(intel_dp
);
2517 intel_dp_set_signal_levels(intel_dp
, &DP
);
2519 /* channel eq pattern */
2520 if (!intel_dp_set_link_train(intel_dp
, DP
,
2521 DP_TRAINING_PATTERN_2
|
2522 DP_LINK_SCRAMBLING_DISABLE
))
2525 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
2526 if (!intel_dp_get_link_status(intel_dp
, link_status
))
2529 /* Make sure clock is still ok */
2530 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2531 intel_dp_start_link_train(intel_dp
);
2536 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2541 /* Try 5 times, then try clock recovery if that fails */
2543 intel_dp_link_down(intel_dp
);
2544 intel_dp_start_link_train(intel_dp
);
2550 /* Compute new intel_dp->train_set as requested by target */
2551 intel_get_adjust_train(intel_dp
, link_status
);
2555 intel_dp_set_idle_link_train(intel_dp
);
2560 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2564 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
2566 intel_dp_set_link_train(intel_dp
, intel_dp
->DP
,
2567 DP_TRAINING_PATTERN_DISABLE
);
2571 intel_dp_link_down(struct intel_dp
*intel_dp
)
2573 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2574 enum port port
= intel_dig_port
->port
;
2575 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2577 struct intel_crtc
*intel_crtc
=
2578 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2579 uint32_t DP
= intel_dp
->DP
;
2582 * DDI code has a strict mode set sequence and we should try to respect
2583 * it, otherwise we might hang the machine in many different ways. So we
2584 * really should be disabling the port only on a complete crtc_disable
2585 * sequence. This function is just called under two conditions on DDI
2587 * - Link train failed while doing crtc_enable, and on this case we
2588 * really should respect the mode set sequence and wait for a
2590 * - Someone turned the monitor off and intel_dp_check_link_status
2591 * called us. We don't need to disable the whole port on this case, so
2592 * when someone turns the monitor on again,
2593 * intel_ddi_prepare_link_retrain will take care of redoing the link
2599 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2602 DRM_DEBUG_KMS("\n");
2604 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2605 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2606 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2608 DP
&= ~DP_LINK_TRAIN_MASK
;
2609 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2611 POSTING_READ(intel_dp
->output_reg
);
2613 /* We don't really know why we're doing this */
2614 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2616 if (HAS_PCH_IBX(dev
) &&
2617 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2618 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2620 /* Hardware workaround: leaving our transcoder select
2621 * set to transcoder B while it's off will prevent the
2622 * corresponding HDMI output on transcoder A.
2624 * Combine this with another hardware workaround:
2625 * transcoder select bit can only be cleared while the
2628 DP
&= ~DP_PIPEB_SELECT
;
2629 I915_WRITE(intel_dp
->output_reg
, DP
);
2631 /* Changes to enable or select take place the vblank
2632 * after being written.
2634 if (WARN_ON(crtc
== NULL
)) {
2635 /* We should never try to disable a port without a crtc
2636 * attached. For paranoia keep the code around for a
2638 POSTING_READ(intel_dp
->output_reg
);
2641 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2644 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2645 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2646 POSTING_READ(intel_dp
->output_reg
);
2647 msleep(intel_dp
->panel_power_down_delay
);
2651 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2653 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2655 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2656 sizeof(intel_dp
->dpcd
)) == 0)
2657 return false; /* aux transfer failed */
2659 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2660 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2661 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2663 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2664 return false; /* DPCD not present */
2666 /* Check if the panel supports PSR */
2667 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
2668 intel_dp_aux_native_read_retry(intel_dp
, DP_PSR_SUPPORT
,
2670 sizeof(intel_dp
->psr_dpcd
));
2671 if (is_edp_psr(intel_dp
))
2672 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2673 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2674 DP_DWN_STRM_PORT_PRESENT
))
2675 return true; /* native DP sink */
2677 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2678 return true; /* no per-port downstream info */
2680 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2681 intel_dp
->downstream_ports
,
2682 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2683 return false; /* downstream port status fetch failed */
2689 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2693 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2696 ironlake_edp_panel_vdd_on(intel_dp
);
2698 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2699 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2700 buf
[0], buf
[1], buf
[2]);
2702 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2703 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2704 buf
[0], buf
[1], buf
[2]);
2706 ironlake_edp_panel_vdd_off(intel_dp
, false);
2710 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2714 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2715 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2716 sink_irq_vector
, 1);
2724 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2726 /* NAK by default */
2727 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2731 * According to DP spec
2734 * 2. Configure link according to Receiver Capabilities
2735 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2736 * 4. Check link status on receipt of hot-plug interrupt
2740 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2742 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2744 u8 link_status
[DP_LINK_STATUS_SIZE
];
2746 if (!intel_encoder
->connectors_active
)
2749 if (WARN_ON(!intel_encoder
->base
.crtc
))
2752 /* Try to read receiver status if the link appears to be up */
2753 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2754 intel_dp_link_down(intel_dp
);
2758 /* Now read the DPCD to see if it's actually running */
2759 if (!intel_dp_get_dpcd(intel_dp
)) {
2760 intel_dp_link_down(intel_dp
);
2764 /* Try to read the source of the interrupt */
2765 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2766 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2767 /* Clear interrupt source */
2768 intel_dp_aux_native_write_1(intel_dp
,
2769 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2772 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2773 intel_dp_handle_test_request(intel_dp
);
2774 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2775 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2778 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2779 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2780 drm_get_encoder_name(&intel_encoder
->base
));
2781 intel_dp_start_link_train(intel_dp
);
2782 intel_dp_complete_link_train(intel_dp
);
2783 intel_dp_stop_link_train(intel_dp
);
2787 /* XXX this is probably wrong for multiple downstream ports */
2788 static enum drm_connector_status
2789 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2791 uint8_t *dpcd
= intel_dp
->dpcd
;
2795 if (!intel_dp_get_dpcd(intel_dp
))
2796 return connector_status_disconnected
;
2798 /* if there's no downstream port, we're done */
2799 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2800 return connector_status_connected
;
2802 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2803 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2806 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2808 return connector_status_unknown
;
2809 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2810 : connector_status_disconnected
;
2813 /* If no HPD, poke DDC gently */
2814 if (drm_probe_ddc(&intel_dp
->adapter
))
2815 return connector_status_connected
;
2817 /* Well we tried, say unknown for unreliable port types */
2818 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2819 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2820 return connector_status_unknown
;
2822 /* Anything else is out of spec, warn and ignore */
2823 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2824 return connector_status_disconnected
;
2827 static enum drm_connector_status
2828 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2830 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2832 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2833 enum drm_connector_status status
;
2835 /* Can't disconnect eDP, but you can close the lid... */
2836 if (is_edp(intel_dp
)) {
2837 status
= intel_panel_detect(dev
);
2838 if (status
== connector_status_unknown
)
2839 status
= connector_status_connected
;
2843 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
2844 return connector_status_disconnected
;
2846 return intel_dp_detect_dpcd(intel_dp
);
2849 static enum drm_connector_status
2850 g4x_dp_detect(struct intel_dp
*intel_dp
)
2852 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2854 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2857 /* Can't disconnect eDP, but you can close the lid... */
2858 if (is_edp(intel_dp
)) {
2859 enum drm_connector_status status
;
2861 status
= intel_panel_detect(dev
);
2862 if (status
== connector_status_unknown
)
2863 status
= connector_status_connected
;
2867 switch (intel_dig_port
->port
) {
2869 bit
= PORTB_HOTPLUG_LIVE_STATUS
;
2872 bit
= PORTC_HOTPLUG_LIVE_STATUS
;
2875 bit
= PORTD_HOTPLUG_LIVE_STATUS
;
2878 return connector_status_unknown
;
2881 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2882 return connector_status_disconnected
;
2884 return intel_dp_detect_dpcd(intel_dp
);
2887 static struct edid
*
2888 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2890 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2892 /* use cached edid if we have one */
2893 if (intel_connector
->edid
) {
2898 if (IS_ERR(intel_connector
->edid
))
2901 size
= (intel_connector
->edid
->extensions
+ 1) * EDID_LENGTH
;
2902 edid
= kmemdup(intel_connector
->edid
, size
, GFP_KERNEL
);
2909 return drm_get_edid(connector
, adapter
);
2913 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2915 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2917 /* use cached edid if we have one */
2918 if (intel_connector
->edid
) {
2920 if (IS_ERR(intel_connector
->edid
))
2923 return intel_connector_update_modes(connector
,
2924 intel_connector
->edid
);
2927 return intel_ddc_get_modes(connector
, adapter
);
2930 static enum drm_connector_status
2931 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2933 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2934 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2935 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2936 struct drm_device
*dev
= connector
->dev
;
2937 enum drm_connector_status status
;
2938 struct edid
*edid
= NULL
;
2940 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2941 connector
->base
.id
, drm_get_connector_name(connector
));
2943 intel_dp
->has_audio
= false;
2945 if (HAS_PCH_SPLIT(dev
))
2946 status
= ironlake_dp_detect(intel_dp
);
2948 status
= g4x_dp_detect(intel_dp
);
2950 if (status
!= connector_status_connected
)
2953 intel_dp_probe_oui(intel_dp
);
2955 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2956 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2958 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2960 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2965 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
2966 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2967 return connector_status_connected
;
2970 static int intel_dp_get_modes(struct drm_connector
*connector
)
2972 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2973 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2974 struct drm_device
*dev
= connector
->dev
;
2977 /* We should parse the EDID data and find out if it has an audio sink
2980 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2984 /* if eDP has no EDID, fall back to fixed mode */
2985 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2986 struct drm_display_mode
*mode
;
2987 mode
= drm_mode_duplicate(dev
,
2988 intel_connector
->panel
.fixed_mode
);
2990 drm_mode_probed_add(connector
, mode
);
2998 intel_dp_detect_audio(struct drm_connector
*connector
)
3000 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3002 bool has_audio
= false;
3004 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
3006 has_audio
= drm_detect_monitor_audio(edid
);
3014 intel_dp_set_property(struct drm_connector
*connector
,
3015 struct drm_property
*property
,
3018 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3019 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3020 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3021 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3024 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3028 if (property
== dev_priv
->force_audio_property
) {
3032 if (i
== intel_dp
->force_audio
)
3035 intel_dp
->force_audio
= i
;
3037 if (i
== HDMI_AUDIO_AUTO
)
3038 has_audio
= intel_dp_detect_audio(connector
);
3040 has_audio
= (i
== HDMI_AUDIO_ON
);
3042 if (has_audio
== intel_dp
->has_audio
)
3045 intel_dp
->has_audio
= has_audio
;
3049 if (property
== dev_priv
->broadcast_rgb_property
) {
3050 bool old_auto
= intel_dp
->color_range_auto
;
3051 uint32_t old_range
= intel_dp
->color_range
;
3054 case INTEL_BROADCAST_RGB_AUTO
:
3055 intel_dp
->color_range_auto
= true;
3057 case INTEL_BROADCAST_RGB_FULL
:
3058 intel_dp
->color_range_auto
= false;
3059 intel_dp
->color_range
= 0;
3061 case INTEL_BROADCAST_RGB_LIMITED
:
3062 intel_dp
->color_range_auto
= false;
3063 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3069 if (old_auto
== intel_dp
->color_range_auto
&&
3070 old_range
== intel_dp
->color_range
)
3076 if (is_edp(intel_dp
) &&
3077 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3078 if (val
== DRM_MODE_SCALE_NONE
) {
3079 DRM_DEBUG_KMS("no scaling not supported\n");
3083 if (intel_connector
->panel
.fitting_mode
== val
) {
3084 /* the eDP scaling property is not changed */
3087 intel_connector
->panel
.fitting_mode
= val
;
3095 if (intel_encoder
->base
.crtc
)
3096 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3102 intel_dp_connector_destroy(struct drm_connector
*connector
)
3104 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3106 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3107 kfree(intel_connector
->edid
);
3109 /* Can't call is_edp() since the encoder may have been destroyed
3111 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3112 intel_panel_fini(&intel_connector
->panel
);
3114 drm_sysfs_connector_remove(connector
);
3115 drm_connector_cleanup(connector
);
3119 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3121 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3122 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3123 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3125 i2c_del_adapter(&intel_dp
->adapter
);
3126 drm_encoder_cleanup(encoder
);
3127 if (is_edp(intel_dp
)) {
3128 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3129 mutex_lock(&dev
->mode_config
.mutex
);
3130 ironlake_panel_vdd_off_sync(intel_dp
);
3131 mutex_unlock(&dev
->mode_config
.mutex
);
3133 kfree(intel_dig_port
);
3136 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
3137 .dpms
= intel_connector_dpms
,
3138 .detect
= intel_dp_detect
,
3139 .fill_modes
= drm_helper_probe_single_connector_modes
,
3140 .set_property
= intel_dp_set_property
,
3141 .destroy
= intel_dp_connector_destroy
,
3144 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
3145 .get_modes
= intel_dp_get_modes
,
3146 .mode_valid
= intel_dp_mode_valid
,
3147 .best_encoder
= intel_best_encoder
,
3150 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
3151 .destroy
= intel_dp_encoder_destroy
,
3155 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
3157 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3159 intel_dp_check_link_status(intel_dp
);
3162 /* Return which DP Port should be selected for Transcoder DP control */
3164 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
3166 struct drm_device
*dev
= crtc
->dev
;
3167 struct intel_encoder
*intel_encoder
;
3168 struct intel_dp
*intel_dp
;
3170 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3171 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3173 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
3174 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
3175 return intel_dp
->output_reg
;
3181 /* check the VBT to see whether the eDP is on DP-D port */
3182 bool intel_dpd_is_edp(struct drm_device
*dev
)
3184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3185 struct child_device_config
*p_child
;
3188 if (!dev_priv
->vbt
.child_dev_num
)
3191 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
3192 p_child
= dev_priv
->vbt
.child_dev
+ i
;
3194 if (p_child
->dvo_port
== PORT_IDPD
&&
3195 p_child
->device_type
== DEVICE_TYPE_eDP
)
3202 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
3204 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3206 intel_attach_force_audio_property(connector
);
3207 intel_attach_broadcast_rgb_property(connector
);
3208 intel_dp
->color_range_auto
= true;
3210 if (is_edp(intel_dp
)) {
3211 drm_mode_create_scaling_mode_property(connector
->dev
);
3212 drm_object_attach_property(
3214 connector
->dev
->mode_config
.scaling_mode_property
,
3215 DRM_MODE_SCALE_ASPECT
);
3216 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
3221 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
3222 struct intel_dp
*intel_dp
,
3223 struct edp_power_seq
*out
)
3225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3226 struct edp_power_seq cur
, vbt
, spec
, final
;
3227 u32 pp_on
, pp_off
, pp_div
, pp
;
3228 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
3230 if (HAS_PCH_SPLIT(dev
)) {
3231 pp_ctrl_reg
= PCH_PP_CONTROL
;
3232 pp_on_reg
= PCH_PP_ON_DELAYS
;
3233 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3234 pp_div_reg
= PCH_PP_DIVISOR
;
3236 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3238 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
3239 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3240 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3241 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3244 /* Workaround: Need to write PP_CONTROL with the unlock key as
3245 * the very first thing. */
3246 pp
= ironlake_get_pp_control(intel_dp
);
3247 I915_WRITE(pp_ctrl_reg
, pp
);
3249 pp_on
= I915_READ(pp_on_reg
);
3250 pp_off
= I915_READ(pp_off_reg
);
3251 pp_div
= I915_READ(pp_div_reg
);
3253 /* Pull timing values out of registers */
3254 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
3255 PANEL_POWER_UP_DELAY_SHIFT
;
3257 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
3258 PANEL_LIGHT_ON_DELAY_SHIFT
;
3260 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
3261 PANEL_LIGHT_OFF_DELAY_SHIFT
;
3263 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
3264 PANEL_POWER_DOWN_DELAY_SHIFT
;
3266 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
3267 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
3269 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3270 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
3272 vbt
= dev_priv
->vbt
.edp_pps
;
3274 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3275 * our hw here, which are all in 100usec. */
3276 spec
.t1_t3
= 210 * 10;
3277 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
3278 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
3279 spec
.t10
= 500 * 10;
3280 /* This one is special and actually in units of 100ms, but zero
3281 * based in the hw (so we need to add 100 ms). But the sw vbt
3282 * table multiplies it with 1000 to make it in units of 100usec,
3284 spec
.t11_t12
= (510 + 100) * 10;
3286 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3287 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
3289 /* Use the max of the register settings and vbt. If both are
3290 * unset, fall back to the spec limits. */
3291 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3293 max(cur.field, vbt.field))
3294 assign_final(t1_t3
);
3298 assign_final(t11_t12
);
3301 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3302 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
3303 intel_dp
->backlight_on_delay
= get_delay(t8
);
3304 intel_dp
->backlight_off_delay
= get_delay(t9
);
3305 intel_dp
->panel_power_down_delay
= get_delay(t10
);
3306 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
3309 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3310 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
3311 intel_dp
->panel_power_cycle_delay
);
3313 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3314 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
3321 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
3322 struct intel_dp
*intel_dp
,
3323 struct edp_power_seq
*seq
)
3325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3326 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
3327 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
3328 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
3330 if (HAS_PCH_SPLIT(dev
)) {
3331 pp_on_reg
= PCH_PP_ON_DELAYS
;
3332 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3333 pp_div_reg
= PCH_PP_DIVISOR
;
3335 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3337 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3338 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3339 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3342 /* And finally store the new values in the power sequencer. */
3343 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
3344 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
3345 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
3346 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
3347 /* Compute the divisor for the pp clock, simply match the Bspec
3349 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
3350 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
3351 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
3353 /* Haswell doesn't have any port selection bits for the panel
3354 * power sequencer any more. */
3355 if (IS_VALLEYVIEW(dev
)) {
3356 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
3357 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
3359 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
3360 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
3361 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
3362 port_sel
= PANEL_PORT_SELECT_DPA
;
3364 port_sel
= PANEL_PORT_SELECT_DPD
;
3369 I915_WRITE(pp_on_reg
, pp_on
);
3370 I915_WRITE(pp_off_reg
, pp_off
);
3371 I915_WRITE(pp_div_reg
, pp_div
);
3373 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3374 I915_READ(pp_on_reg
),
3375 I915_READ(pp_off_reg
),
3376 I915_READ(pp_div_reg
));
3379 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
3380 struct intel_connector
*intel_connector
)
3382 struct drm_connector
*connector
= &intel_connector
->base
;
3383 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3384 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3386 struct drm_display_mode
*fixed_mode
= NULL
;
3387 struct edp_power_seq power_seq
= { 0 };
3389 struct drm_display_mode
*scan
;
3392 if (!is_edp(intel_dp
))
3395 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
3397 /* Cache DPCD and EDID for edp. */
3398 ironlake_edp_panel_vdd_on(intel_dp
);
3399 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
3400 ironlake_edp_panel_vdd_off(intel_dp
, false);
3403 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3404 dev_priv
->no_aux_handshake
=
3405 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3406 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3408 /* if this fails, presume the device is a ghost */
3409 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3413 /* We now know it's not a ghost, init power sequence regs. */
3414 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
3417 ironlake_edp_panel_vdd_on(intel_dp
);
3418 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
3420 if (drm_add_edid_modes(connector
, edid
)) {
3421 drm_mode_connector_update_edid_property(connector
,
3423 drm_edid_to_eld(connector
, edid
);
3426 edid
= ERR_PTR(-EINVAL
);
3429 edid
= ERR_PTR(-ENOENT
);
3431 intel_connector
->edid
= edid
;
3433 /* prefer fixed mode from EDID if available */
3434 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
3435 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
3436 fixed_mode
= drm_mode_duplicate(dev
, scan
);
3441 /* fallback to VBT if available for eDP */
3442 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
3443 fixed_mode
= drm_mode_duplicate(dev
,
3444 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
3446 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
3449 ironlake_edp_panel_vdd_off(intel_dp
, false);
3451 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
3452 intel_panel_setup_backlight(connector
);
3458 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
3459 struct intel_connector
*intel_connector
)
3461 struct drm_connector
*connector
= &intel_connector
->base
;
3462 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3463 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3464 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3466 enum port port
= intel_dig_port
->port
;
3467 const char *name
= NULL
;
3470 /* Preserve the current hw state. */
3471 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
3472 intel_dp
->attached_connector
= intel_connector
;
3474 type
= DRM_MODE_CONNECTOR_DisplayPort
;
3476 * FIXME : We need to initialize built-in panels before external panels.
3477 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3481 type
= DRM_MODE_CONNECTOR_eDP
;
3484 if (IS_VALLEYVIEW(dev
))
3485 type
= DRM_MODE_CONNECTOR_eDP
;
3488 if (HAS_PCH_SPLIT(dev
) && intel_dpd_is_edp(dev
))
3489 type
= DRM_MODE_CONNECTOR_eDP
;
3491 default: /* silence GCC warning */
3496 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3497 * for DP the encoder type can be set by the caller to
3498 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3500 if (type
== DRM_MODE_CONNECTOR_eDP
)
3501 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
3503 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3504 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
3507 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
3508 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
3510 connector
->interlace_allowed
= true;
3511 connector
->doublescan_allowed
= 0;
3513 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
3514 ironlake_panel_vdd_work
);
3516 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3517 drm_sysfs_connector_add(connector
);
3520 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3522 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3524 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
3526 switch (intel_dig_port
->port
) {
3528 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
3531 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
3534 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
3537 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
3544 /* Set up the DDC bus. */
3547 intel_encoder
->hpd_pin
= HPD_PORT_A
;
3551 intel_encoder
->hpd_pin
= HPD_PORT_B
;
3555 intel_encoder
->hpd_pin
= HPD_PORT_C
;
3559 intel_encoder
->hpd_pin
= HPD_PORT_D
;
3566 error
= intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
3567 WARN(error
, "intel_dp_i2c_init failed with error %d for port %c\n",
3568 error
, port_name(port
));
3570 intel_dp
->psr_setup_done
= false;
3572 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
3573 i2c_del_adapter(&intel_dp
->adapter
);
3574 if (is_edp(intel_dp
)) {
3575 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3576 mutex_lock(&dev
->mode_config
.mutex
);
3577 ironlake_panel_vdd_off_sync(intel_dp
);
3578 mutex_unlock(&dev
->mode_config
.mutex
);
3580 drm_sysfs_connector_remove(connector
);
3581 drm_connector_cleanup(connector
);
3585 intel_dp_add_properties(intel_dp
, connector
);
3587 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3588 * 0xd. Failure to do so will result in spurious interrupts being
3589 * generated on the port when a cable is not attached.
3591 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
3592 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
3593 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
3600 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
3602 struct intel_digital_port
*intel_dig_port
;
3603 struct intel_encoder
*intel_encoder
;
3604 struct drm_encoder
*encoder
;
3605 struct intel_connector
*intel_connector
;
3607 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
3608 if (!intel_dig_port
)
3611 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
3612 if (!intel_connector
) {
3613 kfree(intel_dig_port
);
3617 intel_encoder
= &intel_dig_port
->base
;
3618 encoder
= &intel_encoder
->base
;
3620 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
3621 DRM_MODE_ENCODER_TMDS
);
3623 intel_encoder
->compute_config
= intel_dp_compute_config
;
3624 intel_encoder
->mode_set
= intel_dp_mode_set
;
3625 intel_encoder
->disable
= intel_disable_dp
;
3626 intel_encoder
->post_disable
= intel_post_disable_dp
;
3627 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
3628 intel_encoder
->get_config
= intel_dp_get_config
;
3629 if (IS_VALLEYVIEW(dev
)) {
3630 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
3631 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
3632 intel_encoder
->enable
= vlv_enable_dp
;
3634 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
3635 intel_encoder
->enable
= g4x_enable_dp
;
3638 intel_dig_port
->port
= port
;
3639 intel_dig_port
->dp
.output_reg
= output_reg
;
3641 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3642 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3643 intel_encoder
->cloneable
= false;
3644 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
3646 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
3647 drm_encoder_cleanup(encoder
);
3648 kfree(intel_dig_port
);
3649 kfree(intel_connector
);