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drm/i915: clarify IBX dp workaround
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "drm_crtc_helper.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "drm_dp_helper.h"
39
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44 #define DP_LINK_CONFIGURATION_SIZE 9
45
46 struct intel_dp {
47 struct intel_encoder base;
48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
51 bool has_audio;
52 enum hdmi_force_audio force_audio;
53 uint32_t color_range;
54 int dpms_mode;
55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
60 bool is_pch_edp;
61 uint8_t train_set[4];
62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
68 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
70 };
71
72 /**
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
75 *
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
78 */
79 static bool is_edp(struct intel_dp *intel_dp)
80 {
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
82 }
83
84 /**
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
87 *
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
91 */
92 static bool is_pch_edp(struct intel_dp *intel_dp)
93 {
94 return intel_dp->is_pch_edp;
95 }
96
97 /**
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
100 *
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 */
103 static bool is_cpu_edp(struct intel_dp *intel_dp)
104 {
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
106 }
107
108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
109 {
110 return container_of(encoder, struct intel_dp, base.base);
111 }
112
113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
114 {
115 return container_of(intel_attached_encoder(connector),
116 struct intel_dp, base);
117 }
118
119 /**
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
122 *
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
125 */
126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
127 {
128 struct intel_dp *intel_dp;
129
130 if (!encoder)
131 return false;
132
133 intel_dp = enc_to_intel_dp(encoder);
134
135 return is_pch_edp(intel_dp);
136 }
137
138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
140 static void intel_dp_link_down(struct intel_dp *intel_dp);
141
142 void
143 intel_edp_link_config(struct intel_encoder *intel_encoder,
144 int *lane_num, int *link_bw)
145 {
146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
147
148 *lane_num = intel_dp->lane_count;
149 if (intel_dp->link_bw == DP_LINK_BW_1_62)
150 *link_bw = 162000;
151 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
152 *link_bw = 270000;
153 }
154
155 static int
156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
157 {
158 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
159 switch (max_lane_count) {
160 case 1: case 2: case 4:
161 break;
162 default:
163 max_lane_count = 4;
164 }
165 return max_lane_count;
166 }
167
168 static int
169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
170 {
171 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
172
173 switch (max_link_bw) {
174 case DP_LINK_BW_1_62:
175 case DP_LINK_BW_2_7:
176 break;
177 default:
178 max_link_bw = DP_LINK_BW_1_62;
179 break;
180 }
181 return max_link_bw;
182 }
183
184 static int
185 intel_dp_link_clock(uint8_t link_bw)
186 {
187 if (link_bw == DP_LINK_BW_2_7)
188 return 270000;
189 else
190 return 162000;
191 }
192
193 /*
194 * The units on the numbers in the next two are... bizarre. Examples will
195 * make it clearer; this one parallels an example in the eDP spec.
196 *
197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
198 *
199 * 270000 * 1 * 8 / 10 == 216000
200 *
201 * The actual data capacity of that configuration is 2.16Gbit/s, so the
202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
204 * 119000. At 18bpp that's 2142000 kilobits per second.
205 *
206 * Thus the strange-looking division by 10 in intel_dp_link_required, to
207 * get the result in decakilobits instead of kilobits.
208 */
209
210 static int
211 intel_dp_link_required(int pixel_clock, int bpp)
212 {
213 return (pixel_clock * bpp + 9) / 10;
214 }
215
216 static int
217 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
218 {
219 return (max_link_clock * max_lanes * 8) / 10;
220 }
221
222 static bool
223 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
224 struct drm_display_mode *mode,
225 struct drm_display_mode *adjusted_mode)
226 {
227 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
228 int max_lanes = intel_dp_max_lane_count(intel_dp);
229 int max_rate, mode_rate;
230
231 mode_rate = intel_dp_link_required(mode->clock, 24);
232 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
233
234 if (mode_rate > max_rate) {
235 mode_rate = intel_dp_link_required(mode->clock, 18);
236 if (mode_rate > max_rate)
237 return false;
238
239 if (adjusted_mode)
240 adjusted_mode->private_flags
241 |= INTEL_MODE_DP_FORCE_6BPC;
242
243 return true;
244 }
245
246 return true;
247 }
248
249 static int
250 intel_dp_mode_valid(struct drm_connector *connector,
251 struct drm_display_mode *mode)
252 {
253 struct intel_dp *intel_dp = intel_attached_dp(connector);
254
255 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
256 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
257 return MODE_PANEL;
258
259 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
260 return MODE_PANEL;
261 }
262
263 if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
264 return MODE_CLOCK_HIGH;
265
266 if (mode->clock < 10000)
267 return MODE_CLOCK_LOW;
268
269 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
270 return MODE_H_ILLEGAL;
271
272 return MODE_OK;
273 }
274
275 static uint32_t
276 pack_aux(uint8_t *src, int src_bytes)
277 {
278 int i;
279 uint32_t v = 0;
280
281 if (src_bytes > 4)
282 src_bytes = 4;
283 for (i = 0; i < src_bytes; i++)
284 v |= ((uint32_t) src[i]) << ((3-i) * 8);
285 return v;
286 }
287
288 static void
289 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
290 {
291 int i;
292 if (dst_bytes > 4)
293 dst_bytes = 4;
294 for (i = 0; i < dst_bytes; i++)
295 dst[i] = src >> ((3-i) * 8);
296 }
297
298 /* hrawclock is 1/4 the FSB frequency */
299 static int
300 intel_hrawclk(struct drm_device *dev)
301 {
302 struct drm_i915_private *dev_priv = dev->dev_private;
303 uint32_t clkcfg;
304
305 clkcfg = I915_READ(CLKCFG);
306 switch (clkcfg & CLKCFG_FSB_MASK) {
307 case CLKCFG_FSB_400:
308 return 100;
309 case CLKCFG_FSB_533:
310 return 133;
311 case CLKCFG_FSB_667:
312 return 166;
313 case CLKCFG_FSB_800:
314 return 200;
315 case CLKCFG_FSB_1067:
316 return 266;
317 case CLKCFG_FSB_1333:
318 return 333;
319 /* these two are just a guess; one of them might be right */
320 case CLKCFG_FSB_1600:
321 case CLKCFG_FSB_1600_ALT:
322 return 400;
323 default:
324 return 133;
325 }
326 }
327
328 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
329 {
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
332
333 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
334 }
335
336 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
337 {
338 struct drm_device *dev = intel_dp->base.base.dev;
339 struct drm_i915_private *dev_priv = dev->dev_private;
340
341 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
342 }
343
344 static void
345 intel_dp_check_edp(struct intel_dp *intel_dp)
346 {
347 struct drm_device *dev = intel_dp->base.base.dev;
348 struct drm_i915_private *dev_priv = dev->dev_private;
349
350 if (!is_edp(intel_dp))
351 return;
352 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
353 WARN(1, "eDP powered off while attempting aux channel communication.\n");
354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
355 I915_READ(PCH_PP_STATUS),
356 I915_READ(PCH_PP_CONTROL));
357 }
358 }
359
360 static int
361 intel_dp_aux_ch(struct intel_dp *intel_dp,
362 uint8_t *send, int send_bytes,
363 uint8_t *recv, int recv_size)
364 {
365 uint32_t output_reg = intel_dp->output_reg;
366 struct drm_device *dev = intel_dp->base.base.dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368 uint32_t ch_ctl = output_reg + 0x10;
369 uint32_t ch_data = ch_ctl + 4;
370 int i;
371 int recv_bytes;
372 uint32_t status;
373 uint32_t aux_clock_divider;
374 int try, precharge = 5;
375
376 intel_dp_check_edp(intel_dp);
377 /* The clock divider is based off the hrawclk,
378 * and would like to run at 2MHz. So, take the
379 * hrawclk value and divide by 2 and use that
380 *
381 * Note that PCH attached eDP panels should use a 125MHz input
382 * clock divider.
383 */
384 if (is_cpu_edp(intel_dp)) {
385 if (IS_GEN6(dev) || IS_GEN7(dev))
386 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
387 else
388 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
389 } else if (HAS_PCH_SPLIT(dev))
390 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
391 else
392 aux_clock_divider = intel_hrawclk(dev) / 2;
393
394 /* Try to wait for any previous AUX channel activity */
395 for (try = 0; try < 3; try++) {
396 status = I915_READ(ch_ctl);
397 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
398 break;
399 msleep(1);
400 }
401
402 if (try == 3) {
403 WARN(1, "dp_aux_ch not started status 0x%08x\n",
404 I915_READ(ch_ctl));
405 return -EBUSY;
406 }
407
408 /* Must try at least 3 times according to DP spec */
409 for (try = 0; try < 5; try++) {
410 /* Load the send data into the aux channel data registers */
411 for (i = 0; i < send_bytes; i += 4)
412 I915_WRITE(ch_data + i,
413 pack_aux(send + i, send_bytes - i));
414
415 /* Send the command and wait for it to complete */
416 I915_WRITE(ch_ctl,
417 DP_AUX_CH_CTL_SEND_BUSY |
418 DP_AUX_CH_CTL_TIME_OUT_400us |
419 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
420 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
421 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
422 DP_AUX_CH_CTL_DONE |
423 DP_AUX_CH_CTL_TIME_OUT_ERROR |
424 DP_AUX_CH_CTL_RECEIVE_ERROR);
425 for (;;) {
426 status = I915_READ(ch_ctl);
427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
428 break;
429 udelay(100);
430 }
431
432 /* Clear done status and any errors */
433 I915_WRITE(ch_ctl,
434 status |
435 DP_AUX_CH_CTL_DONE |
436 DP_AUX_CH_CTL_TIME_OUT_ERROR |
437 DP_AUX_CH_CTL_RECEIVE_ERROR);
438
439 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
440 DP_AUX_CH_CTL_RECEIVE_ERROR))
441 continue;
442 if (status & DP_AUX_CH_CTL_DONE)
443 break;
444 }
445
446 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
447 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
448 return -EBUSY;
449 }
450
451 /* Check for timeout or receive error.
452 * Timeouts occur when the sink is not connected
453 */
454 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
455 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
456 return -EIO;
457 }
458
459 /* Timeouts occur when the device isn't connected, so they're
460 * "normal" -- don't fill the kernel log with these */
461 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
462 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
463 return -ETIMEDOUT;
464 }
465
466 /* Unload any bytes sent back from the other side */
467 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
468 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
469 if (recv_bytes > recv_size)
470 recv_bytes = recv_size;
471
472 for (i = 0; i < recv_bytes; i += 4)
473 unpack_aux(I915_READ(ch_data + i),
474 recv + i, recv_bytes - i);
475
476 return recv_bytes;
477 }
478
479 /* Write data to the aux channel in native mode */
480 static int
481 intel_dp_aux_native_write(struct intel_dp *intel_dp,
482 uint16_t address, uint8_t *send, int send_bytes)
483 {
484 int ret;
485 uint8_t msg[20];
486 int msg_bytes;
487 uint8_t ack;
488
489 intel_dp_check_edp(intel_dp);
490 if (send_bytes > 16)
491 return -1;
492 msg[0] = AUX_NATIVE_WRITE << 4;
493 msg[1] = address >> 8;
494 msg[2] = address & 0xff;
495 msg[3] = send_bytes - 1;
496 memcpy(&msg[4], send, send_bytes);
497 msg_bytes = send_bytes + 4;
498 for (;;) {
499 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
500 if (ret < 0)
501 return ret;
502 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
503 break;
504 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
505 udelay(100);
506 else
507 return -EIO;
508 }
509 return send_bytes;
510 }
511
512 /* Write a single byte to the aux channel in native mode */
513 static int
514 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
515 uint16_t address, uint8_t byte)
516 {
517 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
518 }
519
520 /* read bytes from a native aux channel */
521 static int
522 intel_dp_aux_native_read(struct intel_dp *intel_dp,
523 uint16_t address, uint8_t *recv, int recv_bytes)
524 {
525 uint8_t msg[4];
526 int msg_bytes;
527 uint8_t reply[20];
528 int reply_bytes;
529 uint8_t ack;
530 int ret;
531
532 intel_dp_check_edp(intel_dp);
533 msg[0] = AUX_NATIVE_READ << 4;
534 msg[1] = address >> 8;
535 msg[2] = address & 0xff;
536 msg[3] = recv_bytes - 1;
537
538 msg_bytes = 4;
539 reply_bytes = recv_bytes + 1;
540
541 for (;;) {
542 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
543 reply, reply_bytes);
544 if (ret == 0)
545 return -EPROTO;
546 if (ret < 0)
547 return ret;
548 ack = reply[0];
549 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
550 memcpy(recv, reply + 1, ret - 1);
551 return ret - 1;
552 }
553 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
554 udelay(100);
555 else
556 return -EIO;
557 }
558 }
559
560 static int
561 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
562 uint8_t write_byte, uint8_t *read_byte)
563 {
564 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
565 struct intel_dp *intel_dp = container_of(adapter,
566 struct intel_dp,
567 adapter);
568 uint16_t address = algo_data->address;
569 uint8_t msg[5];
570 uint8_t reply[2];
571 unsigned retry;
572 int msg_bytes;
573 int reply_bytes;
574 int ret;
575
576 intel_dp_check_edp(intel_dp);
577 /* Set up the command byte */
578 if (mode & MODE_I2C_READ)
579 msg[0] = AUX_I2C_READ << 4;
580 else
581 msg[0] = AUX_I2C_WRITE << 4;
582
583 if (!(mode & MODE_I2C_STOP))
584 msg[0] |= AUX_I2C_MOT << 4;
585
586 msg[1] = address >> 8;
587 msg[2] = address;
588
589 switch (mode) {
590 case MODE_I2C_WRITE:
591 msg[3] = 0;
592 msg[4] = write_byte;
593 msg_bytes = 5;
594 reply_bytes = 1;
595 break;
596 case MODE_I2C_READ:
597 msg[3] = 0;
598 msg_bytes = 4;
599 reply_bytes = 2;
600 break;
601 default:
602 msg_bytes = 3;
603 reply_bytes = 1;
604 break;
605 }
606
607 for (retry = 0; retry < 5; retry++) {
608 ret = intel_dp_aux_ch(intel_dp,
609 msg, msg_bytes,
610 reply, reply_bytes);
611 if (ret < 0) {
612 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
613 return ret;
614 }
615
616 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
617 case AUX_NATIVE_REPLY_ACK:
618 /* I2C-over-AUX Reply field is only valid
619 * when paired with AUX ACK.
620 */
621 break;
622 case AUX_NATIVE_REPLY_NACK:
623 DRM_DEBUG_KMS("aux_ch native nack\n");
624 return -EREMOTEIO;
625 case AUX_NATIVE_REPLY_DEFER:
626 udelay(100);
627 continue;
628 default:
629 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
630 reply[0]);
631 return -EREMOTEIO;
632 }
633
634 switch (reply[0] & AUX_I2C_REPLY_MASK) {
635 case AUX_I2C_REPLY_ACK:
636 if (mode == MODE_I2C_READ) {
637 *read_byte = reply[1];
638 }
639 return reply_bytes - 1;
640 case AUX_I2C_REPLY_NACK:
641 DRM_DEBUG_KMS("aux_i2c nack\n");
642 return -EREMOTEIO;
643 case AUX_I2C_REPLY_DEFER:
644 DRM_DEBUG_KMS("aux_i2c defer\n");
645 udelay(100);
646 break;
647 default:
648 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
649 return -EREMOTEIO;
650 }
651 }
652
653 DRM_ERROR("too many retries, giving up\n");
654 return -EREMOTEIO;
655 }
656
657 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
658 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
659
660 static int
661 intel_dp_i2c_init(struct intel_dp *intel_dp,
662 struct intel_connector *intel_connector, const char *name)
663 {
664 int ret;
665
666 DRM_DEBUG_KMS("i2c_init %s\n", name);
667 intel_dp->algo.running = false;
668 intel_dp->algo.address = 0;
669 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
670
671 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
672 intel_dp->adapter.owner = THIS_MODULE;
673 intel_dp->adapter.class = I2C_CLASS_DDC;
674 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
675 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
676 intel_dp->adapter.algo_data = &intel_dp->algo;
677 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
678
679 ironlake_edp_panel_vdd_on(intel_dp);
680 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
681 ironlake_edp_panel_vdd_off(intel_dp, false);
682 return ret;
683 }
684
685 static bool
686 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
687 struct drm_display_mode *adjusted_mode)
688 {
689 struct drm_device *dev = encoder->dev;
690 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
691 int lane_count, clock;
692 int max_lane_count = intel_dp_max_lane_count(intel_dp);
693 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
694 int bpp, mode_rate;
695 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
696
697 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
698 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
699 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
700 mode, adjusted_mode);
701 /*
702 * the mode->clock is used to calculate the Data&Link M/N
703 * of the pipe. For the eDP the fixed clock should be used.
704 */
705 mode->clock = intel_dp->panel_fixed_mode->clock;
706 }
707
708 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
709 return false;
710
711 DRM_DEBUG_KMS("DP link computation with max lane count %i "
712 "max bw %02x pixel clock %iKHz\n",
713 max_lane_count, bws[max_clock], mode->clock);
714
715 if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
716 return false;
717
718 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
719 mode_rate = intel_dp_link_required(mode->clock, bpp);
720
721 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
722 for (clock = 0; clock <= max_clock; clock++) {
723 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
724
725 if (mode_rate <= link_avail) {
726 intel_dp->link_bw = bws[clock];
727 intel_dp->lane_count = lane_count;
728 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
729 DRM_DEBUG_KMS("DP link bw %02x lane "
730 "count %d clock %d bpp %d\n",
731 intel_dp->link_bw, intel_dp->lane_count,
732 adjusted_mode->clock, bpp);
733 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
734 mode_rate, link_avail);
735 return true;
736 }
737 }
738 }
739
740 return false;
741 }
742
743 struct intel_dp_m_n {
744 uint32_t tu;
745 uint32_t gmch_m;
746 uint32_t gmch_n;
747 uint32_t link_m;
748 uint32_t link_n;
749 };
750
751 static void
752 intel_reduce_ratio(uint32_t *num, uint32_t *den)
753 {
754 while (*num > 0xffffff || *den > 0xffffff) {
755 *num >>= 1;
756 *den >>= 1;
757 }
758 }
759
760 static void
761 intel_dp_compute_m_n(int bpp,
762 int nlanes,
763 int pixel_clock,
764 int link_clock,
765 struct intel_dp_m_n *m_n)
766 {
767 m_n->tu = 64;
768 m_n->gmch_m = (pixel_clock * bpp) >> 3;
769 m_n->gmch_n = link_clock * nlanes;
770 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
771 m_n->link_m = pixel_clock;
772 m_n->link_n = link_clock;
773 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
774 }
775
776 void
777 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
778 struct drm_display_mode *adjusted_mode)
779 {
780 struct drm_device *dev = crtc->dev;
781 struct drm_mode_config *mode_config = &dev->mode_config;
782 struct drm_encoder *encoder;
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
785 int lane_count = 4;
786 struct intel_dp_m_n m_n;
787 int pipe = intel_crtc->pipe;
788
789 /*
790 * Find the lane count in the intel_encoder private
791 */
792 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
793 struct intel_dp *intel_dp;
794
795 if (encoder->crtc != crtc)
796 continue;
797
798 intel_dp = enc_to_intel_dp(encoder);
799 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
800 intel_dp->base.type == INTEL_OUTPUT_EDP)
801 {
802 lane_count = intel_dp->lane_count;
803 break;
804 }
805 }
806
807 /*
808 * Compute the GMCH and Link ratios. The '3' here is
809 * the number of bytes_per_pixel post-LUT, which we always
810 * set up for 8-bits of R/G/B, or 3 bytes total.
811 */
812 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
813 mode->clock, adjusted_mode->clock, &m_n);
814
815 if (HAS_PCH_SPLIT(dev)) {
816 I915_WRITE(TRANSDATA_M1(pipe),
817 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
818 m_n.gmch_m);
819 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
820 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
821 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
822 } else {
823 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
824 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
825 m_n.gmch_m);
826 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
827 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
828 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
829 }
830 }
831
832 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
833 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
834
835 static void
836 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
837 struct drm_display_mode *adjusted_mode)
838 {
839 struct drm_device *dev = encoder->dev;
840 struct drm_i915_private *dev_priv = dev->dev_private;
841 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
842 struct drm_crtc *crtc = intel_dp->base.base.crtc;
843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
844
845 /* Turn on the eDP PLL if needed */
846 if (is_edp(intel_dp)) {
847 if (!is_pch_edp(intel_dp))
848 ironlake_edp_pll_on(encoder);
849 else
850 ironlake_edp_pll_off(encoder);
851 }
852
853 /*
854 * There are four kinds of DP registers:
855 *
856 * IBX PCH
857 * SNB CPU
858 * IVB CPU
859 * CPT PCH
860 *
861 * IBX PCH and CPU are the same for almost everything,
862 * except that the CPU DP PLL is configured in this
863 * register
864 *
865 * CPT PCH is quite different, having many bits moved
866 * to the TRANS_DP_CTL register instead. That
867 * configuration happens (oddly) in ironlake_pch_enable
868 */
869
870 /* Preserve the BIOS-computed detected bit. This is
871 * supposed to be read-only.
872 */
873 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
874 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
875
876 /* Handle DP bits in common between all three register formats */
877
878 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
879
880 switch (intel_dp->lane_count) {
881 case 1:
882 intel_dp->DP |= DP_PORT_WIDTH_1;
883 break;
884 case 2:
885 intel_dp->DP |= DP_PORT_WIDTH_2;
886 break;
887 case 4:
888 intel_dp->DP |= DP_PORT_WIDTH_4;
889 break;
890 }
891 if (intel_dp->has_audio) {
892 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
893 pipe_name(intel_crtc->pipe));
894 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
895 intel_write_eld(encoder, adjusted_mode);
896 }
897 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
898 intel_dp->link_configuration[0] = intel_dp->link_bw;
899 intel_dp->link_configuration[1] = intel_dp->lane_count;
900 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
901 /*
902 * Check for DPCD version > 1.1 and enhanced framing support
903 */
904 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
905 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
906 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
907 }
908
909 /* Split out the IBX/CPU vs CPT settings */
910
911 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
912 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
913 intel_dp->DP |= DP_SYNC_HS_HIGH;
914 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
915 intel_dp->DP |= DP_SYNC_VS_HIGH;
916 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
917
918 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
919 intel_dp->DP |= DP_ENHANCED_FRAMING;
920
921 intel_dp->DP |= intel_crtc->pipe << 29;
922
923 /* don't miss out required setting for eDP */
924 intel_dp->DP |= DP_PLL_ENABLE;
925 if (adjusted_mode->clock < 200000)
926 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
927 else
928 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
929 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
930 intel_dp->DP |= intel_dp->color_range;
931
932 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
933 intel_dp->DP |= DP_SYNC_HS_HIGH;
934 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
935 intel_dp->DP |= DP_SYNC_VS_HIGH;
936 intel_dp->DP |= DP_LINK_TRAIN_OFF;
937
938 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
939 intel_dp->DP |= DP_ENHANCED_FRAMING;
940
941 if (intel_crtc->pipe == 1)
942 intel_dp->DP |= DP_PIPEB_SELECT;
943
944 if (is_cpu_edp(intel_dp)) {
945 /* don't miss out required setting for eDP */
946 intel_dp->DP |= DP_PLL_ENABLE;
947 if (adjusted_mode->clock < 200000)
948 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
949 else
950 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
951 }
952 } else {
953 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
954 }
955 }
956
957 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
958 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
959
960 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
961 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
962
963 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
964 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
965
966 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
967 u32 mask,
968 u32 value)
969 {
970 struct drm_device *dev = intel_dp->base.base.dev;
971 struct drm_i915_private *dev_priv = dev->dev_private;
972
973 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
974 mask, value,
975 I915_READ(PCH_PP_STATUS),
976 I915_READ(PCH_PP_CONTROL));
977
978 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
979 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
980 I915_READ(PCH_PP_STATUS),
981 I915_READ(PCH_PP_CONTROL));
982 }
983 }
984
985 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
986 {
987 DRM_DEBUG_KMS("Wait for panel power on\n");
988 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
989 }
990
991 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
992 {
993 DRM_DEBUG_KMS("Wait for panel power off time\n");
994 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
995 }
996
997 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
998 {
999 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1000 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1001 }
1002
1003
1004 /* Read the current pp_control value, unlocking the register if it
1005 * is locked
1006 */
1007
1008 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1009 {
1010 u32 control = I915_READ(PCH_PP_CONTROL);
1011
1012 control &= ~PANEL_UNLOCK_MASK;
1013 control |= PANEL_UNLOCK_REGS;
1014 return control;
1015 }
1016
1017 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1018 {
1019 struct drm_device *dev = intel_dp->base.base.dev;
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 u32 pp;
1022
1023 if (!is_edp(intel_dp))
1024 return;
1025 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1026
1027 WARN(intel_dp->want_panel_vdd,
1028 "eDP VDD already requested on\n");
1029
1030 intel_dp->want_panel_vdd = true;
1031
1032 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1033 DRM_DEBUG_KMS("eDP VDD already on\n");
1034 return;
1035 }
1036
1037 if (!ironlake_edp_have_panel_power(intel_dp))
1038 ironlake_wait_panel_power_cycle(intel_dp);
1039
1040 pp = ironlake_get_pp_control(dev_priv);
1041 pp |= EDP_FORCE_VDD;
1042 I915_WRITE(PCH_PP_CONTROL, pp);
1043 POSTING_READ(PCH_PP_CONTROL);
1044 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1045 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1046
1047 /*
1048 * If the panel wasn't on, delay before accessing aux channel
1049 */
1050 if (!ironlake_edp_have_panel_power(intel_dp)) {
1051 DRM_DEBUG_KMS("eDP was not running\n");
1052 msleep(intel_dp->panel_power_up_delay);
1053 }
1054 }
1055
1056 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1057 {
1058 struct drm_device *dev = intel_dp->base.base.dev;
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 u32 pp;
1061
1062 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1063 pp = ironlake_get_pp_control(dev_priv);
1064 pp &= ~EDP_FORCE_VDD;
1065 I915_WRITE(PCH_PP_CONTROL, pp);
1066 POSTING_READ(PCH_PP_CONTROL);
1067
1068 /* Make sure sequencer is idle before allowing subsequent activity */
1069 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1070 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1071
1072 msleep(intel_dp->panel_power_down_delay);
1073 }
1074 }
1075
1076 static void ironlake_panel_vdd_work(struct work_struct *__work)
1077 {
1078 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1079 struct intel_dp, panel_vdd_work);
1080 struct drm_device *dev = intel_dp->base.base.dev;
1081
1082 mutex_lock(&dev->mode_config.mutex);
1083 ironlake_panel_vdd_off_sync(intel_dp);
1084 mutex_unlock(&dev->mode_config.mutex);
1085 }
1086
1087 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1088 {
1089 if (!is_edp(intel_dp))
1090 return;
1091
1092 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1093 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1094
1095 intel_dp->want_panel_vdd = false;
1096
1097 if (sync) {
1098 ironlake_panel_vdd_off_sync(intel_dp);
1099 } else {
1100 /*
1101 * Queue the timer to fire a long
1102 * time from now (relative to the power down delay)
1103 * to keep the panel power up across a sequence of operations
1104 */
1105 schedule_delayed_work(&intel_dp->panel_vdd_work,
1106 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1107 }
1108 }
1109
1110 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1111 {
1112 struct drm_device *dev = intel_dp->base.base.dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1114 u32 pp;
1115
1116 if (!is_edp(intel_dp))
1117 return;
1118
1119 DRM_DEBUG_KMS("Turn eDP power on\n");
1120
1121 if (ironlake_edp_have_panel_power(intel_dp)) {
1122 DRM_DEBUG_KMS("eDP power already on\n");
1123 return;
1124 }
1125
1126 ironlake_wait_panel_power_cycle(intel_dp);
1127
1128 pp = ironlake_get_pp_control(dev_priv);
1129 if (IS_GEN5(dev)) {
1130 /* ILK workaround: disable reset around power sequence */
1131 pp &= ~PANEL_POWER_RESET;
1132 I915_WRITE(PCH_PP_CONTROL, pp);
1133 POSTING_READ(PCH_PP_CONTROL);
1134 }
1135
1136 pp |= POWER_TARGET_ON;
1137 if (!IS_GEN5(dev))
1138 pp |= PANEL_POWER_RESET;
1139
1140 I915_WRITE(PCH_PP_CONTROL, pp);
1141 POSTING_READ(PCH_PP_CONTROL);
1142
1143 ironlake_wait_panel_on(intel_dp);
1144
1145 if (IS_GEN5(dev)) {
1146 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1147 I915_WRITE(PCH_PP_CONTROL, pp);
1148 POSTING_READ(PCH_PP_CONTROL);
1149 }
1150 }
1151
1152 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1153 {
1154 struct drm_device *dev = intel_dp->base.base.dev;
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 pp;
1157
1158 if (!is_edp(intel_dp))
1159 return;
1160
1161 DRM_DEBUG_KMS("Turn eDP power off\n");
1162
1163 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1164
1165 pp = ironlake_get_pp_control(dev_priv);
1166 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1167 I915_WRITE(PCH_PP_CONTROL, pp);
1168 POSTING_READ(PCH_PP_CONTROL);
1169
1170 ironlake_wait_panel_off(intel_dp);
1171 }
1172
1173 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1174 {
1175 struct drm_device *dev = intel_dp->base.base.dev;
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 u32 pp;
1178
1179 if (!is_edp(intel_dp))
1180 return;
1181
1182 DRM_DEBUG_KMS("\n");
1183 /*
1184 * If we enable the backlight right away following a panel power
1185 * on, we may see slight flicker as the panel syncs with the eDP
1186 * link. So delay a bit to make sure the image is solid before
1187 * allowing it to appear.
1188 */
1189 msleep(intel_dp->backlight_on_delay);
1190 pp = ironlake_get_pp_control(dev_priv);
1191 pp |= EDP_BLC_ENABLE;
1192 I915_WRITE(PCH_PP_CONTROL, pp);
1193 POSTING_READ(PCH_PP_CONTROL);
1194 }
1195
1196 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1197 {
1198 struct drm_device *dev = intel_dp->base.base.dev;
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200 u32 pp;
1201
1202 if (!is_edp(intel_dp))
1203 return;
1204
1205 DRM_DEBUG_KMS("\n");
1206 pp = ironlake_get_pp_control(dev_priv);
1207 pp &= ~EDP_BLC_ENABLE;
1208 I915_WRITE(PCH_PP_CONTROL, pp);
1209 POSTING_READ(PCH_PP_CONTROL);
1210 msleep(intel_dp->backlight_off_delay);
1211 }
1212
1213 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1214 {
1215 struct drm_device *dev = encoder->dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 u32 dpa_ctl;
1218
1219 DRM_DEBUG_KMS("\n");
1220 dpa_ctl = I915_READ(DP_A);
1221 dpa_ctl |= DP_PLL_ENABLE;
1222 I915_WRITE(DP_A, dpa_ctl);
1223 POSTING_READ(DP_A);
1224 udelay(200);
1225 }
1226
1227 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1228 {
1229 struct drm_device *dev = encoder->dev;
1230 struct drm_i915_private *dev_priv = dev->dev_private;
1231 u32 dpa_ctl;
1232
1233 dpa_ctl = I915_READ(DP_A);
1234 dpa_ctl &= ~DP_PLL_ENABLE;
1235 I915_WRITE(DP_A, dpa_ctl);
1236 POSTING_READ(DP_A);
1237 udelay(200);
1238 }
1239
1240 /* If the sink supports it, try to set the power state appropriately */
1241 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1242 {
1243 int ret, i;
1244
1245 /* Should have a valid DPCD by this point */
1246 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1247 return;
1248
1249 if (mode != DRM_MODE_DPMS_ON) {
1250 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1251 DP_SET_POWER_D3);
1252 if (ret != 1)
1253 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1254 } else {
1255 /*
1256 * When turning on, we need to retry for 1ms to give the sink
1257 * time to wake up.
1258 */
1259 for (i = 0; i < 3; i++) {
1260 ret = intel_dp_aux_native_write_1(intel_dp,
1261 DP_SET_POWER,
1262 DP_SET_POWER_D0);
1263 if (ret == 1)
1264 break;
1265 msleep(1);
1266 }
1267 }
1268 }
1269
1270 static void intel_dp_prepare(struct drm_encoder *encoder)
1271 {
1272 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1273
1274
1275 /* Make sure the panel is off before trying to change the mode. But also
1276 * ensure that we have vdd while we switch off the panel. */
1277 ironlake_edp_panel_vdd_on(intel_dp);
1278 ironlake_edp_backlight_off(intel_dp);
1279 ironlake_edp_panel_off(intel_dp);
1280
1281 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1282 intel_dp_link_down(intel_dp);
1283 ironlake_edp_panel_vdd_off(intel_dp, false);
1284 }
1285
1286 static void intel_dp_commit(struct drm_encoder *encoder)
1287 {
1288 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1289 struct drm_device *dev = encoder->dev;
1290 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1291
1292 ironlake_edp_panel_vdd_on(intel_dp);
1293 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1294 intel_dp_start_link_train(intel_dp);
1295 ironlake_edp_panel_on(intel_dp);
1296 ironlake_edp_panel_vdd_off(intel_dp, true);
1297 intel_dp_complete_link_train(intel_dp);
1298 ironlake_edp_backlight_on(intel_dp);
1299
1300 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1301
1302 if (HAS_PCH_CPT(dev))
1303 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1304 }
1305
1306 static void
1307 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1308 {
1309 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1310 struct drm_device *dev = encoder->dev;
1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1313
1314 if (mode != DRM_MODE_DPMS_ON) {
1315 /* Switching the panel off requires vdd. */
1316 ironlake_edp_panel_vdd_on(intel_dp);
1317 ironlake_edp_backlight_off(intel_dp);
1318 ironlake_edp_panel_off(intel_dp);
1319
1320 intel_dp_sink_dpms(intel_dp, mode);
1321 intel_dp_link_down(intel_dp);
1322 ironlake_edp_panel_vdd_off(intel_dp, false);
1323
1324 if (is_cpu_edp(intel_dp))
1325 ironlake_edp_pll_off(encoder);
1326 } else {
1327 if (is_cpu_edp(intel_dp))
1328 ironlake_edp_pll_on(encoder);
1329
1330 ironlake_edp_panel_vdd_on(intel_dp);
1331 intel_dp_sink_dpms(intel_dp, mode);
1332 if (!(dp_reg & DP_PORT_EN)) {
1333 intel_dp_start_link_train(intel_dp);
1334 ironlake_edp_panel_on(intel_dp);
1335 ironlake_edp_panel_vdd_off(intel_dp, true);
1336 intel_dp_complete_link_train(intel_dp);
1337 } else
1338 ironlake_edp_panel_vdd_off(intel_dp, false);
1339 ironlake_edp_backlight_on(intel_dp);
1340 }
1341 intel_dp->dpms_mode = mode;
1342 }
1343
1344 /*
1345 * Native read with retry for link status and receiver capability reads for
1346 * cases where the sink may still be asleep.
1347 */
1348 static bool
1349 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1350 uint8_t *recv, int recv_bytes)
1351 {
1352 int ret, i;
1353
1354 /*
1355 * Sinks are *supposed* to come up within 1ms from an off state,
1356 * but we're also supposed to retry 3 times per the spec.
1357 */
1358 for (i = 0; i < 3; i++) {
1359 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1360 recv_bytes);
1361 if (ret == recv_bytes)
1362 return true;
1363 msleep(1);
1364 }
1365
1366 return false;
1367 }
1368
1369 /*
1370 * Fetch AUX CH registers 0x202 - 0x207 which contain
1371 * link status information
1372 */
1373 static bool
1374 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1375 {
1376 return intel_dp_aux_native_read_retry(intel_dp,
1377 DP_LANE0_1_STATUS,
1378 link_status,
1379 DP_LINK_STATUS_SIZE);
1380 }
1381
1382 static uint8_t
1383 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1384 int r)
1385 {
1386 return link_status[r - DP_LANE0_1_STATUS];
1387 }
1388
1389 static uint8_t
1390 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1391 int lane)
1392 {
1393 int s = ((lane & 1) ?
1394 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1395 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1396 uint8_t l = adjust_request[lane>>1];
1397
1398 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1399 }
1400
1401 static uint8_t
1402 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1403 int lane)
1404 {
1405 int s = ((lane & 1) ?
1406 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1407 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1408 uint8_t l = adjust_request[lane>>1];
1409
1410 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1411 }
1412
1413
1414 #if 0
1415 static char *voltage_names[] = {
1416 "0.4V", "0.6V", "0.8V", "1.2V"
1417 };
1418 static char *pre_emph_names[] = {
1419 "0dB", "3.5dB", "6dB", "9.5dB"
1420 };
1421 static char *link_train_names[] = {
1422 "pattern 1", "pattern 2", "idle", "off"
1423 };
1424 #endif
1425
1426 /*
1427 * These are source-specific values; current Intel hardware supports
1428 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1429 */
1430
1431 static uint8_t
1432 intel_dp_voltage_max(struct intel_dp *intel_dp)
1433 {
1434 struct drm_device *dev = intel_dp->base.base.dev;
1435
1436 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1437 return DP_TRAIN_VOLTAGE_SWING_800;
1438 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1439 return DP_TRAIN_VOLTAGE_SWING_1200;
1440 else
1441 return DP_TRAIN_VOLTAGE_SWING_800;
1442 }
1443
1444 static uint8_t
1445 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1446 {
1447 struct drm_device *dev = intel_dp->base.base.dev;
1448
1449 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1450 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1451 case DP_TRAIN_VOLTAGE_SWING_400:
1452 return DP_TRAIN_PRE_EMPHASIS_6;
1453 case DP_TRAIN_VOLTAGE_SWING_600:
1454 case DP_TRAIN_VOLTAGE_SWING_800:
1455 return DP_TRAIN_PRE_EMPHASIS_3_5;
1456 default:
1457 return DP_TRAIN_PRE_EMPHASIS_0;
1458 }
1459 } else {
1460 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1461 case DP_TRAIN_VOLTAGE_SWING_400:
1462 return DP_TRAIN_PRE_EMPHASIS_6;
1463 case DP_TRAIN_VOLTAGE_SWING_600:
1464 return DP_TRAIN_PRE_EMPHASIS_6;
1465 case DP_TRAIN_VOLTAGE_SWING_800:
1466 return DP_TRAIN_PRE_EMPHASIS_3_5;
1467 case DP_TRAIN_VOLTAGE_SWING_1200:
1468 default:
1469 return DP_TRAIN_PRE_EMPHASIS_0;
1470 }
1471 }
1472 }
1473
1474 static void
1475 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1476 {
1477 uint8_t v = 0;
1478 uint8_t p = 0;
1479 int lane;
1480 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1481 uint8_t voltage_max;
1482 uint8_t preemph_max;
1483
1484 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1485 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1486 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1487
1488 if (this_v > v)
1489 v = this_v;
1490 if (this_p > p)
1491 p = this_p;
1492 }
1493
1494 voltage_max = intel_dp_voltage_max(intel_dp);
1495 if (v >= voltage_max)
1496 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1497
1498 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1499 if (p >= preemph_max)
1500 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1501
1502 for (lane = 0; lane < 4; lane++)
1503 intel_dp->train_set[lane] = v | p;
1504 }
1505
1506 static uint32_t
1507 intel_dp_signal_levels(uint8_t train_set)
1508 {
1509 uint32_t signal_levels = 0;
1510
1511 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1512 case DP_TRAIN_VOLTAGE_SWING_400:
1513 default:
1514 signal_levels |= DP_VOLTAGE_0_4;
1515 break;
1516 case DP_TRAIN_VOLTAGE_SWING_600:
1517 signal_levels |= DP_VOLTAGE_0_6;
1518 break;
1519 case DP_TRAIN_VOLTAGE_SWING_800:
1520 signal_levels |= DP_VOLTAGE_0_8;
1521 break;
1522 case DP_TRAIN_VOLTAGE_SWING_1200:
1523 signal_levels |= DP_VOLTAGE_1_2;
1524 break;
1525 }
1526 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1527 case DP_TRAIN_PRE_EMPHASIS_0:
1528 default:
1529 signal_levels |= DP_PRE_EMPHASIS_0;
1530 break;
1531 case DP_TRAIN_PRE_EMPHASIS_3_5:
1532 signal_levels |= DP_PRE_EMPHASIS_3_5;
1533 break;
1534 case DP_TRAIN_PRE_EMPHASIS_6:
1535 signal_levels |= DP_PRE_EMPHASIS_6;
1536 break;
1537 case DP_TRAIN_PRE_EMPHASIS_9_5:
1538 signal_levels |= DP_PRE_EMPHASIS_9_5;
1539 break;
1540 }
1541 return signal_levels;
1542 }
1543
1544 /* Gen6's DP voltage swing and pre-emphasis control */
1545 static uint32_t
1546 intel_gen6_edp_signal_levels(uint8_t train_set)
1547 {
1548 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1549 DP_TRAIN_PRE_EMPHASIS_MASK);
1550 switch (signal_levels) {
1551 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1552 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1553 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1554 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1555 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1556 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1557 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1558 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1559 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1560 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1561 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1562 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1563 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1564 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1565 default:
1566 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1567 "0x%x\n", signal_levels);
1568 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1569 }
1570 }
1571
1572 /* Gen7's DP voltage swing and pre-emphasis control */
1573 static uint32_t
1574 intel_gen7_edp_signal_levels(uint8_t train_set)
1575 {
1576 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1577 DP_TRAIN_PRE_EMPHASIS_MASK);
1578 switch (signal_levels) {
1579 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1580 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1581 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1582 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1583 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1584 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1585
1586 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1587 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1588 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1589 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1590
1591 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1592 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1593 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1595
1596 default:
1597 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1598 "0x%x\n", signal_levels);
1599 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1600 }
1601 }
1602
1603 static uint8_t
1604 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1605 int lane)
1606 {
1607 int s = (lane & 1) * 4;
1608 uint8_t l = link_status[lane>>1];
1609
1610 return (l >> s) & 0xf;
1611 }
1612
1613 /* Check for clock recovery is done on all channels */
1614 static bool
1615 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1616 {
1617 int lane;
1618 uint8_t lane_status;
1619
1620 for (lane = 0; lane < lane_count; lane++) {
1621 lane_status = intel_get_lane_status(link_status, lane);
1622 if ((lane_status & DP_LANE_CR_DONE) == 0)
1623 return false;
1624 }
1625 return true;
1626 }
1627
1628 /* Check to see if channel eq is done on all channels */
1629 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1630 DP_LANE_CHANNEL_EQ_DONE|\
1631 DP_LANE_SYMBOL_LOCKED)
1632 static bool
1633 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1634 {
1635 uint8_t lane_align;
1636 uint8_t lane_status;
1637 int lane;
1638
1639 lane_align = intel_dp_link_status(link_status,
1640 DP_LANE_ALIGN_STATUS_UPDATED);
1641 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1642 return false;
1643 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1644 lane_status = intel_get_lane_status(link_status, lane);
1645 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1646 return false;
1647 }
1648 return true;
1649 }
1650
1651 static bool
1652 intel_dp_set_link_train(struct intel_dp *intel_dp,
1653 uint32_t dp_reg_value,
1654 uint8_t dp_train_pat)
1655 {
1656 struct drm_device *dev = intel_dp->base.base.dev;
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 int ret;
1659
1660 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1661 POSTING_READ(intel_dp->output_reg);
1662
1663 intel_dp_aux_native_write_1(intel_dp,
1664 DP_TRAINING_PATTERN_SET,
1665 dp_train_pat);
1666
1667 ret = intel_dp_aux_native_write(intel_dp,
1668 DP_TRAINING_LANE0_SET,
1669 intel_dp->train_set,
1670 intel_dp->lane_count);
1671 if (ret != intel_dp->lane_count)
1672 return false;
1673
1674 return true;
1675 }
1676
1677 /* Enable corresponding port and start training pattern 1 */
1678 static void
1679 intel_dp_start_link_train(struct intel_dp *intel_dp)
1680 {
1681 struct drm_device *dev = intel_dp->base.base.dev;
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1684 int i;
1685 uint8_t voltage;
1686 bool clock_recovery = false;
1687 int voltage_tries, loop_tries;
1688 u32 reg;
1689 uint32_t DP = intel_dp->DP;
1690
1691 /*
1692 * On CPT we have to enable the port in training pattern 1, which
1693 * will happen below in intel_dp_set_link_train. Otherwise, enable
1694 * the port and wait for it to become active.
1695 */
1696 if (!HAS_PCH_CPT(dev)) {
1697 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1698 POSTING_READ(intel_dp->output_reg);
1699 intel_wait_for_vblank(dev, intel_crtc->pipe);
1700 }
1701
1702 /* Write the link configuration data */
1703 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1704 intel_dp->link_configuration,
1705 DP_LINK_CONFIGURATION_SIZE);
1706
1707 DP |= DP_PORT_EN;
1708
1709 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1710 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1711 else
1712 DP &= ~DP_LINK_TRAIN_MASK;
1713 memset(intel_dp->train_set, 0, 4);
1714 voltage = 0xff;
1715 voltage_tries = 0;
1716 loop_tries = 0;
1717 clock_recovery = false;
1718 for (;;) {
1719 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1720 uint8_t link_status[DP_LINK_STATUS_SIZE];
1721 uint32_t signal_levels;
1722
1723
1724 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1725 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1726 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1727 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1728 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1729 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1730 } else {
1731 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1732 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1733 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1734 }
1735
1736 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1737 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1738 else
1739 reg = DP | DP_LINK_TRAIN_PAT_1;
1740
1741 if (!intel_dp_set_link_train(intel_dp, reg,
1742 DP_TRAINING_PATTERN_1 |
1743 DP_LINK_SCRAMBLING_DISABLE))
1744 break;
1745 /* Set training pattern 1 */
1746
1747 udelay(100);
1748 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1749 DRM_ERROR("failed to get link status\n");
1750 break;
1751 }
1752
1753 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1754 DRM_DEBUG_KMS("clock recovery OK\n");
1755 clock_recovery = true;
1756 break;
1757 }
1758
1759 /* Check to see if we've tried the max voltage */
1760 for (i = 0; i < intel_dp->lane_count; i++)
1761 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1762 break;
1763 if (i == intel_dp->lane_count) {
1764 ++loop_tries;
1765 if (loop_tries == 5) {
1766 DRM_DEBUG_KMS("too many full retries, give up\n");
1767 break;
1768 }
1769 memset(intel_dp->train_set, 0, 4);
1770 voltage_tries = 0;
1771 continue;
1772 }
1773
1774 /* Check to see if we've tried the same voltage 5 times */
1775 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1776 ++voltage_tries;
1777 if (voltage_tries == 5) {
1778 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1779 break;
1780 }
1781 } else
1782 voltage_tries = 0;
1783 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1784
1785 /* Compute new intel_dp->train_set as requested by target */
1786 intel_get_adjust_train(intel_dp, link_status);
1787 }
1788
1789 intel_dp->DP = DP;
1790 }
1791
1792 static void
1793 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1794 {
1795 struct drm_device *dev = intel_dp->base.base.dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 bool channel_eq = false;
1798 int tries, cr_tries;
1799 u32 reg;
1800 uint32_t DP = intel_dp->DP;
1801
1802 /* channel equalization */
1803 tries = 0;
1804 cr_tries = 0;
1805 channel_eq = false;
1806 for (;;) {
1807 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1808 uint32_t signal_levels;
1809 uint8_t link_status[DP_LINK_STATUS_SIZE];
1810
1811 if (cr_tries > 5) {
1812 DRM_ERROR("failed to train DP, aborting\n");
1813 intel_dp_link_down(intel_dp);
1814 break;
1815 }
1816
1817 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1818 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1819 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1820 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1821 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1822 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1823 } else {
1824 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1825 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1826 }
1827
1828 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1829 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1830 else
1831 reg = DP | DP_LINK_TRAIN_PAT_2;
1832
1833 /* channel eq pattern */
1834 if (!intel_dp_set_link_train(intel_dp, reg,
1835 DP_TRAINING_PATTERN_2 |
1836 DP_LINK_SCRAMBLING_DISABLE))
1837 break;
1838
1839 udelay(400);
1840 if (!intel_dp_get_link_status(intel_dp, link_status))
1841 break;
1842
1843 /* Make sure clock is still ok */
1844 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1845 intel_dp_start_link_train(intel_dp);
1846 cr_tries++;
1847 continue;
1848 }
1849
1850 if (intel_channel_eq_ok(intel_dp, link_status)) {
1851 channel_eq = true;
1852 break;
1853 }
1854
1855 /* Try 5 times, then try clock recovery if that fails */
1856 if (tries > 5) {
1857 intel_dp_link_down(intel_dp);
1858 intel_dp_start_link_train(intel_dp);
1859 tries = 0;
1860 cr_tries++;
1861 continue;
1862 }
1863
1864 /* Compute new intel_dp->train_set as requested by target */
1865 intel_get_adjust_train(intel_dp, link_status);
1866 ++tries;
1867 }
1868
1869 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1870 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1871 else
1872 reg = DP | DP_LINK_TRAIN_OFF;
1873
1874 I915_WRITE(intel_dp->output_reg, reg);
1875 POSTING_READ(intel_dp->output_reg);
1876 intel_dp_aux_native_write_1(intel_dp,
1877 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1878 }
1879
1880 static void
1881 intel_dp_link_down(struct intel_dp *intel_dp)
1882 {
1883 struct drm_device *dev = intel_dp->base.base.dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 uint32_t DP = intel_dp->DP;
1886
1887 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1888 return;
1889
1890 DRM_DEBUG_KMS("\n");
1891
1892 if (is_edp(intel_dp)) {
1893 DP &= ~DP_PLL_ENABLE;
1894 I915_WRITE(intel_dp->output_reg, DP);
1895 POSTING_READ(intel_dp->output_reg);
1896 udelay(100);
1897 }
1898
1899 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1900 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1901 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1902 } else {
1903 DP &= ~DP_LINK_TRAIN_MASK;
1904 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1905 }
1906 POSTING_READ(intel_dp->output_reg);
1907
1908 msleep(17);
1909
1910 if (is_edp(intel_dp)) {
1911 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1912 DP |= DP_LINK_TRAIN_OFF_CPT;
1913 else
1914 DP |= DP_LINK_TRAIN_OFF;
1915 }
1916
1917 if (HAS_PCH_IBX(dev) &&
1918 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1919 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1920
1921 /* Hardware workaround: leaving our transcoder select
1922 * set to transcoder B while it's off will prevent the
1923 * corresponding HDMI output on transcoder A.
1924 *
1925 * Combine this with another hardware workaround:
1926 * transcoder select bit can only be cleared while the
1927 * port is enabled.
1928 */
1929 DP &= ~DP_PIPEB_SELECT;
1930 I915_WRITE(intel_dp->output_reg, DP);
1931
1932 /* Changes to enable or select take place the vblank
1933 * after being written.
1934 */
1935 if (crtc == NULL) {
1936 /* We can arrive here never having been attached
1937 * to a CRTC, for instance, due to inheriting
1938 * random state from the BIOS.
1939 *
1940 * If the pipe is not running, play safe and
1941 * wait for the clocks to stabilise before
1942 * continuing.
1943 */
1944 POSTING_READ(intel_dp->output_reg);
1945 msleep(50);
1946 } else
1947 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1948 }
1949
1950 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1951 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1952 POSTING_READ(intel_dp->output_reg);
1953 msleep(intel_dp->panel_power_down_delay);
1954 }
1955
1956 static bool
1957 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1958 {
1959 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1960 sizeof(intel_dp->dpcd)) &&
1961 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1962 return true;
1963 }
1964
1965 return false;
1966 }
1967
1968 static void
1969 intel_dp_probe_oui(struct intel_dp *intel_dp)
1970 {
1971 u8 buf[3];
1972
1973 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1974 return;
1975
1976 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1977 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1978 buf[0], buf[1], buf[2]);
1979
1980 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1981 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1982 buf[0], buf[1], buf[2]);
1983 }
1984
1985 static bool
1986 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1987 {
1988 int ret;
1989
1990 ret = intel_dp_aux_native_read_retry(intel_dp,
1991 DP_DEVICE_SERVICE_IRQ_VECTOR,
1992 sink_irq_vector, 1);
1993 if (!ret)
1994 return false;
1995
1996 return true;
1997 }
1998
1999 static void
2000 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2001 {
2002 /* NAK by default */
2003 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2004 }
2005
2006 /*
2007 * According to DP spec
2008 * 5.1.2:
2009 * 1. Read DPCD
2010 * 2. Configure link according to Receiver Capabilities
2011 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2012 * 4. Check link status on receipt of hot-plug interrupt
2013 */
2014
2015 static void
2016 intel_dp_check_link_status(struct intel_dp *intel_dp)
2017 {
2018 u8 sink_irq_vector;
2019 u8 link_status[DP_LINK_STATUS_SIZE];
2020
2021 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2022 return;
2023
2024 if (!intel_dp->base.base.crtc)
2025 return;
2026
2027 /* Try to read receiver status if the link appears to be up */
2028 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2029 intel_dp_link_down(intel_dp);
2030 return;
2031 }
2032
2033 /* Now read the DPCD to see if it's actually running */
2034 if (!intel_dp_get_dpcd(intel_dp)) {
2035 intel_dp_link_down(intel_dp);
2036 return;
2037 }
2038
2039 /* Try to read the source of the interrupt */
2040 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2041 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2042 /* Clear interrupt source */
2043 intel_dp_aux_native_write_1(intel_dp,
2044 DP_DEVICE_SERVICE_IRQ_VECTOR,
2045 sink_irq_vector);
2046
2047 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2048 intel_dp_handle_test_request(intel_dp);
2049 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2050 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2051 }
2052
2053 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2054 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2055 drm_get_encoder_name(&intel_dp->base.base));
2056 intel_dp_start_link_train(intel_dp);
2057 intel_dp_complete_link_train(intel_dp);
2058 }
2059 }
2060
2061 static enum drm_connector_status
2062 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2063 {
2064 if (intel_dp_get_dpcd(intel_dp))
2065 return connector_status_connected;
2066 return connector_status_disconnected;
2067 }
2068
2069 static enum drm_connector_status
2070 ironlake_dp_detect(struct intel_dp *intel_dp)
2071 {
2072 enum drm_connector_status status;
2073
2074 /* Can't disconnect eDP, but you can close the lid... */
2075 if (is_edp(intel_dp)) {
2076 status = intel_panel_detect(intel_dp->base.base.dev);
2077 if (status == connector_status_unknown)
2078 status = connector_status_connected;
2079 return status;
2080 }
2081
2082 return intel_dp_detect_dpcd(intel_dp);
2083 }
2084
2085 static enum drm_connector_status
2086 g4x_dp_detect(struct intel_dp *intel_dp)
2087 {
2088 struct drm_device *dev = intel_dp->base.base.dev;
2089 struct drm_i915_private *dev_priv = dev->dev_private;
2090 uint32_t bit;
2091
2092 switch (intel_dp->output_reg) {
2093 case DP_B:
2094 bit = DPB_HOTPLUG_LIVE_STATUS;
2095 break;
2096 case DP_C:
2097 bit = DPC_HOTPLUG_LIVE_STATUS;
2098 break;
2099 case DP_D:
2100 bit = DPD_HOTPLUG_LIVE_STATUS;
2101 break;
2102 default:
2103 return connector_status_unknown;
2104 }
2105
2106 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2107 return connector_status_disconnected;
2108
2109 return intel_dp_detect_dpcd(intel_dp);
2110 }
2111
2112 static struct edid *
2113 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2114 {
2115 struct intel_dp *intel_dp = intel_attached_dp(connector);
2116 struct edid *edid;
2117
2118 ironlake_edp_panel_vdd_on(intel_dp);
2119 edid = drm_get_edid(connector, adapter);
2120 ironlake_edp_panel_vdd_off(intel_dp, false);
2121 return edid;
2122 }
2123
2124 static int
2125 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2126 {
2127 struct intel_dp *intel_dp = intel_attached_dp(connector);
2128 int ret;
2129
2130 ironlake_edp_panel_vdd_on(intel_dp);
2131 ret = intel_ddc_get_modes(connector, adapter);
2132 ironlake_edp_panel_vdd_off(intel_dp, false);
2133 return ret;
2134 }
2135
2136
2137 /**
2138 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2139 *
2140 * \return true if DP port is connected.
2141 * \return false if DP port is disconnected.
2142 */
2143 static enum drm_connector_status
2144 intel_dp_detect(struct drm_connector *connector, bool force)
2145 {
2146 struct intel_dp *intel_dp = intel_attached_dp(connector);
2147 struct drm_device *dev = intel_dp->base.base.dev;
2148 enum drm_connector_status status;
2149 struct edid *edid = NULL;
2150
2151 intel_dp->has_audio = false;
2152
2153 if (HAS_PCH_SPLIT(dev))
2154 status = ironlake_dp_detect(intel_dp);
2155 else
2156 status = g4x_dp_detect(intel_dp);
2157
2158 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2159 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2160 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2161 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2162
2163 if (status != connector_status_connected)
2164 return status;
2165
2166 intel_dp_probe_oui(intel_dp);
2167
2168 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2169 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2170 } else {
2171 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2172 if (edid) {
2173 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2174 connector->display_info.raw_edid = NULL;
2175 kfree(edid);
2176 }
2177 }
2178
2179 return connector_status_connected;
2180 }
2181
2182 static int intel_dp_get_modes(struct drm_connector *connector)
2183 {
2184 struct intel_dp *intel_dp = intel_attached_dp(connector);
2185 struct drm_device *dev = intel_dp->base.base.dev;
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 int ret;
2188
2189 /* We should parse the EDID data and find out if it has an audio sink
2190 */
2191
2192 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2193 if (ret) {
2194 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2195 struct drm_display_mode *newmode;
2196 list_for_each_entry(newmode, &connector->probed_modes,
2197 head) {
2198 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2199 intel_dp->panel_fixed_mode =
2200 drm_mode_duplicate(dev, newmode);
2201 break;
2202 }
2203 }
2204 }
2205 return ret;
2206 }
2207
2208 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2209 if (is_edp(intel_dp)) {
2210 /* initialize panel mode from VBT if available for eDP */
2211 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2212 intel_dp->panel_fixed_mode =
2213 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2214 if (intel_dp->panel_fixed_mode) {
2215 intel_dp->panel_fixed_mode->type |=
2216 DRM_MODE_TYPE_PREFERRED;
2217 }
2218 }
2219 if (intel_dp->panel_fixed_mode) {
2220 struct drm_display_mode *mode;
2221 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2222 drm_mode_probed_add(connector, mode);
2223 return 1;
2224 }
2225 }
2226 return 0;
2227 }
2228
2229 static bool
2230 intel_dp_detect_audio(struct drm_connector *connector)
2231 {
2232 struct intel_dp *intel_dp = intel_attached_dp(connector);
2233 struct edid *edid;
2234 bool has_audio = false;
2235
2236 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2237 if (edid) {
2238 has_audio = drm_detect_monitor_audio(edid);
2239
2240 connector->display_info.raw_edid = NULL;
2241 kfree(edid);
2242 }
2243
2244 return has_audio;
2245 }
2246
2247 static int
2248 intel_dp_set_property(struct drm_connector *connector,
2249 struct drm_property *property,
2250 uint64_t val)
2251 {
2252 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2253 struct intel_dp *intel_dp = intel_attached_dp(connector);
2254 int ret;
2255
2256 ret = drm_connector_property_set_value(connector, property, val);
2257 if (ret)
2258 return ret;
2259
2260 if (property == dev_priv->force_audio_property) {
2261 int i = val;
2262 bool has_audio;
2263
2264 if (i == intel_dp->force_audio)
2265 return 0;
2266
2267 intel_dp->force_audio = i;
2268
2269 if (i == HDMI_AUDIO_AUTO)
2270 has_audio = intel_dp_detect_audio(connector);
2271 else
2272 has_audio = (i == HDMI_AUDIO_ON);
2273
2274 if (has_audio == intel_dp->has_audio)
2275 return 0;
2276
2277 intel_dp->has_audio = has_audio;
2278 goto done;
2279 }
2280
2281 if (property == dev_priv->broadcast_rgb_property) {
2282 if (val == !!intel_dp->color_range)
2283 return 0;
2284
2285 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2286 goto done;
2287 }
2288
2289 return -EINVAL;
2290
2291 done:
2292 if (intel_dp->base.base.crtc) {
2293 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2294 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2295 crtc->x, crtc->y,
2296 crtc->fb);
2297 }
2298
2299 return 0;
2300 }
2301
2302 static void
2303 intel_dp_destroy(struct drm_connector *connector)
2304 {
2305 struct drm_device *dev = connector->dev;
2306
2307 if (intel_dpd_is_edp(dev))
2308 intel_panel_destroy_backlight(dev);
2309
2310 drm_sysfs_connector_remove(connector);
2311 drm_connector_cleanup(connector);
2312 kfree(connector);
2313 }
2314
2315 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2316 {
2317 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2318
2319 i2c_del_adapter(&intel_dp->adapter);
2320 drm_encoder_cleanup(encoder);
2321 if (is_edp(intel_dp)) {
2322 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2323 ironlake_panel_vdd_off_sync(intel_dp);
2324 }
2325 kfree(intel_dp);
2326 }
2327
2328 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2329 .dpms = intel_dp_dpms,
2330 .mode_fixup = intel_dp_mode_fixup,
2331 .prepare = intel_dp_prepare,
2332 .mode_set = intel_dp_mode_set,
2333 .commit = intel_dp_commit,
2334 };
2335
2336 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2337 .dpms = drm_helper_connector_dpms,
2338 .detect = intel_dp_detect,
2339 .fill_modes = drm_helper_probe_single_connector_modes,
2340 .set_property = intel_dp_set_property,
2341 .destroy = intel_dp_destroy,
2342 };
2343
2344 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2345 .get_modes = intel_dp_get_modes,
2346 .mode_valid = intel_dp_mode_valid,
2347 .best_encoder = intel_best_encoder,
2348 };
2349
2350 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2351 .destroy = intel_dp_encoder_destroy,
2352 };
2353
2354 static void
2355 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2356 {
2357 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2358
2359 intel_dp_check_link_status(intel_dp);
2360 }
2361
2362 /* Return which DP Port should be selected for Transcoder DP control */
2363 int
2364 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2365 {
2366 struct drm_device *dev = crtc->dev;
2367 struct drm_mode_config *mode_config = &dev->mode_config;
2368 struct drm_encoder *encoder;
2369
2370 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2371 struct intel_dp *intel_dp;
2372
2373 if (encoder->crtc != crtc)
2374 continue;
2375
2376 intel_dp = enc_to_intel_dp(encoder);
2377 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2378 intel_dp->base.type == INTEL_OUTPUT_EDP)
2379 return intel_dp->output_reg;
2380 }
2381
2382 return -1;
2383 }
2384
2385 /* check the VBT to see whether the eDP is on DP-D port */
2386 bool intel_dpd_is_edp(struct drm_device *dev)
2387 {
2388 struct drm_i915_private *dev_priv = dev->dev_private;
2389 struct child_device_config *p_child;
2390 int i;
2391
2392 if (!dev_priv->child_dev_num)
2393 return false;
2394
2395 for (i = 0; i < dev_priv->child_dev_num; i++) {
2396 p_child = dev_priv->child_dev + i;
2397
2398 if (p_child->dvo_port == PORT_IDPD &&
2399 p_child->device_type == DEVICE_TYPE_eDP)
2400 return true;
2401 }
2402 return false;
2403 }
2404
2405 static void
2406 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2407 {
2408 intel_attach_force_audio_property(connector);
2409 intel_attach_broadcast_rgb_property(connector);
2410 }
2411
2412 void
2413 intel_dp_init(struct drm_device *dev, int output_reg)
2414 {
2415 struct drm_i915_private *dev_priv = dev->dev_private;
2416 struct drm_connector *connector;
2417 struct intel_dp *intel_dp;
2418 struct intel_encoder *intel_encoder;
2419 struct intel_connector *intel_connector;
2420 const char *name = NULL;
2421 int type;
2422
2423 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2424 if (!intel_dp)
2425 return;
2426
2427 intel_dp->output_reg = output_reg;
2428 intel_dp->dpms_mode = -1;
2429
2430 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2431 if (!intel_connector) {
2432 kfree(intel_dp);
2433 return;
2434 }
2435 intel_encoder = &intel_dp->base;
2436
2437 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2438 if (intel_dpd_is_edp(dev))
2439 intel_dp->is_pch_edp = true;
2440
2441 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2442 type = DRM_MODE_CONNECTOR_eDP;
2443 intel_encoder->type = INTEL_OUTPUT_EDP;
2444 } else {
2445 type = DRM_MODE_CONNECTOR_DisplayPort;
2446 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2447 }
2448
2449 connector = &intel_connector->base;
2450 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2451 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2452
2453 connector->polled = DRM_CONNECTOR_POLL_HPD;
2454
2455 if (output_reg == DP_B || output_reg == PCH_DP_B)
2456 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2457 else if (output_reg == DP_C || output_reg == PCH_DP_C)
2458 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2459 else if (output_reg == DP_D || output_reg == PCH_DP_D)
2460 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2461
2462 if (is_edp(intel_dp)) {
2463 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2464 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2465 ironlake_panel_vdd_work);
2466 }
2467
2468 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2469
2470 connector->interlace_allowed = true;
2471 connector->doublescan_allowed = 0;
2472
2473 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2474 DRM_MODE_ENCODER_TMDS);
2475 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2476
2477 intel_connector_attach_encoder(intel_connector, intel_encoder);
2478 drm_sysfs_connector_add(connector);
2479
2480 /* Set up the DDC bus. */
2481 switch (output_reg) {
2482 case DP_A:
2483 name = "DPDDC-A";
2484 break;
2485 case DP_B:
2486 case PCH_DP_B:
2487 dev_priv->hotplug_supported_mask |=
2488 DPB_HOTPLUG_INT_STATUS;
2489 name = "DPDDC-B";
2490 break;
2491 case DP_C:
2492 case PCH_DP_C:
2493 dev_priv->hotplug_supported_mask |=
2494 DPC_HOTPLUG_INT_STATUS;
2495 name = "DPDDC-C";
2496 break;
2497 case DP_D:
2498 case PCH_DP_D:
2499 dev_priv->hotplug_supported_mask |=
2500 DPD_HOTPLUG_INT_STATUS;
2501 name = "DPDDC-D";
2502 break;
2503 }
2504
2505 /* Cache some DPCD data in the eDP case */
2506 if (is_edp(intel_dp)) {
2507 bool ret;
2508 struct edp_power_seq cur, vbt;
2509 u32 pp_on, pp_off, pp_div;
2510
2511 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2512 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2513 pp_div = I915_READ(PCH_PP_DIVISOR);
2514
2515 if (!pp_on || !pp_off || !pp_div) {
2516 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2517 intel_dp_encoder_destroy(&intel_dp->base.base);
2518 intel_dp_destroy(&intel_connector->base);
2519 return;
2520 }
2521
2522 /* Pull timing values out of registers */
2523 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2524 PANEL_POWER_UP_DELAY_SHIFT;
2525
2526 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2527 PANEL_LIGHT_ON_DELAY_SHIFT;
2528
2529 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2530 PANEL_LIGHT_OFF_DELAY_SHIFT;
2531
2532 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2533 PANEL_POWER_DOWN_DELAY_SHIFT;
2534
2535 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2536 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2537
2538 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2539 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2540
2541 vbt = dev_priv->edp.pps;
2542
2543 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2544 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2545
2546 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2547
2548 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2549 intel_dp->backlight_on_delay = get_delay(t8);
2550 intel_dp->backlight_off_delay = get_delay(t9);
2551 intel_dp->panel_power_down_delay = get_delay(t10);
2552 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2553
2554 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2555 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2556 intel_dp->panel_power_cycle_delay);
2557
2558 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2559 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2560
2561 ironlake_edp_panel_vdd_on(intel_dp);
2562 ret = intel_dp_get_dpcd(intel_dp);
2563 ironlake_edp_panel_vdd_off(intel_dp, false);
2564
2565 if (ret) {
2566 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2567 dev_priv->no_aux_handshake =
2568 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2569 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2570 } else {
2571 /* if this fails, presume the device is a ghost */
2572 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2573 intel_dp_encoder_destroy(&intel_dp->base.base);
2574 intel_dp_destroy(&intel_connector->base);
2575 return;
2576 }
2577 }
2578
2579 intel_dp_i2c_init(intel_dp, intel_connector, name);
2580
2581 intel_encoder->hot_plug = intel_dp_hot_plug;
2582
2583 if (is_edp(intel_dp)) {
2584 dev_priv->int_edp_connector = connector;
2585 intel_panel_setup_backlight(dev);
2586 }
2587
2588 intel_dp_add_properties(intel_dp, connector);
2589
2590 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2591 * 0xd. Failure to do so will result in spurious interrupts being
2592 * generated on the port when a cable is not attached.
2593 */
2594 if (IS_G4X(dev) && !IS_GM45(dev)) {
2595 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2596 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2597 }
2598 }
Linux kernel - Deliverables
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