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ASoC: wm8997: Add inputs for noise and mic mixers
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
56 {
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
60 }
61
62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63 {
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
65 }
66
67 static void intel_dp_link_down(struct intel_dp *intel_dp);
68
69 static int
70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
71 {
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 default:
79 max_link_bw = DP_LINK_BW_1_62;
80 break;
81 }
82 return max_link_bw;
83 }
84
85 /*
86 * The units on the numbers in the next two are... bizarre. Examples will
87 * make it clearer; this one parallels an example in the eDP spec.
88 *
89 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
90 *
91 * 270000 * 1 * 8 / 10 == 216000
92 *
93 * The actual data capacity of that configuration is 2.16Gbit/s, so the
94 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
95 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
96 * 119000. At 18bpp that's 2142000 kilobits per second.
97 *
98 * Thus the strange-looking division by 10 in intel_dp_link_required, to
99 * get the result in decakilobits instead of kilobits.
100 */
101
102 static int
103 intel_dp_link_required(int pixel_clock, int bpp)
104 {
105 return (pixel_clock * bpp + 9) / 10;
106 }
107
108 static int
109 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
110 {
111 return (max_link_clock * max_lanes * 8) / 10;
112 }
113
114 static int
115 intel_dp_mode_valid(struct drm_connector *connector,
116 struct drm_display_mode *mode)
117 {
118 struct intel_dp *intel_dp = intel_attached_dp(connector);
119 struct intel_connector *intel_connector = to_intel_connector(connector);
120 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
121 int target_clock = mode->clock;
122 int max_rate, mode_rate, max_lanes, max_link_clock;
123
124 if (is_edp(intel_dp) && fixed_mode) {
125 if (mode->hdisplay > fixed_mode->hdisplay)
126 return MODE_PANEL;
127
128 if (mode->vdisplay > fixed_mode->vdisplay)
129 return MODE_PANEL;
130
131 target_clock = fixed_mode->clock;
132 }
133
134 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
135 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
136
137 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
138 mode_rate = intel_dp_link_required(target_clock, 18);
139
140 if (mode_rate > max_rate)
141 return MODE_CLOCK_HIGH;
142
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
145
146 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
147 return MODE_H_ILLEGAL;
148
149 return MODE_OK;
150 }
151
152 static uint32_t
153 pack_aux(uint8_t *src, int src_bytes)
154 {
155 int i;
156 uint32_t v = 0;
157
158 if (src_bytes > 4)
159 src_bytes = 4;
160 for (i = 0; i < src_bytes; i++)
161 v |= ((uint32_t) src[i]) << ((3-i) * 8);
162 return v;
163 }
164
165 static void
166 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
167 {
168 int i;
169 if (dst_bytes > 4)
170 dst_bytes = 4;
171 for (i = 0; i < dst_bytes; i++)
172 dst[i] = src >> ((3-i) * 8);
173 }
174
175 /* hrawclock is 1/4 the FSB frequency */
176 static int
177 intel_hrawclk(struct drm_device *dev)
178 {
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 uint32_t clkcfg;
181
182 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
183 if (IS_VALLEYVIEW(dev))
184 return 200;
185
186 clkcfg = I915_READ(CLKCFG);
187 switch (clkcfg & CLKCFG_FSB_MASK) {
188 case CLKCFG_FSB_400:
189 return 100;
190 case CLKCFG_FSB_533:
191 return 133;
192 case CLKCFG_FSB_667:
193 return 166;
194 case CLKCFG_FSB_800:
195 return 200;
196 case CLKCFG_FSB_1067:
197 return 266;
198 case CLKCFG_FSB_1333:
199 return 333;
200 /* these two are just a guess; one of them might be right */
201 case CLKCFG_FSB_1600:
202 case CLKCFG_FSB_1600_ALT:
203 return 400;
204 default:
205 return 133;
206 }
207 }
208
209 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
210 {
211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
212 struct drm_i915_private *dev_priv = dev->dev_private;
213 u32 pp_stat_reg;
214
215 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
216 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
217 }
218
219 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
220 {
221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 u32 pp_ctrl_reg;
224
225 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
226 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
227 }
228
229 static void
230 intel_dp_check_edp(struct intel_dp *intel_dp)
231 {
232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
233 struct drm_i915_private *dev_priv = dev->dev_private;
234 u32 pp_stat_reg, pp_ctrl_reg;
235
236 if (!is_edp(intel_dp))
237 return;
238
239 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
240 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
241
242 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
243 WARN(1, "eDP powered off while attempting aux channel communication.\n");
244 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
245 I915_READ(pp_stat_reg),
246 I915_READ(pp_ctrl_reg));
247 }
248 }
249
250 static uint32_t
251 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
252 {
253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
257 uint32_t status;
258 bool done;
259
260 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
261 if (has_aux_irq)
262 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
263 msecs_to_jiffies_timeout(10));
264 else
265 done = wait_for_atomic(C, 10) == 0;
266 if (!done)
267 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
268 has_aux_irq);
269 #undef C
270
271 return status;
272 }
273
274 static int
275 intel_dp_aux_ch(struct intel_dp *intel_dp,
276 uint8_t *send, int send_bytes,
277 uint8_t *recv, int recv_size)
278 {
279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
280 struct drm_device *dev = intel_dig_port->base.base.dev;
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
283 uint32_t ch_data = ch_ctl + 4;
284 int i, ret, recv_bytes;
285 uint32_t status;
286 uint32_t aux_clock_divider;
287 int try, precharge;
288 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
289
290 /* dp aux is extremely sensitive to irq latency, hence request the
291 * lowest possible wakeup latency and so prevent the cpu from going into
292 * deep sleep states.
293 */
294 pm_qos_update_request(&dev_priv->pm_qos, 0);
295
296 intel_dp_check_edp(intel_dp);
297 /* The clock divider is based off the hrawclk,
298 * and would like to run at 2MHz. So, take the
299 * hrawclk value and divide by 2 and use that
300 *
301 * Note that PCH attached eDP panels should use a 125MHz input
302 * clock divider.
303 */
304 if (IS_VALLEYVIEW(dev)) {
305 aux_clock_divider = 100;
306 } else if (intel_dig_port->port == PORT_A) {
307 if (HAS_DDI(dev))
308 aux_clock_divider = DIV_ROUND_CLOSEST(
309 intel_ddi_get_cdclk_freq(dev_priv), 2000);
310 else if (IS_GEN6(dev) || IS_GEN7(dev))
311 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
312 else
313 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
314 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
315 /* Workaround for non-ULT HSW */
316 aux_clock_divider = 74;
317 } else if (HAS_PCH_SPLIT(dev)) {
318 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
319 } else {
320 aux_clock_divider = intel_hrawclk(dev) / 2;
321 }
322
323 if (IS_GEN6(dev))
324 precharge = 3;
325 else
326 precharge = 5;
327
328 /* Try to wait for any previous AUX channel activity */
329 for (try = 0; try < 3; try++) {
330 status = I915_READ_NOTRACE(ch_ctl);
331 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
332 break;
333 msleep(1);
334 }
335
336 if (try == 3) {
337 WARN(1, "dp_aux_ch not started status 0x%08x\n",
338 I915_READ(ch_ctl));
339 ret = -EBUSY;
340 goto out;
341 }
342
343 /* Must try at least 3 times according to DP spec */
344 for (try = 0; try < 5; try++) {
345 /* Load the send data into the aux channel data registers */
346 for (i = 0; i < send_bytes; i += 4)
347 I915_WRITE(ch_data + i,
348 pack_aux(send + i, send_bytes - i));
349
350 /* Send the command and wait for it to complete */
351 I915_WRITE(ch_ctl,
352 DP_AUX_CH_CTL_SEND_BUSY |
353 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
354 DP_AUX_CH_CTL_TIME_OUT_400us |
355 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
356 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
357 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
358 DP_AUX_CH_CTL_DONE |
359 DP_AUX_CH_CTL_TIME_OUT_ERROR |
360 DP_AUX_CH_CTL_RECEIVE_ERROR);
361
362 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
363
364 /* Clear done status and any errors */
365 I915_WRITE(ch_ctl,
366 status |
367 DP_AUX_CH_CTL_DONE |
368 DP_AUX_CH_CTL_TIME_OUT_ERROR |
369 DP_AUX_CH_CTL_RECEIVE_ERROR);
370
371 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
372 DP_AUX_CH_CTL_RECEIVE_ERROR))
373 continue;
374 if (status & DP_AUX_CH_CTL_DONE)
375 break;
376 }
377
378 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
379 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
380 ret = -EBUSY;
381 goto out;
382 }
383
384 /* Check for timeout or receive error.
385 * Timeouts occur when the sink is not connected
386 */
387 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
388 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
389 ret = -EIO;
390 goto out;
391 }
392
393 /* Timeouts occur when the device isn't connected, so they're
394 * "normal" -- don't fill the kernel log with these */
395 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
396 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
397 ret = -ETIMEDOUT;
398 goto out;
399 }
400
401 /* Unload any bytes sent back from the other side */
402 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
403 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
404 if (recv_bytes > recv_size)
405 recv_bytes = recv_size;
406
407 for (i = 0; i < recv_bytes; i += 4)
408 unpack_aux(I915_READ(ch_data + i),
409 recv + i, recv_bytes - i);
410
411 ret = recv_bytes;
412 out:
413 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
414
415 return ret;
416 }
417
418 /* Write data to the aux channel in native mode */
419 static int
420 intel_dp_aux_native_write(struct intel_dp *intel_dp,
421 uint16_t address, uint8_t *send, int send_bytes)
422 {
423 int ret;
424 uint8_t msg[20];
425 int msg_bytes;
426 uint8_t ack;
427
428 intel_dp_check_edp(intel_dp);
429 if (send_bytes > 16)
430 return -1;
431 msg[0] = AUX_NATIVE_WRITE << 4;
432 msg[1] = address >> 8;
433 msg[2] = address & 0xff;
434 msg[3] = send_bytes - 1;
435 memcpy(&msg[4], send, send_bytes);
436 msg_bytes = send_bytes + 4;
437 for (;;) {
438 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
439 if (ret < 0)
440 return ret;
441 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
442 break;
443 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
444 udelay(100);
445 else
446 return -EIO;
447 }
448 return send_bytes;
449 }
450
451 /* Write a single byte to the aux channel in native mode */
452 static int
453 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
454 uint16_t address, uint8_t byte)
455 {
456 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
457 }
458
459 /* read bytes from a native aux channel */
460 static int
461 intel_dp_aux_native_read(struct intel_dp *intel_dp,
462 uint16_t address, uint8_t *recv, int recv_bytes)
463 {
464 uint8_t msg[4];
465 int msg_bytes;
466 uint8_t reply[20];
467 int reply_bytes;
468 uint8_t ack;
469 int ret;
470
471 intel_dp_check_edp(intel_dp);
472 msg[0] = AUX_NATIVE_READ << 4;
473 msg[1] = address >> 8;
474 msg[2] = address & 0xff;
475 msg[3] = recv_bytes - 1;
476
477 msg_bytes = 4;
478 reply_bytes = recv_bytes + 1;
479
480 for (;;) {
481 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
482 reply, reply_bytes);
483 if (ret == 0)
484 return -EPROTO;
485 if (ret < 0)
486 return ret;
487 ack = reply[0];
488 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
489 memcpy(recv, reply + 1, ret - 1);
490 return ret - 1;
491 }
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 udelay(100);
494 else
495 return -EIO;
496 }
497 }
498
499 static int
500 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
501 uint8_t write_byte, uint8_t *read_byte)
502 {
503 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
504 struct intel_dp *intel_dp = container_of(adapter,
505 struct intel_dp,
506 adapter);
507 uint16_t address = algo_data->address;
508 uint8_t msg[5];
509 uint8_t reply[2];
510 unsigned retry;
511 int msg_bytes;
512 int reply_bytes;
513 int ret;
514
515 intel_dp_check_edp(intel_dp);
516 /* Set up the command byte */
517 if (mode & MODE_I2C_READ)
518 msg[0] = AUX_I2C_READ << 4;
519 else
520 msg[0] = AUX_I2C_WRITE << 4;
521
522 if (!(mode & MODE_I2C_STOP))
523 msg[0] |= AUX_I2C_MOT << 4;
524
525 msg[1] = address >> 8;
526 msg[2] = address;
527
528 switch (mode) {
529 case MODE_I2C_WRITE:
530 msg[3] = 0;
531 msg[4] = write_byte;
532 msg_bytes = 5;
533 reply_bytes = 1;
534 break;
535 case MODE_I2C_READ:
536 msg[3] = 0;
537 msg_bytes = 4;
538 reply_bytes = 2;
539 break;
540 default:
541 msg_bytes = 3;
542 reply_bytes = 1;
543 break;
544 }
545
546 for (retry = 0; retry < 5; retry++) {
547 ret = intel_dp_aux_ch(intel_dp,
548 msg, msg_bytes,
549 reply, reply_bytes);
550 if (ret < 0) {
551 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
552 return ret;
553 }
554
555 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
556 case AUX_NATIVE_REPLY_ACK:
557 /* I2C-over-AUX Reply field is only valid
558 * when paired with AUX ACK.
559 */
560 break;
561 case AUX_NATIVE_REPLY_NACK:
562 DRM_DEBUG_KMS("aux_ch native nack\n");
563 return -EREMOTEIO;
564 case AUX_NATIVE_REPLY_DEFER:
565 udelay(100);
566 continue;
567 default:
568 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
569 reply[0]);
570 return -EREMOTEIO;
571 }
572
573 switch (reply[0] & AUX_I2C_REPLY_MASK) {
574 case AUX_I2C_REPLY_ACK:
575 if (mode == MODE_I2C_READ) {
576 *read_byte = reply[1];
577 }
578 return reply_bytes - 1;
579 case AUX_I2C_REPLY_NACK:
580 DRM_DEBUG_KMS("aux_i2c nack\n");
581 return -EREMOTEIO;
582 case AUX_I2C_REPLY_DEFER:
583 DRM_DEBUG_KMS("aux_i2c defer\n");
584 udelay(100);
585 break;
586 default:
587 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
588 return -EREMOTEIO;
589 }
590 }
591
592 DRM_ERROR("too many retries, giving up\n");
593 return -EREMOTEIO;
594 }
595
596 static int
597 intel_dp_i2c_init(struct intel_dp *intel_dp,
598 struct intel_connector *intel_connector, const char *name)
599 {
600 int ret;
601
602 DRM_DEBUG_KMS("i2c_init %s\n", name);
603 intel_dp->algo.running = false;
604 intel_dp->algo.address = 0;
605 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
606
607 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
608 intel_dp->adapter.owner = THIS_MODULE;
609 intel_dp->adapter.class = I2C_CLASS_DDC;
610 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
611 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
612 intel_dp->adapter.algo_data = &intel_dp->algo;
613 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
614
615 ironlake_edp_panel_vdd_on(intel_dp);
616 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
617 ironlake_edp_panel_vdd_off(intel_dp, false);
618 return ret;
619 }
620
621 static void
622 intel_dp_set_clock(struct intel_encoder *encoder,
623 struct intel_crtc_config *pipe_config, int link_bw)
624 {
625 struct drm_device *dev = encoder->base.dev;
626
627 if (IS_G4X(dev)) {
628 if (link_bw == DP_LINK_BW_1_62) {
629 pipe_config->dpll.p1 = 2;
630 pipe_config->dpll.p2 = 10;
631 pipe_config->dpll.n = 2;
632 pipe_config->dpll.m1 = 23;
633 pipe_config->dpll.m2 = 8;
634 } else {
635 pipe_config->dpll.p1 = 1;
636 pipe_config->dpll.p2 = 10;
637 pipe_config->dpll.n = 1;
638 pipe_config->dpll.m1 = 14;
639 pipe_config->dpll.m2 = 2;
640 }
641 pipe_config->clock_set = true;
642 } else if (IS_HASWELL(dev)) {
643 /* Haswell has special-purpose DP DDI clocks. */
644 } else if (HAS_PCH_SPLIT(dev)) {
645 if (link_bw == DP_LINK_BW_1_62) {
646 pipe_config->dpll.n = 1;
647 pipe_config->dpll.p1 = 2;
648 pipe_config->dpll.p2 = 10;
649 pipe_config->dpll.m1 = 12;
650 pipe_config->dpll.m2 = 9;
651 } else {
652 pipe_config->dpll.n = 2;
653 pipe_config->dpll.p1 = 1;
654 pipe_config->dpll.p2 = 10;
655 pipe_config->dpll.m1 = 14;
656 pipe_config->dpll.m2 = 8;
657 }
658 pipe_config->clock_set = true;
659 } else if (IS_VALLEYVIEW(dev)) {
660 /* FIXME: Need to figure out optimized DP clocks for vlv. */
661 }
662 }
663
664 bool
665 intel_dp_compute_config(struct intel_encoder *encoder,
666 struct intel_crtc_config *pipe_config)
667 {
668 struct drm_device *dev = encoder->base.dev;
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
672 enum port port = dp_to_dig_port(intel_dp)->port;
673 struct intel_crtc *intel_crtc = encoder->new_crtc;
674 struct intel_connector *intel_connector = intel_dp->attached_connector;
675 int lane_count, clock;
676 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
677 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
678 int bpp, mode_rate;
679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
680 int link_avail, link_clock;
681
682 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
683 pipe_config->has_pch_encoder = true;
684
685 pipe_config->has_dp_encoder = true;
686
687 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
688 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
689 adjusted_mode);
690 if (!HAS_PCH_SPLIT(dev))
691 intel_gmch_panel_fitting(intel_crtc, pipe_config,
692 intel_connector->panel.fitting_mode);
693 else
694 intel_pch_panel_fitting(intel_crtc, pipe_config,
695 intel_connector->panel.fitting_mode);
696 }
697
698 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
699 return false;
700
701 DRM_DEBUG_KMS("DP link computation with max lane count %i "
702 "max bw %02x pixel clock %iKHz\n",
703 max_lane_count, bws[max_clock], adjusted_mode->clock);
704
705 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
706 * bpc in between. */
707 bpp = pipe_config->pipe_bpp;
708 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
709 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
710
711 for (; bpp >= 6*3; bpp -= 2*3) {
712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
713
714 for (clock = 0; clock <= max_clock; clock++) {
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
716 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
717 link_avail = intel_dp_max_data_rate(link_clock,
718 lane_count);
719
720 if (mode_rate <= link_avail) {
721 goto found;
722 }
723 }
724 }
725 }
726
727 return false;
728
729 found:
730 if (intel_dp->color_range_auto) {
731 /*
732 * See:
733 * CEA-861-E - 5.1 Default Encoding Parameters
734 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
735 */
736 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
737 intel_dp->color_range = DP_COLOR_RANGE_16_235;
738 else
739 intel_dp->color_range = 0;
740 }
741
742 if (intel_dp->color_range)
743 pipe_config->limited_color_range = true;
744
745 intel_dp->link_bw = bws[clock];
746 intel_dp->lane_count = lane_count;
747 pipe_config->pipe_bpp = bpp;
748 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
749
750 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
751 intel_dp->link_bw, intel_dp->lane_count,
752 pipe_config->port_clock, bpp);
753 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
754 mode_rate, link_avail);
755
756 intel_link_compute_m_n(bpp, lane_count,
757 adjusted_mode->clock, pipe_config->port_clock,
758 &pipe_config->dp_m_n);
759
760 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
761
762 return true;
763 }
764
765 void intel_dp_init_link_config(struct intel_dp *intel_dp)
766 {
767 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
768 intel_dp->link_configuration[0] = intel_dp->link_bw;
769 intel_dp->link_configuration[1] = intel_dp->lane_count;
770 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
771 /*
772 * Check for DPCD version > 1.1 and enhanced framing support
773 */
774 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
775 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
776 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
777 }
778 }
779
780 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
781 {
782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
783 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
784 struct drm_device *dev = crtc->base.dev;
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 u32 dpa_ctl;
787
788 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
789 dpa_ctl = I915_READ(DP_A);
790 dpa_ctl &= ~DP_PLL_FREQ_MASK;
791
792 if (crtc->config.port_clock == 162000) {
793 /* For a long time we've carried around a ILK-DevA w/a for the
794 * 160MHz clock. If we're really unlucky, it's still required.
795 */
796 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
797 dpa_ctl |= DP_PLL_FREQ_160MHZ;
798 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
799 } else {
800 dpa_ctl |= DP_PLL_FREQ_270MHZ;
801 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
802 }
803
804 I915_WRITE(DP_A, dpa_ctl);
805
806 POSTING_READ(DP_A);
807 udelay(500);
808 }
809
810 static void
811 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode)
813 {
814 struct drm_device *dev = encoder->dev;
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
817 enum port port = dp_to_dig_port(intel_dp)->port;
818 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
819
820 /*
821 * There are four kinds of DP registers:
822 *
823 * IBX PCH
824 * SNB CPU
825 * IVB CPU
826 * CPT PCH
827 *
828 * IBX PCH and CPU are the same for almost everything,
829 * except that the CPU DP PLL is configured in this
830 * register
831 *
832 * CPT PCH is quite different, having many bits moved
833 * to the TRANS_DP_CTL register instead. That
834 * configuration happens (oddly) in ironlake_pch_enable
835 */
836
837 /* Preserve the BIOS-computed detected bit. This is
838 * supposed to be read-only.
839 */
840 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
841
842 /* Handle DP bits in common between all three register formats */
843 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
844 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
845
846 if (intel_dp->has_audio) {
847 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
848 pipe_name(crtc->pipe));
849 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
850 intel_write_eld(encoder, adjusted_mode);
851 }
852
853 intel_dp_init_link_config(intel_dp);
854
855 /* Split out the IBX/CPU vs CPT settings */
856
857 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
858 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
859 intel_dp->DP |= DP_SYNC_HS_HIGH;
860 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
861 intel_dp->DP |= DP_SYNC_VS_HIGH;
862 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
863
864 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
865 intel_dp->DP |= DP_ENHANCED_FRAMING;
866
867 intel_dp->DP |= crtc->pipe << 29;
868 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
869 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
870 intel_dp->DP |= intel_dp->color_range;
871
872 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
873 intel_dp->DP |= DP_SYNC_HS_HIGH;
874 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
875 intel_dp->DP |= DP_SYNC_VS_HIGH;
876 intel_dp->DP |= DP_LINK_TRAIN_OFF;
877
878 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
879 intel_dp->DP |= DP_ENHANCED_FRAMING;
880
881 if (crtc->pipe == 1)
882 intel_dp->DP |= DP_PIPEB_SELECT;
883 } else {
884 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
885 }
886
887 if (port == PORT_A && !IS_VALLEYVIEW(dev))
888 ironlake_set_pll_cpu_edp(intel_dp);
889 }
890
891 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
892 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
893
894 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
895 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
896
897 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
898 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
899
900 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
901 u32 mask,
902 u32 value)
903 {
904 struct drm_device *dev = intel_dp_to_dev(intel_dp);
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 u32 pp_stat_reg, pp_ctrl_reg;
907
908 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
909 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
910
911 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
912 mask, value,
913 I915_READ(pp_stat_reg),
914 I915_READ(pp_ctrl_reg));
915
916 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
917 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
918 I915_READ(pp_stat_reg),
919 I915_READ(pp_ctrl_reg));
920 }
921 }
922
923 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
924 {
925 DRM_DEBUG_KMS("Wait for panel power on\n");
926 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
927 }
928
929 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
930 {
931 DRM_DEBUG_KMS("Wait for panel power off time\n");
932 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
933 }
934
935 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
936 {
937 DRM_DEBUG_KMS("Wait for panel power cycle\n");
938 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
939 }
940
941
942 /* Read the current pp_control value, unlocking the register if it
943 * is locked
944 */
945
946 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
947 {
948 struct drm_device *dev = intel_dp_to_dev(intel_dp);
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 control;
951 u32 pp_ctrl_reg;
952
953 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
954 control = I915_READ(pp_ctrl_reg);
955
956 control &= ~PANEL_UNLOCK_MASK;
957 control |= PANEL_UNLOCK_REGS;
958 return control;
959 }
960
961 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
962 {
963 struct drm_device *dev = intel_dp_to_dev(intel_dp);
964 struct drm_i915_private *dev_priv = dev->dev_private;
965 u32 pp;
966 u32 pp_stat_reg, pp_ctrl_reg;
967
968 if (!is_edp(intel_dp))
969 return;
970 DRM_DEBUG_KMS("Turn eDP VDD on\n");
971
972 WARN(intel_dp->want_panel_vdd,
973 "eDP VDD already requested on\n");
974
975 intel_dp->want_panel_vdd = true;
976
977 if (ironlake_edp_have_panel_vdd(intel_dp)) {
978 DRM_DEBUG_KMS("eDP VDD already on\n");
979 return;
980 }
981
982 if (!ironlake_edp_have_panel_power(intel_dp))
983 ironlake_wait_panel_power_cycle(intel_dp);
984
985 pp = ironlake_get_pp_control(intel_dp);
986 pp |= EDP_FORCE_VDD;
987
988 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
989 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
990
991 I915_WRITE(pp_ctrl_reg, pp);
992 POSTING_READ(pp_ctrl_reg);
993 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
994 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
995 /*
996 * If the panel wasn't on, delay before accessing aux channel
997 */
998 if (!ironlake_edp_have_panel_power(intel_dp)) {
999 DRM_DEBUG_KMS("eDP was not running\n");
1000 msleep(intel_dp->panel_power_up_delay);
1001 }
1002 }
1003
1004 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1005 {
1006 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 u32 pp;
1009 u32 pp_stat_reg, pp_ctrl_reg;
1010
1011 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1012
1013 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1014 pp = ironlake_get_pp_control(intel_dp);
1015 pp &= ~EDP_FORCE_VDD;
1016
1017 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1018 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1019
1020 I915_WRITE(pp_ctrl_reg, pp);
1021 POSTING_READ(pp_ctrl_reg);
1022
1023 /* Make sure sequencer is idle before allowing subsequent activity */
1024 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1025 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1026 msleep(intel_dp->panel_power_down_delay);
1027 }
1028 }
1029
1030 static void ironlake_panel_vdd_work(struct work_struct *__work)
1031 {
1032 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1033 struct intel_dp, panel_vdd_work);
1034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1035
1036 mutex_lock(&dev->mode_config.mutex);
1037 ironlake_panel_vdd_off_sync(intel_dp);
1038 mutex_unlock(&dev->mode_config.mutex);
1039 }
1040
1041 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1042 {
1043 if (!is_edp(intel_dp))
1044 return;
1045
1046 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1047 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1048
1049 intel_dp->want_panel_vdd = false;
1050
1051 if (sync) {
1052 ironlake_panel_vdd_off_sync(intel_dp);
1053 } else {
1054 /*
1055 * Queue the timer to fire a long
1056 * time from now (relative to the power down delay)
1057 * to keep the panel power up across a sequence of operations
1058 */
1059 schedule_delayed_work(&intel_dp->panel_vdd_work,
1060 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1061 }
1062 }
1063
1064 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1065 {
1066 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1068 u32 pp;
1069 u32 pp_ctrl_reg;
1070
1071 if (!is_edp(intel_dp))
1072 return;
1073
1074 DRM_DEBUG_KMS("Turn eDP power on\n");
1075
1076 if (ironlake_edp_have_panel_power(intel_dp)) {
1077 DRM_DEBUG_KMS("eDP power already on\n");
1078 return;
1079 }
1080
1081 ironlake_wait_panel_power_cycle(intel_dp);
1082
1083 pp = ironlake_get_pp_control(intel_dp);
1084 if (IS_GEN5(dev)) {
1085 /* ILK workaround: disable reset around power sequence */
1086 pp &= ~PANEL_POWER_RESET;
1087 I915_WRITE(PCH_PP_CONTROL, pp);
1088 POSTING_READ(PCH_PP_CONTROL);
1089 }
1090
1091 pp |= POWER_TARGET_ON;
1092 if (!IS_GEN5(dev))
1093 pp |= PANEL_POWER_RESET;
1094
1095 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1096
1097 I915_WRITE(pp_ctrl_reg, pp);
1098 POSTING_READ(pp_ctrl_reg);
1099
1100 ironlake_wait_panel_on(intel_dp);
1101
1102 if (IS_GEN5(dev)) {
1103 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1104 I915_WRITE(PCH_PP_CONTROL, pp);
1105 POSTING_READ(PCH_PP_CONTROL);
1106 }
1107 }
1108
1109 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1110 {
1111 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1113 u32 pp;
1114 u32 pp_ctrl_reg;
1115
1116 if (!is_edp(intel_dp))
1117 return;
1118
1119 DRM_DEBUG_KMS("Turn eDP power off\n");
1120
1121 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1122
1123 pp = ironlake_get_pp_control(intel_dp);
1124 /* We need to switch off panel power _and_ force vdd, for otherwise some
1125 * panels get very unhappy and cease to work. */
1126 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1127
1128 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1129
1130 I915_WRITE(pp_ctrl_reg, pp);
1131 POSTING_READ(pp_ctrl_reg);
1132
1133 intel_dp->want_panel_vdd = false;
1134
1135 ironlake_wait_panel_off(intel_dp);
1136 }
1137
1138 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1139 {
1140 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1141 struct drm_device *dev = intel_dig_port->base.base.dev;
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1144 u32 pp;
1145 u32 pp_ctrl_reg;
1146
1147 if (!is_edp(intel_dp))
1148 return;
1149
1150 DRM_DEBUG_KMS("\n");
1151 /*
1152 * If we enable the backlight right away following a panel power
1153 * on, we may see slight flicker as the panel syncs with the eDP
1154 * link. So delay a bit to make sure the image is solid before
1155 * allowing it to appear.
1156 */
1157 msleep(intel_dp->backlight_on_delay);
1158 pp = ironlake_get_pp_control(intel_dp);
1159 pp |= EDP_BLC_ENABLE;
1160
1161 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1162
1163 I915_WRITE(pp_ctrl_reg, pp);
1164 POSTING_READ(pp_ctrl_reg);
1165
1166 intel_panel_enable_backlight(dev, pipe);
1167 }
1168
1169 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1170 {
1171 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 pp;
1174 u32 pp_ctrl_reg;
1175
1176 if (!is_edp(intel_dp))
1177 return;
1178
1179 intel_panel_disable_backlight(dev);
1180
1181 DRM_DEBUG_KMS("\n");
1182 pp = ironlake_get_pp_control(intel_dp);
1183 pp &= ~EDP_BLC_ENABLE;
1184
1185 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1186
1187 I915_WRITE(pp_ctrl_reg, pp);
1188 POSTING_READ(pp_ctrl_reg);
1189 msleep(intel_dp->backlight_off_delay);
1190 }
1191
1192 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1193 {
1194 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1195 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1196 struct drm_device *dev = crtc->dev;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 u32 dpa_ctl;
1199
1200 assert_pipe_disabled(dev_priv,
1201 to_intel_crtc(crtc)->pipe);
1202
1203 DRM_DEBUG_KMS("\n");
1204 dpa_ctl = I915_READ(DP_A);
1205 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1206 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1207
1208 /* We don't adjust intel_dp->DP while tearing down the link, to
1209 * facilitate link retraining (e.g. after hotplug). Hence clear all
1210 * enable bits here to ensure that we don't enable too much. */
1211 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1212 intel_dp->DP |= DP_PLL_ENABLE;
1213 I915_WRITE(DP_A, intel_dp->DP);
1214 POSTING_READ(DP_A);
1215 udelay(200);
1216 }
1217
1218 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1219 {
1220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222 struct drm_device *dev = crtc->dev;
1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 u32 dpa_ctl;
1225
1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1228
1229 dpa_ctl = I915_READ(DP_A);
1230 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1231 "dp pll off, should be on\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234 /* We can't rely on the value tracked for the DP register in
1235 * intel_dp->DP because link_down must not change that (otherwise link
1236 * re-training will fail. */
1237 dpa_ctl &= ~DP_PLL_ENABLE;
1238 I915_WRITE(DP_A, dpa_ctl);
1239 POSTING_READ(DP_A);
1240 udelay(200);
1241 }
1242
1243 /* If the sink supports it, try to set the power state appropriately */
1244 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1245 {
1246 int ret, i;
1247
1248 /* Should have a valid DPCD by this point */
1249 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1250 return;
1251
1252 if (mode != DRM_MODE_DPMS_ON) {
1253 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1254 DP_SET_POWER_D3);
1255 if (ret != 1)
1256 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1257 } else {
1258 /*
1259 * When turning on, we need to retry for 1ms to give the sink
1260 * time to wake up.
1261 */
1262 for (i = 0; i < 3; i++) {
1263 ret = intel_dp_aux_native_write_1(intel_dp,
1264 DP_SET_POWER,
1265 DP_SET_POWER_D0);
1266 if (ret == 1)
1267 break;
1268 msleep(1);
1269 }
1270 }
1271 }
1272
1273 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1274 enum pipe *pipe)
1275 {
1276 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1277 enum port port = dp_to_dig_port(intel_dp)->port;
1278 struct drm_device *dev = encoder->base.dev;
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 u32 tmp = I915_READ(intel_dp->output_reg);
1281
1282 if (!(tmp & DP_PORT_EN))
1283 return false;
1284
1285 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1286 *pipe = PORT_TO_PIPE_CPT(tmp);
1287 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1288 *pipe = PORT_TO_PIPE(tmp);
1289 } else {
1290 u32 trans_sel;
1291 u32 trans_dp;
1292 int i;
1293
1294 switch (intel_dp->output_reg) {
1295 case PCH_DP_B:
1296 trans_sel = TRANS_DP_PORT_SEL_B;
1297 break;
1298 case PCH_DP_C:
1299 trans_sel = TRANS_DP_PORT_SEL_C;
1300 break;
1301 case PCH_DP_D:
1302 trans_sel = TRANS_DP_PORT_SEL_D;
1303 break;
1304 default:
1305 return true;
1306 }
1307
1308 for_each_pipe(i) {
1309 trans_dp = I915_READ(TRANS_DP_CTL(i));
1310 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1311 *pipe = i;
1312 return true;
1313 }
1314 }
1315
1316 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1317 intel_dp->output_reg);
1318 }
1319
1320 return true;
1321 }
1322
1323 static void intel_dp_get_config(struct intel_encoder *encoder,
1324 struct intel_crtc_config *pipe_config)
1325 {
1326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1327 u32 tmp, flags = 0;
1328 struct drm_device *dev = encoder->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 enum port port = dp_to_dig_port(intel_dp)->port;
1331 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1332
1333 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1334 tmp = I915_READ(intel_dp->output_reg);
1335 if (tmp & DP_SYNC_HS_HIGH)
1336 flags |= DRM_MODE_FLAG_PHSYNC;
1337 else
1338 flags |= DRM_MODE_FLAG_NHSYNC;
1339
1340 if (tmp & DP_SYNC_VS_HIGH)
1341 flags |= DRM_MODE_FLAG_PVSYNC;
1342 else
1343 flags |= DRM_MODE_FLAG_NVSYNC;
1344 } else {
1345 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1346 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1347 flags |= DRM_MODE_FLAG_PHSYNC;
1348 else
1349 flags |= DRM_MODE_FLAG_NHSYNC;
1350
1351 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1352 flags |= DRM_MODE_FLAG_PVSYNC;
1353 else
1354 flags |= DRM_MODE_FLAG_NVSYNC;
1355 }
1356
1357 pipe_config->adjusted_mode.flags |= flags;
1358 }
1359
1360 static void intel_disable_dp(struct intel_encoder *encoder)
1361 {
1362 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1363 enum port port = dp_to_dig_port(intel_dp)->port;
1364 struct drm_device *dev = encoder->base.dev;
1365
1366 /* Make sure the panel is off before trying to change the mode. But also
1367 * ensure that we have vdd while we switch off the panel. */
1368 ironlake_edp_panel_vdd_on(intel_dp);
1369 ironlake_edp_backlight_off(intel_dp);
1370 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1371 ironlake_edp_panel_off(intel_dp);
1372
1373 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1374 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1375 intel_dp_link_down(intel_dp);
1376 }
1377
1378 static void intel_post_disable_dp(struct intel_encoder *encoder)
1379 {
1380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1381 enum port port = dp_to_dig_port(intel_dp)->port;
1382 struct drm_device *dev = encoder->base.dev;
1383
1384 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1385 intel_dp_link_down(intel_dp);
1386 if (!IS_VALLEYVIEW(dev))
1387 ironlake_edp_pll_off(intel_dp);
1388 }
1389 }
1390
1391 static void intel_enable_dp(struct intel_encoder *encoder)
1392 {
1393 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1394 struct drm_device *dev = encoder->base.dev;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1397
1398 if (WARN_ON(dp_reg & DP_PORT_EN))
1399 return;
1400
1401 ironlake_edp_panel_vdd_on(intel_dp);
1402 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1403 intel_dp_start_link_train(intel_dp);
1404 ironlake_edp_panel_on(intel_dp);
1405 ironlake_edp_panel_vdd_off(intel_dp, true);
1406 intel_dp_complete_link_train(intel_dp);
1407 intel_dp_stop_link_train(intel_dp);
1408 ironlake_edp_backlight_on(intel_dp);
1409
1410 if (IS_VALLEYVIEW(dev)) {
1411 struct intel_digital_port *dport =
1412 enc_to_dig_port(&encoder->base);
1413 int channel = vlv_dport_to_channel(dport);
1414
1415 vlv_wait_port_ready(dev_priv, channel);
1416 }
1417 }
1418
1419 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1420 {
1421 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1422 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1423 struct drm_device *dev = encoder->base.dev;
1424 struct drm_i915_private *dev_priv = dev->dev_private;
1425
1426 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1427 ironlake_edp_pll_on(intel_dp);
1428
1429 if (IS_VALLEYVIEW(dev)) {
1430 struct intel_crtc *intel_crtc =
1431 to_intel_crtc(encoder->base.crtc);
1432 int port = vlv_dport_to_channel(dport);
1433 int pipe = intel_crtc->pipe;
1434 u32 val;
1435
1436 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1437 val = 0;
1438 if (pipe)
1439 val |= (1<<21);
1440 else
1441 val &= ~(1<<21);
1442 val |= 0x001000c4;
1443 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1444
1445 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1446 0x00760018);
1447 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1448 0x00400888);
1449 }
1450 }
1451
1452 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1453 {
1454 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1455 struct drm_device *dev = encoder->base.dev;
1456 struct drm_i915_private *dev_priv = dev->dev_private;
1457 int port = vlv_dport_to_channel(dport);
1458
1459 if (!IS_VALLEYVIEW(dev))
1460 return;
1461
1462 /* Program Tx lane resets to default */
1463 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1464 DPIO_PCS_TX_LANE2_RESET |
1465 DPIO_PCS_TX_LANE1_RESET);
1466 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1467 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1468 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1469 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1470 DPIO_PCS_CLK_SOFT_RESET);
1471
1472 /* Fix up inter-pair skew failure */
1473 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1474 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1475 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1476 }
1477
1478 /*
1479 * Native read with retry for link status and receiver capability reads for
1480 * cases where the sink may still be asleep.
1481 */
1482 static bool
1483 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1484 uint8_t *recv, int recv_bytes)
1485 {
1486 int ret, i;
1487
1488 /*
1489 * Sinks are *supposed* to come up within 1ms from an off state,
1490 * but we're also supposed to retry 3 times per the spec.
1491 */
1492 for (i = 0; i < 3; i++) {
1493 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1494 recv_bytes);
1495 if (ret == recv_bytes)
1496 return true;
1497 msleep(1);
1498 }
1499
1500 return false;
1501 }
1502
1503 /*
1504 * Fetch AUX CH registers 0x202 - 0x207 which contain
1505 * link status information
1506 */
1507 static bool
1508 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1509 {
1510 return intel_dp_aux_native_read_retry(intel_dp,
1511 DP_LANE0_1_STATUS,
1512 link_status,
1513 DP_LINK_STATUS_SIZE);
1514 }
1515
1516 #if 0
1517 static char *voltage_names[] = {
1518 "0.4V", "0.6V", "0.8V", "1.2V"
1519 };
1520 static char *pre_emph_names[] = {
1521 "0dB", "3.5dB", "6dB", "9.5dB"
1522 };
1523 static char *link_train_names[] = {
1524 "pattern 1", "pattern 2", "idle", "off"
1525 };
1526 #endif
1527
1528 /*
1529 * These are source-specific values; current Intel hardware supports
1530 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1531 */
1532
1533 static uint8_t
1534 intel_dp_voltage_max(struct intel_dp *intel_dp)
1535 {
1536 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1537 enum port port = dp_to_dig_port(intel_dp)->port;
1538
1539 if (IS_VALLEYVIEW(dev))
1540 return DP_TRAIN_VOLTAGE_SWING_1200;
1541 else if (IS_GEN7(dev) && port == PORT_A)
1542 return DP_TRAIN_VOLTAGE_SWING_800;
1543 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1544 return DP_TRAIN_VOLTAGE_SWING_1200;
1545 else
1546 return DP_TRAIN_VOLTAGE_SWING_800;
1547 }
1548
1549 static uint8_t
1550 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1551 {
1552 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1553 enum port port = dp_to_dig_port(intel_dp)->port;
1554
1555 if (HAS_DDI(dev)) {
1556 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1557 case DP_TRAIN_VOLTAGE_SWING_400:
1558 return DP_TRAIN_PRE_EMPHASIS_9_5;
1559 case DP_TRAIN_VOLTAGE_SWING_600:
1560 return DP_TRAIN_PRE_EMPHASIS_6;
1561 case DP_TRAIN_VOLTAGE_SWING_800:
1562 return DP_TRAIN_PRE_EMPHASIS_3_5;
1563 case DP_TRAIN_VOLTAGE_SWING_1200:
1564 default:
1565 return DP_TRAIN_PRE_EMPHASIS_0;
1566 }
1567 } else if (IS_VALLEYVIEW(dev)) {
1568 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1569 case DP_TRAIN_VOLTAGE_SWING_400:
1570 return DP_TRAIN_PRE_EMPHASIS_9_5;
1571 case DP_TRAIN_VOLTAGE_SWING_600:
1572 return DP_TRAIN_PRE_EMPHASIS_6;
1573 case DP_TRAIN_VOLTAGE_SWING_800:
1574 return DP_TRAIN_PRE_EMPHASIS_3_5;
1575 case DP_TRAIN_VOLTAGE_SWING_1200:
1576 default:
1577 return DP_TRAIN_PRE_EMPHASIS_0;
1578 }
1579 } else if (IS_GEN7(dev) && port == PORT_A) {
1580 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1581 case DP_TRAIN_VOLTAGE_SWING_400:
1582 return DP_TRAIN_PRE_EMPHASIS_6;
1583 case DP_TRAIN_VOLTAGE_SWING_600:
1584 case DP_TRAIN_VOLTAGE_SWING_800:
1585 return DP_TRAIN_PRE_EMPHASIS_3_5;
1586 default:
1587 return DP_TRAIN_PRE_EMPHASIS_0;
1588 }
1589 } else {
1590 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1591 case DP_TRAIN_VOLTAGE_SWING_400:
1592 return DP_TRAIN_PRE_EMPHASIS_6;
1593 case DP_TRAIN_VOLTAGE_SWING_600:
1594 return DP_TRAIN_PRE_EMPHASIS_6;
1595 case DP_TRAIN_VOLTAGE_SWING_800:
1596 return DP_TRAIN_PRE_EMPHASIS_3_5;
1597 case DP_TRAIN_VOLTAGE_SWING_1200:
1598 default:
1599 return DP_TRAIN_PRE_EMPHASIS_0;
1600 }
1601 }
1602 }
1603
1604 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1605 {
1606 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1609 unsigned long demph_reg_value, preemph_reg_value,
1610 uniqtranscale_reg_value;
1611 uint8_t train_set = intel_dp->train_set[0];
1612 int port = vlv_dport_to_channel(dport);
1613
1614 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1615 case DP_TRAIN_PRE_EMPHASIS_0:
1616 preemph_reg_value = 0x0004000;
1617 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1618 case DP_TRAIN_VOLTAGE_SWING_400:
1619 demph_reg_value = 0x2B405555;
1620 uniqtranscale_reg_value = 0x552AB83A;
1621 break;
1622 case DP_TRAIN_VOLTAGE_SWING_600:
1623 demph_reg_value = 0x2B404040;
1624 uniqtranscale_reg_value = 0x5548B83A;
1625 break;
1626 case DP_TRAIN_VOLTAGE_SWING_800:
1627 demph_reg_value = 0x2B245555;
1628 uniqtranscale_reg_value = 0x5560B83A;
1629 break;
1630 case DP_TRAIN_VOLTAGE_SWING_1200:
1631 demph_reg_value = 0x2B405555;
1632 uniqtranscale_reg_value = 0x5598DA3A;
1633 break;
1634 default:
1635 return 0;
1636 }
1637 break;
1638 case DP_TRAIN_PRE_EMPHASIS_3_5:
1639 preemph_reg_value = 0x0002000;
1640 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1641 case DP_TRAIN_VOLTAGE_SWING_400:
1642 demph_reg_value = 0x2B404040;
1643 uniqtranscale_reg_value = 0x5552B83A;
1644 break;
1645 case DP_TRAIN_VOLTAGE_SWING_600:
1646 demph_reg_value = 0x2B404848;
1647 uniqtranscale_reg_value = 0x5580B83A;
1648 break;
1649 case DP_TRAIN_VOLTAGE_SWING_800:
1650 demph_reg_value = 0x2B404040;
1651 uniqtranscale_reg_value = 0x55ADDA3A;
1652 break;
1653 default:
1654 return 0;
1655 }
1656 break;
1657 case DP_TRAIN_PRE_EMPHASIS_6:
1658 preemph_reg_value = 0x0000000;
1659 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1660 case DP_TRAIN_VOLTAGE_SWING_400:
1661 demph_reg_value = 0x2B305555;
1662 uniqtranscale_reg_value = 0x5570B83A;
1663 break;
1664 case DP_TRAIN_VOLTAGE_SWING_600:
1665 demph_reg_value = 0x2B2B4040;
1666 uniqtranscale_reg_value = 0x55ADDA3A;
1667 break;
1668 default:
1669 return 0;
1670 }
1671 break;
1672 case DP_TRAIN_PRE_EMPHASIS_9_5:
1673 preemph_reg_value = 0x0006000;
1674 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1675 case DP_TRAIN_VOLTAGE_SWING_400:
1676 demph_reg_value = 0x1B405555;
1677 uniqtranscale_reg_value = 0x55ADDA3A;
1678 break;
1679 default:
1680 return 0;
1681 }
1682 break;
1683 default:
1684 return 0;
1685 }
1686
1687 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1688 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1689 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1690 uniqtranscale_reg_value);
1691 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1692 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1693 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1694 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1695
1696 return 0;
1697 }
1698
1699 static void
1700 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1701 {
1702 uint8_t v = 0;
1703 uint8_t p = 0;
1704 int lane;
1705 uint8_t voltage_max;
1706 uint8_t preemph_max;
1707
1708 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1709 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1710 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1711
1712 if (this_v > v)
1713 v = this_v;
1714 if (this_p > p)
1715 p = this_p;
1716 }
1717
1718 voltage_max = intel_dp_voltage_max(intel_dp);
1719 if (v >= voltage_max)
1720 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1721
1722 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1723 if (p >= preemph_max)
1724 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1725
1726 for (lane = 0; lane < 4; lane++)
1727 intel_dp->train_set[lane] = v | p;
1728 }
1729
1730 static uint32_t
1731 intel_gen4_signal_levels(uint8_t train_set)
1732 {
1733 uint32_t signal_levels = 0;
1734
1735 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1736 case DP_TRAIN_VOLTAGE_SWING_400:
1737 default:
1738 signal_levels |= DP_VOLTAGE_0_4;
1739 break;
1740 case DP_TRAIN_VOLTAGE_SWING_600:
1741 signal_levels |= DP_VOLTAGE_0_6;
1742 break;
1743 case DP_TRAIN_VOLTAGE_SWING_800:
1744 signal_levels |= DP_VOLTAGE_0_8;
1745 break;
1746 case DP_TRAIN_VOLTAGE_SWING_1200:
1747 signal_levels |= DP_VOLTAGE_1_2;
1748 break;
1749 }
1750 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1751 case DP_TRAIN_PRE_EMPHASIS_0:
1752 default:
1753 signal_levels |= DP_PRE_EMPHASIS_0;
1754 break;
1755 case DP_TRAIN_PRE_EMPHASIS_3_5:
1756 signal_levels |= DP_PRE_EMPHASIS_3_5;
1757 break;
1758 case DP_TRAIN_PRE_EMPHASIS_6:
1759 signal_levels |= DP_PRE_EMPHASIS_6;
1760 break;
1761 case DP_TRAIN_PRE_EMPHASIS_9_5:
1762 signal_levels |= DP_PRE_EMPHASIS_9_5;
1763 break;
1764 }
1765 return signal_levels;
1766 }
1767
1768 /* Gen6's DP voltage swing and pre-emphasis control */
1769 static uint32_t
1770 intel_gen6_edp_signal_levels(uint8_t train_set)
1771 {
1772 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1773 DP_TRAIN_PRE_EMPHASIS_MASK);
1774 switch (signal_levels) {
1775 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1776 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1777 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1778 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1779 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1780 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1781 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1782 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1783 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1784 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1785 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1786 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1787 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1788 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1789 default:
1790 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1791 "0x%x\n", signal_levels);
1792 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1793 }
1794 }
1795
1796 /* Gen7's DP voltage swing and pre-emphasis control */
1797 static uint32_t
1798 intel_gen7_edp_signal_levels(uint8_t train_set)
1799 {
1800 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1801 DP_TRAIN_PRE_EMPHASIS_MASK);
1802 switch (signal_levels) {
1803 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1804 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1805 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1806 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1807 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1808 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1809
1810 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1811 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1812 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1813 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1814
1815 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1816 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1817 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1818 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1819
1820 default:
1821 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1822 "0x%x\n", signal_levels);
1823 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1824 }
1825 }
1826
1827 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1828 static uint32_t
1829 intel_hsw_signal_levels(uint8_t train_set)
1830 {
1831 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1832 DP_TRAIN_PRE_EMPHASIS_MASK);
1833 switch (signal_levels) {
1834 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1835 return DDI_BUF_EMP_400MV_0DB_HSW;
1836 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1837 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1838 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1839 return DDI_BUF_EMP_400MV_6DB_HSW;
1840 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1841 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1842
1843 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1844 return DDI_BUF_EMP_600MV_0DB_HSW;
1845 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1846 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1847 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1848 return DDI_BUF_EMP_600MV_6DB_HSW;
1849
1850 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1851 return DDI_BUF_EMP_800MV_0DB_HSW;
1852 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1853 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1854 default:
1855 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1856 "0x%x\n", signal_levels);
1857 return DDI_BUF_EMP_400MV_0DB_HSW;
1858 }
1859 }
1860
1861 /* Properly updates "DP" with the correct signal levels. */
1862 static void
1863 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1864 {
1865 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1866 enum port port = intel_dig_port->port;
1867 struct drm_device *dev = intel_dig_port->base.base.dev;
1868 uint32_t signal_levels, mask;
1869 uint8_t train_set = intel_dp->train_set[0];
1870
1871 if (HAS_DDI(dev)) {
1872 signal_levels = intel_hsw_signal_levels(train_set);
1873 mask = DDI_BUF_EMP_MASK;
1874 } else if (IS_VALLEYVIEW(dev)) {
1875 signal_levels = intel_vlv_signal_levels(intel_dp);
1876 mask = 0;
1877 } else if (IS_GEN7(dev) && port == PORT_A) {
1878 signal_levels = intel_gen7_edp_signal_levels(train_set);
1879 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1880 } else if (IS_GEN6(dev) && port == PORT_A) {
1881 signal_levels = intel_gen6_edp_signal_levels(train_set);
1882 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1883 } else {
1884 signal_levels = intel_gen4_signal_levels(train_set);
1885 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1886 }
1887
1888 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1889
1890 *DP = (*DP & ~mask) | signal_levels;
1891 }
1892
1893 static bool
1894 intel_dp_set_link_train(struct intel_dp *intel_dp,
1895 uint32_t dp_reg_value,
1896 uint8_t dp_train_pat)
1897 {
1898 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1899 struct drm_device *dev = intel_dig_port->base.base.dev;
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 enum port port = intel_dig_port->port;
1902 int ret;
1903
1904 if (HAS_DDI(dev)) {
1905 uint32_t temp = I915_READ(DP_TP_CTL(port));
1906
1907 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1908 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1909 else
1910 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1911
1912 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1913 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1914 case DP_TRAINING_PATTERN_DISABLE:
1915 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1916
1917 break;
1918 case DP_TRAINING_PATTERN_1:
1919 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1920 break;
1921 case DP_TRAINING_PATTERN_2:
1922 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1923 break;
1924 case DP_TRAINING_PATTERN_3:
1925 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1926 break;
1927 }
1928 I915_WRITE(DP_TP_CTL(port), temp);
1929
1930 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
1931 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1932
1933 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1934 case DP_TRAINING_PATTERN_DISABLE:
1935 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1936 break;
1937 case DP_TRAINING_PATTERN_1:
1938 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1939 break;
1940 case DP_TRAINING_PATTERN_2:
1941 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1942 break;
1943 case DP_TRAINING_PATTERN_3:
1944 DRM_ERROR("DP training pattern 3 not supported\n");
1945 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1946 break;
1947 }
1948
1949 } else {
1950 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1951
1952 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1953 case DP_TRAINING_PATTERN_DISABLE:
1954 dp_reg_value |= DP_LINK_TRAIN_OFF;
1955 break;
1956 case DP_TRAINING_PATTERN_1:
1957 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1958 break;
1959 case DP_TRAINING_PATTERN_2:
1960 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1961 break;
1962 case DP_TRAINING_PATTERN_3:
1963 DRM_ERROR("DP training pattern 3 not supported\n");
1964 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1965 break;
1966 }
1967 }
1968
1969 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1970 POSTING_READ(intel_dp->output_reg);
1971
1972 intel_dp_aux_native_write_1(intel_dp,
1973 DP_TRAINING_PATTERN_SET,
1974 dp_train_pat);
1975
1976 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1977 DP_TRAINING_PATTERN_DISABLE) {
1978 ret = intel_dp_aux_native_write(intel_dp,
1979 DP_TRAINING_LANE0_SET,
1980 intel_dp->train_set,
1981 intel_dp->lane_count);
1982 if (ret != intel_dp->lane_count)
1983 return false;
1984 }
1985
1986 return true;
1987 }
1988
1989 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1990 {
1991 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1992 struct drm_device *dev = intel_dig_port->base.base.dev;
1993 struct drm_i915_private *dev_priv = dev->dev_private;
1994 enum port port = intel_dig_port->port;
1995 uint32_t val;
1996
1997 if (!HAS_DDI(dev))
1998 return;
1999
2000 val = I915_READ(DP_TP_CTL(port));
2001 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2002 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2003 I915_WRITE(DP_TP_CTL(port), val);
2004
2005 /*
2006 * On PORT_A we can have only eDP in SST mode. There the only reason
2007 * we need to set idle transmission mode is to work around a HW issue
2008 * where we enable the pipe while not in idle link-training mode.
2009 * In this case there is requirement to wait for a minimum number of
2010 * idle patterns to be sent.
2011 */
2012 if (port == PORT_A)
2013 return;
2014
2015 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2016 1))
2017 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2018 }
2019
2020 /* Enable corresponding port and start training pattern 1 */
2021 void
2022 intel_dp_start_link_train(struct intel_dp *intel_dp)
2023 {
2024 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2025 struct drm_device *dev = encoder->dev;
2026 int i;
2027 uint8_t voltage;
2028 bool clock_recovery = false;
2029 int voltage_tries, loop_tries;
2030 uint32_t DP = intel_dp->DP;
2031
2032 if (HAS_DDI(dev))
2033 intel_ddi_prepare_link_retrain(encoder);
2034
2035 /* Write the link configuration data */
2036 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2037 intel_dp->link_configuration,
2038 DP_LINK_CONFIGURATION_SIZE);
2039
2040 DP |= DP_PORT_EN;
2041
2042 memset(intel_dp->train_set, 0, 4);
2043 voltage = 0xff;
2044 voltage_tries = 0;
2045 loop_tries = 0;
2046 clock_recovery = false;
2047 for (;;) {
2048 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2049 uint8_t link_status[DP_LINK_STATUS_SIZE];
2050
2051 intel_dp_set_signal_levels(intel_dp, &DP);
2052
2053 /* Set training pattern 1 */
2054 if (!intel_dp_set_link_train(intel_dp, DP,
2055 DP_TRAINING_PATTERN_1 |
2056 DP_LINK_SCRAMBLING_DISABLE))
2057 break;
2058
2059 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2060 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2061 DRM_ERROR("failed to get link status\n");
2062 break;
2063 }
2064
2065 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2066 DRM_DEBUG_KMS("clock recovery OK\n");
2067 clock_recovery = true;
2068 break;
2069 }
2070
2071 /* Check to see if we've tried the max voltage */
2072 for (i = 0; i < intel_dp->lane_count; i++)
2073 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2074 break;
2075 if (i == intel_dp->lane_count) {
2076 ++loop_tries;
2077 if (loop_tries == 5) {
2078 DRM_DEBUG_KMS("too many full retries, give up\n");
2079 break;
2080 }
2081 memset(intel_dp->train_set, 0, 4);
2082 voltage_tries = 0;
2083 continue;
2084 }
2085
2086 /* Check to see if we've tried the same voltage 5 times */
2087 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2088 ++voltage_tries;
2089 if (voltage_tries == 5) {
2090 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2091 break;
2092 }
2093 } else
2094 voltage_tries = 0;
2095 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2096
2097 /* Compute new intel_dp->train_set as requested by target */
2098 intel_get_adjust_train(intel_dp, link_status);
2099 }
2100
2101 intel_dp->DP = DP;
2102 }
2103
2104 void
2105 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2106 {
2107 bool channel_eq = false;
2108 int tries, cr_tries;
2109 uint32_t DP = intel_dp->DP;
2110
2111 /* channel equalization */
2112 tries = 0;
2113 cr_tries = 0;
2114 channel_eq = false;
2115 for (;;) {
2116 uint8_t link_status[DP_LINK_STATUS_SIZE];
2117
2118 if (cr_tries > 5) {
2119 DRM_ERROR("failed to train DP, aborting\n");
2120 intel_dp_link_down(intel_dp);
2121 break;
2122 }
2123
2124 intel_dp_set_signal_levels(intel_dp, &DP);
2125
2126 /* channel eq pattern */
2127 if (!intel_dp_set_link_train(intel_dp, DP,
2128 DP_TRAINING_PATTERN_2 |
2129 DP_LINK_SCRAMBLING_DISABLE))
2130 break;
2131
2132 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2133 if (!intel_dp_get_link_status(intel_dp, link_status))
2134 break;
2135
2136 /* Make sure clock is still ok */
2137 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2138 intel_dp_start_link_train(intel_dp);
2139 cr_tries++;
2140 continue;
2141 }
2142
2143 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2144 channel_eq = true;
2145 break;
2146 }
2147
2148 /* Try 5 times, then try clock recovery if that fails */
2149 if (tries > 5) {
2150 intel_dp_link_down(intel_dp);
2151 intel_dp_start_link_train(intel_dp);
2152 tries = 0;
2153 cr_tries++;
2154 continue;
2155 }
2156
2157 /* Compute new intel_dp->train_set as requested by target */
2158 intel_get_adjust_train(intel_dp, link_status);
2159 ++tries;
2160 }
2161
2162 intel_dp_set_idle_link_train(intel_dp);
2163
2164 intel_dp->DP = DP;
2165
2166 if (channel_eq)
2167 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2168
2169 }
2170
2171 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2172 {
2173 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2174 DP_TRAINING_PATTERN_DISABLE);
2175 }
2176
2177 static void
2178 intel_dp_link_down(struct intel_dp *intel_dp)
2179 {
2180 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2181 enum port port = intel_dig_port->port;
2182 struct drm_device *dev = intel_dig_port->base.base.dev;
2183 struct drm_i915_private *dev_priv = dev->dev_private;
2184 struct intel_crtc *intel_crtc =
2185 to_intel_crtc(intel_dig_port->base.base.crtc);
2186 uint32_t DP = intel_dp->DP;
2187
2188 /*
2189 * DDI code has a strict mode set sequence and we should try to respect
2190 * it, otherwise we might hang the machine in many different ways. So we
2191 * really should be disabling the port only on a complete crtc_disable
2192 * sequence. This function is just called under two conditions on DDI
2193 * code:
2194 * - Link train failed while doing crtc_enable, and on this case we
2195 * really should respect the mode set sequence and wait for a
2196 * crtc_disable.
2197 * - Someone turned the monitor off and intel_dp_check_link_status
2198 * called us. We don't need to disable the whole port on this case, so
2199 * when someone turns the monitor on again,
2200 * intel_ddi_prepare_link_retrain will take care of redoing the link
2201 * train.
2202 */
2203 if (HAS_DDI(dev))
2204 return;
2205
2206 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2207 return;
2208
2209 DRM_DEBUG_KMS("\n");
2210
2211 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2212 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2213 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2214 } else {
2215 DP &= ~DP_LINK_TRAIN_MASK;
2216 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2217 }
2218 POSTING_READ(intel_dp->output_reg);
2219
2220 /* We don't really know why we're doing this */
2221 intel_wait_for_vblank(dev, intel_crtc->pipe);
2222
2223 if (HAS_PCH_IBX(dev) &&
2224 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2225 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2226
2227 /* Hardware workaround: leaving our transcoder select
2228 * set to transcoder B while it's off will prevent the
2229 * corresponding HDMI output on transcoder A.
2230 *
2231 * Combine this with another hardware workaround:
2232 * transcoder select bit can only be cleared while the
2233 * port is enabled.
2234 */
2235 DP &= ~DP_PIPEB_SELECT;
2236 I915_WRITE(intel_dp->output_reg, DP);
2237
2238 /* Changes to enable or select take place the vblank
2239 * after being written.
2240 */
2241 if (WARN_ON(crtc == NULL)) {
2242 /* We should never try to disable a port without a crtc
2243 * attached. For paranoia keep the code around for a
2244 * bit. */
2245 POSTING_READ(intel_dp->output_reg);
2246 msleep(50);
2247 } else
2248 intel_wait_for_vblank(dev, intel_crtc->pipe);
2249 }
2250
2251 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2252 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2253 POSTING_READ(intel_dp->output_reg);
2254 msleep(intel_dp->panel_power_down_delay);
2255 }
2256
2257 static bool
2258 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2259 {
2260 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2261
2262 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2263 sizeof(intel_dp->dpcd)) == 0)
2264 return false; /* aux transfer failed */
2265
2266 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2267 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2268 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2269
2270 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2271 return false; /* DPCD not present */
2272
2273 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2274 DP_DWN_STRM_PORT_PRESENT))
2275 return true; /* native DP sink */
2276
2277 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2278 return true; /* no per-port downstream info */
2279
2280 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2281 intel_dp->downstream_ports,
2282 DP_MAX_DOWNSTREAM_PORTS) == 0)
2283 return false; /* downstream port status fetch failed */
2284
2285 return true;
2286 }
2287
2288 static void
2289 intel_dp_probe_oui(struct intel_dp *intel_dp)
2290 {
2291 u8 buf[3];
2292
2293 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2294 return;
2295
2296 ironlake_edp_panel_vdd_on(intel_dp);
2297
2298 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2299 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2300 buf[0], buf[1], buf[2]);
2301
2302 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2303 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2304 buf[0], buf[1], buf[2]);
2305
2306 ironlake_edp_panel_vdd_off(intel_dp, false);
2307 }
2308
2309 static bool
2310 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2311 {
2312 int ret;
2313
2314 ret = intel_dp_aux_native_read_retry(intel_dp,
2315 DP_DEVICE_SERVICE_IRQ_VECTOR,
2316 sink_irq_vector, 1);
2317 if (!ret)
2318 return false;
2319
2320 return true;
2321 }
2322
2323 static void
2324 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2325 {
2326 /* NAK by default */
2327 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2328 }
2329
2330 /*
2331 * According to DP spec
2332 * 5.1.2:
2333 * 1. Read DPCD
2334 * 2. Configure link according to Receiver Capabilities
2335 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2336 * 4. Check link status on receipt of hot-plug interrupt
2337 */
2338
2339 void
2340 intel_dp_check_link_status(struct intel_dp *intel_dp)
2341 {
2342 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2343 u8 sink_irq_vector;
2344 u8 link_status[DP_LINK_STATUS_SIZE];
2345
2346 if (!intel_encoder->connectors_active)
2347 return;
2348
2349 if (WARN_ON(!intel_encoder->base.crtc))
2350 return;
2351
2352 /* Try to read receiver status if the link appears to be up */
2353 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2354 intel_dp_link_down(intel_dp);
2355 return;
2356 }
2357
2358 /* Now read the DPCD to see if it's actually running */
2359 if (!intel_dp_get_dpcd(intel_dp)) {
2360 intel_dp_link_down(intel_dp);
2361 return;
2362 }
2363
2364 /* Try to read the source of the interrupt */
2365 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2366 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2367 /* Clear interrupt source */
2368 intel_dp_aux_native_write_1(intel_dp,
2369 DP_DEVICE_SERVICE_IRQ_VECTOR,
2370 sink_irq_vector);
2371
2372 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2373 intel_dp_handle_test_request(intel_dp);
2374 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2375 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2376 }
2377
2378 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2379 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2380 drm_get_encoder_name(&intel_encoder->base));
2381 intel_dp_start_link_train(intel_dp);
2382 intel_dp_complete_link_train(intel_dp);
2383 intel_dp_stop_link_train(intel_dp);
2384 }
2385 }
2386
2387 /* XXX this is probably wrong for multiple downstream ports */
2388 static enum drm_connector_status
2389 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2390 {
2391 uint8_t *dpcd = intel_dp->dpcd;
2392 bool hpd;
2393 uint8_t type;
2394
2395 if (!intel_dp_get_dpcd(intel_dp))
2396 return connector_status_disconnected;
2397
2398 /* if there's no downstream port, we're done */
2399 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2400 return connector_status_connected;
2401
2402 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2403 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2404 if (hpd) {
2405 uint8_t reg;
2406 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2407 &reg, 1))
2408 return connector_status_unknown;
2409 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2410 : connector_status_disconnected;
2411 }
2412
2413 /* If no HPD, poke DDC gently */
2414 if (drm_probe_ddc(&intel_dp->adapter))
2415 return connector_status_connected;
2416
2417 /* Well we tried, say unknown for unreliable port types */
2418 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2419 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2420 return connector_status_unknown;
2421
2422 /* Anything else is out of spec, warn and ignore */
2423 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2424 return connector_status_disconnected;
2425 }
2426
2427 static enum drm_connector_status
2428 ironlake_dp_detect(struct intel_dp *intel_dp)
2429 {
2430 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2431 struct drm_i915_private *dev_priv = dev->dev_private;
2432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2433 enum drm_connector_status status;
2434
2435 /* Can't disconnect eDP, but you can close the lid... */
2436 if (is_edp(intel_dp)) {
2437 status = intel_panel_detect(dev);
2438 if (status == connector_status_unknown)
2439 status = connector_status_connected;
2440 return status;
2441 }
2442
2443 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2444 return connector_status_disconnected;
2445
2446 return intel_dp_detect_dpcd(intel_dp);
2447 }
2448
2449 static enum drm_connector_status
2450 g4x_dp_detect(struct intel_dp *intel_dp)
2451 {
2452 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2455 uint32_t bit;
2456
2457 /* Can't disconnect eDP, but you can close the lid... */
2458 if (is_edp(intel_dp)) {
2459 enum drm_connector_status status;
2460
2461 status = intel_panel_detect(dev);
2462 if (status == connector_status_unknown)
2463 status = connector_status_connected;
2464 return status;
2465 }
2466
2467 switch (intel_dig_port->port) {
2468 case PORT_B:
2469 bit = PORTB_HOTPLUG_LIVE_STATUS;
2470 break;
2471 case PORT_C:
2472 bit = PORTC_HOTPLUG_LIVE_STATUS;
2473 break;
2474 case PORT_D:
2475 bit = PORTD_HOTPLUG_LIVE_STATUS;
2476 break;
2477 default:
2478 return connector_status_unknown;
2479 }
2480
2481 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2482 return connector_status_disconnected;
2483
2484 return intel_dp_detect_dpcd(intel_dp);
2485 }
2486
2487 static struct edid *
2488 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2489 {
2490 struct intel_connector *intel_connector = to_intel_connector(connector);
2491
2492 /* use cached edid if we have one */
2493 if (intel_connector->edid) {
2494 struct edid *edid;
2495 int size;
2496
2497 /* invalid edid */
2498 if (IS_ERR(intel_connector->edid))
2499 return NULL;
2500
2501 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2502 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2503 if (!edid)
2504 return NULL;
2505
2506 return edid;
2507 }
2508
2509 return drm_get_edid(connector, adapter);
2510 }
2511
2512 static int
2513 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2514 {
2515 struct intel_connector *intel_connector = to_intel_connector(connector);
2516
2517 /* use cached edid if we have one */
2518 if (intel_connector->edid) {
2519 /* invalid edid */
2520 if (IS_ERR(intel_connector->edid))
2521 return 0;
2522
2523 return intel_connector_update_modes(connector,
2524 intel_connector->edid);
2525 }
2526
2527 return intel_ddc_get_modes(connector, adapter);
2528 }
2529
2530 static enum drm_connector_status
2531 intel_dp_detect(struct drm_connector *connector, bool force)
2532 {
2533 struct intel_dp *intel_dp = intel_attached_dp(connector);
2534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2535 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2536 struct drm_device *dev = connector->dev;
2537 enum drm_connector_status status;
2538 struct edid *edid = NULL;
2539
2540 intel_dp->has_audio = false;
2541
2542 if (HAS_PCH_SPLIT(dev))
2543 status = ironlake_dp_detect(intel_dp);
2544 else
2545 status = g4x_dp_detect(intel_dp);
2546
2547 if (status != connector_status_connected)
2548 return status;
2549
2550 intel_dp_probe_oui(intel_dp);
2551
2552 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2553 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2554 } else {
2555 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2556 if (edid) {
2557 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2558 kfree(edid);
2559 }
2560 }
2561
2562 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2563 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2564 return connector_status_connected;
2565 }
2566
2567 static int intel_dp_get_modes(struct drm_connector *connector)
2568 {
2569 struct intel_dp *intel_dp = intel_attached_dp(connector);
2570 struct intel_connector *intel_connector = to_intel_connector(connector);
2571 struct drm_device *dev = connector->dev;
2572 int ret;
2573
2574 /* We should parse the EDID data and find out if it has an audio sink
2575 */
2576
2577 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2578 if (ret)
2579 return ret;
2580
2581 /* if eDP has no EDID, fall back to fixed mode */
2582 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2583 struct drm_display_mode *mode;
2584 mode = drm_mode_duplicate(dev,
2585 intel_connector->panel.fixed_mode);
2586 if (mode) {
2587 drm_mode_probed_add(connector, mode);
2588 return 1;
2589 }
2590 }
2591 return 0;
2592 }
2593
2594 static bool
2595 intel_dp_detect_audio(struct drm_connector *connector)
2596 {
2597 struct intel_dp *intel_dp = intel_attached_dp(connector);
2598 struct edid *edid;
2599 bool has_audio = false;
2600
2601 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2602 if (edid) {
2603 has_audio = drm_detect_monitor_audio(edid);
2604 kfree(edid);
2605 }
2606
2607 return has_audio;
2608 }
2609
2610 static int
2611 intel_dp_set_property(struct drm_connector *connector,
2612 struct drm_property *property,
2613 uint64_t val)
2614 {
2615 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2616 struct intel_connector *intel_connector = to_intel_connector(connector);
2617 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2618 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2619 int ret;
2620
2621 ret = drm_object_property_set_value(&connector->base, property, val);
2622 if (ret)
2623 return ret;
2624
2625 if (property == dev_priv->force_audio_property) {
2626 int i = val;
2627 bool has_audio;
2628
2629 if (i == intel_dp->force_audio)
2630 return 0;
2631
2632 intel_dp->force_audio = i;
2633
2634 if (i == HDMI_AUDIO_AUTO)
2635 has_audio = intel_dp_detect_audio(connector);
2636 else
2637 has_audio = (i == HDMI_AUDIO_ON);
2638
2639 if (has_audio == intel_dp->has_audio)
2640 return 0;
2641
2642 intel_dp->has_audio = has_audio;
2643 goto done;
2644 }
2645
2646 if (property == dev_priv->broadcast_rgb_property) {
2647 bool old_auto = intel_dp->color_range_auto;
2648 uint32_t old_range = intel_dp->color_range;
2649
2650 switch (val) {
2651 case INTEL_BROADCAST_RGB_AUTO:
2652 intel_dp->color_range_auto = true;
2653 break;
2654 case INTEL_BROADCAST_RGB_FULL:
2655 intel_dp->color_range_auto = false;
2656 intel_dp->color_range = 0;
2657 break;
2658 case INTEL_BROADCAST_RGB_LIMITED:
2659 intel_dp->color_range_auto = false;
2660 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2661 break;
2662 default:
2663 return -EINVAL;
2664 }
2665
2666 if (old_auto == intel_dp->color_range_auto &&
2667 old_range == intel_dp->color_range)
2668 return 0;
2669
2670 goto done;
2671 }
2672
2673 if (is_edp(intel_dp) &&
2674 property == connector->dev->mode_config.scaling_mode_property) {
2675 if (val == DRM_MODE_SCALE_NONE) {
2676 DRM_DEBUG_KMS("no scaling not supported\n");
2677 return -EINVAL;
2678 }
2679
2680 if (intel_connector->panel.fitting_mode == val) {
2681 /* the eDP scaling property is not changed */
2682 return 0;
2683 }
2684 intel_connector->panel.fitting_mode = val;
2685
2686 goto done;
2687 }
2688
2689 return -EINVAL;
2690
2691 done:
2692 if (intel_encoder->base.crtc)
2693 intel_crtc_restore_mode(intel_encoder->base.crtc);
2694
2695 return 0;
2696 }
2697
2698 static void
2699 intel_dp_connector_destroy(struct drm_connector *connector)
2700 {
2701 struct intel_connector *intel_connector = to_intel_connector(connector);
2702
2703 if (!IS_ERR_OR_NULL(intel_connector->edid))
2704 kfree(intel_connector->edid);
2705
2706 /* Can't call is_edp() since the encoder may have been destroyed
2707 * already. */
2708 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2709 intel_panel_fini(&intel_connector->panel);
2710
2711 drm_sysfs_connector_remove(connector);
2712 drm_connector_cleanup(connector);
2713 kfree(connector);
2714 }
2715
2716 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2717 {
2718 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2719 struct intel_dp *intel_dp = &intel_dig_port->dp;
2720 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2721
2722 i2c_del_adapter(&intel_dp->adapter);
2723 drm_encoder_cleanup(encoder);
2724 if (is_edp(intel_dp)) {
2725 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2726 mutex_lock(&dev->mode_config.mutex);
2727 ironlake_panel_vdd_off_sync(intel_dp);
2728 mutex_unlock(&dev->mode_config.mutex);
2729 }
2730 kfree(intel_dig_port);
2731 }
2732
2733 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2734 .mode_set = intel_dp_mode_set,
2735 };
2736
2737 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2738 .dpms = intel_connector_dpms,
2739 .detect = intel_dp_detect,
2740 .fill_modes = drm_helper_probe_single_connector_modes,
2741 .set_property = intel_dp_set_property,
2742 .destroy = intel_dp_connector_destroy,
2743 };
2744
2745 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2746 .get_modes = intel_dp_get_modes,
2747 .mode_valid = intel_dp_mode_valid,
2748 .best_encoder = intel_best_encoder,
2749 };
2750
2751 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2752 .destroy = intel_dp_encoder_destroy,
2753 };
2754
2755 static void
2756 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2757 {
2758 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2759
2760 intel_dp_check_link_status(intel_dp);
2761 }
2762
2763 /* Return which DP Port should be selected for Transcoder DP control */
2764 int
2765 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2766 {
2767 struct drm_device *dev = crtc->dev;
2768 struct intel_encoder *intel_encoder;
2769 struct intel_dp *intel_dp;
2770
2771 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2772 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2773
2774 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2775 intel_encoder->type == INTEL_OUTPUT_EDP)
2776 return intel_dp->output_reg;
2777 }
2778
2779 return -1;
2780 }
2781
2782 /* check the VBT to see whether the eDP is on DP-D port */
2783 bool intel_dpd_is_edp(struct drm_device *dev)
2784 {
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786 struct child_device_config *p_child;
2787 int i;
2788
2789 if (!dev_priv->vbt.child_dev_num)
2790 return false;
2791
2792 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2793 p_child = dev_priv->vbt.child_dev + i;
2794
2795 if (p_child->dvo_port == PORT_IDPD &&
2796 p_child->device_type == DEVICE_TYPE_eDP)
2797 return true;
2798 }
2799 return false;
2800 }
2801
2802 static void
2803 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2804 {
2805 struct intel_connector *intel_connector = to_intel_connector(connector);
2806
2807 intel_attach_force_audio_property(connector);
2808 intel_attach_broadcast_rgb_property(connector);
2809 intel_dp->color_range_auto = true;
2810
2811 if (is_edp(intel_dp)) {
2812 drm_mode_create_scaling_mode_property(connector->dev);
2813 drm_object_attach_property(
2814 &connector->base,
2815 connector->dev->mode_config.scaling_mode_property,
2816 DRM_MODE_SCALE_ASPECT);
2817 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2818 }
2819 }
2820
2821 static void
2822 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2823 struct intel_dp *intel_dp,
2824 struct edp_power_seq *out)
2825 {
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct edp_power_seq cur, vbt, spec, final;
2828 u32 pp_on, pp_off, pp_div, pp;
2829 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2830
2831 if (HAS_PCH_SPLIT(dev)) {
2832 pp_control_reg = PCH_PP_CONTROL;
2833 pp_on_reg = PCH_PP_ON_DELAYS;
2834 pp_off_reg = PCH_PP_OFF_DELAYS;
2835 pp_div_reg = PCH_PP_DIVISOR;
2836 } else {
2837 pp_control_reg = PIPEA_PP_CONTROL;
2838 pp_on_reg = PIPEA_PP_ON_DELAYS;
2839 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2840 pp_div_reg = PIPEA_PP_DIVISOR;
2841 }
2842
2843 /* Workaround: Need to write PP_CONTROL with the unlock key as
2844 * the very first thing. */
2845 pp = ironlake_get_pp_control(intel_dp);
2846 I915_WRITE(pp_control_reg, pp);
2847
2848 pp_on = I915_READ(pp_on_reg);
2849 pp_off = I915_READ(pp_off_reg);
2850 pp_div = I915_READ(pp_div_reg);
2851
2852 /* Pull timing values out of registers */
2853 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2854 PANEL_POWER_UP_DELAY_SHIFT;
2855
2856 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2857 PANEL_LIGHT_ON_DELAY_SHIFT;
2858
2859 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2860 PANEL_LIGHT_OFF_DELAY_SHIFT;
2861
2862 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2863 PANEL_POWER_DOWN_DELAY_SHIFT;
2864
2865 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2866 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2867
2868 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2869 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2870
2871 vbt = dev_priv->vbt.edp_pps;
2872
2873 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2874 * our hw here, which are all in 100usec. */
2875 spec.t1_t3 = 210 * 10;
2876 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2877 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2878 spec.t10 = 500 * 10;
2879 /* This one is special and actually in units of 100ms, but zero
2880 * based in the hw (so we need to add 100 ms). But the sw vbt
2881 * table multiplies it with 1000 to make it in units of 100usec,
2882 * too. */
2883 spec.t11_t12 = (510 + 100) * 10;
2884
2885 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2886 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2887
2888 /* Use the max of the register settings and vbt. If both are
2889 * unset, fall back to the spec limits. */
2890 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2891 spec.field : \
2892 max(cur.field, vbt.field))
2893 assign_final(t1_t3);
2894 assign_final(t8);
2895 assign_final(t9);
2896 assign_final(t10);
2897 assign_final(t11_t12);
2898 #undef assign_final
2899
2900 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2901 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2902 intel_dp->backlight_on_delay = get_delay(t8);
2903 intel_dp->backlight_off_delay = get_delay(t9);
2904 intel_dp->panel_power_down_delay = get_delay(t10);
2905 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2906 #undef get_delay
2907
2908 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2909 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2910 intel_dp->panel_power_cycle_delay);
2911
2912 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2913 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2914
2915 if (out)
2916 *out = final;
2917 }
2918
2919 static void
2920 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2921 struct intel_dp *intel_dp,
2922 struct edp_power_seq *seq)
2923 {
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925 u32 pp_on, pp_off, pp_div, port_sel = 0;
2926 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2927 int pp_on_reg, pp_off_reg, pp_div_reg;
2928
2929 if (HAS_PCH_SPLIT(dev)) {
2930 pp_on_reg = PCH_PP_ON_DELAYS;
2931 pp_off_reg = PCH_PP_OFF_DELAYS;
2932 pp_div_reg = PCH_PP_DIVISOR;
2933 } else {
2934 pp_on_reg = PIPEA_PP_ON_DELAYS;
2935 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2936 pp_div_reg = PIPEA_PP_DIVISOR;
2937 }
2938
2939 /* And finally store the new values in the power sequencer. */
2940 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2941 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2942 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2943 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2944 /* Compute the divisor for the pp clock, simply match the Bspec
2945 * formula. */
2946 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2947 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2948 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2949
2950 /* Haswell doesn't have any port selection bits for the panel
2951 * power sequencer any more. */
2952 if (IS_VALLEYVIEW(dev)) {
2953 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2954 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2955 if (dp_to_dig_port(intel_dp)->port == PORT_A)
2956 port_sel = PANEL_POWER_PORT_DP_A;
2957 else
2958 port_sel = PANEL_POWER_PORT_DP_D;
2959 }
2960
2961 pp_on |= port_sel;
2962
2963 I915_WRITE(pp_on_reg, pp_on);
2964 I915_WRITE(pp_off_reg, pp_off);
2965 I915_WRITE(pp_div_reg, pp_div);
2966
2967 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2968 I915_READ(pp_on_reg),
2969 I915_READ(pp_off_reg),
2970 I915_READ(pp_div_reg));
2971 }
2972
2973 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
2974 struct intel_connector *intel_connector)
2975 {
2976 struct drm_connector *connector = &intel_connector->base;
2977 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2978 struct drm_device *dev = intel_dig_port->base.base.dev;
2979 struct drm_i915_private *dev_priv = dev->dev_private;
2980 struct drm_display_mode *fixed_mode = NULL;
2981 struct edp_power_seq power_seq = { 0 };
2982 bool has_dpcd;
2983 struct drm_display_mode *scan;
2984 struct edid *edid;
2985
2986 if (!is_edp(intel_dp))
2987 return true;
2988
2989 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2990
2991 /* Cache DPCD and EDID for edp. */
2992 ironlake_edp_panel_vdd_on(intel_dp);
2993 has_dpcd = intel_dp_get_dpcd(intel_dp);
2994 ironlake_edp_panel_vdd_off(intel_dp, false);
2995
2996 if (has_dpcd) {
2997 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2998 dev_priv->no_aux_handshake =
2999 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3000 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3001 } else {
3002 /* if this fails, presume the device is a ghost */
3003 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3004 return false;
3005 }
3006
3007 /* We now know it's not a ghost, init power sequence regs. */
3008 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3009 &power_seq);
3010
3011 ironlake_edp_panel_vdd_on(intel_dp);
3012 edid = drm_get_edid(connector, &intel_dp->adapter);
3013 if (edid) {
3014 if (drm_add_edid_modes(connector, edid)) {
3015 drm_mode_connector_update_edid_property(connector,
3016 edid);
3017 drm_edid_to_eld(connector, edid);
3018 } else {
3019 kfree(edid);
3020 edid = ERR_PTR(-EINVAL);
3021 }
3022 } else {
3023 edid = ERR_PTR(-ENOENT);
3024 }
3025 intel_connector->edid = edid;
3026
3027 /* prefer fixed mode from EDID if available */
3028 list_for_each_entry(scan, &connector->probed_modes, head) {
3029 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3030 fixed_mode = drm_mode_duplicate(dev, scan);
3031 break;
3032 }
3033 }
3034
3035 /* fallback to VBT if available for eDP */
3036 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3037 fixed_mode = drm_mode_duplicate(dev,
3038 dev_priv->vbt.lfp_lvds_vbt_mode);
3039 if (fixed_mode)
3040 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3041 }
3042
3043 ironlake_edp_panel_vdd_off(intel_dp, false);
3044
3045 intel_panel_init(&intel_connector->panel, fixed_mode);
3046 intel_panel_setup_backlight(connector);
3047
3048 return true;
3049 }
3050
3051 bool
3052 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3053 struct intel_connector *intel_connector)
3054 {
3055 struct drm_connector *connector = &intel_connector->base;
3056 struct intel_dp *intel_dp = &intel_dig_port->dp;
3057 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3058 struct drm_device *dev = intel_encoder->base.dev;
3059 struct drm_i915_private *dev_priv = dev->dev_private;
3060 enum port port = intel_dig_port->port;
3061 const char *name = NULL;
3062 int type, error;
3063
3064 /* Preserve the current hw state. */
3065 intel_dp->DP = I915_READ(intel_dp->output_reg);
3066 intel_dp->attached_connector = intel_connector;
3067
3068 type = DRM_MODE_CONNECTOR_DisplayPort;
3069 /*
3070 * FIXME : We need to initialize built-in panels before external panels.
3071 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3072 */
3073 switch (port) {
3074 case PORT_A:
3075 type = DRM_MODE_CONNECTOR_eDP;
3076 break;
3077 case PORT_C:
3078 if (IS_VALLEYVIEW(dev))
3079 type = DRM_MODE_CONNECTOR_eDP;
3080 break;
3081 case PORT_D:
3082 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3083 type = DRM_MODE_CONNECTOR_eDP;
3084 break;
3085 default: /* silence GCC warning */
3086 break;
3087 }
3088
3089 /*
3090 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3091 * for DP the encoder type can be set by the caller to
3092 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3093 */
3094 if (type == DRM_MODE_CONNECTOR_eDP)
3095 intel_encoder->type = INTEL_OUTPUT_EDP;
3096
3097 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3098 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3099 port_name(port));
3100
3101 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3102 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3103
3104 connector->interlace_allowed = true;
3105 connector->doublescan_allowed = 0;
3106
3107 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3108 ironlake_panel_vdd_work);
3109
3110 intel_connector_attach_encoder(intel_connector, intel_encoder);
3111 drm_sysfs_connector_add(connector);
3112
3113 if (HAS_DDI(dev))
3114 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3115 else
3116 intel_connector->get_hw_state = intel_connector_get_hw_state;
3117
3118 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3119 if (HAS_DDI(dev)) {
3120 switch (intel_dig_port->port) {
3121 case PORT_A:
3122 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3123 break;
3124 case PORT_B:
3125 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3126 break;
3127 case PORT_C:
3128 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3129 break;
3130 case PORT_D:
3131 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3132 break;
3133 default:
3134 BUG();
3135 }
3136 }
3137
3138 /* Set up the DDC bus. */
3139 switch (port) {
3140 case PORT_A:
3141 intel_encoder->hpd_pin = HPD_PORT_A;
3142 name = "DPDDC-A";
3143 break;
3144 case PORT_B:
3145 intel_encoder->hpd_pin = HPD_PORT_B;
3146 name = "DPDDC-B";
3147 break;
3148 case PORT_C:
3149 intel_encoder->hpd_pin = HPD_PORT_C;
3150 name = "DPDDC-C";
3151 break;
3152 case PORT_D:
3153 intel_encoder->hpd_pin = HPD_PORT_D;
3154 name = "DPDDC-D";
3155 break;
3156 default:
3157 BUG();
3158 }
3159
3160 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3161 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3162 error, port_name(port));
3163
3164 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3165 i2c_del_adapter(&intel_dp->adapter);
3166 if (is_edp(intel_dp)) {
3167 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3168 mutex_lock(&dev->mode_config.mutex);
3169 ironlake_panel_vdd_off_sync(intel_dp);
3170 mutex_unlock(&dev->mode_config.mutex);
3171 }
3172 drm_sysfs_connector_remove(connector);
3173 drm_connector_cleanup(connector);
3174 return false;
3175 }
3176
3177 intel_dp_add_properties(intel_dp, connector);
3178
3179 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3180 * 0xd. Failure to do so will result in spurious interrupts being
3181 * generated on the port when a cable is not attached.
3182 */
3183 if (IS_G4X(dev) && !IS_GM45(dev)) {
3184 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3185 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3186 }
3187
3188 return true;
3189 }
3190
3191 void
3192 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3193 {
3194 struct intel_digital_port *intel_dig_port;
3195 struct intel_encoder *intel_encoder;
3196 struct drm_encoder *encoder;
3197 struct intel_connector *intel_connector;
3198
3199 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3200 if (!intel_dig_port)
3201 return;
3202
3203 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3204 if (!intel_connector) {
3205 kfree(intel_dig_port);
3206 return;
3207 }
3208
3209 intel_encoder = &intel_dig_port->base;
3210 encoder = &intel_encoder->base;
3211
3212 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3213 DRM_MODE_ENCODER_TMDS);
3214 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3215
3216 intel_encoder->compute_config = intel_dp_compute_config;
3217 intel_encoder->enable = intel_enable_dp;
3218 intel_encoder->pre_enable = intel_pre_enable_dp;
3219 intel_encoder->disable = intel_disable_dp;
3220 intel_encoder->post_disable = intel_post_disable_dp;
3221 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3222 intel_encoder->get_config = intel_dp_get_config;
3223 if (IS_VALLEYVIEW(dev))
3224 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3225
3226 intel_dig_port->port = port;
3227 intel_dig_port->dp.output_reg = output_reg;
3228
3229 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3230 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3231 intel_encoder->cloneable = false;
3232 intel_encoder->hot_plug = intel_dp_hot_plug;
3233
3234 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3235 drm_encoder_cleanup(encoder);
3236 kfree(intel_dig_port);
3237 kfree(intel_connector);
3238 }
3239 }
Linux kernel - Deliverables
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