2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
45 #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46 #define IS_PCH_eDP(i) ((i)->is_pch_edp)
49 struct intel_encoder base
;
52 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
58 struct i2c_adapter adapter
;
59 struct i2c_algo_dp_aux_data algo
;
62 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
65 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
67 return container_of(encoder
, struct intel_dp
, base
.base
);
70 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
72 return container_of(intel_attached_encoder(connector
),
73 struct intel_dp
, base
);
76 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
77 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
78 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
81 intel_edp_link_config (struct intel_encoder
*intel_encoder
,
82 int *lane_num
, int *link_bw
)
84 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
86 *lane_num
= intel_dp
->lane_count
;
87 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
89 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
94 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
96 int max_lane_count
= 4;
98 if (intel_dp
->dpcd
[0] >= 0x11) {
99 max_lane_count
= intel_dp
->dpcd
[2] & 0x1f;
100 switch (max_lane_count
) {
101 case 1: case 2: case 4:
107 return max_lane_count
;
111 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
113 int max_link_bw
= intel_dp
->dpcd
[1];
115 switch (max_link_bw
) {
116 case DP_LINK_BW_1_62
:
120 max_link_bw
= DP_LINK_BW_1_62
;
127 intel_dp_link_clock(uint8_t link_bw
)
129 if (link_bw
== DP_LINK_BW_2_7
)
135 /* I think this is a fiction */
137 intel_dp_link_required(struct drm_device
*dev
, struct intel_dp
*intel_dp
, int pixel_clock
)
139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
141 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
142 return (pixel_clock
* dev_priv
->edp_bpp
) / 8;
144 return pixel_clock
* 3;
148 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
150 return (max_link_clock
* max_lanes
* 8) / 10;
154 intel_dp_mode_valid(struct drm_connector
*connector
,
155 struct drm_display_mode
*mode
)
157 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
158 struct drm_device
*dev
= connector
->dev
;
159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
160 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
161 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
163 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
164 dev_priv
->panel_fixed_mode
) {
165 if (mode
->hdisplay
> dev_priv
->panel_fixed_mode
->hdisplay
)
168 if (mode
->vdisplay
> dev_priv
->panel_fixed_mode
->vdisplay
)
172 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
173 which are outside spec tolerances but somehow work by magic */
174 if (!IS_eDP(intel_dp
) &&
175 (intel_dp_link_required(connector
->dev
, intel_dp
, mode
->clock
)
176 > intel_dp_max_data_rate(max_link_clock
, max_lanes
)))
177 return MODE_CLOCK_HIGH
;
179 if (mode
->clock
< 10000)
180 return MODE_CLOCK_LOW
;
186 pack_aux(uint8_t *src
, int src_bytes
)
193 for (i
= 0; i
< src_bytes
; i
++)
194 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
199 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
204 for (i
= 0; i
< dst_bytes
; i
++)
205 dst
[i
] = src
>> ((3-i
) * 8);
208 /* hrawclock is 1/4 the FSB frequency */
210 intel_hrawclk(struct drm_device
*dev
)
212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
215 clkcfg
= I915_READ(CLKCFG
);
216 switch (clkcfg
& CLKCFG_FSB_MASK
) {
225 case CLKCFG_FSB_1067
:
227 case CLKCFG_FSB_1333
:
229 /* these two are just a guess; one of them might be right */
230 case CLKCFG_FSB_1600
:
231 case CLKCFG_FSB_1600_ALT
:
239 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
240 uint8_t *send
, int send_bytes
,
241 uint8_t *recv
, int recv_size
)
243 uint32_t output_reg
= intel_dp
->output_reg
;
244 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
246 uint32_t ch_ctl
= output_reg
+ 0x10;
247 uint32_t ch_data
= ch_ctl
+ 4;
251 uint32_t aux_clock_divider
;
254 /* The clock divider is based off the hrawclk,
255 * and would like to run at 2MHz. So, take the
256 * hrawclk value and divide by 2 and use that
258 * Note that PCH attached eDP panels should use a 125MHz input
261 if (IS_eDP(intel_dp
) && !IS_PCH_eDP(intel_dp
)) {
263 aux_clock_divider
= 200; /* SNB eDP input clock at 400Mhz */
265 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
266 } else if (HAS_PCH_SPLIT(dev
))
267 aux_clock_divider
= 62; /* IRL input clock fixed at 125Mhz */
269 aux_clock_divider
= intel_hrawclk(dev
) / 2;
276 if (I915_READ(ch_ctl
) & DP_AUX_CH_CTL_SEND_BUSY
) {
277 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
282 /* Must try at least 3 times according to DP spec */
283 for (try = 0; try < 5; try++) {
284 /* Load the send data into the aux channel data registers */
285 for (i
= 0; i
< send_bytes
; i
+= 4)
286 I915_WRITE(ch_data
+ i
,
287 pack_aux(send
+ i
, send_bytes
- i
));
289 /* Send the command and wait for it to complete */
291 DP_AUX_CH_CTL_SEND_BUSY
|
292 DP_AUX_CH_CTL_TIME_OUT_400us
|
293 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
294 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
295 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
297 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
298 DP_AUX_CH_CTL_RECEIVE_ERROR
);
300 status
= I915_READ(ch_ctl
);
301 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
306 /* Clear done status and any errors */
310 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
311 DP_AUX_CH_CTL_RECEIVE_ERROR
);
312 if (status
& DP_AUX_CH_CTL_DONE
)
316 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
317 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
321 /* Check for timeout or receive error.
322 * Timeouts occur when the sink is not connected
324 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
325 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
329 /* Timeouts occur when the device isn't connected, so they're
330 * "normal" -- don't fill the kernel log with these */
331 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
332 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
336 /* Unload any bytes sent back from the other side */
337 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
338 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
339 if (recv_bytes
> recv_size
)
340 recv_bytes
= recv_size
;
342 for (i
= 0; i
< recv_bytes
; i
+= 4)
343 unpack_aux(I915_READ(ch_data
+ i
),
344 recv
+ i
, recv_bytes
- i
);
349 /* Write data to the aux channel in native mode */
351 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
352 uint16_t address
, uint8_t *send
, int send_bytes
)
361 msg
[0] = AUX_NATIVE_WRITE
<< 4;
362 msg
[1] = address
>> 8;
363 msg
[2] = address
& 0xff;
364 msg
[3] = send_bytes
- 1;
365 memcpy(&msg
[4], send
, send_bytes
);
366 msg_bytes
= send_bytes
+ 4;
368 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
371 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
373 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
381 /* Write a single byte to the aux channel in native mode */
383 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
384 uint16_t address
, uint8_t byte
)
386 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
389 /* read bytes from a native aux channel */
391 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
392 uint16_t address
, uint8_t *recv
, int recv_bytes
)
401 msg
[0] = AUX_NATIVE_READ
<< 4;
402 msg
[1] = address
>> 8;
403 msg
[2] = address
& 0xff;
404 msg
[3] = recv_bytes
- 1;
407 reply_bytes
= recv_bytes
+ 1;
410 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
417 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
418 memcpy(recv
, reply
+ 1, ret
- 1);
421 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
429 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
430 uint8_t write_byte
, uint8_t *read_byte
)
432 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
433 struct intel_dp
*intel_dp
= container_of(adapter
,
436 uint16_t address
= algo_data
->address
;
443 /* Set up the command byte */
444 if (mode
& MODE_I2C_READ
)
445 msg
[0] = AUX_I2C_READ
<< 4;
447 msg
[0] = AUX_I2C_WRITE
<< 4;
449 if (!(mode
& MODE_I2C_STOP
))
450 msg
[0] |= AUX_I2C_MOT
<< 4;
452 msg
[1] = address
>> 8;
474 ret
= intel_dp_aux_ch(intel_dp
,
478 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
481 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
482 case AUX_I2C_REPLY_ACK
:
483 if (mode
== MODE_I2C_READ
) {
484 *read_byte
= reply
[1];
486 return reply_bytes
- 1;
487 case AUX_I2C_REPLY_NACK
:
488 DRM_DEBUG_KMS("aux_ch nack\n");
490 case AUX_I2C_REPLY_DEFER
:
491 DRM_DEBUG_KMS("aux_ch defer\n");
495 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply
[0]);
502 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
503 struct intel_connector
*intel_connector
, const char *name
)
505 DRM_DEBUG_KMS("i2c_init %s\n", name
);
506 intel_dp
->algo
.running
= false;
507 intel_dp
->algo
.address
= 0;
508 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
510 memset(&intel_dp
->adapter
, '\0', sizeof (intel_dp
->adapter
));
511 intel_dp
->adapter
.owner
= THIS_MODULE
;
512 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
513 strncpy (intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
514 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
515 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
516 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
518 return i2c_dp_aux_add_bus(&intel_dp
->adapter
);
522 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
523 struct drm_display_mode
*adjusted_mode
)
525 struct drm_device
*dev
= encoder
->dev
;
526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
527 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
528 int lane_count
, clock
;
529 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
530 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
531 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
533 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
534 dev_priv
->panel_fixed_mode
) {
535 intel_fixed_panel_mode(dev_priv
->panel_fixed_mode
, adjusted_mode
);
536 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
537 mode
, adjusted_mode
);
539 * the mode->clock is used to calculate the Data&Link M/N
540 * of the pipe. For the eDP the fixed clock should be used.
542 mode
->clock
= dev_priv
->panel_fixed_mode
->clock
;
545 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
546 for (clock
= 0; clock
<= max_clock
; clock
++) {
547 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
549 if (intel_dp_link_required(encoder
->dev
, intel_dp
, mode
->clock
)
551 intel_dp
->link_bw
= bws
[clock
];
552 intel_dp
->lane_count
= lane_count
;
553 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
554 DRM_DEBUG_KMS("Display port link bw %02x lane "
555 "count %d clock %d\n",
556 intel_dp
->link_bw
, intel_dp
->lane_count
,
557 adjusted_mode
->clock
);
563 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
564 /* okay we failed just pick the highest */
565 intel_dp
->lane_count
= max_lane_count
;
566 intel_dp
->link_bw
= bws
[max_clock
];
567 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
568 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
569 "count %d clock %d\n",
570 intel_dp
->link_bw
, intel_dp
->lane_count
,
571 adjusted_mode
->clock
);
579 struct intel_dp_m_n
{
588 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
590 while (*num
> 0xffffff || *den
> 0xffffff) {
597 intel_dp_compute_m_n(int bpp
,
601 struct intel_dp_m_n
*m_n
)
604 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
605 m_n
->gmch_n
= link_clock
* nlanes
;
606 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
607 m_n
->link_m
= pixel_clock
;
608 m_n
->link_n
= link_clock
;
609 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
612 bool intel_pch_has_edp(struct drm_crtc
*crtc
)
614 struct drm_device
*dev
= crtc
->dev
;
615 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
616 struct drm_encoder
*encoder
;
618 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
619 struct intel_dp
*intel_dp
;
621 if (encoder
->crtc
!= crtc
)
624 intel_dp
= enc_to_intel_dp(encoder
);
625 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
)
626 return intel_dp
->is_pch_edp
;
632 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
633 struct drm_display_mode
*adjusted_mode
)
635 struct drm_device
*dev
= crtc
->dev
;
636 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
637 struct drm_encoder
*encoder
;
638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
639 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
640 int lane_count
= 4, bpp
= 24;
641 struct intel_dp_m_n m_n
;
644 * Find the lane count in the intel_encoder private
646 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
647 struct intel_dp
*intel_dp
;
649 if (encoder
->crtc
!= crtc
)
652 intel_dp
= enc_to_intel_dp(encoder
);
653 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
654 lane_count
= intel_dp
->lane_count
;
655 if (IS_PCH_eDP(intel_dp
))
656 bpp
= dev_priv
->edp_bpp
;
662 * Compute the GMCH and Link ratios. The '3' here is
663 * the number of bytes_per_pixel post-LUT, which we always
664 * set up for 8-bits of R/G/B, or 3 bytes total.
666 intel_dp_compute_m_n(bpp
, lane_count
,
667 mode
->clock
, adjusted_mode
->clock
, &m_n
);
669 if (HAS_PCH_SPLIT(dev
)) {
670 if (intel_crtc
->pipe
== 0) {
671 I915_WRITE(TRANSA_DATA_M1
,
672 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
674 I915_WRITE(TRANSA_DATA_N1
, m_n
.gmch_n
);
675 I915_WRITE(TRANSA_DP_LINK_M1
, m_n
.link_m
);
676 I915_WRITE(TRANSA_DP_LINK_N1
, m_n
.link_n
);
678 I915_WRITE(TRANSB_DATA_M1
,
679 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
681 I915_WRITE(TRANSB_DATA_N1
, m_n
.gmch_n
);
682 I915_WRITE(TRANSB_DP_LINK_M1
, m_n
.link_m
);
683 I915_WRITE(TRANSB_DP_LINK_N1
, m_n
.link_n
);
686 if (intel_crtc
->pipe
== 0) {
687 I915_WRITE(PIPEA_GMCH_DATA_M
,
688 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
690 I915_WRITE(PIPEA_GMCH_DATA_N
,
692 I915_WRITE(PIPEA_DP_LINK_M
, m_n
.link_m
);
693 I915_WRITE(PIPEA_DP_LINK_N
, m_n
.link_n
);
695 I915_WRITE(PIPEB_GMCH_DATA_M
,
696 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
698 I915_WRITE(PIPEB_GMCH_DATA_N
,
700 I915_WRITE(PIPEB_DP_LINK_M
, m_n
.link_m
);
701 I915_WRITE(PIPEB_DP_LINK_N
, m_n
.link_n
);
707 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
708 struct drm_display_mode
*adjusted_mode
)
710 struct drm_device
*dev
= encoder
->dev
;
711 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
712 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
715 intel_dp
->DP
= (DP_VOLTAGE_0_4
|
718 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
719 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
720 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
721 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
723 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
724 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
726 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
728 switch (intel_dp
->lane_count
) {
730 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
733 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
736 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
739 if (intel_dp
->has_audio
)
740 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
742 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
743 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
744 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
747 * Check for DPCD version > 1.1 and enhanced framing support
749 if (intel_dp
->dpcd
[0] >= 0x11 && (intel_dp
->dpcd
[2] & DP_ENHANCED_FRAME_CAP
)) {
750 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
751 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
754 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
755 if (intel_crtc
->pipe
== 1 && !HAS_PCH_CPT(dev
))
756 intel_dp
->DP
|= DP_PIPEB_SELECT
;
758 if (IS_eDP(intel_dp
)) {
759 /* don't miss out required setting for eDP */
760 intel_dp
->DP
|= DP_PLL_ENABLE
;
761 if (adjusted_mode
->clock
< 200000)
762 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
764 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
768 /* Returns true if the panel was already on when called */
769 static bool ironlake_edp_panel_on (struct drm_device
*dev
)
771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
774 if (I915_READ(PCH_PP_STATUS
) & PP_ON
)
777 pp
= I915_READ(PCH_PP_CONTROL
);
779 /* ILK workaround: disable reset around power sequence */
780 pp
&= ~PANEL_POWER_RESET
;
781 I915_WRITE(PCH_PP_CONTROL
, pp
);
782 POSTING_READ(PCH_PP_CONTROL
);
784 pp
|= PANEL_UNLOCK_REGS
| POWER_TARGET_ON
;
785 I915_WRITE(PCH_PP_CONTROL
, pp
);
787 if (wait_for(I915_READ(PCH_PP_STATUS
) & PP_ON
, 5000))
788 DRM_ERROR("panel on wait timed out: 0x%08x\n",
789 I915_READ(PCH_PP_STATUS
));
791 pp
&= ~(PANEL_UNLOCK_REGS
);
792 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
793 I915_WRITE(PCH_PP_CONTROL
, pp
);
794 POSTING_READ(PCH_PP_CONTROL
);
799 static void ironlake_edp_panel_off (struct drm_device
*dev
)
801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
804 pp
= I915_READ(PCH_PP_CONTROL
);
806 /* ILK workaround: disable reset around power sequence */
807 pp
&= ~PANEL_POWER_RESET
;
808 I915_WRITE(PCH_PP_CONTROL
, pp
);
809 POSTING_READ(PCH_PP_CONTROL
);
811 pp
&= ~POWER_TARGET_ON
;
812 I915_WRITE(PCH_PP_CONTROL
, pp
);
814 if (wait_for((I915_READ(PCH_PP_STATUS
) & PP_ON
) == 0, 5000))
815 DRM_ERROR("panel off wait timed out: 0x%08x\n",
816 I915_READ(PCH_PP_STATUS
));
818 /* Make sure VDD is enabled so DP AUX will work */
819 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
820 I915_WRITE(PCH_PP_CONTROL
, pp
);
821 POSTING_READ(PCH_PP_CONTROL
);
824 static void ironlake_edp_panel_vdd_on(struct drm_device
*dev
)
826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
829 pp
= I915_READ(PCH_PP_CONTROL
);
831 I915_WRITE(PCH_PP_CONTROL
, pp
);
832 POSTING_READ(PCH_PP_CONTROL
);
836 static void ironlake_edp_panel_vdd_off(struct drm_device
*dev
)
838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
841 pp
= I915_READ(PCH_PP_CONTROL
);
842 pp
&= ~EDP_FORCE_VDD
;
843 I915_WRITE(PCH_PP_CONTROL
, pp
);
844 POSTING_READ(PCH_PP_CONTROL
);
848 static void ironlake_edp_backlight_on (struct drm_device
*dev
)
850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
854 pp
= I915_READ(PCH_PP_CONTROL
);
855 pp
|= EDP_BLC_ENABLE
;
856 I915_WRITE(PCH_PP_CONTROL
, pp
);
859 static void ironlake_edp_backlight_off (struct drm_device
*dev
)
861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
865 pp
= I915_READ(PCH_PP_CONTROL
);
866 pp
&= ~EDP_BLC_ENABLE
;
867 I915_WRITE(PCH_PP_CONTROL
, pp
);
870 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
872 struct drm_device
*dev
= encoder
->dev
;
873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
877 dpa_ctl
= I915_READ(DP_A
);
878 dpa_ctl
&= ~DP_PLL_ENABLE
;
879 I915_WRITE(DP_A
, dpa_ctl
);
882 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
884 struct drm_device
*dev
= encoder
->dev
;
885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
888 dpa_ctl
= I915_READ(DP_A
);
889 dpa_ctl
|= DP_PLL_ENABLE
;
890 I915_WRITE(DP_A
, dpa_ctl
);
895 static void intel_dp_prepare(struct drm_encoder
*encoder
)
897 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
898 struct drm_device
*dev
= encoder
->dev
;
899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
900 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
902 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
903 ironlake_edp_panel_off(dev
);
904 ironlake_edp_backlight_off(dev
);
905 ironlake_edp_panel_vdd_on(dev
);
906 ironlake_edp_pll_on(encoder
);
908 if (dp_reg
& DP_PORT_EN
)
909 intel_dp_link_down(intel_dp
);
912 static void intel_dp_commit(struct drm_encoder
*encoder
)
914 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
915 struct drm_device
*dev
= encoder
->dev
;
917 intel_dp_start_link_train(intel_dp
);
919 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
920 ironlake_edp_panel_on(dev
);
922 intel_dp_complete_link_train(intel_dp
);
924 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
925 ironlake_edp_backlight_on(dev
);
929 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
931 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
932 struct drm_device
*dev
= encoder
->dev
;
933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
934 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
936 if (mode
!= DRM_MODE_DPMS_ON
) {
937 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
938 ironlake_edp_backlight_off(dev
);
939 ironlake_edp_panel_off(dev
);
941 if (dp_reg
& DP_PORT_EN
)
942 intel_dp_link_down(intel_dp
);
943 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
944 ironlake_edp_pll_off(encoder
);
946 if (!(dp_reg
& DP_PORT_EN
)) {
947 intel_dp_start_link_train(intel_dp
);
948 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
949 ironlake_edp_panel_on(dev
);
950 intel_dp_complete_link_train(intel_dp
);
951 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
952 ironlake_edp_backlight_on(dev
);
955 intel_dp
->dpms_mode
= mode
;
959 * Fetch AUX CH registers 0x202 - 0x207 which contain
960 * link status information
963 intel_dp_get_link_status(struct intel_dp
*intel_dp
)
967 ret
= intel_dp_aux_native_read(intel_dp
,
969 intel_dp
->link_status
, DP_LINK_STATUS_SIZE
);
970 if (ret
!= DP_LINK_STATUS_SIZE
)
976 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
979 return link_status
[r
- DP_LANE0_1_STATUS
];
983 intel_get_adjust_request_voltage(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
986 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
987 int s
= ((lane
& 1) ?
988 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
989 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
990 uint8_t l
= intel_dp_link_status(link_status
, i
);
992 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
996 intel_get_adjust_request_pre_emphasis(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
999 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
1000 int s
= ((lane
& 1) ?
1001 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1002 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1003 uint8_t l
= intel_dp_link_status(link_status
, i
);
1005 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1010 static char *voltage_names
[] = {
1011 "0.4V", "0.6V", "0.8V", "1.2V"
1013 static char *pre_emph_names
[] = {
1014 "0dB", "3.5dB", "6dB", "9.5dB"
1016 static char *link_train_names
[] = {
1017 "pattern 1", "pattern 2", "idle", "off"
1022 * These are source-specific values; current Intel hardware supports
1023 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1025 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1028 intel_dp_pre_emphasis_max(uint8_t voltage_swing
)
1030 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1031 case DP_TRAIN_VOLTAGE_SWING_400
:
1032 return DP_TRAIN_PRE_EMPHASIS_6
;
1033 case DP_TRAIN_VOLTAGE_SWING_600
:
1034 return DP_TRAIN_PRE_EMPHASIS_6
;
1035 case DP_TRAIN_VOLTAGE_SWING_800
:
1036 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1037 case DP_TRAIN_VOLTAGE_SWING_1200
:
1039 return DP_TRAIN_PRE_EMPHASIS_0
;
1044 intel_get_adjust_train(struct intel_dp
*intel_dp
)
1050 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1051 uint8_t this_v
= intel_get_adjust_request_voltage(intel_dp
->link_status
, lane
);
1052 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(intel_dp
->link_status
, lane
);
1060 if (v
>= I830_DP_VOLTAGE_MAX
)
1061 v
= I830_DP_VOLTAGE_MAX
| DP_TRAIN_MAX_SWING_REACHED
;
1063 if (p
>= intel_dp_pre_emphasis_max(v
))
1064 p
= intel_dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1066 for (lane
= 0; lane
< 4; lane
++)
1067 intel_dp
->train_set
[lane
] = v
| p
;
1071 intel_dp_signal_levels(uint8_t train_set
, int lane_count
)
1073 uint32_t signal_levels
= 0;
1075 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1076 case DP_TRAIN_VOLTAGE_SWING_400
:
1078 signal_levels
|= DP_VOLTAGE_0_4
;
1080 case DP_TRAIN_VOLTAGE_SWING_600
:
1081 signal_levels
|= DP_VOLTAGE_0_6
;
1083 case DP_TRAIN_VOLTAGE_SWING_800
:
1084 signal_levels
|= DP_VOLTAGE_0_8
;
1086 case DP_TRAIN_VOLTAGE_SWING_1200
:
1087 signal_levels
|= DP_VOLTAGE_1_2
;
1090 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1091 case DP_TRAIN_PRE_EMPHASIS_0
:
1093 signal_levels
|= DP_PRE_EMPHASIS_0
;
1095 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1096 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1098 case DP_TRAIN_PRE_EMPHASIS_6
:
1099 signal_levels
|= DP_PRE_EMPHASIS_6
;
1101 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1102 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1105 return signal_levels
;
1108 /* Gen6's DP voltage swing and pre-emphasis control */
1110 intel_gen6_edp_signal_levels(uint8_t train_set
)
1112 switch (train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|DP_TRAIN_PRE_EMPHASIS_MASK
)) {
1113 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1114 return EDP_LINK_TRAIN_400MV_0DB_SNB_B
;
1115 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1116 return EDP_LINK_TRAIN_400MV_6DB_SNB_B
;
1117 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1118 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B
;
1119 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1120 return EDP_LINK_TRAIN_800MV_0DB_SNB_B
;
1122 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1123 return EDP_LINK_TRAIN_400MV_0DB_SNB_B
;
1128 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1131 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
1132 int s
= (lane
& 1) * 4;
1133 uint8_t l
= intel_dp_link_status(link_status
, i
);
1135 return (l
>> s
) & 0xf;
1138 /* Check for clock recovery is done on all channels */
1140 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1143 uint8_t lane_status
;
1145 for (lane
= 0; lane
< lane_count
; lane
++) {
1146 lane_status
= intel_get_lane_status(link_status
, lane
);
1147 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1153 /* Check to see if channel eq is done on all channels */
1154 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1155 DP_LANE_CHANNEL_EQ_DONE|\
1156 DP_LANE_SYMBOL_LOCKED)
1158 intel_channel_eq_ok(struct intel_dp
*intel_dp
)
1161 uint8_t lane_status
;
1164 lane_align
= intel_dp_link_status(intel_dp
->link_status
,
1165 DP_LANE_ALIGN_STATUS_UPDATED
);
1166 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1168 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1169 lane_status
= intel_get_lane_status(intel_dp
->link_status
, lane
);
1170 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1177 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1178 uint32_t dp_reg_value
,
1179 uint8_t dp_train_pat
,
1182 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1184 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1187 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1188 POSTING_READ(intel_dp
->output_reg
);
1190 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1192 intel_dp_aux_native_write_1(intel_dp
,
1193 DP_TRAINING_PATTERN_SET
,
1196 ret
= intel_dp_aux_native_write(intel_dp
,
1197 DP_TRAINING_LANE0_SET
, intel_dp
->train_set
, 4);
1204 /* Enable corresponding port and start training pattern 1 */
1206 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1208 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1211 bool clock_recovery
= false;
1215 uint32_t DP
= intel_dp
->DP
;
1217 /* Write the link configuration data */
1218 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1219 intel_dp
->link_configuration
,
1220 DP_LINK_CONFIGURATION_SIZE
);
1223 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1224 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1226 DP
&= ~DP_LINK_TRAIN_MASK
;
1227 memset(intel_dp
->train_set
, 0, 4);
1230 clock_recovery
= false;
1232 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1233 uint32_t signal_levels
;
1234 if (IS_GEN6(dev
) && IS_eDP(intel_dp
)) {
1235 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1236 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1238 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0], intel_dp
->lane_count
);
1239 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1242 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1243 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1245 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1247 if (!intel_dp_set_link_train(intel_dp
, reg
,
1248 DP_TRAINING_PATTERN_1
, first
))
1251 /* Set training pattern 1 */
1254 if (!intel_dp_get_link_status(intel_dp
))
1257 if (intel_clock_recovery_ok(intel_dp
->link_status
, intel_dp
->lane_count
)) {
1258 clock_recovery
= true;
1262 /* Check to see if we've tried the max voltage */
1263 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1264 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1266 if (i
== intel_dp
->lane_count
)
1269 /* Check to see if we've tried the same voltage 5 times */
1270 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1276 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1278 /* Compute new intel_dp->train_set as requested by target */
1279 intel_get_adjust_train(intel_dp
);
1286 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1288 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1290 bool channel_eq
= false;
1293 uint32_t DP
= intel_dp
->DP
;
1295 /* channel equalization */
1299 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1300 uint32_t signal_levels
;
1302 if (IS_GEN6(dev
) && IS_eDP(intel_dp
)) {
1303 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1304 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1306 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0], intel_dp
->lane_count
);
1307 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1310 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1311 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1313 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1315 /* channel eq pattern */
1316 if (!intel_dp_set_link_train(intel_dp
, reg
,
1317 DP_TRAINING_PATTERN_2
,
1322 if (!intel_dp_get_link_status(intel_dp
))
1325 if (intel_channel_eq_ok(intel_dp
)) {
1334 /* Compute new intel_dp->train_set as requested by target */
1335 intel_get_adjust_train(intel_dp
);
1339 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1340 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1342 reg
= DP
| DP_LINK_TRAIN_OFF
;
1344 I915_WRITE(intel_dp
->output_reg
, reg
);
1345 POSTING_READ(intel_dp
->output_reg
);
1346 intel_dp_aux_native_write_1(intel_dp
,
1347 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1351 intel_dp_link_down(struct intel_dp
*intel_dp
)
1353 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1355 uint32_t DP
= intel_dp
->DP
;
1357 DRM_DEBUG_KMS("\n");
1359 if (IS_eDP(intel_dp
)) {
1360 DP
&= ~DP_PLL_ENABLE
;
1361 I915_WRITE(intel_dp
->output_reg
, DP
);
1362 POSTING_READ(intel_dp
->output_reg
);
1366 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
)) {
1367 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1368 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1369 POSTING_READ(intel_dp
->output_reg
);
1371 DP
&= ~DP_LINK_TRAIN_MASK
;
1372 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1373 POSTING_READ(intel_dp
->output_reg
);
1378 if (IS_eDP(intel_dp
))
1379 DP
|= DP_LINK_TRAIN_OFF
;
1380 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1381 POSTING_READ(intel_dp
->output_reg
);
1385 * According to DP spec
1388 * 2. Configure link according to Receiver Capabilities
1389 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1390 * 4. Check link status on receipt of hot-plug interrupt
1394 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
1396 if (!intel_dp
->base
.base
.crtc
)
1399 if (!intel_dp_get_link_status(intel_dp
)) {
1400 intel_dp_link_down(intel_dp
);
1404 if (!intel_channel_eq_ok(intel_dp
)) {
1405 intel_dp_start_link_train(intel_dp
);
1406 intel_dp_complete_link_train(intel_dp
);
1410 static enum drm_connector_status
1411 ironlake_dp_detect(struct drm_connector
*connector
)
1413 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1414 enum drm_connector_status status
;
1416 /* Panel needs power for AUX to work */
1417 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
1418 ironlake_edp_panel_vdd_on(connector
->dev
);
1419 status
= connector_status_disconnected
;
1420 if (intel_dp_aux_native_read(intel_dp
,
1421 0x000, intel_dp
->dpcd
,
1422 sizeof (intel_dp
->dpcd
)) == sizeof (intel_dp
->dpcd
))
1424 if (intel_dp
->dpcd
[0] != 0)
1425 status
= connector_status_connected
;
1427 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp
->dpcd
[0],
1428 intel_dp
->dpcd
[1], intel_dp
->dpcd
[2], intel_dp
->dpcd
[3]);
1429 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
1430 ironlake_edp_panel_vdd_off(connector
->dev
);
1435 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1437 * \return true if DP port is connected.
1438 * \return false if DP port is disconnected.
1440 static enum drm_connector_status
1441 intel_dp_detect(struct drm_connector
*connector
)
1443 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1444 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1447 enum drm_connector_status status
;
1449 intel_dp
->has_audio
= false;
1451 if (HAS_PCH_SPLIT(dev
))
1452 return ironlake_dp_detect(connector
);
1454 switch (intel_dp
->output_reg
) {
1456 bit
= DPB_HOTPLUG_INT_STATUS
;
1459 bit
= DPC_HOTPLUG_INT_STATUS
;
1462 bit
= DPD_HOTPLUG_INT_STATUS
;
1465 return connector_status_unknown
;
1468 temp
= I915_READ(PORT_HOTPLUG_STAT
);
1470 if ((temp
& bit
) == 0)
1471 return connector_status_disconnected
;
1473 status
= connector_status_disconnected
;
1474 if (intel_dp_aux_native_read(intel_dp
,
1475 0x000, intel_dp
->dpcd
,
1476 sizeof (intel_dp
->dpcd
)) == sizeof (intel_dp
->dpcd
))
1478 if (intel_dp
->dpcd
[0] != 0)
1479 status
= connector_status_connected
;
1484 static int intel_dp_get_modes(struct drm_connector
*connector
)
1486 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1487 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1491 /* We should parse the EDID data and find out if it has an audio sink
1494 ret
= intel_ddc_get_modes(connector
, intel_dp
->base
.ddc_bus
);
1496 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
1497 !dev_priv
->panel_fixed_mode
) {
1498 struct drm_display_mode
*newmode
;
1499 list_for_each_entry(newmode
, &connector
->probed_modes
,
1501 if (newmode
->type
& DRM_MODE_TYPE_PREFERRED
) {
1502 dev_priv
->panel_fixed_mode
=
1503 drm_mode_duplicate(dev
, newmode
);
1512 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1513 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
1514 if (dev_priv
->panel_fixed_mode
!= NULL
) {
1515 struct drm_display_mode
*mode
;
1516 mode
= drm_mode_duplicate(dev
, dev_priv
->panel_fixed_mode
);
1517 drm_mode_probed_add(connector
, mode
);
1525 intel_dp_destroy (struct drm_connector
*connector
)
1527 drm_sysfs_connector_remove(connector
);
1528 drm_connector_cleanup(connector
);
1532 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
1534 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1536 i2c_del_adapter(&intel_dp
->adapter
);
1537 drm_encoder_cleanup(encoder
);
1541 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
1542 .dpms
= intel_dp_dpms
,
1543 .mode_fixup
= intel_dp_mode_fixup
,
1544 .prepare
= intel_dp_prepare
,
1545 .mode_set
= intel_dp_mode_set
,
1546 .commit
= intel_dp_commit
,
1549 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
1550 .dpms
= drm_helper_connector_dpms
,
1551 .detect
= intel_dp_detect
,
1552 .fill_modes
= drm_helper_probe_single_connector_modes
,
1553 .destroy
= intel_dp_destroy
,
1556 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
1557 .get_modes
= intel_dp_get_modes
,
1558 .mode_valid
= intel_dp_mode_valid
,
1559 .best_encoder
= intel_best_encoder
,
1562 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
1563 .destroy
= intel_dp_encoder_destroy
,
1567 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
1569 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
1571 if (intel_dp
->dpms_mode
== DRM_MODE_DPMS_ON
)
1572 intel_dp_check_link_status(intel_dp
);
1575 /* Return which DP Port should be selected for Transcoder DP control */
1577 intel_trans_dp_port_sel (struct drm_crtc
*crtc
)
1579 struct drm_device
*dev
= crtc
->dev
;
1580 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1581 struct drm_encoder
*encoder
;
1583 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
1584 struct intel_dp
*intel_dp
;
1586 if (encoder
->crtc
!= crtc
)
1589 intel_dp
= enc_to_intel_dp(encoder
);
1590 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
)
1591 return intel_dp
->output_reg
;
1597 /* check the VBT to see whether the eDP is on DP-D port */
1598 bool intel_dpd_is_edp(struct drm_device
*dev
)
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 struct child_device_config
*p_child
;
1604 if (!dev_priv
->child_dev_num
)
1607 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
1608 p_child
= dev_priv
->child_dev
+ i
;
1610 if (p_child
->dvo_port
== PORT_IDPD
&&
1611 p_child
->device_type
== DEVICE_TYPE_eDP
)
1618 intel_dp_init(struct drm_device
*dev
, int output_reg
)
1620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1621 struct drm_connector
*connector
;
1622 struct intel_dp
*intel_dp
;
1623 struct intel_encoder
*intel_encoder
;
1624 struct intel_connector
*intel_connector
;
1625 const char *name
= NULL
;
1628 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
1632 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1633 if (!intel_connector
) {
1637 intel_encoder
= &intel_dp
->base
;
1639 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
1640 if (intel_dpd_is_edp(dev
))
1641 intel_dp
->is_pch_edp
= true;
1643 if (output_reg
== DP_A
|| IS_PCH_eDP(intel_dp
)) {
1644 type
= DRM_MODE_CONNECTOR_eDP
;
1645 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
1647 type
= DRM_MODE_CONNECTOR_DisplayPort
;
1648 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
1651 connector
= &intel_connector
->base
;
1652 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
1653 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
1655 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1657 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
1658 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
1659 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
1660 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
1661 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
1662 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
1664 if (IS_eDP(intel_dp
))
1665 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
1667 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
1668 connector
->interlace_allowed
= true;
1669 connector
->doublescan_allowed
= 0;
1671 intel_dp
->output_reg
= output_reg
;
1672 intel_dp
->has_audio
= false;
1673 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1675 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
1676 DRM_MODE_ENCODER_TMDS
);
1677 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
1679 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1680 drm_sysfs_connector_add(connector
);
1682 /* Set up the DDC bus. */
1683 switch (output_reg
) {
1689 dev_priv
->hotplug_supported_mask
|=
1690 HDMIB_HOTPLUG_INT_STATUS
;
1695 dev_priv
->hotplug_supported_mask
|=
1696 HDMIC_HOTPLUG_INT_STATUS
;
1701 dev_priv
->hotplug_supported_mask
|=
1702 HDMID_HOTPLUG_INT_STATUS
;
1707 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
1709 intel_encoder
->ddc_bus
= &intel_dp
->adapter
;
1710 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
1712 if (output_reg
== DP_A
|| IS_PCH_eDP(intel_dp
)) {
1713 /* initialize panel mode from VBT if available for eDP */
1714 if (dev_priv
->lfp_lvds_vbt_mode
) {
1715 dev_priv
->panel_fixed_mode
=
1716 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
1717 if (dev_priv
->panel_fixed_mode
) {
1718 dev_priv
->panel_fixed_mode
->type
|=
1719 DRM_MODE_TYPE_PREFERRED
;
1724 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1725 * 0xd. Failure to do so will result in spurious interrupts being
1726 * generated on the port when a cable is not attached.
1728 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1729 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1730 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);