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ba72fbcbbbc95bd44fae14cf78c5bbfdef858275
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 struct intel_dp {
46 struct intel_encoder base;
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
50 bool has_audio;
51 int force_audio;
52 uint32_t color_range;
53 int dpms_mode;
54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[8];
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59 bool is_pch_edp;
60 uint8_t train_set[4];
61 uint8_t link_status[DP_LINK_STATUS_SIZE];
62 };
63
64 /**
65 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
66 * @intel_dp: DP struct
67 *
68 * If a CPU or PCH DP output is attached to an eDP panel, this function
69 * will return true, and false otherwise.
70 */
71 static bool is_edp(struct intel_dp *intel_dp)
72 {
73 return intel_dp->base.type == INTEL_OUTPUT_EDP;
74 }
75
76 /**
77 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
78 * @intel_dp: DP struct
79 *
80 * Returns true if the given DP struct corresponds to a PCH DP port attached
81 * to an eDP panel, false otherwise. Helpful for determining whether we
82 * may need FDI resources for a given DP output or not.
83 */
84 static bool is_pch_edp(struct intel_dp *intel_dp)
85 {
86 return intel_dp->is_pch_edp;
87 }
88
89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
90 {
91 return container_of(encoder, struct intel_dp, base.base);
92 }
93
94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
95 {
96 return container_of(intel_attached_encoder(connector),
97 struct intel_dp, base);
98 }
99
100 /**
101 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
102 * @encoder: DRM encoder
103 *
104 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
105 * by intel_display.c.
106 */
107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
108 {
109 struct intel_dp *intel_dp;
110
111 if (!encoder)
112 return false;
113
114 intel_dp = enc_to_intel_dp(encoder);
115
116 return is_pch_edp(intel_dp);
117 }
118
119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_link_down(struct intel_dp *intel_dp);
122
123 void
124 intel_edp_link_config (struct intel_encoder *intel_encoder,
125 int *lane_num, int *link_bw)
126 {
127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
128
129 *lane_num = intel_dp->lane_count;
130 if (intel_dp->link_bw == DP_LINK_BW_1_62)
131 *link_bw = 162000;
132 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
133 *link_bw = 270000;
134 }
135
136 static int
137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
138 {
139 int max_lane_count = 4;
140
141 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
142 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
143 switch (max_lane_count) {
144 case 1: case 2: case 4:
145 break;
146 default:
147 max_lane_count = 4;
148 }
149 }
150 return max_lane_count;
151 }
152
153 static int
154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
155 {
156 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
157
158 switch (max_link_bw) {
159 case DP_LINK_BW_1_62:
160 case DP_LINK_BW_2_7:
161 break;
162 default:
163 max_link_bw = DP_LINK_BW_1_62;
164 break;
165 }
166 return max_link_bw;
167 }
168
169 static int
170 intel_dp_link_clock(uint8_t link_bw)
171 {
172 if (link_bw == DP_LINK_BW_2_7)
173 return 270000;
174 else
175 return 162000;
176 }
177
178 /* I think this is a fiction */
179 static int
180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
181 {
182 struct drm_i915_private *dev_priv = dev->dev_private;
183
184 if (is_edp(intel_dp))
185 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
186 else
187 return pixel_clock * 3;
188 }
189
190 static int
191 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
192 {
193 return (max_link_clock * max_lanes * 8) / 10;
194 }
195
196 static int
197 intel_dp_mode_valid(struct drm_connector *connector,
198 struct drm_display_mode *mode)
199 {
200 struct intel_dp *intel_dp = intel_attached_dp(connector);
201 struct drm_device *dev = connector->dev;
202 struct drm_i915_private *dev_priv = dev->dev_private;
203 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
204 int max_lanes = intel_dp_max_lane_count(intel_dp);
205
206 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
207 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
208 return MODE_PANEL;
209
210 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
211 return MODE_PANEL;
212 }
213
214 /* only refuse the mode on non eDP since we have seen some weird eDP panels
215 which are outside spec tolerances but somehow work by magic */
216 if (!is_edp(intel_dp) &&
217 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
218 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
219 return MODE_CLOCK_HIGH;
220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
224 return MODE_OK;
225 }
226
227 static uint32_t
228 pack_aux(uint8_t *src, int src_bytes)
229 {
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238 }
239
240 static void
241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242 {
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248 }
249
250 /* hrawclock is 1/4 the FSB frequency */
251 static int
252 intel_hrawclk(struct drm_device *dev)
253 {
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
257 clkcfg = I915_READ(CLKCFG);
258 switch (clkcfg & CLKCFG_FSB_MASK) {
259 case CLKCFG_FSB_400:
260 return 100;
261 case CLKCFG_FSB_533:
262 return 133;
263 case CLKCFG_FSB_667:
264 return 166;
265 case CLKCFG_FSB_800:
266 return 200;
267 case CLKCFG_FSB_1067:
268 return 266;
269 case CLKCFG_FSB_1333:
270 return 333;
271 /* these two are just a guess; one of them might be right */
272 case CLKCFG_FSB_1600:
273 case CLKCFG_FSB_1600_ALT:
274 return 400;
275 default:
276 return 133;
277 }
278 }
279
280 static int
281 intel_dp_aux_ch(struct intel_dp *intel_dp,
282 uint8_t *send, int send_bytes,
283 uint8_t *recv, int recv_size)
284 {
285 uint32_t output_reg = intel_dp->output_reg;
286 struct drm_device *dev = intel_dp->base.base.dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 uint32_t ch_ctl = output_reg + 0x10;
289 uint32_t ch_data = ch_ctl + 4;
290 int i;
291 int recv_bytes;
292 uint32_t status;
293 uint32_t aux_clock_divider;
294 int try, precharge;
295
296 /* The clock divider is based off the hrawclk,
297 * and would like to run at 2MHz. So, take the
298 * hrawclk value and divide by 2 and use that
299 *
300 * Note that PCH attached eDP panels should use a 125MHz input
301 * clock divider.
302 */
303 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
304 if (IS_GEN6(dev))
305 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
306 else
307 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
308 } else if (HAS_PCH_SPLIT(dev))
309 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
310 else
311 aux_clock_divider = intel_hrawclk(dev) / 2;
312
313 if (IS_GEN6(dev))
314 precharge = 3;
315 else
316 precharge = 5;
317
318 /* Try to wait for any previous AUX channel activity */
319 for (try = 0; try < 3; try++) {
320 status = I915_READ(ch_ctl);
321 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
322 break;
323 msleep(1);
324 }
325
326 if (try == 3) {
327 WARN(1, "dp_aux_ch not started status 0x%08x\n",
328 I915_READ(ch_ctl));
329 return -EBUSY;
330 }
331
332 /* Must try at least 3 times according to DP spec */
333 for (try = 0; try < 5; try++) {
334 /* Load the send data into the aux channel data registers */
335 for (i = 0; i < send_bytes; i += 4)
336 I915_WRITE(ch_data + i,
337 pack_aux(send + i, send_bytes - i));
338
339 /* Send the command and wait for it to complete */
340 I915_WRITE(ch_ctl,
341 DP_AUX_CH_CTL_SEND_BUSY |
342 DP_AUX_CH_CTL_TIME_OUT_400us |
343 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
344 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
345 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
346 DP_AUX_CH_CTL_DONE |
347 DP_AUX_CH_CTL_TIME_OUT_ERROR |
348 DP_AUX_CH_CTL_RECEIVE_ERROR);
349 for (;;) {
350 status = I915_READ(ch_ctl);
351 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
352 break;
353 udelay(100);
354 }
355
356 /* Clear done status and any errors */
357 I915_WRITE(ch_ctl,
358 status |
359 DP_AUX_CH_CTL_DONE |
360 DP_AUX_CH_CTL_TIME_OUT_ERROR |
361 DP_AUX_CH_CTL_RECEIVE_ERROR);
362 if (status & DP_AUX_CH_CTL_DONE)
363 break;
364 }
365
366 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
367 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
368 return -EBUSY;
369 }
370
371 /* Check for timeout or receive error.
372 * Timeouts occur when the sink is not connected
373 */
374 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
375 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
376 return -EIO;
377 }
378
379 /* Timeouts occur when the device isn't connected, so they're
380 * "normal" -- don't fill the kernel log with these */
381 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
382 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
383 return -ETIMEDOUT;
384 }
385
386 /* Unload any bytes sent back from the other side */
387 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
388 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
389 if (recv_bytes > recv_size)
390 recv_bytes = recv_size;
391
392 for (i = 0; i < recv_bytes; i += 4)
393 unpack_aux(I915_READ(ch_data + i),
394 recv + i, recv_bytes - i);
395
396 return recv_bytes;
397 }
398
399 /* Write data to the aux channel in native mode */
400 static int
401 intel_dp_aux_native_write(struct intel_dp *intel_dp,
402 uint16_t address, uint8_t *send, int send_bytes)
403 {
404 int ret;
405 uint8_t msg[20];
406 int msg_bytes;
407 uint8_t ack;
408
409 if (send_bytes > 16)
410 return -1;
411 msg[0] = AUX_NATIVE_WRITE << 4;
412 msg[1] = address >> 8;
413 msg[2] = address & 0xff;
414 msg[3] = send_bytes - 1;
415 memcpy(&msg[4], send, send_bytes);
416 msg_bytes = send_bytes + 4;
417 for (;;) {
418 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
419 if (ret < 0)
420 return ret;
421 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
422 break;
423 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
424 udelay(100);
425 else
426 return -EIO;
427 }
428 return send_bytes;
429 }
430
431 /* Write a single byte to the aux channel in native mode */
432 static int
433 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
434 uint16_t address, uint8_t byte)
435 {
436 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
437 }
438
439 /* read bytes from a native aux channel */
440 static int
441 intel_dp_aux_native_read(struct intel_dp *intel_dp,
442 uint16_t address, uint8_t *recv, int recv_bytes)
443 {
444 uint8_t msg[4];
445 int msg_bytes;
446 uint8_t reply[20];
447 int reply_bytes;
448 uint8_t ack;
449 int ret;
450
451 msg[0] = AUX_NATIVE_READ << 4;
452 msg[1] = address >> 8;
453 msg[2] = address & 0xff;
454 msg[3] = recv_bytes - 1;
455
456 msg_bytes = 4;
457 reply_bytes = recv_bytes + 1;
458
459 for (;;) {
460 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
461 reply, reply_bytes);
462 if (ret == 0)
463 return -EPROTO;
464 if (ret < 0)
465 return ret;
466 ack = reply[0];
467 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
468 memcpy(recv, reply + 1, ret - 1);
469 return ret - 1;
470 }
471 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
472 udelay(100);
473 else
474 return -EIO;
475 }
476 }
477
478 static int
479 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
480 uint8_t write_byte, uint8_t *read_byte)
481 {
482 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
483 struct intel_dp *intel_dp = container_of(adapter,
484 struct intel_dp,
485 adapter);
486 uint16_t address = algo_data->address;
487 uint8_t msg[5];
488 uint8_t reply[2];
489 unsigned retry;
490 int msg_bytes;
491 int reply_bytes;
492 int ret;
493
494 /* Set up the command byte */
495 if (mode & MODE_I2C_READ)
496 msg[0] = AUX_I2C_READ << 4;
497 else
498 msg[0] = AUX_I2C_WRITE << 4;
499
500 if (!(mode & MODE_I2C_STOP))
501 msg[0] |= AUX_I2C_MOT << 4;
502
503 msg[1] = address >> 8;
504 msg[2] = address;
505
506 switch (mode) {
507 case MODE_I2C_WRITE:
508 msg[3] = 0;
509 msg[4] = write_byte;
510 msg_bytes = 5;
511 reply_bytes = 1;
512 break;
513 case MODE_I2C_READ:
514 msg[3] = 0;
515 msg_bytes = 4;
516 reply_bytes = 2;
517 break;
518 default:
519 msg_bytes = 3;
520 reply_bytes = 1;
521 break;
522 }
523
524 for (retry = 0; retry < 5; retry++) {
525 ret = intel_dp_aux_ch(intel_dp,
526 msg, msg_bytes,
527 reply, reply_bytes);
528 if (ret < 0) {
529 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
530 return ret;
531 }
532
533 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
534 case AUX_NATIVE_REPLY_ACK:
535 /* I2C-over-AUX Reply field is only valid
536 * when paired with AUX ACK.
537 */
538 break;
539 case AUX_NATIVE_REPLY_NACK:
540 DRM_DEBUG_KMS("aux_ch native nack\n");
541 return -EREMOTEIO;
542 case AUX_NATIVE_REPLY_DEFER:
543 udelay(100);
544 continue;
545 default:
546 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
547 reply[0]);
548 return -EREMOTEIO;
549 }
550
551 switch (reply[0] & AUX_I2C_REPLY_MASK) {
552 case AUX_I2C_REPLY_ACK:
553 if (mode == MODE_I2C_READ) {
554 *read_byte = reply[1];
555 }
556 return reply_bytes - 1;
557 case AUX_I2C_REPLY_NACK:
558 DRM_DEBUG_KMS("aux_i2c nack\n");
559 return -EREMOTEIO;
560 case AUX_I2C_REPLY_DEFER:
561 DRM_DEBUG_KMS("aux_i2c defer\n");
562 udelay(100);
563 break;
564 default:
565 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
566 return -EREMOTEIO;
567 }
568 }
569
570 DRM_ERROR("too many retries, giving up\n");
571 return -EREMOTEIO;
572 }
573
574 static int
575 intel_dp_i2c_init(struct intel_dp *intel_dp,
576 struct intel_connector *intel_connector, const char *name)
577 {
578 DRM_DEBUG_KMS("i2c_init %s\n", name);
579 intel_dp->algo.running = false;
580 intel_dp->algo.address = 0;
581 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
582
583 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
584 intel_dp->adapter.owner = THIS_MODULE;
585 intel_dp->adapter.class = I2C_CLASS_DDC;
586 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
587 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
588 intel_dp->adapter.algo_data = &intel_dp->algo;
589 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
590
591 return i2c_dp_aux_add_bus(&intel_dp->adapter);
592 }
593
594 static bool
595 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
596 struct drm_display_mode *adjusted_mode)
597 {
598 struct drm_device *dev = encoder->dev;
599 struct drm_i915_private *dev_priv = dev->dev_private;
600 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
601 int lane_count, clock;
602 int max_lane_count = intel_dp_max_lane_count(intel_dp);
603 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
604 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
605
606 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
607 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
608 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
609 mode, adjusted_mode);
610 /*
611 * the mode->clock is used to calculate the Data&Link M/N
612 * of the pipe. For the eDP the fixed clock should be used.
613 */
614 mode->clock = dev_priv->panel_fixed_mode->clock;
615 }
616
617 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
618 for (clock = 0; clock <= max_clock; clock++) {
619 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
620
621 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
622 <= link_avail) {
623 intel_dp->link_bw = bws[clock];
624 intel_dp->lane_count = lane_count;
625 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
626 DRM_DEBUG_KMS("Display port link bw %02x lane "
627 "count %d clock %d\n",
628 intel_dp->link_bw, intel_dp->lane_count,
629 adjusted_mode->clock);
630 return true;
631 }
632 }
633 }
634
635 if (is_edp(intel_dp)) {
636 /* okay we failed just pick the highest */
637 intel_dp->lane_count = max_lane_count;
638 intel_dp->link_bw = bws[max_clock];
639 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
640 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
641 "count %d clock %d\n",
642 intel_dp->link_bw, intel_dp->lane_count,
643 adjusted_mode->clock);
644
645 return true;
646 }
647
648 return false;
649 }
650
651 struct intel_dp_m_n {
652 uint32_t tu;
653 uint32_t gmch_m;
654 uint32_t gmch_n;
655 uint32_t link_m;
656 uint32_t link_n;
657 };
658
659 static void
660 intel_reduce_ratio(uint32_t *num, uint32_t *den)
661 {
662 while (*num > 0xffffff || *den > 0xffffff) {
663 *num >>= 1;
664 *den >>= 1;
665 }
666 }
667
668 static void
669 intel_dp_compute_m_n(int bpp,
670 int nlanes,
671 int pixel_clock,
672 int link_clock,
673 struct intel_dp_m_n *m_n)
674 {
675 m_n->tu = 64;
676 m_n->gmch_m = (pixel_clock * bpp) >> 3;
677 m_n->gmch_n = link_clock * nlanes;
678 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
679 m_n->link_m = pixel_clock;
680 m_n->link_n = link_clock;
681 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
682 }
683
684 void
685 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
686 struct drm_display_mode *adjusted_mode)
687 {
688 struct drm_device *dev = crtc->dev;
689 struct drm_mode_config *mode_config = &dev->mode_config;
690 struct drm_encoder *encoder;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
693 int lane_count = 4, bpp = 24;
694 struct intel_dp_m_n m_n;
695 int pipe = intel_crtc->pipe;
696
697 /*
698 * Find the lane count in the intel_encoder private
699 */
700 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
701 struct intel_dp *intel_dp;
702
703 if (encoder->crtc != crtc)
704 continue;
705
706 intel_dp = enc_to_intel_dp(encoder);
707 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
708 lane_count = intel_dp->lane_count;
709 break;
710 } else if (is_edp(intel_dp)) {
711 lane_count = dev_priv->edp.lanes;
712 bpp = dev_priv->edp.bpp;
713 break;
714 }
715 }
716
717 /*
718 * Compute the GMCH and Link ratios. The '3' here is
719 * the number of bytes_per_pixel post-LUT, which we always
720 * set up for 8-bits of R/G/B, or 3 bytes total.
721 */
722 intel_dp_compute_m_n(bpp, lane_count,
723 mode->clock, adjusted_mode->clock, &m_n);
724
725 if (HAS_PCH_SPLIT(dev)) {
726 I915_WRITE(TRANSDATA_M1(pipe),
727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
728 m_n.gmch_m);
729 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
730 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
731 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
732 } else {
733 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
734 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
735 m_n.gmch_m);
736 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
737 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
738 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
739 }
740 }
741
742 static void
743 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
744 struct drm_display_mode *adjusted_mode)
745 {
746 struct drm_device *dev = encoder->dev;
747 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
748 struct drm_crtc *crtc = intel_dp->base.base.crtc;
749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
750
751 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
752 intel_dp->DP |= intel_dp->color_range;
753
754 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
755 intel_dp->DP |= DP_SYNC_HS_HIGH;
756 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
757 intel_dp->DP |= DP_SYNC_VS_HIGH;
758
759 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
760 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
761 else
762 intel_dp->DP |= DP_LINK_TRAIN_OFF;
763
764 switch (intel_dp->lane_count) {
765 case 1:
766 intel_dp->DP |= DP_PORT_WIDTH_1;
767 break;
768 case 2:
769 intel_dp->DP |= DP_PORT_WIDTH_2;
770 break;
771 case 4:
772 intel_dp->DP |= DP_PORT_WIDTH_4;
773 break;
774 }
775 if (intel_dp->has_audio)
776 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
777
778 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
779 intel_dp->link_configuration[0] = intel_dp->link_bw;
780 intel_dp->link_configuration[1] = intel_dp->lane_count;
781 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
782
783 /*
784 * Check for DPCD version > 1.1 and enhanced framing support
785 */
786 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
787 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
788 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
789 intel_dp->DP |= DP_ENHANCED_FRAMING;
790 }
791
792 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
793 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
794 intel_dp->DP |= DP_PIPEB_SELECT;
795
796 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
797 /* don't miss out required setting for eDP */
798 intel_dp->DP |= DP_PLL_ENABLE;
799 if (adjusted_mode->clock < 200000)
800 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
801 else
802 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
803 }
804 }
805
806 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
807 {
808 struct drm_device *dev = intel_dp->base.base.dev;
809 struct drm_i915_private *dev_priv = dev->dev_private;
810 u32 pp;
811
812 /*
813 * If the panel wasn't on, make sure there's not a currently
814 * active PP sequence before enabling AUX VDD.
815 */
816 if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
817 msleep(dev_priv->panel_t3);
818
819 pp = I915_READ(PCH_PP_CONTROL);
820 pp |= EDP_FORCE_VDD;
821 I915_WRITE(PCH_PP_CONTROL, pp);
822 POSTING_READ(PCH_PP_CONTROL);
823 }
824
825 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
826 {
827 struct drm_device *dev = intel_dp->base.base.dev;
828 struct drm_i915_private *dev_priv = dev->dev_private;
829 u32 pp;
830
831 pp = I915_READ(PCH_PP_CONTROL);
832 pp &= ~EDP_FORCE_VDD;
833 I915_WRITE(PCH_PP_CONTROL, pp);
834 POSTING_READ(PCH_PP_CONTROL);
835
836 /* Make sure sequencer is idle before allowing subsequent activity */
837 msleep(dev_priv->panel_t12);
838 }
839
840 /* Returns true if the panel was already on when called */
841 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
842 {
843 struct drm_device *dev = intel_dp->base.base.dev;
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
846
847 if (I915_READ(PCH_PP_STATUS) & PP_ON)
848 return true;
849
850 pp = I915_READ(PCH_PP_CONTROL);
851
852 /* ILK workaround: disable reset around power sequence */
853 pp &= ~PANEL_POWER_RESET;
854 I915_WRITE(PCH_PP_CONTROL, pp);
855 POSTING_READ(PCH_PP_CONTROL);
856
857 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
858 I915_WRITE(PCH_PP_CONTROL, pp);
859 POSTING_READ(PCH_PP_CONTROL);
860
861 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
862 5000))
863 DRM_ERROR("panel on wait timed out: 0x%08x\n",
864 I915_READ(PCH_PP_STATUS));
865
866 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
867 I915_WRITE(PCH_PP_CONTROL, pp);
868 POSTING_READ(PCH_PP_CONTROL);
869
870 return false;
871 }
872
873 static void ironlake_edp_panel_off (struct drm_device *dev)
874 {
875 struct drm_i915_private *dev_priv = dev->dev_private;
876 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
877 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
878
879 pp = I915_READ(PCH_PP_CONTROL);
880
881 /* ILK workaround: disable reset around power sequence */
882 pp &= ~PANEL_POWER_RESET;
883 I915_WRITE(PCH_PP_CONTROL, pp);
884 POSTING_READ(PCH_PP_CONTROL);
885
886 pp &= ~POWER_TARGET_ON;
887 I915_WRITE(PCH_PP_CONTROL, pp);
888 POSTING_READ(PCH_PP_CONTROL);
889
890 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
891 DRM_ERROR("panel off wait timed out: 0x%08x\n",
892 I915_READ(PCH_PP_STATUS));
893
894 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
895 I915_WRITE(PCH_PP_CONTROL, pp);
896 POSTING_READ(PCH_PP_CONTROL);
897 }
898
899 static void ironlake_edp_backlight_on (struct drm_device *dev)
900 {
901 struct drm_i915_private *dev_priv = dev->dev_private;
902 u32 pp;
903
904 DRM_DEBUG_KMS("\n");
905 /*
906 * If we enable the backlight right away following a panel power
907 * on, we may see slight flicker as the panel syncs with the eDP
908 * link. So delay a bit to make sure the image is solid before
909 * allowing it to appear.
910 */
911 msleep(300);
912 pp = I915_READ(PCH_PP_CONTROL);
913 pp |= EDP_BLC_ENABLE;
914 I915_WRITE(PCH_PP_CONTROL, pp);
915 }
916
917 static void ironlake_edp_backlight_off (struct drm_device *dev)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 u32 pp;
921
922 DRM_DEBUG_KMS("\n");
923 pp = I915_READ(PCH_PP_CONTROL);
924 pp &= ~EDP_BLC_ENABLE;
925 I915_WRITE(PCH_PP_CONTROL, pp);
926 }
927
928 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
929 {
930 struct drm_device *dev = encoder->dev;
931 struct drm_i915_private *dev_priv = dev->dev_private;
932 u32 dpa_ctl;
933
934 DRM_DEBUG_KMS("\n");
935 dpa_ctl = I915_READ(DP_A);
936 dpa_ctl |= DP_PLL_ENABLE;
937 I915_WRITE(DP_A, dpa_ctl);
938 POSTING_READ(DP_A);
939 udelay(200);
940 }
941
942 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
943 {
944 struct drm_device *dev = encoder->dev;
945 struct drm_i915_private *dev_priv = dev->dev_private;
946 u32 dpa_ctl;
947
948 dpa_ctl = I915_READ(DP_A);
949 dpa_ctl &= ~DP_PLL_ENABLE;
950 I915_WRITE(DP_A, dpa_ctl);
951 POSTING_READ(DP_A);
952 udelay(200);
953 }
954
955 /* If the sink supports it, try to set the power state appropriately */
956 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
957 {
958 int ret, i;
959
960 /* Should have a valid DPCD by this point */
961 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
962 return;
963
964 if (mode != DRM_MODE_DPMS_ON) {
965 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
966 DP_SET_POWER_D3);
967 if (ret != 1)
968 DRM_DEBUG_DRIVER("failed to write sink power state\n");
969 } else {
970 /*
971 * When turning on, we need to retry for 1ms to give the sink
972 * time to wake up.
973 */
974 for (i = 0; i < 3; i++) {
975 ret = intel_dp_aux_native_write_1(intel_dp,
976 DP_SET_POWER,
977 DP_SET_POWER_D0);
978 if (ret == 1)
979 break;
980 msleep(1);
981 }
982 }
983 }
984
985 static void intel_dp_prepare(struct drm_encoder *encoder)
986 {
987 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
988 struct drm_device *dev = encoder->dev;
989
990 /* Wake up the sink first */
991 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
992
993 if (is_edp(intel_dp)) {
994 ironlake_edp_backlight_off(dev);
995 ironlake_edp_panel_off(dev);
996 if (!is_pch_edp(intel_dp))
997 ironlake_edp_pll_on(encoder);
998 else
999 ironlake_edp_pll_off(encoder);
1000 }
1001 intel_dp_link_down(intel_dp);
1002 }
1003
1004 static void intel_dp_commit(struct drm_encoder *encoder)
1005 {
1006 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1007 struct drm_device *dev = encoder->dev;
1008
1009 if (is_edp(intel_dp))
1010 ironlake_edp_panel_vdd_on(intel_dp);
1011
1012 intel_dp_start_link_train(intel_dp);
1013
1014 if (is_edp(intel_dp)) {
1015 ironlake_edp_panel_on(intel_dp);
1016 ironlake_edp_panel_vdd_off(intel_dp);
1017 }
1018
1019 intel_dp_complete_link_train(intel_dp);
1020
1021 if (is_edp(intel_dp))
1022 ironlake_edp_backlight_on(dev);
1023
1024 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1025 }
1026
1027 static void
1028 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1029 {
1030 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1031 struct drm_device *dev = encoder->dev;
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1034
1035 if (mode != DRM_MODE_DPMS_ON) {
1036 if (is_edp(intel_dp))
1037 ironlake_edp_backlight_off(dev);
1038 intel_dp_sink_dpms(intel_dp, mode);
1039 intel_dp_link_down(intel_dp);
1040 if (is_edp(intel_dp))
1041 ironlake_edp_panel_off(dev);
1042 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1043 ironlake_edp_pll_off(encoder);
1044 } else {
1045 if (is_edp(intel_dp))
1046 ironlake_edp_panel_vdd_on(intel_dp);
1047 intel_dp_sink_dpms(intel_dp, mode);
1048 if (!(dp_reg & DP_PORT_EN)) {
1049 intel_dp_start_link_train(intel_dp);
1050 if (is_edp(intel_dp)) {
1051 ironlake_edp_panel_on(intel_dp);
1052 ironlake_edp_panel_vdd_off(intel_dp);
1053 }
1054 intel_dp_complete_link_train(intel_dp);
1055 }
1056 if (is_edp(intel_dp))
1057 ironlake_edp_backlight_on(dev);
1058 }
1059 intel_dp->dpms_mode = mode;
1060 }
1061
1062 /*
1063 * Native read with retry for link status and receiver capability reads for
1064 * cases where the sink may still be asleep.
1065 */
1066 static bool
1067 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1068 uint8_t *recv, int recv_bytes)
1069 {
1070 int ret, i;
1071
1072 /*
1073 * Sinks are *supposed* to come up within 1ms from an off state,
1074 * but we're also supposed to retry 3 times per the spec.
1075 */
1076 for (i = 0; i < 3; i++) {
1077 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1078 recv_bytes);
1079 if (ret == recv_bytes)
1080 return true;
1081 msleep(1);
1082 }
1083
1084 return false;
1085 }
1086
1087 /*
1088 * Fetch AUX CH registers 0x202 - 0x207 which contain
1089 * link status information
1090 */
1091 static bool
1092 intel_dp_get_link_status(struct intel_dp *intel_dp)
1093 {
1094 return intel_dp_aux_native_read_retry(intel_dp,
1095 DP_LANE0_1_STATUS,
1096 intel_dp->link_status,
1097 DP_LINK_STATUS_SIZE);
1098 }
1099
1100 static uint8_t
1101 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1102 int r)
1103 {
1104 return link_status[r - DP_LANE0_1_STATUS];
1105 }
1106
1107 static uint8_t
1108 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1109 int lane)
1110 {
1111 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1112 int s = ((lane & 1) ?
1113 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1114 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1115 uint8_t l = intel_dp_link_status(link_status, i);
1116
1117 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1118 }
1119
1120 static uint8_t
1121 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1122 int lane)
1123 {
1124 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1125 int s = ((lane & 1) ?
1126 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1127 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1128 uint8_t l = intel_dp_link_status(link_status, i);
1129
1130 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1131 }
1132
1133
1134 #if 0
1135 static char *voltage_names[] = {
1136 "0.4V", "0.6V", "0.8V", "1.2V"
1137 };
1138 static char *pre_emph_names[] = {
1139 "0dB", "3.5dB", "6dB", "9.5dB"
1140 };
1141 static char *link_train_names[] = {
1142 "pattern 1", "pattern 2", "idle", "off"
1143 };
1144 #endif
1145
1146 /*
1147 * These are source-specific values; current Intel hardware supports
1148 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1149 */
1150 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1151
1152 static uint8_t
1153 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1154 {
1155 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1156 case DP_TRAIN_VOLTAGE_SWING_400:
1157 return DP_TRAIN_PRE_EMPHASIS_6;
1158 case DP_TRAIN_VOLTAGE_SWING_600:
1159 return DP_TRAIN_PRE_EMPHASIS_6;
1160 case DP_TRAIN_VOLTAGE_SWING_800:
1161 return DP_TRAIN_PRE_EMPHASIS_3_5;
1162 case DP_TRAIN_VOLTAGE_SWING_1200:
1163 default:
1164 return DP_TRAIN_PRE_EMPHASIS_0;
1165 }
1166 }
1167
1168 static void
1169 intel_get_adjust_train(struct intel_dp *intel_dp)
1170 {
1171 uint8_t v = 0;
1172 uint8_t p = 0;
1173 int lane;
1174
1175 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1176 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1177 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1178
1179 if (this_v > v)
1180 v = this_v;
1181 if (this_p > p)
1182 p = this_p;
1183 }
1184
1185 if (v >= I830_DP_VOLTAGE_MAX)
1186 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1187
1188 if (p >= intel_dp_pre_emphasis_max(v))
1189 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1190
1191 for (lane = 0; lane < 4; lane++)
1192 intel_dp->train_set[lane] = v | p;
1193 }
1194
1195 static uint32_t
1196 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1197 {
1198 uint32_t signal_levels = 0;
1199
1200 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1201 case DP_TRAIN_VOLTAGE_SWING_400:
1202 default:
1203 signal_levels |= DP_VOLTAGE_0_4;
1204 break;
1205 case DP_TRAIN_VOLTAGE_SWING_600:
1206 signal_levels |= DP_VOLTAGE_0_6;
1207 break;
1208 case DP_TRAIN_VOLTAGE_SWING_800:
1209 signal_levels |= DP_VOLTAGE_0_8;
1210 break;
1211 case DP_TRAIN_VOLTAGE_SWING_1200:
1212 signal_levels |= DP_VOLTAGE_1_2;
1213 break;
1214 }
1215 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1216 case DP_TRAIN_PRE_EMPHASIS_0:
1217 default:
1218 signal_levels |= DP_PRE_EMPHASIS_0;
1219 break;
1220 case DP_TRAIN_PRE_EMPHASIS_3_5:
1221 signal_levels |= DP_PRE_EMPHASIS_3_5;
1222 break;
1223 case DP_TRAIN_PRE_EMPHASIS_6:
1224 signal_levels |= DP_PRE_EMPHASIS_6;
1225 break;
1226 case DP_TRAIN_PRE_EMPHASIS_9_5:
1227 signal_levels |= DP_PRE_EMPHASIS_9_5;
1228 break;
1229 }
1230 return signal_levels;
1231 }
1232
1233 /* Gen6's DP voltage swing and pre-emphasis control */
1234 static uint32_t
1235 intel_gen6_edp_signal_levels(uint8_t train_set)
1236 {
1237 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1238 DP_TRAIN_PRE_EMPHASIS_MASK);
1239 switch (signal_levels) {
1240 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1241 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1242 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1243 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1244 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1245 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1246 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1247 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1248 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1249 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1250 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1251 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1252 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1253 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1254 default:
1255 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1256 "0x%x\n", signal_levels);
1257 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1258 }
1259 }
1260
1261 static uint8_t
1262 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1263 int lane)
1264 {
1265 int i = DP_LANE0_1_STATUS + (lane >> 1);
1266 int s = (lane & 1) * 4;
1267 uint8_t l = intel_dp_link_status(link_status, i);
1268
1269 return (l >> s) & 0xf;
1270 }
1271
1272 /* Check for clock recovery is done on all channels */
1273 static bool
1274 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1275 {
1276 int lane;
1277 uint8_t lane_status;
1278
1279 for (lane = 0; lane < lane_count; lane++) {
1280 lane_status = intel_get_lane_status(link_status, lane);
1281 if ((lane_status & DP_LANE_CR_DONE) == 0)
1282 return false;
1283 }
1284 return true;
1285 }
1286
1287 /* Check to see if channel eq is done on all channels */
1288 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1289 DP_LANE_CHANNEL_EQ_DONE|\
1290 DP_LANE_SYMBOL_LOCKED)
1291 static bool
1292 intel_channel_eq_ok(struct intel_dp *intel_dp)
1293 {
1294 uint8_t lane_align;
1295 uint8_t lane_status;
1296 int lane;
1297
1298 lane_align = intel_dp_link_status(intel_dp->link_status,
1299 DP_LANE_ALIGN_STATUS_UPDATED);
1300 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1301 return false;
1302 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1303 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1304 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1305 return false;
1306 }
1307 return true;
1308 }
1309
1310 static bool
1311 intel_dp_set_link_train(struct intel_dp *intel_dp,
1312 uint32_t dp_reg_value,
1313 uint8_t dp_train_pat)
1314 {
1315 struct drm_device *dev = intel_dp->base.base.dev;
1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 int ret;
1318
1319 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1320 POSTING_READ(intel_dp->output_reg);
1321
1322 intel_dp_aux_native_write_1(intel_dp,
1323 DP_TRAINING_PATTERN_SET,
1324 dp_train_pat);
1325
1326 ret = intel_dp_aux_native_write(intel_dp,
1327 DP_TRAINING_LANE0_SET,
1328 intel_dp->train_set, 4);
1329 if (ret != 4)
1330 return false;
1331
1332 return true;
1333 }
1334
1335 /* Enable corresponding port and start training pattern 1 */
1336 static void
1337 intel_dp_start_link_train(struct intel_dp *intel_dp)
1338 {
1339 struct drm_device *dev = intel_dp->base.base.dev;
1340 struct drm_i915_private *dev_priv = dev->dev_private;
1341 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1342 int i;
1343 uint8_t voltage;
1344 bool clock_recovery = false;
1345 int tries;
1346 u32 reg;
1347 uint32_t DP = intel_dp->DP;
1348
1349 /*
1350 * On CPT we have to enable the port in training pattern 1, which
1351 * will happen below in intel_dp_set_link_train. Otherwise, enable
1352 * the port and wait for it to become active.
1353 */
1354 if (!HAS_PCH_CPT(dev)) {
1355 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1356 POSTING_READ(intel_dp->output_reg);
1357 intel_wait_for_vblank(dev, intel_crtc->pipe);
1358 }
1359
1360 /* Write the link configuration data */
1361 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1362 intel_dp->link_configuration,
1363 DP_LINK_CONFIGURATION_SIZE);
1364
1365 DP |= DP_PORT_EN;
1366 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1367 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1368 else
1369 DP &= ~DP_LINK_TRAIN_MASK;
1370 memset(intel_dp->train_set, 0, 4);
1371 voltage = 0xff;
1372 tries = 0;
1373 clock_recovery = false;
1374 for (;;) {
1375 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1376 uint32_t signal_levels;
1377 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1378 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1379 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1380 } else {
1381 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1382 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1383 }
1384
1385 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1386 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1387 else
1388 reg = DP | DP_LINK_TRAIN_PAT_1;
1389
1390 if (!intel_dp_set_link_train(intel_dp, reg,
1391 DP_TRAINING_PATTERN_1 |
1392 DP_LINK_SCRAMBLING_DISABLE))
1393 break;
1394 /* Set training pattern 1 */
1395
1396 udelay(100);
1397 if (!intel_dp_get_link_status(intel_dp))
1398 break;
1399
1400 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1401 clock_recovery = true;
1402 break;
1403 }
1404
1405 /* Check to see if we've tried the max voltage */
1406 for (i = 0; i < intel_dp->lane_count; i++)
1407 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1408 break;
1409 if (i == intel_dp->lane_count)
1410 break;
1411
1412 /* Check to see if we've tried the same voltage 5 times */
1413 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1414 ++tries;
1415 if (tries == 5)
1416 break;
1417 } else
1418 tries = 0;
1419 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1420
1421 /* Compute new intel_dp->train_set as requested by target */
1422 intel_get_adjust_train(intel_dp);
1423 }
1424
1425 intel_dp->DP = DP;
1426 }
1427
1428 static void
1429 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1430 {
1431 struct drm_device *dev = intel_dp->base.base.dev;
1432 struct drm_i915_private *dev_priv = dev->dev_private;
1433 bool channel_eq = false;
1434 int tries, cr_tries;
1435 u32 reg;
1436 uint32_t DP = intel_dp->DP;
1437
1438 /* channel equalization */
1439 tries = 0;
1440 cr_tries = 0;
1441 channel_eq = false;
1442 for (;;) {
1443 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1444 uint32_t signal_levels;
1445
1446 if (cr_tries > 5) {
1447 DRM_ERROR("failed to train DP, aborting\n");
1448 intel_dp_link_down(intel_dp);
1449 break;
1450 }
1451
1452 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1453 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1454 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1455 } else {
1456 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1457 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1458 }
1459
1460 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1461 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1462 else
1463 reg = DP | DP_LINK_TRAIN_PAT_2;
1464
1465 /* channel eq pattern */
1466 if (!intel_dp_set_link_train(intel_dp, reg,
1467 DP_TRAINING_PATTERN_2 |
1468 DP_LINK_SCRAMBLING_DISABLE))
1469 break;
1470
1471 udelay(400);
1472 if (!intel_dp_get_link_status(intel_dp))
1473 break;
1474
1475 /* Make sure clock is still ok */
1476 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1477 intel_dp_start_link_train(intel_dp);
1478 cr_tries++;
1479 continue;
1480 }
1481
1482 if (intel_channel_eq_ok(intel_dp)) {
1483 channel_eq = true;
1484 break;
1485 }
1486
1487 /* Try 5 times, then try clock recovery if that fails */
1488 if (tries > 5) {
1489 intel_dp_link_down(intel_dp);
1490 intel_dp_start_link_train(intel_dp);
1491 tries = 0;
1492 cr_tries++;
1493 continue;
1494 }
1495
1496 /* Compute new intel_dp->train_set as requested by target */
1497 intel_get_adjust_train(intel_dp);
1498 ++tries;
1499 }
1500
1501 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1502 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1503 else
1504 reg = DP | DP_LINK_TRAIN_OFF;
1505
1506 I915_WRITE(intel_dp->output_reg, reg);
1507 POSTING_READ(intel_dp->output_reg);
1508 intel_dp_aux_native_write_1(intel_dp,
1509 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1510 }
1511
1512 static void
1513 intel_dp_link_down(struct intel_dp *intel_dp)
1514 {
1515 struct drm_device *dev = intel_dp->base.base.dev;
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517 uint32_t DP = intel_dp->DP;
1518
1519 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1520 return;
1521
1522 DRM_DEBUG_KMS("\n");
1523
1524 if (is_edp(intel_dp)) {
1525 DP &= ~DP_PLL_ENABLE;
1526 I915_WRITE(intel_dp->output_reg, DP);
1527 POSTING_READ(intel_dp->output_reg);
1528 udelay(100);
1529 }
1530
1531 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1532 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1533 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1534 } else {
1535 DP &= ~DP_LINK_TRAIN_MASK;
1536 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1537 }
1538 POSTING_READ(intel_dp->output_reg);
1539
1540 msleep(17);
1541
1542 if (is_edp(intel_dp))
1543 DP |= DP_LINK_TRAIN_OFF;
1544
1545 if (!HAS_PCH_CPT(dev) &&
1546 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1547 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1548
1549 /* Hardware workaround: leaving our transcoder select
1550 * set to transcoder B while it's off will prevent the
1551 * corresponding HDMI output on transcoder A.
1552 *
1553 * Combine this with another hardware workaround:
1554 * transcoder select bit can only be cleared while the
1555 * port is enabled.
1556 */
1557 DP &= ~DP_PIPEB_SELECT;
1558 I915_WRITE(intel_dp->output_reg, DP);
1559
1560 /* Changes to enable or select take place the vblank
1561 * after being written.
1562 */
1563 if (crtc == NULL) {
1564 /* We can arrive here never having been attached
1565 * to a CRTC, for instance, due to inheriting
1566 * random state from the BIOS.
1567 *
1568 * If the pipe is not running, play safe and
1569 * wait for the clocks to stabilise before
1570 * continuing.
1571 */
1572 POSTING_READ(intel_dp->output_reg);
1573 msleep(50);
1574 } else
1575 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1576 }
1577
1578 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1579 POSTING_READ(intel_dp->output_reg);
1580 }
1581
1582 static bool
1583 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1584 {
1585 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1586 sizeof (intel_dp->dpcd)) &&
1587 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1588 return true;
1589 }
1590
1591 return false;
1592 }
1593
1594 /*
1595 * According to DP spec
1596 * 5.1.2:
1597 * 1. Read DPCD
1598 * 2. Configure link according to Receiver Capabilities
1599 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1600 * 4. Check link status on receipt of hot-plug interrupt
1601 */
1602
1603 static void
1604 intel_dp_check_link_status(struct intel_dp *intel_dp)
1605 {
1606 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1607 return;
1608
1609 if (!intel_dp->base.base.crtc)
1610 return;
1611
1612 /* Try to read receiver status if the link appears to be up */
1613 if (!intel_dp_get_link_status(intel_dp)) {
1614 intel_dp_link_down(intel_dp);
1615 return;
1616 }
1617
1618 /* Now read the DPCD to see if it's actually running */
1619 if (!intel_dp_get_dpcd(intel_dp)) {
1620 intel_dp_link_down(intel_dp);
1621 return;
1622 }
1623
1624 if (!intel_channel_eq_ok(intel_dp)) {
1625 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1626 drm_get_encoder_name(&intel_dp->base.base));
1627 intel_dp_start_link_train(intel_dp);
1628 intel_dp_complete_link_train(intel_dp);
1629 }
1630 }
1631
1632 static enum drm_connector_status
1633 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1634 {
1635 if (intel_dp_get_dpcd(intel_dp))
1636 return connector_status_connected;
1637 return connector_status_disconnected;
1638 }
1639
1640 static enum drm_connector_status
1641 ironlake_dp_detect(struct intel_dp *intel_dp)
1642 {
1643 enum drm_connector_status status;
1644
1645 /* Can't disconnect eDP, but you can close the lid... */
1646 if (is_edp(intel_dp)) {
1647 status = intel_panel_detect(intel_dp->base.base.dev);
1648 if (status == connector_status_unknown)
1649 status = connector_status_connected;
1650 return status;
1651 }
1652
1653 return intel_dp_detect_dpcd(intel_dp);
1654 }
1655
1656 static enum drm_connector_status
1657 g4x_dp_detect(struct intel_dp *intel_dp)
1658 {
1659 struct drm_device *dev = intel_dp->base.base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 uint32_t temp, bit;
1662
1663 switch (intel_dp->output_reg) {
1664 case DP_B:
1665 bit = DPB_HOTPLUG_INT_STATUS;
1666 break;
1667 case DP_C:
1668 bit = DPC_HOTPLUG_INT_STATUS;
1669 break;
1670 case DP_D:
1671 bit = DPD_HOTPLUG_INT_STATUS;
1672 break;
1673 default:
1674 return connector_status_unknown;
1675 }
1676
1677 temp = I915_READ(PORT_HOTPLUG_STAT);
1678
1679 if ((temp & bit) == 0)
1680 return connector_status_disconnected;
1681
1682 return intel_dp_detect_dpcd(intel_dp);
1683 }
1684
1685 /**
1686 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1687 *
1688 * \return true if DP port is connected.
1689 * \return false if DP port is disconnected.
1690 */
1691 static enum drm_connector_status
1692 intel_dp_detect(struct drm_connector *connector, bool force)
1693 {
1694 struct intel_dp *intel_dp = intel_attached_dp(connector);
1695 struct drm_device *dev = intel_dp->base.base.dev;
1696 enum drm_connector_status status;
1697 struct edid *edid = NULL;
1698
1699 intel_dp->has_audio = false;
1700 memset(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd));
1701
1702 if (HAS_PCH_SPLIT(dev))
1703 status = ironlake_dp_detect(intel_dp);
1704 else
1705 status = g4x_dp_detect(intel_dp);
1706
1707 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1708 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1709 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1710 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1711
1712 if (status != connector_status_connected)
1713 return status;
1714
1715 if (intel_dp->force_audio) {
1716 intel_dp->has_audio = intel_dp->force_audio > 0;
1717 } else {
1718 edid = drm_get_edid(connector, &intel_dp->adapter);
1719 if (edid) {
1720 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1721 connector->display_info.raw_edid = NULL;
1722 kfree(edid);
1723 }
1724 }
1725
1726 return connector_status_connected;
1727 }
1728
1729 static int intel_dp_get_modes(struct drm_connector *connector)
1730 {
1731 struct intel_dp *intel_dp = intel_attached_dp(connector);
1732 struct drm_device *dev = intel_dp->base.base.dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734 int ret;
1735
1736 /* We should parse the EDID data and find out if it has an audio sink
1737 */
1738
1739 ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1740 if (ret) {
1741 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1742 struct drm_display_mode *newmode;
1743 list_for_each_entry(newmode, &connector->probed_modes,
1744 head) {
1745 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1746 dev_priv->panel_fixed_mode =
1747 drm_mode_duplicate(dev, newmode);
1748 break;
1749 }
1750 }
1751 }
1752
1753 return ret;
1754 }
1755
1756 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1757 if (is_edp(intel_dp)) {
1758 if (dev_priv->panel_fixed_mode != NULL) {
1759 struct drm_display_mode *mode;
1760 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1761 drm_mode_probed_add(connector, mode);
1762 return 1;
1763 }
1764 }
1765 return 0;
1766 }
1767
1768 static bool
1769 intel_dp_detect_audio(struct drm_connector *connector)
1770 {
1771 struct intel_dp *intel_dp = intel_attached_dp(connector);
1772 struct edid *edid;
1773 bool has_audio = false;
1774
1775 edid = drm_get_edid(connector, &intel_dp->adapter);
1776 if (edid) {
1777 has_audio = drm_detect_monitor_audio(edid);
1778
1779 connector->display_info.raw_edid = NULL;
1780 kfree(edid);
1781 }
1782
1783 return has_audio;
1784 }
1785
1786 static int
1787 intel_dp_set_property(struct drm_connector *connector,
1788 struct drm_property *property,
1789 uint64_t val)
1790 {
1791 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1792 struct intel_dp *intel_dp = intel_attached_dp(connector);
1793 int ret;
1794
1795 ret = drm_connector_property_set_value(connector, property, val);
1796 if (ret)
1797 return ret;
1798
1799 if (property == dev_priv->force_audio_property) {
1800 int i = val;
1801 bool has_audio;
1802
1803 if (i == intel_dp->force_audio)
1804 return 0;
1805
1806 intel_dp->force_audio = i;
1807
1808 if (i == 0)
1809 has_audio = intel_dp_detect_audio(connector);
1810 else
1811 has_audio = i > 0;
1812
1813 if (has_audio == intel_dp->has_audio)
1814 return 0;
1815
1816 intel_dp->has_audio = has_audio;
1817 goto done;
1818 }
1819
1820 if (property == dev_priv->broadcast_rgb_property) {
1821 if (val == !!intel_dp->color_range)
1822 return 0;
1823
1824 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1825 goto done;
1826 }
1827
1828 return -EINVAL;
1829
1830 done:
1831 if (intel_dp->base.base.crtc) {
1832 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1833 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1834 crtc->x, crtc->y,
1835 crtc->fb);
1836 }
1837
1838 return 0;
1839 }
1840
1841 static void
1842 intel_dp_destroy (struct drm_connector *connector)
1843 {
1844 drm_sysfs_connector_remove(connector);
1845 drm_connector_cleanup(connector);
1846 kfree(connector);
1847 }
1848
1849 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1850 {
1851 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1852
1853 i2c_del_adapter(&intel_dp->adapter);
1854 drm_encoder_cleanup(encoder);
1855 kfree(intel_dp);
1856 }
1857
1858 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1859 .dpms = intel_dp_dpms,
1860 .mode_fixup = intel_dp_mode_fixup,
1861 .prepare = intel_dp_prepare,
1862 .mode_set = intel_dp_mode_set,
1863 .commit = intel_dp_commit,
1864 };
1865
1866 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1867 .dpms = drm_helper_connector_dpms,
1868 .detect = intel_dp_detect,
1869 .fill_modes = drm_helper_probe_single_connector_modes,
1870 .set_property = intel_dp_set_property,
1871 .destroy = intel_dp_destroy,
1872 };
1873
1874 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1875 .get_modes = intel_dp_get_modes,
1876 .mode_valid = intel_dp_mode_valid,
1877 .best_encoder = intel_best_encoder,
1878 };
1879
1880 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1881 .destroy = intel_dp_encoder_destroy,
1882 };
1883
1884 static void
1885 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1886 {
1887 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1888
1889 intel_dp_check_link_status(intel_dp);
1890 }
1891
1892 /* Return which DP Port should be selected for Transcoder DP control */
1893 int
1894 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1895 {
1896 struct drm_device *dev = crtc->dev;
1897 struct drm_mode_config *mode_config = &dev->mode_config;
1898 struct drm_encoder *encoder;
1899
1900 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1901 struct intel_dp *intel_dp;
1902
1903 if (encoder->crtc != crtc)
1904 continue;
1905
1906 intel_dp = enc_to_intel_dp(encoder);
1907 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1908 return intel_dp->output_reg;
1909 }
1910
1911 return -1;
1912 }
1913
1914 /* check the VBT to see whether the eDP is on DP-D port */
1915 bool intel_dpd_is_edp(struct drm_device *dev)
1916 {
1917 struct drm_i915_private *dev_priv = dev->dev_private;
1918 struct child_device_config *p_child;
1919 int i;
1920
1921 if (!dev_priv->child_dev_num)
1922 return false;
1923
1924 for (i = 0; i < dev_priv->child_dev_num; i++) {
1925 p_child = dev_priv->child_dev + i;
1926
1927 if (p_child->dvo_port == PORT_IDPD &&
1928 p_child->device_type == DEVICE_TYPE_eDP)
1929 return true;
1930 }
1931 return false;
1932 }
1933
1934 static void
1935 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1936 {
1937 intel_attach_force_audio_property(connector);
1938 intel_attach_broadcast_rgb_property(connector);
1939 }
1940
1941 void
1942 intel_dp_init(struct drm_device *dev, int output_reg)
1943 {
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1945 struct drm_connector *connector;
1946 struct intel_dp *intel_dp;
1947 struct intel_encoder *intel_encoder;
1948 struct intel_connector *intel_connector;
1949 const char *name = NULL;
1950 int type;
1951
1952 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1953 if (!intel_dp)
1954 return;
1955
1956 intel_dp->output_reg = output_reg;
1957 intel_dp->dpms_mode = -1;
1958
1959 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1960 if (!intel_connector) {
1961 kfree(intel_dp);
1962 return;
1963 }
1964 intel_encoder = &intel_dp->base;
1965
1966 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1967 if (intel_dpd_is_edp(dev))
1968 intel_dp->is_pch_edp = true;
1969
1970 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1971 type = DRM_MODE_CONNECTOR_eDP;
1972 intel_encoder->type = INTEL_OUTPUT_EDP;
1973 } else {
1974 type = DRM_MODE_CONNECTOR_DisplayPort;
1975 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1976 }
1977
1978 connector = &intel_connector->base;
1979 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1980 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1981
1982 connector->polled = DRM_CONNECTOR_POLL_HPD;
1983
1984 if (output_reg == DP_B || output_reg == PCH_DP_B)
1985 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1986 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1987 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1988 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1989 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1990
1991 if (is_edp(intel_dp))
1992 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1993
1994 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1995 connector->interlace_allowed = true;
1996 connector->doublescan_allowed = 0;
1997
1998 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1999 DRM_MODE_ENCODER_TMDS);
2000 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2001
2002 intel_connector_attach_encoder(intel_connector, intel_encoder);
2003 drm_sysfs_connector_add(connector);
2004
2005 /* Set up the DDC bus. */
2006 switch (output_reg) {
2007 case DP_A:
2008 name = "DPDDC-A";
2009 break;
2010 case DP_B:
2011 case PCH_DP_B:
2012 dev_priv->hotplug_supported_mask |=
2013 HDMIB_HOTPLUG_INT_STATUS;
2014 name = "DPDDC-B";
2015 break;
2016 case DP_C:
2017 case PCH_DP_C:
2018 dev_priv->hotplug_supported_mask |=
2019 HDMIC_HOTPLUG_INT_STATUS;
2020 name = "DPDDC-C";
2021 break;
2022 case DP_D:
2023 case PCH_DP_D:
2024 dev_priv->hotplug_supported_mask |=
2025 HDMID_HOTPLUG_INT_STATUS;
2026 name = "DPDDC-D";
2027 break;
2028 }
2029
2030 intel_dp_i2c_init(intel_dp, intel_connector, name);
2031
2032 /* Cache some DPCD data in the eDP case */
2033 if (is_edp(intel_dp)) {
2034 bool ret;
2035 u32 pp_on, pp_div;
2036
2037 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2038 pp_div = I915_READ(PCH_PP_DIVISOR);
2039
2040 /* Get T3 & T12 values (note: VESA not bspec terminology) */
2041 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
2042 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
2043 dev_priv->panel_t12 = pp_div & 0xf;
2044 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
2045
2046 ironlake_edp_panel_vdd_on(intel_dp);
2047 ret = intel_dp_get_dpcd(intel_dp);
2048 ironlake_edp_panel_vdd_off(intel_dp);
2049 if (ret) {
2050 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2051 dev_priv->no_aux_handshake =
2052 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2053 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2054 } else {
2055 /* if this fails, presume the device is a ghost */
2056 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2057 intel_dp_encoder_destroy(&intel_dp->base.base);
2058 intel_dp_destroy(&intel_connector->base);
2059 return;
2060 }
2061 }
2062
2063 intel_encoder->hot_plug = intel_dp_hot_plug;
2064
2065 if (is_edp(intel_dp)) {
2066 /* initialize panel mode from VBT if available for eDP */
2067 if (dev_priv->lfp_lvds_vbt_mode) {
2068 dev_priv->panel_fixed_mode =
2069 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2070 if (dev_priv->panel_fixed_mode) {
2071 dev_priv->panel_fixed_mode->type |=
2072 DRM_MODE_TYPE_PREFERRED;
2073 }
2074 }
2075 }
2076
2077 intel_dp_add_properties(intel_dp, connector);
2078
2079 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2080 * 0xd. Failure to do so will result in spurious interrupts being
2081 * generated on the port when a cable is not attached.
2082 */
2083 if (IS_G4X(dev) && !IS_GM45(dev)) {
2084 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2085 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2086 }
2087 }
Linux kernel - Deliverables
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