2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
34 #include "drm_crtc_helper.h"
36 #include "intel_drv.h"
39 #include "drm_dp_helper.h"
41 #define DP_RECEIVER_CAP_SIZE 0xf
42 #define DP_LINK_STATUS_SIZE 6
43 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
45 #define DP_LINK_CONFIGURATION_SIZE 9
48 struct intel_encoder base
;
51 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
53 enum hdmi_force_audio force_audio
;
58 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
59 struct i2c_adapter adapter
;
60 struct i2c_algo_dp_aux_data algo
;
63 int panel_power_up_delay
;
64 int panel_power_down_delay
;
65 int panel_power_cycle_delay
;
66 int backlight_on_delay
;
67 int backlight_off_delay
;
68 struct drm_display_mode
*panel_fixed_mode
; /* for eDP */
69 struct delayed_work panel_vdd_work
;
71 struct edid
*edid
; /* cached EDID for eDP */
76 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
77 * @intel_dp: DP struct
79 * If a CPU or PCH DP output is attached to an eDP panel, this function
80 * will return true, and false otherwise.
82 static bool is_edp(struct intel_dp
*intel_dp
)
84 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
88 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
89 * @intel_dp: DP struct
91 * Returns true if the given DP struct corresponds to a PCH DP port attached
92 * to an eDP panel, false otherwise. Helpful for determining whether we
93 * may need FDI resources for a given DP output or not.
95 static bool is_pch_edp(struct intel_dp
*intel_dp
)
97 return intel_dp
->is_pch_edp
;
101 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
102 * @intel_dp: DP struct
104 * Returns true if the given DP struct corresponds to a CPU eDP port.
106 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
108 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
111 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
113 return container_of(encoder
, struct intel_dp
, base
.base
);
116 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
118 return container_of(intel_attached_encoder(connector
),
119 struct intel_dp
, base
);
123 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
124 * @encoder: DRM encoder
126 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
127 * by intel_display.c.
129 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
131 struct intel_dp
*intel_dp
;
136 intel_dp
= enc_to_intel_dp(encoder
);
138 return is_pch_edp(intel_dp
);
141 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
142 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
143 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
146 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
147 int *lane_num
, int *link_bw
)
149 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
151 *lane_num
= intel_dp
->lane_count
;
152 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
154 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
159 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
161 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
162 switch (max_lane_count
) {
163 case 1: case 2: case 4:
168 return max_lane_count
;
172 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
174 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
176 switch (max_link_bw
) {
177 case DP_LINK_BW_1_62
:
181 max_link_bw
= DP_LINK_BW_1_62
;
188 intel_dp_link_clock(uint8_t link_bw
)
190 if (link_bw
== DP_LINK_BW_2_7
)
197 * The units on the numbers in the next two are... bizarre. Examples will
198 * make it clearer; this one parallels an example in the eDP spec.
200 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
202 * 270000 * 1 * 8 / 10 == 216000
204 * The actual data capacity of that configuration is 2.16Gbit/s, so the
205 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
206 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
207 * 119000. At 18bpp that's 2142000 kilobits per second.
209 * Thus the strange-looking division by 10 in intel_dp_link_required, to
210 * get the result in decakilobits instead of kilobits.
214 intel_dp_link_required(int pixel_clock
, int bpp
)
216 return (pixel_clock
* bpp
+ 9) / 10;
220 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
222 return (max_link_clock
* max_lanes
* 8) / 10;
226 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
227 struct drm_display_mode
*mode
,
228 struct drm_display_mode
*adjusted_mode
)
230 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
231 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
232 int max_rate
, mode_rate
;
234 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
235 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
237 if (mode_rate
> max_rate
) {
238 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
239 if (mode_rate
> max_rate
)
243 adjusted_mode
->private_flags
244 |= INTEL_MODE_DP_FORCE_6BPC
;
253 intel_dp_mode_valid(struct drm_connector
*connector
,
254 struct drm_display_mode
*mode
)
256 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
258 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
259 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
262 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
266 if (!intel_dp_adjust_dithering(intel_dp
, mode
, NULL
))
267 return MODE_CLOCK_HIGH
;
269 if (mode
->clock
< 10000)
270 return MODE_CLOCK_LOW
;
272 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
273 return MODE_H_ILLEGAL
;
279 pack_aux(uint8_t *src
, int src_bytes
)
286 for (i
= 0; i
< src_bytes
; i
++)
287 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
292 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
297 for (i
= 0; i
< dst_bytes
; i
++)
298 dst
[i
] = src
>> ((3-i
) * 8);
301 /* hrawclock is 1/4 the FSB frequency */
303 intel_hrawclk(struct drm_device
*dev
)
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
308 clkcfg
= I915_READ(CLKCFG
);
309 switch (clkcfg
& CLKCFG_FSB_MASK
) {
318 case CLKCFG_FSB_1067
:
320 case CLKCFG_FSB_1333
:
322 /* these two are just a guess; one of them might be right */
323 case CLKCFG_FSB_1600
:
324 case CLKCFG_FSB_1600_ALT
:
331 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
333 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
336 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
339 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
341 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
344 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
348 intel_dp_check_edp(struct intel_dp
*intel_dp
)
350 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
353 if (!is_edp(intel_dp
))
355 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
356 WARN(1, "eDP powered off while attempting aux channel communication.\n");
357 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
358 I915_READ(PCH_PP_STATUS
),
359 I915_READ(PCH_PP_CONTROL
));
364 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
365 uint8_t *send
, int send_bytes
,
366 uint8_t *recv
, int recv_size
)
368 uint32_t output_reg
= intel_dp
->output_reg
;
369 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
371 uint32_t ch_ctl
= output_reg
+ 0x10;
372 uint32_t ch_data
= ch_ctl
+ 4;
376 uint32_t aux_clock_divider
;
379 intel_dp_check_edp(intel_dp
);
380 /* The clock divider is based off the hrawclk,
381 * and would like to run at 2MHz. So, take the
382 * hrawclk value and divide by 2 and use that
384 * Note that PCH attached eDP panels should use a 125MHz input
387 if (is_cpu_edp(intel_dp
)) {
388 if (IS_GEN6(dev
) || IS_GEN7(dev
))
389 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
391 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
392 } else if (HAS_PCH_SPLIT(dev
))
393 aux_clock_divider
= 63; /* IRL input clock fixed at 125Mhz */
395 aux_clock_divider
= intel_hrawclk(dev
) / 2;
402 /* Try to wait for any previous AUX channel activity */
403 for (try = 0; try < 3; try++) {
404 status
= I915_READ(ch_ctl
);
405 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
411 WARN(1, "dp_aux_ch not started status 0x%08x\n",
416 /* Must try at least 3 times according to DP spec */
417 for (try = 0; try < 5; try++) {
418 /* Load the send data into the aux channel data registers */
419 for (i
= 0; i
< send_bytes
; i
+= 4)
420 I915_WRITE(ch_data
+ i
,
421 pack_aux(send
+ i
, send_bytes
- i
));
423 /* Send the command and wait for it to complete */
425 DP_AUX_CH_CTL_SEND_BUSY
|
426 DP_AUX_CH_CTL_TIME_OUT_400us
|
427 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
428 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
429 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
431 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
432 DP_AUX_CH_CTL_RECEIVE_ERROR
);
434 status
= I915_READ(ch_ctl
);
435 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
440 /* Clear done status and any errors */
444 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
445 DP_AUX_CH_CTL_RECEIVE_ERROR
);
447 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
448 DP_AUX_CH_CTL_RECEIVE_ERROR
))
450 if (status
& DP_AUX_CH_CTL_DONE
)
454 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
455 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
459 /* Check for timeout or receive error.
460 * Timeouts occur when the sink is not connected
462 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
463 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
467 /* Timeouts occur when the device isn't connected, so they're
468 * "normal" -- don't fill the kernel log with these */
469 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
470 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
474 /* Unload any bytes sent back from the other side */
475 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
476 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
477 if (recv_bytes
> recv_size
)
478 recv_bytes
= recv_size
;
480 for (i
= 0; i
< recv_bytes
; i
+= 4)
481 unpack_aux(I915_READ(ch_data
+ i
),
482 recv
+ i
, recv_bytes
- i
);
487 /* Write data to the aux channel in native mode */
489 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
490 uint16_t address
, uint8_t *send
, int send_bytes
)
497 intel_dp_check_edp(intel_dp
);
500 msg
[0] = AUX_NATIVE_WRITE
<< 4;
501 msg
[1] = address
>> 8;
502 msg
[2] = address
& 0xff;
503 msg
[3] = send_bytes
- 1;
504 memcpy(&msg
[4], send
, send_bytes
);
505 msg_bytes
= send_bytes
+ 4;
507 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
510 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
512 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
520 /* Write a single byte to the aux channel in native mode */
522 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
523 uint16_t address
, uint8_t byte
)
525 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
528 /* read bytes from a native aux channel */
530 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
531 uint16_t address
, uint8_t *recv
, int recv_bytes
)
540 intel_dp_check_edp(intel_dp
);
541 msg
[0] = AUX_NATIVE_READ
<< 4;
542 msg
[1] = address
>> 8;
543 msg
[2] = address
& 0xff;
544 msg
[3] = recv_bytes
- 1;
547 reply_bytes
= recv_bytes
+ 1;
550 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
557 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
558 memcpy(recv
, reply
+ 1, ret
- 1);
561 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
569 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
570 uint8_t write_byte
, uint8_t *read_byte
)
572 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
573 struct intel_dp
*intel_dp
= container_of(adapter
,
576 uint16_t address
= algo_data
->address
;
584 intel_dp_check_edp(intel_dp
);
585 /* Set up the command byte */
586 if (mode
& MODE_I2C_READ
)
587 msg
[0] = AUX_I2C_READ
<< 4;
589 msg
[0] = AUX_I2C_WRITE
<< 4;
591 if (!(mode
& MODE_I2C_STOP
))
592 msg
[0] |= AUX_I2C_MOT
<< 4;
594 msg
[1] = address
>> 8;
615 for (retry
= 0; retry
< 5; retry
++) {
616 ret
= intel_dp_aux_ch(intel_dp
,
620 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
624 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
625 case AUX_NATIVE_REPLY_ACK
:
626 /* I2C-over-AUX Reply field is only valid
627 * when paired with AUX ACK.
630 case AUX_NATIVE_REPLY_NACK
:
631 DRM_DEBUG_KMS("aux_ch native nack\n");
633 case AUX_NATIVE_REPLY_DEFER
:
637 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
642 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
643 case AUX_I2C_REPLY_ACK
:
644 if (mode
== MODE_I2C_READ
) {
645 *read_byte
= reply
[1];
647 return reply_bytes
- 1;
648 case AUX_I2C_REPLY_NACK
:
649 DRM_DEBUG_KMS("aux_i2c nack\n");
651 case AUX_I2C_REPLY_DEFER
:
652 DRM_DEBUG_KMS("aux_i2c defer\n");
656 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
661 DRM_ERROR("too many retries, giving up\n");
665 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
666 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
669 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
670 struct intel_connector
*intel_connector
, const char *name
)
674 DRM_DEBUG_KMS("i2c_init %s\n", name
);
675 intel_dp
->algo
.running
= false;
676 intel_dp
->algo
.address
= 0;
677 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
679 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
680 intel_dp
->adapter
.owner
= THIS_MODULE
;
681 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
682 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
683 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
684 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
685 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
687 ironlake_edp_panel_vdd_on(intel_dp
);
688 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
689 ironlake_edp_panel_vdd_off(intel_dp
, false);
694 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
695 struct drm_display_mode
*adjusted_mode
)
697 struct drm_device
*dev
= encoder
->dev
;
698 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
699 int lane_count
, clock
;
700 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
701 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
703 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
705 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
706 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
707 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
708 mode
, adjusted_mode
);
710 * the mode->clock is used to calculate the Data&Link M/N
711 * of the pipe. For the eDP the fixed clock should be used.
713 mode
->clock
= intel_dp
->panel_fixed_mode
->clock
;
716 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
719 DRM_DEBUG_KMS("DP link computation with max lane count %i "
720 "max bw %02x pixel clock %iKHz\n",
721 max_lane_count
, bws
[max_clock
], mode
->clock
);
723 if (!intel_dp_adjust_dithering(intel_dp
, mode
, adjusted_mode
))
726 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
727 mode_rate
= intel_dp_link_required(mode
->clock
, bpp
);
729 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
730 for (clock
= 0; clock
<= max_clock
; clock
++) {
731 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
733 if (mode_rate
<= link_avail
) {
734 intel_dp
->link_bw
= bws
[clock
];
735 intel_dp
->lane_count
= lane_count
;
736 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
737 DRM_DEBUG_KMS("DP link bw %02x lane "
738 "count %d clock %d bpp %d\n",
739 intel_dp
->link_bw
, intel_dp
->lane_count
,
740 adjusted_mode
->clock
, bpp
);
741 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
742 mode_rate
, link_avail
);
751 struct intel_dp_m_n
{
760 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
762 while (*num
> 0xffffff || *den
> 0xffffff) {
769 intel_dp_compute_m_n(int bpp
,
773 struct intel_dp_m_n
*m_n
)
776 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
777 m_n
->gmch_n
= link_clock
* nlanes
;
778 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
779 m_n
->link_m
= pixel_clock
;
780 m_n
->link_n
= link_clock
;
781 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
785 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
786 struct drm_display_mode
*adjusted_mode
)
788 struct drm_device
*dev
= crtc
->dev
;
789 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
790 struct drm_encoder
*encoder
;
791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
792 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
794 struct intel_dp_m_n m_n
;
795 int pipe
= intel_crtc
->pipe
;
798 * Find the lane count in the intel_encoder private
800 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
801 struct intel_dp
*intel_dp
;
803 if (encoder
->crtc
!= crtc
)
806 intel_dp
= enc_to_intel_dp(encoder
);
807 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
808 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
810 lane_count
= intel_dp
->lane_count
;
816 * Compute the GMCH and Link ratios. The '3' here is
817 * the number of bytes_per_pixel post-LUT, which we always
818 * set up for 8-bits of R/G/B, or 3 bytes total.
820 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
821 mode
->clock
, adjusted_mode
->clock
, &m_n
);
823 if (HAS_PCH_SPLIT(dev
)) {
824 I915_WRITE(TRANSDATA_M1(pipe
),
825 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
827 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
828 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
829 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
831 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
832 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
834 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
835 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
836 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
840 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
);
841 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
);
844 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
845 struct drm_display_mode
*adjusted_mode
)
847 struct drm_device
*dev
= encoder
->dev
;
848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
849 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
850 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
851 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
853 /* Turn on the eDP PLL if needed */
854 if (is_edp(intel_dp
)) {
855 if (!is_pch_edp(intel_dp
))
856 ironlake_edp_pll_on(encoder
);
858 ironlake_edp_pll_off(encoder
);
862 * There are four kinds of DP registers:
869 * IBX PCH and CPU are the same for almost everything,
870 * except that the CPU DP PLL is configured in this
873 * CPT PCH is quite different, having many bits moved
874 * to the TRANS_DP_CTL register instead. That
875 * configuration happens (oddly) in ironlake_pch_enable
878 /* Preserve the BIOS-computed detected bit. This is
879 * supposed to be read-only.
881 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
882 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
884 /* Handle DP bits in common between all three register formats */
886 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
888 switch (intel_dp
->lane_count
) {
890 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
893 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
896 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
899 if (intel_dp
->has_audio
) {
900 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
901 pipe_name(intel_crtc
->pipe
));
902 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
903 intel_write_eld(encoder
, adjusted_mode
);
905 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
906 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
907 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
908 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
910 * Check for DPCD version > 1.1 and enhanced framing support
912 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
913 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
914 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
917 /* Split out the IBX/CPU vs CPT settings */
919 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
920 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
921 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
922 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
923 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
924 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
926 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
927 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
929 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
931 /* don't miss out required setting for eDP */
932 intel_dp
->DP
|= DP_PLL_ENABLE
;
933 if (adjusted_mode
->clock
< 200000)
934 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
936 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
937 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
938 intel_dp
->DP
|= intel_dp
->color_range
;
940 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
941 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
942 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
943 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
944 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
946 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
947 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
949 if (intel_crtc
->pipe
== 1)
950 intel_dp
->DP
|= DP_PIPEB_SELECT
;
952 if (is_cpu_edp(intel_dp
)) {
953 /* don't miss out required setting for eDP */
954 intel_dp
->DP
|= DP_PLL_ENABLE
;
955 if (adjusted_mode
->clock
< 200000)
956 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
958 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
961 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
965 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
966 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
968 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
969 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
971 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
972 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
974 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
978 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
981 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
983 I915_READ(PCH_PP_STATUS
),
984 I915_READ(PCH_PP_CONTROL
));
986 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
987 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
988 I915_READ(PCH_PP_STATUS
),
989 I915_READ(PCH_PP_CONTROL
));
993 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
995 DRM_DEBUG_KMS("Wait for panel power on\n");
996 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
999 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
1001 DRM_DEBUG_KMS("Wait for panel power off time\n");
1002 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1005 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1007 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1008 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1012 /* Read the current pp_control value, unlocking the register if it
1016 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
1018 u32 control
= I915_READ(PCH_PP_CONTROL
);
1020 control
&= ~PANEL_UNLOCK_MASK
;
1021 control
|= PANEL_UNLOCK_REGS
;
1025 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1027 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1031 if (!is_edp(intel_dp
))
1033 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1035 WARN(intel_dp
->want_panel_vdd
,
1036 "eDP VDD already requested on\n");
1038 intel_dp
->want_panel_vdd
= true;
1040 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1041 DRM_DEBUG_KMS("eDP VDD already on\n");
1045 if (!ironlake_edp_have_panel_power(intel_dp
))
1046 ironlake_wait_panel_power_cycle(intel_dp
);
1048 pp
= ironlake_get_pp_control(dev_priv
);
1049 pp
|= EDP_FORCE_VDD
;
1050 I915_WRITE(PCH_PP_CONTROL
, pp
);
1051 POSTING_READ(PCH_PP_CONTROL
);
1052 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1053 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1056 * If the panel wasn't on, delay before accessing aux channel
1058 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1059 DRM_DEBUG_KMS("eDP was not running\n");
1060 msleep(intel_dp
->panel_power_up_delay
);
1064 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1066 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1070 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1071 pp
= ironlake_get_pp_control(dev_priv
);
1072 pp
&= ~EDP_FORCE_VDD
;
1073 I915_WRITE(PCH_PP_CONTROL
, pp
);
1074 POSTING_READ(PCH_PP_CONTROL
);
1076 /* Make sure sequencer is idle before allowing subsequent activity */
1077 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1078 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1080 msleep(intel_dp
->panel_power_down_delay
);
1084 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1086 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1087 struct intel_dp
, panel_vdd_work
);
1088 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1090 mutex_lock(&dev
->mode_config
.mutex
);
1091 ironlake_panel_vdd_off_sync(intel_dp
);
1092 mutex_unlock(&dev
->mode_config
.mutex
);
1095 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1097 if (!is_edp(intel_dp
))
1100 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1101 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1103 intel_dp
->want_panel_vdd
= false;
1106 ironlake_panel_vdd_off_sync(intel_dp
);
1109 * Queue the timer to fire a long
1110 * time from now (relative to the power down delay)
1111 * to keep the panel power up across a sequence of operations
1113 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1114 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1118 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1120 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1124 if (!is_edp(intel_dp
))
1127 DRM_DEBUG_KMS("Turn eDP power on\n");
1129 if (ironlake_edp_have_panel_power(intel_dp
)) {
1130 DRM_DEBUG_KMS("eDP power already on\n");
1134 ironlake_wait_panel_power_cycle(intel_dp
);
1136 pp
= ironlake_get_pp_control(dev_priv
);
1138 /* ILK workaround: disable reset around power sequence */
1139 pp
&= ~PANEL_POWER_RESET
;
1140 I915_WRITE(PCH_PP_CONTROL
, pp
);
1141 POSTING_READ(PCH_PP_CONTROL
);
1144 pp
|= POWER_TARGET_ON
;
1146 pp
|= PANEL_POWER_RESET
;
1148 I915_WRITE(PCH_PP_CONTROL
, pp
);
1149 POSTING_READ(PCH_PP_CONTROL
);
1151 ironlake_wait_panel_on(intel_dp
);
1154 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1155 I915_WRITE(PCH_PP_CONTROL
, pp
);
1156 POSTING_READ(PCH_PP_CONTROL
);
1160 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1162 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1166 if (!is_edp(intel_dp
))
1169 DRM_DEBUG_KMS("Turn eDP power off\n");
1171 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1173 pp
= ironlake_get_pp_control(dev_priv
);
1174 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1175 I915_WRITE(PCH_PP_CONTROL
, pp
);
1176 POSTING_READ(PCH_PP_CONTROL
);
1178 ironlake_wait_panel_off(intel_dp
);
1181 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1183 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1187 if (!is_edp(intel_dp
))
1190 DRM_DEBUG_KMS("\n");
1192 * If we enable the backlight right away following a panel power
1193 * on, we may see slight flicker as the panel syncs with the eDP
1194 * link. So delay a bit to make sure the image is solid before
1195 * allowing it to appear.
1197 msleep(intel_dp
->backlight_on_delay
);
1198 pp
= ironlake_get_pp_control(dev_priv
);
1199 pp
|= EDP_BLC_ENABLE
;
1200 I915_WRITE(PCH_PP_CONTROL
, pp
);
1201 POSTING_READ(PCH_PP_CONTROL
);
1204 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1206 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1210 if (!is_edp(intel_dp
))
1213 DRM_DEBUG_KMS("\n");
1214 pp
= ironlake_get_pp_control(dev_priv
);
1215 pp
&= ~EDP_BLC_ENABLE
;
1216 I915_WRITE(PCH_PP_CONTROL
, pp
);
1217 POSTING_READ(PCH_PP_CONTROL
);
1218 msleep(intel_dp
->backlight_off_delay
);
1221 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
1223 struct drm_device
*dev
= encoder
->dev
;
1224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1227 DRM_DEBUG_KMS("\n");
1228 dpa_ctl
= I915_READ(DP_A
);
1229 dpa_ctl
|= DP_PLL_ENABLE
;
1230 I915_WRITE(DP_A
, dpa_ctl
);
1235 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
1237 struct drm_device
*dev
= encoder
->dev
;
1238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1241 dpa_ctl
= I915_READ(DP_A
);
1242 dpa_ctl
&= ~DP_PLL_ENABLE
;
1243 I915_WRITE(DP_A
, dpa_ctl
);
1248 /* If the sink supports it, try to set the power state appropriately */
1249 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1253 /* Should have a valid DPCD by this point */
1254 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1257 if (mode
!= DRM_MODE_DPMS_ON
) {
1258 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1261 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1264 * When turning on, we need to retry for 1ms to give the sink
1267 for (i
= 0; i
< 3; i
++) {
1268 ret
= intel_dp_aux_native_write_1(intel_dp
,
1278 static void intel_dp_prepare(struct drm_encoder
*encoder
)
1280 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1283 /* Make sure the panel is off before trying to change the mode. But also
1284 * ensure that we have vdd while we switch off the panel. */
1285 ironlake_edp_panel_vdd_on(intel_dp
);
1286 ironlake_edp_backlight_off(intel_dp
);
1287 ironlake_edp_panel_off(intel_dp
);
1289 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1290 intel_dp_link_down(intel_dp
);
1291 ironlake_edp_panel_vdd_off(intel_dp
, false);
1294 static void intel_dp_commit(struct drm_encoder
*encoder
)
1296 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1297 struct drm_device
*dev
= encoder
->dev
;
1298 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1300 ironlake_edp_panel_vdd_on(intel_dp
);
1301 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1302 intel_dp_start_link_train(intel_dp
);
1303 ironlake_edp_panel_on(intel_dp
);
1304 ironlake_edp_panel_vdd_off(intel_dp
, true);
1305 intel_dp_complete_link_train(intel_dp
);
1306 ironlake_edp_backlight_on(intel_dp
);
1308 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1310 if (HAS_PCH_CPT(dev
))
1311 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
1315 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
1317 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1318 struct drm_device
*dev
= encoder
->dev
;
1319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1320 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1322 if (mode
!= DRM_MODE_DPMS_ON
) {
1323 /* Switching the panel off requires vdd. */
1324 ironlake_edp_panel_vdd_on(intel_dp
);
1325 ironlake_edp_backlight_off(intel_dp
);
1326 ironlake_edp_panel_off(intel_dp
);
1328 intel_dp_sink_dpms(intel_dp
, mode
);
1329 intel_dp_link_down(intel_dp
);
1330 ironlake_edp_panel_vdd_off(intel_dp
, false);
1332 if (is_cpu_edp(intel_dp
))
1333 ironlake_edp_pll_off(encoder
);
1335 if (is_cpu_edp(intel_dp
))
1336 ironlake_edp_pll_on(encoder
);
1338 ironlake_edp_panel_vdd_on(intel_dp
);
1339 intel_dp_sink_dpms(intel_dp
, mode
);
1340 if (!(dp_reg
& DP_PORT_EN
)) {
1341 intel_dp_start_link_train(intel_dp
);
1342 ironlake_edp_panel_on(intel_dp
);
1343 ironlake_edp_panel_vdd_off(intel_dp
, true);
1344 intel_dp_complete_link_train(intel_dp
);
1346 ironlake_edp_panel_vdd_off(intel_dp
, false);
1347 ironlake_edp_backlight_on(intel_dp
);
1349 intel_dp
->dpms_mode
= mode
;
1353 * Native read with retry for link status and receiver capability reads for
1354 * cases where the sink may still be asleep.
1357 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1358 uint8_t *recv
, int recv_bytes
)
1363 * Sinks are *supposed* to come up within 1ms from an off state,
1364 * but we're also supposed to retry 3 times per the spec.
1366 for (i
= 0; i
< 3; i
++) {
1367 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1369 if (ret
== recv_bytes
)
1378 * Fetch AUX CH registers 0x202 - 0x207 which contain
1379 * link status information
1382 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1384 return intel_dp_aux_native_read_retry(intel_dp
,
1387 DP_LINK_STATUS_SIZE
);
1391 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1394 return link_status
[r
- DP_LANE0_1_STATUS
];
1398 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1401 int s
= ((lane
& 1) ?
1402 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1403 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1404 uint8_t l
= adjust_request
[lane
>>1];
1406 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1410 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1413 int s
= ((lane
& 1) ?
1414 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1415 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1416 uint8_t l
= adjust_request
[lane
>>1];
1418 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1423 static char *voltage_names
[] = {
1424 "0.4V", "0.6V", "0.8V", "1.2V"
1426 static char *pre_emph_names
[] = {
1427 "0dB", "3.5dB", "6dB", "9.5dB"
1429 static char *link_train_names
[] = {
1430 "pattern 1", "pattern 2", "idle", "off"
1435 * These are source-specific values; current Intel hardware supports
1436 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1440 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1442 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1444 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1445 return DP_TRAIN_VOLTAGE_SWING_800
;
1446 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1447 return DP_TRAIN_VOLTAGE_SWING_1200
;
1449 return DP_TRAIN_VOLTAGE_SWING_800
;
1453 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1455 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1457 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1458 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1459 case DP_TRAIN_VOLTAGE_SWING_400
:
1460 return DP_TRAIN_PRE_EMPHASIS_6
;
1461 case DP_TRAIN_VOLTAGE_SWING_600
:
1462 case DP_TRAIN_VOLTAGE_SWING_800
:
1463 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1465 return DP_TRAIN_PRE_EMPHASIS_0
;
1468 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1469 case DP_TRAIN_VOLTAGE_SWING_400
:
1470 return DP_TRAIN_PRE_EMPHASIS_6
;
1471 case DP_TRAIN_VOLTAGE_SWING_600
:
1472 return DP_TRAIN_PRE_EMPHASIS_6
;
1473 case DP_TRAIN_VOLTAGE_SWING_800
:
1474 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1475 case DP_TRAIN_VOLTAGE_SWING_1200
:
1477 return DP_TRAIN_PRE_EMPHASIS_0
;
1483 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1488 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1489 uint8_t voltage_max
;
1490 uint8_t preemph_max
;
1492 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1493 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1494 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1502 voltage_max
= intel_dp_voltage_max(intel_dp
);
1503 if (v
>= voltage_max
)
1504 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1506 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1507 if (p
>= preemph_max
)
1508 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1510 for (lane
= 0; lane
< 4; lane
++)
1511 intel_dp
->train_set
[lane
] = v
| p
;
1515 intel_dp_signal_levels(uint8_t train_set
)
1517 uint32_t signal_levels
= 0;
1519 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1520 case DP_TRAIN_VOLTAGE_SWING_400
:
1522 signal_levels
|= DP_VOLTAGE_0_4
;
1524 case DP_TRAIN_VOLTAGE_SWING_600
:
1525 signal_levels
|= DP_VOLTAGE_0_6
;
1527 case DP_TRAIN_VOLTAGE_SWING_800
:
1528 signal_levels
|= DP_VOLTAGE_0_8
;
1530 case DP_TRAIN_VOLTAGE_SWING_1200
:
1531 signal_levels
|= DP_VOLTAGE_1_2
;
1534 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1535 case DP_TRAIN_PRE_EMPHASIS_0
:
1537 signal_levels
|= DP_PRE_EMPHASIS_0
;
1539 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1540 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1542 case DP_TRAIN_PRE_EMPHASIS_6
:
1543 signal_levels
|= DP_PRE_EMPHASIS_6
;
1545 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1546 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1549 return signal_levels
;
1552 /* Gen6's DP voltage swing and pre-emphasis control */
1554 intel_gen6_edp_signal_levels(uint8_t train_set
)
1556 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1557 DP_TRAIN_PRE_EMPHASIS_MASK
);
1558 switch (signal_levels
) {
1559 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1560 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1561 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1562 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1563 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1564 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1565 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1566 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1567 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1568 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1569 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1570 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1571 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1572 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1574 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1575 "0x%x\n", signal_levels
);
1576 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1580 /* Gen7's DP voltage swing and pre-emphasis control */
1582 intel_gen7_edp_signal_levels(uint8_t train_set
)
1584 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1585 DP_TRAIN_PRE_EMPHASIS_MASK
);
1586 switch (signal_levels
) {
1587 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1588 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1589 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1590 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1591 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1592 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1594 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1595 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1596 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1597 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1599 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1600 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1601 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1602 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1605 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1606 "0x%x\n", signal_levels
);
1607 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1612 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1615 int s
= (lane
& 1) * 4;
1616 uint8_t l
= link_status
[lane
>>1];
1618 return (l
>> s
) & 0xf;
1621 /* Check for clock recovery is done on all channels */
1623 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1626 uint8_t lane_status
;
1628 for (lane
= 0; lane
< lane_count
; lane
++) {
1629 lane_status
= intel_get_lane_status(link_status
, lane
);
1630 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1636 /* Check to see if channel eq is done on all channels */
1637 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1638 DP_LANE_CHANNEL_EQ_DONE|\
1639 DP_LANE_SYMBOL_LOCKED)
1641 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1644 uint8_t lane_status
;
1647 lane_align
= intel_dp_link_status(link_status
,
1648 DP_LANE_ALIGN_STATUS_UPDATED
);
1649 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1651 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1652 lane_status
= intel_get_lane_status(link_status
, lane
);
1653 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1660 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1661 uint32_t dp_reg_value
,
1662 uint8_t dp_train_pat
)
1664 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1668 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1669 POSTING_READ(intel_dp
->output_reg
);
1671 intel_dp_aux_native_write_1(intel_dp
,
1672 DP_TRAINING_PATTERN_SET
,
1675 ret
= intel_dp_aux_native_write(intel_dp
,
1676 DP_TRAINING_LANE0_SET
,
1677 intel_dp
->train_set
,
1678 intel_dp
->lane_count
);
1679 if (ret
!= intel_dp
->lane_count
)
1685 /* Enable corresponding port and start training pattern 1 */
1687 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1689 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1691 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1694 bool clock_recovery
= false;
1695 int voltage_tries
, loop_tries
;
1697 uint32_t DP
= intel_dp
->DP
;
1700 * On CPT we have to enable the port in training pattern 1, which
1701 * will happen below in intel_dp_set_link_train. Otherwise, enable
1702 * the port and wait for it to become active.
1704 if (!HAS_PCH_CPT(dev
)) {
1705 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
1706 POSTING_READ(intel_dp
->output_reg
);
1707 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1710 /* Write the link configuration data */
1711 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1712 intel_dp
->link_configuration
,
1713 DP_LINK_CONFIGURATION_SIZE
);
1717 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1718 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1720 DP
&= ~DP_LINK_TRAIN_MASK
;
1721 memset(intel_dp
->train_set
, 0, 4);
1725 clock_recovery
= false;
1727 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1728 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1729 uint32_t signal_levels
;
1732 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1733 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1734 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1735 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1736 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1737 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1739 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1740 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels
);
1741 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1744 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1745 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1747 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1749 if (!intel_dp_set_link_train(intel_dp
, reg
,
1750 DP_TRAINING_PATTERN_1
|
1751 DP_LINK_SCRAMBLING_DISABLE
))
1753 /* Set training pattern 1 */
1756 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1757 DRM_ERROR("failed to get link status\n");
1761 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1762 DRM_DEBUG_KMS("clock recovery OK\n");
1763 clock_recovery
= true;
1767 /* Check to see if we've tried the max voltage */
1768 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1769 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1771 if (i
== intel_dp
->lane_count
) {
1773 if (loop_tries
== 5) {
1774 DRM_DEBUG_KMS("too many full retries, give up\n");
1777 memset(intel_dp
->train_set
, 0, 4);
1782 /* Check to see if we've tried the same voltage 5 times */
1783 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1785 if (voltage_tries
== 5) {
1786 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1791 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1793 /* Compute new intel_dp->train_set as requested by target */
1794 intel_get_adjust_train(intel_dp
, link_status
);
1801 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1803 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1805 bool channel_eq
= false;
1806 int tries
, cr_tries
;
1808 uint32_t DP
= intel_dp
->DP
;
1810 /* channel equalization */
1815 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1816 uint32_t signal_levels
;
1817 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1820 DRM_ERROR("failed to train DP, aborting\n");
1821 intel_dp_link_down(intel_dp
);
1825 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1826 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1827 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1828 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1829 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1830 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1832 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1833 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1836 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1837 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1839 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1841 /* channel eq pattern */
1842 if (!intel_dp_set_link_train(intel_dp
, reg
,
1843 DP_TRAINING_PATTERN_2
|
1844 DP_LINK_SCRAMBLING_DISABLE
))
1848 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1851 /* Make sure clock is still ok */
1852 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1853 intel_dp_start_link_train(intel_dp
);
1858 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
1863 /* Try 5 times, then try clock recovery if that fails */
1865 intel_dp_link_down(intel_dp
);
1866 intel_dp_start_link_train(intel_dp
);
1872 /* Compute new intel_dp->train_set as requested by target */
1873 intel_get_adjust_train(intel_dp
, link_status
);
1877 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1878 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1880 reg
= DP
| DP_LINK_TRAIN_OFF
;
1882 I915_WRITE(intel_dp
->output_reg
, reg
);
1883 POSTING_READ(intel_dp
->output_reg
);
1884 intel_dp_aux_native_write_1(intel_dp
,
1885 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1889 intel_dp_link_down(struct intel_dp
*intel_dp
)
1891 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1893 uint32_t DP
= intel_dp
->DP
;
1895 if ((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0)
1898 DRM_DEBUG_KMS("\n");
1900 if (is_edp(intel_dp
)) {
1901 DP
&= ~DP_PLL_ENABLE
;
1902 I915_WRITE(intel_dp
->output_reg
, DP
);
1903 POSTING_READ(intel_dp
->output_reg
);
1907 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1908 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1909 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1911 DP
&= ~DP_LINK_TRAIN_MASK
;
1912 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1914 POSTING_READ(intel_dp
->output_reg
);
1918 if (is_edp(intel_dp
)) {
1919 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1920 DP
|= DP_LINK_TRAIN_OFF_CPT
;
1922 DP
|= DP_LINK_TRAIN_OFF
;
1925 if (!HAS_PCH_CPT(dev
) &&
1926 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1927 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1929 /* Hardware workaround: leaving our transcoder select
1930 * set to transcoder B while it's off will prevent the
1931 * corresponding HDMI output on transcoder A.
1933 * Combine this with another hardware workaround:
1934 * transcoder select bit can only be cleared while the
1937 DP
&= ~DP_PIPEB_SELECT
;
1938 I915_WRITE(intel_dp
->output_reg
, DP
);
1940 /* Changes to enable or select take place the vblank
1941 * after being written.
1944 /* We can arrive here never having been attached
1945 * to a CRTC, for instance, due to inheriting
1946 * random state from the BIOS.
1948 * If the pipe is not running, play safe and
1949 * wait for the clocks to stabilise before
1952 POSTING_READ(intel_dp
->output_reg
);
1955 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
1958 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
1959 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1960 POSTING_READ(intel_dp
->output_reg
);
1961 msleep(intel_dp
->panel_power_down_delay
);
1965 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
1967 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
1968 sizeof(intel_dp
->dpcd
)) &&
1969 (intel_dp
->dpcd
[DP_DPCD_REV
] != 0)) {
1977 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
1981 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
1984 ironlake_edp_panel_vdd_on(intel_dp
);
1986 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
1987 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1988 buf
[0], buf
[1], buf
[2]);
1990 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
1991 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1992 buf
[0], buf
[1], buf
[2]);
1994 ironlake_edp_panel_vdd_off(intel_dp
, false);
1998 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2002 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2003 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2004 sink_irq_vector
, 1);
2012 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2014 /* NAK by default */
2015 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
2019 * According to DP spec
2022 * 2. Configure link according to Receiver Capabilities
2023 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2024 * 4. Check link status on receipt of hot-plug interrupt
2028 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2031 u8 link_status
[DP_LINK_STATUS_SIZE
];
2033 if (intel_dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
2036 if (!intel_dp
->base
.base
.crtc
)
2039 /* Try to read receiver status if the link appears to be up */
2040 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2041 intel_dp_link_down(intel_dp
);
2045 /* Now read the DPCD to see if it's actually running */
2046 if (!intel_dp_get_dpcd(intel_dp
)) {
2047 intel_dp_link_down(intel_dp
);
2051 /* Try to read the source of the interrupt */
2052 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2053 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2054 /* Clear interrupt source */
2055 intel_dp_aux_native_write_1(intel_dp
,
2056 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2059 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2060 intel_dp_handle_test_request(intel_dp
);
2061 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2062 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2065 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
2066 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2067 drm_get_encoder_name(&intel_dp
->base
.base
));
2068 intel_dp_start_link_train(intel_dp
);
2069 intel_dp_complete_link_train(intel_dp
);
2073 static enum drm_connector_status
2074 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2076 if (intel_dp_get_dpcd(intel_dp
))
2077 return connector_status_connected
;
2078 return connector_status_disconnected
;
2081 static enum drm_connector_status
2082 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2084 enum drm_connector_status status
;
2086 /* Can't disconnect eDP, but you can close the lid... */
2087 if (is_edp(intel_dp
)) {
2088 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2089 if (status
== connector_status_unknown
)
2090 status
= connector_status_connected
;
2094 return intel_dp_detect_dpcd(intel_dp
);
2097 static enum drm_connector_status
2098 g4x_dp_detect(struct intel_dp
*intel_dp
)
2100 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2104 switch (intel_dp
->output_reg
) {
2106 bit
= DPB_HOTPLUG_INT_STATUS
;
2109 bit
= DPC_HOTPLUG_INT_STATUS
;
2112 bit
= DPD_HOTPLUG_INT_STATUS
;
2115 return connector_status_unknown
;
2118 temp
= I915_READ(PORT_HOTPLUG_STAT
);
2120 if ((temp
& bit
) == 0)
2121 return connector_status_disconnected
;
2123 return intel_dp_detect_dpcd(intel_dp
);
2126 static struct edid
*
2127 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2129 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2133 if (is_edp(intel_dp
)) {
2134 if (!intel_dp
->edid
)
2137 size
= (intel_dp
->edid
->extensions
+ 1) * EDID_LENGTH
;
2138 edid
= kmalloc(size
, GFP_KERNEL
);
2142 memcpy(edid
, intel_dp
->edid
, size
);
2146 edid
= drm_get_edid(connector
, adapter
);
2151 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2153 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2156 if (is_edp(intel_dp
)) {
2157 drm_mode_connector_update_edid_property(connector
,
2159 ret
= drm_add_edid_modes(connector
, intel_dp
->edid
);
2160 drm_edid_to_eld(connector
,
2162 connector
->display_info
.raw_edid
= NULL
;
2163 return intel_dp
->edid_mode_count
;
2166 ret
= intel_ddc_get_modes(connector
, adapter
);
2172 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2174 * \return true if DP port is connected.
2175 * \return false if DP port is disconnected.
2177 static enum drm_connector_status
2178 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2180 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2181 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2182 enum drm_connector_status status
;
2183 struct edid
*edid
= NULL
;
2185 intel_dp
->has_audio
= false;
2187 if (HAS_PCH_SPLIT(dev
))
2188 status
= ironlake_dp_detect(intel_dp
);
2190 status
= g4x_dp_detect(intel_dp
);
2192 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2193 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2194 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2195 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2197 if (status
!= connector_status_connected
)
2200 intel_dp_probe_oui(intel_dp
);
2202 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2203 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2205 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2207 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2208 connector
->display_info
.raw_edid
= NULL
;
2213 return connector_status_connected
;
2216 static int intel_dp_get_modes(struct drm_connector
*connector
)
2218 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2219 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2223 /* We should parse the EDID data and find out if it has an audio sink
2226 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2228 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2229 struct drm_display_mode
*newmode
;
2230 list_for_each_entry(newmode
, &connector
->probed_modes
,
2232 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2233 intel_dp
->panel_fixed_mode
=
2234 drm_mode_duplicate(dev
, newmode
);
2242 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2243 if (is_edp(intel_dp
)) {
2244 /* initialize panel mode from VBT if available for eDP */
2245 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2246 intel_dp
->panel_fixed_mode
=
2247 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2248 if (intel_dp
->panel_fixed_mode
) {
2249 intel_dp
->panel_fixed_mode
->type
|=
2250 DRM_MODE_TYPE_PREFERRED
;
2253 if (intel_dp
->panel_fixed_mode
) {
2254 struct drm_display_mode
*mode
;
2255 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2256 drm_mode_probed_add(connector
, mode
);
2264 intel_dp_detect_audio(struct drm_connector
*connector
)
2266 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2268 bool has_audio
= false;
2270 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2272 has_audio
= drm_detect_monitor_audio(edid
);
2274 connector
->display_info
.raw_edid
= NULL
;
2282 intel_dp_set_property(struct drm_connector
*connector
,
2283 struct drm_property
*property
,
2286 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2287 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2290 ret
= drm_connector_property_set_value(connector
, property
, val
);
2294 if (property
== dev_priv
->force_audio_property
) {
2298 if (i
== intel_dp
->force_audio
)
2301 intel_dp
->force_audio
= i
;
2303 if (i
== HDMI_AUDIO_AUTO
)
2304 has_audio
= intel_dp_detect_audio(connector
);
2306 has_audio
= (i
== HDMI_AUDIO_ON
);
2308 if (has_audio
== intel_dp
->has_audio
)
2311 intel_dp
->has_audio
= has_audio
;
2315 if (property
== dev_priv
->broadcast_rgb_property
) {
2316 if (val
== !!intel_dp
->color_range
)
2319 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2326 if (intel_dp
->base
.base
.crtc
) {
2327 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2328 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
2337 intel_dp_destroy(struct drm_connector
*connector
)
2339 struct drm_device
*dev
= connector
->dev
;
2341 if (intel_dpd_is_edp(dev
))
2342 intel_panel_destroy_backlight(dev
);
2344 drm_sysfs_connector_remove(connector
);
2345 drm_connector_cleanup(connector
);
2349 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2351 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2353 i2c_del_adapter(&intel_dp
->adapter
);
2354 drm_encoder_cleanup(encoder
);
2355 if (is_edp(intel_dp
)) {
2356 kfree(intel_dp
->edid
);
2357 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2358 ironlake_panel_vdd_off_sync(intel_dp
);
2363 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2364 .dpms
= intel_dp_dpms
,
2365 .mode_fixup
= intel_dp_mode_fixup
,
2366 .prepare
= intel_dp_prepare
,
2367 .mode_set
= intel_dp_mode_set
,
2368 .commit
= intel_dp_commit
,
2371 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2372 .dpms
= drm_helper_connector_dpms
,
2373 .detect
= intel_dp_detect
,
2374 .fill_modes
= drm_helper_probe_single_connector_modes
,
2375 .set_property
= intel_dp_set_property
,
2376 .destroy
= intel_dp_destroy
,
2379 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2380 .get_modes
= intel_dp_get_modes
,
2381 .mode_valid
= intel_dp_mode_valid
,
2382 .best_encoder
= intel_best_encoder
,
2385 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2386 .destroy
= intel_dp_encoder_destroy
,
2390 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2392 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2394 intel_dp_check_link_status(intel_dp
);
2397 /* Return which DP Port should be selected for Transcoder DP control */
2399 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2401 struct drm_device
*dev
= crtc
->dev
;
2402 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2403 struct drm_encoder
*encoder
;
2405 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
2406 struct intel_dp
*intel_dp
;
2408 if (encoder
->crtc
!= crtc
)
2411 intel_dp
= enc_to_intel_dp(encoder
);
2412 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2413 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2414 return intel_dp
->output_reg
;
2420 /* check the VBT to see whether the eDP is on DP-D port */
2421 bool intel_dpd_is_edp(struct drm_device
*dev
)
2423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2424 struct child_device_config
*p_child
;
2427 if (!dev_priv
->child_dev_num
)
2430 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2431 p_child
= dev_priv
->child_dev
+ i
;
2433 if (p_child
->dvo_port
== PORT_IDPD
&&
2434 p_child
->device_type
== DEVICE_TYPE_eDP
)
2441 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2443 intel_attach_force_audio_property(connector
);
2444 intel_attach_broadcast_rgb_property(connector
);
2448 intel_dp_init(struct drm_device
*dev
, int output_reg
)
2450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2451 struct drm_connector
*connector
;
2452 struct intel_dp
*intel_dp
;
2453 struct intel_encoder
*intel_encoder
;
2454 struct intel_connector
*intel_connector
;
2455 const char *name
= NULL
;
2458 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2462 intel_dp
->output_reg
= output_reg
;
2463 intel_dp
->dpms_mode
= -1;
2465 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2466 if (!intel_connector
) {
2470 intel_encoder
= &intel_dp
->base
;
2472 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2473 if (intel_dpd_is_edp(dev
))
2474 intel_dp
->is_pch_edp
= true;
2476 if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2477 type
= DRM_MODE_CONNECTOR_eDP
;
2478 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2480 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2481 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2484 connector
= &intel_connector
->base
;
2485 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2486 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2488 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2490 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
2491 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
2492 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
2493 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
2494 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
2495 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
2497 if (is_edp(intel_dp
)) {
2498 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
2499 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2500 ironlake_panel_vdd_work
);
2503 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2505 connector
->interlace_allowed
= true;
2506 connector
->doublescan_allowed
= 0;
2508 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2509 DRM_MODE_ENCODER_TMDS
);
2510 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2512 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2513 drm_sysfs_connector_add(connector
);
2515 /* Set up the DDC bus. */
2516 switch (output_reg
) {
2522 dev_priv
->hotplug_supported_mask
|=
2523 HDMIB_HOTPLUG_INT_STATUS
;
2528 dev_priv
->hotplug_supported_mask
|=
2529 HDMIC_HOTPLUG_INT_STATUS
;
2534 dev_priv
->hotplug_supported_mask
|=
2535 HDMID_HOTPLUG_INT_STATUS
;
2540 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2542 /* Cache some DPCD data in the eDP case */
2543 if (is_edp(intel_dp
)) {
2545 struct edp_power_seq cur
, vbt
;
2546 u32 pp_on
, pp_off
, pp_div
;
2549 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2550 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2551 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2553 if (!pp_on
|| !pp_off
|| !pp_div
) {
2554 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2555 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2556 intel_dp_destroy(&intel_connector
->base
);
2560 /* Pull timing values out of registers */
2561 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2562 PANEL_POWER_UP_DELAY_SHIFT
;
2564 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2565 PANEL_LIGHT_ON_DELAY_SHIFT
;
2567 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2568 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2570 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2571 PANEL_POWER_DOWN_DELAY_SHIFT
;
2573 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2574 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2576 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2577 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2579 vbt
= dev_priv
->edp
.pps
;
2581 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2582 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2584 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2586 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2587 intel_dp
->backlight_on_delay
= get_delay(t8
);
2588 intel_dp
->backlight_off_delay
= get_delay(t9
);
2589 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2590 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2592 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2593 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2594 intel_dp
->panel_power_cycle_delay
);
2596 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2597 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2599 ironlake_edp_panel_vdd_on(intel_dp
);
2600 ret
= intel_dp_get_dpcd(intel_dp
);
2601 ironlake_edp_panel_vdd_off(intel_dp
, false);
2604 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2605 dev_priv
->no_aux_handshake
=
2606 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2607 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2609 /* if this fails, presume the device is a ghost */
2610 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2611 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2612 intel_dp_destroy(&intel_connector
->base
);
2616 ironlake_edp_panel_vdd_on(intel_dp
);
2617 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2619 drm_mode_connector_update_edid_property(connector
,
2621 intel_dp
->edid_mode_count
=
2622 drm_add_edid_modes(connector
, edid
);
2623 drm_edid_to_eld(connector
, edid
);
2624 intel_dp
->edid
= edid
;
2626 ironlake_edp_panel_vdd_off(intel_dp
, false);
2629 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2631 if (is_edp(intel_dp
)) {
2632 dev_priv
->int_edp_connector
= connector
;
2633 intel_panel_setup_backlight(dev
);
2636 intel_dp_add_properties(intel_dp
, connector
);
2638 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2639 * 0xd. Failure to do so will result in spurious interrupts being
2640 * generated on the port when a cable is not attached.
2642 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2643 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2644 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);