2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
34 #include "drm_crtc_helper.h"
36 #include "intel_drv.h"
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
51 static bool is_edp(struct intel_dp
*intel_dp
)
53 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
64 static bool is_pch_edp(struct intel_dp
*intel_dp
)
66 return intel_dp
->is_pch_edp
;
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
75 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
77 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
80 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
82 return container_of(intel_attached_encoder(connector
),
83 struct intel_dp
, base
);
87 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
88 * @encoder: DRM encoder
90 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
93 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
95 struct intel_dp
*intel_dp
;
100 intel_dp
= enc_to_intel_dp(encoder
);
102 return is_pch_edp(intel_dp
);
105 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
106 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
107 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
110 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
111 int *lane_num
, int *link_bw
)
113 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
115 *lane_num
= intel_dp
->lane_count
;
116 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
118 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
123 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
124 struct drm_display_mode
*mode
)
126 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
128 if (intel_dp
->panel_fixed_mode
)
129 return intel_dp
->panel_fixed_mode
->clock
;
135 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
137 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
138 switch (max_lane_count
) {
139 case 1: case 2: case 4:
144 return max_lane_count
;
148 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
150 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
152 switch (max_link_bw
) {
153 case DP_LINK_BW_1_62
:
157 max_link_bw
= DP_LINK_BW_1_62
;
164 intel_dp_link_clock(uint8_t link_bw
)
166 if (link_bw
== DP_LINK_BW_2_7
)
173 * The units on the numbers in the next two are... bizarre. Examples will
174 * make it clearer; this one parallels an example in the eDP spec.
176 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
178 * 270000 * 1 * 8 / 10 == 216000
180 * The actual data capacity of that configuration is 2.16Gbit/s, so the
181 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
182 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
183 * 119000. At 18bpp that's 2142000 kilobits per second.
185 * Thus the strange-looking division by 10 in intel_dp_link_required, to
186 * get the result in decakilobits instead of kilobits.
190 intel_dp_link_required(int pixel_clock
, int bpp
)
192 return (pixel_clock
* bpp
+ 9) / 10;
196 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
198 return (max_link_clock
* max_lanes
* 8) / 10;
202 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
203 struct drm_display_mode
*mode
,
206 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
207 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
208 int max_rate
, mode_rate
;
210 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
211 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 if (mode_rate
> max_rate
) {
214 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
215 if (mode_rate
> max_rate
)
220 |= INTEL_MODE_DP_FORCE_6BPC
;
229 intel_dp_mode_valid(struct drm_connector
*connector
,
230 struct drm_display_mode
*mode
)
232 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
234 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
235 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
238 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
242 if (!intel_dp_adjust_dithering(intel_dp
, mode
, false))
243 return MODE_CLOCK_HIGH
;
245 if (mode
->clock
< 10000)
246 return MODE_CLOCK_LOW
;
248 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
249 return MODE_H_ILLEGAL
;
255 pack_aux(uint8_t *src
, int src_bytes
)
262 for (i
= 0; i
< src_bytes
; i
++)
263 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
268 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
273 for (i
= 0; i
< dst_bytes
; i
++)
274 dst
[i
] = src
>> ((3-i
) * 8);
277 /* hrawclock is 1/4 the FSB frequency */
279 intel_hrawclk(struct drm_device
*dev
)
281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
284 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
285 if (IS_VALLEYVIEW(dev
))
288 clkcfg
= I915_READ(CLKCFG
);
289 switch (clkcfg
& CLKCFG_FSB_MASK
) {
298 case CLKCFG_FSB_1067
:
300 case CLKCFG_FSB_1333
:
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600
:
304 case CLKCFG_FSB_1600_ALT
:
311 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
313 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
319 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
321 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
328 intel_dp_check_edp(struct intel_dp
*intel_dp
)
330 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 if (!is_edp(intel_dp
))
335 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
338 I915_READ(PCH_PP_STATUS
),
339 I915_READ(PCH_PP_CONTROL
));
344 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
345 uint8_t *send
, int send_bytes
,
346 uint8_t *recv
, int recv_size
)
348 uint32_t output_reg
= intel_dp
->output_reg
;
349 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 uint32_t ch_ctl
= output_reg
+ 0x10;
352 uint32_t ch_data
= ch_ctl
+ 4;
356 uint32_t aux_clock_divider
;
359 if (IS_HASWELL(dev
)) {
360 switch (intel_dp
->port
) {
362 ch_ctl
= DPA_AUX_CH_CTL
;
363 ch_data
= DPA_AUX_CH_DATA1
;
366 ch_ctl
= PCH_DPB_AUX_CH_CTL
;
367 ch_data
= PCH_DPB_AUX_CH_DATA1
;
370 ch_ctl
= PCH_DPC_AUX_CH_CTL
;
371 ch_data
= PCH_DPC_AUX_CH_DATA1
;
374 ch_ctl
= PCH_DPD_AUX_CH_CTL
;
375 ch_data
= PCH_DPD_AUX_CH_DATA1
;
382 intel_dp_check_edp(intel_dp
);
383 /* The clock divider is based off the hrawclk,
384 * and would like to run at 2MHz. So, take the
385 * hrawclk value and divide by 2 and use that
387 * Note that PCH attached eDP panels should use a 125MHz input
390 if (is_cpu_edp(intel_dp
)) {
391 if (IS_VALLEYVIEW(dev
))
392 aux_clock_divider
= 100;
393 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
394 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
396 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
397 } else if (HAS_PCH_SPLIT(dev
))
398 aux_clock_divider
= 63; /* IRL input clock fixed at 125Mhz */
400 aux_clock_divider
= intel_hrawclk(dev
) / 2;
407 /* Try to wait for any previous AUX channel activity */
408 for (try = 0; try < 3; try++) {
409 status
= I915_READ(ch_ctl
);
410 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
416 WARN(1, "dp_aux_ch not started status 0x%08x\n",
421 /* Must try at least 3 times according to DP spec */
422 for (try = 0; try < 5; try++) {
423 /* Load the send data into the aux channel data registers */
424 for (i
= 0; i
< send_bytes
; i
+= 4)
425 I915_WRITE(ch_data
+ i
,
426 pack_aux(send
+ i
, send_bytes
- i
));
428 /* Send the command and wait for it to complete */
430 DP_AUX_CH_CTL_SEND_BUSY
|
431 DP_AUX_CH_CTL_TIME_OUT_400us
|
432 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
433 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
434 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
436 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
437 DP_AUX_CH_CTL_RECEIVE_ERROR
);
439 status
= I915_READ(ch_ctl
);
440 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
445 /* Clear done status and any errors */
449 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
450 DP_AUX_CH_CTL_RECEIVE_ERROR
);
452 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
453 DP_AUX_CH_CTL_RECEIVE_ERROR
))
455 if (status
& DP_AUX_CH_CTL_DONE
)
459 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
460 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
464 /* Check for timeout or receive error.
465 * Timeouts occur when the sink is not connected
467 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
468 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
472 /* Timeouts occur when the device isn't connected, so they're
473 * "normal" -- don't fill the kernel log with these */
474 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
475 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
479 /* Unload any bytes sent back from the other side */
480 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
481 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
482 if (recv_bytes
> recv_size
)
483 recv_bytes
= recv_size
;
485 for (i
= 0; i
< recv_bytes
; i
+= 4)
486 unpack_aux(I915_READ(ch_data
+ i
),
487 recv
+ i
, recv_bytes
- i
);
492 /* Write data to the aux channel in native mode */
494 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
495 uint16_t address
, uint8_t *send
, int send_bytes
)
502 intel_dp_check_edp(intel_dp
);
505 msg
[0] = AUX_NATIVE_WRITE
<< 4;
506 msg
[1] = address
>> 8;
507 msg
[2] = address
& 0xff;
508 msg
[3] = send_bytes
- 1;
509 memcpy(&msg
[4], send
, send_bytes
);
510 msg_bytes
= send_bytes
+ 4;
512 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
515 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
517 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
525 /* Write a single byte to the aux channel in native mode */
527 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
528 uint16_t address
, uint8_t byte
)
530 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
533 /* read bytes from a native aux channel */
535 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
536 uint16_t address
, uint8_t *recv
, int recv_bytes
)
545 intel_dp_check_edp(intel_dp
);
546 msg
[0] = AUX_NATIVE_READ
<< 4;
547 msg
[1] = address
>> 8;
548 msg
[2] = address
& 0xff;
549 msg
[3] = recv_bytes
- 1;
552 reply_bytes
= recv_bytes
+ 1;
555 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
562 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
563 memcpy(recv
, reply
+ 1, ret
- 1);
566 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
574 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
575 uint8_t write_byte
, uint8_t *read_byte
)
577 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
578 struct intel_dp
*intel_dp
= container_of(adapter
,
581 uint16_t address
= algo_data
->address
;
589 intel_dp_check_edp(intel_dp
);
590 /* Set up the command byte */
591 if (mode
& MODE_I2C_READ
)
592 msg
[0] = AUX_I2C_READ
<< 4;
594 msg
[0] = AUX_I2C_WRITE
<< 4;
596 if (!(mode
& MODE_I2C_STOP
))
597 msg
[0] |= AUX_I2C_MOT
<< 4;
599 msg
[1] = address
>> 8;
620 for (retry
= 0; retry
< 5; retry
++) {
621 ret
= intel_dp_aux_ch(intel_dp
,
625 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
629 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
630 case AUX_NATIVE_REPLY_ACK
:
631 /* I2C-over-AUX Reply field is only valid
632 * when paired with AUX ACK.
635 case AUX_NATIVE_REPLY_NACK
:
636 DRM_DEBUG_KMS("aux_ch native nack\n");
638 case AUX_NATIVE_REPLY_DEFER
:
642 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
647 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
648 case AUX_I2C_REPLY_ACK
:
649 if (mode
== MODE_I2C_READ
) {
650 *read_byte
= reply
[1];
652 return reply_bytes
- 1;
653 case AUX_I2C_REPLY_NACK
:
654 DRM_DEBUG_KMS("aux_i2c nack\n");
656 case AUX_I2C_REPLY_DEFER
:
657 DRM_DEBUG_KMS("aux_i2c defer\n");
661 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
666 DRM_ERROR("too many retries, giving up\n");
670 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
671 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
674 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
675 struct intel_connector
*intel_connector
, const char *name
)
679 DRM_DEBUG_KMS("i2c_init %s\n", name
);
680 intel_dp
->algo
.running
= false;
681 intel_dp
->algo
.address
= 0;
682 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
684 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
685 intel_dp
->adapter
.owner
= THIS_MODULE
;
686 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
687 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
688 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
689 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
690 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
692 ironlake_edp_panel_vdd_on(intel_dp
);
693 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
694 ironlake_edp_panel_vdd_off(intel_dp
, false);
699 intel_dp_mode_fixup(struct drm_encoder
*encoder
,
700 const struct drm_display_mode
*mode
,
701 struct drm_display_mode
*adjusted_mode
)
703 struct drm_device
*dev
= encoder
->dev
;
704 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
705 int lane_count
, clock
;
706 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
707 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
709 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
711 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
712 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
713 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
714 mode
, adjusted_mode
);
717 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
720 DRM_DEBUG_KMS("DP link computation with max lane count %i "
721 "max bw %02x pixel clock %iKHz\n",
722 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
724 if (!intel_dp_adjust_dithering(intel_dp
, adjusted_mode
, true))
727 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
728 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
730 for (clock
= 0; clock
<= max_clock
; clock
++) {
731 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
732 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
734 if (mode_rate
<= link_avail
) {
735 intel_dp
->link_bw
= bws
[clock
];
736 intel_dp
->lane_count
= lane_count
;
737 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
738 DRM_DEBUG_KMS("DP link bw %02x lane "
739 "count %d clock %d bpp %d\n",
740 intel_dp
->link_bw
, intel_dp
->lane_count
,
741 adjusted_mode
->clock
, bpp
);
742 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
743 mode_rate
, link_avail
);
752 struct intel_dp_m_n
{
761 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
763 while (*num
> 0xffffff || *den
> 0xffffff) {
770 intel_dp_compute_m_n(int bpp
,
774 struct intel_dp_m_n
*m_n
)
777 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
778 m_n
->gmch_n
= link_clock
* nlanes
;
779 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
780 m_n
->link_m
= pixel_clock
;
781 m_n
->link_n
= link_clock
;
782 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
786 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
787 struct drm_display_mode
*adjusted_mode
)
789 struct drm_device
*dev
= crtc
->dev
;
790 struct intel_encoder
*encoder
;
791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
792 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
794 struct intel_dp_m_n m_n
;
795 int pipe
= intel_crtc
->pipe
;
798 * Find the lane count in the intel_encoder private
800 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
801 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
803 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
804 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
806 lane_count
= intel_dp
->lane_count
;
812 * Compute the GMCH and Link ratios. The '3' here is
813 * the number of bytes_per_pixel post-LUT, which we always
814 * set up for 8-bits of R/G/B, or 3 bytes total.
816 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
817 mode
->clock
, adjusted_mode
->clock
, &m_n
);
819 if (HAS_PCH_SPLIT(dev
)) {
820 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
821 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
822 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
823 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
824 } else if (IS_VALLEYVIEW(dev
)) {
825 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
826 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
827 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
828 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
830 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
831 TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
832 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
833 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
834 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
838 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
840 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
841 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
842 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
843 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
845 * Check for DPCD version > 1.1 and enhanced framing support
847 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
848 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
849 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
854 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
855 struct drm_display_mode
*adjusted_mode
)
857 struct drm_device
*dev
= encoder
->dev
;
858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
859 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
860 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
861 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
864 * There are four kinds of DP registers:
871 * IBX PCH and CPU are the same for almost everything,
872 * except that the CPU DP PLL is configured in this
875 * CPT PCH is quite different, having many bits moved
876 * to the TRANS_DP_CTL register instead. That
877 * configuration happens (oddly) in ironlake_pch_enable
880 /* Preserve the BIOS-computed detected bit. This is
881 * supposed to be read-only.
883 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
885 /* Handle DP bits in common between all three register formats */
886 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
888 switch (intel_dp
->lane_count
) {
890 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
893 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
896 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
899 if (intel_dp
->has_audio
) {
900 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
901 pipe_name(intel_crtc
->pipe
));
902 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
903 intel_write_eld(encoder
, adjusted_mode
);
906 intel_dp_init_link_config(intel_dp
);
908 /* Split out the IBX/CPU vs CPT settings */
910 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
911 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
912 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
913 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
914 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
915 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
917 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
918 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
920 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
922 /* don't miss out required setting for eDP */
923 if (adjusted_mode
->clock
< 200000)
924 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
926 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
927 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
928 intel_dp
->DP
|= intel_dp
->color_range
;
930 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
931 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
932 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
933 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
934 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
936 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
937 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
939 if (intel_crtc
->pipe
== 1)
940 intel_dp
->DP
|= DP_PIPEB_SELECT
;
942 if (is_cpu_edp(intel_dp
)) {
943 /* don't miss out required setting for eDP */
944 if (adjusted_mode
->clock
< 200000)
945 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
947 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
950 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
954 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
955 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
957 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
958 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
960 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
961 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
963 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
967 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
972 I915_READ(PCH_PP_STATUS
),
973 I915_READ(PCH_PP_CONTROL
));
975 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
976 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
977 I915_READ(PCH_PP_STATUS
),
978 I915_READ(PCH_PP_CONTROL
));
982 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
984 DRM_DEBUG_KMS("Wait for panel power on\n");
985 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
988 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
990 DRM_DEBUG_KMS("Wait for panel power off time\n");
991 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
994 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
996 DRM_DEBUG_KMS("Wait for panel power cycle\n");
997 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1001 /* Read the current pp_control value, unlocking the register if it
1005 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
1007 u32 control
= I915_READ(PCH_PP_CONTROL
);
1009 control
&= ~PANEL_UNLOCK_MASK
;
1010 control
|= PANEL_UNLOCK_REGS
;
1014 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1016 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1020 if (!is_edp(intel_dp
))
1022 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1024 WARN(intel_dp
->want_panel_vdd
,
1025 "eDP VDD already requested on\n");
1027 intel_dp
->want_panel_vdd
= true;
1029 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1030 DRM_DEBUG_KMS("eDP VDD already on\n");
1034 if (!ironlake_edp_have_panel_power(intel_dp
))
1035 ironlake_wait_panel_power_cycle(intel_dp
);
1037 pp
= ironlake_get_pp_control(dev_priv
);
1038 pp
|= EDP_FORCE_VDD
;
1039 I915_WRITE(PCH_PP_CONTROL
, pp
);
1040 POSTING_READ(PCH_PP_CONTROL
);
1041 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1042 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1045 * If the panel wasn't on, delay before accessing aux channel
1047 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1048 DRM_DEBUG_KMS("eDP was not running\n");
1049 msleep(intel_dp
->panel_power_up_delay
);
1053 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1055 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1059 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1060 pp
= ironlake_get_pp_control(dev_priv
);
1061 pp
&= ~EDP_FORCE_VDD
;
1062 I915_WRITE(PCH_PP_CONTROL
, pp
);
1063 POSTING_READ(PCH_PP_CONTROL
);
1065 /* Make sure sequencer is idle before allowing subsequent activity */
1066 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1067 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1069 msleep(intel_dp
->panel_power_down_delay
);
1073 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1075 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1076 struct intel_dp
, panel_vdd_work
);
1077 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1079 mutex_lock(&dev
->mode_config
.mutex
);
1080 ironlake_panel_vdd_off_sync(intel_dp
);
1081 mutex_unlock(&dev
->mode_config
.mutex
);
1084 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1086 if (!is_edp(intel_dp
))
1089 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1090 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1092 intel_dp
->want_panel_vdd
= false;
1095 ironlake_panel_vdd_off_sync(intel_dp
);
1098 * Queue the timer to fire a long
1099 * time from now (relative to the power down delay)
1100 * to keep the panel power up across a sequence of operations
1102 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1103 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1107 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1109 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1113 if (!is_edp(intel_dp
))
1116 DRM_DEBUG_KMS("Turn eDP power on\n");
1118 if (ironlake_edp_have_panel_power(intel_dp
)) {
1119 DRM_DEBUG_KMS("eDP power already on\n");
1123 ironlake_wait_panel_power_cycle(intel_dp
);
1125 pp
= ironlake_get_pp_control(dev_priv
);
1127 /* ILK workaround: disable reset around power sequence */
1128 pp
&= ~PANEL_POWER_RESET
;
1129 I915_WRITE(PCH_PP_CONTROL
, pp
);
1130 POSTING_READ(PCH_PP_CONTROL
);
1133 pp
|= POWER_TARGET_ON
;
1135 pp
|= PANEL_POWER_RESET
;
1137 I915_WRITE(PCH_PP_CONTROL
, pp
);
1138 POSTING_READ(PCH_PP_CONTROL
);
1140 ironlake_wait_panel_on(intel_dp
);
1143 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1144 I915_WRITE(PCH_PP_CONTROL
, pp
);
1145 POSTING_READ(PCH_PP_CONTROL
);
1149 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1151 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1155 if (!is_edp(intel_dp
))
1158 DRM_DEBUG_KMS("Turn eDP power off\n");
1160 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1162 pp
= ironlake_get_pp_control(dev_priv
);
1163 /* We need to switch off panel power _and_ force vdd, for otherwise some
1164 * panels get very unhappy and cease to work. */
1165 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1166 I915_WRITE(PCH_PP_CONTROL
, pp
);
1167 POSTING_READ(PCH_PP_CONTROL
);
1169 intel_dp
->want_panel_vdd
= false;
1171 ironlake_wait_panel_off(intel_dp
);
1174 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1176 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 if (!is_edp(intel_dp
))
1183 DRM_DEBUG_KMS("\n");
1185 * If we enable the backlight right away following a panel power
1186 * on, we may see slight flicker as the panel syncs with the eDP
1187 * link. So delay a bit to make sure the image is solid before
1188 * allowing it to appear.
1190 msleep(intel_dp
->backlight_on_delay
);
1191 pp
= ironlake_get_pp_control(dev_priv
);
1192 pp
|= EDP_BLC_ENABLE
;
1193 I915_WRITE(PCH_PP_CONTROL
, pp
);
1194 POSTING_READ(PCH_PP_CONTROL
);
1197 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1199 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1203 if (!is_edp(intel_dp
))
1206 DRM_DEBUG_KMS("\n");
1207 pp
= ironlake_get_pp_control(dev_priv
);
1208 pp
&= ~EDP_BLC_ENABLE
;
1209 I915_WRITE(PCH_PP_CONTROL
, pp
);
1210 POSTING_READ(PCH_PP_CONTROL
);
1211 msleep(intel_dp
->backlight_off_delay
);
1214 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1216 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1217 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1221 assert_pipe_disabled(dev_priv
,
1222 to_intel_crtc(crtc
)->pipe
);
1224 DRM_DEBUG_KMS("\n");
1225 dpa_ctl
= I915_READ(DP_A
);
1226 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1227 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1229 /* We don't adjust intel_dp->DP while tearing down the link, to
1230 * facilitate link retraining (e.g. after hotplug). Hence clear all
1231 * enable bits here to ensure that we don't enable too much. */
1232 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1233 intel_dp
->DP
|= DP_PLL_ENABLE
;
1234 I915_WRITE(DP_A
, intel_dp
->DP
);
1239 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1241 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1242 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1246 assert_pipe_disabled(dev_priv
,
1247 to_intel_crtc(crtc
)->pipe
);
1249 dpa_ctl
= I915_READ(DP_A
);
1250 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1251 "dp pll off, should be on\n");
1252 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1254 /* We can't rely on the value tracked for the DP register in
1255 * intel_dp->DP because link_down must not change that (otherwise link
1256 * re-training will fail. */
1257 dpa_ctl
&= ~DP_PLL_ENABLE
;
1258 I915_WRITE(DP_A
, dpa_ctl
);
1263 /* If the sink supports it, try to set the power state appropriately */
1264 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1268 /* Should have a valid DPCD by this point */
1269 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1272 if (mode
!= DRM_MODE_DPMS_ON
) {
1273 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1276 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1279 * When turning on, we need to retry for 1ms to give the sink
1282 for (i
= 0; i
< 3; i
++) {
1283 ret
= intel_dp_aux_native_write_1(intel_dp
,
1293 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1296 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1297 struct drm_device
*dev
= encoder
->base
.dev
;
1298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1299 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1301 if (!(tmp
& DP_PORT_EN
))
1304 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
1305 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1306 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1307 *pipe
= PORT_TO_PIPE(tmp
);
1313 switch (intel_dp
->output_reg
) {
1315 trans_sel
= TRANS_DP_PORT_SEL_B
;
1318 trans_sel
= TRANS_DP_PORT_SEL_C
;
1321 trans_sel
= TRANS_DP_PORT_SEL_D
;
1328 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1329 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1336 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp
->output_reg
);
1341 static void intel_disable_dp(struct intel_encoder
*encoder
)
1343 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1345 /* Make sure the panel is off before trying to change the mode. But also
1346 * ensure that we have vdd while we switch off the panel. */
1347 ironlake_edp_panel_vdd_on(intel_dp
);
1348 ironlake_edp_backlight_off(intel_dp
);
1349 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1350 ironlake_edp_panel_off(intel_dp
);
1352 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1353 if (!is_cpu_edp(intel_dp
))
1354 intel_dp_link_down(intel_dp
);
1357 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1359 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1361 if (is_cpu_edp(intel_dp
)) {
1362 intel_dp_link_down(intel_dp
);
1363 ironlake_edp_pll_off(intel_dp
);
1367 static void intel_enable_dp(struct intel_encoder
*encoder
)
1369 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1370 struct drm_device
*dev
= encoder
->base
.dev
;
1371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1372 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1374 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1377 ironlake_edp_panel_vdd_on(intel_dp
);
1378 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1379 intel_dp_start_link_train(intel_dp
);
1380 ironlake_edp_panel_on(intel_dp
);
1381 ironlake_edp_panel_vdd_off(intel_dp
, true);
1382 intel_dp_complete_link_train(intel_dp
);
1383 ironlake_edp_backlight_on(intel_dp
);
1386 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1388 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1390 if (is_cpu_edp(intel_dp
))
1391 ironlake_edp_pll_on(intel_dp
);
1395 * Native read with retry for link status and receiver capability reads for
1396 * cases where the sink may still be asleep.
1399 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1400 uint8_t *recv
, int recv_bytes
)
1405 * Sinks are *supposed* to come up within 1ms from an off state,
1406 * but we're also supposed to retry 3 times per the spec.
1408 for (i
= 0; i
< 3; i
++) {
1409 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1411 if (ret
== recv_bytes
)
1420 * Fetch AUX CH registers 0x202 - 0x207 which contain
1421 * link status information
1424 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1426 return intel_dp_aux_native_read_retry(intel_dp
,
1429 DP_LINK_STATUS_SIZE
);
1433 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1436 return link_status
[r
- DP_LANE0_1_STATUS
];
1440 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1443 int s
= ((lane
& 1) ?
1444 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1445 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1446 uint8_t l
= adjust_request
[lane
>>1];
1448 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1452 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1455 int s
= ((lane
& 1) ?
1456 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1457 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1458 uint8_t l
= adjust_request
[lane
>>1];
1460 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1465 static char *voltage_names
[] = {
1466 "0.4V", "0.6V", "0.8V", "1.2V"
1468 static char *pre_emph_names
[] = {
1469 "0dB", "3.5dB", "6dB", "9.5dB"
1471 static char *link_train_names
[] = {
1472 "pattern 1", "pattern 2", "idle", "off"
1477 * These are source-specific values; current Intel hardware supports
1478 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1482 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1484 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1486 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1487 return DP_TRAIN_VOLTAGE_SWING_800
;
1488 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1489 return DP_TRAIN_VOLTAGE_SWING_1200
;
1491 return DP_TRAIN_VOLTAGE_SWING_800
;
1495 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1497 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1499 if (IS_HASWELL(dev
)) {
1500 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1501 case DP_TRAIN_VOLTAGE_SWING_400
:
1502 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1503 case DP_TRAIN_VOLTAGE_SWING_600
:
1504 return DP_TRAIN_PRE_EMPHASIS_6
;
1505 case DP_TRAIN_VOLTAGE_SWING_800
:
1506 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1507 case DP_TRAIN_VOLTAGE_SWING_1200
:
1509 return DP_TRAIN_PRE_EMPHASIS_0
;
1511 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1512 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1513 case DP_TRAIN_VOLTAGE_SWING_400
:
1514 return DP_TRAIN_PRE_EMPHASIS_6
;
1515 case DP_TRAIN_VOLTAGE_SWING_600
:
1516 case DP_TRAIN_VOLTAGE_SWING_800
:
1517 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1519 return DP_TRAIN_PRE_EMPHASIS_0
;
1522 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1523 case DP_TRAIN_VOLTAGE_SWING_400
:
1524 return DP_TRAIN_PRE_EMPHASIS_6
;
1525 case DP_TRAIN_VOLTAGE_SWING_600
:
1526 return DP_TRAIN_PRE_EMPHASIS_6
;
1527 case DP_TRAIN_VOLTAGE_SWING_800
:
1528 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1529 case DP_TRAIN_VOLTAGE_SWING_1200
:
1531 return DP_TRAIN_PRE_EMPHASIS_0
;
1537 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1542 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1543 uint8_t voltage_max
;
1544 uint8_t preemph_max
;
1546 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1547 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1548 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1556 voltage_max
= intel_dp_voltage_max(intel_dp
);
1557 if (v
>= voltage_max
)
1558 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1560 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1561 if (p
>= preemph_max
)
1562 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1564 for (lane
= 0; lane
< 4; lane
++)
1565 intel_dp
->train_set
[lane
] = v
| p
;
1569 intel_dp_signal_levels(uint8_t train_set
)
1571 uint32_t signal_levels
= 0;
1573 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1574 case DP_TRAIN_VOLTAGE_SWING_400
:
1576 signal_levels
|= DP_VOLTAGE_0_4
;
1578 case DP_TRAIN_VOLTAGE_SWING_600
:
1579 signal_levels
|= DP_VOLTAGE_0_6
;
1581 case DP_TRAIN_VOLTAGE_SWING_800
:
1582 signal_levels
|= DP_VOLTAGE_0_8
;
1584 case DP_TRAIN_VOLTAGE_SWING_1200
:
1585 signal_levels
|= DP_VOLTAGE_1_2
;
1588 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1589 case DP_TRAIN_PRE_EMPHASIS_0
:
1591 signal_levels
|= DP_PRE_EMPHASIS_0
;
1593 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1594 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1596 case DP_TRAIN_PRE_EMPHASIS_6
:
1597 signal_levels
|= DP_PRE_EMPHASIS_6
;
1599 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1600 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1603 return signal_levels
;
1606 /* Gen6's DP voltage swing and pre-emphasis control */
1608 intel_gen6_edp_signal_levels(uint8_t train_set
)
1610 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1611 DP_TRAIN_PRE_EMPHASIS_MASK
);
1612 switch (signal_levels
) {
1613 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1614 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1615 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1616 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1617 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1618 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1619 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1620 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1621 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1622 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1623 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1624 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1625 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1626 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1628 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1629 "0x%x\n", signal_levels
);
1630 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1634 /* Gen7's DP voltage swing and pre-emphasis control */
1636 intel_gen7_edp_signal_levels(uint8_t train_set
)
1638 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1639 DP_TRAIN_PRE_EMPHASIS_MASK
);
1640 switch (signal_levels
) {
1641 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1642 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1643 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1644 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1645 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1646 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1648 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1649 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1650 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1651 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1653 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1654 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1655 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1656 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1659 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1660 "0x%x\n", signal_levels
);
1661 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1665 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1667 intel_dp_signal_levels_hsw(uint8_t train_set
)
1669 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1670 DP_TRAIN_PRE_EMPHASIS_MASK
);
1671 switch (signal_levels
) {
1672 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1673 return DDI_BUF_EMP_400MV_0DB_HSW
;
1674 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1675 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1676 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1677 return DDI_BUF_EMP_400MV_6DB_HSW
;
1678 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1679 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1681 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1682 return DDI_BUF_EMP_600MV_0DB_HSW
;
1683 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1684 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1685 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1686 return DDI_BUF_EMP_600MV_6DB_HSW
;
1688 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1689 return DDI_BUF_EMP_800MV_0DB_HSW
;
1690 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1691 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1693 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1694 "0x%x\n", signal_levels
);
1695 return DDI_BUF_EMP_400MV_0DB_HSW
;
1700 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1703 int s
= (lane
& 1) * 4;
1704 uint8_t l
= link_status
[lane
>>1];
1706 return (l
>> s
) & 0xf;
1709 /* Check for clock recovery is done on all channels */
1711 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1714 uint8_t lane_status
;
1716 for (lane
= 0; lane
< lane_count
; lane
++) {
1717 lane_status
= intel_get_lane_status(link_status
, lane
);
1718 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1724 /* Check to see if channel eq is done on all channels */
1725 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1726 DP_LANE_CHANNEL_EQ_DONE|\
1727 DP_LANE_SYMBOL_LOCKED)
1729 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1732 uint8_t lane_status
;
1735 lane_align
= intel_dp_link_status(link_status
,
1736 DP_LANE_ALIGN_STATUS_UPDATED
);
1737 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1739 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1740 lane_status
= intel_get_lane_status(link_status
, lane
);
1741 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1748 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1749 uint32_t dp_reg_value
,
1750 uint8_t dp_train_pat
)
1752 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1757 if (IS_HASWELL(dev
)) {
1758 temp
= I915_READ(DP_TP_CTL(intel_dp
->port
));
1760 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1761 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1763 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1765 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1766 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1767 case DP_TRAINING_PATTERN_DISABLE
:
1768 temp
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
1769 I915_WRITE(DP_TP_CTL(intel_dp
->port
), temp
);
1771 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp
->port
)) &
1772 DP_TP_STATUS_IDLE_DONE
), 1))
1773 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1775 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1776 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1779 case DP_TRAINING_PATTERN_1
:
1780 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1782 case DP_TRAINING_PATTERN_2
:
1783 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1785 case DP_TRAINING_PATTERN_3
:
1786 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1789 I915_WRITE(DP_TP_CTL(intel_dp
->port
), temp
);
1791 } else if (HAS_PCH_CPT(dev
) &&
1792 (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1793 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1795 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1796 case DP_TRAINING_PATTERN_DISABLE
:
1797 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1799 case DP_TRAINING_PATTERN_1
:
1800 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1802 case DP_TRAINING_PATTERN_2
:
1803 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1805 case DP_TRAINING_PATTERN_3
:
1806 DRM_ERROR("DP training pattern 3 not supported\n");
1807 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1812 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1814 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1815 case DP_TRAINING_PATTERN_DISABLE
:
1816 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1818 case DP_TRAINING_PATTERN_1
:
1819 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1821 case DP_TRAINING_PATTERN_2
:
1822 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1824 case DP_TRAINING_PATTERN_3
:
1825 DRM_ERROR("DP training pattern 3 not supported\n");
1826 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1831 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1832 POSTING_READ(intel_dp
->output_reg
);
1834 intel_dp_aux_native_write_1(intel_dp
,
1835 DP_TRAINING_PATTERN_SET
,
1838 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1839 DP_TRAINING_PATTERN_DISABLE
) {
1840 ret
= intel_dp_aux_native_write(intel_dp
,
1841 DP_TRAINING_LANE0_SET
,
1842 intel_dp
->train_set
,
1843 intel_dp
->lane_count
);
1844 if (ret
!= intel_dp
->lane_count
)
1851 /* Enable corresponding port and start training pattern 1 */
1853 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1855 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1858 bool clock_recovery
= false;
1859 int voltage_tries
, loop_tries
;
1860 uint32_t DP
= intel_dp
->DP
;
1862 /* Write the link configuration data */
1863 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1864 intel_dp
->link_configuration
,
1865 DP_LINK_CONFIGURATION_SIZE
);
1869 memset(intel_dp
->train_set
, 0, 4);
1873 clock_recovery
= false;
1875 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1876 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1877 uint32_t signal_levels
;
1879 if (IS_HASWELL(dev
)) {
1880 signal_levels
= intel_dp_signal_levels_hsw(
1881 intel_dp
->train_set
[0]);
1882 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1883 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1884 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1885 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1886 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1887 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1888 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1890 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1891 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1893 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1896 if (!intel_dp_set_link_train(intel_dp
, DP
,
1897 DP_TRAINING_PATTERN_1
|
1898 DP_LINK_SCRAMBLING_DISABLE
))
1900 /* Set training pattern 1 */
1903 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1904 DRM_ERROR("failed to get link status\n");
1908 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1909 DRM_DEBUG_KMS("clock recovery OK\n");
1910 clock_recovery
= true;
1914 /* Check to see if we've tried the max voltage */
1915 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1916 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1918 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1920 if (loop_tries
== 5) {
1921 DRM_DEBUG_KMS("too many full retries, give up\n");
1924 memset(intel_dp
->train_set
, 0, 4);
1929 /* Check to see if we've tried the same voltage 5 times */
1930 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1932 if (voltage_tries
== 5) {
1933 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1938 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1940 /* Compute new intel_dp->train_set as requested by target */
1941 intel_get_adjust_train(intel_dp
, link_status
);
1948 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1950 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1951 bool channel_eq
= false;
1952 int tries
, cr_tries
;
1953 uint32_t DP
= intel_dp
->DP
;
1955 /* channel equalization */
1960 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1961 uint32_t signal_levels
;
1962 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1965 DRM_ERROR("failed to train DP, aborting\n");
1966 intel_dp_link_down(intel_dp
);
1970 if (IS_HASWELL(dev
)) {
1971 signal_levels
= intel_dp_signal_levels_hsw(intel_dp
->train_set
[0]);
1972 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1973 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1974 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1975 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1976 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1977 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1978 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1980 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1981 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1984 /* channel eq pattern */
1985 if (!intel_dp_set_link_train(intel_dp
, DP
,
1986 DP_TRAINING_PATTERN_2
|
1987 DP_LINK_SCRAMBLING_DISABLE
))
1991 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1994 /* Make sure clock is still ok */
1995 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1996 intel_dp_start_link_train(intel_dp
);
2001 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
2006 /* Try 5 times, then try clock recovery if that fails */
2008 intel_dp_link_down(intel_dp
);
2009 intel_dp_start_link_train(intel_dp
);
2015 /* Compute new intel_dp->train_set as requested by target */
2016 intel_get_adjust_train(intel_dp
, link_status
);
2021 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2023 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
2027 intel_dp_link_down(struct intel_dp
*intel_dp
)
2029 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2031 uint32_t DP
= intel_dp
->DP
;
2033 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2036 DRM_DEBUG_KMS("\n");
2038 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
2039 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2040 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2042 DP
&= ~DP_LINK_TRAIN_MASK
;
2043 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2045 POSTING_READ(intel_dp
->output_reg
);
2049 if (HAS_PCH_IBX(dev
) &&
2050 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2051 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2053 /* Hardware workaround: leaving our transcoder select
2054 * set to transcoder B while it's off will prevent the
2055 * corresponding HDMI output on transcoder A.
2057 * Combine this with another hardware workaround:
2058 * transcoder select bit can only be cleared while the
2061 DP
&= ~DP_PIPEB_SELECT
;
2062 I915_WRITE(intel_dp
->output_reg
, DP
);
2064 /* Changes to enable or select take place the vblank
2065 * after being written.
2068 /* We can arrive here never having been attached
2069 * to a CRTC, for instance, due to inheriting
2070 * random state from the BIOS.
2072 * If the pipe is not running, play safe and
2073 * wait for the clocks to stabilise before
2076 POSTING_READ(intel_dp
->output_reg
);
2079 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
2082 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2083 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2084 POSTING_READ(intel_dp
->output_reg
);
2085 msleep(intel_dp
->panel_power_down_delay
);
2089 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2091 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2092 sizeof(intel_dp
->dpcd
)) == 0)
2093 return false; /* aux transfer failed */
2095 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2096 return false; /* DPCD not present */
2098 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2099 DP_DWN_STRM_PORT_PRESENT
))
2100 return true; /* native DP sink */
2102 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2103 return true; /* no per-port downstream info */
2105 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2106 intel_dp
->downstream_ports
,
2107 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2108 return false; /* downstream port status fetch failed */
2114 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2118 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2121 ironlake_edp_panel_vdd_on(intel_dp
);
2123 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2124 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2125 buf
[0], buf
[1], buf
[2]);
2127 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2128 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2129 buf
[0], buf
[1], buf
[2]);
2131 ironlake_edp_panel_vdd_off(intel_dp
, false);
2135 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2139 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2140 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2141 sink_irq_vector
, 1);
2149 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2151 /* NAK by default */
2152 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
2156 * According to DP spec
2159 * 2. Configure link according to Receiver Capabilities
2160 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2161 * 4. Check link status on receipt of hot-plug interrupt
2165 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2168 u8 link_status
[DP_LINK_STATUS_SIZE
];
2170 if (!intel_dp
->base
.connectors_active
)
2173 if (WARN_ON(!intel_dp
->base
.base
.crtc
))
2176 /* Try to read receiver status if the link appears to be up */
2177 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2178 intel_dp_link_down(intel_dp
);
2182 /* Now read the DPCD to see if it's actually running */
2183 if (!intel_dp_get_dpcd(intel_dp
)) {
2184 intel_dp_link_down(intel_dp
);
2188 /* Try to read the source of the interrupt */
2189 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2190 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2191 /* Clear interrupt source */
2192 intel_dp_aux_native_write_1(intel_dp
,
2193 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2196 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2197 intel_dp_handle_test_request(intel_dp
);
2198 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2199 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2202 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
2203 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2204 drm_get_encoder_name(&intel_dp
->base
.base
));
2205 intel_dp_start_link_train(intel_dp
);
2206 intel_dp_complete_link_train(intel_dp
);
2210 /* XXX this is probably wrong for multiple downstream ports */
2211 static enum drm_connector_status
2212 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2214 uint8_t *dpcd
= intel_dp
->dpcd
;
2218 if (!intel_dp_get_dpcd(intel_dp
))
2219 return connector_status_disconnected
;
2221 /* if there's no downstream port, we're done */
2222 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2223 return connector_status_connected
;
2225 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2226 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2229 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2231 return connector_status_unknown
;
2232 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2233 : connector_status_disconnected
;
2236 /* If no HPD, poke DDC gently */
2237 if (drm_probe_ddc(&intel_dp
->adapter
))
2238 return connector_status_connected
;
2240 /* Well we tried, say unknown for unreliable port types */
2241 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2242 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2243 return connector_status_unknown
;
2245 /* Anything else is out of spec, warn and ignore */
2246 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2247 return connector_status_disconnected
;
2250 static enum drm_connector_status
2251 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2253 enum drm_connector_status status
;
2255 /* Can't disconnect eDP, but you can close the lid... */
2256 if (is_edp(intel_dp
)) {
2257 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2258 if (status
== connector_status_unknown
)
2259 status
= connector_status_connected
;
2263 return intel_dp_detect_dpcd(intel_dp
);
2266 static enum drm_connector_status
2267 g4x_dp_detect(struct intel_dp
*intel_dp
)
2269 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2273 switch (intel_dp
->output_reg
) {
2275 bit
= DPB_HOTPLUG_LIVE_STATUS
;
2278 bit
= DPC_HOTPLUG_LIVE_STATUS
;
2281 bit
= DPD_HOTPLUG_LIVE_STATUS
;
2284 return connector_status_unknown
;
2287 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2288 return connector_status_disconnected
;
2290 return intel_dp_detect_dpcd(intel_dp
);
2293 static struct edid
*
2294 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2296 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2300 if (is_edp(intel_dp
)) {
2301 if (!intel_dp
->edid
)
2304 size
= (intel_dp
->edid
->extensions
+ 1) * EDID_LENGTH
;
2305 edid
= kmalloc(size
, GFP_KERNEL
);
2309 memcpy(edid
, intel_dp
->edid
, size
);
2313 edid
= drm_get_edid(connector
, adapter
);
2318 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2320 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2323 if (is_edp(intel_dp
)) {
2324 drm_mode_connector_update_edid_property(connector
,
2326 ret
= drm_add_edid_modes(connector
, intel_dp
->edid
);
2327 drm_edid_to_eld(connector
,
2329 return intel_dp
->edid_mode_count
;
2332 ret
= intel_ddc_get_modes(connector
, adapter
);
2338 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2340 * \return true if DP port is connected.
2341 * \return false if DP port is disconnected.
2343 static enum drm_connector_status
2344 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2346 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2347 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2348 enum drm_connector_status status
;
2349 struct edid
*edid
= NULL
;
2351 intel_dp
->has_audio
= false;
2353 if (HAS_PCH_SPLIT(dev
))
2354 status
= ironlake_dp_detect(intel_dp
);
2356 status
= g4x_dp_detect(intel_dp
);
2358 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2359 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2360 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2361 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2363 if (status
!= connector_status_connected
)
2366 intel_dp_probe_oui(intel_dp
);
2368 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2369 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2371 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2373 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2378 return connector_status_connected
;
2381 static int intel_dp_get_modes(struct drm_connector
*connector
)
2383 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2384 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2388 /* We should parse the EDID data and find out if it has an audio sink
2391 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2393 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2394 struct drm_display_mode
*newmode
;
2395 list_for_each_entry(newmode
, &connector
->probed_modes
,
2397 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2398 intel_dp
->panel_fixed_mode
=
2399 drm_mode_duplicate(dev
, newmode
);
2407 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2408 if (is_edp(intel_dp
)) {
2409 /* initialize panel mode from VBT if available for eDP */
2410 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2411 intel_dp
->panel_fixed_mode
=
2412 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2413 if (intel_dp
->panel_fixed_mode
) {
2414 intel_dp
->panel_fixed_mode
->type
|=
2415 DRM_MODE_TYPE_PREFERRED
;
2418 if (intel_dp
->panel_fixed_mode
) {
2419 struct drm_display_mode
*mode
;
2420 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2421 drm_mode_probed_add(connector
, mode
);
2429 intel_dp_detect_audio(struct drm_connector
*connector
)
2431 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2433 bool has_audio
= false;
2435 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2437 has_audio
= drm_detect_monitor_audio(edid
);
2445 intel_dp_set_property(struct drm_connector
*connector
,
2446 struct drm_property
*property
,
2449 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2450 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2453 ret
= drm_connector_property_set_value(connector
, property
, val
);
2457 if (property
== dev_priv
->force_audio_property
) {
2461 if (i
== intel_dp
->force_audio
)
2464 intel_dp
->force_audio
= i
;
2466 if (i
== HDMI_AUDIO_AUTO
)
2467 has_audio
= intel_dp_detect_audio(connector
);
2469 has_audio
= (i
== HDMI_AUDIO_ON
);
2471 if (has_audio
== intel_dp
->has_audio
)
2474 intel_dp
->has_audio
= has_audio
;
2478 if (property
== dev_priv
->broadcast_rgb_property
) {
2479 if (val
== !!intel_dp
->color_range
)
2482 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2489 if (intel_dp
->base
.base
.crtc
) {
2490 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2491 intel_set_mode(crtc
, &crtc
->mode
,
2492 crtc
->x
, crtc
->y
, crtc
->fb
);
2499 intel_dp_destroy(struct drm_connector
*connector
)
2501 struct drm_device
*dev
= connector
->dev
;
2503 if (intel_dpd_is_edp(dev
))
2504 intel_panel_destroy_backlight(dev
);
2506 drm_sysfs_connector_remove(connector
);
2507 drm_connector_cleanup(connector
);
2511 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2513 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2515 i2c_del_adapter(&intel_dp
->adapter
);
2516 drm_encoder_cleanup(encoder
);
2517 if (is_edp(intel_dp
)) {
2518 kfree(intel_dp
->edid
);
2519 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2520 ironlake_panel_vdd_off_sync(intel_dp
);
2525 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2526 .mode_fixup
= intel_dp_mode_fixup
,
2527 .mode_set
= intel_dp_mode_set
,
2528 .disable
= intel_encoder_noop
,
2531 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2532 .dpms
= intel_connector_dpms
,
2533 .detect
= intel_dp_detect
,
2534 .fill_modes
= drm_helper_probe_single_connector_modes
,
2535 .set_property
= intel_dp_set_property
,
2536 .destroy
= intel_dp_destroy
,
2539 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2540 .get_modes
= intel_dp_get_modes
,
2541 .mode_valid
= intel_dp_mode_valid
,
2542 .best_encoder
= intel_best_encoder
,
2545 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2546 .destroy
= intel_dp_encoder_destroy
,
2550 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2552 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2554 intel_dp_check_link_status(intel_dp
);
2557 /* Return which DP Port should be selected for Transcoder DP control */
2559 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2561 struct drm_device
*dev
= crtc
->dev
;
2562 struct intel_encoder
*encoder
;
2564 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2565 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2567 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2568 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2569 return intel_dp
->output_reg
;
2575 /* check the VBT to see whether the eDP is on DP-D port */
2576 bool intel_dpd_is_edp(struct drm_device
*dev
)
2578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2579 struct child_device_config
*p_child
;
2582 if (!dev_priv
->child_dev_num
)
2585 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2586 p_child
= dev_priv
->child_dev
+ i
;
2588 if (p_child
->dvo_port
== PORT_IDPD
&&
2589 p_child
->device_type
== DEVICE_TYPE_eDP
)
2596 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2598 intel_attach_force_audio_property(connector
);
2599 intel_attach_broadcast_rgb_property(connector
);
2603 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2606 struct drm_connector
*connector
;
2607 struct intel_dp
*intel_dp
;
2608 struct intel_encoder
*intel_encoder
;
2609 struct intel_connector
*intel_connector
;
2610 const char *name
= NULL
;
2613 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2617 intel_dp
->output_reg
= output_reg
;
2618 intel_dp
->port
= port
;
2619 /* Preserve the current hw state. */
2620 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2622 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2623 if (!intel_connector
) {
2627 intel_encoder
= &intel_dp
->base
;
2629 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2630 if (intel_dpd_is_edp(dev
))
2631 intel_dp
->is_pch_edp
= true;
2634 * FIXME : We need to initialize built-in panels before external panels.
2635 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2637 if (IS_VALLEYVIEW(dev
) && output_reg
== DP_C
) {
2638 type
= DRM_MODE_CONNECTOR_eDP
;
2639 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2640 } else if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2641 type
= DRM_MODE_CONNECTOR_eDP
;
2642 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2644 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2645 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2648 connector
= &intel_connector
->base
;
2649 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2650 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2652 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2654 intel_encoder
->cloneable
= false;
2656 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2657 ironlake_panel_vdd_work
);
2659 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2661 connector
->interlace_allowed
= true;
2662 connector
->doublescan_allowed
= 0;
2664 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2665 DRM_MODE_ENCODER_TMDS
);
2666 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2668 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2669 drm_sysfs_connector_add(connector
);
2671 intel_encoder
->enable
= intel_enable_dp
;
2672 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2673 intel_encoder
->disable
= intel_disable_dp
;
2674 intel_encoder
->post_disable
= intel_post_disable_dp
;
2675 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2676 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2678 /* Set up the DDC bus. */
2684 dev_priv
->hotplug_supported_mask
|= DPB_HOTPLUG_INT_STATUS
;
2688 dev_priv
->hotplug_supported_mask
|= DPC_HOTPLUG_INT_STATUS
;
2692 dev_priv
->hotplug_supported_mask
|= DPD_HOTPLUG_INT_STATUS
;
2696 WARN(1, "Invalid port %c\n", port_name(port
));
2700 /* Cache some DPCD data in the eDP case */
2701 if (is_edp(intel_dp
)) {
2702 struct edp_power_seq cur
, vbt
;
2703 u32 pp_on
, pp_off
, pp_div
;
2705 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2706 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2707 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2709 if (!pp_on
|| !pp_off
|| !pp_div
) {
2710 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2711 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2712 intel_dp_destroy(&intel_connector
->base
);
2716 /* Pull timing values out of registers */
2717 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2718 PANEL_POWER_UP_DELAY_SHIFT
;
2720 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2721 PANEL_LIGHT_ON_DELAY_SHIFT
;
2723 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2724 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2726 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2727 PANEL_POWER_DOWN_DELAY_SHIFT
;
2729 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2730 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2732 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2733 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2735 vbt
= dev_priv
->edp
.pps
;
2737 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2738 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2740 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2742 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2743 intel_dp
->backlight_on_delay
= get_delay(t8
);
2744 intel_dp
->backlight_off_delay
= get_delay(t9
);
2745 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2746 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2748 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2749 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2750 intel_dp
->panel_power_cycle_delay
);
2752 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2753 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2756 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2758 if (is_edp(intel_dp
)) {
2762 ironlake_edp_panel_vdd_on(intel_dp
);
2763 ret
= intel_dp_get_dpcd(intel_dp
);
2764 ironlake_edp_panel_vdd_off(intel_dp
, false);
2767 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2768 dev_priv
->no_aux_handshake
=
2769 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2770 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2772 /* if this fails, presume the device is a ghost */
2773 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2774 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2775 intel_dp_destroy(&intel_connector
->base
);
2779 ironlake_edp_panel_vdd_on(intel_dp
);
2780 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2782 drm_mode_connector_update_edid_property(connector
,
2784 intel_dp
->edid_mode_count
=
2785 drm_add_edid_modes(connector
, edid
);
2786 drm_edid_to_eld(connector
, edid
);
2787 intel_dp
->edid
= edid
;
2789 ironlake_edp_panel_vdd_off(intel_dp
, false);
2792 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2794 if (is_edp(intel_dp
)) {
2795 dev_priv
->int_edp_connector
= connector
;
2796 intel_panel_setup_backlight(dev
);
2799 intel_dp_add_properties(intel_dp
, connector
);
2801 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2802 * 0xd. Failure to do so will result in spurious interrupts being
2803 * generated on the port when a cable is not attached.
2805 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2806 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2807 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);