2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll
[] = {
48 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
50 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
53 static const struct dp_link_dpll pch_dpll
[] = {
55 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
57 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
60 static const struct dp_link_dpll vlv_dpll
[] = {
62 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
64 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp
*intel_dp
)
76 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
78 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
81 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
83 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
85 return intel_dig_port
->base
.base
.dev
;
88 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
90 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
93 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
94 static void edp_panel_vdd_on(struct intel_dp
*intel_dp
);
95 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
98 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
100 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
101 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
103 switch (max_link_bw
) {
104 case DP_LINK_BW_1_62
:
107 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev
) || INTEL_INFO(dev
)->gen
>= 8) &&
109 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
110 max_link_bw
= DP_LINK_BW_5_4
;
112 max_link_bw
= DP_LINK_BW_2_7
;
115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw
= DP_LINK_BW_1_62
;
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
129 * 270000 * 1 * 8 / 10 == 216000
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
141 intel_dp_link_required(int pixel_clock
, int bpp
)
143 return (pixel_clock
* bpp
+ 9) / 10;
147 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
149 return (max_link_clock
* max_lanes
* 8) / 10;
152 static enum drm_mode_status
153 intel_dp_mode_valid(struct drm_connector
*connector
,
154 struct drm_display_mode
*mode
)
156 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
157 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
158 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
159 int target_clock
= mode
->clock
;
160 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
162 if (is_edp(intel_dp
) && fixed_mode
) {
163 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
166 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
169 target_clock
= fixed_mode
->clock
;
172 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
173 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
175 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
176 mode_rate
= intel_dp_link_required(target_clock
, 18);
178 if (mode_rate
> max_rate
)
179 return MODE_CLOCK_HIGH
;
181 if (mode
->clock
< 10000)
182 return MODE_CLOCK_LOW
;
184 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
185 return MODE_H_ILLEGAL
;
191 pack_aux(uint8_t *src
, int src_bytes
)
198 for (i
= 0; i
< src_bytes
; i
++)
199 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
204 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
209 for (i
= 0; i
< dst_bytes
; i
++)
210 dst
[i
] = src
>> ((3-i
) * 8);
213 /* hrawclock is 1/4 the FSB frequency */
215 intel_hrawclk(struct drm_device
*dev
)
217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev
))
224 clkcfg
= I915_READ(CLKCFG
);
225 switch (clkcfg
& CLKCFG_FSB_MASK
) {
234 case CLKCFG_FSB_1067
:
236 case CLKCFG_FSB_1333
:
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600
:
240 case CLKCFG_FSB_1600_ALT
:
248 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
249 struct intel_dp
*intel_dp
,
250 struct edp_power_seq
*out
);
252 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
253 struct intel_dp
*intel_dp
,
254 struct edp_power_seq
*out
);
257 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
259 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
260 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
261 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
263 enum port port
= intel_dig_port
->port
;
266 /* modeset should have pipe */
268 return to_intel_crtc(crtc
)->pipe
;
270 /* init time, try to find a pipe with this port selected */
271 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
272 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
273 PANEL_PORT_SELECT_MASK
;
274 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
276 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
284 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
286 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
288 if (HAS_PCH_SPLIT(dev
))
289 return PCH_PP_CONTROL
;
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
294 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
296 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
298 if (HAS_PCH_SPLIT(dev
))
299 return PCH_PP_STATUS
;
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
304 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
306 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
309 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
312 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
314 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 return (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
321 intel_dp_check_edp(struct intel_dp
*intel_dp
)
323 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
326 if (!is_edp(intel_dp
))
329 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
332 I915_READ(_pp_stat_reg(intel_dp
)),
333 I915_READ(_pp_ctrl_reg(intel_dp
)));
338 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
340 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
341 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
343 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
347 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
349 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
350 msecs_to_jiffies_timeout(10));
352 done
= wait_for_atomic(C
, 10) == 0;
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
361 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
363 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
364 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
367 * The clock divider is based off the hrawclk, and would like to run at
368 * 2MHz. So, take the hrawclk value and divide by 2 and use that
370 return index
? 0 : intel_hrawclk(dev
) / 2;
373 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
375 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
376 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
381 if (intel_dig_port
->port
== PORT_A
) {
382 if (IS_GEN6(dev
) || IS_GEN7(dev
))
383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
385 return 225; /* eDP input clock at 450Mhz */
387 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
391 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
393 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
394 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
397 if (intel_dig_port
->port
== PORT_A
) {
400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
401 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
402 /* Workaround for non-ULT HSW */
409 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
413 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
415 return index
? 0 : 100;
418 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
421 uint32_t aux_clock_divider
)
423 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
424 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
425 uint32_t precharge
, timeout
;
432 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
433 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
435 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
437 return DP_AUX_CH_CTL_SEND_BUSY
|
439 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
440 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
442 DP_AUX_CH_CTL_RECEIVE_ERROR
|
443 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
444 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
445 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
449 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
450 uint8_t *send
, int send_bytes
,
451 uint8_t *recv
, int recv_size
)
453 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
454 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
456 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
457 uint32_t ch_data
= ch_ctl
+ 4;
458 uint32_t aux_clock_divider
;
459 int i
, ret
, recv_bytes
;
462 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
464 /* dp aux is extremely sensitive to irq latency, hence request the
465 * lowest possible wakeup latency and so prevent the cpu from going into
468 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
470 intel_dp_check_edp(intel_dp
);
472 intel_aux_display_runtime_get(dev_priv
);
474 /* Try to wait for any previous AUX channel activity */
475 for (try = 0; try < 3; try++) {
476 status
= I915_READ_NOTRACE(ch_ctl
);
477 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
483 WARN(1, "dp_aux_ch not started status 0x%08x\n",
489 /* Only 5 data registers! */
490 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
495 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
496 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
501 /* Must try at least 3 times according to DP spec */
502 for (try = 0; try < 5; try++) {
503 /* Load the send data into the aux channel data registers */
504 for (i
= 0; i
< send_bytes
; i
+= 4)
505 I915_WRITE(ch_data
+ i
,
506 pack_aux(send
+ i
, send_bytes
- i
));
508 /* Send the command and wait for it to complete */
509 I915_WRITE(ch_ctl
, send_ctl
);
511 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
513 /* Clear done status and any errors */
517 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
518 DP_AUX_CH_CTL_RECEIVE_ERROR
);
520 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
521 DP_AUX_CH_CTL_RECEIVE_ERROR
))
523 if (status
& DP_AUX_CH_CTL_DONE
)
526 if (status
& DP_AUX_CH_CTL_DONE
)
530 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
531 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
536 /* Check for timeout or receive error.
537 * Timeouts occur when the sink is not connected
539 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
540 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
545 /* Timeouts occur when the device isn't connected, so they're
546 * "normal" -- don't fill the kernel log with these */
547 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
548 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
553 /* Unload any bytes sent back from the other side */
554 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
555 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
556 if (recv_bytes
> recv_size
)
557 recv_bytes
= recv_size
;
559 for (i
= 0; i
< recv_bytes
; i
+= 4)
560 unpack_aux(I915_READ(ch_data
+ i
),
561 recv
+ i
, recv_bytes
- i
);
565 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
566 intel_aux_display_runtime_put(dev_priv
);
571 /* Write data to the aux channel in native mode */
573 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
574 uint16_t address
, uint8_t *send
, int send_bytes
)
582 if (WARN_ON(send_bytes
> 16))
585 intel_dp_check_edp(intel_dp
);
586 msg
[0] = DP_AUX_NATIVE_WRITE
<< 4;
587 msg
[1] = address
>> 8;
588 msg
[2] = address
& 0xff;
589 msg
[3] = send_bytes
- 1;
590 memcpy(&msg
[4], send
, send_bytes
);
591 msg_bytes
= send_bytes
+ 4;
592 for (retry
= 0; retry
< 7; retry
++) {
593 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
597 if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_ACK
)
599 else if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_DEFER
)
600 usleep_range(400, 500);
605 DRM_ERROR("too many retries, giving up\n");
609 /* Write a single byte to the aux channel in native mode */
611 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
612 uint16_t address
, uint8_t byte
)
614 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
617 /* read bytes from a native aux channel */
619 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
620 uint16_t address
, uint8_t *recv
, int recv_bytes
)
630 if (WARN_ON(recv_bytes
> 19))
633 intel_dp_check_edp(intel_dp
);
634 msg
[0] = DP_AUX_NATIVE_READ
<< 4;
635 msg
[1] = address
>> 8;
636 msg
[2] = address
& 0xff;
637 msg
[3] = recv_bytes
- 1;
640 reply_bytes
= recv_bytes
+ 1;
642 for (retry
= 0; retry
< 7; retry
++) {
643 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
650 if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_ACK
) {
651 memcpy(recv
, reply
+ 1, ret
- 1);
654 else if ((ack
& DP_AUX_NATIVE_REPLY_MASK
) == DP_AUX_NATIVE_REPLY_DEFER
)
655 usleep_range(400, 500);
660 DRM_ERROR("too many retries, giving up\n");
665 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
666 uint8_t write_byte
, uint8_t *read_byte
)
668 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
669 struct intel_dp
*intel_dp
= container_of(adapter
,
672 uint16_t address
= algo_data
->address
;
680 edp_panel_vdd_on(intel_dp
);
681 intel_dp_check_edp(intel_dp
);
682 /* Set up the command byte */
683 if (mode
& MODE_I2C_READ
)
684 msg
[0] = DP_AUX_I2C_READ
<< 4;
686 msg
[0] = DP_AUX_I2C_WRITE
<< 4;
688 if (!(mode
& MODE_I2C_STOP
))
689 msg
[0] |= DP_AUX_I2C_MOT
<< 4;
691 msg
[1] = address
>> 8;
713 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
714 * required to retry at least seven times upon receiving AUX_DEFER
715 * before giving up the AUX transaction.
717 for (retry
= 0; retry
< 7; retry
++) {
718 ret
= intel_dp_aux_ch(intel_dp
,
722 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
726 switch ((reply
[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK
) {
727 case DP_AUX_NATIVE_REPLY_ACK
:
728 /* I2C-over-AUX Reply field is only valid
729 * when paired with AUX ACK.
732 case DP_AUX_NATIVE_REPLY_NACK
:
733 DRM_DEBUG_KMS("aux_ch native nack\n");
736 case DP_AUX_NATIVE_REPLY_DEFER
:
738 * For now, just give more slack to branch devices. We
739 * could check the DPCD for I2C bit rate capabilities,
740 * and if available, adjust the interval. We could also
741 * be more careful with DP-to-Legacy adapters where a
742 * long legacy cable may force very low I2C bit rates.
744 if (intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
745 DP_DWN_STRM_PORT_PRESENT
)
746 usleep_range(500, 600);
748 usleep_range(300, 400);
751 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
757 switch ((reply
[0] >> 4) & DP_AUX_I2C_REPLY_MASK
) {
758 case DP_AUX_I2C_REPLY_ACK
:
759 if (mode
== MODE_I2C_READ
) {
760 *read_byte
= reply
[1];
762 ret
= reply_bytes
- 1;
764 case DP_AUX_I2C_REPLY_NACK
:
765 DRM_DEBUG_KMS("aux_i2c nack\n");
768 case DP_AUX_I2C_REPLY_DEFER
:
769 DRM_DEBUG_KMS("aux_i2c defer\n");
773 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
779 DRM_ERROR("too many retries, giving up\n");
783 edp_panel_vdd_off(intel_dp
, false);
788 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
790 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
792 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
793 intel_dp
->adapter
.dev
.kobj
.name
);
794 intel_connector_unregister(intel_connector
);
798 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
799 struct intel_connector
*intel_connector
, const char *name
)
803 DRM_DEBUG_KMS("i2c_init %s\n", name
);
804 intel_dp
->algo
.running
= false;
805 intel_dp
->algo
.address
= 0;
806 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
808 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
809 intel_dp
->adapter
.owner
= THIS_MODULE
;
810 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
811 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
812 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
813 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
814 intel_dp
->adapter
.dev
.parent
= intel_connector
->base
.dev
->dev
;
816 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
820 ret
= sysfs_create_link(&intel_connector
->base
.kdev
->kobj
,
821 &intel_dp
->adapter
.dev
.kobj
,
822 intel_dp
->adapter
.dev
.kobj
.name
);
825 i2c_del_adapter(&intel_dp
->adapter
);
831 intel_dp_set_clock(struct intel_encoder
*encoder
,
832 struct intel_crtc_config
*pipe_config
, int link_bw
)
834 struct drm_device
*dev
= encoder
->base
.dev
;
835 const struct dp_link_dpll
*divisor
= NULL
;
840 count
= ARRAY_SIZE(gen4_dpll
);
841 } else if (IS_HASWELL(dev
)) {
842 /* Haswell has special-purpose DP DDI clocks. */
843 } else if (HAS_PCH_SPLIT(dev
)) {
845 count
= ARRAY_SIZE(pch_dpll
);
846 } else if (IS_VALLEYVIEW(dev
)) {
848 count
= ARRAY_SIZE(vlv_dpll
);
851 if (divisor
&& count
) {
852 for (i
= 0; i
< count
; i
++) {
853 if (link_bw
== divisor
[i
].link_bw
) {
854 pipe_config
->dpll
= divisor
[i
].dpll
;
855 pipe_config
->clock_set
= true;
863 intel_dp_compute_config(struct intel_encoder
*encoder
,
864 struct intel_crtc_config
*pipe_config
)
866 struct drm_device
*dev
= encoder
->base
.dev
;
867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
868 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
869 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
870 enum port port
= dp_to_dig_port(intel_dp
)->port
;
871 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
872 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
873 int lane_count
, clock
;
874 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
875 /* Conveniently, the link BW constants become indices with a shift...*/
876 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
878 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
879 int link_avail
, link_clock
;
881 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
882 pipe_config
->has_pch_encoder
= true;
884 pipe_config
->has_dp_encoder
= true;
886 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
887 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
889 if (!HAS_PCH_SPLIT(dev
))
890 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
891 intel_connector
->panel
.fitting_mode
);
893 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
894 intel_connector
->panel
.fitting_mode
);
897 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
900 DRM_DEBUG_KMS("DP link computation with max lane count %i "
901 "max bw %02x pixel clock %iKHz\n",
902 max_lane_count
, bws
[max_clock
],
903 adjusted_mode
->crtc_clock
);
905 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
907 bpp
= pipe_config
->pipe_bpp
;
908 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
909 dev_priv
->vbt
.edp_bpp
< bpp
) {
910 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
911 dev_priv
->vbt
.edp_bpp
);
912 bpp
= dev_priv
->vbt
.edp_bpp
;
915 for (; bpp
>= 6*3; bpp
-= 2*3) {
916 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
919 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
920 for (clock
= 0; clock
<= max_clock
; clock
++) {
921 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
922 link_avail
= intel_dp_max_data_rate(link_clock
,
925 if (mode_rate
<= link_avail
) {
935 if (intel_dp
->color_range_auto
) {
938 * CEA-861-E - 5.1 Default Encoding Parameters
939 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
941 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
942 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
944 intel_dp
->color_range
= 0;
947 if (intel_dp
->color_range
)
948 pipe_config
->limited_color_range
= true;
950 intel_dp
->link_bw
= bws
[clock
];
951 intel_dp
->lane_count
= lane_count
;
952 pipe_config
->pipe_bpp
= bpp
;
953 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
955 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
956 intel_dp
->link_bw
, intel_dp
->lane_count
,
957 pipe_config
->port_clock
, bpp
);
958 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
959 mode_rate
, link_avail
);
961 intel_link_compute_m_n(bpp
, lane_count
,
962 adjusted_mode
->crtc_clock
,
963 pipe_config
->port_clock
,
964 &pipe_config
->dp_m_n
);
966 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
971 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
973 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
974 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
975 struct drm_device
*dev
= crtc
->base
.dev
;
976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
979 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
980 dpa_ctl
= I915_READ(DP_A
);
981 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
983 if (crtc
->config
.port_clock
== 162000) {
984 /* For a long time we've carried around a ILK-DevA w/a for the
985 * 160MHz clock. If we're really unlucky, it's still required.
987 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
988 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
989 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
991 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
992 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
995 I915_WRITE(DP_A
, dpa_ctl
);
1001 static void intel_dp_mode_set(struct intel_encoder
*encoder
)
1003 struct drm_device
*dev
= encoder
->base
.dev
;
1004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1005 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1006 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1007 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1008 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1011 * There are four kinds of DP registers:
1018 * IBX PCH and CPU are the same for almost everything,
1019 * except that the CPU DP PLL is configured in this
1022 * CPT PCH is quite different, having many bits moved
1023 * to the TRANS_DP_CTL register instead. That
1024 * configuration happens (oddly) in ironlake_pch_enable
1027 /* Preserve the BIOS-computed detected bit. This is
1028 * supposed to be read-only.
1030 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1032 /* Handle DP bits in common between all three register formats */
1033 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1034 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1036 if (intel_dp
->has_audio
) {
1037 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1038 pipe_name(crtc
->pipe
));
1039 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1040 intel_write_eld(&encoder
->base
, adjusted_mode
);
1043 /* Split out the IBX/CPU vs CPT settings */
1045 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1046 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1047 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1048 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1049 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1050 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1052 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1053 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1055 intel_dp
->DP
|= crtc
->pipe
<< 29;
1056 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1057 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1058 intel_dp
->DP
|= intel_dp
->color_range
;
1060 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1061 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1062 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1063 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1064 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1066 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1067 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1069 if (crtc
->pipe
== 1)
1070 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1072 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1075 if (port
== PORT_A
&& !IS_VALLEYVIEW(dev
))
1076 ironlake_set_pll_cpu_edp(intel_dp
);
1079 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1080 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1082 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1083 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1085 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1086 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1088 static void wait_panel_status(struct intel_dp
*intel_dp
,
1092 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1094 u32 pp_stat_reg
, pp_ctrl_reg
;
1096 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1097 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1099 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1101 I915_READ(pp_stat_reg
),
1102 I915_READ(pp_ctrl_reg
));
1104 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1105 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1106 I915_READ(pp_stat_reg
),
1107 I915_READ(pp_ctrl_reg
));
1110 DRM_DEBUG_KMS("Wait complete\n");
1113 static void wait_panel_on(struct intel_dp
*intel_dp
)
1115 DRM_DEBUG_KMS("Wait for panel power on\n");
1116 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1119 static void wait_panel_off(struct intel_dp
*intel_dp
)
1121 DRM_DEBUG_KMS("Wait for panel power off time\n");
1122 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1125 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1127 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1129 /* When we disable the VDD override bit last we have to do the manual
1131 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1132 intel_dp
->panel_power_cycle_delay
);
1134 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1137 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1139 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1140 intel_dp
->backlight_on_delay
);
1143 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1145 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1146 intel_dp
->backlight_off_delay
);
1149 /* Read the current pp_control value, unlocking the register if it
1153 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1155 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1159 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1160 control
&= ~PANEL_UNLOCK_MASK
;
1161 control
|= PANEL_UNLOCK_REGS
;
1165 static void edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1167 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1170 u32 pp_stat_reg
, pp_ctrl_reg
;
1172 if (!is_edp(intel_dp
))
1175 WARN(intel_dp
->want_panel_vdd
,
1176 "eDP VDD already requested on\n");
1178 intel_dp
->want_panel_vdd
= true;
1180 if (edp_have_panel_vdd(intel_dp
))
1183 intel_runtime_pm_get(dev_priv
);
1185 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1187 if (!edp_have_panel_power(intel_dp
))
1188 wait_panel_power_cycle(intel_dp
);
1190 pp
= ironlake_get_pp_control(intel_dp
);
1191 pp
|= EDP_FORCE_VDD
;
1193 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1194 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1196 I915_WRITE(pp_ctrl_reg
, pp
);
1197 POSTING_READ(pp_ctrl_reg
);
1198 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1199 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1201 * If the panel wasn't on, delay before accessing aux channel
1203 if (!edp_have_panel_power(intel_dp
)) {
1204 DRM_DEBUG_KMS("eDP was not running\n");
1205 msleep(intel_dp
->panel_power_up_delay
);
1209 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1211 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1214 u32 pp_stat_reg
, pp_ctrl_reg
;
1216 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1218 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1219 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1221 pp
= ironlake_get_pp_control(intel_dp
);
1222 pp
&= ~EDP_FORCE_VDD
;
1224 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1225 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1227 I915_WRITE(pp_ctrl_reg
, pp
);
1228 POSTING_READ(pp_ctrl_reg
);
1230 /* Make sure sequencer is idle before allowing subsequent activity */
1231 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1232 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1234 if ((pp
& POWER_TARGET_ON
) == 0)
1235 intel_dp
->last_power_cycle
= jiffies
;
1237 intel_runtime_pm_put(dev_priv
);
1241 static void edp_panel_vdd_work(struct work_struct
*__work
)
1243 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1244 struct intel_dp
, panel_vdd_work
);
1245 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1247 mutex_lock(&dev
->mode_config
.mutex
);
1248 edp_panel_vdd_off_sync(intel_dp
);
1249 mutex_unlock(&dev
->mode_config
.mutex
);
1252 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1254 if (!is_edp(intel_dp
))
1257 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1259 intel_dp
->want_panel_vdd
= false;
1262 edp_panel_vdd_off_sync(intel_dp
);
1265 * Queue the timer to fire a long
1266 * time from now (relative to the power down delay)
1267 * to keep the panel power up across a sequence of operations
1269 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1270 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1274 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1276 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1281 if (!is_edp(intel_dp
))
1284 DRM_DEBUG_KMS("Turn eDP power on\n");
1286 if (edp_have_panel_power(intel_dp
)) {
1287 DRM_DEBUG_KMS("eDP power already on\n");
1291 wait_panel_power_cycle(intel_dp
);
1293 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1294 pp
= ironlake_get_pp_control(intel_dp
);
1296 /* ILK workaround: disable reset around power sequence */
1297 pp
&= ~PANEL_POWER_RESET
;
1298 I915_WRITE(pp_ctrl_reg
, pp
);
1299 POSTING_READ(pp_ctrl_reg
);
1302 pp
|= POWER_TARGET_ON
;
1304 pp
|= PANEL_POWER_RESET
;
1306 I915_WRITE(pp_ctrl_reg
, pp
);
1307 POSTING_READ(pp_ctrl_reg
);
1309 wait_panel_on(intel_dp
);
1310 intel_dp
->last_power_on
= jiffies
;
1313 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1314 I915_WRITE(pp_ctrl_reg
, pp
);
1315 POSTING_READ(pp_ctrl_reg
);
1319 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1321 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1326 if (!is_edp(intel_dp
))
1329 DRM_DEBUG_KMS("Turn eDP power off\n");
1331 edp_wait_backlight_off(intel_dp
);
1333 pp
= ironlake_get_pp_control(intel_dp
);
1334 /* We need to switch off panel power _and_ force vdd, for otherwise some
1335 * panels get very unhappy and cease to work. */
1336 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1339 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1341 I915_WRITE(pp_ctrl_reg
, pp
);
1342 POSTING_READ(pp_ctrl_reg
);
1344 intel_dp
->last_power_cycle
= jiffies
;
1345 wait_panel_off(intel_dp
);
1348 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1350 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1351 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1356 if (!is_edp(intel_dp
))
1359 DRM_DEBUG_KMS("\n");
1361 * If we enable the backlight right away following a panel power
1362 * on, we may see slight flicker as the panel syncs with the eDP
1363 * link. So delay a bit to make sure the image is solid before
1364 * allowing it to appear.
1366 wait_backlight_on(intel_dp
);
1367 pp
= ironlake_get_pp_control(intel_dp
);
1368 pp
|= EDP_BLC_ENABLE
;
1370 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1372 I915_WRITE(pp_ctrl_reg
, pp
);
1373 POSTING_READ(pp_ctrl_reg
);
1375 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1378 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1380 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1385 if (!is_edp(intel_dp
))
1388 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1390 DRM_DEBUG_KMS("\n");
1391 pp
= ironlake_get_pp_control(intel_dp
);
1392 pp
&= ~EDP_BLC_ENABLE
;
1394 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1396 I915_WRITE(pp_ctrl_reg
, pp
);
1397 POSTING_READ(pp_ctrl_reg
);
1398 intel_dp
->last_backlight_off
= jiffies
;
1401 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1403 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1404 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1405 struct drm_device
*dev
= crtc
->dev
;
1406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1409 assert_pipe_disabled(dev_priv
,
1410 to_intel_crtc(crtc
)->pipe
);
1412 DRM_DEBUG_KMS("\n");
1413 dpa_ctl
= I915_READ(DP_A
);
1414 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1415 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1417 /* We don't adjust intel_dp->DP while tearing down the link, to
1418 * facilitate link retraining (e.g. after hotplug). Hence clear all
1419 * enable bits here to ensure that we don't enable too much. */
1420 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1421 intel_dp
->DP
|= DP_PLL_ENABLE
;
1422 I915_WRITE(DP_A
, intel_dp
->DP
);
1427 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1429 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1430 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1431 struct drm_device
*dev
= crtc
->dev
;
1432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1435 assert_pipe_disabled(dev_priv
,
1436 to_intel_crtc(crtc
)->pipe
);
1438 dpa_ctl
= I915_READ(DP_A
);
1439 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1440 "dp pll off, should be on\n");
1441 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1443 /* We can't rely on the value tracked for the DP register in
1444 * intel_dp->DP because link_down must not change that (otherwise link
1445 * re-training will fail. */
1446 dpa_ctl
&= ~DP_PLL_ENABLE
;
1447 I915_WRITE(DP_A
, dpa_ctl
);
1452 /* If the sink supports it, try to set the power state appropriately */
1453 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1457 /* Should have a valid DPCD by this point */
1458 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1461 if (mode
!= DRM_MODE_DPMS_ON
) {
1462 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1465 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1468 * When turning on, we need to retry for 1ms to give the sink
1471 for (i
= 0; i
< 3; i
++) {
1472 ret
= intel_dp_aux_native_write_1(intel_dp
,
1482 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1485 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1486 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1487 struct drm_device
*dev
= encoder
->base
.dev
;
1488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 enum intel_display_power_domain power_domain
;
1492 power_domain
= intel_display_port_power_domain(encoder
);
1493 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1496 tmp
= I915_READ(intel_dp
->output_reg
);
1498 if (!(tmp
& DP_PORT_EN
))
1501 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1502 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1503 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1504 *pipe
= PORT_TO_PIPE(tmp
);
1510 switch (intel_dp
->output_reg
) {
1512 trans_sel
= TRANS_DP_PORT_SEL_B
;
1515 trans_sel
= TRANS_DP_PORT_SEL_C
;
1518 trans_sel
= TRANS_DP_PORT_SEL_D
;
1525 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1526 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1532 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1533 intel_dp
->output_reg
);
1539 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1540 struct intel_crtc_config
*pipe_config
)
1542 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1544 struct drm_device
*dev
= encoder
->base
.dev
;
1545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1546 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1547 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1550 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1551 tmp
= I915_READ(intel_dp
->output_reg
);
1552 if (tmp
& DP_SYNC_HS_HIGH
)
1553 flags
|= DRM_MODE_FLAG_PHSYNC
;
1555 flags
|= DRM_MODE_FLAG_NHSYNC
;
1557 if (tmp
& DP_SYNC_VS_HIGH
)
1558 flags
|= DRM_MODE_FLAG_PVSYNC
;
1560 flags
|= DRM_MODE_FLAG_NVSYNC
;
1562 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1563 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1564 flags
|= DRM_MODE_FLAG_PHSYNC
;
1566 flags
|= DRM_MODE_FLAG_NHSYNC
;
1568 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1569 flags
|= DRM_MODE_FLAG_PVSYNC
;
1571 flags
|= DRM_MODE_FLAG_NVSYNC
;
1574 pipe_config
->adjusted_mode
.flags
|= flags
;
1576 pipe_config
->has_dp_encoder
= true;
1578 intel_dp_get_m_n(crtc
, pipe_config
);
1580 if (port
== PORT_A
) {
1581 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1582 pipe_config
->port_clock
= 162000;
1584 pipe_config
->port_clock
= 270000;
1587 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1588 &pipe_config
->dp_m_n
);
1590 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1591 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1593 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1595 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1596 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1598 * This is a big fat ugly hack.
1600 * Some machines in UEFI boot mode provide us a VBT that has 18
1601 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1602 * unknown we fail to light up. Yet the same BIOS boots up with
1603 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1604 * max, not what it tells us to use.
1606 * Note: This will still be broken if the eDP panel is not lit
1607 * up by the BIOS, and thus we can't get the mode at module
1610 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1611 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1612 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1616 static bool is_edp_psr(struct drm_device
*dev
)
1618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1620 return dev_priv
->psr
.sink_support
;
1623 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1630 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1633 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1634 struct edp_vsc_psr
*vsc_psr
)
1636 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1637 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1640 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1641 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1642 uint32_t *data
= (uint32_t *) vsc_psr
;
1645 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1646 the video DIP being updated before program video DIP data buffer
1647 registers for DIP being updated. */
1648 I915_WRITE(ctl_reg
, 0);
1649 POSTING_READ(ctl_reg
);
1651 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1652 if (i
< sizeof(struct edp_vsc_psr
))
1653 I915_WRITE(data_reg
+ i
, *data
++);
1655 I915_WRITE(data_reg
+ i
, 0);
1658 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1659 POSTING_READ(ctl_reg
);
1662 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1664 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1666 struct edp_vsc_psr psr_vsc
;
1668 if (intel_dp
->psr_setup_done
)
1671 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1672 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1673 psr_vsc
.sdp_header
.HB0
= 0;
1674 psr_vsc
.sdp_header
.HB1
= 0x7;
1675 psr_vsc
.sdp_header
.HB2
= 0x2;
1676 psr_vsc
.sdp_header
.HB3
= 0x8;
1677 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1679 /* Avoid continuous PSR exit by masking memup and hpd */
1680 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1681 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1683 intel_dp
->psr_setup_done
= true;
1686 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1688 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1690 uint32_t aux_clock_divider
;
1691 int precharge
= 0x3;
1692 int msg_size
= 5; /* Header(4) + Message(1) */
1694 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1696 /* Enable PSR in sink */
1697 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
)
1698 intel_dp_aux_native_write_1(intel_dp
, DP_PSR_EN_CFG
,
1700 ~DP_PSR_MAIN_LINK_ACTIVE
);
1702 intel_dp_aux_native_write_1(intel_dp
, DP_PSR_EN_CFG
,
1704 DP_PSR_MAIN_LINK_ACTIVE
);
1706 /* Setup AUX registers */
1707 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1708 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1709 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1710 DP_AUX_CH_CTL_TIME_OUT_400us
|
1711 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1712 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1713 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1716 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1718 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1720 uint32_t max_sleep_time
= 0x1f;
1721 uint32_t idle_frames
= 1;
1723 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1725 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
1726 val
|= EDP_PSR_LINK_STANDBY
;
1727 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1728 val
|= EDP_PSR_TP1_TIME_0us
;
1729 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1731 val
|= EDP_PSR_LINK_DISABLE
;
1733 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1734 IS_BROADWELL(dev
) ? 0 : link_entry_time
|
1735 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1736 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1740 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1742 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1743 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1745 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1747 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1748 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
1750 dev_priv
->psr
.source_ok
= false;
1752 if (!HAS_PSR(dev
)) {
1753 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1757 if ((intel_encoder
->type
!= INTEL_OUTPUT_EDP
) ||
1758 (dig_port
->port
!= PORT_A
)) {
1759 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1763 if (!i915
.enable_psr
) {
1764 DRM_DEBUG_KMS("PSR disable by flag\n");
1768 crtc
= dig_port
->base
.base
.crtc
;
1770 DRM_DEBUG_KMS("crtc not active for PSR\n");
1774 intel_crtc
= to_intel_crtc(crtc
);
1775 if (!intel_crtc_active(crtc
)) {
1776 DRM_DEBUG_KMS("crtc not active for PSR\n");
1780 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
1781 if (obj
->tiling_mode
!= I915_TILING_X
||
1782 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1783 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1787 if (I915_READ(SPRCTL(intel_crtc
->pipe
)) & SPRITE_ENABLE
) {
1788 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1792 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1794 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1798 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1799 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1803 dev_priv
->psr
.source_ok
= true;
1807 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1809 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1811 if (!intel_edp_psr_match_conditions(intel_dp
) ||
1812 intel_edp_is_psr_enabled(dev
))
1815 /* Setup PSR once */
1816 intel_edp_psr_setup(intel_dp
);
1818 /* Enable PSR on the panel */
1819 intel_edp_psr_enable_sink(intel_dp
);
1821 /* Enable PSR on the host */
1822 intel_edp_psr_enable_source(intel_dp
);
1825 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1827 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1829 if (intel_edp_psr_match_conditions(intel_dp
) &&
1830 !intel_edp_is_psr_enabled(dev
))
1831 intel_edp_psr_do_enable(intel_dp
);
1834 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1836 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1839 if (!intel_edp_is_psr_enabled(dev
))
1842 I915_WRITE(EDP_PSR_CTL(dev
),
1843 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1845 /* Wait till PSR is idle */
1846 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1847 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1848 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1851 void intel_edp_psr_update(struct drm_device
*dev
)
1853 struct intel_encoder
*encoder
;
1854 struct intel_dp
*intel_dp
= NULL
;
1856 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
)
1857 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
1858 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1860 if (!is_edp_psr(dev
))
1863 if (!intel_edp_psr_match_conditions(intel_dp
))
1864 intel_edp_psr_disable(intel_dp
);
1866 if (!intel_edp_is_psr_enabled(dev
))
1867 intel_edp_psr_do_enable(intel_dp
);
1871 static void intel_disable_dp(struct intel_encoder
*encoder
)
1873 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1874 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1875 struct drm_device
*dev
= encoder
->base
.dev
;
1877 /* Make sure the panel is off before trying to change the mode. But also
1878 * ensure that we have vdd while we switch off the panel. */
1879 edp_panel_vdd_on(intel_dp
);
1880 intel_edp_backlight_off(intel_dp
);
1881 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1882 intel_edp_panel_off(intel_dp
);
1883 edp_panel_vdd_off(intel_dp
, true);
1885 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1886 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1887 intel_dp_link_down(intel_dp
);
1890 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1892 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1893 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1894 struct drm_device
*dev
= encoder
->base
.dev
;
1896 if (port
== PORT_A
|| IS_VALLEYVIEW(dev
)) {
1897 intel_dp_link_down(intel_dp
);
1898 if (!IS_VALLEYVIEW(dev
))
1899 ironlake_edp_pll_off(intel_dp
);
1903 static void intel_enable_dp(struct intel_encoder
*encoder
)
1905 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1906 struct drm_device
*dev
= encoder
->base
.dev
;
1907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1908 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1910 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1913 edp_panel_vdd_on(intel_dp
);
1914 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1915 intel_dp_start_link_train(intel_dp
);
1916 intel_edp_panel_on(intel_dp
);
1917 edp_panel_vdd_off(intel_dp
, true);
1918 intel_dp_complete_link_train(intel_dp
);
1919 intel_dp_stop_link_train(intel_dp
);
1922 static void g4x_enable_dp(struct intel_encoder
*encoder
)
1924 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1926 intel_enable_dp(encoder
);
1927 intel_edp_backlight_on(intel_dp
);
1930 static void vlv_enable_dp(struct intel_encoder
*encoder
)
1932 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1934 intel_edp_backlight_on(intel_dp
);
1937 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
1939 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1940 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1942 if (dport
->port
== PORT_A
)
1943 ironlake_edp_pll_on(intel_dp
);
1946 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
1948 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1949 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1950 struct drm_device
*dev
= encoder
->base
.dev
;
1951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1952 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1953 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1954 int pipe
= intel_crtc
->pipe
;
1955 struct edp_power_seq power_seq
;
1958 mutex_lock(&dev_priv
->dpio_lock
);
1960 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
1967 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
1968 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
1969 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
1971 mutex_unlock(&dev_priv
->dpio_lock
);
1973 if (is_edp(intel_dp
)) {
1974 /* init power sequencer on this pipe and port */
1975 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
1976 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
1980 intel_enable_dp(encoder
);
1982 vlv_wait_port_ready(dev_priv
, dport
);
1985 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
1987 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1988 struct drm_device
*dev
= encoder
->base
.dev
;
1989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1990 struct intel_crtc
*intel_crtc
=
1991 to_intel_crtc(encoder
->base
.crtc
);
1992 enum dpio_channel port
= vlv_dport_to_channel(dport
);
1993 int pipe
= intel_crtc
->pipe
;
1995 /* Program Tx lane resets to default */
1996 mutex_lock(&dev_priv
->dpio_lock
);
1997 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
1998 DPIO_PCS_TX_LANE2_RESET
|
1999 DPIO_PCS_TX_LANE1_RESET
);
2000 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2001 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2002 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2003 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2004 DPIO_PCS_CLK_SOFT_RESET
);
2006 /* Fix up inter-pair skew failure */
2007 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2008 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2009 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2010 mutex_unlock(&dev_priv
->dpio_lock
);
2014 * Native read with retry for link status and receiver capability reads for
2015 * cases where the sink may still be asleep.
2018 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
2019 uint8_t *recv
, int recv_bytes
)
2024 * Sinks are *supposed* to come up within 1ms from an off state,
2025 * but we're also supposed to retry 3 times per the spec.
2027 for (i
= 0; i
< 3; i
++) {
2028 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
2030 if (ret
== recv_bytes
)
2039 * Fetch AUX CH registers 0x202 - 0x207 which contain
2040 * link status information
2043 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2045 return intel_dp_aux_native_read_retry(intel_dp
,
2048 DP_LINK_STATUS_SIZE
);
2052 * These are source-specific values; current Intel hardware supports
2053 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2057 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2059 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2060 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2062 if (IS_VALLEYVIEW(dev
) || IS_BROADWELL(dev
))
2063 return DP_TRAIN_VOLTAGE_SWING_1200
;
2064 else if (IS_GEN7(dev
) && port
== PORT_A
)
2065 return DP_TRAIN_VOLTAGE_SWING_800
;
2066 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2067 return DP_TRAIN_VOLTAGE_SWING_1200
;
2069 return DP_TRAIN_VOLTAGE_SWING_800
;
2073 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2075 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2076 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2078 if (IS_BROADWELL(dev
)) {
2079 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2080 case DP_TRAIN_VOLTAGE_SWING_400
:
2081 case DP_TRAIN_VOLTAGE_SWING_600
:
2082 return DP_TRAIN_PRE_EMPHASIS_6
;
2083 case DP_TRAIN_VOLTAGE_SWING_800
:
2084 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2085 case DP_TRAIN_VOLTAGE_SWING_1200
:
2087 return DP_TRAIN_PRE_EMPHASIS_0
;
2089 } else if (IS_HASWELL(dev
)) {
2090 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2091 case DP_TRAIN_VOLTAGE_SWING_400
:
2092 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2093 case DP_TRAIN_VOLTAGE_SWING_600
:
2094 return DP_TRAIN_PRE_EMPHASIS_6
;
2095 case DP_TRAIN_VOLTAGE_SWING_800
:
2096 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2097 case DP_TRAIN_VOLTAGE_SWING_1200
:
2099 return DP_TRAIN_PRE_EMPHASIS_0
;
2101 } else if (IS_VALLEYVIEW(dev
)) {
2102 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2103 case DP_TRAIN_VOLTAGE_SWING_400
:
2104 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2105 case DP_TRAIN_VOLTAGE_SWING_600
:
2106 return DP_TRAIN_PRE_EMPHASIS_6
;
2107 case DP_TRAIN_VOLTAGE_SWING_800
:
2108 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2109 case DP_TRAIN_VOLTAGE_SWING_1200
:
2111 return DP_TRAIN_PRE_EMPHASIS_0
;
2113 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2114 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2115 case DP_TRAIN_VOLTAGE_SWING_400
:
2116 return DP_TRAIN_PRE_EMPHASIS_6
;
2117 case DP_TRAIN_VOLTAGE_SWING_600
:
2118 case DP_TRAIN_VOLTAGE_SWING_800
:
2119 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2121 return DP_TRAIN_PRE_EMPHASIS_0
;
2124 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2125 case DP_TRAIN_VOLTAGE_SWING_400
:
2126 return DP_TRAIN_PRE_EMPHASIS_6
;
2127 case DP_TRAIN_VOLTAGE_SWING_600
:
2128 return DP_TRAIN_PRE_EMPHASIS_6
;
2129 case DP_TRAIN_VOLTAGE_SWING_800
:
2130 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2131 case DP_TRAIN_VOLTAGE_SWING_1200
:
2133 return DP_TRAIN_PRE_EMPHASIS_0
;
2138 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2140 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2142 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2143 struct intel_crtc
*intel_crtc
=
2144 to_intel_crtc(dport
->base
.base
.crtc
);
2145 unsigned long demph_reg_value
, preemph_reg_value
,
2146 uniqtranscale_reg_value
;
2147 uint8_t train_set
= intel_dp
->train_set
[0];
2148 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2149 int pipe
= intel_crtc
->pipe
;
2151 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2152 case DP_TRAIN_PRE_EMPHASIS_0
:
2153 preemph_reg_value
= 0x0004000;
2154 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2155 case DP_TRAIN_VOLTAGE_SWING_400
:
2156 demph_reg_value
= 0x2B405555;
2157 uniqtranscale_reg_value
= 0x552AB83A;
2159 case DP_TRAIN_VOLTAGE_SWING_600
:
2160 demph_reg_value
= 0x2B404040;
2161 uniqtranscale_reg_value
= 0x5548B83A;
2163 case DP_TRAIN_VOLTAGE_SWING_800
:
2164 demph_reg_value
= 0x2B245555;
2165 uniqtranscale_reg_value
= 0x5560B83A;
2167 case DP_TRAIN_VOLTAGE_SWING_1200
:
2168 demph_reg_value
= 0x2B405555;
2169 uniqtranscale_reg_value
= 0x5598DA3A;
2175 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2176 preemph_reg_value
= 0x0002000;
2177 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2178 case DP_TRAIN_VOLTAGE_SWING_400
:
2179 demph_reg_value
= 0x2B404040;
2180 uniqtranscale_reg_value
= 0x5552B83A;
2182 case DP_TRAIN_VOLTAGE_SWING_600
:
2183 demph_reg_value
= 0x2B404848;
2184 uniqtranscale_reg_value
= 0x5580B83A;
2186 case DP_TRAIN_VOLTAGE_SWING_800
:
2187 demph_reg_value
= 0x2B404040;
2188 uniqtranscale_reg_value
= 0x55ADDA3A;
2194 case DP_TRAIN_PRE_EMPHASIS_6
:
2195 preemph_reg_value
= 0x0000000;
2196 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2197 case DP_TRAIN_VOLTAGE_SWING_400
:
2198 demph_reg_value
= 0x2B305555;
2199 uniqtranscale_reg_value
= 0x5570B83A;
2201 case DP_TRAIN_VOLTAGE_SWING_600
:
2202 demph_reg_value
= 0x2B2B4040;
2203 uniqtranscale_reg_value
= 0x55ADDA3A;
2209 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2210 preemph_reg_value
= 0x0006000;
2211 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2212 case DP_TRAIN_VOLTAGE_SWING_400
:
2213 demph_reg_value
= 0x1B405555;
2214 uniqtranscale_reg_value
= 0x55ADDA3A;
2224 mutex_lock(&dev_priv
->dpio_lock
);
2225 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2226 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2227 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2228 uniqtranscale_reg_value
);
2229 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2230 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2231 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2232 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2233 mutex_unlock(&dev_priv
->dpio_lock
);
2239 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2240 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2245 uint8_t voltage_max
;
2246 uint8_t preemph_max
;
2248 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2249 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2250 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2258 voltage_max
= intel_dp_voltage_max(intel_dp
);
2259 if (v
>= voltage_max
)
2260 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2262 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2263 if (p
>= preemph_max
)
2264 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2266 for (lane
= 0; lane
< 4; lane
++)
2267 intel_dp
->train_set
[lane
] = v
| p
;
2271 intel_gen4_signal_levels(uint8_t train_set
)
2273 uint32_t signal_levels
= 0;
2275 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2276 case DP_TRAIN_VOLTAGE_SWING_400
:
2278 signal_levels
|= DP_VOLTAGE_0_4
;
2280 case DP_TRAIN_VOLTAGE_SWING_600
:
2281 signal_levels
|= DP_VOLTAGE_0_6
;
2283 case DP_TRAIN_VOLTAGE_SWING_800
:
2284 signal_levels
|= DP_VOLTAGE_0_8
;
2286 case DP_TRAIN_VOLTAGE_SWING_1200
:
2287 signal_levels
|= DP_VOLTAGE_1_2
;
2290 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2291 case DP_TRAIN_PRE_EMPHASIS_0
:
2293 signal_levels
|= DP_PRE_EMPHASIS_0
;
2295 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2296 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2298 case DP_TRAIN_PRE_EMPHASIS_6
:
2299 signal_levels
|= DP_PRE_EMPHASIS_6
;
2301 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2302 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2305 return signal_levels
;
2308 /* Gen6's DP voltage swing and pre-emphasis control */
2310 intel_gen6_edp_signal_levels(uint8_t train_set
)
2312 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2313 DP_TRAIN_PRE_EMPHASIS_MASK
);
2314 switch (signal_levels
) {
2315 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2316 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2317 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2318 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2319 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2320 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2321 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2322 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2323 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2324 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2325 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2326 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2327 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2328 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2330 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2331 "0x%x\n", signal_levels
);
2332 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2336 /* Gen7's DP voltage swing and pre-emphasis control */
2338 intel_gen7_edp_signal_levels(uint8_t train_set
)
2340 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2341 DP_TRAIN_PRE_EMPHASIS_MASK
);
2342 switch (signal_levels
) {
2343 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2344 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2345 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2346 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2347 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2348 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2350 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2351 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2352 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2353 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2355 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2356 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2357 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2358 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2361 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2362 "0x%x\n", signal_levels
);
2363 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2367 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2369 intel_hsw_signal_levels(uint8_t train_set
)
2371 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2372 DP_TRAIN_PRE_EMPHASIS_MASK
);
2373 switch (signal_levels
) {
2374 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2375 return DDI_BUF_EMP_400MV_0DB_HSW
;
2376 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2377 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2378 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2379 return DDI_BUF_EMP_400MV_6DB_HSW
;
2380 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2381 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2383 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2384 return DDI_BUF_EMP_600MV_0DB_HSW
;
2385 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2386 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2387 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2388 return DDI_BUF_EMP_600MV_6DB_HSW
;
2390 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2391 return DDI_BUF_EMP_800MV_0DB_HSW
;
2392 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2393 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2395 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2396 "0x%x\n", signal_levels
);
2397 return DDI_BUF_EMP_400MV_0DB_HSW
;
2402 intel_bdw_signal_levels(uint8_t train_set
)
2404 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2405 DP_TRAIN_PRE_EMPHASIS_MASK
);
2406 switch (signal_levels
) {
2407 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2408 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2409 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2410 return DDI_BUF_EMP_400MV_3_5DB_BDW
; /* Sel1 */
2411 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2412 return DDI_BUF_EMP_400MV_6DB_BDW
; /* Sel2 */
2414 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2415 return DDI_BUF_EMP_600MV_0DB_BDW
; /* Sel3 */
2416 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2417 return DDI_BUF_EMP_600MV_3_5DB_BDW
; /* Sel4 */
2418 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2419 return DDI_BUF_EMP_600MV_6DB_BDW
; /* Sel5 */
2421 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2422 return DDI_BUF_EMP_800MV_0DB_BDW
; /* Sel6 */
2423 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2424 return DDI_BUF_EMP_800MV_3_5DB_BDW
; /* Sel7 */
2426 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2427 return DDI_BUF_EMP_1200MV_0DB_BDW
; /* Sel8 */
2430 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2431 "0x%x\n", signal_levels
);
2432 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2436 /* Properly updates "DP" with the correct signal levels. */
2438 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2440 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2441 enum port port
= intel_dig_port
->port
;
2442 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2443 uint32_t signal_levels
, mask
;
2444 uint8_t train_set
= intel_dp
->train_set
[0];
2446 if (IS_BROADWELL(dev
)) {
2447 signal_levels
= intel_bdw_signal_levels(train_set
);
2448 mask
= DDI_BUF_EMP_MASK
;
2449 } else if (IS_HASWELL(dev
)) {
2450 signal_levels
= intel_hsw_signal_levels(train_set
);
2451 mask
= DDI_BUF_EMP_MASK
;
2452 } else if (IS_VALLEYVIEW(dev
)) {
2453 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2455 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2456 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2457 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2458 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2459 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2460 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2462 signal_levels
= intel_gen4_signal_levels(train_set
);
2463 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2466 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2468 *DP
= (*DP
& ~mask
) | signal_levels
;
2472 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2474 uint8_t dp_train_pat
)
2476 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2477 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2479 enum port port
= intel_dig_port
->port
;
2480 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2484 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2486 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2487 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2489 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2491 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2492 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2493 case DP_TRAINING_PATTERN_DISABLE
:
2494 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2497 case DP_TRAINING_PATTERN_1
:
2498 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2500 case DP_TRAINING_PATTERN_2
:
2501 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2503 case DP_TRAINING_PATTERN_3
:
2504 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2507 I915_WRITE(DP_TP_CTL(port
), temp
);
2509 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2510 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2512 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2513 case DP_TRAINING_PATTERN_DISABLE
:
2514 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2516 case DP_TRAINING_PATTERN_1
:
2517 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2519 case DP_TRAINING_PATTERN_2
:
2520 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2522 case DP_TRAINING_PATTERN_3
:
2523 DRM_ERROR("DP training pattern 3 not supported\n");
2524 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2529 *DP
&= ~DP_LINK_TRAIN_MASK
;
2531 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2532 case DP_TRAINING_PATTERN_DISABLE
:
2533 *DP
|= DP_LINK_TRAIN_OFF
;
2535 case DP_TRAINING_PATTERN_1
:
2536 *DP
|= DP_LINK_TRAIN_PAT_1
;
2538 case DP_TRAINING_PATTERN_2
:
2539 *DP
|= DP_LINK_TRAIN_PAT_2
;
2541 case DP_TRAINING_PATTERN_3
:
2542 DRM_ERROR("DP training pattern 3 not supported\n");
2543 *DP
|= DP_LINK_TRAIN_PAT_2
;
2548 I915_WRITE(intel_dp
->output_reg
, *DP
);
2549 POSTING_READ(intel_dp
->output_reg
);
2551 buf
[0] = dp_train_pat
;
2552 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2553 DP_TRAINING_PATTERN_DISABLE
) {
2554 /* don't write DP_TRAINING_LANEx_SET on disable */
2557 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2558 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
2559 len
= intel_dp
->lane_count
+ 1;
2562 ret
= intel_dp_aux_native_write(intel_dp
, DP_TRAINING_PATTERN_SET
,
2569 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2570 uint8_t dp_train_pat
)
2572 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
2573 intel_dp_set_signal_levels(intel_dp
, DP
);
2574 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
2578 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2579 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2581 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2582 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2586 intel_get_adjust_train(intel_dp
, link_status
);
2587 intel_dp_set_signal_levels(intel_dp
, DP
);
2589 I915_WRITE(intel_dp
->output_reg
, *DP
);
2590 POSTING_READ(intel_dp
->output_reg
);
2592 ret
= intel_dp_aux_native_write(intel_dp
, DP_TRAINING_LANE0_SET
,
2593 intel_dp
->train_set
,
2594 intel_dp
->lane_count
);
2596 return ret
== intel_dp
->lane_count
;
2599 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
2601 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2602 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2604 enum port port
= intel_dig_port
->port
;
2610 val
= I915_READ(DP_TP_CTL(port
));
2611 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2612 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2613 I915_WRITE(DP_TP_CTL(port
), val
);
2616 * On PORT_A we can have only eDP in SST mode. There the only reason
2617 * we need to set idle transmission mode is to work around a HW issue
2618 * where we enable the pipe while not in idle link-training mode.
2619 * In this case there is requirement to wait for a minimum number of
2620 * idle patterns to be sent.
2625 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2627 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2630 /* Enable corresponding port and start training pattern 1 */
2632 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2634 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2635 struct drm_device
*dev
= encoder
->dev
;
2638 int voltage_tries
, loop_tries
;
2639 uint32_t DP
= intel_dp
->DP
;
2640 uint8_t link_config
[2];
2643 intel_ddi_prepare_link_retrain(encoder
);
2645 /* Write the link configuration data */
2646 link_config
[0] = intel_dp
->link_bw
;
2647 link_config
[1] = intel_dp
->lane_count
;
2648 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2649 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
2650 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
, link_config
, 2);
2653 link_config
[1] = DP_SET_ANSI_8B10B
;
2654 intel_dp_aux_native_write(intel_dp
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
2658 /* clock recovery */
2659 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
2660 DP_TRAINING_PATTERN_1
|
2661 DP_LINK_SCRAMBLING_DISABLE
)) {
2662 DRM_ERROR("failed to enable link training\n");
2670 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2672 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2673 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2674 DRM_ERROR("failed to get link status\n");
2678 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2679 DRM_DEBUG_KMS("clock recovery OK\n");
2683 /* Check to see if we've tried the max voltage */
2684 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2685 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2687 if (i
== intel_dp
->lane_count
) {
2689 if (loop_tries
== 5) {
2690 DRM_ERROR("too many full retries, give up\n");
2693 intel_dp_reset_link_train(intel_dp
, &DP
,
2694 DP_TRAINING_PATTERN_1
|
2695 DP_LINK_SCRAMBLING_DISABLE
);
2700 /* Check to see if we've tried the same voltage 5 times */
2701 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
2703 if (voltage_tries
== 5) {
2704 DRM_ERROR("too many voltage retries, give up\n");
2709 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
2711 /* Update training set as requested by target */
2712 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2713 DRM_ERROR("failed to update link training\n");
2722 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
2724 bool channel_eq
= false;
2725 int tries
, cr_tries
;
2726 uint32_t DP
= intel_dp
->DP
;
2727 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
2729 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2730 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
2731 training_pattern
= DP_TRAINING_PATTERN_3
;
2733 /* channel equalization */
2734 if (!intel_dp_set_link_train(intel_dp
, &DP
,
2736 DP_LINK_SCRAMBLING_DISABLE
)) {
2737 DRM_ERROR("failed to start channel equalization\n");
2745 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2748 DRM_ERROR("failed to train DP, aborting\n");
2752 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
2753 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2754 DRM_ERROR("failed to get link status\n");
2758 /* Make sure clock is still ok */
2759 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2760 intel_dp_start_link_train(intel_dp
);
2761 intel_dp_set_link_train(intel_dp
, &DP
,
2763 DP_LINK_SCRAMBLING_DISABLE
);
2768 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2773 /* Try 5 times, then try clock recovery if that fails */
2775 intel_dp_link_down(intel_dp
);
2776 intel_dp_start_link_train(intel_dp
);
2777 intel_dp_set_link_train(intel_dp
, &DP
,
2779 DP_LINK_SCRAMBLING_DISABLE
);
2785 /* Update training set as requested by target */
2786 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
2787 DRM_ERROR("failed to update link training\n");
2793 intel_dp_set_idle_link_train(intel_dp
);
2798 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2802 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
2804 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2805 DP_TRAINING_PATTERN_DISABLE
);
2809 intel_dp_link_down(struct intel_dp
*intel_dp
)
2811 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2812 enum port port
= intel_dig_port
->port
;
2813 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2815 struct intel_crtc
*intel_crtc
=
2816 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2817 uint32_t DP
= intel_dp
->DP
;
2820 * DDI code has a strict mode set sequence and we should try to respect
2821 * it, otherwise we might hang the machine in many different ways. So we
2822 * really should be disabling the port only on a complete crtc_disable
2823 * sequence. This function is just called under two conditions on DDI
2825 * - Link train failed while doing crtc_enable, and on this case we
2826 * really should respect the mode set sequence and wait for a
2828 * - Someone turned the monitor off and intel_dp_check_link_status
2829 * called us. We don't need to disable the whole port on this case, so
2830 * when someone turns the monitor on again,
2831 * intel_ddi_prepare_link_retrain will take care of redoing the link
2837 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2840 DRM_DEBUG_KMS("\n");
2842 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2843 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2844 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2846 DP
&= ~DP_LINK_TRAIN_MASK
;
2847 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2849 POSTING_READ(intel_dp
->output_reg
);
2851 /* We don't really know why we're doing this */
2852 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2854 if (HAS_PCH_IBX(dev
) &&
2855 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2856 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2858 /* Hardware workaround: leaving our transcoder select
2859 * set to transcoder B while it's off will prevent the
2860 * corresponding HDMI output on transcoder A.
2862 * Combine this with another hardware workaround:
2863 * transcoder select bit can only be cleared while the
2866 DP
&= ~DP_PIPEB_SELECT
;
2867 I915_WRITE(intel_dp
->output_reg
, DP
);
2869 /* Changes to enable or select take place the vblank
2870 * after being written.
2872 if (WARN_ON(crtc
== NULL
)) {
2873 /* We should never try to disable a port without a crtc
2874 * attached. For paranoia keep the code around for a
2876 POSTING_READ(intel_dp
->output_reg
);
2879 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2882 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2883 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2884 POSTING_READ(intel_dp
->output_reg
);
2885 msleep(intel_dp
->panel_power_down_delay
);
2889 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2891 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2892 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2895 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2897 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2898 sizeof(intel_dp
->dpcd
)) == 0)
2899 return false; /* aux transfer failed */
2901 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2902 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2903 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2905 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2906 return false; /* DPCD not present */
2908 /* Check if the panel supports PSR */
2909 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
2910 if (is_edp(intel_dp
)) {
2911 intel_dp_aux_native_read_retry(intel_dp
, DP_PSR_SUPPORT
,
2913 sizeof(intel_dp
->psr_dpcd
));
2914 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
2915 dev_priv
->psr
.sink_support
= true;
2916 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2920 /* Training Pattern 3 support */
2921 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
2922 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
2923 intel_dp
->use_tps3
= true;
2924 DRM_DEBUG_KMS("Displayport TPS3 supported");
2926 intel_dp
->use_tps3
= false;
2928 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2929 DP_DWN_STRM_PORT_PRESENT
))
2930 return true; /* native DP sink */
2932 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2933 return true; /* no per-port downstream info */
2935 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2936 intel_dp
->downstream_ports
,
2937 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2938 return false; /* downstream port status fetch failed */
2944 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2948 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2951 edp_panel_vdd_on(intel_dp
);
2953 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2954 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2955 buf
[0], buf
[1], buf
[2]);
2957 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2958 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2959 buf
[0], buf
[1], buf
[2]);
2961 edp_panel_vdd_off(intel_dp
, false);
2964 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
2966 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2967 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2968 struct intel_crtc
*intel_crtc
=
2969 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2972 if (!intel_dp_aux_native_read(intel_dp
, DP_TEST_SINK_MISC
, buf
, 1))
2975 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
2978 if (!intel_dp_aux_native_write_1(intel_dp
, DP_TEST_SINK
,
2979 DP_TEST_SINK_START
))
2982 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2983 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2984 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2986 if (!intel_dp_aux_native_read(intel_dp
, DP_TEST_CRC_R_CR
, crc
, 6))
2989 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_SINK
, 0);
2994 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2998 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2999 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3000 sink_irq_vector
, 1);
3008 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3010 /* NAK by default */
3011 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3015 * According to DP spec
3018 * 2. Configure link according to Receiver Capabilities
3019 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3020 * 4. Check link status on receipt of hot-plug interrupt
3024 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3026 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3028 u8 link_status
[DP_LINK_STATUS_SIZE
];
3030 if (!intel_encoder
->connectors_active
)
3033 if (WARN_ON(!intel_encoder
->base
.crtc
))
3036 /* Try to read receiver status if the link appears to be up */
3037 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3041 /* Now read the DPCD to see if it's actually running */
3042 if (!intel_dp_get_dpcd(intel_dp
)) {
3046 /* Try to read the source of the interrupt */
3047 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3048 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3049 /* Clear interrupt source */
3050 intel_dp_aux_native_write_1(intel_dp
,
3051 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3054 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3055 intel_dp_handle_test_request(intel_dp
);
3056 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3057 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3060 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3061 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3062 drm_get_encoder_name(&intel_encoder
->base
));
3063 intel_dp_start_link_train(intel_dp
);
3064 intel_dp_complete_link_train(intel_dp
);
3065 intel_dp_stop_link_train(intel_dp
);
3069 /* XXX this is probably wrong for multiple downstream ports */
3070 static enum drm_connector_status
3071 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3073 uint8_t *dpcd
= intel_dp
->dpcd
;
3076 if (!intel_dp_get_dpcd(intel_dp
))
3077 return connector_status_disconnected
;
3079 /* if there's no downstream port, we're done */
3080 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3081 return connector_status_connected
;
3083 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3084 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3085 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3087 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
3089 return connector_status_unknown
;
3090 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3091 : connector_status_disconnected
;
3094 /* If no HPD, poke DDC gently */
3095 if (drm_probe_ddc(&intel_dp
->adapter
))
3096 return connector_status_connected
;
3098 /* Well we tried, say unknown for unreliable port types */
3099 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3100 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3101 if (type
== DP_DS_PORT_TYPE_VGA
||
3102 type
== DP_DS_PORT_TYPE_NON_EDID
)
3103 return connector_status_unknown
;
3105 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3106 DP_DWN_STRM_PORT_TYPE_MASK
;
3107 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3108 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3109 return connector_status_unknown
;
3112 /* Anything else is out of spec, warn and ignore */
3113 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3114 return connector_status_disconnected
;
3117 static enum drm_connector_status
3118 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3120 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3122 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3123 enum drm_connector_status status
;
3125 /* Can't disconnect eDP, but you can close the lid... */
3126 if (is_edp(intel_dp
)) {
3127 status
= intel_panel_detect(dev
);
3128 if (status
== connector_status_unknown
)
3129 status
= connector_status_connected
;
3133 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3134 return connector_status_disconnected
;
3136 return intel_dp_detect_dpcd(intel_dp
);
3139 static enum drm_connector_status
3140 g4x_dp_detect(struct intel_dp
*intel_dp
)
3142 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3144 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3147 /* Can't disconnect eDP, but you can close the lid... */
3148 if (is_edp(intel_dp
)) {
3149 enum drm_connector_status status
;
3151 status
= intel_panel_detect(dev
);
3152 if (status
== connector_status_unknown
)
3153 status
= connector_status_connected
;
3157 if (IS_VALLEYVIEW(dev
)) {
3158 switch (intel_dig_port
->port
) {
3160 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3163 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3166 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3169 return connector_status_unknown
;
3172 switch (intel_dig_port
->port
) {
3174 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3177 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3180 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3183 return connector_status_unknown
;
3187 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3188 return connector_status_disconnected
;
3190 return intel_dp_detect_dpcd(intel_dp
);
3193 static struct edid
*
3194 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3196 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3198 /* use cached edid if we have one */
3199 if (intel_connector
->edid
) {
3201 if (IS_ERR(intel_connector
->edid
))
3204 return drm_edid_duplicate(intel_connector
->edid
);
3207 return drm_get_edid(connector
, adapter
);
3211 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3213 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3215 /* use cached edid if we have one */
3216 if (intel_connector
->edid
) {
3218 if (IS_ERR(intel_connector
->edid
))
3221 return intel_connector_update_modes(connector
,
3222 intel_connector
->edid
);
3225 return intel_ddc_get_modes(connector
, adapter
);
3228 static enum drm_connector_status
3229 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3231 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3232 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3233 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3234 struct drm_device
*dev
= connector
->dev
;
3235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3236 enum drm_connector_status status
;
3237 enum intel_display_power_domain power_domain
;
3238 struct edid
*edid
= NULL
;
3240 intel_runtime_pm_get(dev_priv
);
3242 power_domain
= intel_display_port_power_domain(intel_encoder
);
3243 intel_display_power_get(dev_priv
, power_domain
);
3245 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3246 connector
->base
.id
, drm_get_connector_name(connector
));
3248 intel_dp
->has_audio
= false;
3250 if (HAS_PCH_SPLIT(dev
))
3251 status
= ironlake_dp_detect(intel_dp
);
3253 status
= g4x_dp_detect(intel_dp
);
3255 if (status
!= connector_status_connected
)
3258 intel_dp_probe_oui(intel_dp
);
3260 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3261 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3263 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
3265 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3270 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3271 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3272 status
= connector_status_connected
;
3275 intel_display_power_put(dev_priv
, power_domain
);
3277 intel_runtime_pm_put(dev_priv
);
3282 static int intel_dp_get_modes(struct drm_connector
*connector
)
3284 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3285 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3286 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3287 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3288 struct drm_device
*dev
= connector
->dev
;
3289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3290 enum intel_display_power_domain power_domain
;
3293 /* We should parse the EDID data and find out if it has an audio sink
3296 power_domain
= intel_display_port_power_domain(intel_encoder
);
3297 intel_display_power_get(dev_priv
, power_domain
);
3299 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
3300 intel_display_power_put(dev_priv
, power_domain
);
3304 /* if eDP has no EDID, fall back to fixed mode */
3305 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3306 struct drm_display_mode
*mode
;
3307 mode
= drm_mode_duplicate(dev
,
3308 intel_connector
->panel
.fixed_mode
);
3310 drm_mode_probed_add(connector
, mode
);
3318 intel_dp_detect_audio(struct drm_connector
*connector
)
3320 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3321 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3322 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3323 struct drm_device
*dev
= connector
->dev
;
3324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3325 enum intel_display_power_domain power_domain
;
3327 bool has_audio
= false;
3329 power_domain
= intel_display_port_power_domain(intel_encoder
);
3330 intel_display_power_get(dev_priv
, power_domain
);
3332 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
3334 has_audio
= drm_detect_monitor_audio(edid
);
3338 intel_display_power_put(dev_priv
, power_domain
);
3344 intel_dp_set_property(struct drm_connector
*connector
,
3345 struct drm_property
*property
,
3348 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3349 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3350 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3351 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3354 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3358 if (property
== dev_priv
->force_audio_property
) {
3362 if (i
== intel_dp
->force_audio
)
3365 intel_dp
->force_audio
= i
;
3367 if (i
== HDMI_AUDIO_AUTO
)
3368 has_audio
= intel_dp_detect_audio(connector
);
3370 has_audio
= (i
== HDMI_AUDIO_ON
);
3372 if (has_audio
== intel_dp
->has_audio
)
3375 intel_dp
->has_audio
= has_audio
;
3379 if (property
== dev_priv
->broadcast_rgb_property
) {
3380 bool old_auto
= intel_dp
->color_range_auto
;
3381 uint32_t old_range
= intel_dp
->color_range
;
3384 case INTEL_BROADCAST_RGB_AUTO
:
3385 intel_dp
->color_range_auto
= true;
3387 case INTEL_BROADCAST_RGB_FULL
:
3388 intel_dp
->color_range_auto
= false;
3389 intel_dp
->color_range
= 0;
3391 case INTEL_BROADCAST_RGB_LIMITED
:
3392 intel_dp
->color_range_auto
= false;
3393 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3399 if (old_auto
== intel_dp
->color_range_auto
&&
3400 old_range
== intel_dp
->color_range
)
3406 if (is_edp(intel_dp
) &&
3407 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3408 if (val
== DRM_MODE_SCALE_NONE
) {
3409 DRM_DEBUG_KMS("no scaling not supported\n");
3413 if (intel_connector
->panel
.fitting_mode
== val
) {
3414 /* the eDP scaling property is not changed */
3417 intel_connector
->panel
.fitting_mode
= val
;
3425 if (intel_encoder
->base
.crtc
)
3426 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3432 intel_dp_connector_destroy(struct drm_connector
*connector
)
3434 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3436 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3437 kfree(intel_connector
->edid
);
3439 /* Can't call is_edp() since the encoder may have been destroyed
3441 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3442 intel_panel_fini(&intel_connector
->panel
);
3444 drm_connector_cleanup(connector
);
3448 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3450 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3451 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3452 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3454 i2c_del_adapter(&intel_dp
->adapter
);
3455 drm_encoder_cleanup(encoder
);
3456 if (is_edp(intel_dp
)) {
3457 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3458 mutex_lock(&dev
->mode_config
.mutex
);
3459 edp_panel_vdd_off_sync(intel_dp
);
3460 mutex_unlock(&dev
->mode_config
.mutex
);
3462 kfree(intel_dig_port
);
3465 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
3466 .dpms
= intel_connector_dpms
,
3467 .detect
= intel_dp_detect
,
3468 .fill_modes
= drm_helper_probe_single_connector_modes
,
3469 .set_property
= intel_dp_set_property
,
3470 .destroy
= intel_dp_connector_destroy
,
3473 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
3474 .get_modes
= intel_dp_get_modes
,
3475 .mode_valid
= intel_dp_mode_valid
,
3476 .best_encoder
= intel_best_encoder
,
3479 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
3480 .destroy
= intel_dp_encoder_destroy
,
3484 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
3486 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3488 intel_dp_check_link_status(intel_dp
);
3491 /* Return which DP Port should be selected for Transcoder DP control */
3493 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
3495 struct drm_device
*dev
= crtc
->dev
;
3496 struct intel_encoder
*intel_encoder
;
3497 struct intel_dp
*intel_dp
;
3499 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3500 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3502 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
3503 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
3504 return intel_dp
->output_reg
;
3510 /* check the VBT to see whether the eDP is on DP-D port */
3511 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
3513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3514 union child_device_config
*p_child
;
3516 static const short port_mapping
[] = {
3517 [PORT_B
] = PORT_IDPB
,
3518 [PORT_C
] = PORT_IDPC
,
3519 [PORT_D
] = PORT_IDPD
,
3525 if (!dev_priv
->vbt
.child_dev_num
)
3528 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
3529 p_child
= dev_priv
->vbt
.child_dev
+ i
;
3531 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
3532 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
3533 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
3540 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
3542 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3544 intel_attach_force_audio_property(connector
);
3545 intel_attach_broadcast_rgb_property(connector
);
3546 intel_dp
->color_range_auto
= true;
3548 if (is_edp(intel_dp
)) {
3549 drm_mode_create_scaling_mode_property(connector
->dev
);
3550 drm_object_attach_property(
3552 connector
->dev
->mode_config
.scaling_mode_property
,
3553 DRM_MODE_SCALE_ASPECT
);
3554 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
3558 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
3560 intel_dp
->last_power_cycle
= jiffies
;
3561 intel_dp
->last_power_on
= jiffies
;
3562 intel_dp
->last_backlight_off
= jiffies
;
3566 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
3567 struct intel_dp
*intel_dp
,
3568 struct edp_power_seq
*out
)
3570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3571 struct edp_power_seq cur
, vbt
, spec
, final
;
3572 u32 pp_on
, pp_off
, pp_div
, pp
;
3573 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
3575 if (HAS_PCH_SPLIT(dev
)) {
3576 pp_ctrl_reg
= PCH_PP_CONTROL
;
3577 pp_on_reg
= PCH_PP_ON_DELAYS
;
3578 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3579 pp_div_reg
= PCH_PP_DIVISOR
;
3581 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3583 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
3584 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3585 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3586 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3589 /* Workaround: Need to write PP_CONTROL with the unlock key as
3590 * the very first thing. */
3591 pp
= ironlake_get_pp_control(intel_dp
);
3592 I915_WRITE(pp_ctrl_reg
, pp
);
3594 pp_on
= I915_READ(pp_on_reg
);
3595 pp_off
= I915_READ(pp_off_reg
);
3596 pp_div
= I915_READ(pp_div_reg
);
3598 /* Pull timing values out of registers */
3599 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
3600 PANEL_POWER_UP_DELAY_SHIFT
;
3602 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
3603 PANEL_LIGHT_ON_DELAY_SHIFT
;
3605 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
3606 PANEL_LIGHT_OFF_DELAY_SHIFT
;
3608 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
3609 PANEL_POWER_DOWN_DELAY_SHIFT
;
3611 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
3612 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
3614 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3615 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
3617 vbt
= dev_priv
->vbt
.edp_pps
;
3619 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3620 * our hw here, which are all in 100usec. */
3621 spec
.t1_t3
= 210 * 10;
3622 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
3623 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
3624 spec
.t10
= 500 * 10;
3625 /* This one is special and actually in units of 100ms, but zero
3626 * based in the hw (so we need to add 100 ms). But the sw vbt
3627 * table multiplies it with 1000 to make it in units of 100usec,
3629 spec
.t11_t12
= (510 + 100) * 10;
3631 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3632 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
3634 /* Use the max of the register settings and vbt. If both are
3635 * unset, fall back to the spec limits. */
3636 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3638 max(cur.field, vbt.field))
3639 assign_final(t1_t3
);
3643 assign_final(t11_t12
);
3646 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3647 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
3648 intel_dp
->backlight_on_delay
= get_delay(t8
);
3649 intel_dp
->backlight_off_delay
= get_delay(t9
);
3650 intel_dp
->panel_power_down_delay
= get_delay(t10
);
3651 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
3654 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3655 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
3656 intel_dp
->panel_power_cycle_delay
);
3658 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3659 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
3666 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
3667 struct intel_dp
*intel_dp
,
3668 struct edp_power_seq
*seq
)
3670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3671 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
3672 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
3673 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
3675 if (HAS_PCH_SPLIT(dev
)) {
3676 pp_on_reg
= PCH_PP_ON_DELAYS
;
3677 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3678 pp_div_reg
= PCH_PP_DIVISOR
;
3680 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3682 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3683 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3684 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3688 * And finally store the new values in the power sequencer. The
3689 * backlight delays are set to 1 because we do manual waits on them. For
3690 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3691 * we'll end up waiting for the backlight off delay twice: once when we
3692 * do the manual sleep, and once when we disable the panel and wait for
3693 * the PP_STATUS bit to become zero.
3695 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
3696 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
3697 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
3698 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
3699 /* Compute the divisor for the pp clock, simply match the Bspec
3701 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
3702 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
3703 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
3705 /* Haswell doesn't have any port selection bits for the panel
3706 * power sequencer any more. */
3707 if (IS_VALLEYVIEW(dev
)) {
3708 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
3709 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
3711 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
3712 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
3713 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
3714 port_sel
= PANEL_PORT_SELECT_DPA
;
3716 port_sel
= PANEL_PORT_SELECT_DPD
;
3721 I915_WRITE(pp_on_reg
, pp_on
);
3722 I915_WRITE(pp_off_reg
, pp_off
);
3723 I915_WRITE(pp_div_reg
, pp_div
);
3725 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3726 I915_READ(pp_on_reg
),
3727 I915_READ(pp_off_reg
),
3728 I915_READ(pp_div_reg
));
3731 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
3732 struct intel_connector
*intel_connector
,
3733 struct edp_power_seq
*power_seq
)
3735 struct drm_connector
*connector
= &intel_connector
->base
;
3736 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3737 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3739 struct drm_display_mode
*fixed_mode
= NULL
;
3741 struct drm_display_mode
*scan
;
3744 if (!is_edp(intel_dp
))
3747 /* Cache DPCD and EDID for edp. */
3748 edp_panel_vdd_on(intel_dp
);
3749 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
3750 edp_panel_vdd_off(intel_dp
, false);
3753 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
3754 dev_priv
->no_aux_handshake
=
3755 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
3756 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
3758 /* if this fails, presume the device is a ghost */
3759 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3763 /* We now know it's not a ghost, init power sequence regs. */
3764 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
3766 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
3768 if (drm_add_edid_modes(connector
, edid
)) {
3769 drm_mode_connector_update_edid_property(connector
,
3771 drm_edid_to_eld(connector
, edid
);
3774 edid
= ERR_PTR(-EINVAL
);
3777 edid
= ERR_PTR(-ENOENT
);
3779 intel_connector
->edid
= edid
;
3781 /* prefer fixed mode from EDID if available */
3782 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
3783 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
3784 fixed_mode
= drm_mode_duplicate(dev
, scan
);
3789 /* fallback to VBT if available for eDP */
3790 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
3791 fixed_mode
= drm_mode_duplicate(dev
,
3792 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
3794 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
3797 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
3798 intel_panel_setup_backlight(connector
);
3804 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
3805 struct intel_connector
*intel_connector
)
3807 struct drm_connector
*connector
= &intel_connector
->base
;
3808 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3809 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3810 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3812 enum port port
= intel_dig_port
->port
;
3813 struct edp_power_seq power_seq
= { 0 };
3814 const char *name
= NULL
;
3817 /* intel_dp vfuncs */
3818 if (IS_VALLEYVIEW(dev
))
3819 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
3820 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3821 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
3822 else if (HAS_PCH_SPLIT(dev
))
3823 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
3825 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
3827 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
3829 /* Preserve the current hw state. */
3830 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
3831 intel_dp
->attached_connector
= intel_connector
;
3833 if (intel_dp_is_edp(dev
, port
))
3834 type
= DRM_MODE_CONNECTOR_eDP
;
3836 type
= DRM_MODE_CONNECTOR_DisplayPort
;
3839 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3840 * for DP the encoder type can be set by the caller to
3841 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3843 if (type
== DRM_MODE_CONNECTOR_eDP
)
3844 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
3846 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3847 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
3850 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
3851 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
3853 connector
->interlace_allowed
= true;
3854 connector
->doublescan_allowed
= 0;
3856 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
3857 edp_panel_vdd_work
);
3859 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3860 drm_sysfs_connector_add(connector
);
3863 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3865 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3866 intel_connector
->unregister
= intel_dp_connector_unregister
;
3868 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
3870 switch (intel_dig_port
->port
) {
3872 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
3875 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
3878 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
3881 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
3888 /* Set up the DDC bus. */
3891 intel_encoder
->hpd_pin
= HPD_PORT_A
;
3895 intel_encoder
->hpd_pin
= HPD_PORT_B
;
3899 intel_encoder
->hpd_pin
= HPD_PORT_C
;
3903 intel_encoder
->hpd_pin
= HPD_PORT_D
;
3910 if (is_edp(intel_dp
)) {
3911 intel_dp_init_panel_power_timestamps(intel_dp
);
3912 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
3915 error
= intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
3916 WARN(error
, "intel_dp_i2c_init failed with error %d for port %c\n",
3917 error
, port_name(port
));
3919 intel_dp
->psr_setup_done
= false;
3921 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
3922 i2c_del_adapter(&intel_dp
->adapter
);
3923 if (is_edp(intel_dp
)) {
3924 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3925 mutex_lock(&dev
->mode_config
.mutex
);
3926 edp_panel_vdd_off_sync(intel_dp
);
3927 mutex_unlock(&dev
->mode_config
.mutex
);
3929 drm_sysfs_connector_remove(connector
);
3930 drm_connector_cleanup(connector
);
3934 intel_dp_add_properties(intel_dp
, connector
);
3936 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3937 * 0xd. Failure to do so will result in spurious interrupts being
3938 * generated on the port when a cable is not attached.
3940 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
3941 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
3942 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
3949 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
3951 struct intel_digital_port
*intel_dig_port
;
3952 struct intel_encoder
*intel_encoder
;
3953 struct drm_encoder
*encoder
;
3954 struct intel_connector
*intel_connector
;
3956 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3957 if (!intel_dig_port
)
3960 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
3961 if (!intel_connector
) {
3962 kfree(intel_dig_port
);
3966 intel_encoder
= &intel_dig_port
->base
;
3967 encoder
= &intel_encoder
->base
;
3969 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
3970 DRM_MODE_ENCODER_TMDS
);
3972 intel_encoder
->compute_config
= intel_dp_compute_config
;
3973 intel_encoder
->mode_set
= intel_dp_mode_set
;
3974 intel_encoder
->disable
= intel_disable_dp
;
3975 intel_encoder
->post_disable
= intel_post_disable_dp
;
3976 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
3977 intel_encoder
->get_config
= intel_dp_get_config
;
3978 if (IS_VALLEYVIEW(dev
)) {
3979 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
3980 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
3981 intel_encoder
->enable
= vlv_enable_dp
;
3983 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
3984 intel_encoder
->enable
= g4x_enable_dp
;
3987 intel_dig_port
->port
= port
;
3988 intel_dig_port
->dp
.output_reg
= output_reg
;
3990 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3991 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
3992 intel_encoder
->cloneable
= 0;
3993 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
3995 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
3996 drm_encoder_cleanup(encoder
);
3997 kfree(intel_dig_port
);
3998 kfree(intel_connector
);