2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp
*intel_dp
)
50 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
52 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp
*intel_dp
)
65 return intel_dp
->is_pch_edp
;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
76 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
79 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
81 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
83 return intel_dig_port
->base
.base
.dev
;
86 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
88 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
98 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
100 struct intel_dp
*intel_dp
;
105 intel_dp
= enc_to_intel_dp(encoder
);
107 return is_pch_edp(intel_dp
);
110 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
113 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
114 int *lane_num
, int *link_bw
)
116 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
118 *lane_num
= intel_dp
->lane_count
;
119 *link_bw
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
123 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
124 struct drm_display_mode
*mode
)
126 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
127 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
129 if (intel_connector
->panel
.fixed_mode
)
130 return intel_connector
->panel
.fixed_mode
->clock
;
136 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
138 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
140 switch (max_link_bw
) {
141 case DP_LINK_BW_1_62
:
145 max_link_bw
= DP_LINK_BW_1_62
;
152 intel_dp_link_clock(uint8_t link_bw
)
154 if (link_bw
== DP_LINK_BW_2_7
)
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
190 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
191 struct drm_display_mode
*mode
,
194 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
195 int max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
196 int max_rate
, mode_rate
;
198 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
199 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
201 if (mode_rate
> max_rate
) {
202 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
203 if (mode_rate
> max_rate
)
208 |= INTEL_MODE_DP_FORCE_6BPC
;
217 intel_dp_mode_valid(struct drm_connector
*connector
,
218 struct drm_display_mode
*mode
)
220 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
221 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
222 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
224 if (is_edp(intel_dp
) && fixed_mode
) {
225 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
228 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
232 if (!intel_dp_adjust_dithering(intel_dp
, mode
, false))
233 return MODE_CLOCK_HIGH
;
235 if (mode
->clock
< 10000)
236 return MODE_CLOCK_LOW
;
238 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
239 return MODE_H_ILLEGAL
;
245 pack_aux(uint8_t *src
, int src_bytes
)
252 for (i
= 0; i
< src_bytes
; i
++)
253 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
258 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
263 for (i
= 0; i
< dst_bytes
; i
++)
264 dst
[i
] = src
>> ((3-i
) * 8);
267 /* hrawclock is 1/4 the FSB frequency */
269 intel_hrawclk(struct drm_device
*dev
)
271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
274 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
275 if (IS_VALLEYVIEW(dev
))
278 clkcfg
= I915_READ(CLKCFG
);
279 switch (clkcfg
& CLKCFG_FSB_MASK
) {
288 case CLKCFG_FSB_1067
:
290 case CLKCFG_FSB_1333
:
292 /* these two are just a guess; one of them might be right */
293 case CLKCFG_FSB_1600
:
294 case CLKCFG_FSB_1600_ALT
:
301 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
303 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
309 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
311 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
314 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
318 intel_dp_check_edp(struct intel_dp
*intel_dp
)
320 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
323 if (!is_edp(intel_dp
))
325 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
326 WARN(1, "eDP powered off while attempting aux channel communication.\n");
327 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
328 I915_READ(PCH_PP_STATUS
),
329 I915_READ(PCH_PP_CONTROL
));
334 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
335 uint8_t *send
, int send_bytes
,
336 uint8_t *recv
, int recv_size
)
338 uint32_t output_reg
= intel_dp
->output_reg
;
339 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
340 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 uint32_t ch_ctl
= output_reg
+ 0x10;
343 uint32_t ch_data
= ch_ctl
+ 4;
347 uint32_t aux_clock_divider
;
350 if (IS_HASWELL(dev
)) {
351 switch (intel_dig_port
->port
) {
353 ch_ctl
= DPA_AUX_CH_CTL
;
354 ch_data
= DPA_AUX_CH_DATA1
;
357 ch_ctl
= PCH_DPB_AUX_CH_CTL
;
358 ch_data
= PCH_DPB_AUX_CH_DATA1
;
361 ch_ctl
= PCH_DPC_AUX_CH_CTL
;
362 ch_data
= PCH_DPC_AUX_CH_DATA1
;
365 ch_ctl
= PCH_DPD_AUX_CH_CTL
;
366 ch_data
= PCH_DPD_AUX_CH_DATA1
;
373 intel_dp_check_edp(intel_dp
);
374 /* The clock divider is based off the hrawclk,
375 * and would like to run at 2MHz. So, take the
376 * hrawclk value and divide by 2 and use that
378 * Note that PCH attached eDP panels should use a 125MHz input
381 if (is_cpu_edp(intel_dp
)) {
383 aux_clock_divider
= intel_ddi_get_cdclk_freq(dev_priv
) >> 1;
384 else if (IS_VALLEYVIEW(dev
))
385 aux_clock_divider
= 100;
386 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
387 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
389 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
390 } else if (HAS_PCH_SPLIT(dev
))
391 aux_clock_divider
= DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
393 aux_clock_divider
= intel_hrawclk(dev
) / 2;
400 /* Try to wait for any previous AUX channel activity */
401 for (try = 0; try < 3; try++) {
402 status
= I915_READ(ch_ctl
);
403 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
409 WARN(1, "dp_aux_ch not started status 0x%08x\n",
414 /* Must try at least 3 times according to DP spec */
415 for (try = 0; try < 5; try++) {
416 /* Load the send data into the aux channel data registers */
417 for (i
= 0; i
< send_bytes
; i
+= 4)
418 I915_WRITE(ch_data
+ i
,
419 pack_aux(send
+ i
, send_bytes
- i
));
421 /* Send the command and wait for it to complete */
423 DP_AUX_CH_CTL_SEND_BUSY
|
424 DP_AUX_CH_CTL_TIME_OUT_400us
|
425 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
426 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
427 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
429 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
430 DP_AUX_CH_CTL_RECEIVE_ERROR
);
432 status
= I915_READ(ch_ctl
);
433 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
438 /* Clear done status and any errors */
442 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
443 DP_AUX_CH_CTL_RECEIVE_ERROR
);
445 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
446 DP_AUX_CH_CTL_RECEIVE_ERROR
))
448 if (status
& DP_AUX_CH_CTL_DONE
)
452 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
453 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
457 /* Check for timeout or receive error.
458 * Timeouts occur when the sink is not connected
460 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
461 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
465 /* Timeouts occur when the device isn't connected, so they're
466 * "normal" -- don't fill the kernel log with these */
467 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
468 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
472 /* Unload any bytes sent back from the other side */
473 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
474 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
475 if (recv_bytes
> recv_size
)
476 recv_bytes
= recv_size
;
478 for (i
= 0; i
< recv_bytes
; i
+= 4)
479 unpack_aux(I915_READ(ch_data
+ i
),
480 recv
+ i
, recv_bytes
- i
);
485 /* Write data to the aux channel in native mode */
487 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
488 uint16_t address
, uint8_t *send
, int send_bytes
)
495 intel_dp_check_edp(intel_dp
);
498 msg
[0] = AUX_NATIVE_WRITE
<< 4;
499 msg
[1] = address
>> 8;
500 msg
[2] = address
& 0xff;
501 msg
[3] = send_bytes
- 1;
502 memcpy(&msg
[4], send
, send_bytes
);
503 msg_bytes
= send_bytes
+ 4;
505 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
508 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
510 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
518 /* Write a single byte to the aux channel in native mode */
520 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
521 uint16_t address
, uint8_t byte
)
523 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
526 /* read bytes from a native aux channel */
528 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
529 uint16_t address
, uint8_t *recv
, int recv_bytes
)
538 intel_dp_check_edp(intel_dp
);
539 msg
[0] = AUX_NATIVE_READ
<< 4;
540 msg
[1] = address
>> 8;
541 msg
[2] = address
& 0xff;
542 msg
[3] = recv_bytes
- 1;
545 reply_bytes
= recv_bytes
+ 1;
548 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
555 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
556 memcpy(recv
, reply
+ 1, ret
- 1);
559 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
567 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
568 uint8_t write_byte
, uint8_t *read_byte
)
570 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
571 struct intel_dp
*intel_dp
= container_of(adapter
,
574 uint16_t address
= algo_data
->address
;
582 intel_dp_check_edp(intel_dp
);
583 /* Set up the command byte */
584 if (mode
& MODE_I2C_READ
)
585 msg
[0] = AUX_I2C_READ
<< 4;
587 msg
[0] = AUX_I2C_WRITE
<< 4;
589 if (!(mode
& MODE_I2C_STOP
))
590 msg
[0] |= AUX_I2C_MOT
<< 4;
592 msg
[1] = address
>> 8;
613 for (retry
= 0; retry
< 5; retry
++) {
614 ret
= intel_dp_aux_ch(intel_dp
,
618 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
622 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
623 case AUX_NATIVE_REPLY_ACK
:
624 /* I2C-over-AUX Reply field is only valid
625 * when paired with AUX ACK.
628 case AUX_NATIVE_REPLY_NACK
:
629 DRM_DEBUG_KMS("aux_ch native nack\n");
631 case AUX_NATIVE_REPLY_DEFER
:
635 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
640 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
641 case AUX_I2C_REPLY_ACK
:
642 if (mode
== MODE_I2C_READ
) {
643 *read_byte
= reply
[1];
645 return reply_bytes
- 1;
646 case AUX_I2C_REPLY_NACK
:
647 DRM_DEBUG_KMS("aux_i2c nack\n");
649 case AUX_I2C_REPLY_DEFER
:
650 DRM_DEBUG_KMS("aux_i2c defer\n");
654 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
659 DRM_ERROR("too many retries, giving up\n");
664 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
665 struct intel_connector
*intel_connector
, const char *name
)
669 DRM_DEBUG_KMS("i2c_init %s\n", name
);
670 intel_dp
->algo
.running
= false;
671 intel_dp
->algo
.address
= 0;
672 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
674 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
675 intel_dp
->adapter
.owner
= THIS_MODULE
;
676 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
677 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
678 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
679 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
680 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
682 ironlake_edp_panel_vdd_on(intel_dp
);
683 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
684 ironlake_edp_panel_vdd_off(intel_dp
, false);
689 intel_dp_mode_fixup(struct drm_encoder
*encoder
,
690 const struct drm_display_mode
*mode
,
691 struct drm_display_mode
*adjusted_mode
)
693 struct drm_device
*dev
= encoder
->dev
;
694 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
695 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
696 int lane_count
, clock
;
697 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
698 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
700 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
702 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
703 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
705 intel_pch_panel_fitting(dev
,
706 intel_connector
->panel
.fitting_mode
,
707 mode
, adjusted_mode
);
710 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
713 DRM_DEBUG_KMS("DP link computation with max lane count %i "
714 "max bw %02x pixel clock %iKHz\n",
715 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
717 if (!intel_dp_adjust_dithering(intel_dp
, adjusted_mode
, true))
720 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
721 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
723 for (clock
= 0; clock
<= max_clock
; clock
++) {
724 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
725 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
727 if (mode_rate
<= link_avail
) {
728 intel_dp
->link_bw
= bws
[clock
];
729 intel_dp
->lane_count
= lane_count
;
730 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
731 DRM_DEBUG_KMS("DP link bw %02x lane "
732 "count %d clock %d bpp %d\n",
733 intel_dp
->link_bw
, intel_dp
->lane_count
,
734 adjusted_mode
->clock
, bpp
);
735 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
736 mode_rate
, link_avail
);
745 struct intel_dp_m_n
{
754 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
756 while (*num
> 0xffffff || *den
> 0xffffff) {
763 intel_dp_compute_m_n(int bpp
,
767 struct intel_dp_m_n
*m_n
)
770 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
771 m_n
->gmch_n
= link_clock
* nlanes
;
772 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
773 m_n
->link_m
= pixel_clock
;
774 m_n
->link_n
= link_clock
;
775 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
779 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
780 struct drm_display_mode
*adjusted_mode
)
782 struct drm_device
*dev
= crtc
->dev
;
783 struct intel_encoder
*intel_encoder
;
784 struct intel_dp
*intel_dp
;
785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
786 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
788 struct intel_dp_m_n m_n
;
789 int pipe
= intel_crtc
->pipe
;
790 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
793 * Find the lane count in the intel_encoder private
795 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
796 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
798 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
799 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
801 lane_count
= intel_dp
->lane_count
;
807 * Compute the GMCH and Link ratios. The '3' here is
808 * the number of bytes_per_pixel post-LUT, which we always
809 * set up for 8-bits of R/G/B, or 3 bytes total.
811 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
812 mode
->clock
, adjusted_mode
->clock
, &m_n
);
814 if (IS_HASWELL(dev
)) {
815 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
),
816 TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
817 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
818 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
819 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
820 } else if (HAS_PCH_SPLIT(dev
)) {
821 I915_WRITE(TRANSDATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
822 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
823 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
824 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
825 } else if (IS_VALLEYVIEW(dev
)) {
826 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
827 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
828 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
829 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
831 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
832 TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
833 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
834 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
835 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
839 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
841 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
842 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
843 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
844 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
846 * Check for DPCD version > 1.1 and enhanced framing support
848 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
849 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
850 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
855 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
856 struct drm_display_mode
*adjusted_mode
)
858 struct drm_device
*dev
= encoder
->dev
;
859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
860 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
861 struct drm_crtc
*crtc
= encoder
->crtc
;
862 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
865 * There are four kinds of DP registers:
872 * IBX PCH and CPU are the same for almost everything,
873 * except that the CPU DP PLL is configured in this
876 * CPT PCH is quite different, having many bits moved
877 * to the TRANS_DP_CTL register instead. That
878 * configuration happens (oddly) in ironlake_pch_enable
881 /* Preserve the BIOS-computed detected bit. This is
882 * supposed to be read-only.
884 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
886 /* Handle DP bits in common between all three register formats */
887 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
889 switch (intel_dp
->lane_count
) {
891 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
894 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
897 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
900 if (intel_dp
->has_audio
) {
901 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
902 pipe_name(intel_crtc
->pipe
));
903 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
904 intel_write_eld(encoder
, adjusted_mode
);
907 intel_dp_init_link_config(intel_dp
);
909 /* Split out the IBX/CPU vs CPT settings */
911 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
912 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
913 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
914 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
915 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
916 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
918 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
919 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
921 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
923 /* don't miss out required setting for eDP */
924 if (adjusted_mode
->clock
< 200000)
925 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
927 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
928 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
929 intel_dp
->DP
|= intel_dp
->color_range
;
931 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
932 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
933 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
934 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
935 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
937 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
938 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
940 if (intel_crtc
->pipe
== 1)
941 intel_dp
->DP
|= DP_PIPEB_SELECT
;
943 if (is_cpu_edp(intel_dp
)) {
944 /* don't miss out required setting for eDP */
945 if (adjusted_mode
->clock
< 200000)
946 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
948 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
951 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
955 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
956 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
958 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
959 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
961 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
962 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
964 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
968 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
971 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
973 I915_READ(PCH_PP_STATUS
),
974 I915_READ(PCH_PP_CONTROL
));
976 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
977 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
978 I915_READ(PCH_PP_STATUS
),
979 I915_READ(PCH_PP_CONTROL
));
983 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
985 DRM_DEBUG_KMS("Wait for panel power on\n");
986 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
989 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
991 DRM_DEBUG_KMS("Wait for panel power off time\n");
992 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
995 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
997 DRM_DEBUG_KMS("Wait for panel power cycle\n");
998 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1002 /* Read the current pp_control value, unlocking the register if it
1006 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
1008 u32 control
= I915_READ(PCH_PP_CONTROL
);
1010 control
&= ~PANEL_UNLOCK_MASK
;
1011 control
|= PANEL_UNLOCK_REGS
;
1015 void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1017 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1021 if (!is_edp(intel_dp
))
1023 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1025 WARN(intel_dp
->want_panel_vdd
,
1026 "eDP VDD already requested on\n");
1028 intel_dp
->want_panel_vdd
= true;
1030 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1031 DRM_DEBUG_KMS("eDP VDD already on\n");
1035 if (!ironlake_edp_have_panel_power(intel_dp
))
1036 ironlake_wait_panel_power_cycle(intel_dp
);
1038 pp
= ironlake_get_pp_control(dev_priv
);
1039 pp
|= EDP_FORCE_VDD
;
1040 I915_WRITE(PCH_PP_CONTROL
, pp
);
1041 POSTING_READ(PCH_PP_CONTROL
);
1042 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1043 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1046 * If the panel wasn't on, delay before accessing aux channel
1048 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1049 DRM_DEBUG_KMS("eDP was not running\n");
1050 msleep(intel_dp
->panel_power_up_delay
);
1054 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1056 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1060 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1061 pp
= ironlake_get_pp_control(dev_priv
);
1062 pp
&= ~EDP_FORCE_VDD
;
1063 I915_WRITE(PCH_PP_CONTROL
, pp
);
1064 POSTING_READ(PCH_PP_CONTROL
);
1066 /* Make sure sequencer is idle before allowing subsequent activity */
1067 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1068 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1070 msleep(intel_dp
->panel_power_down_delay
);
1074 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1076 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1077 struct intel_dp
, panel_vdd_work
);
1078 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1080 mutex_lock(&dev
->mode_config
.mutex
);
1081 ironlake_panel_vdd_off_sync(intel_dp
);
1082 mutex_unlock(&dev
->mode_config
.mutex
);
1085 void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1087 if (!is_edp(intel_dp
))
1090 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1091 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1093 intel_dp
->want_panel_vdd
= false;
1096 ironlake_panel_vdd_off_sync(intel_dp
);
1099 * Queue the timer to fire a long
1100 * time from now (relative to the power down delay)
1101 * to keep the panel power up across a sequence of operations
1103 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1104 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1108 void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1110 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1114 if (!is_edp(intel_dp
))
1117 DRM_DEBUG_KMS("Turn eDP power on\n");
1119 if (ironlake_edp_have_panel_power(intel_dp
)) {
1120 DRM_DEBUG_KMS("eDP power already on\n");
1124 ironlake_wait_panel_power_cycle(intel_dp
);
1126 pp
= ironlake_get_pp_control(dev_priv
);
1128 /* ILK workaround: disable reset around power sequence */
1129 pp
&= ~PANEL_POWER_RESET
;
1130 I915_WRITE(PCH_PP_CONTROL
, pp
);
1131 POSTING_READ(PCH_PP_CONTROL
);
1134 pp
|= POWER_TARGET_ON
;
1136 pp
|= PANEL_POWER_RESET
;
1138 I915_WRITE(PCH_PP_CONTROL
, pp
);
1139 POSTING_READ(PCH_PP_CONTROL
);
1141 ironlake_wait_panel_on(intel_dp
);
1144 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1145 I915_WRITE(PCH_PP_CONTROL
, pp
);
1146 POSTING_READ(PCH_PP_CONTROL
);
1150 void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1152 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1156 if (!is_edp(intel_dp
))
1159 DRM_DEBUG_KMS("Turn eDP power off\n");
1161 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1163 pp
= ironlake_get_pp_control(dev_priv
);
1164 /* We need to switch off panel power _and_ force vdd, for otherwise some
1165 * panels get very unhappy and cease to work. */
1166 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1167 I915_WRITE(PCH_PP_CONTROL
, pp
);
1168 POSTING_READ(PCH_PP_CONTROL
);
1170 intel_dp
->want_panel_vdd
= false;
1172 ironlake_wait_panel_off(intel_dp
);
1175 void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1177 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1178 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 int pipe
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
)->pipe
;
1183 if (!is_edp(intel_dp
))
1186 DRM_DEBUG_KMS("\n");
1188 * If we enable the backlight right away following a panel power
1189 * on, we may see slight flicker as the panel syncs with the eDP
1190 * link. So delay a bit to make sure the image is solid before
1191 * allowing it to appear.
1193 msleep(intel_dp
->backlight_on_delay
);
1194 pp
= ironlake_get_pp_control(dev_priv
);
1195 pp
|= EDP_BLC_ENABLE
;
1196 I915_WRITE(PCH_PP_CONTROL
, pp
);
1197 POSTING_READ(PCH_PP_CONTROL
);
1199 intel_panel_enable_backlight(dev
, pipe
);
1202 void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1204 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1208 if (!is_edp(intel_dp
))
1211 intel_panel_disable_backlight(dev
);
1213 DRM_DEBUG_KMS("\n");
1214 pp
= ironlake_get_pp_control(dev_priv
);
1215 pp
&= ~EDP_BLC_ENABLE
;
1216 I915_WRITE(PCH_PP_CONTROL
, pp
);
1217 POSTING_READ(PCH_PP_CONTROL
);
1218 msleep(intel_dp
->backlight_off_delay
);
1221 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1223 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1224 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1225 struct drm_device
*dev
= crtc
->dev
;
1226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1229 assert_pipe_disabled(dev_priv
,
1230 to_intel_crtc(crtc
)->pipe
);
1232 DRM_DEBUG_KMS("\n");
1233 dpa_ctl
= I915_READ(DP_A
);
1234 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1235 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1237 /* We don't adjust intel_dp->DP while tearing down the link, to
1238 * facilitate link retraining (e.g. after hotplug). Hence clear all
1239 * enable bits here to ensure that we don't enable too much. */
1240 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1241 intel_dp
->DP
|= DP_PLL_ENABLE
;
1242 I915_WRITE(DP_A
, intel_dp
->DP
);
1247 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1249 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1250 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1251 struct drm_device
*dev
= crtc
->dev
;
1252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1255 assert_pipe_disabled(dev_priv
,
1256 to_intel_crtc(crtc
)->pipe
);
1258 dpa_ctl
= I915_READ(DP_A
);
1259 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1260 "dp pll off, should be on\n");
1261 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1263 /* We can't rely on the value tracked for the DP register in
1264 * intel_dp->DP because link_down must not change that (otherwise link
1265 * re-training will fail. */
1266 dpa_ctl
&= ~DP_PLL_ENABLE
;
1267 I915_WRITE(DP_A
, dpa_ctl
);
1272 /* If the sink supports it, try to set the power state appropriately */
1273 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1277 /* Should have a valid DPCD by this point */
1278 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1281 if (mode
!= DRM_MODE_DPMS_ON
) {
1282 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1285 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1288 * When turning on, we need to retry for 1ms to give the sink
1291 for (i
= 0; i
< 3; i
++) {
1292 ret
= intel_dp_aux_native_write_1(intel_dp
,
1302 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1305 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1306 struct drm_device
*dev
= encoder
->base
.dev
;
1307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1308 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1310 if (!(tmp
& DP_PORT_EN
))
1313 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
1314 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1315 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1316 *pipe
= PORT_TO_PIPE(tmp
);
1322 switch (intel_dp
->output_reg
) {
1324 trans_sel
= TRANS_DP_PORT_SEL_B
;
1327 trans_sel
= TRANS_DP_PORT_SEL_C
;
1330 trans_sel
= TRANS_DP_PORT_SEL_D
;
1337 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1338 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1344 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1345 intel_dp
->output_reg
);
1351 static void intel_disable_dp(struct intel_encoder
*encoder
)
1353 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1355 /* Make sure the panel is off before trying to change the mode. But also
1356 * ensure that we have vdd while we switch off the panel. */
1357 ironlake_edp_panel_vdd_on(intel_dp
);
1358 ironlake_edp_backlight_off(intel_dp
);
1359 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1360 ironlake_edp_panel_off(intel_dp
);
1362 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1363 if (!is_cpu_edp(intel_dp
))
1364 intel_dp_link_down(intel_dp
);
1367 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1369 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1371 if (is_cpu_edp(intel_dp
)) {
1372 intel_dp_link_down(intel_dp
);
1373 ironlake_edp_pll_off(intel_dp
);
1377 static void intel_enable_dp(struct intel_encoder
*encoder
)
1379 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1380 struct drm_device
*dev
= encoder
->base
.dev
;
1381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1382 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1384 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1387 ironlake_edp_panel_vdd_on(intel_dp
);
1388 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1389 intel_dp_start_link_train(intel_dp
);
1390 ironlake_edp_panel_on(intel_dp
);
1391 ironlake_edp_panel_vdd_off(intel_dp
, true);
1392 intel_dp_complete_link_train(intel_dp
);
1393 ironlake_edp_backlight_on(intel_dp
);
1396 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1398 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1400 if (is_cpu_edp(intel_dp
))
1401 ironlake_edp_pll_on(intel_dp
);
1405 * Native read with retry for link status and receiver capability reads for
1406 * cases where the sink may still be asleep.
1409 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1410 uint8_t *recv
, int recv_bytes
)
1415 * Sinks are *supposed* to come up within 1ms from an off state,
1416 * but we're also supposed to retry 3 times per the spec.
1418 for (i
= 0; i
< 3; i
++) {
1419 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1421 if (ret
== recv_bytes
)
1430 * Fetch AUX CH registers 0x202 - 0x207 which contain
1431 * link status information
1434 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1436 return intel_dp_aux_native_read_retry(intel_dp
,
1439 DP_LINK_STATUS_SIZE
);
1443 static char *voltage_names
[] = {
1444 "0.4V", "0.6V", "0.8V", "1.2V"
1446 static char *pre_emph_names
[] = {
1447 "0dB", "3.5dB", "6dB", "9.5dB"
1449 static char *link_train_names
[] = {
1450 "pattern 1", "pattern 2", "idle", "off"
1455 * These are source-specific values; current Intel hardware supports
1456 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1460 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1462 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1464 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1465 return DP_TRAIN_VOLTAGE_SWING_800
;
1466 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1467 return DP_TRAIN_VOLTAGE_SWING_1200
;
1469 return DP_TRAIN_VOLTAGE_SWING_800
;
1473 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1475 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1477 if (IS_HASWELL(dev
)) {
1478 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1479 case DP_TRAIN_VOLTAGE_SWING_400
:
1480 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1481 case DP_TRAIN_VOLTAGE_SWING_600
:
1482 return DP_TRAIN_PRE_EMPHASIS_6
;
1483 case DP_TRAIN_VOLTAGE_SWING_800
:
1484 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1485 case DP_TRAIN_VOLTAGE_SWING_1200
:
1487 return DP_TRAIN_PRE_EMPHASIS_0
;
1489 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1490 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1491 case DP_TRAIN_VOLTAGE_SWING_400
:
1492 return DP_TRAIN_PRE_EMPHASIS_6
;
1493 case DP_TRAIN_VOLTAGE_SWING_600
:
1494 case DP_TRAIN_VOLTAGE_SWING_800
:
1495 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1497 return DP_TRAIN_PRE_EMPHASIS_0
;
1500 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1501 case DP_TRAIN_VOLTAGE_SWING_400
:
1502 return DP_TRAIN_PRE_EMPHASIS_6
;
1503 case DP_TRAIN_VOLTAGE_SWING_600
:
1504 return DP_TRAIN_PRE_EMPHASIS_6
;
1505 case DP_TRAIN_VOLTAGE_SWING_800
:
1506 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1507 case DP_TRAIN_VOLTAGE_SWING_1200
:
1509 return DP_TRAIN_PRE_EMPHASIS_0
;
1515 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1520 uint8_t voltage_max
;
1521 uint8_t preemph_max
;
1523 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1524 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
1525 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
1533 voltage_max
= intel_dp_voltage_max(intel_dp
);
1534 if (v
>= voltage_max
)
1535 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1537 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1538 if (p
>= preemph_max
)
1539 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1541 for (lane
= 0; lane
< 4; lane
++)
1542 intel_dp
->train_set
[lane
] = v
| p
;
1546 intel_dp_signal_levels(uint8_t train_set
)
1548 uint32_t signal_levels
= 0;
1550 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1551 case DP_TRAIN_VOLTAGE_SWING_400
:
1553 signal_levels
|= DP_VOLTAGE_0_4
;
1555 case DP_TRAIN_VOLTAGE_SWING_600
:
1556 signal_levels
|= DP_VOLTAGE_0_6
;
1558 case DP_TRAIN_VOLTAGE_SWING_800
:
1559 signal_levels
|= DP_VOLTAGE_0_8
;
1561 case DP_TRAIN_VOLTAGE_SWING_1200
:
1562 signal_levels
|= DP_VOLTAGE_1_2
;
1565 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1566 case DP_TRAIN_PRE_EMPHASIS_0
:
1568 signal_levels
|= DP_PRE_EMPHASIS_0
;
1570 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1571 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1573 case DP_TRAIN_PRE_EMPHASIS_6
:
1574 signal_levels
|= DP_PRE_EMPHASIS_6
;
1576 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1577 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1580 return signal_levels
;
1583 /* Gen6's DP voltage swing and pre-emphasis control */
1585 intel_gen6_edp_signal_levels(uint8_t train_set
)
1587 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1588 DP_TRAIN_PRE_EMPHASIS_MASK
);
1589 switch (signal_levels
) {
1590 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1591 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1592 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1593 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1594 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1595 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1596 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1597 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1598 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1599 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1600 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1601 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1602 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1603 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1605 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1606 "0x%x\n", signal_levels
);
1607 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1611 /* Gen7's DP voltage swing and pre-emphasis control */
1613 intel_gen7_edp_signal_levels(uint8_t train_set
)
1615 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1616 DP_TRAIN_PRE_EMPHASIS_MASK
);
1617 switch (signal_levels
) {
1618 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1619 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1620 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1621 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1622 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1623 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1625 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1626 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1627 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1628 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1630 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1631 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1632 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1633 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1636 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1637 "0x%x\n", signal_levels
);
1638 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1642 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1644 intel_dp_signal_levels_hsw(uint8_t train_set
)
1646 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1647 DP_TRAIN_PRE_EMPHASIS_MASK
);
1648 switch (signal_levels
) {
1649 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1650 return DDI_BUF_EMP_400MV_0DB_HSW
;
1651 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1652 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1653 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1654 return DDI_BUF_EMP_400MV_6DB_HSW
;
1655 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1656 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1658 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1659 return DDI_BUF_EMP_600MV_0DB_HSW
;
1660 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1661 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1662 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1663 return DDI_BUF_EMP_600MV_6DB_HSW
;
1665 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1666 return DDI_BUF_EMP_800MV_0DB_HSW
;
1667 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1668 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1670 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1671 "0x%x\n", signal_levels
);
1672 return DDI_BUF_EMP_400MV_0DB_HSW
;
1677 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1678 uint32_t dp_reg_value
,
1679 uint8_t dp_train_pat
)
1681 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1682 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1684 enum port port
= intel_dig_port
->port
;
1688 if (IS_HASWELL(dev
)) {
1689 temp
= I915_READ(DP_TP_CTL(port
));
1691 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1692 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1694 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1696 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1697 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1698 case DP_TRAINING_PATTERN_DISABLE
:
1699 temp
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
1700 I915_WRITE(DP_TP_CTL(port
), temp
);
1702 if (wait_for((I915_READ(DP_TP_STATUS(port
)) &
1703 DP_TP_STATUS_IDLE_DONE
), 1))
1704 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1706 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1707 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1710 case DP_TRAINING_PATTERN_1
:
1711 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1713 case DP_TRAINING_PATTERN_2
:
1714 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1716 case DP_TRAINING_PATTERN_3
:
1717 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1720 I915_WRITE(DP_TP_CTL(port
), temp
);
1722 } else if (HAS_PCH_CPT(dev
) &&
1723 (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1724 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1726 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1727 case DP_TRAINING_PATTERN_DISABLE
:
1728 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1730 case DP_TRAINING_PATTERN_1
:
1731 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1733 case DP_TRAINING_PATTERN_2
:
1734 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1736 case DP_TRAINING_PATTERN_3
:
1737 DRM_ERROR("DP training pattern 3 not supported\n");
1738 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1743 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1745 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1746 case DP_TRAINING_PATTERN_DISABLE
:
1747 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1749 case DP_TRAINING_PATTERN_1
:
1750 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1752 case DP_TRAINING_PATTERN_2
:
1753 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1755 case DP_TRAINING_PATTERN_3
:
1756 DRM_ERROR("DP training pattern 3 not supported\n");
1757 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1762 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1763 POSTING_READ(intel_dp
->output_reg
);
1765 intel_dp_aux_native_write_1(intel_dp
,
1766 DP_TRAINING_PATTERN_SET
,
1769 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1770 DP_TRAINING_PATTERN_DISABLE
) {
1771 ret
= intel_dp_aux_native_write(intel_dp
,
1772 DP_TRAINING_LANE0_SET
,
1773 intel_dp
->train_set
,
1774 intel_dp
->lane_count
);
1775 if (ret
!= intel_dp
->lane_count
)
1782 /* Enable corresponding port and start training pattern 1 */
1784 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1786 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
1787 struct drm_device
*dev
= encoder
->dev
;
1790 bool clock_recovery
= false;
1791 int voltage_tries
, loop_tries
;
1792 uint32_t DP
= intel_dp
->DP
;
1794 if (IS_HASWELL(dev
))
1795 intel_ddi_prepare_link_retrain(encoder
);
1797 /* Write the link configuration data */
1798 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1799 intel_dp
->link_configuration
,
1800 DP_LINK_CONFIGURATION_SIZE
);
1804 memset(intel_dp
->train_set
, 0, 4);
1808 clock_recovery
= false;
1810 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1811 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1812 uint32_t signal_levels
;
1814 if (IS_HASWELL(dev
)) {
1815 signal_levels
= intel_dp_signal_levels_hsw(
1816 intel_dp
->train_set
[0]);
1817 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1818 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1819 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1820 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1821 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1822 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1823 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1825 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1826 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1828 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1831 /* Set training pattern 1 */
1832 if (!intel_dp_set_link_train(intel_dp
, DP
,
1833 DP_TRAINING_PATTERN_1
|
1834 DP_LINK_SCRAMBLING_DISABLE
))
1837 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
1838 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1839 DRM_ERROR("failed to get link status\n");
1843 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1844 DRM_DEBUG_KMS("clock recovery OK\n");
1845 clock_recovery
= true;
1849 /* Check to see if we've tried the max voltage */
1850 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1851 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1853 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1855 if (loop_tries
== 5) {
1856 DRM_DEBUG_KMS("too many full retries, give up\n");
1859 memset(intel_dp
->train_set
, 0, 4);
1864 /* Check to see if we've tried the same voltage 5 times */
1865 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1867 if (voltage_tries
== 5) {
1868 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1873 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1875 /* Compute new intel_dp->train_set as requested by target */
1876 intel_get_adjust_train(intel_dp
, link_status
);
1883 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1885 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1886 bool channel_eq
= false;
1887 int tries
, cr_tries
;
1888 uint32_t DP
= intel_dp
->DP
;
1890 /* channel equalization */
1895 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1896 uint32_t signal_levels
;
1897 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1900 DRM_ERROR("failed to train DP, aborting\n");
1901 intel_dp_link_down(intel_dp
);
1905 if (IS_HASWELL(dev
)) {
1906 signal_levels
= intel_dp_signal_levels_hsw(intel_dp
->train_set
[0]);
1907 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1908 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1909 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1910 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1911 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1912 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1913 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1915 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1916 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1919 /* channel eq pattern */
1920 if (!intel_dp_set_link_train(intel_dp
, DP
,
1921 DP_TRAINING_PATTERN_2
|
1922 DP_LINK_SCRAMBLING_DISABLE
))
1925 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
1926 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1929 /* Make sure clock is still ok */
1930 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1931 intel_dp_start_link_train(intel_dp
);
1936 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
1941 /* Try 5 times, then try clock recovery if that fails */
1943 intel_dp_link_down(intel_dp
);
1944 intel_dp_start_link_train(intel_dp
);
1950 /* Compute new intel_dp->train_set as requested by target */
1951 intel_get_adjust_train(intel_dp
, link_status
);
1956 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1958 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
1962 intel_dp_link_down(struct intel_dp
*intel_dp
)
1964 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1965 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1967 uint32_t DP
= intel_dp
->DP
;
1970 * DDI code has a strict mode set sequence and we should try to respect
1971 * it, otherwise we might hang the machine in many different ways. So we
1972 * really should be disabling the port only on a complete crtc_disable
1973 * sequence. This function is just called under two conditions on DDI
1975 * - Link train failed while doing crtc_enable, and on this case we
1976 * really should respect the mode set sequence and wait for a
1978 * - Someone turned the monitor off and intel_dp_check_link_status
1979 * called us. We don't need to disable the whole port on this case, so
1980 * when someone turns the monitor on again,
1981 * intel_ddi_prepare_link_retrain will take care of redoing the link
1984 if (IS_HASWELL(dev
))
1987 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
1990 DRM_DEBUG_KMS("\n");
1992 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1993 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1994 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1996 DP
&= ~DP_LINK_TRAIN_MASK
;
1997 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1999 POSTING_READ(intel_dp
->output_reg
);
2003 if (HAS_PCH_IBX(dev
) &&
2004 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2005 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2007 /* Hardware workaround: leaving our transcoder select
2008 * set to transcoder B while it's off will prevent the
2009 * corresponding HDMI output on transcoder A.
2011 * Combine this with another hardware workaround:
2012 * transcoder select bit can only be cleared while the
2015 DP
&= ~DP_PIPEB_SELECT
;
2016 I915_WRITE(intel_dp
->output_reg
, DP
);
2018 /* Changes to enable or select take place the vblank
2019 * after being written.
2022 /* We can arrive here never having been attached
2023 * to a CRTC, for instance, due to inheriting
2024 * random state from the BIOS.
2026 * If the pipe is not running, play safe and
2027 * wait for the clocks to stabilise before
2030 POSTING_READ(intel_dp
->output_reg
);
2033 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
2036 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2037 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2038 POSTING_READ(intel_dp
->output_reg
);
2039 msleep(intel_dp
->panel_power_down_delay
);
2043 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2045 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2046 sizeof(intel_dp
->dpcd
)) == 0)
2047 return false; /* aux transfer failed */
2049 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2050 return false; /* DPCD not present */
2052 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2053 DP_DWN_STRM_PORT_PRESENT
))
2054 return true; /* native DP sink */
2056 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2057 return true; /* no per-port downstream info */
2059 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2060 intel_dp
->downstream_ports
,
2061 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2062 return false; /* downstream port status fetch failed */
2068 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2072 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2075 ironlake_edp_panel_vdd_on(intel_dp
);
2077 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2078 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2079 buf
[0], buf
[1], buf
[2]);
2081 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2082 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2083 buf
[0], buf
[1], buf
[2]);
2085 ironlake_edp_panel_vdd_off(intel_dp
, false);
2089 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2093 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2094 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2095 sink_irq_vector
, 1);
2103 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2105 /* NAK by default */
2106 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2110 * According to DP spec
2113 * 2. Configure link according to Receiver Capabilities
2114 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2115 * 4. Check link status on receipt of hot-plug interrupt
2119 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2121 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2123 u8 link_status
[DP_LINK_STATUS_SIZE
];
2125 if (!intel_encoder
->connectors_active
)
2128 if (WARN_ON(!intel_encoder
->base
.crtc
))
2131 /* Try to read receiver status if the link appears to be up */
2132 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2133 intel_dp_link_down(intel_dp
);
2137 /* Now read the DPCD to see if it's actually running */
2138 if (!intel_dp_get_dpcd(intel_dp
)) {
2139 intel_dp_link_down(intel_dp
);
2143 /* Try to read the source of the interrupt */
2144 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2145 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2146 /* Clear interrupt source */
2147 intel_dp_aux_native_write_1(intel_dp
,
2148 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2151 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2152 intel_dp_handle_test_request(intel_dp
);
2153 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2154 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2157 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2158 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2159 drm_get_encoder_name(&intel_encoder
->base
));
2160 intel_dp_start_link_train(intel_dp
);
2161 intel_dp_complete_link_train(intel_dp
);
2165 /* XXX this is probably wrong for multiple downstream ports */
2166 static enum drm_connector_status
2167 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2169 uint8_t *dpcd
= intel_dp
->dpcd
;
2173 if (!intel_dp_get_dpcd(intel_dp
))
2174 return connector_status_disconnected
;
2176 /* if there's no downstream port, we're done */
2177 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2178 return connector_status_connected
;
2180 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2181 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2184 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2186 return connector_status_unknown
;
2187 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2188 : connector_status_disconnected
;
2191 /* If no HPD, poke DDC gently */
2192 if (drm_probe_ddc(&intel_dp
->adapter
))
2193 return connector_status_connected
;
2195 /* Well we tried, say unknown for unreliable port types */
2196 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2197 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2198 return connector_status_unknown
;
2200 /* Anything else is out of spec, warn and ignore */
2201 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2202 return connector_status_disconnected
;
2205 static enum drm_connector_status
2206 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2208 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2209 enum drm_connector_status status
;
2211 /* Can't disconnect eDP, but you can close the lid... */
2212 if (is_edp(intel_dp
)) {
2213 status
= intel_panel_detect(dev
);
2214 if (status
== connector_status_unknown
)
2215 status
= connector_status_connected
;
2219 return intel_dp_detect_dpcd(intel_dp
);
2222 static enum drm_connector_status
2223 g4x_dp_detect(struct intel_dp
*intel_dp
)
2225 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2229 switch (intel_dp
->output_reg
) {
2231 bit
= DPB_HOTPLUG_LIVE_STATUS
;
2234 bit
= DPC_HOTPLUG_LIVE_STATUS
;
2237 bit
= DPD_HOTPLUG_LIVE_STATUS
;
2240 return connector_status_unknown
;
2243 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2244 return connector_status_disconnected
;
2246 return intel_dp_detect_dpcd(intel_dp
);
2249 static struct edid
*
2250 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2252 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2254 /* use cached edid if we have one */
2255 if (intel_connector
->edid
) {
2260 if (IS_ERR(intel_connector
->edid
))
2263 size
= (intel_connector
->edid
->extensions
+ 1) * EDID_LENGTH
;
2264 edid
= kmalloc(size
, GFP_KERNEL
);
2268 memcpy(edid
, intel_connector
->edid
, size
);
2272 return drm_get_edid(connector
, adapter
);
2276 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2278 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2280 /* use cached edid if we have one */
2281 if (intel_connector
->edid
) {
2283 if (IS_ERR(intel_connector
->edid
))
2286 return intel_connector_update_modes(connector
,
2287 intel_connector
->edid
);
2290 return intel_ddc_get_modes(connector
, adapter
);
2295 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2297 * \return true if DP port is connected.
2298 * \return false if DP port is disconnected.
2300 static enum drm_connector_status
2301 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2303 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2304 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2305 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2306 struct drm_device
*dev
= connector
->dev
;
2307 enum drm_connector_status status
;
2308 struct edid
*edid
= NULL
;
2309 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2311 intel_dp
->has_audio
= false;
2313 if (HAS_PCH_SPLIT(dev
))
2314 status
= ironlake_dp_detect(intel_dp
);
2316 status
= g4x_dp_detect(intel_dp
);
2318 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2319 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2320 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2322 if (status
!= connector_status_connected
)
2325 intel_dp_probe_oui(intel_dp
);
2327 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2328 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2330 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2332 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2337 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
2338 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2339 return connector_status_connected
;
2342 static int intel_dp_get_modes(struct drm_connector
*connector
)
2344 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2345 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2346 struct drm_device
*dev
= connector
->dev
;
2349 /* We should parse the EDID data and find out if it has an audio sink
2352 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2356 /* if eDP has no EDID, fall back to fixed mode */
2357 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2358 struct drm_display_mode
*mode
;
2359 mode
= drm_mode_duplicate(dev
,
2360 intel_connector
->panel
.fixed_mode
);
2362 drm_mode_probed_add(connector
, mode
);
2370 intel_dp_detect_audio(struct drm_connector
*connector
)
2372 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2374 bool has_audio
= false;
2376 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2378 has_audio
= drm_detect_monitor_audio(edid
);
2386 intel_dp_set_property(struct drm_connector
*connector
,
2387 struct drm_property
*property
,
2390 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2391 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2392 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
2393 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2396 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
2400 if (property
== dev_priv
->force_audio_property
) {
2404 if (i
== intel_dp
->force_audio
)
2407 intel_dp
->force_audio
= i
;
2409 if (i
== HDMI_AUDIO_AUTO
)
2410 has_audio
= intel_dp_detect_audio(connector
);
2412 has_audio
= (i
== HDMI_AUDIO_ON
);
2414 if (has_audio
== intel_dp
->has_audio
)
2417 intel_dp
->has_audio
= has_audio
;
2421 if (property
== dev_priv
->broadcast_rgb_property
) {
2422 if (val
== !!intel_dp
->color_range
)
2425 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2429 if (is_edp(intel_dp
) &&
2430 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
2431 if (val
== DRM_MODE_SCALE_NONE
) {
2432 DRM_DEBUG_KMS("no scaling not supported\n");
2436 if (intel_connector
->panel
.fitting_mode
== val
) {
2437 /* the eDP scaling property is not changed */
2440 intel_connector
->panel
.fitting_mode
= val
;
2448 if (intel_encoder
->base
.crtc
) {
2449 struct drm_crtc
*crtc
= intel_encoder
->base
.crtc
;
2450 intel_set_mode(crtc
, &crtc
->mode
,
2451 crtc
->x
, crtc
->y
, crtc
->fb
);
2458 intel_dp_destroy(struct drm_connector
*connector
)
2460 struct drm_device
*dev
= connector
->dev
;
2461 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2462 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2464 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
2465 kfree(intel_connector
->edid
);
2467 if (is_edp(intel_dp
)) {
2468 intel_panel_destroy_backlight(dev
);
2469 intel_panel_fini(&intel_connector
->panel
);
2472 drm_sysfs_connector_remove(connector
);
2473 drm_connector_cleanup(connector
);
2477 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2479 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2480 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2482 i2c_del_adapter(&intel_dp
->adapter
);
2483 drm_encoder_cleanup(encoder
);
2484 if (is_edp(intel_dp
)) {
2485 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2486 ironlake_panel_vdd_off_sync(intel_dp
);
2488 kfree(intel_dig_port
);
2491 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2492 .mode_fixup
= intel_dp_mode_fixup
,
2493 .mode_set
= intel_dp_mode_set
,
2494 .disable
= intel_encoder_noop
,
2497 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2498 .dpms
= intel_connector_dpms
,
2499 .detect
= intel_dp_detect
,
2500 .fill_modes
= drm_helper_probe_single_connector_modes
,
2501 .set_property
= intel_dp_set_property
,
2502 .destroy
= intel_dp_destroy
,
2505 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2506 .get_modes
= intel_dp_get_modes
,
2507 .mode_valid
= intel_dp_mode_valid
,
2508 .best_encoder
= intel_best_encoder
,
2511 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2512 .destroy
= intel_dp_encoder_destroy
,
2516 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2518 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2520 intel_dp_check_link_status(intel_dp
);
2523 /* Return which DP Port should be selected for Transcoder DP control */
2525 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2527 struct drm_device
*dev
= crtc
->dev
;
2528 struct intel_encoder
*intel_encoder
;
2529 struct intel_dp
*intel_dp
;
2531 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2532 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2534 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2535 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2536 return intel_dp
->output_reg
;
2542 /* check the VBT to see whether the eDP is on DP-D port */
2543 bool intel_dpd_is_edp(struct drm_device
*dev
)
2545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2546 struct child_device_config
*p_child
;
2549 if (!dev_priv
->child_dev_num
)
2552 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2553 p_child
= dev_priv
->child_dev
+ i
;
2555 if (p_child
->dvo_port
== PORT_IDPD
&&
2556 p_child
->device_type
== DEVICE_TYPE_eDP
)
2563 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2565 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2567 intel_attach_force_audio_property(connector
);
2568 intel_attach_broadcast_rgb_property(connector
);
2570 if (is_edp(intel_dp
)) {
2571 drm_mode_create_scaling_mode_property(connector
->dev
);
2572 drm_connector_attach_property(
2574 connector
->dev
->mode_config
.scaling_mode_property
,
2575 DRM_MODE_SCALE_ASPECT
);
2576 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
2581 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
2582 struct intel_dp
*intel_dp
)
2584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2585 struct edp_power_seq cur
, vbt
, spec
, final
;
2586 u32 pp_on
, pp_off
, pp_div
, pp
;
2588 /* Workaround: Need to write PP_CONTROL with the unlock key as
2589 * the very first thing. */
2590 pp
= ironlake_get_pp_control(dev_priv
);
2591 I915_WRITE(PCH_PP_CONTROL
, pp
);
2593 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2594 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2595 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2597 /* Pull timing values out of registers */
2598 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2599 PANEL_POWER_UP_DELAY_SHIFT
;
2601 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2602 PANEL_LIGHT_ON_DELAY_SHIFT
;
2604 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2605 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2607 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2608 PANEL_POWER_DOWN_DELAY_SHIFT
;
2610 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2611 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2613 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2614 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2616 vbt
= dev_priv
->edp
.pps
;
2618 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2619 * our hw here, which are all in 100usec. */
2620 spec
.t1_t3
= 210 * 10;
2621 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
2622 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
2623 spec
.t10
= 500 * 10;
2624 /* This one is special and actually in units of 100ms, but zero
2625 * based in the hw (so we need to add 100 ms). But the sw vbt
2626 * table multiplies it with 1000 to make it in units of 100usec,
2628 spec
.t11_t12
= (510 + 100) * 10;
2630 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2631 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2633 /* Use the max of the register settings and vbt. If both are
2634 * unset, fall back to the spec limits. */
2635 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2637 max(cur.field, vbt.field))
2638 assign_final(t1_t3
);
2642 assign_final(t11_t12
);
2645 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2646 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2647 intel_dp
->backlight_on_delay
= get_delay(t8
);
2648 intel_dp
->backlight_off_delay
= get_delay(t9
);
2649 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2650 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2653 /* And finally store the new values in the power sequencer. */
2654 pp_on
= (final
.t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
2655 (final
.t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
2656 pp_off
= (final
.t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
2657 (final
.t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
2658 /* Compute the divisor for the pp clock, simply match the Bspec
2660 pp_div
= ((100 * intel_pch_rawclk(dev
))/2 - 1)
2661 << PP_REFERENCE_DIVIDER_SHIFT
;
2662 pp_div
|= (DIV_ROUND_UP(final
.t11_t12
, 1000)
2663 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
2665 /* Haswell doesn't have any port selection bits for the panel
2666 * power sequencer any more. */
2667 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
2668 if (is_cpu_edp(intel_dp
))
2669 pp_on
|= PANEL_POWER_PORT_DP_A
;
2671 pp_on
|= PANEL_POWER_PORT_DP_D
;
2674 I915_WRITE(PCH_PP_ON_DELAYS
, pp_on
);
2675 I915_WRITE(PCH_PP_OFF_DELAYS
, pp_off
);
2676 I915_WRITE(PCH_PP_DIVISOR
, pp_div
);
2679 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2680 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2681 intel_dp
->panel_power_cycle_delay
);
2683 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2684 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2686 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2687 I915_READ(PCH_PP_ON_DELAYS
),
2688 I915_READ(PCH_PP_OFF_DELAYS
),
2689 I915_READ(PCH_PP_DIVISOR
));
2693 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
2694 struct intel_connector
*intel_connector
)
2696 struct drm_connector
*connector
= &intel_connector
->base
;
2697 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2698 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2699 struct drm_device
*dev
= intel_encoder
->base
.dev
;
2700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2701 struct drm_display_mode
*fixed_mode
= NULL
;
2702 enum port port
= intel_dig_port
->port
;
2703 const char *name
= NULL
;
2706 /* Preserve the current hw state. */
2707 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2708 intel_dp
->attached_connector
= intel_connector
;
2710 if (HAS_PCH_SPLIT(dev
) && port
== PORT_D
)
2711 if (intel_dpd_is_edp(dev
))
2712 intel_dp
->is_pch_edp
= true;
2715 * FIXME : We need to initialize built-in panels before external panels.
2716 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2718 if (IS_VALLEYVIEW(dev
) && port
== PORT_C
) {
2719 type
= DRM_MODE_CONNECTOR_eDP
;
2720 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2721 } else if (port
== PORT_A
|| is_pch_edp(intel_dp
)) {
2722 type
= DRM_MODE_CONNECTOR_eDP
;
2723 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2725 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2726 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2729 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2732 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2733 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2735 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2736 connector
->interlace_allowed
= true;
2737 connector
->doublescan_allowed
= 0;
2739 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2740 ironlake_panel_vdd_work
);
2742 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2743 drm_sysfs_connector_add(connector
);
2745 if (IS_HASWELL(dev
))
2746 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
2748 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2751 /* Set up the DDC bus. */
2757 dev_priv
->hotplug_supported_mask
|= DPB_HOTPLUG_INT_STATUS
;
2761 dev_priv
->hotplug_supported_mask
|= DPC_HOTPLUG_INT_STATUS
;
2765 dev_priv
->hotplug_supported_mask
|= DPD_HOTPLUG_INT_STATUS
;
2769 WARN(1, "Invalid port %c\n", port_name(port
));
2773 if (is_edp(intel_dp
))
2774 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2776 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2778 /* Cache DPCD and EDID for edp. */
2779 if (is_edp(intel_dp
)) {
2781 struct drm_display_mode
*scan
;
2784 ironlake_edp_panel_vdd_on(intel_dp
);
2785 ret
= intel_dp_get_dpcd(intel_dp
);
2786 ironlake_edp_panel_vdd_off(intel_dp
, false);
2789 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2790 dev_priv
->no_aux_handshake
=
2791 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2792 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2794 /* if this fails, presume the device is a ghost */
2795 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2796 intel_dp_encoder_destroy(&intel_encoder
->base
);
2797 intel_dp_destroy(connector
);
2801 ironlake_edp_panel_vdd_on(intel_dp
);
2802 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2804 if (drm_add_edid_modes(connector
, edid
)) {
2805 drm_mode_connector_update_edid_property(connector
, edid
);
2806 drm_edid_to_eld(connector
, edid
);
2809 edid
= ERR_PTR(-EINVAL
);
2812 edid
= ERR_PTR(-ENOENT
);
2814 intel_connector
->edid
= edid
;
2816 /* prefer fixed mode from EDID if available */
2817 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
2818 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2819 fixed_mode
= drm_mode_duplicate(dev
, scan
);
2824 /* fallback to VBT if available for eDP */
2825 if (!fixed_mode
&& dev_priv
->lfp_lvds_vbt_mode
) {
2826 fixed_mode
= drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2828 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
2831 ironlake_edp_panel_vdd_off(intel_dp
, false);
2834 if (is_edp(intel_dp
)) {
2835 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
2836 intel_panel_setup_backlight(connector
);
2839 intel_dp_add_properties(intel_dp
, connector
);
2841 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2842 * 0xd. Failure to do so will result in spurious interrupts being
2843 * generated on the port when a cable is not attached.
2845 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2846 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2847 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
2852 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2854 struct intel_digital_port
*intel_dig_port
;
2855 struct intel_encoder
*intel_encoder
;
2856 struct drm_encoder
*encoder
;
2857 struct intel_connector
*intel_connector
;
2859 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
2860 if (!intel_dig_port
)
2863 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2864 if (!intel_connector
) {
2865 kfree(intel_dig_port
);
2869 intel_encoder
= &intel_dig_port
->base
;
2870 encoder
= &intel_encoder
->base
;
2872 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2873 DRM_MODE_ENCODER_TMDS
);
2874 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2876 intel_encoder
->enable
= intel_enable_dp
;
2877 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2878 intel_encoder
->disable
= intel_disable_dp
;
2879 intel_encoder
->post_disable
= intel_post_disable_dp
;
2880 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2882 intel_dig_port
->port
= port
;
2883 intel_dig_port
->dp
.output_reg
= output_reg
;
2885 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2886 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2887 intel_encoder
->cloneable
= false;
2888 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2890 intel_dp_init_connector(intel_dig_port
, intel_connector
);