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drm/i915: Remove duplicate intel_uncore_forcewake_reset.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44 };
45
46 static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51 };
52
53 static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58 };
59
60 static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65 };
66
67 /**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74 static bool is_edp(struct intel_dp *intel_dp)
75 {
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
79 }
80
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
82 {
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
86 }
87
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89 {
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
91 }
92
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94
95 static int
96 intel_dp_max_link_bw(struct intel_dp *intel_dp)
97 {
98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
107 default:
108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114 }
115
116 /*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
133 static int
134 intel_dp_link_required(int pixel_clock, int bpp)
135 {
136 return (pixel_clock * bpp + 9) / 10;
137 }
138
139 static int
140 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141 {
142 return (max_link_clock * max_lanes * 8) / 10;
143 }
144
145 static enum drm_mode_status
146 intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148 {
149 struct intel_dp *intel_dp = intel_attached_dp(connector);
150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
154
155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
157 return MODE_PANEL;
158
159 if (mode->vdisplay > fixed_mode->vdisplay)
160 return MODE_PANEL;
161
162 target_clock = fixed_mode->clock;
163 }
164
165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
172 return MODE_CLOCK_HIGH;
173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
180 return MODE_OK;
181 }
182
183 static uint32_t
184 pack_aux(uint8_t *src, int src_bytes)
185 {
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194 }
195
196 static void
197 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198 {
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204 }
205
206 /* hrawclock is 1/4 the FSB frequency */
207 static int
208 intel_hrawclk(struct drm_device *dev)
209 {
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238 }
239
240 static void
241 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244 static void
245 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249 static enum pipe
250 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251 {
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275 }
276
277 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278 {
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285 }
286
287 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288 {
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295 }
296
297 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298 {
299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
300 struct drm_i915_private *dev_priv = dev->dev_private;
301
302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
303 }
304
305 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306 {
307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
308 struct drm_i915_private *dev_priv = dev->dev_private;
309
310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
311 }
312
313 static void
314 intel_dp_check_edp(struct intel_dp *intel_dp)
315 {
316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
317 struct drm_i915_private *dev_priv = dev->dev_private;
318
319 if (!is_edp(intel_dp))
320 return;
321
322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
327 }
328 }
329
330 static uint32_t
331 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332 {
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
337 uint32_t status;
338 bool done;
339
340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
341 if (has_aux_irq)
342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
343 msecs_to_jiffies_timeout(10));
344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349 #undef C
350
351 return status;
352 }
353
354 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
356 {
357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
359 struct drm_i915_private *dev_priv = dev->dev_private;
360
361 /* The clock divider is based off the hrawclk,
362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
367 */
368 if (IS_VALLEYVIEW(dev)) {
369 return index ? 0 : 100;
370 } else if (intel_dig_port->port == PORT_A) {
371 if (index)
372 return 0;
373 if (HAS_DDI(dev))
374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
377 else
378 return 225; /* eDP input clock at 450Mhz */
379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
386 } else if (HAS_PCH_SPLIT(dev)) {
387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
388 } else {
389 return index ? 0 :intel_hrawclk(dev) / 2;
390 }
391 }
392
393 static int
394 intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397 {
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
403 uint32_t aux_clock_divider;
404 int i, ret, recv_bytes;
405 uint32_t status;
406 int try, precharge, clock = 0;
407 bool has_aux_irq = true;
408 uint32_t timeout;
409
410 /* dp aux is extremely sensitive to irq latency, hence request the
411 * lowest possible wakeup latency and so prevent the cpu from going into
412 * deep sleep states.
413 */
414 pm_qos_update_request(&dev_priv->pm_qos, 0);
415
416 intel_dp_check_edp(intel_dp);
417
418 if (IS_GEN6(dev))
419 precharge = 3;
420 else
421 precharge = 5;
422
423 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
424 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
425 else
426 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
427
428 intel_aux_display_runtime_get(dev_priv);
429
430 /* Try to wait for any previous AUX channel activity */
431 for (try = 0; try < 3; try++) {
432 status = I915_READ_NOTRACE(ch_ctl);
433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
434 break;
435 msleep(1);
436 }
437
438 if (try == 3) {
439 WARN(1, "dp_aux_ch not started status 0x%08x\n",
440 I915_READ(ch_ctl));
441 ret = -EBUSY;
442 goto out;
443 }
444
445 /* Only 5 data registers! */
446 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
447 ret = -E2BIG;
448 goto out;
449 }
450
451 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
452 /* Must try at least 3 times according to DP spec */
453 for (try = 0; try < 5; try++) {
454 /* Load the send data into the aux channel data registers */
455 for (i = 0; i < send_bytes; i += 4)
456 I915_WRITE(ch_data + i,
457 pack_aux(send + i, send_bytes - i));
458
459 /* Send the command and wait for it to complete */
460 I915_WRITE(ch_ctl,
461 DP_AUX_CH_CTL_SEND_BUSY |
462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
463 timeout |
464 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
465 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
466 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
467 DP_AUX_CH_CTL_DONE |
468 DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR);
470
471 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
472
473 /* Clear done status and any errors */
474 I915_WRITE(ch_ctl,
475 status |
476 DP_AUX_CH_CTL_DONE |
477 DP_AUX_CH_CTL_TIME_OUT_ERROR |
478 DP_AUX_CH_CTL_RECEIVE_ERROR);
479
480 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR))
482 continue;
483 if (status & DP_AUX_CH_CTL_DONE)
484 break;
485 }
486 if (status & DP_AUX_CH_CTL_DONE)
487 break;
488 }
489
490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
492 ret = -EBUSY;
493 goto out;
494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
501 ret = -EIO;
502 goto out;
503 }
504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
509 ret = -ETIMEDOUT;
510 goto out;
511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
518
519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
522
523 ret = recv_bytes;
524 out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526 intel_aux_display_runtime_put(dev_priv);
527
528 return ret;
529 }
530
531 /* Write data to the aux channel in native mode */
532 static int
533 intel_dp_aux_native_write(struct intel_dp *intel_dp,
534 uint16_t address, uint8_t *send, int send_bytes)
535 {
536 int ret;
537 uint8_t msg[20];
538 int msg_bytes;
539 uint8_t ack;
540
541 if (WARN_ON(send_bytes > 16))
542 return -E2BIG;
543
544 intel_dp_check_edp(intel_dp);
545 msg[0] = AUX_NATIVE_WRITE << 4;
546 msg[1] = address >> 8;
547 msg[2] = address & 0xff;
548 msg[3] = send_bytes - 1;
549 memcpy(&msg[4], send, send_bytes);
550 msg_bytes = send_bytes + 4;
551 for (;;) {
552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
553 if (ret < 0)
554 return ret;
555 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
556 break;
557 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
558 udelay(100);
559 else
560 return -EIO;
561 }
562 return send_bytes;
563 }
564
565 /* Write a single byte to the aux channel in native mode */
566 static int
567 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
568 uint16_t address, uint8_t byte)
569 {
570 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
571 }
572
573 /* read bytes from a native aux channel */
574 static int
575 intel_dp_aux_native_read(struct intel_dp *intel_dp,
576 uint16_t address, uint8_t *recv, int recv_bytes)
577 {
578 uint8_t msg[4];
579 int msg_bytes;
580 uint8_t reply[20];
581 int reply_bytes;
582 uint8_t ack;
583 int ret;
584
585 if (WARN_ON(recv_bytes > 19))
586 return -E2BIG;
587
588 intel_dp_check_edp(intel_dp);
589 msg[0] = AUX_NATIVE_READ << 4;
590 msg[1] = address >> 8;
591 msg[2] = address & 0xff;
592 msg[3] = recv_bytes - 1;
593
594 msg_bytes = 4;
595 reply_bytes = recv_bytes + 1;
596
597 for (;;) {
598 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
599 reply, reply_bytes);
600 if (ret == 0)
601 return -EPROTO;
602 if (ret < 0)
603 return ret;
604 ack = reply[0];
605 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
606 memcpy(recv, reply + 1, ret - 1);
607 return ret - 1;
608 }
609 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
610 udelay(100);
611 else
612 return -EIO;
613 }
614 }
615
616 static int
617 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
618 uint8_t write_byte, uint8_t *read_byte)
619 {
620 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
621 struct intel_dp *intel_dp = container_of(adapter,
622 struct intel_dp,
623 adapter);
624 uint16_t address = algo_data->address;
625 uint8_t msg[5];
626 uint8_t reply[2];
627 unsigned retry;
628 int msg_bytes;
629 int reply_bytes;
630 int ret;
631
632 ironlake_edp_panel_vdd_on(intel_dp);
633 intel_dp_check_edp(intel_dp);
634 /* Set up the command byte */
635 if (mode & MODE_I2C_READ)
636 msg[0] = AUX_I2C_READ << 4;
637 else
638 msg[0] = AUX_I2C_WRITE << 4;
639
640 if (!(mode & MODE_I2C_STOP))
641 msg[0] |= AUX_I2C_MOT << 4;
642
643 msg[1] = address >> 8;
644 msg[2] = address;
645
646 switch (mode) {
647 case MODE_I2C_WRITE:
648 msg[3] = 0;
649 msg[4] = write_byte;
650 msg_bytes = 5;
651 reply_bytes = 1;
652 break;
653 case MODE_I2C_READ:
654 msg[3] = 0;
655 msg_bytes = 4;
656 reply_bytes = 2;
657 break;
658 default:
659 msg_bytes = 3;
660 reply_bytes = 1;
661 break;
662 }
663
664 /*
665 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
666 * required to retry at least seven times upon receiving AUX_DEFER
667 * before giving up the AUX transaction.
668 */
669 for (retry = 0; retry < 7; retry++) {
670 ret = intel_dp_aux_ch(intel_dp,
671 msg, msg_bytes,
672 reply, reply_bytes);
673 if (ret < 0) {
674 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
675 goto out;
676 }
677
678 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
679 case AUX_NATIVE_REPLY_ACK:
680 /* I2C-over-AUX Reply field is only valid
681 * when paired with AUX ACK.
682 */
683 break;
684 case AUX_NATIVE_REPLY_NACK:
685 DRM_DEBUG_KMS("aux_ch native nack\n");
686 ret = -EREMOTEIO;
687 goto out;
688 case AUX_NATIVE_REPLY_DEFER:
689 /*
690 * For now, just give more slack to branch devices. We
691 * could check the DPCD for I2C bit rate capabilities,
692 * and if available, adjust the interval. We could also
693 * be more careful with DP-to-Legacy adapters where a
694 * long legacy cable may force very low I2C bit rates.
695 */
696 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
697 DP_DWN_STRM_PORT_PRESENT)
698 usleep_range(500, 600);
699 else
700 usleep_range(300, 400);
701 continue;
702 default:
703 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
704 reply[0]);
705 ret = -EREMOTEIO;
706 goto out;
707 }
708
709 switch (reply[0] & AUX_I2C_REPLY_MASK) {
710 case AUX_I2C_REPLY_ACK:
711 if (mode == MODE_I2C_READ) {
712 *read_byte = reply[1];
713 }
714 ret = reply_bytes - 1;
715 goto out;
716 case AUX_I2C_REPLY_NACK:
717 DRM_DEBUG_KMS("aux_i2c nack\n");
718 ret = -EREMOTEIO;
719 goto out;
720 case AUX_I2C_REPLY_DEFER:
721 DRM_DEBUG_KMS("aux_i2c defer\n");
722 udelay(100);
723 break;
724 default:
725 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
726 ret = -EREMOTEIO;
727 goto out;
728 }
729 }
730
731 DRM_ERROR("too many retries, giving up\n");
732 ret = -EREMOTEIO;
733
734 out:
735 ironlake_edp_panel_vdd_off(intel_dp, false);
736 return ret;
737 }
738
739 static int
740 intel_dp_i2c_init(struct intel_dp *intel_dp,
741 struct intel_connector *intel_connector, const char *name)
742 {
743 int ret;
744
745 DRM_DEBUG_KMS("i2c_init %s\n", name);
746 intel_dp->algo.running = false;
747 intel_dp->algo.address = 0;
748 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
749
750 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
751 intel_dp->adapter.owner = THIS_MODULE;
752 intel_dp->adapter.class = I2C_CLASS_DDC;
753 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
754 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
755 intel_dp->adapter.algo_data = &intel_dp->algo;
756 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
757
758 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
759 return ret;
760 }
761
762 static void
763 intel_dp_set_clock(struct intel_encoder *encoder,
764 struct intel_crtc_config *pipe_config, int link_bw)
765 {
766 struct drm_device *dev = encoder->base.dev;
767 const struct dp_link_dpll *divisor = NULL;
768 int i, count = 0;
769
770 if (IS_G4X(dev)) {
771 divisor = gen4_dpll;
772 count = ARRAY_SIZE(gen4_dpll);
773 } else if (IS_HASWELL(dev)) {
774 /* Haswell has special-purpose DP DDI clocks. */
775 } else if (HAS_PCH_SPLIT(dev)) {
776 divisor = pch_dpll;
777 count = ARRAY_SIZE(pch_dpll);
778 } else if (IS_VALLEYVIEW(dev)) {
779 divisor = vlv_dpll;
780 count = ARRAY_SIZE(vlv_dpll);
781 }
782
783 if (divisor && count) {
784 for (i = 0; i < count; i++) {
785 if (link_bw == divisor[i].link_bw) {
786 pipe_config->dpll = divisor[i].dpll;
787 pipe_config->clock_set = true;
788 break;
789 }
790 }
791 }
792 }
793
794 bool
795 intel_dp_compute_config(struct intel_encoder *encoder,
796 struct intel_crtc_config *pipe_config)
797 {
798 struct drm_device *dev = encoder->base.dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
800 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
802 enum port port = dp_to_dig_port(intel_dp)->port;
803 struct intel_crtc *intel_crtc = encoder->new_crtc;
804 struct intel_connector *intel_connector = intel_dp->attached_connector;
805 int lane_count, clock;
806 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
807 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
808 int bpp, mode_rate;
809 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
810 int link_avail, link_clock;
811
812 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
813 pipe_config->has_pch_encoder = true;
814
815 pipe_config->has_dp_encoder = true;
816
817 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
818 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
819 adjusted_mode);
820 if (!HAS_PCH_SPLIT(dev))
821 intel_gmch_panel_fitting(intel_crtc, pipe_config,
822 intel_connector->panel.fitting_mode);
823 else
824 intel_pch_panel_fitting(intel_crtc, pipe_config,
825 intel_connector->panel.fitting_mode);
826 }
827
828 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
829 return false;
830
831 DRM_DEBUG_KMS("DP link computation with max lane count %i "
832 "max bw %02x pixel clock %iKHz\n",
833 max_lane_count, bws[max_clock],
834 adjusted_mode->crtc_clock);
835
836 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
837 * bpc in between. */
838 bpp = pipe_config->pipe_bpp;
839 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
840 dev_priv->vbt.edp_bpp < bpp) {
841 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
842 dev_priv->vbt.edp_bpp);
843 bpp = dev_priv->vbt.edp_bpp;
844 }
845
846 for (; bpp >= 6*3; bpp -= 2*3) {
847 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
848 bpp);
849
850 for (clock = 0; clock <= max_clock; clock++) {
851 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
852 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
853 link_avail = intel_dp_max_data_rate(link_clock,
854 lane_count);
855
856 if (mode_rate <= link_avail) {
857 goto found;
858 }
859 }
860 }
861 }
862
863 return false;
864
865 found:
866 if (intel_dp->color_range_auto) {
867 /*
868 * See:
869 * CEA-861-E - 5.1 Default Encoding Parameters
870 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
871 */
872 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
873 intel_dp->color_range = DP_COLOR_RANGE_16_235;
874 else
875 intel_dp->color_range = 0;
876 }
877
878 if (intel_dp->color_range)
879 pipe_config->limited_color_range = true;
880
881 intel_dp->link_bw = bws[clock];
882 intel_dp->lane_count = lane_count;
883 pipe_config->pipe_bpp = bpp;
884 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
885
886 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
887 intel_dp->link_bw, intel_dp->lane_count,
888 pipe_config->port_clock, bpp);
889 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
890 mode_rate, link_avail);
891
892 intel_link_compute_m_n(bpp, lane_count,
893 adjusted_mode->crtc_clock,
894 pipe_config->port_clock,
895 &pipe_config->dp_m_n);
896
897 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
898
899 return true;
900 }
901
902 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
903 {
904 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
905 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
906 struct drm_device *dev = crtc->base.dev;
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 u32 dpa_ctl;
909
910 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
911 dpa_ctl = I915_READ(DP_A);
912 dpa_ctl &= ~DP_PLL_FREQ_MASK;
913
914 if (crtc->config.port_clock == 162000) {
915 /* For a long time we've carried around a ILK-DevA w/a for the
916 * 160MHz clock. If we're really unlucky, it's still required.
917 */
918 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
919 dpa_ctl |= DP_PLL_FREQ_160MHZ;
920 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
921 } else {
922 dpa_ctl |= DP_PLL_FREQ_270MHZ;
923 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
924 }
925
926 I915_WRITE(DP_A, dpa_ctl);
927
928 POSTING_READ(DP_A);
929 udelay(500);
930 }
931
932 static void intel_dp_mode_set(struct intel_encoder *encoder)
933 {
934 struct drm_device *dev = encoder->base.dev;
935 struct drm_i915_private *dev_priv = dev->dev_private;
936 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
937 enum port port = dp_to_dig_port(intel_dp)->port;
938 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
939 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
940
941 /*
942 * There are four kinds of DP registers:
943 *
944 * IBX PCH
945 * SNB CPU
946 * IVB CPU
947 * CPT PCH
948 *
949 * IBX PCH and CPU are the same for almost everything,
950 * except that the CPU DP PLL is configured in this
951 * register
952 *
953 * CPT PCH is quite different, having many bits moved
954 * to the TRANS_DP_CTL register instead. That
955 * configuration happens (oddly) in ironlake_pch_enable
956 */
957
958 /* Preserve the BIOS-computed detected bit. This is
959 * supposed to be read-only.
960 */
961 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
962
963 /* Handle DP bits in common between all three register formats */
964 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
965 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
966
967 if (intel_dp->has_audio) {
968 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
969 pipe_name(crtc->pipe));
970 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
971 intel_write_eld(&encoder->base, adjusted_mode);
972 }
973
974 /* Split out the IBX/CPU vs CPT settings */
975
976 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
977 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
978 intel_dp->DP |= DP_SYNC_HS_HIGH;
979 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
980 intel_dp->DP |= DP_SYNC_VS_HIGH;
981 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
982
983 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
984 intel_dp->DP |= DP_ENHANCED_FRAMING;
985
986 intel_dp->DP |= crtc->pipe << 29;
987 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
988 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
989 intel_dp->DP |= intel_dp->color_range;
990
991 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
992 intel_dp->DP |= DP_SYNC_HS_HIGH;
993 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
994 intel_dp->DP |= DP_SYNC_VS_HIGH;
995 intel_dp->DP |= DP_LINK_TRAIN_OFF;
996
997 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
998 intel_dp->DP |= DP_ENHANCED_FRAMING;
999
1000 if (crtc->pipe == 1)
1001 intel_dp->DP |= DP_PIPEB_SELECT;
1002 } else {
1003 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1004 }
1005
1006 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1007 ironlake_set_pll_cpu_edp(intel_dp);
1008 }
1009
1010 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1011 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1012
1013 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1014 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1015
1016 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1017 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1018
1019 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1020 u32 mask,
1021 u32 value)
1022 {
1023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 u32 pp_stat_reg, pp_ctrl_reg;
1026
1027 pp_stat_reg = _pp_stat_reg(intel_dp);
1028 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1029
1030 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1031 mask, value,
1032 I915_READ(pp_stat_reg),
1033 I915_READ(pp_ctrl_reg));
1034
1035 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1036 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1037 I915_READ(pp_stat_reg),
1038 I915_READ(pp_ctrl_reg));
1039 }
1040
1041 DRM_DEBUG_KMS("Wait complete\n");
1042 }
1043
1044 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1045 {
1046 DRM_DEBUG_KMS("Wait for panel power on\n");
1047 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1048 }
1049
1050 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1051 {
1052 DRM_DEBUG_KMS("Wait for panel power off time\n");
1053 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1054 }
1055
1056 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1057 {
1058 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1059 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1060 }
1061
1062
1063 /* Read the current pp_control value, unlocking the register if it
1064 * is locked
1065 */
1066
1067 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1068 {
1069 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 u32 control;
1072
1073 control = I915_READ(_pp_ctrl_reg(intel_dp));
1074 control &= ~PANEL_UNLOCK_MASK;
1075 control |= PANEL_UNLOCK_REGS;
1076 return control;
1077 }
1078
1079 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1080 {
1081 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1083 u32 pp;
1084 u32 pp_stat_reg, pp_ctrl_reg;
1085
1086 if (!is_edp(intel_dp))
1087 return;
1088
1089 WARN(intel_dp->want_panel_vdd,
1090 "eDP VDD already requested on\n");
1091
1092 intel_dp->want_panel_vdd = true;
1093
1094 if (ironlake_edp_have_panel_vdd(intel_dp))
1095 return;
1096
1097 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1098
1099 if (!ironlake_edp_have_panel_power(intel_dp))
1100 ironlake_wait_panel_power_cycle(intel_dp);
1101
1102 pp = ironlake_get_pp_control(intel_dp);
1103 pp |= EDP_FORCE_VDD;
1104
1105 pp_stat_reg = _pp_stat_reg(intel_dp);
1106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1107
1108 I915_WRITE(pp_ctrl_reg, pp);
1109 POSTING_READ(pp_ctrl_reg);
1110 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1111 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1112 /*
1113 * If the panel wasn't on, delay before accessing aux channel
1114 */
1115 if (!ironlake_edp_have_panel_power(intel_dp)) {
1116 DRM_DEBUG_KMS("eDP was not running\n");
1117 msleep(intel_dp->panel_power_up_delay);
1118 }
1119 }
1120
1121 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1122 {
1123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1124 struct drm_i915_private *dev_priv = dev->dev_private;
1125 u32 pp;
1126 u32 pp_stat_reg, pp_ctrl_reg;
1127
1128 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1129
1130 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1131 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1132
1133 pp = ironlake_get_pp_control(intel_dp);
1134 pp &= ~EDP_FORCE_VDD;
1135
1136 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1137 pp_stat_reg = _pp_stat_reg(intel_dp);
1138
1139 I915_WRITE(pp_ctrl_reg, pp);
1140 POSTING_READ(pp_ctrl_reg);
1141
1142 /* Make sure sequencer is idle before allowing subsequent activity */
1143 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1144 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1145 msleep(intel_dp->panel_power_down_delay);
1146 }
1147 }
1148
1149 static void ironlake_panel_vdd_work(struct work_struct *__work)
1150 {
1151 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1152 struct intel_dp, panel_vdd_work);
1153 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1154
1155 mutex_lock(&dev->mode_config.mutex);
1156 ironlake_panel_vdd_off_sync(intel_dp);
1157 mutex_unlock(&dev->mode_config.mutex);
1158 }
1159
1160 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1161 {
1162 if (!is_edp(intel_dp))
1163 return;
1164
1165 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1166
1167 intel_dp->want_panel_vdd = false;
1168
1169 if (sync) {
1170 ironlake_panel_vdd_off_sync(intel_dp);
1171 } else {
1172 /*
1173 * Queue the timer to fire a long
1174 * time from now (relative to the power down delay)
1175 * to keep the panel power up across a sequence of operations
1176 */
1177 schedule_delayed_work(&intel_dp->panel_vdd_work,
1178 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1179 }
1180 }
1181
1182 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1183 {
1184 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186 u32 pp;
1187 u32 pp_ctrl_reg;
1188
1189 if (!is_edp(intel_dp))
1190 return;
1191
1192 DRM_DEBUG_KMS("Turn eDP power on\n");
1193
1194 if (ironlake_edp_have_panel_power(intel_dp)) {
1195 DRM_DEBUG_KMS("eDP power already on\n");
1196 return;
1197 }
1198
1199 ironlake_wait_panel_power_cycle(intel_dp);
1200
1201 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1202 pp = ironlake_get_pp_control(intel_dp);
1203 if (IS_GEN5(dev)) {
1204 /* ILK workaround: disable reset around power sequence */
1205 pp &= ~PANEL_POWER_RESET;
1206 I915_WRITE(pp_ctrl_reg, pp);
1207 POSTING_READ(pp_ctrl_reg);
1208 }
1209
1210 pp |= POWER_TARGET_ON;
1211 if (!IS_GEN5(dev))
1212 pp |= PANEL_POWER_RESET;
1213
1214 I915_WRITE(pp_ctrl_reg, pp);
1215 POSTING_READ(pp_ctrl_reg);
1216
1217 ironlake_wait_panel_on(intel_dp);
1218
1219 if (IS_GEN5(dev)) {
1220 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1221 I915_WRITE(pp_ctrl_reg, pp);
1222 POSTING_READ(pp_ctrl_reg);
1223 }
1224 }
1225
1226 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1227 {
1228 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1229 struct drm_i915_private *dev_priv = dev->dev_private;
1230 u32 pp;
1231 u32 pp_ctrl_reg;
1232
1233 if (!is_edp(intel_dp))
1234 return;
1235
1236 DRM_DEBUG_KMS("Turn eDP power off\n");
1237
1238 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1239
1240 pp = ironlake_get_pp_control(intel_dp);
1241 /* We need to switch off panel power _and_ force vdd, for otherwise some
1242 * panels get very unhappy and cease to work. */
1243 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1244
1245 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1246
1247 I915_WRITE(pp_ctrl_reg, pp);
1248 POSTING_READ(pp_ctrl_reg);
1249
1250 intel_dp->want_panel_vdd = false;
1251
1252 ironlake_wait_panel_off(intel_dp);
1253 }
1254
1255 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1256 {
1257 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1258 struct drm_device *dev = intel_dig_port->base.base.dev;
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 u32 pp;
1261 u32 pp_ctrl_reg;
1262
1263 if (!is_edp(intel_dp))
1264 return;
1265
1266 DRM_DEBUG_KMS("\n");
1267 /*
1268 * If we enable the backlight right away following a panel power
1269 * on, we may see slight flicker as the panel syncs with the eDP
1270 * link. So delay a bit to make sure the image is solid before
1271 * allowing it to appear.
1272 */
1273 msleep(intel_dp->backlight_on_delay);
1274 pp = ironlake_get_pp_control(intel_dp);
1275 pp |= EDP_BLC_ENABLE;
1276
1277 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1278
1279 I915_WRITE(pp_ctrl_reg, pp);
1280 POSTING_READ(pp_ctrl_reg);
1281
1282 intel_panel_enable_backlight(intel_dp->attached_connector);
1283 }
1284
1285 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1286 {
1287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1288 struct drm_i915_private *dev_priv = dev->dev_private;
1289 u32 pp;
1290 u32 pp_ctrl_reg;
1291
1292 if (!is_edp(intel_dp))
1293 return;
1294
1295 intel_panel_disable_backlight(intel_dp->attached_connector);
1296
1297 DRM_DEBUG_KMS("\n");
1298 pp = ironlake_get_pp_control(intel_dp);
1299 pp &= ~EDP_BLC_ENABLE;
1300
1301 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1302
1303 I915_WRITE(pp_ctrl_reg, pp);
1304 POSTING_READ(pp_ctrl_reg);
1305 msleep(intel_dp->backlight_off_delay);
1306 }
1307
1308 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1309 {
1310 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1311 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1312 struct drm_device *dev = crtc->dev;
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 u32 dpa_ctl;
1315
1316 assert_pipe_disabled(dev_priv,
1317 to_intel_crtc(crtc)->pipe);
1318
1319 DRM_DEBUG_KMS("\n");
1320 dpa_ctl = I915_READ(DP_A);
1321 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1322 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1323
1324 /* We don't adjust intel_dp->DP while tearing down the link, to
1325 * facilitate link retraining (e.g. after hotplug). Hence clear all
1326 * enable bits here to ensure that we don't enable too much. */
1327 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1328 intel_dp->DP |= DP_PLL_ENABLE;
1329 I915_WRITE(DP_A, intel_dp->DP);
1330 POSTING_READ(DP_A);
1331 udelay(200);
1332 }
1333
1334 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1335 {
1336 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1337 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1338 struct drm_device *dev = crtc->dev;
1339 struct drm_i915_private *dev_priv = dev->dev_private;
1340 u32 dpa_ctl;
1341
1342 assert_pipe_disabled(dev_priv,
1343 to_intel_crtc(crtc)->pipe);
1344
1345 dpa_ctl = I915_READ(DP_A);
1346 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1347 "dp pll off, should be on\n");
1348 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1349
1350 /* We can't rely on the value tracked for the DP register in
1351 * intel_dp->DP because link_down must not change that (otherwise link
1352 * re-training will fail. */
1353 dpa_ctl &= ~DP_PLL_ENABLE;
1354 I915_WRITE(DP_A, dpa_ctl);
1355 POSTING_READ(DP_A);
1356 udelay(200);
1357 }
1358
1359 /* If the sink supports it, try to set the power state appropriately */
1360 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1361 {
1362 int ret, i;
1363
1364 /* Should have a valid DPCD by this point */
1365 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1366 return;
1367
1368 if (mode != DRM_MODE_DPMS_ON) {
1369 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1370 DP_SET_POWER_D3);
1371 if (ret != 1)
1372 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1373 } else {
1374 /*
1375 * When turning on, we need to retry for 1ms to give the sink
1376 * time to wake up.
1377 */
1378 for (i = 0; i < 3; i++) {
1379 ret = intel_dp_aux_native_write_1(intel_dp,
1380 DP_SET_POWER,
1381 DP_SET_POWER_D0);
1382 if (ret == 1)
1383 break;
1384 msleep(1);
1385 }
1386 }
1387 }
1388
1389 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1390 enum pipe *pipe)
1391 {
1392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1393 enum port port = dp_to_dig_port(intel_dp)->port;
1394 struct drm_device *dev = encoder->base.dev;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 u32 tmp = I915_READ(intel_dp->output_reg);
1397
1398 if (!(tmp & DP_PORT_EN))
1399 return false;
1400
1401 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1402 *pipe = PORT_TO_PIPE_CPT(tmp);
1403 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1404 *pipe = PORT_TO_PIPE(tmp);
1405 } else {
1406 u32 trans_sel;
1407 u32 trans_dp;
1408 int i;
1409
1410 switch (intel_dp->output_reg) {
1411 case PCH_DP_B:
1412 trans_sel = TRANS_DP_PORT_SEL_B;
1413 break;
1414 case PCH_DP_C:
1415 trans_sel = TRANS_DP_PORT_SEL_C;
1416 break;
1417 case PCH_DP_D:
1418 trans_sel = TRANS_DP_PORT_SEL_D;
1419 break;
1420 default:
1421 return true;
1422 }
1423
1424 for_each_pipe(i) {
1425 trans_dp = I915_READ(TRANS_DP_CTL(i));
1426 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1427 *pipe = i;
1428 return true;
1429 }
1430 }
1431
1432 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1433 intel_dp->output_reg);
1434 }
1435
1436 return true;
1437 }
1438
1439 static void intel_dp_get_config(struct intel_encoder *encoder,
1440 struct intel_crtc_config *pipe_config)
1441 {
1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1443 u32 tmp, flags = 0;
1444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 enum port port = dp_to_dig_port(intel_dp)->port;
1447 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1448 int dotclock;
1449
1450 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1451 tmp = I915_READ(intel_dp->output_reg);
1452 if (tmp & DP_SYNC_HS_HIGH)
1453 flags |= DRM_MODE_FLAG_PHSYNC;
1454 else
1455 flags |= DRM_MODE_FLAG_NHSYNC;
1456
1457 if (tmp & DP_SYNC_VS_HIGH)
1458 flags |= DRM_MODE_FLAG_PVSYNC;
1459 else
1460 flags |= DRM_MODE_FLAG_NVSYNC;
1461 } else {
1462 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1463 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1464 flags |= DRM_MODE_FLAG_PHSYNC;
1465 else
1466 flags |= DRM_MODE_FLAG_NHSYNC;
1467
1468 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1469 flags |= DRM_MODE_FLAG_PVSYNC;
1470 else
1471 flags |= DRM_MODE_FLAG_NVSYNC;
1472 }
1473
1474 pipe_config->adjusted_mode.flags |= flags;
1475
1476 pipe_config->has_dp_encoder = true;
1477
1478 intel_dp_get_m_n(crtc, pipe_config);
1479
1480 if (port == PORT_A) {
1481 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1482 pipe_config->port_clock = 162000;
1483 else
1484 pipe_config->port_clock = 270000;
1485 }
1486
1487 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1488 &pipe_config->dp_m_n);
1489
1490 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1491 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1492
1493 pipe_config->adjusted_mode.crtc_clock = dotclock;
1494
1495 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1496 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1497 /*
1498 * This is a big fat ugly hack.
1499 *
1500 * Some machines in UEFI boot mode provide us a VBT that has 18
1501 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1502 * unknown we fail to light up. Yet the same BIOS boots up with
1503 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1504 * max, not what it tells us to use.
1505 *
1506 * Note: This will still be broken if the eDP panel is not lit
1507 * up by the BIOS, and thus we can't get the mode at module
1508 * load.
1509 */
1510 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1511 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1512 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1513 }
1514 }
1515
1516 static bool is_edp_psr(struct drm_device *dev)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520 return dev_priv->psr.sink_support;
1521 }
1522
1523 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1524 {
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1526
1527 if (!HAS_PSR(dev))
1528 return false;
1529
1530 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1531 }
1532
1533 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1534 struct edp_vsc_psr *vsc_psr)
1535 {
1536 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1537 struct drm_device *dev = dig_port->base.base.dev;
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1540 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1541 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1542 uint32_t *data = (uint32_t *) vsc_psr;
1543 unsigned int i;
1544
1545 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1546 the video DIP being updated before program video DIP data buffer
1547 registers for DIP being updated. */
1548 I915_WRITE(ctl_reg, 0);
1549 POSTING_READ(ctl_reg);
1550
1551 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1552 if (i < sizeof(struct edp_vsc_psr))
1553 I915_WRITE(data_reg + i, *data++);
1554 else
1555 I915_WRITE(data_reg + i, 0);
1556 }
1557
1558 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1559 POSTING_READ(ctl_reg);
1560 }
1561
1562 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1563 {
1564 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566 struct edp_vsc_psr psr_vsc;
1567
1568 if (intel_dp->psr_setup_done)
1569 return;
1570
1571 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1572 memset(&psr_vsc, 0, sizeof(psr_vsc));
1573 psr_vsc.sdp_header.HB0 = 0;
1574 psr_vsc.sdp_header.HB1 = 0x7;
1575 psr_vsc.sdp_header.HB2 = 0x2;
1576 psr_vsc.sdp_header.HB3 = 0x8;
1577 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1578
1579 /* Avoid continuous PSR exit by masking memup and hpd */
1580 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1581 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1582
1583 intel_dp->psr_setup_done = true;
1584 }
1585
1586 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1587 {
1588 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1591 int precharge = 0x3;
1592 int msg_size = 5; /* Header(4) + Message(1) */
1593
1594 /* Enable PSR in sink */
1595 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1596 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1597 DP_PSR_ENABLE &
1598 ~DP_PSR_MAIN_LINK_ACTIVE);
1599 else
1600 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1601 DP_PSR_ENABLE |
1602 DP_PSR_MAIN_LINK_ACTIVE);
1603
1604 /* Setup AUX registers */
1605 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1606 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1607 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1608 DP_AUX_CH_CTL_TIME_OUT_400us |
1609 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1610 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1611 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1612 }
1613
1614 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1615 {
1616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 uint32_t max_sleep_time = 0x1f;
1619 uint32_t idle_frames = 1;
1620 uint32_t val = 0x0;
1621 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1622
1623 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1624 val |= EDP_PSR_LINK_STANDBY;
1625 val |= EDP_PSR_TP2_TP3_TIME_0us;
1626 val |= EDP_PSR_TP1_TIME_0us;
1627 val |= EDP_PSR_SKIP_AUX_EXIT;
1628 } else
1629 val |= EDP_PSR_LINK_DISABLE;
1630
1631 I915_WRITE(EDP_PSR_CTL(dev), val |
1632 IS_BROADWELL(dev) ? 0 : link_entry_time |
1633 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1634 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1635 EDP_PSR_ENABLE);
1636 }
1637
1638 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1639 {
1640 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1641 struct drm_device *dev = dig_port->base.base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 struct drm_crtc *crtc = dig_port->base.base.crtc;
1644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1645 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1646 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1647
1648 dev_priv->psr.source_ok = false;
1649
1650 if (!HAS_PSR(dev)) {
1651 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1652 return false;
1653 }
1654
1655 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1656 (dig_port->port != PORT_A)) {
1657 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1658 return false;
1659 }
1660
1661 if (!i915_enable_psr) {
1662 DRM_DEBUG_KMS("PSR disable by flag\n");
1663 return false;
1664 }
1665
1666 crtc = dig_port->base.base.crtc;
1667 if (crtc == NULL) {
1668 DRM_DEBUG_KMS("crtc not active for PSR\n");
1669 return false;
1670 }
1671
1672 intel_crtc = to_intel_crtc(crtc);
1673 if (!intel_crtc_active(crtc)) {
1674 DRM_DEBUG_KMS("crtc not active for PSR\n");
1675 return false;
1676 }
1677
1678 obj = to_intel_framebuffer(crtc->fb)->obj;
1679 if (obj->tiling_mode != I915_TILING_X ||
1680 obj->fence_reg == I915_FENCE_REG_NONE) {
1681 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1682 return false;
1683 }
1684
1685 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1686 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1687 return false;
1688 }
1689
1690 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1691 S3D_ENABLE) {
1692 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1693 return false;
1694 }
1695
1696 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1697 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1698 return false;
1699 }
1700
1701 dev_priv->psr.source_ok = true;
1702 return true;
1703 }
1704
1705 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1706 {
1707 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1708
1709 if (!intel_edp_psr_match_conditions(intel_dp) ||
1710 intel_edp_is_psr_enabled(dev))
1711 return;
1712
1713 /* Setup PSR once */
1714 intel_edp_psr_setup(intel_dp);
1715
1716 /* Enable PSR on the panel */
1717 intel_edp_psr_enable_sink(intel_dp);
1718
1719 /* Enable PSR on the host */
1720 intel_edp_psr_enable_source(intel_dp);
1721 }
1722
1723 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1724 {
1725 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1726
1727 if (intel_edp_psr_match_conditions(intel_dp) &&
1728 !intel_edp_is_psr_enabled(dev))
1729 intel_edp_psr_do_enable(intel_dp);
1730 }
1731
1732 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1733 {
1734 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1735 struct drm_i915_private *dev_priv = dev->dev_private;
1736
1737 if (!intel_edp_is_psr_enabled(dev))
1738 return;
1739
1740 I915_WRITE(EDP_PSR_CTL(dev),
1741 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1742
1743 /* Wait till PSR is idle */
1744 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1745 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1746 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1747 }
1748
1749 void intel_edp_psr_update(struct drm_device *dev)
1750 {
1751 struct intel_encoder *encoder;
1752 struct intel_dp *intel_dp = NULL;
1753
1754 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1755 if (encoder->type == INTEL_OUTPUT_EDP) {
1756 intel_dp = enc_to_intel_dp(&encoder->base);
1757
1758 if (!is_edp_psr(dev))
1759 return;
1760
1761 if (!intel_edp_psr_match_conditions(intel_dp))
1762 intel_edp_psr_disable(intel_dp);
1763 else
1764 if (!intel_edp_is_psr_enabled(dev))
1765 intel_edp_psr_do_enable(intel_dp);
1766 }
1767 }
1768
1769 static void intel_disable_dp(struct intel_encoder *encoder)
1770 {
1771 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1772 enum port port = dp_to_dig_port(intel_dp)->port;
1773 struct drm_device *dev = encoder->base.dev;
1774
1775 /* Make sure the panel is off before trying to change the mode. But also
1776 * ensure that we have vdd while we switch off the panel. */
1777 ironlake_edp_panel_vdd_on(intel_dp);
1778 ironlake_edp_backlight_off(intel_dp);
1779 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1780 ironlake_edp_panel_off(intel_dp);
1781
1782 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1783 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1784 intel_dp_link_down(intel_dp);
1785 }
1786
1787 static void intel_post_disable_dp(struct intel_encoder *encoder)
1788 {
1789 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1790 enum port port = dp_to_dig_port(intel_dp)->port;
1791 struct drm_device *dev = encoder->base.dev;
1792
1793 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1794 intel_dp_link_down(intel_dp);
1795 if (!IS_VALLEYVIEW(dev))
1796 ironlake_edp_pll_off(intel_dp);
1797 }
1798 }
1799
1800 static void intel_enable_dp(struct intel_encoder *encoder)
1801 {
1802 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1803 struct drm_device *dev = encoder->base.dev;
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1806
1807 if (WARN_ON(dp_reg & DP_PORT_EN))
1808 return;
1809
1810 ironlake_edp_panel_vdd_on(intel_dp);
1811 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1812 intel_dp_start_link_train(intel_dp);
1813 ironlake_edp_panel_on(intel_dp);
1814 ironlake_edp_panel_vdd_off(intel_dp, true);
1815 intel_dp_complete_link_train(intel_dp);
1816 intel_dp_stop_link_train(intel_dp);
1817 }
1818
1819 static void g4x_enable_dp(struct intel_encoder *encoder)
1820 {
1821 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1822
1823 intel_enable_dp(encoder);
1824 ironlake_edp_backlight_on(intel_dp);
1825 }
1826
1827 static void vlv_enable_dp(struct intel_encoder *encoder)
1828 {
1829 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1830
1831 ironlake_edp_backlight_on(intel_dp);
1832 }
1833
1834 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1835 {
1836 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1837 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1838
1839 if (dport->port == PORT_A)
1840 ironlake_edp_pll_on(intel_dp);
1841 }
1842
1843 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1844 {
1845 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1846 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1847 struct drm_device *dev = encoder->base.dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
1849 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1850 enum dpio_channel port = vlv_dport_to_channel(dport);
1851 int pipe = intel_crtc->pipe;
1852 struct edp_power_seq power_seq;
1853 u32 val;
1854
1855 mutex_lock(&dev_priv->dpio_lock);
1856
1857 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1858 val = 0;
1859 if (pipe)
1860 val |= (1<<21);
1861 else
1862 val &= ~(1<<21);
1863 val |= 0x001000c4;
1864 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1865 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1866 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1867
1868 mutex_unlock(&dev_priv->dpio_lock);
1869
1870 /* init power sequencer on this pipe and port */
1871 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1872 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1873 &power_seq);
1874
1875 intel_enable_dp(encoder);
1876
1877 vlv_wait_port_ready(dev_priv, dport);
1878 }
1879
1880 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1881 {
1882 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1883 struct drm_device *dev = encoder->base.dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_crtc *intel_crtc =
1886 to_intel_crtc(encoder->base.crtc);
1887 enum dpio_channel port = vlv_dport_to_channel(dport);
1888 int pipe = intel_crtc->pipe;
1889
1890 /* Program Tx lane resets to default */
1891 mutex_lock(&dev_priv->dpio_lock);
1892 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1893 DPIO_PCS_TX_LANE2_RESET |
1894 DPIO_PCS_TX_LANE1_RESET);
1895 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1896 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1897 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1898 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1899 DPIO_PCS_CLK_SOFT_RESET);
1900
1901 /* Fix up inter-pair skew failure */
1902 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1903 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1904 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1905 mutex_unlock(&dev_priv->dpio_lock);
1906 }
1907
1908 /*
1909 * Native read with retry for link status and receiver capability reads for
1910 * cases where the sink may still be asleep.
1911 */
1912 static bool
1913 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1914 uint8_t *recv, int recv_bytes)
1915 {
1916 int ret, i;
1917
1918 /*
1919 * Sinks are *supposed* to come up within 1ms from an off state,
1920 * but we're also supposed to retry 3 times per the spec.
1921 */
1922 for (i = 0; i < 3; i++) {
1923 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1924 recv_bytes);
1925 if (ret == recv_bytes)
1926 return true;
1927 msleep(1);
1928 }
1929
1930 return false;
1931 }
1932
1933 /*
1934 * Fetch AUX CH registers 0x202 - 0x207 which contain
1935 * link status information
1936 */
1937 static bool
1938 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1939 {
1940 return intel_dp_aux_native_read_retry(intel_dp,
1941 DP_LANE0_1_STATUS,
1942 link_status,
1943 DP_LINK_STATUS_SIZE);
1944 }
1945
1946 /*
1947 * These are source-specific values; current Intel hardware supports
1948 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1949 */
1950
1951 static uint8_t
1952 intel_dp_voltage_max(struct intel_dp *intel_dp)
1953 {
1954 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1955 enum port port = dp_to_dig_port(intel_dp)->port;
1956
1957 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1958 return DP_TRAIN_VOLTAGE_SWING_1200;
1959 else if (IS_GEN7(dev) && port == PORT_A)
1960 return DP_TRAIN_VOLTAGE_SWING_800;
1961 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1962 return DP_TRAIN_VOLTAGE_SWING_1200;
1963 else
1964 return DP_TRAIN_VOLTAGE_SWING_800;
1965 }
1966
1967 static uint8_t
1968 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1969 {
1970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1971 enum port port = dp_to_dig_port(intel_dp)->port;
1972
1973 if (IS_BROADWELL(dev)) {
1974 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1975 case DP_TRAIN_VOLTAGE_SWING_400:
1976 case DP_TRAIN_VOLTAGE_SWING_600:
1977 return DP_TRAIN_PRE_EMPHASIS_6;
1978 case DP_TRAIN_VOLTAGE_SWING_800:
1979 return DP_TRAIN_PRE_EMPHASIS_3_5;
1980 case DP_TRAIN_VOLTAGE_SWING_1200:
1981 default:
1982 return DP_TRAIN_PRE_EMPHASIS_0;
1983 }
1984 } else if (IS_HASWELL(dev)) {
1985 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1986 case DP_TRAIN_VOLTAGE_SWING_400:
1987 return DP_TRAIN_PRE_EMPHASIS_9_5;
1988 case DP_TRAIN_VOLTAGE_SWING_600:
1989 return DP_TRAIN_PRE_EMPHASIS_6;
1990 case DP_TRAIN_VOLTAGE_SWING_800:
1991 return DP_TRAIN_PRE_EMPHASIS_3_5;
1992 case DP_TRAIN_VOLTAGE_SWING_1200:
1993 default:
1994 return DP_TRAIN_PRE_EMPHASIS_0;
1995 }
1996 } else if (IS_VALLEYVIEW(dev)) {
1997 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1998 case DP_TRAIN_VOLTAGE_SWING_400:
1999 return DP_TRAIN_PRE_EMPHASIS_9_5;
2000 case DP_TRAIN_VOLTAGE_SWING_600:
2001 return DP_TRAIN_PRE_EMPHASIS_6;
2002 case DP_TRAIN_VOLTAGE_SWING_800:
2003 return DP_TRAIN_PRE_EMPHASIS_3_5;
2004 case DP_TRAIN_VOLTAGE_SWING_1200:
2005 default:
2006 return DP_TRAIN_PRE_EMPHASIS_0;
2007 }
2008 } else if (IS_GEN7(dev) && port == PORT_A) {
2009 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2010 case DP_TRAIN_VOLTAGE_SWING_400:
2011 return DP_TRAIN_PRE_EMPHASIS_6;
2012 case DP_TRAIN_VOLTAGE_SWING_600:
2013 case DP_TRAIN_VOLTAGE_SWING_800:
2014 return DP_TRAIN_PRE_EMPHASIS_3_5;
2015 default:
2016 return DP_TRAIN_PRE_EMPHASIS_0;
2017 }
2018 } else {
2019 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2020 case DP_TRAIN_VOLTAGE_SWING_400:
2021 return DP_TRAIN_PRE_EMPHASIS_6;
2022 case DP_TRAIN_VOLTAGE_SWING_600:
2023 return DP_TRAIN_PRE_EMPHASIS_6;
2024 case DP_TRAIN_VOLTAGE_SWING_800:
2025 return DP_TRAIN_PRE_EMPHASIS_3_5;
2026 case DP_TRAIN_VOLTAGE_SWING_1200:
2027 default:
2028 return DP_TRAIN_PRE_EMPHASIS_0;
2029 }
2030 }
2031 }
2032
2033 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2034 {
2035 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2037 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2038 struct intel_crtc *intel_crtc =
2039 to_intel_crtc(dport->base.base.crtc);
2040 unsigned long demph_reg_value, preemph_reg_value,
2041 uniqtranscale_reg_value;
2042 uint8_t train_set = intel_dp->train_set[0];
2043 enum dpio_channel port = vlv_dport_to_channel(dport);
2044 int pipe = intel_crtc->pipe;
2045
2046 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2047 case DP_TRAIN_PRE_EMPHASIS_0:
2048 preemph_reg_value = 0x0004000;
2049 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2050 case DP_TRAIN_VOLTAGE_SWING_400:
2051 demph_reg_value = 0x2B405555;
2052 uniqtranscale_reg_value = 0x552AB83A;
2053 break;
2054 case DP_TRAIN_VOLTAGE_SWING_600:
2055 demph_reg_value = 0x2B404040;
2056 uniqtranscale_reg_value = 0x5548B83A;
2057 break;
2058 case DP_TRAIN_VOLTAGE_SWING_800:
2059 demph_reg_value = 0x2B245555;
2060 uniqtranscale_reg_value = 0x5560B83A;
2061 break;
2062 case DP_TRAIN_VOLTAGE_SWING_1200:
2063 demph_reg_value = 0x2B405555;
2064 uniqtranscale_reg_value = 0x5598DA3A;
2065 break;
2066 default:
2067 return 0;
2068 }
2069 break;
2070 case DP_TRAIN_PRE_EMPHASIS_3_5:
2071 preemph_reg_value = 0x0002000;
2072 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2073 case DP_TRAIN_VOLTAGE_SWING_400:
2074 demph_reg_value = 0x2B404040;
2075 uniqtranscale_reg_value = 0x5552B83A;
2076 break;
2077 case DP_TRAIN_VOLTAGE_SWING_600:
2078 demph_reg_value = 0x2B404848;
2079 uniqtranscale_reg_value = 0x5580B83A;
2080 break;
2081 case DP_TRAIN_VOLTAGE_SWING_800:
2082 demph_reg_value = 0x2B404040;
2083 uniqtranscale_reg_value = 0x55ADDA3A;
2084 break;
2085 default:
2086 return 0;
2087 }
2088 break;
2089 case DP_TRAIN_PRE_EMPHASIS_6:
2090 preemph_reg_value = 0x0000000;
2091 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2092 case DP_TRAIN_VOLTAGE_SWING_400:
2093 demph_reg_value = 0x2B305555;
2094 uniqtranscale_reg_value = 0x5570B83A;
2095 break;
2096 case DP_TRAIN_VOLTAGE_SWING_600:
2097 demph_reg_value = 0x2B2B4040;
2098 uniqtranscale_reg_value = 0x55ADDA3A;
2099 break;
2100 default:
2101 return 0;
2102 }
2103 break;
2104 case DP_TRAIN_PRE_EMPHASIS_9_5:
2105 preemph_reg_value = 0x0006000;
2106 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2107 case DP_TRAIN_VOLTAGE_SWING_400:
2108 demph_reg_value = 0x1B405555;
2109 uniqtranscale_reg_value = 0x55ADDA3A;
2110 break;
2111 default:
2112 return 0;
2113 }
2114 break;
2115 default:
2116 return 0;
2117 }
2118
2119 mutex_lock(&dev_priv->dpio_lock);
2120 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2121 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2122 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2123 uniqtranscale_reg_value);
2124 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2125 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2126 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2127 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2128 mutex_unlock(&dev_priv->dpio_lock);
2129
2130 return 0;
2131 }
2132
2133 static void
2134 intel_get_adjust_train(struct intel_dp *intel_dp,
2135 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2136 {
2137 uint8_t v = 0;
2138 uint8_t p = 0;
2139 int lane;
2140 uint8_t voltage_max;
2141 uint8_t preemph_max;
2142
2143 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2144 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2145 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2146
2147 if (this_v > v)
2148 v = this_v;
2149 if (this_p > p)
2150 p = this_p;
2151 }
2152
2153 voltage_max = intel_dp_voltage_max(intel_dp);
2154 if (v >= voltage_max)
2155 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2156
2157 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2158 if (p >= preemph_max)
2159 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2160
2161 for (lane = 0; lane < 4; lane++)
2162 intel_dp->train_set[lane] = v | p;
2163 }
2164
2165 static uint32_t
2166 intel_gen4_signal_levels(uint8_t train_set)
2167 {
2168 uint32_t signal_levels = 0;
2169
2170 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2171 case DP_TRAIN_VOLTAGE_SWING_400:
2172 default:
2173 signal_levels |= DP_VOLTAGE_0_4;
2174 break;
2175 case DP_TRAIN_VOLTAGE_SWING_600:
2176 signal_levels |= DP_VOLTAGE_0_6;
2177 break;
2178 case DP_TRAIN_VOLTAGE_SWING_800:
2179 signal_levels |= DP_VOLTAGE_0_8;
2180 break;
2181 case DP_TRAIN_VOLTAGE_SWING_1200:
2182 signal_levels |= DP_VOLTAGE_1_2;
2183 break;
2184 }
2185 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2186 case DP_TRAIN_PRE_EMPHASIS_0:
2187 default:
2188 signal_levels |= DP_PRE_EMPHASIS_0;
2189 break;
2190 case DP_TRAIN_PRE_EMPHASIS_3_5:
2191 signal_levels |= DP_PRE_EMPHASIS_3_5;
2192 break;
2193 case DP_TRAIN_PRE_EMPHASIS_6:
2194 signal_levels |= DP_PRE_EMPHASIS_6;
2195 break;
2196 case DP_TRAIN_PRE_EMPHASIS_9_5:
2197 signal_levels |= DP_PRE_EMPHASIS_9_5;
2198 break;
2199 }
2200 return signal_levels;
2201 }
2202
2203 /* Gen6's DP voltage swing and pre-emphasis control */
2204 static uint32_t
2205 intel_gen6_edp_signal_levels(uint8_t train_set)
2206 {
2207 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2208 DP_TRAIN_PRE_EMPHASIS_MASK);
2209 switch (signal_levels) {
2210 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2211 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2212 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2213 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2214 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2215 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2216 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2217 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2218 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2219 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2220 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2221 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2222 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2223 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2224 default:
2225 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2226 "0x%x\n", signal_levels);
2227 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2228 }
2229 }
2230
2231 /* Gen7's DP voltage swing and pre-emphasis control */
2232 static uint32_t
2233 intel_gen7_edp_signal_levels(uint8_t train_set)
2234 {
2235 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2236 DP_TRAIN_PRE_EMPHASIS_MASK);
2237 switch (signal_levels) {
2238 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2239 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2240 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2241 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2242 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2243 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2244
2245 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2246 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2247 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2248 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2249
2250 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2251 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2252 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2253 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2254
2255 default:
2256 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2257 "0x%x\n", signal_levels);
2258 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2259 }
2260 }
2261
2262 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2263 static uint32_t
2264 intel_hsw_signal_levels(uint8_t train_set)
2265 {
2266 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2267 DP_TRAIN_PRE_EMPHASIS_MASK);
2268 switch (signal_levels) {
2269 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2270 return DDI_BUF_EMP_400MV_0DB_HSW;
2271 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2272 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2273 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2274 return DDI_BUF_EMP_400MV_6DB_HSW;
2275 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2276 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2277
2278 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2279 return DDI_BUF_EMP_600MV_0DB_HSW;
2280 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2281 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2282 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2283 return DDI_BUF_EMP_600MV_6DB_HSW;
2284
2285 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2286 return DDI_BUF_EMP_800MV_0DB_HSW;
2287 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2288 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2289 default:
2290 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2291 "0x%x\n", signal_levels);
2292 return DDI_BUF_EMP_400MV_0DB_HSW;
2293 }
2294 }
2295
2296 static uint32_t
2297 intel_bdw_signal_levels(uint8_t train_set)
2298 {
2299 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2300 DP_TRAIN_PRE_EMPHASIS_MASK);
2301 switch (signal_levels) {
2302 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2303 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2305 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2306 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2307 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2308
2309 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2310 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2311 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2312 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2313 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2314 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2315
2316 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2317 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2318 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2319 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2320
2321 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2322 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2323
2324 default:
2325 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2326 "0x%x\n", signal_levels);
2327 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2328 }
2329 }
2330
2331 /* Properly updates "DP" with the correct signal levels. */
2332 static void
2333 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2334 {
2335 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2336 enum port port = intel_dig_port->port;
2337 struct drm_device *dev = intel_dig_port->base.base.dev;
2338 uint32_t signal_levels, mask;
2339 uint8_t train_set = intel_dp->train_set[0];
2340
2341 if (IS_BROADWELL(dev)) {
2342 signal_levels = intel_bdw_signal_levels(train_set);
2343 mask = DDI_BUF_EMP_MASK;
2344 } else if (IS_HASWELL(dev)) {
2345 signal_levels = intel_hsw_signal_levels(train_set);
2346 mask = DDI_BUF_EMP_MASK;
2347 } else if (IS_VALLEYVIEW(dev)) {
2348 signal_levels = intel_vlv_signal_levels(intel_dp);
2349 mask = 0;
2350 } else if (IS_GEN7(dev) && port == PORT_A) {
2351 signal_levels = intel_gen7_edp_signal_levels(train_set);
2352 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2353 } else if (IS_GEN6(dev) && port == PORT_A) {
2354 signal_levels = intel_gen6_edp_signal_levels(train_set);
2355 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2356 } else {
2357 signal_levels = intel_gen4_signal_levels(train_set);
2358 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2359 }
2360
2361 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2362
2363 *DP = (*DP & ~mask) | signal_levels;
2364 }
2365
2366 static bool
2367 intel_dp_set_link_train(struct intel_dp *intel_dp,
2368 uint32_t *DP,
2369 uint8_t dp_train_pat)
2370 {
2371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2372 struct drm_device *dev = intel_dig_port->base.base.dev;
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 enum port port = intel_dig_port->port;
2375 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2376 int ret, len;
2377
2378 if (HAS_DDI(dev)) {
2379 uint32_t temp = I915_READ(DP_TP_CTL(port));
2380
2381 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2382 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2383 else
2384 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2385
2386 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2387 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2388 case DP_TRAINING_PATTERN_DISABLE:
2389 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2390
2391 break;
2392 case DP_TRAINING_PATTERN_1:
2393 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2394 break;
2395 case DP_TRAINING_PATTERN_2:
2396 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2397 break;
2398 case DP_TRAINING_PATTERN_3:
2399 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2400 break;
2401 }
2402 I915_WRITE(DP_TP_CTL(port), temp);
2403
2404 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2405 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2406
2407 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2408 case DP_TRAINING_PATTERN_DISABLE:
2409 *DP |= DP_LINK_TRAIN_OFF_CPT;
2410 break;
2411 case DP_TRAINING_PATTERN_1:
2412 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2413 break;
2414 case DP_TRAINING_PATTERN_2:
2415 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2416 break;
2417 case DP_TRAINING_PATTERN_3:
2418 DRM_ERROR("DP training pattern 3 not supported\n");
2419 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2420 break;
2421 }
2422
2423 } else {
2424 *DP &= ~DP_LINK_TRAIN_MASK;
2425
2426 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2427 case DP_TRAINING_PATTERN_DISABLE:
2428 *DP |= DP_LINK_TRAIN_OFF;
2429 break;
2430 case DP_TRAINING_PATTERN_1:
2431 *DP |= DP_LINK_TRAIN_PAT_1;
2432 break;
2433 case DP_TRAINING_PATTERN_2:
2434 *DP |= DP_LINK_TRAIN_PAT_2;
2435 break;
2436 case DP_TRAINING_PATTERN_3:
2437 DRM_ERROR("DP training pattern 3 not supported\n");
2438 *DP |= DP_LINK_TRAIN_PAT_2;
2439 break;
2440 }
2441 }
2442
2443 I915_WRITE(intel_dp->output_reg, *DP);
2444 POSTING_READ(intel_dp->output_reg);
2445
2446 buf[0] = dp_train_pat;
2447 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2448 DP_TRAINING_PATTERN_DISABLE) {
2449 /* don't write DP_TRAINING_LANEx_SET on disable */
2450 len = 1;
2451 } else {
2452 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2453 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2454 len = intel_dp->lane_count + 1;
2455 }
2456
2457 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2458 buf, len);
2459
2460 return ret == len;
2461 }
2462
2463 static bool
2464 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2465 uint8_t dp_train_pat)
2466 {
2467 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2468 intel_dp_set_signal_levels(intel_dp, DP);
2469 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2470 }
2471
2472 static bool
2473 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2474 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2475 {
2476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2477 struct drm_device *dev = intel_dig_port->base.base.dev;
2478 struct drm_i915_private *dev_priv = dev->dev_private;
2479 int ret;
2480
2481 intel_get_adjust_train(intel_dp, link_status);
2482 intel_dp_set_signal_levels(intel_dp, DP);
2483
2484 I915_WRITE(intel_dp->output_reg, *DP);
2485 POSTING_READ(intel_dp->output_reg);
2486
2487 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2488 intel_dp->train_set,
2489 intel_dp->lane_count);
2490
2491 return ret == intel_dp->lane_count;
2492 }
2493
2494 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2495 {
2496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2497 struct drm_device *dev = intel_dig_port->base.base.dev;
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 enum port port = intel_dig_port->port;
2500 uint32_t val;
2501
2502 if (!HAS_DDI(dev))
2503 return;
2504
2505 val = I915_READ(DP_TP_CTL(port));
2506 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2507 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2508 I915_WRITE(DP_TP_CTL(port), val);
2509
2510 /*
2511 * On PORT_A we can have only eDP in SST mode. There the only reason
2512 * we need to set idle transmission mode is to work around a HW issue
2513 * where we enable the pipe while not in idle link-training mode.
2514 * In this case there is requirement to wait for a minimum number of
2515 * idle patterns to be sent.
2516 */
2517 if (port == PORT_A)
2518 return;
2519
2520 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2521 1))
2522 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2523 }
2524
2525 /* Enable corresponding port and start training pattern 1 */
2526 void
2527 intel_dp_start_link_train(struct intel_dp *intel_dp)
2528 {
2529 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2530 struct drm_device *dev = encoder->dev;
2531 int i;
2532 uint8_t voltage;
2533 int voltage_tries, loop_tries;
2534 uint32_t DP = intel_dp->DP;
2535 uint8_t link_config[2];
2536
2537 if (HAS_DDI(dev))
2538 intel_ddi_prepare_link_retrain(encoder);
2539
2540 /* Write the link configuration data */
2541 link_config[0] = intel_dp->link_bw;
2542 link_config[1] = intel_dp->lane_count;
2543 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2544 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2545 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2546
2547 link_config[0] = 0;
2548 link_config[1] = DP_SET_ANSI_8B10B;
2549 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2550
2551 DP |= DP_PORT_EN;
2552
2553 /* clock recovery */
2554 if (!intel_dp_reset_link_train(intel_dp, &DP,
2555 DP_TRAINING_PATTERN_1 |
2556 DP_LINK_SCRAMBLING_DISABLE)) {
2557 DRM_ERROR("failed to enable link training\n");
2558 return;
2559 }
2560
2561 voltage = 0xff;
2562 voltage_tries = 0;
2563 loop_tries = 0;
2564 for (;;) {
2565 uint8_t link_status[DP_LINK_STATUS_SIZE];
2566
2567 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2568 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2569 DRM_ERROR("failed to get link status\n");
2570 break;
2571 }
2572
2573 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2574 DRM_DEBUG_KMS("clock recovery OK\n");
2575 break;
2576 }
2577
2578 /* Check to see if we've tried the max voltage */
2579 for (i = 0; i < intel_dp->lane_count; i++)
2580 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2581 break;
2582 if (i == intel_dp->lane_count) {
2583 ++loop_tries;
2584 if (loop_tries == 5) {
2585 DRM_ERROR("too many full retries, give up\n");
2586 break;
2587 }
2588 intel_dp_reset_link_train(intel_dp, &DP,
2589 DP_TRAINING_PATTERN_1 |
2590 DP_LINK_SCRAMBLING_DISABLE);
2591 voltage_tries = 0;
2592 continue;
2593 }
2594
2595 /* Check to see if we've tried the same voltage 5 times */
2596 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2597 ++voltage_tries;
2598 if (voltage_tries == 5) {
2599 DRM_ERROR("too many voltage retries, give up\n");
2600 break;
2601 }
2602 } else
2603 voltage_tries = 0;
2604 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2605
2606 /* Update training set as requested by target */
2607 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2608 DRM_ERROR("failed to update link training\n");
2609 break;
2610 }
2611 }
2612
2613 intel_dp->DP = DP;
2614 }
2615
2616 void
2617 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2618 {
2619 bool channel_eq = false;
2620 int tries, cr_tries;
2621 uint32_t DP = intel_dp->DP;
2622
2623 /* channel equalization */
2624 if (!intel_dp_set_link_train(intel_dp, &DP,
2625 DP_TRAINING_PATTERN_2 |
2626 DP_LINK_SCRAMBLING_DISABLE)) {
2627 DRM_ERROR("failed to start channel equalization\n");
2628 return;
2629 }
2630
2631 tries = 0;
2632 cr_tries = 0;
2633 channel_eq = false;
2634 for (;;) {
2635 uint8_t link_status[DP_LINK_STATUS_SIZE];
2636
2637 if (cr_tries > 5) {
2638 DRM_ERROR("failed to train DP, aborting\n");
2639 intel_dp_link_down(intel_dp);
2640 break;
2641 }
2642
2643 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2644 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2645 DRM_ERROR("failed to get link status\n");
2646 break;
2647 }
2648
2649 /* Make sure clock is still ok */
2650 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2651 intel_dp_start_link_train(intel_dp);
2652 intel_dp_set_link_train(intel_dp, &DP,
2653 DP_TRAINING_PATTERN_2 |
2654 DP_LINK_SCRAMBLING_DISABLE);
2655 cr_tries++;
2656 continue;
2657 }
2658
2659 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2660 channel_eq = true;
2661 break;
2662 }
2663
2664 /* Try 5 times, then try clock recovery if that fails */
2665 if (tries > 5) {
2666 intel_dp_link_down(intel_dp);
2667 intel_dp_start_link_train(intel_dp);
2668 intel_dp_set_link_train(intel_dp, &DP,
2669 DP_TRAINING_PATTERN_2 |
2670 DP_LINK_SCRAMBLING_DISABLE);
2671 tries = 0;
2672 cr_tries++;
2673 continue;
2674 }
2675
2676 /* Update training set as requested by target */
2677 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2678 DRM_ERROR("failed to update link training\n");
2679 break;
2680 }
2681 ++tries;
2682 }
2683
2684 intel_dp_set_idle_link_train(intel_dp);
2685
2686 intel_dp->DP = DP;
2687
2688 if (channel_eq)
2689 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2690
2691 }
2692
2693 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2694 {
2695 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2696 DP_TRAINING_PATTERN_DISABLE);
2697 }
2698
2699 static void
2700 intel_dp_link_down(struct intel_dp *intel_dp)
2701 {
2702 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2703 enum port port = intel_dig_port->port;
2704 struct drm_device *dev = intel_dig_port->base.base.dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc =
2707 to_intel_crtc(intel_dig_port->base.base.crtc);
2708 uint32_t DP = intel_dp->DP;
2709
2710 /*
2711 * DDI code has a strict mode set sequence and we should try to respect
2712 * it, otherwise we might hang the machine in many different ways. So we
2713 * really should be disabling the port only on a complete crtc_disable
2714 * sequence. This function is just called under two conditions on DDI
2715 * code:
2716 * - Link train failed while doing crtc_enable, and on this case we
2717 * really should respect the mode set sequence and wait for a
2718 * crtc_disable.
2719 * - Someone turned the monitor off and intel_dp_check_link_status
2720 * called us. We don't need to disable the whole port on this case, so
2721 * when someone turns the monitor on again,
2722 * intel_ddi_prepare_link_retrain will take care of redoing the link
2723 * train.
2724 */
2725 if (HAS_DDI(dev))
2726 return;
2727
2728 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2729 return;
2730
2731 DRM_DEBUG_KMS("\n");
2732
2733 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2734 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2735 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2736 } else {
2737 DP &= ~DP_LINK_TRAIN_MASK;
2738 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2739 }
2740 POSTING_READ(intel_dp->output_reg);
2741
2742 /* We don't really know why we're doing this */
2743 intel_wait_for_vblank(dev, intel_crtc->pipe);
2744
2745 if (HAS_PCH_IBX(dev) &&
2746 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2747 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2748
2749 /* Hardware workaround: leaving our transcoder select
2750 * set to transcoder B while it's off will prevent the
2751 * corresponding HDMI output on transcoder A.
2752 *
2753 * Combine this with another hardware workaround:
2754 * transcoder select bit can only be cleared while the
2755 * port is enabled.
2756 */
2757 DP &= ~DP_PIPEB_SELECT;
2758 I915_WRITE(intel_dp->output_reg, DP);
2759
2760 /* Changes to enable or select take place the vblank
2761 * after being written.
2762 */
2763 if (WARN_ON(crtc == NULL)) {
2764 /* We should never try to disable a port without a crtc
2765 * attached. For paranoia keep the code around for a
2766 * bit. */
2767 POSTING_READ(intel_dp->output_reg);
2768 msleep(50);
2769 } else
2770 intel_wait_for_vblank(dev, intel_crtc->pipe);
2771 }
2772
2773 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2774 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2775 POSTING_READ(intel_dp->output_reg);
2776 msleep(intel_dp->panel_power_down_delay);
2777 }
2778
2779 static bool
2780 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2781 {
2782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2783 struct drm_device *dev = dig_port->base.base.dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785
2786 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2787
2788 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2789 sizeof(intel_dp->dpcd)) == 0)
2790 return false; /* aux transfer failed */
2791
2792 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2793 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2794 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2795
2796 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2797 return false; /* DPCD not present */
2798
2799 /* Check if the panel supports PSR */
2800 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2801 if (is_edp(intel_dp)) {
2802 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2803 intel_dp->psr_dpcd,
2804 sizeof(intel_dp->psr_dpcd));
2805 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2806 dev_priv->psr.sink_support = true;
2807 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2808 }
2809 }
2810
2811 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2812 DP_DWN_STRM_PORT_PRESENT))
2813 return true; /* native DP sink */
2814
2815 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2816 return true; /* no per-port downstream info */
2817
2818 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2819 intel_dp->downstream_ports,
2820 DP_MAX_DOWNSTREAM_PORTS) == 0)
2821 return false; /* downstream port status fetch failed */
2822
2823 return true;
2824 }
2825
2826 static void
2827 intel_dp_probe_oui(struct intel_dp *intel_dp)
2828 {
2829 u8 buf[3];
2830
2831 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2832 return;
2833
2834 ironlake_edp_panel_vdd_on(intel_dp);
2835
2836 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2837 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2838 buf[0], buf[1], buf[2]);
2839
2840 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2841 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2842 buf[0], buf[1], buf[2]);
2843
2844 ironlake_edp_panel_vdd_off(intel_dp, false);
2845 }
2846
2847 static bool
2848 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2849 {
2850 int ret;
2851
2852 ret = intel_dp_aux_native_read_retry(intel_dp,
2853 DP_DEVICE_SERVICE_IRQ_VECTOR,
2854 sink_irq_vector, 1);
2855 if (!ret)
2856 return false;
2857
2858 return true;
2859 }
2860
2861 static void
2862 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2863 {
2864 /* NAK by default */
2865 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2866 }
2867
2868 /*
2869 * According to DP spec
2870 * 5.1.2:
2871 * 1. Read DPCD
2872 * 2. Configure link according to Receiver Capabilities
2873 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2874 * 4. Check link status on receipt of hot-plug interrupt
2875 */
2876
2877 void
2878 intel_dp_check_link_status(struct intel_dp *intel_dp)
2879 {
2880 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2881 u8 sink_irq_vector;
2882 u8 link_status[DP_LINK_STATUS_SIZE];
2883
2884 if (!intel_encoder->connectors_active)
2885 return;
2886
2887 if (WARN_ON(!intel_encoder->base.crtc))
2888 return;
2889
2890 /* Try to read receiver status if the link appears to be up */
2891 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2892 intel_dp_link_down(intel_dp);
2893 return;
2894 }
2895
2896 /* Now read the DPCD to see if it's actually running */
2897 if (!intel_dp_get_dpcd(intel_dp)) {
2898 intel_dp_link_down(intel_dp);
2899 return;
2900 }
2901
2902 /* Try to read the source of the interrupt */
2903 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2904 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2905 /* Clear interrupt source */
2906 intel_dp_aux_native_write_1(intel_dp,
2907 DP_DEVICE_SERVICE_IRQ_VECTOR,
2908 sink_irq_vector);
2909
2910 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2911 intel_dp_handle_test_request(intel_dp);
2912 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2913 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2914 }
2915
2916 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2917 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2918 drm_get_encoder_name(&intel_encoder->base));
2919 intel_dp_start_link_train(intel_dp);
2920 intel_dp_complete_link_train(intel_dp);
2921 intel_dp_stop_link_train(intel_dp);
2922 }
2923 }
2924
2925 /* XXX this is probably wrong for multiple downstream ports */
2926 static enum drm_connector_status
2927 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2928 {
2929 uint8_t *dpcd = intel_dp->dpcd;
2930 uint8_t type;
2931
2932 if (!intel_dp_get_dpcd(intel_dp))
2933 return connector_status_disconnected;
2934
2935 /* if there's no downstream port, we're done */
2936 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2937 return connector_status_connected;
2938
2939 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2940 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2941 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2942 uint8_t reg;
2943 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2944 &reg, 1))
2945 return connector_status_unknown;
2946 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2947 : connector_status_disconnected;
2948 }
2949
2950 /* If no HPD, poke DDC gently */
2951 if (drm_probe_ddc(&intel_dp->adapter))
2952 return connector_status_connected;
2953
2954 /* Well we tried, say unknown for unreliable port types */
2955 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2956 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2957 if (type == DP_DS_PORT_TYPE_VGA ||
2958 type == DP_DS_PORT_TYPE_NON_EDID)
2959 return connector_status_unknown;
2960 } else {
2961 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2962 DP_DWN_STRM_PORT_TYPE_MASK;
2963 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2964 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2965 return connector_status_unknown;
2966 }
2967
2968 /* Anything else is out of spec, warn and ignore */
2969 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2970 return connector_status_disconnected;
2971 }
2972
2973 static enum drm_connector_status
2974 ironlake_dp_detect(struct intel_dp *intel_dp)
2975 {
2976 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2977 struct drm_i915_private *dev_priv = dev->dev_private;
2978 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2979 enum drm_connector_status status;
2980
2981 /* Can't disconnect eDP, but you can close the lid... */
2982 if (is_edp(intel_dp)) {
2983 status = intel_panel_detect(dev);
2984 if (status == connector_status_unknown)
2985 status = connector_status_connected;
2986 return status;
2987 }
2988
2989 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2990 return connector_status_disconnected;
2991
2992 return intel_dp_detect_dpcd(intel_dp);
2993 }
2994
2995 static enum drm_connector_status
2996 g4x_dp_detect(struct intel_dp *intel_dp)
2997 {
2998 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3001 uint32_t bit;
3002
3003 /* Can't disconnect eDP, but you can close the lid... */
3004 if (is_edp(intel_dp)) {
3005 enum drm_connector_status status;
3006
3007 status = intel_panel_detect(dev);
3008 if (status == connector_status_unknown)
3009 status = connector_status_connected;
3010 return status;
3011 }
3012
3013 switch (intel_dig_port->port) {
3014 case PORT_B:
3015 bit = PORTB_HOTPLUG_LIVE_STATUS;
3016 break;
3017 case PORT_C:
3018 bit = PORTC_HOTPLUG_LIVE_STATUS;
3019 break;
3020 case PORT_D:
3021 bit = PORTD_HOTPLUG_LIVE_STATUS;
3022 break;
3023 default:
3024 return connector_status_unknown;
3025 }
3026
3027 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3028 return connector_status_disconnected;
3029
3030 return intel_dp_detect_dpcd(intel_dp);
3031 }
3032
3033 static struct edid *
3034 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3035 {
3036 struct intel_connector *intel_connector = to_intel_connector(connector);
3037
3038 /* use cached edid if we have one */
3039 if (intel_connector->edid) {
3040 /* invalid edid */
3041 if (IS_ERR(intel_connector->edid))
3042 return NULL;
3043
3044 return drm_edid_duplicate(intel_connector->edid);
3045 }
3046
3047 return drm_get_edid(connector, adapter);
3048 }
3049
3050 static int
3051 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3052 {
3053 struct intel_connector *intel_connector = to_intel_connector(connector);
3054
3055 /* use cached edid if we have one */
3056 if (intel_connector->edid) {
3057 /* invalid edid */
3058 if (IS_ERR(intel_connector->edid))
3059 return 0;
3060
3061 return intel_connector_update_modes(connector,
3062 intel_connector->edid);
3063 }
3064
3065 return intel_ddc_get_modes(connector, adapter);
3066 }
3067
3068 static enum drm_connector_status
3069 intel_dp_detect(struct drm_connector *connector, bool force)
3070 {
3071 struct intel_dp *intel_dp = intel_attached_dp(connector);
3072 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3073 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3074 struct drm_device *dev = connector->dev;
3075 enum drm_connector_status status;
3076 struct edid *edid = NULL;
3077
3078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3079 connector->base.id, drm_get_connector_name(connector));
3080
3081 intel_dp->has_audio = false;
3082
3083 if (HAS_PCH_SPLIT(dev))
3084 status = ironlake_dp_detect(intel_dp);
3085 else
3086 status = g4x_dp_detect(intel_dp);
3087
3088 if (status != connector_status_connected)
3089 return status;
3090
3091 intel_dp_probe_oui(intel_dp);
3092
3093 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3094 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3095 } else {
3096 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3097 if (edid) {
3098 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3099 kfree(edid);
3100 }
3101 }
3102
3103 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3104 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3105 return connector_status_connected;
3106 }
3107
3108 static int intel_dp_get_modes(struct drm_connector *connector)
3109 {
3110 struct intel_dp *intel_dp = intel_attached_dp(connector);
3111 struct intel_connector *intel_connector = to_intel_connector(connector);
3112 struct drm_device *dev = connector->dev;
3113 int ret;
3114
3115 /* We should parse the EDID data and find out if it has an audio sink
3116 */
3117
3118 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3119 if (ret)
3120 return ret;
3121
3122 /* if eDP has no EDID, fall back to fixed mode */
3123 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3124 struct drm_display_mode *mode;
3125 mode = drm_mode_duplicate(dev,
3126 intel_connector->panel.fixed_mode);
3127 if (mode) {
3128 drm_mode_probed_add(connector, mode);
3129 return 1;
3130 }
3131 }
3132 return 0;
3133 }
3134
3135 static bool
3136 intel_dp_detect_audio(struct drm_connector *connector)
3137 {
3138 struct intel_dp *intel_dp = intel_attached_dp(connector);
3139 struct edid *edid;
3140 bool has_audio = false;
3141
3142 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3143 if (edid) {
3144 has_audio = drm_detect_monitor_audio(edid);
3145 kfree(edid);
3146 }
3147
3148 return has_audio;
3149 }
3150
3151 static int
3152 intel_dp_set_property(struct drm_connector *connector,
3153 struct drm_property *property,
3154 uint64_t val)
3155 {
3156 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3157 struct intel_connector *intel_connector = to_intel_connector(connector);
3158 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3159 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3160 int ret;
3161
3162 ret = drm_object_property_set_value(&connector->base, property, val);
3163 if (ret)
3164 return ret;
3165
3166 if (property == dev_priv->force_audio_property) {
3167 int i = val;
3168 bool has_audio;
3169
3170 if (i == intel_dp->force_audio)
3171 return 0;
3172
3173 intel_dp->force_audio = i;
3174
3175 if (i == HDMI_AUDIO_AUTO)
3176 has_audio = intel_dp_detect_audio(connector);
3177 else
3178 has_audio = (i == HDMI_AUDIO_ON);
3179
3180 if (has_audio == intel_dp->has_audio)
3181 return 0;
3182
3183 intel_dp->has_audio = has_audio;
3184 goto done;
3185 }
3186
3187 if (property == dev_priv->broadcast_rgb_property) {
3188 bool old_auto = intel_dp->color_range_auto;
3189 uint32_t old_range = intel_dp->color_range;
3190
3191 switch (val) {
3192 case INTEL_BROADCAST_RGB_AUTO:
3193 intel_dp->color_range_auto = true;
3194 break;
3195 case INTEL_BROADCAST_RGB_FULL:
3196 intel_dp->color_range_auto = false;
3197 intel_dp->color_range = 0;
3198 break;
3199 case INTEL_BROADCAST_RGB_LIMITED:
3200 intel_dp->color_range_auto = false;
3201 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3202 break;
3203 default:
3204 return -EINVAL;
3205 }
3206
3207 if (old_auto == intel_dp->color_range_auto &&
3208 old_range == intel_dp->color_range)
3209 return 0;
3210
3211 goto done;
3212 }
3213
3214 if (is_edp(intel_dp) &&
3215 property == connector->dev->mode_config.scaling_mode_property) {
3216 if (val == DRM_MODE_SCALE_NONE) {
3217 DRM_DEBUG_KMS("no scaling not supported\n");
3218 return -EINVAL;
3219 }
3220
3221 if (intel_connector->panel.fitting_mode == val) {
3222 /* the eDP scaling property is not changed */
3223 return 0;
3224 }
3225 intel_connector->panel.fitting_mode = val;
3226
3227 goto done;
3228 }
3229
3230 return -EINVAL;
3231
3232 done:
3233 if (intel_encoder->base.crtc)
3234 intel_crtc_restore_mode(intel_encoder->base.crtc);
3235
3236 return 0;
3237 }
3238
3239 static void
3240 intel_dp_connector_destroy(struct drm_connector *connector)
3241 {
3242 struct intel_connector *intel_connector = to_intel_connector(connector);
3243
3244 if (!IS_ERR_OR_NULL(intel_connector->edid))
3245 kfree(intel_connector->edid);
3246
3247 /* Can't call is_edp() since the encoder may have been destroyed
3248 * already. */
3249 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3250 intel_panel_fini(&intel_connector->panel);
3251
3252 drm_connector_cleanup(connector);
3253 kfree(connector);
3254 }
3255
3256 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3257 {
3258 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3259 struct intel_dp *intel_dp = &intel_dig_port->dp;
3260 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3261
3262 i2c_del_adapter(&intel_dp->adapter);
3263 drm_encoder_cleanup(encoder);
3264 if (is_edp(intel_dp)) {
3265 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3266 mutex_lock(&dev->mode_config.mutex);
3267 ironlake_panel_vdd_off_sync(intel_dp);
3268 mutex_unlock(&dev->mode_config.mutex);
3269 }
3270 kfree(intel_dig_port);
3271 }
3272
3273 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3274 .dpms = intel_connector_dpms,
3275 .detect = intel_dp_detect,
3276 .fill_modes = drm_helper_probe_single_connector_modes,
3277 .set_property = intel_dp_set_property,
3278 .destroy = intel_dp_connector_destroy,
3279 };
3280
3281 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3282 .get_modes = intel_dp_get_modes,
3283 .mode_valid = intel_dp_mode_valid,
3284 .best_encoder = intel_best_encoder,
3285 };
3286
3287 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3288 .destroy = intel_dp_encoder_destroy,
3289 };
3290
3291 static void
3292 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3293 {
3294 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3295
3296 intel_dp_check_link_status(intel_dp);
3297 }
3298
3299 /* Return which DP Port should be selected for Transcoder DP control */
3300 int
3301 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3302 {
3303 struct drm_device *dev = crtc->dev;
3304 struct intel_encoder *intel_encoder;
3305 struct intel_dp *intel_dp;
3306
3307 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3308 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3309
3310 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3311 intel_encoder->type == INTEL_OUTPUT_EDP)
3312 return intel_dp->output_reg;
3313 }
3314
3315 return -1;
3316 }
3317
3318 /* check the VBT to see whether the eDP is on DP-D port */
3319 bool intel_dpd_is_edp(struct drm_device *dev)
3320 {
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 union child_device_config *p_child;
3323 int i;
3324
3325 if (!dev_priv->vbt.child_dev_num)
3326 return false;
3327
3328 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3329 p_child = dev_priv->vbt.child_dev + i;
3330
3331 if (p_child->common.dvo_port == PORT_IDPD &&
3332 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3333 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3334 return true;
3335 }
3336 return false;
3337 }
3338
3339 static void
3340 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3341 {
3342 struct intel_connector *intel_connector = to_intel_connector(connector);
3343
3344 intel_attach_force_audio_property(connector);
3345 intel_attach_broadcast_rgb_property(connector);
3346 intel_dp->color_range_auto = true;
3347
3348 if (is_edp(intel_dp)) {
3349 drm_mode_create_scaling_mode_property(connector->dev);
3350 drm_object_attach_property(
3351 &connector->base,
3352 connector->dev->mode_config.scaling_mode_property,
3353 DRM_MODE_SCALE_ASPECT);
3354 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3355 }
3356 }
3357
3358 static void
3359 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3360 struct intel_dp *intel_dp,
3361 struct edp_power_seq *out)
3362 {
3363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 struct edp_power_seq cur, vbt, spec, final;
3365 u32 pp_on, pp_off, pp_div, pp;
3366 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3367
3368 if (HAS_PCH_SPLIT(dev)) {
3369 pp_ctrl_reg = PCH_PP_CONTROL;
3370 pp_on_reg = PCH_PP_ON_DELAYS;
3371 pp_off_reg = PCH_PP_OFF_DELAYS;
3372 pp_div_reg = PCH_PP_DIVISOR;
3373 } else {
3374 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3375
3376 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3377 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3378 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3379 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3380 }
3381
3382 /* Workaround: Need to write PP_CONTROL with the unlock key as
3383 * the very first thing. */
3384 pp = ironlake_get_pp_control(intel_dp);
3385 I915_WRITE(pp_ctrl_reg, pp);
3386
3387 pp_on = I915_READ(pp_on_reg);
3388 pp_off = I915_READ(pp_off_reg);
3389 pp_div = I915_READ(pp_div_reg);
3390
3391 /* Pull timing values out of registers */
3392 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3393 PANEL_POWER_UP_DELAY_SHIFT;
3394
3395 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3396 PANEL_LIGHT_ON_DELAY_SHIFT;
3397
3398 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3399 PANEL_LIGHT_OFF_DELAY_SHIFT;
3400
3401 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3402 PANEL_POWER_DOWN_DELAY_SHIFT;
3403
3404 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3405 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3406
3407 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3408 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3409
3410 vbt = dev_priv->vbt.edp_pps;
3411
3412 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3413 * our hw here, which are all in 100usec. */
3414 spec.t1_t3 = 210 * 10;
3415 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3416 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3417 spec.t10 = 500 * 10;
3418 /* This one is special and actually in units of 100ms, but zero
3419 * based in the hw (so we need to add 100 ms). But the sw vbt
3420 * table multiplies it with 1000 to make it in units of 100usec,
3421 * too. */
3422 spec.t11_t12 = (510 + 100) * 10;
3423
3424 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3425 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3426
3427 /* Use the max of the register settings and vbt. If both are
3428 * unset, fall back to the spec limits. */
3429 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3430 spec.field : \
3431 max(cur.field, vbt.field))
3432 assign_final(t1_t3);
3433 assign_final(t8);
3434 assign_final(t9);
3435 assign_final(t10);
3436 assign_final(t11_t12);
3437 #undef assign_final
3438
3439 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3440 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3441 intel_dp->backlight_on_delay = get_delay(t8);
3442 intel_dp->backlight_off_delay = get_delay(t9);
3443 intel_dp->panel_power_down_delay = get_delay(t10);
3444 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3445 #undef get_delay
3446
3447 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3448 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3449 intel_dp->panel_power_cycle_delay);
3450
3451 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3452 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3453
3454 if (out)
3455 *out = final;
3456 }
3457
3458 static void
3459 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3460 struct intel_dp *intel_dp,
3461 struct edp_power_seq *seq)
3462 {
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 u32 pp_on, pp_off, pp_div, port_sel = 0;
3465 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3466 int pp_on_reg, pp_off_reg, pp_div_reg;
3467
3468 if (HAS_PCH_SPLIT(dev)) {
3469 pp_on_reg = PCH_PP_ON_DELAYS;
3470 pp_off_reg = PCH_PP_OFF_DELAYS;
3471 pp_div_reg = PCH_PP_DIVISOR;
3472 } else {
3473 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3474
3475 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3476 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3477 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3478 }
3479
3480 /* And finally store the new values in the power sequencer. */
3481 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3482 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3483 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3484 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3485 /* Compute the divisor for the pp clock, simply match the Bspec
3486 * formula. */
3487 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3488 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3489 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3490
3491 /* Haswell doesn't have any port selection bits for the panel
3492 * power sequencer any more. */
3493 if (IS_VALLEYVIEW(dev)) {
3494 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3495 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3496 else
3497 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3498 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3499 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3500 port_sel = PANEL_PORT_SELECT_DPA;
3501 else
3502 port_sel = PANEL_PORT_SELECT_DPD;
3503 }
3504
3505 pp_on |= port_sel;
3506
3507 I915_WRITE(pp_on_reg, pp_on);
3508 I915_WRITE(pp_off_reg, pp_off);
3509 I915_WRITE(pp_div_reg, pp_div);
3510
3511 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3512 I915_READ(pp_on_reg),
3513 I915_READ(pp_off_reg),
3514 I915_READ(pp_div_reg));
3515 }
3516
3517 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3518 struct intel_connector *intel_connector)
3519 {
3520 struct drm_connector *connector = &intel_connector->base;
3521 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3522 struct drm_device *dev = intel_dig_port->base.base.dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct drm_display_mode *fixed_mode = NULL;
3525 struct edp_power_seq power_seq = { 0 };
3526 bool has_dpcd;
3527 struct drm_display_mode *scan;
3528 struct edid *edid;
3529
3530 if (!is_edp(intel_dp))
3531 return true;
3532
3533 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3534
3535 /* Cache DPCD and EDID for edp. */
3536 ironlake_edp_panel_vdd_on(intel_dp);
3537 has_dpcd = intel_dp_get_dpcd(intel_dp);
3538 ironlake_edp_panel_vdd_off(intel_dp, false);
3539
3540 if (has_dpcd) {
3541 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3542 dev_priv->no_aux_handshake =
3543 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3544 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3545 } else {
3546 /* if this fails, presume the device is a ghost */
3547 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3548 return false;
3549 }
3550
3551 /* We now know it's not a ghost, init power sequence regs. */
3552 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3553 &power_seq);
3554
3555 edid = drm_get_edid(connector, &intel_dp->adapter);
3556 if (edid) {
3557 if (drm_add_edid_modes(connector, edid)) {
3558 drm_mode_connector_update_edid_property(connector,
3559 edid);
3560 drm_edid_to_eld(connector, edid);
3561 } else {
3562 kfree(edid);
3563 edid = ERR_PTR(-EINVAL);
3564 }
3565 } else {
3566 edid = ERR_PTR(-ENOENT);
3567 }
3568 intel_connector->edid = edid;
3569
3570 /* prefer fixed mode from EDID if available */
3571 list_for_each_entry(scan, &connector->probed_modes, head) {
3572 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3573 fixed_mode = drm_mode_duplicate(dev, scan);
3574 break;
3575 }
3576 }
3577
3578 /* fallback to VBT if available for eDP */
3579 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3580 fixed_mode = drm_mode_duplicate(dev,
3581 dev_priv->vbt.lfp_lvds_vbt_mode);
3582 if (fixed_mode)
3583 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3584 }
3585
3586 intel_panel_init(&intel_connector->panel, fixed_mode);
3587 intel_panel_setup_backlight(connector);
3588
3589 return true;
3590 }
3591
3592 bool
3593 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3594 struct intel_connector *intel_connector)
3595 {
3596 struct drm_connector *connector = &intel_connector->base;
3597 struct intel_dp *intel_dp = &intel_dig_port->dp;
3598 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3599 struct drm_device *dev = intel_encoder->base.dev;
3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601 enum port port = intel_dig_port->port;
3602 const char *name = NULL;
3603 int type, error;
3604
3605 /* Preserve the current hw state. */
3606 intel_dp->DP = I915_READ(intel_dp->output_reg);
3607 intel_dp->attached_connector = intel_connector;
3608
3609 type = DRM_MODE_CONNECTOR_DisplayPort;
3610 /*
3611 * FIXME : We need to initialize built-in panels before external panels.
3612 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3613 */
3614 switch (port) {
3615 case PORT_A:
3616 type = DRM_MODE_CONNECTOR_eDP;
3617 break;
3618 case PORT_C:
3619 if (IS_VALLEYVIEW(dev))
3620 type = DRM_MODE_CONNECTOR_eDP;
3621 break;
3622 case PORT_D:
3623 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3624 type = DRM_MODE_CONNECTOR_eDP;
3625 break;
3626 default: /* silence GCC warning */
3627 break;
3628 }
3629
3630 /*
3631 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3632 * for DP the encoder type can be set by the caller to
3633 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3634 */
3635 if (type == DRM_MODE_CONNECTOR_eDP)
3636 intel_encoder->type = INTEL_OUTPUT_EDP;
3637
3638 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3639 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3640 port_name(port));
3641
3642 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3643 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3644
3645 connector->interlace_allowed = true;
3646 connector->doublescan_allowed = 0;
3647
3648 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3649 ironlake_panel_vdd_work);
3650
3651 intel_connector_attach_encoder(intel_connector, intel_encoder);
3652 drm_sysfs_connector_add(connector);
3653
3654 if (HAS_DDI(dev))
3655 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3656 else
3657 intel_connector->get_hw_state = intel_connector_get_hw_state;
3658
3659 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3660 if (HAS_DDI(dev)) {
3661 switch (intel_dig_port->port) {
3662 case PORT_A:
3663 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3664 break;
3665 case PORT_B:
3666 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3667 break;
3668 case PORT_C:
3669 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3670 break;
3671 case PORT_D:
3672 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3673 break;
3674 default:
3675 BUG();
3676 }
3677 }
3678
3679 /* Set up the DDC bus. */
3680 switch (port) {
3681 case PORT_A:
3682 intel_encoder->hpd_pin = HPD_PORT_A;
3683 name = "DPDDC-A";
3684 break;
3685 case PORT_B:
3686 intel_encoder->hpd_pin = HPD_PORT_B;
3687 name = "DPDDC-B";
3688 break;
3689 case PORT_C:
3690 intel_encoder->hpd_pin = HPD_PORT_C;
3691 name = "DPDDC-C";
3692 break;
3693 case PORT_D:
3694 intel_encoder->hpd_pin = HPD_PORT_D;
3695 name = "DPDDC-D";
3696 break;
3697 default:
3698 BUG();
3699 }
3700
3701 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3702 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3703 error, port_name(port));
3704
3705 intel_dp->psr_setup_done = false;
3706
3707 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3708 i2c_del_adapter(&intel_dp->adapter);
3709 if (is_edp(intel_dp)) {
3710 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3711 mutex_lock(&dev->mode_config.mutex);
3712 ironlake_panel_vdd_off_sync(intel_dp);
3713 mutex_unlock(&dev->mode_config.mutex);
3714 }
3715 drm_sysfs_connector_remove(connector);
3716 drm_connector_cleanup(connector);
3717 return false;
3718 }
3719
3720 intel_dp_add_properties(intel_dp, connector);
3721
3722 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3723 * 0xd. Failure to do so will result in spurious interrupts being
3724 * generated on the port when a cable is not attached.
3725 */
3726 if (IS_G4X(dev) && !IS_GM45(dev)) {
3727 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3728 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3729 }
3730
3731 return true;
3732 }
3733
3734 void
3735 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3736 {
3737 struct intel_digital_port *intel_dig_port;
3738 struct intel_encoder *intel_encoder;
3739 struct drm_encoder *encoder;
3740 struct intel_connector *intel_connector;
3741
3742 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3743 if (!intel_dig_port)
3744 return;
3745
3746 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3747 if (!intel_connector) {
3748 kfree(intel_dig_port);
3749 return;
3750 }
3751
3752 intel_encoder = &intel_dig_port->base;
3753 encoder = &intel_encoder->base;
3754
3755 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3756 DRM_MODE_ENCODER_TMDS);
3757
3758 intel_encoder->compute_config = intel_dp_compute_config;
3759 intel_encoder->mode_set = intel_dp_mode_set;
3760 intel_encoder->disable = intel_disable_dp;
3761 intel_encoder->post_disable = intel_post_disable_dp;
3762 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3763 intel_encoder->get_config = intel_dp_get_config;
3764 if (IS_VALLEYVIEW(dev)) {
3765 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3766 intel_encoder->pre_enable = vlv_pre_enable_dp;
3767 intel_encoder->enable = vlv_enable_dp;
3768 } else {
3769 intel_encoder->pre_enable = g4x_pre_enable_dp;
3770 intel_encoder->enable = g4x_enable_dp;
3771 }
3772
3773 intel_dig_port->port = port;
3774 intel_dig_port->dp.output_reg = output_reg;
3775
3776 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3777 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3778 intel_encoder->cloneable = false;
3779 intel_encoder->hot_plug = intel_dp_hot_plug;
3780
3781 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3782 drm_encoder_cleanup(encoder);
3783 kfree(intel_dig_port);
3784 kfree(intel_connector);
3785 }
3786 }
Linux kernel - Deliverables
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