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drm/i915: Use dev_priv as first argument of for_each_pipe()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46 };
47
48 static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 };
54
55 static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 };
61
62 static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67 };
68
69 /*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73 static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85 };
86
87 /**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94 static bool is_edp(struct intel_dp *intel_dp)
95 {
96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
99 }
100
101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
102 {
103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
106 }
107
108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109 {
110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
111 }
112
113 static void intel_dp_link_down(struct intel_dp *intel_dp);
114 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
116
117 int
118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
119 {
120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
134 break;
135 default:
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142 }
143
144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145 {
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158 }
159
160 /*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
177 static int
178 intel_dp_link_required(int pixel_clock, int bpp)
179 {
180 return (pixel_clock * bpp + 9) / 10;
181 }
182
183 static int
184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185 {
186 return (max_link_clock * max_lanes * 8) / 10;
187 }
188
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192 {
193 struct intel_dp *intel_dp = intel_attached_dp(connector);
194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
198
199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
201 return MODE_PANEL;
202
203 if (mode->vdisplay > fixed_mode->vdisplay)
204 return MODE_PANEL;
205
206 target_clock = fixed_mode->clock;
207 }
208
209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
210 max_lanes = intel_dp_max_lane_count(intel_dp);
211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
216 return MODE_CLOCK_HIGH;
217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
224 return MODE_OK;
225 }
226
227 static uint32_t
228 pack_aux(uint8_t *src, int src_bytes)
229 {
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238 }
239
240 static void
241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242 {
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248 }
249
250 /* hrawclock is 1/4 the FSB frequency */
251 static int
252 intel_hrawclk(struct drm_device *dev)
253 {
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282 }
283
284 static void
285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288 static void
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293 static enum pipe
294 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295 {
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
311 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
312 return pipe;
313 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
314 return pipe;
315 }
316
317 /* shrug */
318 return PIPE_A;
319 }
320
321 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
322 {
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324
325 if (HAS_PCH_SPLIT(dev))
326 return PCH_PP_CONTROL;
327 else
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
329 }
330
331 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
332 {
333 struct drm_device *dev = intel_dp_to_dev(intel_dp);
334
335 if (HAS_PCH_SPLIT(dev))
336 return PCH_PP_STATUS;
337 else
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
339 }
340
341 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
344 void *unused)
345 {
346 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
347 edp_notifier);
348 struct drm_device *dev = intel_dp_to_dev(intel_dp);
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 pp_div;
351 u32 pp_ctrl_reg, pp_div_reg;
352 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
353
354 if (!is_edp(intel_dp) || code != SYS_RESTART)
355 return 0;
356
357 if (IS_VALLEYVIEW(dev)) {
358 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
359 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
360 pp_div = I915_READ(pp_div_reg);
361 pp_div &= PP_REFERENCE_DIVIDER_MASK;
362
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg, pp_div | 0x1F);
365 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
366 msleep(intel_dp->panel_power_cycle_delay);
367 }
368
369 return 0;
370 }
371
372 static bool edp_have_panel_power(struct intel_dp *intel_dp)
373 {
374 struct drm_device *dev = intel_dp_to_dev(intel_dp);
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
378 }
379
380 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
381 {
382 struct drm_device *dev = intel_dp_to_dev(intel_dp);
383 struct drm_i915_private *dev_priv = dev->dev_private;
384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
385 struct intel_encoder *intel_encoder = &intel_dig_port->base;
386 enum intel_display_power_domain power_domain;
387
388 power_domain = intel_display_port_power_domain(intel_encoder);
389 return intel_display_power_enabled(dev_priv, power_domain) &&
390 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
391 }
392
393 static void
394 intel_dp_check_edp(struct intel_dp *intel_dp)
395 {
396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
397 struct drm_i915_private *dev_priv = dev->dev_private;
398
399 if (!is_edp(intel_dp))
400 return;
401
402 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
405 I915_READ(_pp_stat_reg(intel_dp)),
406 I915_READ(_pp_ctrl_reg(intel_dp)));
407 }
408 }
409
410 static uint32_t
411 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
412 {
413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
414 struct drm_device *dev = intel_dig_port->base.base.dev;
415 struct drm_i915_private *dev_priv = dev->dev_private;
416 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
417 uint32_t status;
418 bool done;
419
420 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
421 if (has_aux_irq)
422 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
423 msecs_to_jiffies_timeout(10));
424 else
425 done = wait_for_atomic(C, 10) == 0;
426 if (!done)
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
428 has_aux_irq);
429 #undef C
430
431 return status;
432 }
433
434 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
435 {
436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
437 struct drm_device *dev = intel_dig_port->base.base.dev;
438
439 /*
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
442 */
443 return index ? 0 : intel_hrawclk(dev) / 2;
444 }
445
446 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
447 {
448 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
449 struct drm_device *dev = intel_dig_port->base.base.dev;
450
451 if (index)
452 return 0;
453
454 if (intel_dig_port->port == PORT_A) {
455 if (IS_GEN6(dev) || IS_GEN7(dev))
456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
457 else
458 return 225; /* eDP input clock at 450Mhz */
459 } else {
460 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
461 }
462 }
463
464 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
465 {
466 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
467 struct drm_device *dev = intel_dig_port->base.base.dev;
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 if (intel_dig_port->port == PORT_A) {
471 if (index)
472 return 0;
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
474 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
475 /* Workaround for non-ULT HSW */
476 switch (index) {
477 case 0: return 63;
478 case 1: return 72;
479 default: return 0;
480 }
481 } else {
482 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
483 }
484 }
485
486 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
487 {
488 return index ? 0 : 100;
489 }
490
491 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
492 bool has_aux_irq,
493 int send_bytes,
494 uint32_t aux_clock_divider)
495 {
496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
497 struct drm_device *dev = intel_dig_port->base.base.dev;
498 uint32_t precharge, timeout;
499
500 if (IS_GEN6(dev))
501 precharge = 3;
502 else
503 precharge = 5;
504
505 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
506 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
507 else
508 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
509
510 return DP_AUX_CH_CTL_SEND_BUSY |
511 DP_AUX_CH_CTL_DONE |
512 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
513 DP_AUX_CH_CTL_TIME_OUT_ERROR |
514 timeout |
515 DP_AUX_CH_CTL_RECEIVE_ERROR |
516 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
517 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
518 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
519 }
520
521 static int
522 intel_dp_aux_ch(struct intel_dp *intel_dp,
523 uint8_t *send, int send_bytes,
524 uint8_t *recv, int recv_size)
525 {
526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
527 struct drm_device *dev = intel_dig_port->base.base.dev;
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
530 uint32_t ch_data = ch_ctl + 4;
531 uint32_t aux_clock_divider;
532 int i, ret, recv_bytes;
533 uint32_t status;
534 int try, clock = 0;
535 bool has_aux_irq = HAS_AUX_IRQ(dev);
536 bool vdd;
537
538 vdd = _edp_panel_vdd_on(intel_dp);
539
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
542 * deep sleep states.
543 */
544 pm_qos_update_request(&dev_priv->pm_qos, 0);
545
546 intel_dp_check_edp(intel_dp);
547
548 intel_aux_display_runtime_get(dev_priv);
549
550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
552 status = I915_READ_NOTRACE(ch_ctl);
553 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
554 break;
555 msleep(1);
556 }
557
558 if (try == 3) {
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
560 I915_READ(ch_ctl));
561 ret = -EBUSY;
562 goto out;
563 }
564
565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
567 ret = -E2BIG;
568 goto out;
569 }
570
571 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
572 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
573 has_aux_irq,
574 send_bytes,
575 aux_clock_divider);
576
577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i = 0; i < send_bytes; i += 4)
581 I915_WRITE(ch_data + i,
582 pack_aux(send + i, send_bytes - i));
583
584 /* Send the command and wait for it to complete */
585 I915_WRITE(ch_ctl, send_ctl);
586
587 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
588
589 /* Clear done status and any errors */
590 I915_WRITE(ch_ctl,
591 status |
592 DP_AUX_CH_CTL_DONE |
593 DP_AUX_CH_CTL_TIME_OUT_ERROR |
594 DP_AUX_CH_CTL_RECEIVE_ERROR);
595
596 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
597 DP_AUX_CH_CTL_RECEIVE_ERROR))
598 continue;
599 if (status & DP_AUX_CH_CTL_DONE)
600 break;
601 }
602 if (status & DP_AUX_CH_CTL_DONE)
603 break;
604 }
605
606 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
608 ret = -EBUSY;
609 goto out;
610 }
611
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
614 */
615 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
617 ret = -EIO;
618 goto out;
619 }
620
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
623 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
625 ret = -ETIMEDOUT;
626 goto out;
627 }
628
629 /* Unload any bytes sent back from the other side */
630 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
632 if (recv_bytes > recv_size)
633 recv_bytes = recv_size;
634
635 for (i = 0; i < recv_bytes; i += 4)
636 unpack_aux(I915_READ(ch_data + i),
637 recv + i, recv_bytes - i);
638
639 ret = recv_bytes;
640 out:
641 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
642 intel_aux_display_runtime_put(dev_priv);
643
644 if (vdd)
645 edp_panel_vdd_off(intel_dp, false);
646
647 return ret;
648 }
649
650 #define BARE_ADDRESS_SIZE 3
651 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
652 static ssize_t
653 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
654 {
655 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
656 uint8_t txbuf[20], rxbuf[20];
657 size_t txsize, rxsize;
658 int ret;
659
660 txbuf[0] = msg->request << 4;
661 txbuf[1] = msg->address >> 8;
662 txbuf[2] = msg->address & 0xff;
663 txbuf[3] = msg->size - 1;
664
665 switch (msg->request & ~DP_AUX_I2C_MOT) {
666 case DP_AUX_NATIVE_WRITE:
667 case DP_AUX_I2C_WRITE:
668 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
669 rxsize = 1;
670
671 if (WARN_ON(txsize > 20))
672 return -E2BIG;
673
674 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
675
676 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
677 if (ret > 0) {
678 msg->reply = rxbuf[0] >> 4;
679
680 /* Return payload size. */
681 ret = msg->size;
682 }
683 break;
684
685 case DP_AUX_NATIVE_READ:
686 case DP_AUX_I2C_READ:
687 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
688 rxsize = msg->size + 1;
689
690 if (WARN_ON(rxsize > 20))
691 return -E2BIG;
692
693 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
694 if (ret > 0) {
695 msg->reply = rxbuf[0] >> 4;
696 /*
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
699 *
700 * Return payload size.
701 */
702 ret--;
703 memcpy(msg->buffer, rxbuf + 1, ret);
704 }
705 break;
706
707 default:
708 ret = -EINVAL;
709 break;
710 }
711
712 return ret;
713 }
714
715 static void
716 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
717 {
718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
720 enum port port = intel_dig_port->port;
721 const char *name = NULL;
722 int ret;
723
724 switch (port) {
725 case PORT_A:
726 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
727 name = "DPDDC-A";
728 break;
729 case PORT_B:
730 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
731 name = "DPDDC-B";
732 break;
733 case PORT_C:
734 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
735 name = "DPDDC-C";
736 break;
737 case PORT_D:
738 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
739 name = "DPDDC-D";
740 break;
741 default:
742 BUG();
743 }
744
745 if (!HAS_DDI(dev))
746 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
747
748 intel_dp->aux.name = name;
749 intel_dp->aux.dev = dev->dev;
750 intel_dp->aux.transfer = intel_dp_aux_transfer;
751
752 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
753 connector->base.kdev->kobj.name);
754
755 ret = drm_dp_aux_register(&intel_dp->aux);
756 if (ret < 0) {
757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
758 name, ret);
759 return;
760 }
761
762 ret = sysfs_create_link(&connector->base.kdev->kobj,
763 &intel_dp->aux.ddc.dev.kobj,
764 intel_dp->aux.ddc.dev.kobj.name);
765 if (ret < 0) {
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
767 drm_dp_aux_unregister(&intel_dp->aux);
768 }
769 }
770
771 static void
772 intel_dp_connector_unregister(struct intel_connector *intel_connector)
773 {
774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
775
776 if (!intel_connector->mst_port)
777 sysfs_remove_link(&intel_connector->base.kdev->kobj,
778 intel_dp->aux.ddc.dev.kobj.name);
779 intel_connector_unregister(intel_connector);
780 }
781
782 static void
783 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
784 {
785 switch (link_bw) {
786 case DP_LINK_BW_1_62:
787 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
788 break;
789 case DP_LINK_BW_2_7:
790 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
791 break;
792 case DP_LINK_BW_5_4:
793 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
794 break;
795 }
796 }
797
798 static void
799 intel_dp_set_clock(struct intel_encoder *encoder,
800 struct intel_crtc_config *pipe_config, int link_bw)
801 {
802 struct drm_device *dev = encoder->base.dev;
803 const struct dp_link_dpll *divisor = NULL;
804 int i, count = 0;
805
806 if (IS_G4X(dev)) {
807 divisor = gen4_dpll;
808 count = ARRAY_SIZE(gen4_dpll);
809 } else if (HAS_PCH_SPLIT(dev)) {
810 divisor = pch_dpll;
811 count = ARRAY_SIZE(pch_dpll);
812 } else if (IS_CHERRYVIEW(dev)) {
813 divisor = chv_dpll;
814 count = ARRAY_SIZE(chv_dpll);
815 } else if (IS_VALLEYVIEW(dev)) {
816 divisor = vlv_dpll;
817 count = ARRAY_SIZE(vlv_dpll);
818 }
819
820 if (divisor && count) {
821 for (i = 0; i < count; i++) {
822 if (link_bw == divisor[i].link_bw) {
823 pipe_config->dpll = divisor[i].dpll;
824 pipe_config->clock_set = true;
825 break;
826 }
827 }
828 }
829 }
830
831 bool
832 intel_dp_compute_config(struct intel_encoder *encoder,
833 struct intel_crtc_config *pipe_config)
834 {
835 struct drm_device *dev = encoder->base.dev;
836 struct drm_i915_private *dev_priv = dev->dev_private;
837 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
839 enum port port = dp_to_dig_port(intel_dp)->port;
840 struct intel_crtc *intel_crtc = encoder->new_crtc;
841 struct intel_connector *intel_connector = intel_dp->attached_connector;
842 int lane_count, clock;
843 int min_lane_count = 1;
844 int max_lane_count = intel_dp_max_lane_count(intel_dp);
845 /* Conveniently, the link BW constants become indices with a shift...*/
846 int min_clock = 0;
847 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
848 int bpp, mode_rate;
849 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
850 int link_avail, link_clock;
851
852 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
853 pipe_config->has_pch_encoder = true;
854
855 pipe_config->has_dp_encoder = true;
856 pipe_config->has_drrs = false;
857 pipe_config->has_audio = intel_dp->has_audio;
858
859 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
860 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
861 adjusted_mode);
862 if (!HAS_PCH_SPLIT(dev))
863 intel_gmch_panel_fitting(intel_crtc, pipe_config,
864 intel_connector->panel.fitting_mode);
865 else
866 intel_pch_panel_fitting(intel_crtc, pipe_config,
867 intel_connector->panel.fitting_mode);
868 }
869
870 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
871 return false;
872
873 DRM_DEBUG_KMS("DP link computation with max lane count %i "
874 "max bw %02x pixel clock %iKHz\n",
875 max_lane_count, bws[max_clock],
876 adjusted_mode->crtc_clock);
877
878 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
879 * bpc in between. */
880 bpp = pipe_config->pipe_bpp;
881 if (is_edp(intel_dp)) {
882 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
883 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
884 dev_priv->vbt.edp_bpp);
885 bpp = dev_priv->vbt.edp_bpp;
886 }
887
888 if (IS_BROADWELL(dev)) {
889 /* Yes, it's an ugly hack. */
890 min_lane_count = max_lane_count;
891 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
892 min_lane_count);
893 } else if (dev_priv->vbt.edp_lanes) {
894 min_lane_count = min(dev_priv->vbt.edp_lanes,
895 max_lane_count);
896 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
897 min_lane_count);
898 }
899
900 if (dev_priv->vbt.edp_rate) {
901 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
902 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
903 bws[min_clock]);
904 }
905 }
906
907 for (; bpp >= 6*3; bpp -= 2*3) {
908 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
909 bpp);
910
911 for (clock = min_clock; clock <= max_clock; clock++) {
912 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
913 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
914 link_avail = intel_dp_max_data_rate(link_clock,
915 lane_count);
916
917 if (mode_rate <= link_avail) {
918 goto found;
919 }
920 }
921 }
922 }
923
924 return false;
925
926 found:
927 if (intel_dp->color_range_auto) {
928 /*
929 * See:
930 * CEA-861-E - 5.1 Default Encoding Parameters
931 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
932 */
933 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
934 intel_dp->color_range = DP_COLOR_RANGE_16_235;
935 else
936 intel_dp->color_range = 0;
937 }
938
939 if (intel_dp->color_range)
940 pipe_config->limited_color_range = true;
941
942 intel_dp->link_bw = bws[clock];
943 intel_dp->lane_count = lane_count;
944 pipe_config->pipe_bpp = bpp;
945 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
946
947 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
948 intel_dp->link_bw, intel_dp->lane_count,
949 pipe_config->port_clock, bpp);
950 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
951 mode_rate, link_avail);
952
953 intel_link_compute_m_n(bpp, lane_count,
954 adjusted_mode->crtc_clock,
955 pipe_config->port_clock,
956 &pipe_config->dp_m_n);
957
958 if (intel_connector->panel.downclock_mode != NULL &&
959 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
960 pipe_config->has_drrs = true;
961 intel_link_compute_m_n(bpp, lane_count,
962 intel_connector->panel.downclock_mode->clock,
963 pipe_config->port_clock,
964 &pipe_config->dp_m2_n2);
965 }
966
967 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
968 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
969 else
970 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
971
972 return true;
973 }
974
975 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
976 {
977 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
978 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
979 struct drm_device *dev = crtc->base.dev;
980 struct drm_i915_private *dev_priv = dev->dev_private;
981 u32 dpa_ctl;
982
983 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
984 dpa_ctl = I915_READ(DP_A);
985 dpa_ctl &= ~DP_PLL_FREQ_MASK;
986
987 if (crtc->config.port_clock == 162000) {
988 /* For a long time we've carried around a ILK-DevA w/a for the
989 * 160MHz clock. If we're really unlucky, it's still required.
990 */
991 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
992 dpa_ctl |= DP_PLL_FREQ_160MHZ;
993 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
994 } else {
995 dpa_ctl |= DP_PLL_FREQ_270MHZ;
996 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
997 }
998
999 I915_WRITE(DP_A, dpa_ctl);
1000
1001 POSTING_READ(DP_A);
1002 udelay(500);
1003 }
1004
1005 static void intel_dp_prepare(struct intel_encoder *encoder)
1006 {
1007 struct drm_device *dev = encoder->base.dev;
1008 struct drm_i915_private *dev_priv = dev->dev_private;
1009 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1010 enum port port = dp_to_dig_port(intel_dp)->port;
1011 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1012 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1013
1014 /*
1015 * There are four kinds of DP registers:
1016 *
1017 * IBX PCH
1018 * SNB CPU
1019 * IVB CPU
1020 * CPT PCH
1021 *
1022 * IBX PCH and CPU are the same for almost everything,
1023 * except that the CPU DP PLL is configured in this
1024 * register
1025 *
1026 * CPT PCH is quite different, having many bits moved
1027 * to the TRANS_DP_CTL register instead. That
1028 * configuration happens (oddly) in ironlake_pch_enable
1029 */
1030
1031 /* Preserve the BIOS-computed detected bit. This is
1032 * supposed to be read-only.
1033 */
1034 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1035
1036 /* Handle DP bits in common between all three register formats */
1037 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1038 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1039
1040 if (crtc->config.has_audio) {
1041 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1042 pipe_name(crtc->pipe));
1043 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1044 intel_write_eld(&encoder->base, adjusted_mode);
1045 }
1046
1047 /* Split out the IBX/CPU vs CPT settings */
1048
1049 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1050 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1051 intel_dp->DP |= DP_SYNC_HS_HIGH;
1052 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1053 intel_dp->DP |= DP_SYNC_VS_HIGH;
1054 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1055
1056 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1057 intel_dp->DP |= DP_ENHANCED_FRAMING;
1058
1059 intel_dp->DP |= crtc->pipe << 29;
1060 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1061 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1062 intel_dp->DP |= intel_dp->color_range;
1063
1064 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1065 intel_dp->DP |= DP_SYNC_HS_HIGH;
1066 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1067 intel_dp->DP |= DP_SYNC_VS_HIGH;
1068 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1069
1070 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1071 intel_dp->DP |= DP_ENHANCED_FRAMING;
1072
1073 if (!IS_CHERRYVIEW(dev)) {
1074 if (crtc->pipe == 1)
1075 intel_dp->DP |= DP_PIPEB_SELECT;
1076 } else {
1077 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1078 }
1079 } else {
1080 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1081 }
1082 }
1083
1084 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1085 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1086
1087 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1088 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1089
1090 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1091 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1092
1093 static void wait_panel_status(struct intel_dp *intel_dp,
1094 u32 mask,
1095 u32 value)
1096 {
1097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 u32 pp_stat_reg, pp_ctrl_reg;
1100
1101 pp_stat_reg = _pp_stat_reg(intel_dp);
1102 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1103
1104 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1105 mask, value,
1106 I915_READ(pp_stat_reg),
1107 I915_READ(pp_ctrl_reg));
1108
1109 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1110 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1111 I915_READ(pp_stat_reg),
1112 I915_READ(pp_ctrl_reg));
1113 }
1114
1115 DRM_DEBUG_KMS("Wait complete\n");
1116 }
1117
1118 static void wait_panel_on(struct intel_dp *intel_dp)
1119 {
1120 DRM_DEBUG_KMS("Wait for panel power on\n");
1121 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1122 }
1123
1124 static void wait_panel_off(struct intel_dp *intel_dp)
1125 {
1126 DRM_DEBUG_KMS("Wait for panel power off time\n");
1127 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1128 }
1129
1130 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1131 {
1132 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1133
1134 /* When we disable the VDD override bit last we have to do the manual
1135 * wait. */
1136 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1137 intel_dp->panel_power_cycle_delay);
1138
1139 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1140 }
1141
1142 static void wait_backlight_on(struct intel_dp *intel_dp)
1143 {
1144 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1145 intel_dp->backlight_on_delay);
1146 }
1147
1148 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1149 {
1150 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1151 intel_dp->backlight_off_delay);
1152 }
1153
1154 /* Read the current pp_control value, unlocking the register if it
1155 * is locked
1156 */
1157
1158 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1159 {
1160 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 control;
1163
1164 control = I915_READ(_pp_ctrl_reg(intel_dp));
1165 control &= ~PANEL_UNLOCK_MASK;
1166 control |= PANEL_UNLOCK_REGS;
1167 return control;
1168 }
1169
1170 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1171 {
1172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1173 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1174 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 enum intel_display_power_domain power_domain;
1177 u32 pp;
1178 u32 pp_stat_reg, pp_ctrl_reg;
1179 bool need_to_disable = !intel_dp->want_panel_vdd;
1180
1181 if (!is_edp(intel_dp))
1182 return false;
1183
1184 intel_dp->want_panel_vdd = true;
1185
1186 if (edp_have_panel_vdd(intel_dp))
1187 return need_to_disable;
1188
1189 power_domain = intel_display_port_power_domain(intel_encoder);
1190 intel_display_power_get(dev_priv, power_domain);
1191
1192 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1193
1194 if (!edp_have_panel_power(intel_dp))
1195 wait_panel_power_cycle(intel_dp);
1196
1197 pp = ironlake_get_pp_control(intel_dp);
1198 pp |= EDP_FORCE_VDD;
1199
1200 pp_stat_reg = _pp_stat_reg(intel_dp);
1201 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1202
1203 I915_WRITE(pp_ctrl_reg, pp);
1204 POSTING_READ(pp_ctrl_reg);
1205 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1206 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1207 /*
1208 * If the panel wasn't on, delay before accessing aux channel
1209 */
1210 if (!edp_have_panel_power(intel_dp)) {
1211 DRM_DEBUG_KMS("eDP was not running\n");
1212 msleep(intel_dp->panel_power_up_delay);
1213 }
1214
1215 return need_to_disable;
1216 }
1217
1218 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1219 {
1220 if (is_edp(intel_dp)) {
1221 bool vdd = _edp_panel_vdd_on(intel_dp);
1222
1223 WARN(!vdd, "eDP VDD already requested on\n");
1224 }
1225 }
1226
1227 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1228 {
1229 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1230 struct drm_i915_private *dev_priv = dev->dev_private;
1231 u32 pp;
1232 u32 pp_stat_reg, pp_ctrl_reg;
1233
1234 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1235
1236 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1237 struct intel_digital_port *intel_dig_port =
1238 dp_to_dig_port(intel_dp);
1239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1240 enum intel_display_power_domain power_domain;
1241
1242 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1243
1244 pp = ironlake_get_pp_control(intel_dp);
1245 pp &= ~EDP_FORCE_VDD;
1246
1247 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1248 pp_stat_reg = _pp_stat_reg(intel_dp);
1249
1250 I915_WRITE(pp_ctrl_reg, pp);
1251 POSTING_READ(pp_ctrl_reg);
1252
1253 /* Make sure sequencer is idle before allowing subsequent activity */
1254 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1255 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1256
1257 if ((pp & POWER_TARGET_ON) == 0)
1258 intel_dp->last_power_cycle = jiffies;
1259
1260 power_domain = intel_display_port_power_domain(intel_encoder);
1261 intel_display_power_put(dev_priv, power_domain);
1262 }
1263 }
1264
1265 static void edp_panel_vdd_work(struct work_struct *__work)
1266 {
1267 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1268 struct intel_dp, panel_vdd_work);
1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1270
1271 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1272 edp_panel_vdd_off_sync(intel_dp);
1273 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1274 }
1275
1276 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1277 {
1278 unsigned long delay;
1279
1280 /*
1281 * Queue the timer to fire a long time from now (relative to the power
1282 * down delay) to keep the panel power up across a sequence of
1283 * operations.
1284 */
1285 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1286 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1287 }
1288
1289 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1290 {
1291 if (!is_edp(intel_dp))
1292 return;
1293
1294 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1295
1296 intel_dp->want_panel_vdd = false;
1297
1298 if (sync)
1299 edp_panel_vdd_off_sync(intel_dp);
1300 else
1301 edp_panel_vdd_schedule_off(intel_dp);
1302 }
1303
1304 void intel_edp_panel_on(struct intel_dp *intel_dp)
1305 {
1306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 u32 pp;
1309 u32 pp_ctrl_reg;
1310
1311 if (!is_edp(intel_dp))
1312 return;
1313
1314 DRM_DEBUG_KMS("Turn eDP power on\n");
1315
1316 if (edp_have_panel_power(intel_dp)) {
1317 DRM_DEBUG_KMS("eDP power already on\n");
1318 return;
1319 }
1320
1321 wait_panel_power_cycle(intel_dp);
1322
1323 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1324 pp = ironlake_get_pp_control(intel_dp);
1325 if (IS_GEN5(dev)) {
1326 /* ILK workaround: disable reset around power sequence */
1327 pp &= ~PANEL_POWER_RESET;
1328 I915_WRITE(pp_ctrl_reg, pp);
1329 POSTING_READ(pp_ctrl_reg);
1330 }
1331
1332 pp |= POWER_TARGET_ON;
1333 if (!IS_GEN5(dev))
1334 pp |= PANEL_POWER_RESET;
1335
1336 I915_WRITE(pp_ctrl_reg, pp);
1337 POSTING_READ(pp_ctrl_reg);
1338
1339 wait_panel_on(intel_dp);
1340 intel_dp->last_power_on = jiffies;
1341
1342 if (IS_GEN5(dev)) {
1343 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1344 I915_WRITE(pp_ctrl_reg, pp);
1345 POSTING_READ(pp_ctrl_reg);
1346 }
1347 }
1348
1349 void intel_edp_panel_off(struct intel_dp *intel_dp)
1350 {
1351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1353 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 enum intel_display_power_domain power_domain;
1356 u32 pp;
1357 u32 pp_ctrl_reg;
1358
1359 if (!is_edp(intel_dp))
1360 return;
1361
1362 DRM_DEBUG_KMS("Turn eDP power off\n");
1363
1364 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1365
1366 pp = ironlake_get_pp_control(intel_dp);
1367 /* We need to switch off panel power _and_ force vdd, for otherwise some
1368 * panels get very unhappy and cease to work. */
1369 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1370 EDP_BLC_ENABLE);
1371
1372 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1373
1374 intel_dp->want_panel_vdd = false;
1375
1376 I915_WRITE(pp_ctrl_reg, pp);
1377 POSTING_READ(pp_ctrl_reg);
1378
1379 intel_dp->last_power_cycle = jiffies;
1380 wait_panel_off(intel_dp);
1381
1382 /* We got a reference when we enabled the VDD. */
1383 power_domain = intel_display_port_power_domain(intel_encoder);
1384 intel_display_power_put(dev_priv, power_domain);
1385 }
1386
1387 /* Enable backlight in the panel power control. */
1388 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1389 {
1390 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1391 struct drm_device *dev = intel_dig_port->base.base.dev;
1392 struct drm_i915_private *dev_priv = dev->dev_private;
1393 u32 pp;
1394 u32 pp_ctrl_reg;
1395
1396 /*
1397 * If we enable the backlight right away following a panel power
1398 * on, we may see slight flicker as the panel syncs with the eDP
1399 * link. So delay a bit to make sure the image is solid before
1400 * allowing it to appear.
1401 */
1402 wait_backlight_on(intel_dp);
1403 pp = ironlake_get_pp_control(intel_dp);
1404 pp |= EDP_BLC_ENABLE;
1405
1406 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1407
1408 I915_WRITE(pp_ctrl_reg, pp);
1409 POSTING_READ(pp_ctrl_reg);
1410 }
1411
1412 /* Enable backlight PWM and backlight PP control. */
1413 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1414 {
1415 if (!is_edp(intel_dp))
1416 return;
1417
1418 DRM_DEBUG_KMS("\n");
1419
1420 intel_panel_enable_backlight(intel_dp->attached_connector);
1421 _intel_edp_backlight_on(intel_dp);
1422 }
1423
1424 /* Disable backlight in the panel power control. */
1425 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1426 {
1427 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 u32 pp;
1430 u32 pp_ctrl_reg;
1431
1432 pp = ironlake_get_pp_control(intel_dp);
1433 pp &= ~EDP_BLC_ENABLE;
1434
1435 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1436
1437 I915_WRITE(pp_ctrl_reg, pp);
1438 POSTING_READ(pp_ctrl_reg);
1439 intel_dp->last_backlight_off = jiffies;
1440
1441 edp_wait_backlight_off(intel_dp);
1442 }
1443
1444 /* Disable backlight PP control and backlight PWM. */
1445 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1446 {
1447 if (!is_edp(intel_dp))
1448 return;
1449
1450 DRM_DEBUG_KMS("\n");
1451
1452 _intel_edp_backlight_off(intel_dp);
1453 intel_panel_disable_backlight(intel_dp->attached_connector);
1454 }
1455
1456 /*
1457 * Hook for controlling the panel power control backlight through the bl_power
1458 * sysfs attribute. Take care to handle multiple calls.
1459 */
1460 static void intel_edp_backlight_power(struct intel_connector *connector,
1461 bool enable)
1462 {
1463 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1464 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1465
1466 if (is_enabled == enable)
1467 return;
1468
1469 DRM_DEBUG_KMS("\n");
1470
1471 if (enable)
1472 _intel_edp_backlight_on(intel_dp);
1473 else
1474 _intel_edp_backlight_off(intel_dp);
1475 }
1476
1477 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1478 {
1479 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1480 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1481 struct drm_device *dev = crtc->dev;
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483 u32 dpa_ctl;
1484
1485 assert_pipe_disabled(dev_priv,
1486 to_intel_crtc(crtc)->pipe);
1487
1488 DRM_DEBUG_KMS("\n");
1489 dpa_ctl = I915_READ(DP_A);
1490 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1491 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1492
1493 /* We don't adjust intel_dp->DP while tearing down the link, to
1494 * facilitate link retraining (e.g. after hotplug). Hence clear all
1495 * enable bits here to ensure that we don't enable too much. */
1496 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1497 intel_dp->DP |= DP_PLL_ENABLE;
1498 I915_WRITE(DP_A, intel_dp->DP);
1499 POSTING_READ(DP_A);
1500 udelay(200);
1501 }
1502
1503 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1504 {
1505 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1506 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1507 struct drm_device *dev = crtc->dev;
1508 struct drm_i915_private *dev_priv = dev->dev_private;
1509 u32 dpa_ctl;
1510
1511 assert_pipe_disabled(dev_priv,
1512 to_intel_crtc(crtc)->pipe);
1513
1514 dpa_ctl = I915_READ(DP_A);
1515 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1516 "dp pll off, should be on\n");
1517 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1518
1519 /* We can't rely on the value tracked for the DP register in
1520 * intel_dp->DP because link_down must not change that (otherwise link
1521 * re-training will fail. */
1522 dpa_ctl &= ~DP_PLL_ENABLE;
1523 I915_WRITE(DP_A, dpa_ctl);
1524 POSTING_READ(DP_A);
1525 udelay(200);
1526 }
1527
1528 /* If the sink supports it, try to set the power state appropriately */
1529 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1530 {
1531 int ret, i;
1532
1533 /* Should have a valid DPCD by this point */
1534 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1535 return;
1536
1537 if (mode != DRM_MODE_DPMS_ON) {
1538 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1539 DP_SET_POWER_D3);
1540 if (ret != 1)
1541 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1542 } else {
1543 /*
1544 * When turning on, we need to retry for 1ms to give the sink
1545 * time to wake up.
1546 */
1547 for (i = 0; i < 3; i++) {
1548 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1549 DP_SET_POWER_D0);
1550 if (ret == 1)
1551 break;
1552 msleep(1);
1553 }
1554 }
1555 }
1556
1557 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1558 enum pipe *pipe)
1559 {
1560 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1561 enum port port = dp_to_dig_port(intel_dp)->port;
1562 struct drm_device *dev = encoder->base.dev;
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 enum intel_display_power_domain power_domain;
1565 u32 tmp;
1566
1567 power_domain = intel_display_port_power_domain(encoder);
1568 if (!intel_display_power_enabled(dev_priv, power_domain))
1569 return false;
1570
1571 tmp = I915_READ(intel_dp->output_reg);
1572
1573 if (!(tmp & DP_PORT_EN))
1574 return false;
1575
1576 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1577 *pipe = PORT_TO_PIPE_CPT(tmp);
1578 } else if (IS_CHERRYVIEW(dev)) {
1579 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1580 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1581 *pipe = PORT_TO_PIPE(tmp);
1582 } else {
1583 u32 trans_sel;
1584 u32 trans_dp;
1585 int i;
1586
1587 switch (intel_dp->output_reg) {
1588 case PCH_DP_B:
1589 trans_sel = TRANS_DP_PORT_SEL_B;
1590 break;
1591 case PCH_DP_C:
1592 trans_sel = TRANS_DP_PORT_SEL_C;
1593 break;
1594 case PCH_DP_D:
1595 trans_sel = TRANS_DP_PORT_SEL_D;
1596 break;
1597 default:
1598 return true;
1599 }
1600
1601 for_each_pipe(dev_priv, i) {
1602 trans_dp = I915_READ(TRANS_DP_CTL(i));
1603 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1604 *pipe = i;
1605 return true;
1606 }
1607 }
1608
1609 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1610 intel_dp->output_reg);
1611 }
1612
1613 return true;
1614 }
1615
1616 static void intel_dp_get_config(struct intel_encoder *encoder,
1617 struct intel_crtc_config *pipe_config)
1618 {
1619 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1620 u32 tmp, flags = 0;
1621 struct drm_device *dev = encoder->base.dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623 enum port port = dp_to_dig_port(intel_dp)->port;
1624 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1625 int dotclock;
1626
1627 tmp = I915_READ(intel_dp->output_reg);
1628 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1629 pipe_config->has_audio = true;
1630
1631 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1632 if (tmp & DP_SYNC_HS_HIGH)
1633 flags |= DRM_MODE_FLAG_PHSYNC;
1634 else
1635 flags |= DRM_MODE_FLAG_NHSYNC;
1636
1637 if (tmp & DP_SYNC_VS_HIGH)
1638 flags |= DRM_MODE_FLAG_PVSYNC;
1639 else
1640 flags |= DRM_MODE_FLAG_NVSYNC;
1641 } else {
1642 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1643 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1644 flags |= DRM_MODE_FLAG_PHSYNC;
1645 else
1646 flags |= DRM_MODE_FLAG_NHSYNC;
1647
1648 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1649 flags |= DRM_MODE_FLAG_PVSYNC;
1650 else
1651 flags |= DRM_MODE_FLAG_NVSYNC;
1652 }
1653
1654 pipe_config->adjusted_mode.flags |= flags;
1655
1656 pipe_config->has_dp_encoder = true;
1657
1658 intel_dp_get_m_n(crtc, pipe_config);
1659
1660 if (port == PORT_A) {
1661 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1662 pipe_config->port_clock = 162000;
1663 else
1664 pipe_config->port_clock = 270000;
1665 }
1666
1667 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1668 &pipe_config->dp_m_n);
1669
1670 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1671 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1672
1673 pipe_config->adjusted_mode.crtc_clock = dotclock;
1674
1675 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1676 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1677 /*
1678 * This is a big fat ugly hack.
1679 *
1680 * Some machines in UEFI boot mode provide us a VBT that has 18
1681 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1682 * unknown we fail to light up. Yet the same BIOS boots up with
1683 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1684 * max, not what it tells us to use.
1685 *
1686 * Note: This will still be broken if the eDP panel is not lit
1687 * up by the BIOS, and thus we can't get the mode at module
1688 * load.
1689 */
1690 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1691 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1692 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1693 }
1694 }
1695
1696 static bool is_edp_psr(struct intel_dp *intel_dp)
1697 {
1698 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1699 }
1700
1701 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1702 {
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704
1705 if (!HAS_PSR(dev))
1706 return false;
1707
1708 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1709 }
1710
1711 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1712 struct edp_vsc_psr *vsc_psr)
1713 {
1714 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1715 struct drm_device *dev = dig_port->base.base.dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1718 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1719 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1720 uint32_t *data = (uint32_t *) vsc_psr;
1721 unsigned int i;
1722
1723 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1724 the video DIP being updated before program video DIP data buffer
1725 registers for DIP being updated. */
1726 I915_WRITE(ctl_reg, 0);
1727 POSTING_READ(ctl_reg);
1728
1729 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1730 if (i < sizeof(struct edp_vsc_psr))
1731 I915_WRITE(data_reg + i, *data++);
1732 else
1733 I915_WRITE(data_reg + i, 0);
1734 }
1735
1736 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1737 POSTING_READ(ctl_reg);
1738 }
1739
1740 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1741 {
1742 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1743 struct drm_i915_private *dev_priv = dev->dev_private;
1744 struct edp_vsc_psr psr_vsc;
1745
1746 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1747 memset(&psr_vsc, 0, sizeof(psr_vsc));
1748 psr_vsc.sdp_header.HB0 = 0;
1749 psr_vsc.sdp_header.HB1 = 0x7;
1750 psr_vsc.sdp_header.HB2 = 0x2;
1751 psr_vsc.sdp_header.HB3 = 0x8;
1752 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1753
1754 /* Avoid continuous PSR exit by masking memup and hpd */
1755 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1756 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1757 }
1758
1759 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1760 {
1761 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1762 struct drm_device *dev = dig_port->base.base.dev;
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 uint32_t aux_clock_divider;
1765 int precharge = 0x3;
1766 int msg_size = 5; /* Header(4) + Message(1) */
1767 bool only_standby = false;
1768
1769 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1770
1771 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1772 only_standby = true;
1773
1774 /* Enable PSR in sink */
1775 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1776 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1777 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1778 else
1779 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1780 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1781
1782 /* Setup AUX registers */
1783 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1784 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1785 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1786 DP_AUX_CH_CTL_TIME_OUT_400us |
1787 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1788 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1789 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1790 }
1791
1792 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1793 {
1794 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1795 struct drm_device *dev = dig_port->base.base.dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 uint32_t max_sleep_time = 0x1f;
1798 uint32_t idle_frames = 1;
1799 uint32_t val = 0x0;
1800 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1801 bool only_standby = false;
1802
1803 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1804 only_standby = true;
1805
1806 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1807 val |= EDP_PSR_LINK_STANDBY;
1808 val |= EDP_PSR_TP2_TP3_TIME_0us;
1809 val |= EDP_PSR_TP1_TIME_0us;
1810 val |= EDP_PSR_SKIP_AUX_EXIT;
1811 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1812 } else
1813 val |= EDP_PSR_LINK_DISABLE;
1814
1815 I915_WRITE(EDP_PSR_CTL(dev), val |
1816 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1817 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1818 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1819 EDP_PSR_ENABLE);
1820 }
1821
1822 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1823 {
1824 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1825 struct drm_device *dev = dig_port->base.base.dev;
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827 struct drm_crtc *crtc = dig_port->base.base.crtc;
1828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1829
1830 lockdep_assert_held(&dev_priv->psr.lock);
1831 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1832 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1833
1834 dev_priv->psr.source_ok = false;
1835
1836 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1837 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1838 return false;
1839 }
1840
1841 if (!i915.enable_psr) {
1842 DRM_DEBUG_KMS("PSR disable by flag\n");
1843 return false;
1844 }
1845
1846 /* Below limitations aren't valid for Broadwell */
1847 if (IS_BROADWELL(dev))
1848 goto out;
1849
1850 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1851 S3D_ENABLE) {
1852 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1853 return false;
1854 }
1855
1856 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1857 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1858 return false;
1859 }
1860
1861 out:
1862 dev_priv->psr.source_ok = true;
1863 return true;
1864 }
1865
1866 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1867 {
1868 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1869 struct drm_device *dev = intel_dig_port->base.base.dev;
1870 struct drm_i915_private *dev_priv = dev->dev_private;
1871
1872 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1873 WARN_ON(dev_priv->psr.active);
1874 lockdep_assert_held(&dev_priv->psr.lock);
1875
1876 /* Enable PSR on the panel */
1877 intel_edp_psr_enable_sink(intel_dp);
1878
1879 /* Enable PSR on the host */
1880 intel_edp_psr_enable_source(intel_dp);
1881
1882 dev_priv->psr.active = true;
1883 }
1884
1885 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1886 {
1887 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889
1890 if (!HAS_PSR(dev)) {
1891 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1892 return;
1893 }
1894
1895 if (!is_edp_psr(intel_dp)) {
1896 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1897 return;
1898 }
1899
1900 mutex_lock(&dev_priv->psr.lock);
1901 if (dev_priv->psr.enabled) {
1902 DRM_DEBUG_KMS("PSR already in use\n");
1903 mutex_unlock(&dev_priv->psr.lock);
1904 return;
1905 }
1906
1907 dev_priv->psr.busy_frontbuffer_bits = 0;
1908
1909 /* Setup PSR once */
1910 intel_edp_psr_setup(intel_dp);
1911
1912 if (intel_edp_psr_match_conditions(intel_dp))
1913 dev_priv->psr.enabled = intel_dp;
1914 mutex_unlock(&dev_priv->psr.lock);
1915 }
1916
1917 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1918 {
1919 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921
1922 mutex_lock(&dev_priv->psr.lock);
1923 if (!dev_priv->psr.enabled) {
1924 mutex_unlock(&dev_priv->psr.lock);
1925 return;
1926 }
1927
1928 if (dev_priv->psr.active) {
1929 I915_WRITE(EDP_PSR_CTL(dev),
1930 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1931
1932 /* Wait till PSR is idle */
1933 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1934 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1935 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1936
1937 dev_priv->psr.active = false;
1938 } else {
1939 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1940 }
1941
1942 dev_priv->psr.enabled = NULL;
1943 mutex_unlock(&dev_priv->psr.lock);
1944
1945 cancel_delayed_work_sync(&dev_priv->psr.work);
1946 }
1947
1948 static void intel_edp_psr_work(struct work_struct *work)
1949 {
1950 struct drm_i915_private *dev_priv =
1951 container_of(work, typeof(*dev_priv), psr.work.work);
1952 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1953
1954 mutex_lock(&dev_priv->psr.lock);
1955 intel_dp = dev_priv->psr.enabled;
1956
1957 if (!intel_dp)
1958 goto unlock;
1959
1960 /*
1961 * The delayed work can race with an invalidate hence we need to
1962 * recheck. Since psr_flush first clears this and then reschedules we
1963 * won't ever miss a flush when bailing out here.
1964 */
1965 if (dev_priv->psr.busy_frontbuffer_bits)
1966 goto unlock;
1967
1968 intel_edp_psr_do_enable(intel_dp);
1969 unlock:
1970 mutex_unlock(&dev_priv->psr.lock);
1971 }
1972
1973 static void intel_edp_psr_do_exit(struct drm_device *dev)
1974 {
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976
1977 if (dev_priv->psr.active) {
1978 u32 val = I915_READ(EDP_PSR_CTL(dev));
1979
1980 WARN_ON(!(val & EDP_PSR_ENABLE));
1981
1982 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1983
1984 dev_priv->psr.active = false;
1985 }
1986
1987 }
1988
1989 void intel_edp_psr_invalidate(struct drm_device *dev,
1990 unsigned frontbuffer_bits)
1991 {
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1993 struct drm_crtc *crtc;
1994 enum pipe pipe;
1995
1996 mutex_lock(&dev_priv->psr.lock);
1997 if (!dev_priv->psr.enabled) {
1998 mutex_unlock(&dev_priv->psr.lock);
1999 return;
2000 }
2001
2002 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2003 pipe = to_intel_crtc(crtc)->pipe;
2004
2005 intel_edp_psr_do_exit(dev);
2006
2007 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2008
2009 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2010 mutex_unlock(&dev_priv->psr.lock);
2011 }
2012
2013 void intel_edp_psr_flush(struct drm_device *dev,
2014 unsigned frontbuffer_bits)
2015 {
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 struct drm_crtc *crtc;
2018 enum pipe pipe;
2019
2020 mutex_lock(&dev_priv->psr.lock);
2021 if (!dev_priv->psr.enabled) {
2022 mutex_unlock(&dev_priv->psr.lock);
2023 return;
2024 }
2025
2026 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2027 pipe = to_intel_crtc(crtc)->pipe;
2028 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2029
2030 /*
2031 * On Haswell sprite plane updates don't result in a psr invalidating
2032 * signal in the hardware. Which means we need to manually fake this in
2033 * software for all flushes, not just when we've seen a preceding
2034 * invalidation through frontbuffer rendering.
2035 */
2036 if (IS_HASWELL(dev) &&
2037 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2038 intel_edp_psr_do_exit(dev);
2039
2040 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2041 schedule_delayed_work(&dev_priv->psr.work,
2042 msecs_to_jiffies(100));
2043 mutex_unlock(&dev_priv->psr.lock);
2044 }
2045
2046 void intel_edp_psr_init(struct drm_device *dev)
2047 {
2048 struct drm_i915_private *dev_priv = dev->dev_private;
2049
2050 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2051 mutex_init(&dev_priv->psr.lock);
2052 }
2053
2054 static void intel_disable_dp(struct intel_encoder *encoder)
2055 {
2056 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2057 enum port port = dp_to_dig_port(intel_dp)->port;
2058 struct drm_device *dev = encoder->base.dev;
2059
2060 /* Make sure the panel is off before trying to change the mode. But also
2061 * ensure that we have vdd while we switch off the panel. */
2062 intel_edp_panel_vdd_on(intel_dp);
2063 intel_edp_backlight_off(intel_dp);
2064 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2065 intel_edp_panel_off(intel_dp);
2066
2067 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2068 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2069 intel_dp_link_down(intel_dp);
2070 }
2071
2072 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2073 {
2074 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2075 enum port port = dp_to_dig_port(intel_dp)->port;
2076
2077 if (port != PORT_A)
2078 return;
2079
2080 intel_dp_link_down(intel_dp);
2081 ironlake_edp_pll_off(intel_dp);
2082 }
2083
2084 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2085 {
2086 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2087
2088 intel_dp_link_down(intel_dp);
2089 }
2090
2091 static void chv_post_disable_dp(struct intel_encoder *encoder)
2092 {
2093 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2094 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2095 struct drm_device *dev = encoder->base.dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 struct intel_crtc *intel_crtc =
2098 to_intel_crtc(encoder->base.crtc);
2099 enum dpio_channel ch = vlv_dport_to_channel(dport);
2100 enum pipe pipe = intel_crtc->pipe;
2101 u32 val;
2102
2103 intel_dp_link_down(intel_dp);
2104
2105 mutex_lock(&dev_priv->dpio_lock);
2106
2107 /* Propagate soft reset to data lane reset */
2108 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2109 val |= CHV_PCS_REQ_SOFTRESET_EN;
2110 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2111
2112 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2113 val |= CHV_PCS_REQ_SOFTRESET_EN;
2114 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2115
2116 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2117 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2118 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2119
2120 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2121 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2122 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2123
2124 mutex_unlock(&dev_priv->dpio_lock);
2125 }
2126
2127 static void intel_enable_dp(struct intel_encoder *encoder)
2128 {
2129 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2130 struct drm_device *dev = encoder->base.dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2133
2134 if (WARN_ON(dp_reg & DP_PORT_EN))
2135 return;
2136
2137 intel_edp_panel_vdd_on(intel_dp);
2138 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2139 intel_dp_start_link_train(intel_dp);
2140 intel_edp_panel_on(intel_dp);
2141 edp_panel_vdd_off(intel_dp, true);
2142 intel_dp_complete_link_train(intel_dp);
2143 intel_dp_stop_link_train(intel_dp);
2144 }
2145
2146 static void g4x_enable_dp(struct intel_encoder *encoder)
2147 {
2148 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2149
2150 intel_enable_dp(encoder);
2151 intel_edp_backlight_on(intel_dp);
2152 }
2153
2154 static void vlv_enable_dp(struct intel_encoder *encoder)
2155 {
2156 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2157
2158 intel_edp_backlight_on(intel_dp);
2159 }
2160
2161 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2162 {
2163 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2164 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2165
2166 intel_dp_prepare(encoder);
2167
2168 /* Only ilk+ has port A */
2169 if (dport->port == PORT_A) {
2170 ironlake_set_pll_cpu_edp(intel_dp);
2171 ironlake_edp_pll_on(intel_dp);
2172 }
2173 }
2174
2175 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2176 {
2177 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2178 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2179 struct drm_device *dev = encoder->base.dev;
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2182 enum dpio_channel port = vlv_dport_to_channel(dport);
2183 int pipe = intel_crtc->pipe;
2184 struct edp_power_seq power_seq;
2185 u32 val;
2186
2187 mutex_lock(&dev_priv->dpio_lock);
2188
2189 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2190 val = 0;
2191 if (pipe)
2192 val |= (1<<21);
2193 else
2194 val &= ~(1<<21);
2195 val |= 0x001000c4;
2196 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2197 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2198 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2199
2200 mutex_unlock(&dev_priv->dpio_lock);
2201
2202 if (is_edp(intel_dp)) {
2203 /* init power sequencer on this pipe and port */
2204 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2205 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2206 &power_seq);
2207 }
2208
2209 intel_enable_dp(encoder);
2210
2211 vlv_wait_port_ready(dev_priv, dport);
2212 }
2213
2214 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2215 {
2216 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2217 struct drm_device *dev = encoder->base.dev;
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2219 struct intel_crtc *intel_crtc =
2220 to_intel_crtc(encoder->base.crtc);
2221 enum dpio_channel port = vlv_dport_to_channel(dport);
2222 int pipe = intel_crtc->pipe;
2223
2224 intel_dp_prepare(encoder);
2225
2226 /* Program Tx lane resets to default */
2227 mutex_lock(&dev_priv->dpio_lock);
2228 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2229 DPIO_PCS_TX_LANE2_RESET |
2230 DPIO_PCS_TX_LANE1_RESET);
2231 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2232 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2233 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2234 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2235 DPIO_PCS_CLK_SOFT_RESET);
2236
2237 /* Fix up inter-pair skew failure */
2238 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2239 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2240 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2241 mutex_unlock(&dev_priv->dpio_lock);
2242 }
2243
2244 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2245 {
2246 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2247 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2248 struct drm_device *dev = encoder->base.dev;
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct edp_power_seq power_seq;
2251 struct intel_crtc *intel_crtc =
2252 to_intel_crtc(encoder->base.crtc);
2253 enum dpio_channel ch = vlv_dport_to_channel(dport);
2254 int pipe = intel_crtc->pipe;
2255 int data, i;
2256 u32 val;
2257
2258 mutex_lock(&dev_priv->dpio_lock);
2259
2260 /* Deassert soft data lane reset*/
2261 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2262 val |= CHV_PCS_REQ_SOFTRESET_EN;
2263 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2264
2265 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2266 val |= CHV_PCS_REQ_SOFTRESET_EN;
2267 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2268
2269 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2270 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2271 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2272
2273 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2274 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2275 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2276
2277 /* Program Tx lane latency optimal setting*/
2278 for (i = 0; i < 4; i++) {
2279 /* Set the latency optimal bit */
2280 data = (i == 1) ? 0x0 : 0x6;
2281 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2282 data << DPIO_FRC_LATENCY_SHFIT);
2283
2284 /* Set the upar bit */
2285 data = (i == 1) ? 0x0 : 0x1;
2286 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2287 data << DPIO_UPAR_SHIFT);
2288 }
2289
2290 /* Data lane stagger programming */
2291 /* FIXME: Fix up value only after power analysis */
2292
2293 mutex_unlock(&dev_priv->dpio_lock);
2294
2295 if (is_edp(intel_dp)) {
2296 /* init power sequencer on this pipe and port */
2297 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2298 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2299 &power_seq);
2300 }
2301
2302 intel_enable_dp(encoder);
2303
2304 vlv_wait_port_ready(dev_priv, dport);
2305 }
2306
2307 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2308 {
2309 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2310 struct drm_device *dev = encoder->base.dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct intel_crtc *intel_crtc =
2313 to_intel_crtc(encoder->base.crtc);
2314 enum dpio_channel ch = vlv_dport_to_channel(dport);
2315 enum pipe pipe = intel_crtc->pipe;
2316 u32 val;
2317
2318 intel_dp_prepare(encoder);
2319
2320 mutex_lock(&dev_priv->dpio_lock);
2321
2322 /* program left/right clock distribution */
2323 if (pipe != PIPE_B) {
2324 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2325 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2326 if (ch == DPIO_CH0)
2327 val |= CHV_BUFLEFTENA1_FORCE;
2328 if (ch == DPIO_CH1)
2329 val |= CHV_BUFRIGHTENA1_FORCE;
2330 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2331 } else {
2332 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2333 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2334 if (ch == DPIO_CH0)
2335 val |= CHV_BUFLEFTENA2_FORCE;
2336 if (ch == DPIO_CH1)
2337 val |= CHV_BUFRIGHTENA2_FORCE;
2338 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2339 }
2340
2341 /* program clock channel usage */
2342 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2343 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2344 if (pipe != PIPE_B)
2345 val &= ~CHV_PCS_USEDCLKCHANNEL;
2346 else
2347 val |= CHV_PCS_USEDCLKCHANNEL;
2348 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2349
2350 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2351 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2352 if (pipe != PIPE_B)
2353 val &= ~CHV_PCS_USEDCLKCHANNEL;
2354 else
2355 val |= CHV_PCS_USEDCLKCHANNEL;
2356 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2357
2358 /*
2359 * This a a bit weird since generally CL
2360 * matches the pipe, but here we need to
2361 * pick the CL based on the port.
2362 */
2363 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2364 if (pipe != PIPE_B)
2365 val &= ~CHV_CMN_USEDCLKCHANNEL;
2366 else
2367 val |= CHV_CMN_USEDCLKCHANNEL;
2368 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2369
2370 mutex_unlock(&dev_priv->dpio_lock);
2371 }
2372
2373 /*
2374 * Native read with retry for link status and receiver capability reads for
2375 * cases where the sink may still be asleep.
2376 *
2377 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2378 * supposed to retry 3 times per the spec.
2379 */
2380 static ssize_t
2381 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2382 void *buffer, size_t size)
2383 {
2384 ssize_t ret;
2385 int i;
2386
2387 for (i = 0; i < 3; i++) {
2388 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2389 if (ret == size)
2390 return ret;
2391 msleep(1);
2392 }
2393
2394 return ret;
2395 }
2396
2397 /*
2398 * Fetch AUX CH registers 0x202 - 0x207 which contain
2399 * link status information
2400 */
2401 static bool
2402 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2403 {
2404 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2405 DP_LANE0_1_STATUS,
2406 link_status,
2407 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2408 }
2409
2410 /* These are source-specific values. */
2411 static uint8_t
2412 intel_dp_voltage_max(struct intel_dp *intel_dp)
2413 {
2414 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2415 enum port port = dp_to_dig_port(intel_dp)->port;
2416
2417 if (IS_VALLEYVIEW(dev))
2418 return DP_TRAIN_VOLTAGE_SWING_1200;
2419 else if (IS_GEN7(dev) && port == PORT_A)
2420 return DP_TRAIN_VOLTAGE_SWING_800;
2421 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2422 return DP_TRAIN_VOLTAGE_SWING_1200;
2423 else
2424 return DP_TRAIN_VOLTAGE_SWING_800;
2425 }
2426
2427 static uint8_t
2428 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2429 {
2430 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2431 enum port port = dp_to_dig_port(intel_dp)->port;
2432
2433 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2434 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2435 case DP_TRAIN_VOLTAGE_SWING_400:
2436 return DP_TRAIN_PRE_EMPHASIS_9_5;
2437 case DP_TRAIN_VOLTAGE_SWING_600:
2438 return DP_TRAIN_PRE_EMPHASIS_6;
2439 case DP_TRAIN_VOLTAGE_SWING_800:
2440 return DP_TRAIN_PRE_EMPHASIS_3_5;
2441 case DP_TRAIN_VOLTAGE_SWING_1200:
2442 default:
2443 return DP_TRAIN_PRE_EMPHASIS_0;
2444 }
2445 } else if (IS_VALLEYVIEW(dev)) {
2446 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2447 case DP_TRAIN_VOLTAGE_SWING_400:
2448 return DP_TRAIN_PRE_EMPHASIS_9_5;
2449 case DP_TRAIN_VOLTAGE_SWING_600:
2450 return DP_TRAIN_PRE_EMPHASIS_6;
2451 case DP_TRAIN_VOLTAGE_SWING_800:
2452 return DP_TRAIN_PRE_EMPHASIS_3_5;
2453 case DP_TRAIN_VOLTAGE_SWING_1200:
2454 default:
2455 return DP_TRAIN_PRE_EMPHASIS_0;
2456 }
2457 } else if (IS_GEN7(dev) && port == PORT_A) {
2458 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2459 case DP_TRAIN_VOLTAGE_SWING_400:
2460 return DP_TRAIN_PRE_EMPHASIS_6;
2461 case DP_TRAIN_VOLTAGE_SWING_600:
2462 case DP_TRAIN_VOLTAGE_SWING_800:
2463 return DP_TRAIN_PRE_EMPHASIS_3_5;
2464 default:
2465 return DP_TRAIN_PRE_EMPHASIS_0;
2466 }
2467 } else {
2468 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2469 case DP_TRAIN_VOLTAGE_SWING_400:
2470 return DP_TRAIN_PRE_EMPHASIS_6;
2471 case DP_TRAIN_VOLTAGE_SWING_600:
2472 return DP_TRAIN_PRE_EMPHASIS_6;
2473 case DP_TRAIN_VOLTAGE_SWING_800:
2474 return DP_TRAIN_PRE_EMPHASIS_3_5;
2475 case DP_TRAIN_VOLTAGE_SWING_1200:
2476 default:
2477 return DP_TRAIN_PRE_EMPHASIS_0;
2478 }
2479 }
2480 }
2481
2482 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2483 {
2484 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2487 struct intel_crtc *intel_crtc =
2488 to_intel_crtc(dport->base.base.crtc);
2489 unsigned long demph_reg_value, preemph_reg_value,
2490 uniqtranscale_reg_value;
2491 uint8_t train_set = intel_dp->train_set[0];
2492 enum dpio_channel port = vlv_dport_to_channel(dport);
2493 int pipe = intel_crtc->pipe;
2494
2495 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2496 case DP_TRAIN_PRE_EMPHASIS_0:
2497 preemph_reg_value = 0x0004000;
2498 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2499 case DP_TRAIN_VOLTAGE_SWING_400:
2500 demph_reg_value = 0x2B405555;
2501 uniqtranscale_reg_value = 0x552AB83A;
2502 break;
2503 case DP_TRAIN_VOLTAGE_SWING_600:
2504 demph_reg_value = 0x2B404040;
2505 uniqtranscale_reg_value = 0x5548B83A;
2506 break;
2507 case DP_TRAIN_VOLTAGE_SWING_800:
2508 demph_reg_value = 0x2B245555;
2509 uniqtranscale_reg_value = 0x5560B83A;
2510 break;
2511 case DP_TRAIN_VOLTAGE_SWING_1200:
2512 demph_reg_value = 0x2B405555;
2513 uniqtranscale_reg_value = 0x5598DA3A;
2514 break;
2515 default:
2516 return 0;
2517 }
2518 break;
2519 case DP_TRAIN_PRE_EMPHASIS_3_5:
2520 preemph_reg_value = 0x0002000;
2521 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2522 case DP_TRAIN_VOLTAGE_SWING_400:
2523 demph_reg_value = 0x2B404040;
2524 uniqtranscale_reg_value = 0x5552B83A;
2525 break;
2526 case DP_TRAIN_VOLTAGE_SWING_600:
2527 demph_reg_value = 0x2B404848;
2528 uniqtranscale_reg_value = 0x5580B83A;
2529 break;
2530 case DP_TRAIN_VOLTAGE_SWING_800:
2531 demph_reg_value = 0x2B404040;
2532 uniqtranscale_reg_value = 0x55ADDA3A;
2533 break;
2534 default:
2535 return 0;
2536 }
2537 break;
2538 case DP_TRAIN_PRE_EMPHASIS_6:
2539 preemph_reg_value = 0x0000000;
2540 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2541 case DP_TRAIN_VOLTAGE_SWING_400:
2542 demph_reg_value = 0x2B305555;
2543 uniqtranscale_reg_value = 0x5570B83A;
2544 break;
2545 case DP_TRAIN_VOLTAGE_SWING_600:
2546 demph_reg_value = 0x2B2B4040;
2547 uniqtranscale_reg_value = 0x55ADDA3A;
2548 break;
2549 default:
2550 return 0;
2551 }
2552 break;
2553 case DP_TRAIN_PRE_EMPHASIS_9_5:
2554 preemph_reg_value = 0x0006000;
2555 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2556 case DP_TRAIN_VOLTAGE_SWING_400:
2557 demph_reg_value = 0x1B405555;
2558 uniqtranscale_reg_value = 0x55ADDA3A;
2559 break;
2560 default:
2561 return 0;
2562 }
2563 break;
2564 default:
2565 return 0;
2566 }
2567
2568 mutex_lock(&dev_priv->dpio_lock);
2569 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2570 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2571 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2572 uniqtranscale_reg_value);
2573 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2574 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2575 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2576 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2577 mutex_unlock(&dev_priv->dpio_lock);
2578
2579 return 0;
2580 }
2581
2582 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2583 {
2584 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2587 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2588 u32 deemph_reg_value, margin_reg_value, val;
2589 uint8_t train_set = intel_dp->train_set[0];
2590 enum dpio_channel ch = vlv_dport_to_channel(dport);
2591 enum pipe pipe = intel_crtc->pipe;
2592 int i;
2593
2594 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2595 case DP_TRAIN_PRE_EMPHASIS_0:
2596 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2597 case DP_TRAIN_VOLTAGE_SWING_400:
2598 deemph_reg_value = 128;
2599 margin_reg_value = 52;
2600 break;
2601 case DP_TRAIN_VOLTAGE_SWING_600:
2602 deemph_reg_value = 128;
2603 margin_reg_value = 77;
2604 break;
2605 case DP_TRAIN_VOLTAGE_SWING_800:
2606 deemph_reg_value = 128;
2607 margin_reg_value = 102;
2608 break;
2609 case DP_TRAIN_VOLTAGE_SWING_1200:
2610 deemph_reg_value = 128;
2611 margin_reg_value = 154;
2612 /* FIXME extra to set for 1200 */
2613 break;
2614 default:
2615 return 0;
2616 }
2617 break;
2618 case DP_TRAIN_PRE_EMPHASIS_3_5:
2619 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2620 case DP_TRAIN_VOLTAGE_SWING_400:
2621 deemph_reg_value = 85;
2622 margin_reg_value = 78;
2623 break;
2624 case DP_TRAIN_VOLTAGE_SWING_600:
2625 deemph_reg_value = 85;
2626 margin_reg_value = 116;
2627 break;
2628 case DP_TRAIN_VOLTAGE_SWING_800:
2629 deemph_reg_value = 85;
2630 margin_reg_value = 154;
2631 break;
2632 default:
2633 return 0;
2634 }
2635 break;
2636 case DP_TRAIN_PRE_EMPHASIS_6:
2637 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2638 case DP_TRAIN_VOLTAGE_SWING_400:
2639 deemph_reg_value = 64;
2640 margin_reg_value = 104;
2641 break;
2642 case DP_TRAIN_VOLTAGE_SWING_600:
2643 deemph_reg_value = 64;
2644 margin_reg_value = 154;
2645 break;
2646 default:
2647 return 0;
2648 }
2649 break;
2650 case DP_TRAIN_PRE_EMPHASIS_9_5:
2651 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2652 case DP_TRAIN_VOLTAGE_SWING_400:
2653 deemph_reg_value = 43;
2654 margin_reg_value = 154;
2655 break;
2656 default:
2657 return 0;
2658 }
2659 break;
2660 default:
2661 return 0;
2662 }
2663
2664 mutex_lock(&dev_priv->dpio_lock);
2665
2666 /* Clear calc init */
2667 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2668 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2669 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2670
2671 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2672 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2673 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2674
2675 /* Program swing deemph */
2676 for (i = 0; i < 4; i++) {
2677 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2678 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2679 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2680 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2681 }
2682
2683 /* Program swing margin */
2684 for (i = 0; i < 4; i++) {
2685 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2686 val &= ~DPIO_SWING_MARGIN000_MASK;
2687 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2688 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2689 }
2690
2691 /* Disable unique transition scale */
2692 for (i = 0; i < 4; i++) {
2693 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2694 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2695 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2696 }
2697
2698 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2699 == DP_TRAIN_PRE_EMPHASIS_0) &&
2700 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2701 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2702
2703 /*
2704 * The document said it needs to set bit 27 for ch0 and bit 26
2705 * for ch1. Might be a typo in the doc.
2706 * For now, for this unique transition scale selection, set bit
2707 * 27 for ch0 and ch1.
2708 */
2709 for (i = 0; i < 4; i++) {
2710 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2711 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2712 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2713 }
2714
2715 for (i = 0; i < 4; i++) {
2716 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2717 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2718 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2719 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2720 }
2721 }
2722
2723 /* Start swing calculation */
2724 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2725 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2726 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2727
2728 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2729 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2730 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2731
2732 /* LRC Bypass */
2733 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2734 val |= DPIO_LRC_BYPASS;
2735 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2736
2737 mutex_unlock(&dev_priv->dpio_lock);
2738
2739 return 0;
2740 }
2741
2742 static void
2743 intel_get_adjust_train(struct intel_dp *intel_dp,
2744 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2745 {
2746 uint8_t v = 0;
2747 uint8_t p = 0;
2748 int lane;
2749 uint8_t voltage_max;
2750 uint8_t preemph_max;
2751
2752 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2753 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2754 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2755
2756 if (this_v > v)
2757 v = this_v;
2758 if (this_p > p)
2759 p = this_p;
2760 }
2761
2762 voltage_max = intel_dp_voltage_max(intel_dp);
2763 if (v >= voltage_max)
2764 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2765
2766 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2767 if (p >= preemph_max)
2768 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2769
2770 for (lane = 0; lane < 4; lane++)
2771 intel_dp->train_set[lane] = v | p;
2772 }
2773
2774 static uint32_t
2775 intel_gen4_signal_levels(uint8_t train_set)
2776 {
2777 uint32_t signal_levels = 0;
2778
2779 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2780 case DP_TRAIN_VOLTAGE_SWING_400:
2781 default:
2782 signal_levels |= DP_VOLTAGE_0_4;
2783 break;
2784 case DP_TRAIN_VOLTAGE_SWING_600:
2785 signal_levels |= DP_VOLTAGE_0_6;
2786 break;
2787 case DP_TRAIN_VOLTAGE_SWING_800:
2788 signal_levels |= DP_VOLTAGE_0_8;
2789 break;
2790 case DP_TRAIN_VOLTAGE_SWING_1200:
2791 signal_levels |= DP_VOLTAGE_1_2;
2792 break;
2793 }
2794 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2795 case DP_TRAIN_PRE_EMPHASIS_0:
2796 default:
2797 signal_levels |= DP_PRE_EMPHASIS_0;
2798 break;
2799 case DP_TRAIN_PRE_EMPHASIS_3_5:
2800 signal_levels |= DP_PRE_EMPHASIS_3_5;
2801 break;
2802 case DP_TRAIN_PRE_EMPHASIS_6:
2803 signal_levels |= DP_PRE_EMPHASIS_6;
2804 break;
2805 case DP_TRAIN_PRE_EMPHASIS_9_5:
2806 signal_levels |= DP_PRE_EMPHASIS_9_5;
2807 break;
2808 }
2809 return signal_levels;
2810 }
2811
2812 /* Gen6's DP voltage swing and pre-emphasis control */
2813 static uint32_t
2814 intel_gen6_edp_signal_levels(uint8_t train_set)
2815 {
2816 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2817 DP_TRAIN_PRE_EMPHASIS_MASK);
2818 switch (signal_levels) {
2819 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2820 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2821 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2822 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2823 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2824 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2825 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2826 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2827 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2828 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2829 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2830 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2831 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2832 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2833 default:
2834 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2835 "0x%x\n", signal_levels);
2836 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2837 }
2838 }
2839
2840 /* Gen7's DP voltage swing and pre-emphasis control */
2841 static uint32_t
2842 intel_gen7_edp_signal_levels(uint8_t train_set)
2843 {
2844 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2845 DP_TRAIN_PRE_EMPHASIS_MASK);
2846 switch (signal_levels) {
2847 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2848 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2849 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2850 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2851 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2852 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2853
2854 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2855 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2856 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2857 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2858
2859 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2860 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2861 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2862 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2863
2864 default:
2865 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2866 "0x%x\n", signal_levels);
2867 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2868 }
2869 }
2870
2871 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2872 static uint32_t
2873 intel_hsw_signal_levels(uint8_t train_set)
2874 {
2875 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2876 DP_TRAIN_PRE_EMPHASIS_MASK);
2877 switch (signal_levels) {
2878 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2879 return DDI_BUF_EMP_400MV_0DB_HSW;
2880 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2881 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2882 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2883 return DDI_BUF_EMP_400MV_6DB_HSW;
2884 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2885 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2886
2887 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2888 return DDI_BUF_EMP_600MV_0DB_HSW;
2889 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2890 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2891 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2892 return DDI_BUF_EMP_600MV_6DB_HSW;
2893
2894 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2895 return DDI_BUF_EMP_800MV_0DB_HSW;
2896 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2897 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2898 default:
2899 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2900 "0x%x\n", signal_levels);
2901 return DDI_BUF_EMP_400MV_0DB_HSW;
2902 }
2903 }
2904
2905 /* Properly updates "DP" with the correct signal levels. */
2906 static void
2907 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2908 {
2909 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2910 enum port port = intel_dig_port->port;
2911 struct drm_device *dev = intel_dig_port->base.base.dev;
2912 uint32_t signal_levels, mask;
2913 uint8_t train_set = intel_dp->train_set[0];
2914
2915 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2916 signal_levels = intel_hsw_signal_levels(train_set);
2917 mask = DDI_BUF_EMP_MASK;
2918 } else if (IS_CHERRYVIEW(dev)) {
2919 signal_levels = intel_chv_signal_levels(intel_dp);
2920 mask = 0;
2921 } else if (IS_VALLEYVIEW(dev)) {
2922 signal_levels = intel_vlv_signal_levels(intel_dp);
2923 mask = 0;
2924 } else if (IS_GEN7(dev) && port == PORT_A) {
2925 signal_levels = intel_gen7_edp_signal_levels(train_set);
2926 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2927 } else if (IS_GEN6(dev) && port == PORT_A) {
2928 signal_levels = intel_gen6_edp_signal_levels(train_set);
2929 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2930 } else {
2931 signal_levels = intel_gen4_signal_levels(train_set);
2932 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2933 }
2934
2935 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2936
2937 *DP = (*DP & ~mask) | signal_levels;
2938 }
2939
2940 static bool
2941 intel_dp_set_link_train(struct intel_dp *intel_dp,
2942 uint32_t *DP,
2943 uint8_t dp_train_pat)
2944 {
2945 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2946 struct drm_device *dev = intel_dig_port->base.base.dev;
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2948 enum port port = intel_dig_port->port;
2949 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2950 int ret, len;
2951
2952 if (HAS_DDI(dev)) {
2953 uint32_t temp = I915_READ(DP_TP_CTL(port));
2954
2955 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2956 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2957 else
2958 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2959
2960 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2961 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2962 case DP_TRAINING_PATTERN_DISABLE:
2963 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2964
2965 break;
2966 case DP_TRAINING_PATTERN_1:
2967 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2968 break;
2969 case DP_TRAINING_PATTERN_2:
2970 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2971 break;
2972 case DP_TRAINING_PATTERN_3:
2973 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2974 break;
2975 }
2976 I915_WRITE(DP_TP_CTL(port), temp);
2977
2978 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2979 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2980
2981 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2982 case DP_TRAINING_PATTERN_DISABLE:
2983 *DP |= DP_LINK_TRAIN_OFF_CPT;
2984 break;
2985 case DP_TRAINING_PATTERN_1:
2986 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2987 break;
2988 case DP_TRAINING_PATTERN_2:
2989 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2990 break;
2991 case DP_TRAINING_PATTERN_3:
2992 DRM_ERROR("DP training pattern 3 not supported\n");
2993 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2994 break;
2995 }
2996
2997 } else {
2998 if (IS_CHERRYVIEW(dev))
2999 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3000 else
3001 *DP &= ~DP_LINK_TRAIN_MASK;
3002
3003 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3004 case DP_TRAINING_PATTERN_DISABLE:
3005 *DP |= DP_LINK_TRAIN_OFF;
3006 break;
3007 case DP_TRAINING_PATTERN_1:
3008 *DP |= DP_LINK_TRAIN_PAT_1;
3009 break;
3010 case DP_TRAINING_PATTERN_2:
3011 *DP |= DP_LINK_TRAIN_PAT_2;
3012 break;
3013 case DP_TRAINING_PATTERN_3:
3014 if (IS_CHERRYVIEW(dev)) {
3015 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3016 } else {
3017 DRM_ERROR("DP training pattern 3 not supported\n");
3018 *DP |= DP_LINK_TRAIN_PAT_2;
3019 }
3020 break;
3021 }
3022 }
3023
3024 I915_WRITE(intel_dp->output_reg, *DP);
3025 POSTING_READ(intel_dp->output_reg);
3026
3027 buf[0] = dp_train_pat;
3028 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3029 DP_TRAINING_PATTERN_DISABLE) {
3030 /* don't write DP_TRAINING_LANEx_SET on disable */
3031 len = 1;
3032 } else {
3033 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3034 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3035 len = intel_dp->lane_count + 1;
3036 }
3037
3038 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3039 buf, len);
3040
3041 return ret == len;
3042 }
3043
3044 static bool
3045 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3046 uint8_t dp_train_pat)
3047 {
3048 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3049 intel_dp_set_signal_levels(intel_dp, DP);
3050 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3051 }
3052
3053 static bool
3054 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3055 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3056 {
3057 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3058 struct drm_device *dev = intel_dig_port->base.base.dev;
3059 struct drm_i915_private *dev_priv = dev->dev_private;
3060 int ret;
3061
3062 intel_get_adjust_train(intel_dp, link_status);
3063 intel_dp_set_signal_levels(intel_dp, DP);
3064
3065 I915_WRITE(intel_dp->output_reg, *DP);
3066 POSTING_READ(intel_dp->output_reg);
3067
3068 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3069 intel_dp->train_set, intel_dp->lane_count);
3070
3071 return ret == intel_dp->lane_count;
3072 }
3073
3074 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3075 {
3076 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3077 struct drm_device *dev = intel_dig_port->base.base.dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 enum port port = intel_dig_port->port;
3080 uint32_t val;
3081
3082 if (!HAS_DDI(dev))
3083 return;
3084
3085 val = I915_READ(DP_TP_CTL(port));
3086 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3087 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3088 I915_WRITE(DP_TP_CTL(port), val);
3089
3090 /*
3091 * On PORT_A we can have only eDP in SST mode. There the only reason
3092 * we need to set idle transmission mode is to work around a HW issue
3093 * where we enable the pipe while not in idle link-training mode.
3094 * In this case there is requirement to wait for a minimum number of
3095 * idle patterns to be sent.
3096 */
3097 if (port == PORT_A)
3098 return;
3099
3100 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3101 1))
3102 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3103 }
3104
3105 /* Enable corresponding port and start training pattern 1 */
3106 void
3107 intel_dp_start_link_train(struct intel_dp *intel_dp)
3108 {
3109 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3110 struct drm_device *dev = encoder->dev;
3111 int i;
3112 uint8_t voltage;
3113 int voltage_tries, loop_tries;
3114 uint32_t DP = intel_dp->DP;
3115 uint8_t link_config[2];
3116
3117 if (HAS_DDI(dev))
3118 intel_ddi_prepare_link_retrain(encoder);
3119
3120 /* Write the link configuration data */
3121 link_config[0] = intel_dp->link_bw;
3122 link_config[1] = intel_dp->lane_count;
3123 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3124 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3125 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3126
3127 link_config[0] = 0;
3128 link_config[1] = DP_SET_ANSI_8B10B;
3129 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3130
3131 DP |= DP_PORT_EN;
3132
3133 /* clock recovery */
3134 if (!intel_dp_reset_link_train(intel_dp, &DP,
3135 DP_TRAINING_PATTERN_1 |
3136 DP_LINK_SCRAMBLING_DISABLE)) {
3137 DRM_ERROR("failed to enable link training\n");
3138 return;
3139 }
3140
3141 voltage = 0xff;
3142 voltage_tries = 0;
3143 loop_tries = 0;
3144 for (;;) {
3145 uint8_t link_status[DP_LINK_STATUS_SIZE];
3146
3147 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3148 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3149 DRM_ERROR("failed to get link status\n");
3150 break;
3151 }
3152
3153 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3154 DRM_DEBUG_KMS("clock recovery OK\n");
3155 break;
3156 }
3157
3158 /* Check to see if we've tried the max voltage */
3159 for (i = 0; i < intel_dp->lane_count; i++)
3160 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3161 break;
3162 if (i == intel_dp->lane_count) {
3163 ++loop_tries;
3164 if (loop_tries == 5) {
3165 DRM_ERROR("too many full retries, give up\n");
3166 break;
3167 }
3168 intel_dp_reset_link_train(intel_dp, &DP,
3169 DP_TRAINING_PATTERN_1 |
3170 DP_LINK_SCRAMBLING_DISABLE);
3171 voltage_tries = 0;
3172 continue;
3173 }
3174
3175 /* Check to see if we've tried the same voltage 5 times */
3176 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3177 ++voltage_tries;
3178 if (voltage_tries == 5) {
3179 DRM_ERROR("too many voltage retries, give up\n");
3180 break;
3181 }
3182 } else
3183 voltage_tries = 0;
3184 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3185
3186 /* Update training set as requested by target */
3187 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3188 DRM_ERROR("failed to update link training\n");
3189 break;
3190 }
3191 }
3192
3193 intel_dp->DP = DP;
3194 }
3195
3196 void
3197 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3198 {
3199 bool channel_eq = false;
3200 int tries, cr_tries;
3201 uint32_t DP = intel_dp->DP;
3202 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3203
3204 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3205 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3206 training_pattern = DP_TRAINING_PATTERN_3;
3207
3208 /* channel equalization */
3209 if (!intel_dp_set_link_train(intel_dp, &DP,
3210 training_pattern |
3211 DP_LINK_SCRAMBLING_DISABLE)) {
3212 DRM_ERROR("failed to start channel equalization\n");
3213 return;
3214 }
3215
3216 tries = 0;
3217 cr_tries = 0;
3218 channel_eq = false;
3219 for (;;) {
3220 uint8_t link_status[DP_LINK_STATUS_SIZE];
3221
3222 if (cr_tries > 5) {
3223 DRM_ERROR("failed to train DP, aborting\n");
3224 break;
3225 }
3226
3227 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3228 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3229 DRM_ERROR("failed to get link status\n");
3230 break;
3231 }
3232
3233 /* Make sure clock is still ok */
3234 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3235 intel_dp_start_link_train(intel_dp);
3236 intel_dp_set_link_train(intel_dp, &DP,
3237 training_pattern |
3238 DP_LINK_SCRAMBLING_DISABLE);
3239 cr_tries++;
3240 continue;
3241 }
3242
3243 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3244 channel_eq = true;
3245 break;
3246 }
3247
3248 /* Try 5 times, then try clock recovery if that fails */
3249 if (tries > 5) {
3250 intel_dp_link_down(intel_dp);
3251 intel_dp_start_link_train(intel_dp);
3252 intel_dp_set_link_train(intel_dp, &DP,
3253 training_pattern |
3254 DP_LINK_SCRAMBLING_DISABLE);
3255 tries = 0;
3256 cr_tries++;
3257 continue;
3258 }
3259
3260 /* Update training set as requested by target */
3261 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3262 DRM_ERROR("failed to update link training\n");
3263 break;
3264 }
3265 ++tries;
3266 }
3267
3268 intel_dp_set_idle_link_train(intel_dp);
3269
3270 intel_dp->DP = DP;
3271
3272 if (channel_eq)
3273 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3274
3275 }
3276
3277 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3278 {
3279 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3280 DP_TRAINING_PATTERN_DISABLE);
3281 }
3282
3283 static void
3284 intel_dp_link_down(struct intel_dp *intel_dp)
3285 {
3286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3287 enum port port = intel_dig_port->port;
3288 struct drm_device *dev = intel_dig_port->base.base.dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc =
3291 to_intel_crtc(intel_dig_port->base.base.crtc);
3292 uint32_t DP = intel_dp->DP;
3293
3294 if (WARN_ON(HAS_DDI(dev)))
3295 return;
3296
3297 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3298 return;
3299
3300 DRM_DEBUG_KMS("\n");
3301
3302 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3303 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3304 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3305 } else {
3306 if (IS_CHERRYVIEW(dev))
3307 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3308 else
3309 DP &= ~DP_LINK_TRAIN_MASK;
3310 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3311 }
3312 POSTING_READ(intel_dp->output_reg);
3313
3314 if (HAS_PCH_IBX(dev) &&
3315 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3316 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3317
3318 /* Hardware workaround: leaving our transcoder select
3319 * set to transcoder B while it's off will prevent the
3320 * corresponding HDMI output on transcoder A.
3321 *
3322 * Combine this with another hardware workaround:
3323 * transcoder select bit can only be cleared while the
3324 * port is enabled.
3325 */
3326 DP &= ~DP_PIPEB_SELECT;
3327 I915_WRITE(intel_dp->output_reg, DP);
3328
3329 /* Changes to enable or select take place the vblank
3330 * after being written.
3331 */
3332 if (WARN_ON(crtc == NULL)) {
3333 /* We should never try to disable a port without a crtc
3334 * attached. For paranoia keep the code around for a
3335 * bit. */
3336 POSTING_READ(intel_dp->output_reg);
3337 msleep(50);
3338 } else
3339 intel_wait_for_vblank(dev, intel_crtc->pipe);
3340 }
3341
3342 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3343 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3344 POSTING_READ(intel_dp->output_reg);
3345 msleep(intel_dp->panel_power_down_delay);
3346 }
3347
3348 static bool
3349 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3350 {
3351 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3352 struct drm_device *dev = dig_port->base.base.dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354
3355 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3356
3357 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3358 sizeof(intel_dp->dpcd)) < 0)
3359 return false; /* aux transfer failed */
3360
3361 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3362 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3363 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3364
3365 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3366 return false; /* DPCD not present */
3367
3368 /* Check if the panel supports PSR */
3369 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3370 if (is_edp(intel_dp)) {
3371 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3372 intel_dp->psr_dpcd,
3373 sizeof(intel_dp->psr_dpcd));
3374 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3375 dev_priv->psr.sink_support = true;
3376 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3377 }
3378 }
3379
3380 /* Training Pattern 3 support */
3381 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3382 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3383 intel_dp->use_tps3 = true;
3384 DRM_DEBUG_KMS("Displayport TPS3 supported");
3385 } else
3386 intel_dp->use_tps3 = false;
3387
3388 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3389 DP_DWN_STRM_PORT_PRESENT))
3390 return true; /* native DP sink */
3391
3392 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3393 return true; /* no per-port downstream info */
3394
3395 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3396 intel_dp->downstream_ports,
3397 DP_MAX_DOWNSTREAM_PORTS) < 0)
3398 return false; /* downstream port status fetch failed */
3399
3400 return true;
3401 }
3402
3403 static void
3404 intel_dp_probe_oui(struct intel_dp *intel_dp)
3405 {
3406 u8 buf[3];
3407
3408 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3409 return;
3410
3411 intel_edp_panel_vdd_on(intel_dp);
3412
3413 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3414 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3415 buf[0], buf[1], buf[2]);
3416
3417 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3418 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3419 buf[0], buf[1], buf[2]);
3420
3421 edp_panel_vdd_off(intel_dp, false);
3422 }
3423
3424 static bool
3425 intel_dp_probe_mst(struct intel_dp *intel_dp)
3426 {
3427 u8 buf[1];
3428
3429 if (!intel_dp->can_mst)
3430 return false;
3431
3432 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3433 return false;
3434
3435 _edp_panel_vdd_on(intel_dp);
3436 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3437 if (buf[0] & DP_MST_CAP) {
3438 DRM_DEBUG_KMS("Sink is MST capable\n");
3439 intel_dp->is_mst = true;
3440 } else {
3441 DRM_DEBUG_KMS("Sink is not MST capable\n");
3442 intel_dp->is_mst = false;
3443 }
3444 }
3445 edp_panel_vdd_off(intel_dp, false);
3446
3447 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3448 return intel_dp->is_mst;
3449 }
3450
3451 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3452 {
3453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3454 struct drm_device *dev = intel_dig_port->base.base.dev;
3455 struct intel_crtc *intel_crtc =
3456 to_intel_crtc(intel_dig_port->base.base.crtc);
3457 u8 buf[1];
3458
3459 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3460 return -EAGAIN;
3461
3462 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3463 return -ENOTTY;
3464
3465 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3466 DP_TEST_SINK_START) < 0)
3467 return -EAGAIN;
3468
3469 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3470 intel_wait_for_vblank(dev, intel_crtc->pipe);
3471 intel_wait_for_vblank(dev, intel_crtc->pipe);
3472
3473 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3474 return -EAGAIN;
3475
3476 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3477 return 0;
3478 }
3479
3480 static bool
3481 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3482 {
3483 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3484 DP_DEVICE_SERVICE_IRQ_VECTOR,
3485 sink_irq_vector, 1) == 1;
3486 }
3487
3488 static bool
3489 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3490 {
3491 int ret;
3492
3493 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3494 DP_SINK_COUNT_ESI,
3495 sink_irq_vector, 14);
3496 if (ret != 14)
3497 return false;
3498
3499 return true;
3500 }
3501
3502 static void
3503 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3504 {
3505 /* NAK by default */
3506 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3507 }
3508
3509 static int
3510 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3511 {
3512 bool bret;
3513
3514 if (intel_dp->is_mst) {
3515 u8 esi[16] = { 0 };
3516 int ret = 0;
3517 int retry;
3518 bool handled;
3519 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3520 go_again:
3521 if (bret == true) {
3522
3523 /* check link status - esi[10] = 0x200c */
3524 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3525 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3526 intel_dp_start_link_train(intel_dp);
3527 intel_dp_complete_link_train(intel_dp);
3528 intel_dp_stop_link_train(intel_dp);
3529 }
3530
3531 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3532 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3533
3534 if (handled) {
3535 for (retry = 0; retry < 3; retry++) {
3536 int wret;
3537 wret = drm_dp_dpcd_write(&intel_dp->aux,
3538 DP_SINK_COUNT_ESI+1,
3539 &esi[1], 3);
3540 if (wret == 3) {
3541 break;
3542 }
3543 }
3544
3545 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3546 if (bret == true) {
3547 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3548 goto go_again;
3549 }
3550 } else
3551 ret = 0;
3552
3553 return ret;
3554 } else {
3555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3556 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3557 intel_dp->is_mst = false;
3558 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3559 /* send a hotplug event */
3560 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3561 }
3562 }
3563 return -EINVAL;
3564 }
3565
3566 /*
3567 * According to DP spec
3568 * 5.1.2:
3569 * 1. Read DPCD
3570 * 2. Configure link according to Receiver Capabilities
3571 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3572 * 4. Check link status on receipt of hot-plug interrupt
3573 */
3574 void
3575 intel_dp_check_link_status(struct intel_dp *intel_dp)
3576 {
3577 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3578 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3579 u8 sink_irq_vector;
3580 u8 link_status[DP_LINK_STATUS_SIZE];
3581
3582 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3583
3584 if (!intel_encoder->connectors_active)
3585 return;
3586
3587 if (WARN_ON(!intel_encoder->base.crtc))
3588 return;
3589
3590 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3591 return;
3592
3593 /* Try to read receiver status if the link appears to be up */
3594 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3595 return;
3596 }
3597
3598 /* Now read the DPCD to see if it's actually running */
3599 if (!intel_dp_get_dpcd(intel_dp)) {
3600 return;
3601 }
3602
3603 /* Try to read the source of the interrupt */
3604 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3605 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3606 /* Clear interrupt source */
3607 drm_dp_dpcd_writeb(&intel_dp->aux,
3608 DP_DEVICE_SERVICE_IRQ_VECTOR,
3609 sink_irq_vector);
3610
3611 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3612 intel_dp_handle_test_request(intel_dp);
3613 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3614 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3615 }
3616
3617 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3618 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3619 intel_encoder->base.name);
3620 intel_dp_start_link_train(intel_dp);
3621 intel_dp_complete_link_train(intel_dp);
3622 intel_dp_stop_link_train(intel_dp);
3623 }
3624 }
3625
3626 /* XXX this is probably wrong for multiple downstream ports */
3627 static enum drm_connector_status
3628 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3629 {
3630 uint8_t *dpcd = intel_dp->dpcd;
3631 uint8_t type;
3632
3633 if (!intel_dp_get_dpcd(intel_dp))
3634 return connector_status_disconnected;
3635
3636 /* if there's no downstream port, we're done */
3637 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3638 return connector_status_connected;
3639
3640 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3641 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3642 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3643 uint8_t reg;
3644
3645 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3646 &reg, 1) < 0)
3647 return connector_status_unknown;
3648
3649 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3650 : connector_status_disconnected;
3651 }
3652
3653 /* If no HPD, poke DDC gently */
3654 if (drm_probe_ddc(&intel_dp->aux.ddc))
3655 return connector_status_connected;
3656
3657 /* Well we tried, say unknown for unreliable port types */
3658 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3659 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3660 if (type == DP_DS_PORT_TYPE_VGA ||
3661 type == DP_DS_PORT_TYPE_NON_EDID)
3662 return connector_status_unknown;
3663 } else {
3664 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3665 DP_DWN_STRM_PORT_TYPE_MASK;
3666 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3667 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3668 return connector_status_unknown;
3669 }
3670
3671 /* Anything else is out of spec, warn and ignore */
3672 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3673 return connector_status_disconnected;
3674 }
3675
3676 static enum drm_connector_status
3677 ironlake_dp_detect(struct intel_dp *intel_dp)
3678 {
3679 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3682 enum drm_connector_status status;
3683
3684 /* Can't disconnect eDP, but you can close the lid... */
3685 if (is_edp(intel_dp)) {
3686 status = intel_panel_detect(dev);
3687 if (status == connector_status_unknown)
3688 status = connector_status_connected;
3689 return status;
3690 }
3691
3692 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3693 return connector_status_disconnected;
3694
3695 return intel_dp_detect_dpcd(intel_dp);
3696 }
3697
3698 static enum drm_connector_status
3699 g4x_dp_detect(struct intel_dp *intel_dp)
3700 {
3701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3704 uint32_t bit;
3705
3706 /* Can't disconnect eDP, but you can close the lid... */
3707 if (is_edp(intel_dp)) {
3708 enum drm_connector_status status;
3709
3710 status = intel_panel_detect(dev);
3711 if (status == connector_status_unknown)
3712 status = connector_status_connected;
3713 return status;
3714 }
3715
3716 if (IS_VALLEYVIEW(dev)) {
3717 switch (intel_dig_port->port) {
3718 case PORT_B:
3719 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3720 break;
3721 case PORT_C:
3722 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3723 break;
3724 case PORT_D:
3725 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3726 break;
3727 default:
3728 return connector_status_unknown;
3729 }
3730 } else {
3731 switch (intel_dig_port->port) {
3732 case PORT_B:
3733 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3734 break;
3735 case PORT_C:
3736 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3737 break;
3738 case PORT_D:
3739 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3740 break;
3741 default:
3742 return connector_status_unknown;
3743 }
3744 }
3745
3746 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3747 return connector_status_disconnected;
3748
3749 return intel_dp_detect_dpcd(intel_dp);
3750 }
3751
3752 static struct edid *
3753 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3754 {
3755 struct intel_connector *intel_connector = to_intel_connector(connector);
3756
3757 /* use cached edid if we have one */
3758 if (intel_connector->edid) {
3759 /* invalid edid */
3760 if (IS_ERR(intel_connector->edid))
3761 return NULL;
3762
3763 return drm_edid_duplicate(intel_connector->edid);
3764 }
3765
3766 return drm_get_edid(connector, adapter);
3767 }
3768
3769 static int
3770 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3771 {
3772 struct intel_connector *intel_connector = to_intel_connector(connector);
3773
3774 /* use cached edid if we have one */
3775 if (intel_connector->edid) {
3776 /* invalid edid */
3777 if (IS_ERR(intel_connector->edid))
3778 return 0;
3779
3780 return intel_connector_update_modes(connector,
3781 intel_connector->edid);
3782 }
3783
3784 return intel_ddc_get_modes(connector, adapter);
3785 }
3786
3787 static enum drm_connector_status
3788 intel_dp_detect(struct drm_connector *connector, bool force)
3789 {
3790 struct intel_dp *intel_dp = intel_attached_dp(connector);
3791 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3792 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3793 struct drm_device *dev = connector->dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 enum drm_connector_status status;
3796 enum intel_display_power_domain power_domain;
3797 struct edid *edid = NULL;
3798 bool ret;
3799
3800 power_domain = intel_display_port_power_domain(intel_encoder);
3801 intel_display_power_get(dev_priv, power_domain);
3802
3803 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3804 connector->base.id, connector->name);
3805
3806 if (intel_dp->is_mst) {
3807 /* MST devices are disconnected from a monitor POV */
3808 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3809 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3810 status = connector_status_disconnected;
3811 goto out;
3812 }
3813
3814 intel_dp->has_audio = false;
3815
3816 if (HAS_PCH_SPLIT(dev))
3817 status = ironlake_dp_detect(intel_dp);
3818 else
3819 status = g4x_dp_detect(intel_dp);
3820
3821 if (status != connector_status_connected)
3822 goto out;
3823
3824 intel_dp_probe_oui(intel_dp);
3825
3826 ret = intel_dp_probe_mst(intel_dp);
3827 if (ret) {
3828 /* if we are in MST mode then this connector
3829 won't appear connected or have anything with EDID on it */
3830 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3831 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3832 status = connector_status_disconnected;
3833 goto out;
3834 }
3835
3836 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3837 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3838 } else {
3839 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3840 if (edid) {
3841 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3842 kfree(edid);
3843 }
3844 }
3845
3846 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3847 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3848 status = connector_status_connected;
3849
3850 out:
3851 intel_display_power_put(dev_priv, power_domain);
3852 return status;
3853 }
3854
3855 static int intel_dp_get_modes(struct drm_connector *connector)
3856 {
3857 struct intel_dp *intel_dp = intel_attached_dp(connector);
3858 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3859 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3860 struct intel_connector *intel_connector = to_intel_connector(connector);
3861 struct drm_device *dev = connector->dev;
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 enum intel_display_power_domain power_domain;
3864 int ret;
3865
3866 /* We should parse the EDID data and find out if it has an audio sink
3867 */
3868
3869 power_domain = intel_display_port_power_domain(intel_encoder);
3870 intel_display_power_get(dev_priv, power_domain);
3871
3872 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3873 intel_display_power_put(dev_priv, power_domain);
3874 if (ret)
3875 return ret;
3876
3877 /* if eDP has no EDID, fall back to fixed mode */
3878 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3879 struct drm_display_mode *mode;
3880 mode = drm_mode_duplicate(dev,
3881 intel_connector->panel.fixed_mode);
3882 if (mode) {
3883 drm_mode_probed_add(connector, mode);
3884 return 1;
3885 }
3886 }
3887 return 0;
3888 }
3889
3890 static bool
3891 intel_dp_detect_audio(struct drm_connector *connector)
3892 {
3893 struct intel_dp *intel_dp = intel_attached_dp(connector);
3894 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3895 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3896 struct drm_device *dev = connector->dev;
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 enum intel_display_power_domain power_domain;
3899 struct edid *edid;
3900 bool has_audio = false;
3901
3902 power_domain = intel_display_port_power_domain(intel_encoder);
3903 intel_display_power_get(dev_priv, power_domain);
3904
3905 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3906 if (edid) {
3907 has_audio = drm_detect_monitor_audio(edid);
3908 kfree(edid);
3909 }
3910
3911 intel_display_power_put(dev_priv, power_domain);
3912
3913 return has_audio;
3914 }
3915
3916 static int
3917 intel_dp_set_property(struct drm_connector *connector,
3918 struct drm_property *property,
3919 uint64_t val)
3920 {
3921 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3922 struct intel_connector *intel_connector = to_intel_connector(connector);
3923 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3924 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3925 int ret;
3926
3927 ret = drm_object_property_set_value(&connector->base, property, val);
3928 if (ret)
3929 return ret;
3930
3931 if (property == dev_priv->force_audio_property) {
3932 int i = val;
3933 bool has_audio;
3934
3935 if (i == intel_dp->force_audio)
3936 return 0;
3937
3938 intel_dp->force_audio = i;
3939
3940 if (i == HDMI_AUDIO_AUTO)
3941 has_audio = intel_dp_detect_audio(connector);
3942 else
3943 has_audio = (i == HDMI_AUDIO_ON);
3944
3945 if (has_audio == intel_dp->has_audio)
3946 return 0;
3947
3948 intel_dp->has_audio = has_audio;
3949 goto done;
3950 }
3951
3952 if (property == dev_priv->broadcast_rgb_property) {
3953 bool old_auto = intel_dp->color_range_auto;
3954 uint32_t old_range = intel_dp->color_range;
3955
3956 switch (val) {
3957 case INTEL_BROADCAST_RGB_AUTO:
3958 intel_dp->color_range_auto = true;
3959 break;
3960 case INTEL_BROADCAST_RGB_FULL:
3961 intel_dp->color_range_auto = false;
3962 intel_dp->color_range = 0;
3963 break;
3964 case INTEL_BROADCAST_RGB_LIMITED:
3965 intel_dp->color_range_auto = false;
3966 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3967 break;
3968 default:
3969 return -EINVAL;
3970 }
3971
3972 if (old_auto == intel_dp->color_range_auto &&
3973 old_range == intel_dp->color_range)
3974 return 0;
3975
3976 goto done;
3977 }
3978
3979 if (is_edp(intel_dp) &&
3980 property == connector->dev->mode_config.scaling_mode_property) {
3981 if (val == DRM_MODE_SCALE_NONE) {
3982 DRM_DEBUG_KMS("no scaling not supported\n");
3983 return -EINVAL;
3984 }
3985
3986 if (intel_connector->panel.fitting_mode == val) {
3987 /* the eDP scaling property is not changed */
3988 return 0;
3989 }
3990 intel_connector->panel.fitting_mode = val;
3991
3992 goto done;
3993 }
3994
3995 return -EINVAL;
3996
3997 done:
3998 if (intel_encoder->base.crtc)
3999 intel_crtc_restore_mode(intel_encoder->base.crtc);
4000
4001 return 0;
4002 }
4003
4004 static void
4005 intel_dp_connector_destroy(struct drm_connector *connector)
4006 {
4007 struct intel_connector *intel_connector = to_intel_connector(connector);
4008
4009 if (!IS_ERR_OR_NULL(intel_connector->edid))
4010 kfree(intel_connector->edid);
4011
4012 /* Can't call is_edp() since the encoder may have been destroyed
4013 * already. */
4014 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4015 intel_panel_fini(&intel_connector->panel);
4016
4017 drm_connector_cleanup(connector);
4018 kfree(connector);
4019 }
4020
4021 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4022 {
4023 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4024 struct intel_dp *intel_dp = &intel_dig_port->dp;
4025 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4026
4027 drm_dp_aux_unregister(&intel_dp->aux);
4028 intel_dp_mst_encoder_cleanup(intel_dig_port);
4029 drm_encoder_cleanup(encoder);
4030 if (is_edp(intel_dp)) {
4031 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4032 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4033 edp_panel_vdd_off_sync(intel_dp);
4034 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4035 if (intel_dp->edp_notifier.notifier_call) {
4036 unregister_reboot_notifier(&intel_dp->edp_notifier);
4037 intel_dp->edp_notifier.notifier_call = NULL;
4038 }
4039 }
4040 kfree(intel_dig_port);
4041 }
4042
4043 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4044 {
4045 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4046
4047 if (!is_edp(intel_dp))
4048 return;
4049
4050 edp_panel_vdd_off_sync(intel_dp);
4051 }
4052
4053 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4054 {
4055 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4056 }
4057
4058 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4059 .dpms = intel_connector_dpms,
4060 .detect = intel_dp_detect,
4061 .fill_modes = drm_helper_probe_single_connector_modes,
4062 .set_property = intel_dp_set_property,
4063 .destroy = intel_dp_connector_destroy,
4064 };
4065
4066 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4067 .get_modes = intel_dp_get_modes,
4068 .mode_valid = intel_dp_mode_valid,
4069 .best_encoder = intel_best_encoder,
4070 };
4071
4072 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4073 .reset = intel_dp_encoder_reset,
4074 .destroy = intel_dp_encoder_destroy,
4075 };
4076
4077 void
4078 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4079 {
4080 return;
4081 }
4082
4083 bool
4084 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4085 {
4086 struct intel_dp *intel_dp = &intel_dig_port->dp;
4087 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4088 struct drm_device *dev = intel_dig_port->base.base.dev;
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 enum intel_display_power_domain power_domain;
4091 bool ret = true;
4092
4093 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4094 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4095
4096 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4097 port_name(intel_dig_port->port),
4098 long_hpd ? "long" : "short");
4099
4100 power_domain = intel_display_port_power_domain(intel_encoder);
4101 intel_display_power_get(dev_priv, power_domain);
4102
4103 if (long_hpd) {
4104 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4105 goto mst_fail;
4106
4107 if (!intel_dp_get_dpcd(intel_dp)) {
4108 goto mst_fail;
4109 }
4110
4111 intel_dp_probe_oui(intel_dp);
4112
4113 if (!intel_dp_probe_mst(intel_dp))
4114 goto mst_fail;
4115
4116 } else {
4117 if (intel_dp->is_mst) {
4118 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4119 goto mst_fail;
4120 }
4121
4122 if (!intel_dp->is_mst) {
4123 /*
4124 * we'll check the link status via the normal hot plug path later -
4125 * but for short hpds we should check it now
4126 */
4127 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4128 intel_dp_check_link_status(intel_dp);
4129 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4130 }
4131 }
4132 ret = false;
4133 goto put_power;
4134 mst_fail:
4135 /* if we were in MST mode, and device is not there get out of MST mode */
4136 if (intel_dp->is_mst) {
4137 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4138 intel_dp->is_mst = false;
4139 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4140 }
4141 put_power:
4142 intel_display_power_put(dev_priv, power_domain);
4143
4144 return ret;
4145 }
4146
4147 /* Return which DP Port should be selected for Transcoder DP control */
4148 int
4149 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4150 {
4151 struct drm_device *dev = crtc->dev;
4152 struct intel_encoder *intel_encoder;
4153 struct intel_dp *intel_dp;
4154
4155 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4156 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4157
4158 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4159 intel_encoder->type == INTEL_OUTPUT_EDP)
4160 return intel_dp->output_reg;
4161 }
4162
4163 return -1;
4164 }
4165
4166 /* check the VBT to see whether the eDP is on DP-D port */
4167 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4168 {
4169 struct drm_i915_private *dev_priv = dev->dev_private;
4170 union child_device_config *p_child;
4171 int i;
4172 static const short port_mapping[] = {
4173 [PORT_B] = PORT_IDPB,
4174 [PORT_C] = PORT_IDPC,
4175 [PORT_D] = PORT_IDPD,
4176 };
4177
4178 if (port == PORT_A)
4179 return true;
4180
4181 if (!dev_priv->vbt.child_dev_num)
4182 return false;
4183
4184 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4185 p_child = dev_priv->vbt.child_dev + i;
4186
4187 if (p_child->common.dvo_port == port_mapping[port] &&
4188 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4189 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4190 return true;
4191 }
4192 return false;
4193 }
4194
4195 void
4196 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4197 {
4198 struct intel_connector *intel_connector = to_intel_connector(connector);
4199
4200 intel_attach_force_audio_property(connector);
4201 intel_attach_broadcast_rgb_property(connector);
4202 intel_dp->color_range_auto = true;
4203
4204 if (is_edp(intel_dp)) {
4205 drm_mode_create_scaling_mode_property(connector->dev);
4206 drm_object_attach_property(
4207 &connector->base,
4208 connector->dev->mode_config.scaling_mode_property,
4209 DRM_MODE_SCALE_ASPECT);
4210 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4211 }
4212 }
4213
4214 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4215 {
4216 intel_dp->last_power_cycle = jiffies;
4217 intel_dp->last_power_on = jiffies;
4218 intel_dp->last_backlight_off = jiffies;
4219 }
4220
4221 static void
4222 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4223 struct intel_dp *intel_dp,
4224 struct edp_power_seq *out)
4225 {
4226 struct drm_i915_private *dev_priv = dev->dev_private;
4227 struct edp_power_seq cur, vbt, spec, final;
4228 u32 pp_on, pp_off, pp_div, pp;
4229 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4230
4231 if (HAS_PCH_SPLIT(dev)) {
4232 pp_ctrl_reg = PCH_PP_CONTROL;
4233 pp_on_reg = PCH_PP_ON_DELAYS;
4234 pp_off_reg = PCH_PP_OFF_DELAYS;
4235 pp_div_reg = PCH_PP_DIVISOR;
4236 } else {
4237 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4238
4239 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4240 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4241 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4242 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4243 }
4244
4245 /* Workaround: Need to write PP_CONTROL with the unlock key as
4246 * the very first thing. */
4247 pp = ironlake_get_pp_control(intel_dp);
4248 I915_WRITE(pp_ctrl_reg, pp);
4249
4250 pp_on = I915_READ(pp_on_reg);
4251 pp_off = I915_READ(pp_off_reg);
4252 pp_div = I915_READ(pp_div_reg);
4253
4254 /* Pull timing values out of registers */
4255 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4256 PANEL_POWER_UP_DELAY_SHIFT;
4257
4258 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4259 PANEL_LIGHT_ON_DELAY_SHIFT;
4260
4261 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4262 PANEL_LIGHT_OFF_DELAY_SHIFT;
4263
4264 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4265 PANEL_POWER_DOWN_DELAY_SHIFT;
4266
4267 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4268 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4269
4270 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4271 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4272
4273 vbt = dev_priv->vbt.edp_pps;
4274
4275 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4276 * our hw here, which are all in 100usec. */
4277 spec.t1_t3 = 210 * 10;
4278 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4279 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4280 spec.t10 = 500 * 10;
4281 /* This one is special and actually in units of 100ms, but zero
4282 * based in the hw (so we need to add 100 ms). But the sw vbt
4283 * table multiplies it with 1000 to make it in units of 100usec,
4284 * too. */
4285 spec.t11_t12 = (510 + 100) * 10;
4286
4287 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4288 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4289
4290 /* Use the max of the register settings and vbt. If both are
4291 * unset, fall back to the spec limits. */
4292 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4293 spec.field : \
4294 max(cur.field, vbt.field))
4295 assign_final(t1_t3);
4296 assign_final(t8);
4297 assign_final(t9);
4298 assign_final(t10);
4299 assign_final(t11_t12);
4300 #undef assign_final
4301
4302 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4303 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4304 intel_dp->backlight_on_delay = get_delay(t8);
4305 intel_dp->backlight_off_delay = get_delay(t9);
4306 intel_dp->panel_power_down_delay = get_delay(t10);
4307 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4308 #undef get_delay
4309
4310 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4311 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4312 intel_dp->panel_power_cycle_delay);
4313
4314 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4315 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4316
4317 if (out)
4318 *out = final;
4319 }
4320
4321 static void
4322 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4323 struct intel_dp *intel_dp,
4324 struct edp_power_seq *seq)
4325 {
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 u32 pp_on, pp_off, pp_div, port_sel = 0;
4328 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4329 int pp_on_reg, pp_off_reg, pp_div_reg;
4330
4331 if (HAS_PCH_SPLIT(dev)) {
4332 pp_on_reg = PCH_PP_ON_DELAYS;
4333 pp_off_reg = PCH_PP_OFF_DELAYS;
4334 pp_div_reg = PCH_PP_DIVISOR;
4335 } else {
4336 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4337
4338 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4339 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4340 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4341 }
4342
4343 /*
4344 * And finally store the new values in the power sequencer. The
4345 * backlight delays are set to 1 because we do manual waits on them. For
4346 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4347 * we'll end up waiting for the backlight off delay twice: once when we
4348 * do the manual sleep, and once when we disable the panel and wait for
4349 * the PP_STATUS bit to become zero.
4350 */
4351 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4352 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4353 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4354 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4355 /* Compute the divisor for the pp clock, simply match the Bspec
4356 * formula. */
4357 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4358 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4359 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4360
4361 /* Haswell doesn't have any port selection bits for the panel
4362 * power sequencer any more. */
4363 if (IS_VALLEYVIEW(dev)) {
4364 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4365 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4366 else
4367 port_sel = PANEL_PORT_SELECT_DPC_VLV;
4368 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4369 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4370 port_sel = PANEL_PORT_SELECT_DPA;
4371 else
4372 port_sel = PANEL_PORT_SELECT_DPD;
4373 }
4374
4375 pp_on |= port_sel;
4376
4377 I915_WRITE(pp_on_reg, pp_on);
4378 I915_WRITE(pp_off_reg, pp_off);
4379 I915_WRITE(pp_div_reg, pp_div);
4380
4381 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4382 I915_READ(pp_on_reg),
4383 I915_READ(pp_off_reg),
4384 I915_READ(pp_div_reg));
4385 }
4386
4387 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4388 {
4389 struct drm_i915_private *dev_priv = dev->dev_private;
4390 struct intel_encoder *encoder;
4391 struct intel_dp *intel_dp = NULL;
4392 struct intel_crtc_config *config = NULL;
4393 struct intel_crtc *intel_crtc = NULL;
4394 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4395 u32 reg, val;
4396 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4397
4398 if (refresh_rate <= 0) {
4399 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4400 return;
4401 }
4402
4403 if (intel_connector == NULL) {
4404 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4405 return;
4406 }
4407
4408 /*
4409 * FIXME: This needs proper synchronization with psr state. But really
4410 * hard to tell without seeing the user of this function of this code.
4411 * Check locking and ordering once that lands.
4412 */
4413 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4414 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4415 return;
4416 }
4417
4418 encoder = intel_attached_encoder(&intel_connector->base);
4419 intel_dp = enc_to_intel_dp(&encoder->base);
4420 intel_crtc = encoder->new_crtc;
4421
4422 if (!intel_crtc) {
4423 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4424 return;
4425 }
4426
4427 config = &intel_crtc->config;
4428
4429 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4430 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4431 return;
4432 }
4433
4434 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4435 index = DRRS_LOW_RR;
4436
4437 if (index == intel_dp->drrs_state.refresh_rate_type) {
4438 DRM_DEBUG_KMS(
4439 "DRRS requested for previously set RR...ignoring\n");
4440 return;
4441 }
4442
4443 if (!intel_crtc->active) {
4444 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4445 return;
4446 }
4447
4448 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4449 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4450 val = I915_READ(reg);
4451 if (index > DRRS_HIGH_RR) {
4452 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4453 intel_dp_set_m_n(intel_crtc);
4454 } else {
4455 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4456 }
4457 I915_WRITE(reg, val);
4458 }
4459
4460 /*
4461 * mutex taken to ensure that there is no race between differnt
4462 * drrs calls trying to update refresh rate. This scenario may occur
4463 * in future when idleness detection based DRRS in kernel and
4464 * possible calls from user space to set differnt RR are made.
4465 */
4466
4467 mutex_lock(&intel_dp->drrs_state.mutex);
4468
4469 intel_dp->drrs_state.refresh_rate_type = index;
4470
4471 mutex_unlock(&intel_dp->drrs_state.mutex);
4472
4473 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4474 }
4475
4476 static struct drm_display_mode *
4477 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4478 struct intel_connector *intel_connector,
4479 struct drm_display_mode *fixed_mode)
4480 {
4481 struct drm_connector *connector = &intel_connector->base;
4482 struct intel_dp *intel_dp = &intel_dig_port->dp;
4483 struct drm_device *dev = intel_dig_port->base.base.dev;
4484 struct drm_i915_private *dev_priv = dev->dev_private;
4485 struct drm_display_mode *downclock_mode = NULL;
4486
4487 if (INTEL_INFO(dev)->gen <= 6) {
4488 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4489 return NULL;
4490 }
4491
4492 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4493 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4494 return NULL;
4495 }
4496
4497 downclock_mode = intel_find_panel_downclock
4498 (dev, fixed_mode, connector);
4499
4500 if (!downclock_mode) {
4501 DRM_DEBUG_KMS("DRRS not supported\n");
4502 return NULL;
4503 }
4504
4505 dev_priv->drrs.connector = intel_connector;
4506
4507 mutex_init(&intel_dp->drrs_state.mutex);
4508
4509 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4510
4511 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4512 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4513 return downclock_mode;
4514 }
4515
4516 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4517 {
4518 struct drm_device *dev = intel_encoder->base.dev;
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4520 struct intel_dp *intel_dp;
4521 enum intel_display_power_domain power_domain;
4522
4523 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4524 return;
4525
4526 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4527 if (!edp_have_panel_vdd(intel_dp))
4528 return;
4529 /*
4530 * The VDD bit needs a power domain reference, so if the bit is
4531 * already enabled when we boot or resume, grab this reference and
4532 * schedule a vdd off, so we don't hold on to the reference
4533 * indefinitely.
4534 */
4535 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4536 power_domain = intel_display_port_power_domain(intel_encoder);
4537 intel_display_power_get(dev_priv, power_domain);
4538
4539 edp_panel_vdd_schedule_off(intel_dp);
4540 }
4541
4542 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4543 struct intel_connector *intel_connector,
4544 struct edp_power_seq *power_seq)
4545 {
4546 struct drm_connector *connector = &intel_connector->base;
4547 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4548 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4549 struct drm_device *dev = intel_encoder->base.dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 struct drm_display_mode *fixed_mode = NULL;
4552 struct drm_display_mode *downclock_mode = NULL;
4553 bool has_dpcd;
4554 struct drm_display_mode *scan;
4555 struct edid *edid;
4556
4557 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4558
4559 if (!is_edp(intel_dp))
4560 return true;
4561
4562 intel_edp_panel_vdd_sanitize(intel_encoder);
4563
4564 /* Cache DPCD and EDID for edp. */
4565 intel_edp_panel_vdd_on(intel_dp);
4566 has_dpcd = intel_dp_get_dpcd(intel_dp);
4567 edp_panel_vdd_off(intel_dp, false);
4568
4569 if (has_dpcd) {
4570 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4571 dev_priv->no_aux_handshake =
4572 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4573 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4574 } else {
4575 /* if this fails, presume the device is a ghost */
4576 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4577 return false;
4578 }
4579
4580 /* We now know it's not a ghost, init power sequence regs. */
4581 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4582
4583 mutex_lock(&dev->mode_config.mutex);
4584 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4585 if (edid) {
4586 if (drm_add_edid_modes(connector, edid)) {
4587 drm_mode_connector_update_edid_property(connector,
4588 edid);
4589 drm_edid_to_eld(connector, edid);
4590 } else {
4591 kfree(edid);
4592 edid = ERR_PTR(-EINVAL);
4593 }
4594 } else {
4595 edid = ERR_PTR(-ENOENT);
4596 }
4597 intel_connector->edid = edid;
4598
4599 /* prefer fixed mode from EDID if available */
4600 list_for_each_entry(scan, &connector->probed_modes, head) {
4601 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4602 fixed_mode = drm_mode_duplicate(dev, scan);
4603 downclock_mode = intel_dp_drrs_init(
4604 intel_dig_port,
4605 intel_connector, fixed_mode);
4606 break;
4607 }
4608 }
4609
4610 /* fallback to VBT if available for eDP */
4611 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4612 fixed_mode = drm_mode_duplicate(dev,
4613 dev_priv->vbt.lfp_lvds_vbt_mode);
4614 if (fixed_mode)
4615 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4616 }
4617 mutex_unlock(&dev->mode_config.mutex);
4618
4619 if (IS_VALLEYVIEW(dev)) {
4620 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4621 register_reboot_notifier(&intel_dp->edp_notifier);
4622 }
4623
4624 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4625 intel_connector->panel.backlight_power = intel_edp_backlight_power;
4626 intel_panel_setup_backlight(connector);
4627
4628 return true;
4629 }
4630
4631 bool
4632 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4633 struct intel_connector *intel_connector)
4634 {
4635 struct drm_connector *connector = &intel_connector->base;
4636 struct intel_dp *intel_dp = &intel_dig_port->dp;
4637 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4638 struct drm_device *dev = intel_encoder->base.dev;
4639 struct drm_i915_private *dev_priv = dev->dev_private;
4640 enum port port = intel_dig_port->port;
4641 struct edp_power_seq power_seq = { 0 };
4642 int type;
4643
4644 /* intel_dp vfuncs */
4645 if (IS_VALLEYVIEW(dev))
4646 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4647 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4648 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4649 else if (HAS_PCH_SPLIT(dev))
4650 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4651 else
4652 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4653
4654 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4655
4656 /* Preserve the current hw state. */
4657 intel_dp->DP = I915_READ(intel_dp->output_reg);
4658 intel_dp->attached_connector = intel_connector;
4659
4660 if (intel_dp_is_edp(dev, port))
4661 type = DRM_MODE_CONNECTOR_eDP;
4662 else
4663 type = DRM_MODE_CONNECTOR_DisplayPort;
4664
4665 /*
4666 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4667 * for DP the encoder type can be set by the caller to
4668 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4669 */
4670 if (type == DRM_MODE_CONNECTOR_eDP)
4671 intel_encoder->type = INTEL_OUTPUT_EDP;
4672
4673 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4674 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4675 port_name(port));
4676
4677 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4678 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4679
4680 connector->interlace_allowed = true;
4681 connector->doublescan_allowed = 0;
4682
4683 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4684 edp_panel_vdd_work);
4685
4686 intel_connector_attach_encoder(intel_connector, intel_encoder);
4687 drm_connector_register(connector);
4688
4689 if (HAS_DDI(dev))
4690 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4691 else
4692 intel_connector->get_hw_state = intel_connector_get_hw_state;
4693 intel_connector->unregister = intel_dp_connector_unregister;
4694
4695 /* Set up the hotplug pin. */
4696 switch (port) {
4697 case PORT_A:
4698 intel_encoder->hpd_pin = HPD_PORT_A;
4699 break;
4700 case PORT_B:
4701 intel_encoder->hpd_pin = HPD_PORT_B;
4702 break;
4703 case PORT_C:
4704 intel_encoder->hpd_pin = HPD_PORT_C;
4705 break;
4706 case PORT_D:
4707 intel_encoder->hpd_pin = HPD_PORT_D;
4708 break;
4709 default:
4710 BUG();
4711 }
4712
4713 if (is_edp(intel_dp)) {
4714 intel_dp_init_panel_power_timestamps(intel_dp);
4715 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4716 }
4717
4718 intel_dp_aux_init(intel_dp, intel_connector);
4719
4720 /* init MST on ports that can support it */
4721 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4722 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4723 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4724 }
4725 }
4726
4727 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4728 drm_dp_aux_unregister(&intel_dp->aux);
4729 if (is_edp(intel_dp)) {
4730 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4731 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4732 edp_panel_vdd_off_sync(intel_dp);
4733 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4734 }
4735 drm_connector_unregister(connector);
4736 drm_connector_cleanup(connector);
4737 return false;
4738 }
4739
4740 intel_dp_add_properties(intel_dp, connector);
4741
4742 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4743 * 0xd. Failure to do so will result in spurious interrupts being
4744 * generated on the port when a cable is not attached.
4745 */
4746 if (IS_G4X(dev) && !IS_GM45(dev)) {
4747 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4748 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4749 }
4750
4751 return true;
4752 }
4753
4754 void
4755 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4756 {
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 struct intel_digital_port *intel_dig_port;
4759 struct intel_encoder *intel_encoder;
4760 struct drm_encoder *encoder;
4761 struct intel_connector *intel_connector;
4762
4763 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4764 if (!intel_dig_port)
4765 return;
4766
4767 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4768 if (!intel_connector) {
4769 kfree(intel_dig_port);
4770 return;
4771 }
4772
4773 intel_encoder = &intel_dig_port->base;
4774 encoder = &intel_encoder->base;
4775
4776 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4777 DRM_MODE_ENCODER_TMDS);
4778
4779 intel_encoder->compute_config = intel_dp_compute_config;
4780 intel_encoder->disable = intel_disable_dp;
4781 intel_encoder->get_hw_state = intel_dp_get_hw_state;
4782 intel_encoder->get_config = intel_dp_get_config;
4783 intel_encoder->suspend = intel_dp_encoder_suspend;
4784 if (IS_CHERRYVIEW(dev)) {
4785 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4786 intel_encoder->pre_enable = chv_pre_enable_dp;
4787 intel_encoder->enable = vlv_enable_dp;
4788 intel_encoder->post_disable = chv_post_disable_dp;
4789 } else if (IS_VALLEYVIEW(dev)) {
4790 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4791 intel_encoder->pre_enable = vlv_pre_enable_dp;
4792 intel_encoder->enable = vlv_enable_dp;
4793 intel_encoder->post_disable = vlv_post_disable_dp;
4794 } else {
4795 intel_encoder->pre_enable = g4x_pre_enable_dp;
4796 intel_encoder->enable = g4x_enable_dp;
4797 intel_encoder->post_disable = g4x_post_disable_dp;
4798 }
4799
4800 intel_dig_port->port = port;
4801 intel_dig_port->dp.output_reg = output_reg;
4802
4803 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4804 if (IS_CHERRYVIEW(dev)) {
4805 if (port == PORT_D)
4806 intel_encoder->crtc_mask = 1 << 2;
4807 else
4808 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4809 } else {
4810 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4811 }
4812 intel_encoder->cloneable = 0;
4813 intel_encoder->hot_plug = intel_dp_hot_plug;
4814
4815 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4816 dev_priv->hpd_irq_port[port] = intel_dig_port;
4817
4818 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4819 drm_encoder_cleanup(encoder);
4820 kfree(intel_dig_port);
4821 kfree(intel_connector);
4822 }
4823 }
4824
4825 void intel_dp_mst_suspend(struct drm_device *dev)
4826 {
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828 int i;
4829
4830 /* disable MST */
4831 for (i = 0; i < I915_MAX_PORTS; i++) {
4832 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4833 if (!intel_dig_port)
4834 continue;
4835
4836 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4837 if (!intel_dig_port->dp.can_mst)
4838 continue;
4839 if (intel_dig_port->dp.is_mst)
4840 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4841 }
4842 }
4843 }
4844
4845 void intel_dp_mst_resume(struct drm_device *dev)
4846 {
4847 struct drm_i915_private *dev_priv = dev->dev_private;
4848 int i;
4849
4850 for (i = 0; i < I915_MAX_PORTS; i++) {
4851 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4852 if (!intel_dig_port)
4853 continue;
4854 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4855 int ret;
4856
4857 if (!intel_dig_port->dp.can_mst)
4858 continue;
4859
4860 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4861 if (ret != 0) {
4862 intel_dp_check_mst_status(&intel_dig_port->dp);
4863 }
4864 }
4865 }
4866 }
Linux kernel - Deliverables
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