2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
116 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
119 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
121 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
122 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
124 switch (max_link_bw
) {
125 case DP_LINK_BW_1_62
:
128 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
129 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
130 INTEL_INFO(dev
)->gen
>= 8) &&
131 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
132 max_link_bw
= DP_LINK_BW_5_4
;
134 max_link_bw
= DP_LINK_BW_2_7
;
137 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
139 max_link_bw
= DP_LINK_BW_1_62
;
145 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
147 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
148 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
149 u8 source_max
, sink_max
;
152 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
153 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
156 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
158 return min(source_max
, sink_max
);
162 * The units on the numbers in the next two are... bizarre. Examples will
163 * make it clearer; this one parallels an example in the eDP spec.
165 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
167 * 270000 * 1 * 8 / 10 == 216000
169 * The actual data capacity of that configuration is 2.16Gbit/s, so the
170 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
171 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
172 * 119000. At 18bpp that's 2142000 kilobits per second.
174 * Thus the strange-looking division by 10 in intel_dp_link_required, to
175 * get the result in decakilobits instead of kilobits.
179 intel_dp_link_required(int pixel_clock
, int bpp
)
181 return (pixel_clock
* bpp
+ 9) / 10;
185 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
187 return (max_link_clock
* max_lanes
* 8) / 10;
190 static enum drm_mode_status
191 intel_dp_mode_valid(struct drm_connector
*connector
,
192 struct drm_display_mode
*mode
)
194 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
195 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
196 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
197 int target_clock
= mode
->clock
;
198 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
200 if (is_edp(intel_dp
) && fixed_mode
) {
201 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
204 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
207 target_clock
= fixed_mode
->clock
;
210 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
211 max_lanes
= intel_dp_max_lane_count(intel_dp
);
213 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
214 mode_rate
= intel_dp_link_required(target_clock
, 18);
216 if (mode_rate
> max_rate
)
217 return MODE_CLOCK_HIGH
;
219 if (mode
->clock
< 10000)
220 return MODE_CLOCK_LOW
;
222 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
223 return MODE_H_ILLEGAL
;
229 pack_aux(const uint8_t *src
, int src_bytes
)
236 for (i
= 0; i
< src_bytes
; i
++)
237 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
242 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
247 for (i
= 0; i
< dst_bytes
; i
++)
248 dst
[i
] = src
>> ((3-i
) * 8);
251 /* hrawclock is 1/4 the FSB frequency */
253 intel_hrawclk(struct drm_device
*dev
)
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev
))
262 clkcfg
= I915_READ(CLKCFG
);
263 switch (clkcfg
& CLKCFG_FSB_MASK
) {
272 case CLKCFG_FSB_1067
:
274 case CLKCFG_FSB_1333
:
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600
:
278 case CLKCFG_FSB_1600_ALT
:
286 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
287 struct intel_dp
*intel_dp
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
);
292 static void pps_lock(struct intel_dp
*intel_dp
)
294 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
295 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
296 struct drm_device
*dev
= encoder
->base
.dev
;
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 enum intel_display_power_domain power_domain
;
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
304 power_domain
= intel_display_port_power_domain(encoder
);
305 intel_display_power_get(dev_priv
, power_domain
);
307 mutex_lock(&dev_priv
->pps_mutex
);
310 static void pps_unlock(struct intel_dp
*intel_dp
)
312 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
313 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
314 struct drm_device
*dev
= encoder
->base
.dev
;
315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 enum intel_display_power_domain power_domain
;
318 mutex_unlock(&dev_priv
->pps_mutex
);
320 power_domain
= intel_display_port_power_domain(encoder
);
321 intel_display_power_put(dev_priv
, power_domain
);
325 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
327 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
328 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
330 struct intel_encoder
*encoder
;
331 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
333 lockdep_assert_held(&dev_priv
->pps_mutex
);
335 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
336 return intel_dp
->pps_pipe
;
339 * We don't have power sequencer currently.
340 * Pick one that's not used by other ports.
342 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
344 struct intel_dp
*tmp
;
346 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
349 tmp
= enc_to_intel_dp(&encoder
->base
);
351 if (tmp
->pps_pipe
!= INVALID_PIPE
)
352 pipes
&= ~(1 << tmp
->pps_pipe
);
356 * Didn't find one. This should not happen since there
357 * are two power sequencers and up to two eDP ports.
359 if (WARN_ON(pipes
== 0))
362 intel_dp
->pps_pipe
= ffs(pipes
) - 1;
364 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
365 pipe_name(intel_dp
->pps_pipe
),
366 port_name(intel_dig_port
->port
));
368 /* init power sequencer on this pipe and port */
369 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
370 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
372 return intel_dp
->pps_pipe
;
375 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
378 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
381 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
384 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
387 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
390 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
397 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
399 vlv_pipe_check pipe_check
)
403 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
404 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
405 PANEL_PORT_SELECT_MASK
;
407 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
410 if (!pipe_check(dev_priv
, pipe
))
420 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
422 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
423 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
425 enum port port
= intel_dig_port
->port
;
427 lockdep_assert_held(&dev_priv
->pps_mutex
);
429 /* try to find a pipe with this port selected */
430 /* first pick one where the panel is on */
431 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
433 /* didn't find one? pick one where vdd is on */
434 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
435 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
436 vlv_pipe_has_vdd_on
);
437 /* didn't find one? pick one with just the correct port */
438 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
439 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
442 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
443 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
444 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
450 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
452 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
453 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
456 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
458 struct drm_device
*dev
= dev_priv
->dev
;
459 struct intel_encoder
*encoder
;
461 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
465 * We can't grab pps_mutex here due to deadlock with power_domain
466 * mutex when power_domain functions are called while holding pps_mutex.
467 * That also means that in order to use pps_pipe the code needs to
468 * hold both a power domain reference and pps_mutex, and the power domain
469 * reference get/put must be done while _not_ holding pps_mutex.
470 * pps_{lock,unlock}() do these steps in the correct order, so one
471 * should use them always.
474 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
475 struct intel_dp
*intel_dp
;
477 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
480 intel_dp
= enc_to_intel_dp(&encoder
->base
);
481 intel_dp
->pps_pipe
= INVALID_PIPE
;
485 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
487 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
489 if (HAS_PCH_SPLIT(dev
))
490 return PCH_PP_CONTROL
;
492 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
495 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
497 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
499 if (HAS_PCH_SPLIT(dev
))
500 return PCH_PP_STATUS
;
502 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
505 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
506 This function only applicable when panel PM state is not to be tracked */
507 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
510 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
512 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
515 u32 pp_ctrl_reg
, pp_div_reg
;
517 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
522 if (IS_VALLEYVIEW(dev
)) {
523 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
525 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
526 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
527 pp_div
= I915_READ(pp_div_reg
);
528 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
530 /* 0x1F write to PP_DIV_REG sets max cycle delay */
531 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
532 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
533 msleep(intel_dp
->panel_power_cycle_delay
);
536 pps_unlock(intel_dp
);
541 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
543 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
546 lockdep_assert_held(&dev_priv
->pps_mutex
);
548 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
551 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
553 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
556 lockdep_assert_held(&dev_priv
->pps_mutex
);
558 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
562 intel_dp_check_edp(struct intel_dp
*intel_dp
)
564 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
567 if (!is_edp(intel_dp
))
570 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
571 WARN(1, "eDP powered off while attempting aux channel communication.\n");
572 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
573 I915_READ(_pp_stat_reg(intel_dp
)),
574 I915_READ(_pp_ctrl_reg(intel_dp
)));
579 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
581 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
582 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
584 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
588 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
590 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
591 msecs_to_jiffies_timeout(10));
593 done
= wait_for_atomic(C
, 10) == 0;
595 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
602 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
604 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
605 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
608 * The clock divider is based off the hrawclk, and would like to run at
609 * 2MHz. So, take the hrawclk value and divide by 2 and use that
611 return index
? 0 : intel_hrawclk(dev
) / 2;
614 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
616 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
617 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
622 if (intel_dig_port
->port
== PORT_A
) {
623 if (IS_GEN6(dev
) || IS_GEN7(dev
))
624 return 200; /* SNB & IVB eDP input clock at 400Mhz */
626 return 225; /* eDP input clock at 450Mhz */
628 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
632 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
634 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
635 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
638 if (intel_dig_port
->port
== PORT_A
) {
641 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
642 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
643 /* Workaround for non-ULT HSW */
650 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
654 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
656 return index
? 0 : 100;
659 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
662 * SKL doesn't need us to program the AUX clock divider (Hardware will
663 * derive the clock from CDCLK automatically). We still implement the
664 * get_aux_clock_divider vfunc to plug-in into the existing code.
666 return index
? 0 : 1;
669 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
672 uint32_t aux_clock_divider
)
674 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
675 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
676 uint32_t precharge
, timeout
;
683 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
684 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
686 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
688 return DP_AUX_CH_CTL_SEND_BUSY
|
690 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
691 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
693 DP_AUX_CH_CTL_RECEIVE_ERROR
|
694 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
695 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
696 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
699 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
704 return DP_AUX_CH_CTL_SEND_BUSY
|
706 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
707 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
708 DP_AUX_CH_CTL_TIME_OUT_1600us
|
709 DP_AUX_CH_CTL_RECEIVE_ERROR
|
710 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
711 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
715 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
716 const uint8_t *send
, int send_bytes
,
717 uint8_t *recv
, int recv_size
)
719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
720 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
722 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
723 uint32_t ch_data
= ch_ctl
+ 4;
724 uint32_t aux_clock_divider
;
725 int i
, ret
, recv_bytes
;
728 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
734 * We will be called with VDD already enabled for dpcd/edid/oui reads.
735 * In such cases we want to leave VDD enabled and it's up to upper layers
736 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
739 vdd
= edp_panel_vdd_on(intel_dp
);
741 /* dp aux is extremely sensitive to irq latency, hence request the
742 * lowest possible wakeup latency and so prevent the cpu from going into
745 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
747 intel_dp_check_edp(intel_dp
);
749 intel_aux_display_runtime_get(dev_priv
);
751 /* Try to wait for any previous AUX channel activity */
752 for (try = 0; try < 3; try++) {
753 status
= I915_READ_NOTRACE(ch_ctl
);
754 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
760 WARN(1, "dp_aux_ch not started status 0x%08x\n",
766 /* Only 5 data registers! */
767 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
772 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
773 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
778 /* Must try at least 3 times according to DP spec */
779 for (try = 0; try < 5; try++) {
780 /* Load the send data into the aux channel data registers */
781 for (i
= 0; i
< send_bytes
; i
+= 4)
782 I915_WRITE(ch_data
+ i
,
783 pack_aux(send
+ i
, send_bytes
- i
));
785 /* Send the command and wait for it to complete */
786 I915_WRITE(ch_ctl
, send_ctl
);
788 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
790 /* Clear done status and any errors */
794 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
795 DP_AUX_CH_CTL_RECEIVE_ERROR
);
797 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
798 DP_AUX_CH_CTL_RECEIVE_ERROR
))
800 if (status
& DP_AUX_CH_CTL_DONE
)
803 if (status
& DP_AUX_CH_CTL_DONE
)
807 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
808 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
813 /* Check for timeout or receive error.
814 * Timeouts occur when the sink is not connected
816 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
817 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
822 /* Timeouts occur when the device isn't connected, so they're
823 * "normal" -- don't fill the kernel log with these */
824 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
825 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
830 /* Unload any bytes sent back from the other side */
831 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
832 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
833 if (recv_bytes
> recv_size
)
834 recv_bytes
= recv_size
;
836 for (i
= 0; i
< recv_bytes
; i
+= 4)
837 unpack_aux(I915_READ(ch_data
+ i
),
838 recv
+ i
, recv_bytes
- i
);
842 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
843 intel_aux_display_runtime_put(dev_priv
);
846 edp_panel_vdd_off(intel_dp
, false);
848 pps_unlock(intel_dp
);
853 #define BARE_ADDRESS_SIZE 3
854 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
856 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
858 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
859 uint8_t txbuf
[20], rxbuf
[20];
860 size_t txsize
, rxsize
;
863 txbuf
[0] = msg
->request
<< 4;
864 txbuf
[1] = msg
->address
>> 8;
865 txbuf
[2] = msg
->address
& 0xff;
866 txbuf
[3] = msg
->size
- 1;
868 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
869 case DP_AUX_NATIVE_WRITE
:
870 case DP_AUX_I2C_WRITE
:
871 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
874 if (WARN_ON(txsize
> 20))
877 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
879 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
881 msg
->reply
= rxbuf
[0] >> 4;
883 /* Return payload size. */
888 case DP_AUX_NATIVE_READ
:
889 case DP_AUX_I2C_READ
:
890 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
891 rxsize
= msg
->size
+ 1;
893 if (WARN_ON(rxsize
> 20))
896 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
898 msg
->reply
= rxbuf
[0] >> 4;
900 * Assume happy day, and copy the data. The caller is
901 * expected to check msg->reply before touching it.
903 * Return payload size.
906 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
919 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
921 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
922 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
923 enum port port
= intel_dig_port
->port
;
924 const char *name
= NULL
;
929 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
933 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
937 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
941 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
949 * The AUX_CTL register is usually DP_CTL + 0x10.
951 * On Haswell and Broadwell though:
952 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
953 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
955 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
957 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
958 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
960 intel_dp
->aux
.name
= name
;
961 intel_dp
->aux
.dev
= dev
->dev
;
962 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
964 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
965 connector
->base
.kdev
->kobj
.name
);
967 ret
= drm_dp_aux_register(&intel_dp
->aux
);
969 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
974 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
975 &intel_dp
->aux
.ddc
.dev
.kobj
,
976 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
978 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
979 drm_dp_aux_unregister(&intel_dp
->aux
);
984 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
986 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
988 if (!intel_connector
->mst_port
)
989 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
990 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
991 intel_connector_unregister(intel_connector
);
995 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
998 case DP_LINK_BW_1_62
:
999 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1001 case DP_LINK_BW_2_7
:
1002 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1004 case DP_LINK_BW_5_4
:
1005 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1011 intel_dp_set_clock(struct intel_encoder
*encoder
,
1012 struct intel_crtc_config
*pipe_config
, int link_bw
)
1014 struct drm_device
*dev
= encoder
->base
.dev
;
1015 const struct dp_link_dpll
*divisor
= NULL
;
1019 divisor
= gen4_dpll
;
1020 count
= ARRAY_SIZE(gen4_dpll
);
1021 } else if (HAS_PCH_SPLIT(dev
)) {
1023 count
= ARRAY_SIZE(pch_dpll
);
1024 } else if (IS_CHERRYVIEW(dev
)) {
1026 count
= ARRAY_SIZE(chv_dpll
);
1027 } else if (IS_VALLEYVIEW(dev
)) {
1029 count
= ARRAY_SIZE(vlv_dpll
);
1032 if (divisor
&& count
) {
1033 for (i
= 0; i
< count
; i
++) {
1034 if (link_bw
== divisor
[i
].link_bw
) {
1035 pipe_config
->dpll
= divisor
[i
].dpll
;
1036 pipe_config
->clock_set
= true;
1044 intel_dp_compute_config(struct intel_encoder
*encoder
,
1045 struct intel_crtc_config
*pipe_config
)
1047 struct drm_device
*dev
= encoder
->base
.dev
;
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1049 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1050 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1051 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1052 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1053 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1054 int lane_count
, clock
;
1055 int min_lane_count
= 1;
1056 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1057 /* Conveniently, the link BW constants become indices with a shift...*/
1059 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1061 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1062 int link_avail
, link_clock
;
1064 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1065 pipe_config
->has_pch_encoder
= true;
1067 pipe_config
->has_dp_encoder
= true;
1068 pipe_config
->has_drrs
= false;
1069 pipe_config
->has_audio
= intel_dp
->has_audio
;
1071 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1072 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1074 if (!HAS_PCH_SPLIT(dev
))
1075 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1076 intel_connector
->panel
.fitting_mode
);
1078 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1079 intel_connector
->panel
.fitting_mode
);
1082 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1085 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1086 "max bw %02x pixel clock %iKHz\n",
1087 max_lane_count
, bws
[max_clock
],
1088 adjusted_mode
->crtc_clock
);
1090 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1091 * bpc in between. */
1092 bpp
= pipe_config
->pipe_bpp
;
1093 if (is_edp(intel_dp
)) {
1094 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1095 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1096 dev_priv
->vbt
.edp_bpp
);
1097 bpp
= dev_priv
->vbt
.edp_bpp
;
1101 * Use the maximum clock and number of lanes the eDP panel
1102 * advertizes being capable of. The panels are generally
1103 * designed to support only a single clock and lane
1104 * configuration, and typically these values correspond to the
1105 * native resolution of the panel.
1107 min_lane_count
= max_lane_count
;
1108 min_clock
= max_clock
;
1111 for (; bpp
>= 6*3; bpp
-= 2*3) {
1112 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1115 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1116 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1117 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1118 link_avail
= intel_dp_max_data_rate(link_clock
,
1121 if (mode_rate
<= link_avail
) {
1131 if (intel_dp
->color_range_auto
) {
1134 * CEA-861-E - 5.1 Default Encoding Parameters
1135 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1137 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1138 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1140 intel_dp
->color_range
= 0;
1143 if (intel_dp
->color_range
)
1144 pipe_config
->limited_color_range
= true;
1146 intel_dp
->link_bw
= bws
[clock
];
1147 intel_dp
->lane_count
= lane_count
;
1148 pipe_config
->pipe_bpp
= bpp
;
1149 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1151 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1152 intel_dp
->link_bw
, intel_dp
->lane_count
,
1153 pipe_config
->port_clock
, bpp
);
1154 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1155 mode_rate
, link_avail
);
1157 intel_link_compute_m_n(bpp
, lane_count
,
1158 adjusted_mode
->crtc_clock
,
1159 pipe_config
->port_clock
,
1160 &pipe_config
->dp_m_n
);
1162 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1163 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1164 pipe_config
->has_drrs
= true;
1165 intel_link_compute_m_n(bpp
, lane_count
,
1166 intel_connector
->panel
.downclock_mode
->clock
,
1167 pipe_config
->port_clock
,
1168 &pipe_config
->dp_m2_n2
);
1171 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1172 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1174 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1179 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1181 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1182 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1183 struct drm_device
*dev
= crtc
->base
.dev
;
1184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1187 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1188 dpa_ctl
= I915_READ(DP_A
);
1189 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1191 if (crtc
->config
.port_clock
== 162000) {
1192 /* For a long time we've carried around a ILK-DevA w/a for the
1193 * 160MHz clock. If we're really unlucky, it's still required.
1195 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1196 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1197 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1199 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1200 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1203 I915_WRITE(DP_A
, dpa_ctl
);
1209 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1211 struct drm_device
*dev
= encoder
->base
.dev
;
1212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1213 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1214 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1215 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1216 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1219 * There are four kinds of DP registers:
1226 * IBX PCH and CPU are the same for almost everything,
1227 * except that the CPU DP PLL is configured in this
1230 * CPT PCH is quite different, having many bits moved
1231 * to the TRANS_DP_CTL register instead. That
1232 * configuration happens (oddly) in ironlake_pch_enable
1235 /* Preserve the BIOS-computed detected bit. This is
1236 * supposed to be read-only.
1238 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1240 /* Handle DP bits in common between all three register formats */
1241 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1242 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1244 if (crtc
->config
.has_audio
) {
1245 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1246 pipe_name(crtc
->pipe
));
1247 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1248 intel_write_eld(encoder
);
1251 /* Split out the IBX/CPU vs CPT settings */
1253 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1254 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1255 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1256 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1257 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1258 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1260 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1261 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1263 intel_dp
->DP
|= crtc
->pipe
<< 29;
1264 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1265 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1266 intel_dp
->DP
|= intel_dp
->color_range
;
1268 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1269 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1270 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1271 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1272 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1274 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1275 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1277 if (!IS_CHERRYVIEW(dev
)) {
1278 if (crtc
->pipe
== 1)
1279 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1281 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1284 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1288 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1289 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1291 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1292 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1294 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1295 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1297 static void wait_panel_status(struct intel_dp
*intel_dp
,
1301 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1303 u32 pp_stat_reg
, pp_ctrl_reg
;
1305 lockdep_assert_held(&dev_priv
->pps_mutex
);
1307 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1308 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1310 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1312 I915_READ(pp_stat_reg
),
1313 I915_READ(pp_ctrl_reg
));
1315 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1316 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1317 I915_READ(pp_stat_reg
),
1318 I915_READ(pp_ctrl_reg
));
1321 DRM_DEBUG_KMS("Wait complete\n");
1324 static void wait_panel_on(struct intel_dp
*intel_dp
)
1326 DRM_DEBUG_KMS("Wait for panel power on\n");
1327 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1330 static void wait_panel_off(struct intel_dp
*intel_dp
)
1332 DRM_DEBUG_KMS("Wait for panel power off time\n");
1333 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1336 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1338 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1340 /* When we disable the VDD override bit last we have to do the manual
1342 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1343 intel_dp
->panel_power_cycle_delay
);
1345 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1348 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1350 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1351 intel_dp
->backlight_on_delay
);
1354 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1356 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1357 intel_dp
->backlight_off_delay
);
1360 /* Read the current pp_control value, unlocking the register if it
1364 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1366 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1370 lockdep_assert_held(&dev_priv
->pps_mutex
);
1372 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1373 control
&= ~PANEL_UNLOCK_MASK
;
1374 control
|= PANEL_UNLOCK_REGS
;
1379 * Must be paired with edp_panel_vdd_off().
1380 * Must hold pps_mutex around the whole on/off sequence.
1381 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1383 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1385 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1386 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1387 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1389 enum intel_display_power_domain power_domain
;
1391 u32 pp_stat_reg
, pp_ctrl_reg
;
1392 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1394 lockdep_assert_held(&dev_priv
->pps_mutex
);
1396 if (!is_edp(intel_dp
))
1399 intel_dp
->want_panel_vdd
= true;
1401 if (edp_have_panel_vdd(intel_dp
))
1402 return need_to_disable
;
1404 power_domain
= intel_display_port_power_domain(intel_encoder
);
1405 intel_display_power_get(dev_priv
, power_domain
);
1407 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1409 if (!edp_have_panel_power(intel_dp
))
1410 wait_panel_power_cycle(intel_dp
);
1412 pp
= ironlake_get_pp_control(intel_dp
);
1413 pp
|= EDP_FORCE_VDD
;
1415 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1416 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1418 I915_WRITE(pp_ctrl_reg
, pp
);
1419 POSTING_READ(pp_ctrl_reg
);
1420 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1421 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1423 * If the panel wasn't on, delay before accessing aux channel
1425 if (!edp_have_panel_power(intel_dp
)) {
1426 DRM_DEBUG_KMS("eDP was not running\n");
1427 msleep(intel_dp
->panel_power_up_delay
);
1430 return need_to_disable
;
1434 * Must be paired with intel_edp_panel_vdd_off() or
1435 * intel_edp_panel_off().
1436 * Nested calls to these functions are not allowed since
1437 * we drop the lock. Caller must use some higher level
1438 * locking to prevent nested calls from other threads.
1440 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1444 if (!is_edp(intel_dp
))
1448 vdd
= edp_panel_vdd_on(intel_dp
);
1449 pps_unlock(intel_dp
);
1451 WARN(!vdd
, "eDP VDD already requested on\n");
1454 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1456 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1458 struct intel_digital_port
*intel_dig_port
=
1459 dp_to_dig_port(intel_dp
);
1460 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1461 enum intel_display_power_domain power_domain
;
1463 u32 pp_stat_reg
, pp_ctrl_reg
;
1465 lockdep_assert_held(&dev_priv
->pps_mutex
);
1467 WARN_ON(intel_dp
->want_panel_vdd
);
1469 if (!edp_have_panel_vdd(intel_dp
))
1472 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1474 pp
= ironlake_get_pp_control(intel_dp
);
1475 pp
&= ~EDP_FORCE_VDD
;
1477 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1478 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1480 I915_WRITE(pp_ctrl_reg
, pp
);
1481 POSTING_READ(pp_ctrl_reg
);
1483 /* Make sure sequencer is idle before allowing subsequent activity */
1484 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1485 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1487 if ((pp
& POWER_TARGET_ON
) == 0)
1488 intel_dp
->last_power_cycle
= jiffies
;
1490 power_domain
= intel_display_port_power_domain(intel_encoder
);
1491 intel_display_power_put(dev_priv
, power_domain
);
1494 static void edp_panel_vdd_work(struct work_struct
*__work
)
1496 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1497 struct intel_dp
, panel_vdd_work
);
1500 if (!intel_dp
->want_panel_vdd
)
1501 edp_panel_vdd_off_sync(intel_dp
);
1502 pps_unlock(intel_dp
);
1505 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1507 unsigned long delay
;
1510 * Queue the timer to fire a long time from now (relative to the power
1511 * down delay) to keep the panel power up across a sequence of
1514 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1515 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1519 * Must be paired with edp_panel_vdd_on().
1520 * Must hold pps_mutex around the whole on/off sequence.
1521 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1523 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1525 struct drm_i915_private
*dev_priv
=
1526 intel_dp_to_dev(intel_dp
)->dev_private
;
1528 lockdep_assert_held(&dev_priv
->pps_mutex
);
1530 if (!is_edp(intel_dp
))
1533 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1535 intel_dp
->want_panel_vdd
= false;
1538 edp_panel_vdd_off_sync(intel_dp
);
1540 edp_panel_vdd_schedule_off(intel_dp
);
1543 static void edp_panel_on(struct intel_dp
*intel_dp
)
1545 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1550 lockdep_assert_held(&dev_priv
->pps_mutex
);
1552 if (!is_edp(intel_dp
))
1555 DRM_DEBUG_KMS("Turn eDP power on\n");
1557 if (edp_have_panel_power(intel_dp
)) {
1558 DRM_DEBUG_KMS("eDP power already on\n");
1562 wait_panel_power_cycle(intel_dp
);
1564 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1565 pp
= ironlake_get_pp_control(intel_dp
);
1567 /* ILK workaround: disable reset around power sequence */
1568 pp
&= ~PANEL_POWER_RESET
;
1569 I915_WRITE(pp_ctrl_reg
, pp
);
1570 POSTING_READ(pp_ctrl_reg
);
1573 pp
|= POWER_TARGET_ON
;
1575 pp
|= PANEL_POWER_RESET
;
1577 I915_WRITE(pp_ctrl_reg
, pp
);
1578 POSTING_READ(pp_ctrl_reg
);
1580 wait_panel_on(intel_dp
);
1581 intel_dp
->last_power_on
= jiffies
;
1584 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1585 I915_WRITE(pp_ctrl_reg
, pp
);
1586 POSTING_READ(pp_ctrl_reg
);
1590 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1592 if (!is_edp(intel_dp
))
1596 edp_panel_on(intel_dp
);
1597 pps_unlock(intel_dp
);
1601 static void edp_panel_off(struct intel_dp
*intel_dp
)
1603 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1604 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1605 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1607 enum intel_display_power_domain power_domain
;
1611 lockdep_assert_held(&dev_priv
->pps_mutex
);
1613 if (!is_edp(intel_dp
))
1616 DRM_DEBUG_KMS("Turn eDP power off\n");
1618 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1620 pp
= ironlake_get_pp_control(intel_dp
);
1621 /* We need to switch off panel power _and_ force vdd, for otherwise some
1622 * panels get very unhappy and cease to work. */
1623 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1626 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1628 intel_dp
->want_panel_vdd
= false;
1630 I915_WRITE(pp_ctrl_reg
, pp
);
1631 POSTING_READ(pp_ctrl_reg
);
1633 intel_dp
->last_power_cycle
= jiffies
;
1634 wait_panel_off(intel_dp
);
1636 /* We got a reference when we enabled the VDD. */
1637 power_domain
= intel_display_port_power_domain(intel_encoder
);
1638 intel_display_power_put(dev_priv
, power_domain
);
1641 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1643 if (!is_edp(intel_dp
))
1647 edp_panel_off(intel_dp
);
1648 pps_unlock(intel_dp
);
1651 /* Enable backlight in the panel power control. */
1652 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1654 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1655 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1661 * If we enable the backlight right away following a panel power
1662 * on, we may see slight flicker as the panel syncs with the eDP
1663 * link. So delay a bit to make sure the image is solid before
1664 * allowing it to appear.
1666 wait_backlight_on(intel_dp
);
1670 pp
= ironlake_get_pp_control(intel_dp
);
1671 pp
|= EDP_BLC_ENABLE
;
1673 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1675 I915_WRITE(pp_ctrl_reg
, pp
);
1676 POSTING_READ(pp_ctrl_reg
);
1678 pps_unlock(intel_dp
);
1681 /* Enable backlight PWM and backlight PP control. */
1682 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1684 if (!is_edp(intel_dp
))
1687 DRM_DEBUG_KMS("\n");
1689 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1690 _intel_edp_backlight_on(intel_dp
);
1693 /* Disable backlight in the panel power control. */
1694 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1696 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1701 if (!is_edp(intel_dp
))
1706 pp
= ironlake_get_pp_control(intel_dp
);
1707 pp
&= ~EDP_BLC_ENABLE
;
1709 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1711 I915_WRITE(pp_ctrl_reg
, pp
);
1712 POSTING_READ(pp_ctrl_reg
);
1714 pps_unlock(intel_dp
);
1716 intel_dp
->last_backlight_off
= jiffies
;
1717 edp_wait_backlight_off(intel_dp
);
1720 /* Disable backlight PP control and backlight PWM. */
1721 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1723 if (!is_edp(intel_dp
))
1726 DRM_DEBUG_KMS("\n");
1728 _intel_edp_backlight_off(intel_dp
);
1729 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1733 * Hook for controlling the panel power control backlight through the bl_power
1734 * sysfs attribute. Take care to handle multiple calls.
1736 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1739 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1743 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1744 pps_unlock(intel_dp
);
1746 if (is_enabled
== enable
)
1749 DRM_DEBUG_KMS("panel power control backlight %s\n",
1750 enable
? "enable" : "disable");
1753 _intel_edp_backlight_on(intel_dp
);
1755 _intel_edp_backlight_off(intel_dp
);
1758 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1760 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1761 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1762 struct drm_device
*dev
= crtc
->dev
;
1763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 assert_pipe_disabled(dev_priv
,
1767 to_intel_crtc(crtc
)->pipe
);
1769 DRM_DEBUG_KMS("\n");
1770 dpa_ctl
= I915_READ(DP_A
);
1771 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1772 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1774 /* We don't adjust intel_dp->DP while tearing down the link, to
1775 * facilitate link retraining (e.g. after hotplug). Hence clear all
1776 * enable bits here to ensure that we don't enable too much. */
1777 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1778 intel_dp
->DP
|= DP_PLL_ENABLE
;
1779 I915_WRITE(DP_A
, intel_dp
->DP
);
1784 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1786 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1787 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1788 struct drm_device
*dev
= crtc
->dev
;
1789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1792 assert_pipe_disabled(dev_priv
,
1793 to_intel_crtc(crtc
)->pipe
);
1795 dpa_ctl
= I915_READ(DP_A
);
1796 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1797 "dp pll off, should be on\n");
1798 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1800 /* We can't rely on the value tracked for the DP register in
1801 * intel_dp->DP because link_down must not change that (otherwise link
1802 * re-training will fail. */
1803 dpa_ctl
&= ~DP_PLL_ENABLE
;
1804 I915_WRITE(DP_A
, dpa_ctl
);
1809 /* If the sink supports it, try to set the power state appropriately */
1810 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1814 /* Should have a valid DPCD by this point */
1815 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1818 if (mode
!= DRM_MODE_DPMS_ON
) {
1819 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1823 * When turning on, we need to retry for 1ms to give the sink
1826 for (i
= 0; i
< 3; i
++) {
1827 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1836 DRM_DEBUG_KMS("failed to %s sink power state\n",
1837 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1840 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1843 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1844 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1845 struct drm_device
*dev
= encoder
->base
.dev
;
1846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1847 enum intel_display_power_domain power_domain
;
1850 power_domain
= intel_display_port_power_domain(encoder
);
1851 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1854 tmp
= I915_READ(intel_dp
->output_reg
);
1856 if (!(tmp
& DP_PORT_EN
))
1859 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1860 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1861 } else if (IS_CHERRYVIEW(dev
)) {
1862 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1863 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1864 *pipe
= PORT_TO_PIPE(tmp
);
1870 switch (intel_dp
->output_reg
) {
1872 trans_sel
= TRANS_DP_PORT_SEL_B
;
1875 trans_sel
= TRANS_DP_PORT_SEL_C
;
1878 trans_sel
= TRANS_DP_PORT_SEL_D
;
1884 for_each_pipe(dev_priv
, i
) {
1885 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1886 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1892 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1893 intel_dp
->output_reg
);
1899 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1900 struct intel_crtc_config
*pipe_config
)
1902 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1904 struct drm_device
*dev
= encoder
->base
.dev
;
1905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1906 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1907 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1910 tmp
= I915_READ(intel_dp
->output_reg
);
1911 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1912 pipe_config
->has_audio
= true;
1914 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1915 if (tmp
& DP_SYNC_HS_HIGH
)
1916 flags
|= DRM_MODE_FLAG_PHSYNC
;
1918 flags
|= DRM_MODE_FLAG_NHSYNC
;
1920 if (tmp
& DP_SYNC_VS_HIGH
)
1921 flags
|= DRM_MODE_FLAG_PVSYNC
;
1923 flags
|= DRM_MODE_FLAG_NVSYNC
;
1925 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1926 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1927 flags
|= DRM_MODE_FLAG_PHSYNC
;
1929 flags
|= DRM_MODE_FLAG_NHSYNC
;
1931 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1932 flags
|= DRM_MODE_FLAG_PVSYNC
;
1934 flags
|= DRM_MODE_FLAG_NVSYNC
;
1937 pipe_config
->adjusted_mode
.flags
|= flags
;
1939 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1940 tmp
& DP_COLOR_RANGE_16_235
)
1941 pipe_config
->limited_color_range
= true;
1943 pipe_config
->has_dp_encoder
= true;
1945 intel_dp_get_m_n(crtc
, pipe_config
);
1947 if (port
== PORT_A
) {
1948 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1949 pipe_config
->port_clock
= 162000;
1951 pipe_config
->port_clock
= 270000;
1954 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1955 &pipe_config
->dp_m_n
);
1957 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1958 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1960 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1962 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1963 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1965 * This is a big fat ugly hack.
1967 * Some machines in UEFI boot mode provide us a VBT that has 18
1968 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1969 * unknown we fail to light up. Yet the same BIOS boots up with
1970 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1971 * max, not what it tells us to use.
1973 * Note: This will still be broken if the eDP panel is not lit
1974 * up by the BIOS, and thus we can't get the mode at module
1977 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1978 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1979 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1983 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1985 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1988 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1995 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1998 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1999 struct edp_vsc_psr
*vsc_psr
)
2001 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2002 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2004 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
2005 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
2006 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
2007 uint32_t *data
= (uint32_t *) vsc_psr
;
2010 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2011 the video DIP being updated before program video DIP data buffer
2012 registers for DIP being updated. */
2013 I915_WRITE(ctl_reg
, 0);
2014 POSTING_READ(ctl_reg
);
2016 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
2017 if (i
< sizeof(struct edp_vsc_psr
))
2018 I915_WRITE(data_reg
+ i
, *data
++);
2020 I915_WRITE(data_reg
+ i
, 0);
2023 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
2024 POSTING_READ(ctl_reg
);
2027 static void intel_edp_psr_setup_vsc(struct intel_dp
*intel_dp
)
2029 struct edp_vsc_psr psr_vsc
;
2031 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2032 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
2033 psr_vsc
.sdp_header
.HB0
= 0;
2034 psr_vsc
.sdp_header
.HB1
= 0x7;
2035 psr_vsc
.sdp_header
.HB2
= 0x2;
2036 psr_vsc
.sdp_header
.HB3
= 0x8;
2037 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
2040 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
2042 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2043 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2045 uint32_t aux_clock_divider
;
2046 int precharge
= 0x3;
2047 bool only_standby
= false;
2048 static const uint8_t aux_msg
[] = {
2049 [0] = DP_AUX_NATIVE_WRITE
<< 4,
2050 [1] = DP_SET_POWER
>> 8,
2051 [2] = DP_SET_POWER
& 0xff,
2053 [4] = DP_SET_POWER_D0
,
2057 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
2059 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
2061 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2062 only_standby
= true;
2064 /* Enable PSR in sink */
2065 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
2066 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2067 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
2069 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2070 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
2072 /* Setup AUX registers */
2073 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
2074 I915_WRITE(EDP_PSR_AUX_DATA1(dev
) + i
,
2075 pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
2077 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
2078 DP_AUX_CH_CTL_TIME_OUT_400us
|
2079 (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
2080 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
2081 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
2084 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
2086 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2087 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2089 uint32_t max_sleep_time
= 0x1f;
2090 uint32_t idle_frames
= 1;
2092 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
2093 bool only_standby
= false;
2095 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2096 only_standby
= true;
2098 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
2099 val
|= EDP_PSR_LINK_STANDBY
;
2100 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
2101 val
|= EDP_PSR_TP1_TIME_0us
;
2102 val
|= EDP_PSR_SKIP_AUX_EXIT
;
2103 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
2105 val
|= EDP_PSR_LINK_DISABLE
;
2107 I915_WRITE(EDP_PSR_CTL(dev
), val
|
2108 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
2109 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
2110 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
2114 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
2116 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2117 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2119 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
2120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2122 lockdep_assert_held(&dev_priv
->psr
.lock
);
2123 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
2124 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
2126 dev_priv
->psr
.source_ok
= false;
2128 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
2129 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2133 if (!i915
.enable_psr
) {
2134 DRM_DEBUG_KMS("PSR disable by flag\n");
2138 /* Below limitations aren't valid for Broadwell */
2139 if (IS_BROADWELL(dev
))
2142 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
2144 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2148 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2149 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2154 dev_priv
->psr
.source_ok
= true;
2158 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
2160 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2161 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2164 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2165 WARN_ON(dev_priv
->psr
.active
);
2166 lockdep_assert_held(&dev_priv
->psr
.lock
);
2168 /* Enable/Re-enable PSR on the host */
2169 intel_edp_psr_enable_source(intel_dp
);
2171 dev_priv
->psr
.active
= true;
2174 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
2176 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2179 if (!HAS_PSR(dev
)) {
2180 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2184 if (!is_edp_psr(intel_dp
)) {
2185 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2189 mutex_lock(&dev_priv
->psr
.lock
);
2190 if (dev_priv
->psr
.enabled
) {
2191 DRM_DEBUG_KMS("PSR already in use\n");
2195 if (!intel_edp_psr_match_conditions(intel_dp
))
2198 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
2200 intel_edp_psr_setup_vsc(intel_dp
);
2202 /* Avoid continuous PSR exit by masking memup and hpd */
2203 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
2204 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
2206 /* Enable PSR on the panel */
2207 intel_edp_psr_enable_sink(intel_dp
);
2209 dev_priv
->psr
.enabled
= intel_dp
;
2211 mutex_unlock(&dev_priv
->psr
.lock
);
2214 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
2216 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2219 mutex_lock(&dev_priv
->psr
.lock
);
2220 if (!dev_priv
->psr
.enabled
) {
2221 mutex_unlock(&dev_priv
->psr
.lock
);
2225 if (dev_priv
->psr
.active
) {
2226 I915_WRITE(EDP_PSR_CTL(dev
),
2227 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
2229 /* Wait till PSR is idle */
2230 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
2231 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
2232 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2234 dev_priv
->psr
.active
= false;
2236 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2239 dev_priv
->psr
.enabled
= NULL
;
2240 mutex_unlock(&dev_priv
->psr
.lock
);
2242 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
2245 static void intel_edp_psr_work(struct work_struct
*work
)
2247 struct drm_i915_private
*dev_priv
=
2248 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
2249 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
2251 /* We have to make sure PSR is ready for re-enable
2252 * otherwise it keeps disabled until next full enable/disable cycle.
2253 * PSR might take some time to get fully disabled
2254 * and be ready for re-enable.
2256 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv
->dev
)) &
2257 EDP_PSR_STATUS_STATE_MASK
) == 0, 50)) {
2258 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2262 mutex_lock(&dev_priv
->psr
.lock
);
2263 intel_dp
= dev_priv
->psr
.enabled
;
2269 * The delayed work can race with an invalidate hence we need to
2270 * recheck. Since psr_flush first clears this and then reschedules we
2271 * won't ever miss a flush when bailing out here.
2273 if (dev_priv
->psr
.busy_frontbuffer_bits
)
2276 intel_edp_psr_do_enable(intel_dp
);
2278 mutex_unlock(&dev_priv
->psr
.lock
);
2281 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
2283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2285 if (dev_priv
->psr
.active
) {
2286 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
2288 WARN_ON(!(val
& EDP_PSR_ENABLE
));
2290 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
2292 dev_priv
->psr
.active
= false;
2297 void intel_edp_psr_invalidate(struct drm_device
*dev
,
2298 unsigned frontbuffer_bits
)
2300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2301 struct drm_crtc
*crtc
;
2304 mutex_lock(&dev_priv
->psr
.lock
);
2305 if (!dev_priv
->psr
.enabled
) {
2306 mutex_unlock(&dev_priv
->psr
.lock
);
2310 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2311 pipe
= to_intel_crtc(crtc
)->pipe
;
2313 intel_edp_psr_do_exit(dev
);
2315 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2317 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2318 mutex_unlock(&dev_priv
->psr
.lock
);
2321 void intel_edp_psr_flush(struct drm_device
*dev
,
2322 unsigned frontbuffer_bits
)
2324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2325 struct drm_crtc
*crtc
;
2328 mutex_lock(&dev_priv
->psr
.lock
);
2329 if (!dev_priv
->psr
.enabled
) {
2330 mutex_unlock(&dev_priv
->psr
.lock
);
2334 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2335 pipe
= to_intel_crtc(crtc
)->pipe
;
2336 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2339 * On Haswell sprite plane updates don't result in a psr invalidating
2340 * signal in the hardware. Which means we need to manually fake this in
2341 * software for all flushes, not just when we've seen a preceding
2342 * invalidation through frontbuffer rendering.
2344 if (IS_HASWELL(dev
) &&
2345 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2346 intel_edp_psr_do_exit(dev
);
2348 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2349 schedule_delayed_work(&dev_priv
->psr
.work
,
2350 msecs_to_jiffies(100));
2351 mutex_unlock(&dev_priv
->psr
.lock
);
2354 void intel_edp_psr_init(struct drm_device
*dev
)
2356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2358 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2359 mutex_init(&dev_priv
->psr
.lock
);
2362 static void intel_disable_dp(struct intel_encoder
*encoder
)
2364 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2365 struct drm_device
*dev
= encoder
->base
.dev
;
2367 /* Make sure the panel is off before trying to change the mode. But also
2368 * ensure that we have vdd while we switch off the panel. */
2369 intel_edp_panel_vdd_on(intel_dp
);
2370 intel_edp_backlight_off(intel_dp
);
2371 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2372 intel_edp_panel_off(intel_dp
);
2374 /* disable the port before the pipe on g4x */
2375 if (INTEL_INFO(dev
)->gen
< 5)
2376 intel_dp_link_down(intel_dp
);
2379 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2381 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2382 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2384 intel_dp_link_down(intel_dp
);
2386 ironlake_edp_pll_off(intel_dp
);
2389 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2391 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2393 intel_dp_link_down(intel_dp
);
2396 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2398 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2399 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2400 struct drm_device
*dev
= encoder
->base
.dev
;
2401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2402 struct intel_crtc
*intel_crtc
=
2403 to_intel_crtc(encoder
->base
.crtc
);
2404 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2405 enum pipe pipe
= intel_crtc
->pipe
;
2408 intel_dp_link_down(intel_dp
);
2410 mutex_lock(&dev_priv
->dpio_lock
);
2412 /* Propagate soft reset to data lane reset */
2413 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2414 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2415 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2417 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2418 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2419 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2421 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2422 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2423 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2425 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2426 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2427 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2429 mutex_unlock(&dev_priv
->dpio_lock
);
2433 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2435 uint8_t dp_train_pat
)
2437 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2438 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2440 enum port port
= intel_dig_port
->port
;
2443 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2445 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2446 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2448 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2450 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2451 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2452 case DP_TRAINING_PATTERN_DISABLE
:
2453 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2456 case DP_TRAINING_PATTERN_1
:
2457 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2459 case DP_TRAINING_PATTERN_2
:
2460 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2462 case DP_TRAINING_PATTERN_3
:
2463 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2466 I915_WRITE(DP_TP_CTL(port
), temp
);
2468 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2469 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2471 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2472 case DP_TRAINING_PATTERN_DISABLE
:
2473 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2475 case DP_TRAINING_PATTERN_1
:
2476 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2478 case DP_TRAINING_PATTERN_2
:
2479 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2481 case DP_TRAINING_PATTERN_3
:
2482 DRM_ERROR("DP training pattern 3 not supported\n");
2483 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2488 if (IS_CHERRYVIEW(dev
))
2489 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2491 *DP
&= ~DP_LINK_TRAIN_MASK
;
2493 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2494 case DP_TRAINING_PATTERN_DISABLE
:
2495 *DP
|= DP_LINK_TRAIN_OFF
;
2497 case DP_TRAINING_PATTERN_1
:
2498 *DP
|= DP_LINK_TRAIN_PAT_1
;
2500 case DP_TRAINING_PATTERN_2
:
2501 *DP
|= DP_LINK_TRAIN_PAT_2
;
2503 case DP_TRAINING_PATTERN_3
:
2504 if (IS_CHERRYVIEW(dev
)) {
2505 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2507 DRM_ERROR("DP training pattern 3 not supported\n");
2508 *DP
|= DP_LINK_TRAIN_PAT_2
;
2515 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2517 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2520 intel_dp
->DP
|= DP_PORT_EN
;
2522 /* enable with pattern 1 (as per spec) */
2523 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2524 DP_TRAINING_PATTERN_1
);
2526 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2527 POSTING_READ(intel_dp
->output_reg
);
2530 static void intel_enable_dp(struct intel_encoder
*encoder
)
2532 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2533 struct drm_device
*dev
= encoder
->base
.dev
;
2534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2535 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2537 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2542 if (IS_VALLEYVIEW(dev
))
2543 vlv_init_panel_power_sequencer(intel_dp
);
2545 intel_dp_enable_port(intel_dp
);
2547 edp_panel_vdd_on(intel_dp
);
2548 edp_panel_on(intel_dp
);
2549 edp_panel_vdd_off(intel_dp
, true);
2551 pps_unlock(intel_dp
);
2553 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2554 intel_dp_start_link_train(intel_dp
);
2555 intel_dp_complete_link_train(intel_dp
);
2556 intel_dp_stop_link_train(intel_dp
);
2559 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2561 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2563 intel_enable_dp(encoder
);
2564 intel_edp_backlight_on(intel_dp
);
2567 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2569 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2571 intel_edp_backlight_on(intel_dp
);
2574 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2576 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2577 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2579 intel_dp_prepare(encoder
);
2581 /* Only ilk+ has port A */
2582 if (dport
->port
== PORT_A
) {
2583 ironlake_set_pll_cpu_edp(intel_dp
);
2584 ironlake_edp_pll_on(intel_dp
);
2588 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2592 struct intel_encoder
*encoder
;
2594 lockdep_assert_held(&dev_priv
->pps_mutex
);
2596 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2598 struct intel_dp
*intel_dp
;
2601 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2604 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2605 port
= dp_to_dig_port(intel_dp
)->port
;
2607 if (intel_dp
->pps_pipe
!= pipe
)
2610 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2611 pipe_name(pipe
), port_name(port
));
2613 /* make sure vdd is off before we steal it */
2614 edp_panel_vdd_off_sync(intel_dp
);
2616 intel_dp
->pps_pipe
= INVALID_PIPE
;
2620 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2622 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2623 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2624 struct drm_device
*dev
= encoder
->base
.dev
;
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2626 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2628 lockdep_assert_held(&dev_priv
->pps_mutex
);
2630 if (!is_edp(intel_dp
))
2633 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2637 * If another power sequencer was being used on this
2638 * port previously make sure to turn off vdd there while
2639 * we still have control of it.
2641 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2642 edp_panel_vdd_off_sync(intel_dp
);
2645 * We may be stealing the power
2646 * sequencer from another port.
2648 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2650 /* now it's all ours */
2651 intel_dp
->pps_pipe
= crtc
->pipe
;
2653 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2654 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2656 /* init power sequencer on this pipe and port */
2657 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2658 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2661 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2663 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2664 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2665 struct drm_device
*dev
= encoder
->base
.dev
;
2666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2667 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2668 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2669 int pipe
= intel_crtc
->pipe
;
2672 mutex_lock(&dev_priv
->dpio_lock
);
2674 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2681 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2682 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2683 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2685 mutex_unlock(&dev_priv
->dpio_lock
);
2687 intel_enable_dp(encoder
);
2689 vlv_wait_port_ready(dev_priv
, dport
);
2692 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2694 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2695 struct drm_device
*dev
= encoder
->base
.dev
;
2696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2697 struct intel_crtc
*intel_crtc
=
2698 to_intel_crtc(encoder
->base
.crtc
);
2699 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2700 int pipe
= intel_crtc
->pipe
;
2702 intel_dp_prepare(encoder
);
2704 /* Program Tx lane resets to default */
2705 mutex_lock(&dev_priv
->dpio_lock
);
2706 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2707 DPIO_PCS_TX_LANE2_RESET
|
2708 DPIO_PCS_TX_LANE1_RESET
);
2709 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2710 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2711 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2712 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2713 DPIO_PCS_CLK_SOFT_RESET
);
2715 /* Fix up inter-pair skew failure */
2716 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2717 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2718 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2719 mutex_unlock(&dev_priv
->dpio_lock
);
2722 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2724 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2725 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2726 struct drm_device
*dev
= encoder
->base
.dev
;
2727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2728 struct intel_crtc
*intel_crtc
=
2729 to_intel_crtc(encoder
->base
.crtc
);
2730 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2731 int pipe
= intel_crtc
->pipe
;
2735 mutex_lock(&dev_priv
->dpio_lock
);
2737 /* allow hardware to manage TX FIFO reset source */
2738 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2739 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2740 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2742 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2743 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2744 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2746 /* Deassert soft data lane reset*/
2747 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2748 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2749 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2751 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2752 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2753 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2755 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2756 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2757 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2759 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2760 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2761 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2763 /* Program Tx lane latency optimal setting*/
2764 for (i
= 0; i
< 4; i
++) {
2765 /* Set the latency optimal bit */
2766 data
= (i
== 1) ? 0x0 : 0x6;
2767 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2768 data
<< DPIO_FRC_LATENCY_SHFIT
);
2770 /* Set the upar bit */
2771 data
= (i
== 1) ? 0x0 : 0x1;
2772 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2773 data
<< DPIO_UPAR_SHIFT
);
2776 /* Data lane stagger programming */
2777 /* FIXME: Fix up value only after power analysis */
2779 mutex_unlock(&dev_priv
->dpio_lock
);
2781 intel_enable_dp(encoder
);
2783 vlv_wait_port_ready(dev_priv
, dport
);
2786 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2788 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2789 struct drm_device
*dev
= encoder
->base
.dev
;
2790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2791 struct intel_crtc
*intel_crtc
=
2792 to_intel_crtc(encoder
->base
.crtc
);
2793 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2794 enum pipe pipe
= intel_crtc
->pipe
;
2797 intel_dp_prepare(encoder
);
2799 mutex_lock(&dev_priv
->dpio_lock
);
2801 /* program left/right clock distribution */
2802 if (pipe
!= PIPE_B
) {
2803 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2804 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2806 val
|= CHV_BUFLEFTENA1_FORCE
;
2808 val
|= CHV_BUFRIGHTENA1_FORCE
;
2809 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2811 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2812 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2814 val
|= CHV_BUFLEFTENA2_FORCE
;
2816 val
|= CHV_BUFRIGHTENA2_FORCE
;
2817 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2820 /* program clock channel usage */
2821 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2822 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2824 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2826 val
|= CHV_PCS_USEDCLKCHANNEL
;
2827 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2829 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2830 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2832 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2834 val
|= CHV_PCS_USEDCLKCHANNEL
;
2835 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2838 * This a a bit weird since generally CL
2839 * matches the pipe, but here we need to
2840 * pick the CL based on the port.
2842 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2844 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2846 val
|= CHV_CMN_USEDCLKCHANNEL
;
2847 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2849 mutex_unlock(&dev_priv
->dpio_lock
);
2853 * Native read with retry for link status and receiver capability reads for
2854 * cases where the sink may still be asleep.
2856 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2857 * supposed to retry 3 times per the spec.
2860 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2861 void *buffer
, size_t size
)
2866 for (i
= 0; i
< 3; i
++) {
2867 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2877 * Fetch AUX CH registers 0x202 - 0x207 which contain
2878 * link status information
2881 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2883 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2886 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2889 /* These are source-specific values. */
2891 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2893 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2894 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2896 if (INTEL_INFO(dev
)->gen
>= 9)
2897 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2898 else if (IS_VALLEYVIEW(dev
))
2899 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2900 else if (IS_GEN7(dev
) && port
== PORT_A
)
2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2902 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2903 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2905 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2909 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2911 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2912 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2914 if (INTEL_INFO(dev
)->gen
>= 9) {
2915 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2917 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2919 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2921 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2923 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2925 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2926 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2928 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2930 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2932 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2935 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2937 } else if (IS_VALLEYVIEW(dev
)) {
2938 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2940 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2941 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2942 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2944 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2949 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2950 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2952 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2954 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2955 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2957 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2960 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2962 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2964 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2969 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2974 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2976 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2978 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2979 struct intel_crtc
*intel_crtc
=
2980 to_intel_crtc(dport
->base
.base
.crtc
);
2981 unsigned long demph_reg_value
, preemph_reg_value
,
2982 uniqtranscale_reg_value
;
2983 uint8_t train_set
= intel_dp
->train_set
[0];
2984 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2985 int pipe
= intel_crtc
->pipe
;
2987 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2988 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2989 preemph_reg_value
= 0x0004000;
2990 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2992 demph_reg_value
= 0x2B405555;
2993 uniqtranscale_reg_value
= 0x552AB83A;
2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2996 demph_reg_value
= 0x2B404040;
2997 uniqtranscale_reg_value
= 0x5548B83A;
2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3000 demph_reg_value
= 0x2B245555;
3001 uniqtranscale_reg_value
= 0x5560B83A;
3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3004 demph_reg_value
= 0x2B405555;
3005 uniqtranscale_reg_value
= 0x5598DA3A;
3011 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3012 preemph_reg_value
= 0x0002000;
3013 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3015 demph_reg_value
= 0x2B404040;
3016 uniqtranscale_reg_value
= 0x5552B83A;
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3019 demph_reg_value
= 0x2B404848;
3020 uniqtranscale_reg_value
= 0x5580B83A;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3023 demph_reg_value
= 0x2B404040;
3024 uniqtranscale_reg_value
= 0x55ADDA3A;
3030 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3031 preemph_reg_value
= 0x0000000;
3032 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3034 demph_reg_value
= 0x2B305555;
3035 uniqtranscale_reg_value
= 0x5570B83A;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3038 demph_reg_value
= 0x2B2B4040;
3039 uniqtranscale_reg_value
= 0x55ADDA3A;
3045 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3046 preemph_reg_value
= 0x0006000;
3047 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3049 demph_reg_value
= 0x1B405555;
3050 uniqtranscale_reg_value
= 0x55ADDA3A;
3060 mutex_lock(&dev_priv
->dpio_lock
);
3061 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3062 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3063 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3064 uniqtranscale_reg_value
);
3065 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3066 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3067 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3068 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3069 mutex_unlock(&dev_priv
->dpio_lock
);
3074 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
3076 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3078 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3079 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3080 u32 deemph_reg_value
, margin_reg_value
, val
;
3081 uint8_t train_set
= intel_dp
->train_set
[0];
3082 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3083 enum pipe pipe
= intel_crtc
->pipe
;
3086 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3087 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3088 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3090 deemph_reg_value
= 128;
3091 margin_reg_value
= 52;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3094 deemph_reg_value
= 128;
3095 margin_reg_value
= 77;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3098 deemph_reg_value
= 128;
3099 margin_reg_value
= 102;
3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3102 deemph_reg_value
= 128;
3103 margin_reg_value
= 154;
3104 /* FIXME extra to set for 1200 */
3110 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3111 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3113 deemph_reg_value
= 85;
3114 margin_reg_value
= 78;
3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3117 deemph_reg_value
= 85;
3118 margin_reg_value
= 116;
3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3121 deemph_reg_value
= 85;
3122 margin_reg_value
= 154;
3128 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3129 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3131 deemph_reg_value
= 64;
3132 margin_reg_value
= 104;
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3135 deemph_reg_value
= 64;
3136 margin_reg_value
= 154;
3142 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3143 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3145 deemph_reg_value
= 43;
3146 margin_reg_value
= 154;
3156 mutex_lock(&dev_priv
->dpio_lock
);
3158 /* Clear calc init */
3159 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3160 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3161 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3162 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3163 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3165 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3166 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3167 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3168 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3169 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3171 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3172 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3173 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3174 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3176 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3177 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3178 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3179 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3181 /* Program swing deemph */
3182 for (i
= 0; i
< 4; i
++) {
3183 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3184 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3185 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3186 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3189 /* Program swing margin */
3190 for (i
= 0; i
< 4; i
++) {
3191 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3192 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3193 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3194 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3197 /* Disable unique transition scale */
3198 for (i
= 0; i
< 4; i
++) {
3199 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3200 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3201 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3204 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3205 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3206 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3207 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3210 * The document said it needs to set bit 27 for ch0 and bit 26
3211 * for ch1. Might be a typo in the doc.
3212 * For now, for this unique transition scale selection, set bit
3213 * 27 for ch0 and ch1.
3215 for (i
= 0; i
< 4; i
++) {
3216 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3217 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3218 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3221 for (i
= 0; i
< 4; i
++) {
3222 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3223 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3224 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3225 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3229 /* Start swing calculation */
3230 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3231 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3232 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3234 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3235 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3236 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3239 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3240 val
|= DPIO_LRC_BYPASS
;
3241 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3243 mutex_unlock(&dev_priv
->dpio_lock
);
3249 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3250 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3255 uint8_t voltage_max
;
3256 uint8_t preemph_max
;
3258 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3259 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3260 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3268 voltage_max
= intel_dp_voltage_max(intel_dp
);
3269 if (v
>= voltage_max
)
3270 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3272 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3273 if (p
>= preemph_max
)
3274 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3276 for (lane
= 0; lane
< 4; lane
++)
3277 intel_dp
->train_set
[lane
] = v
| p
;
3281 intel_gen4_signal_levels(uint8_t train_set
)
3283 uint32_t signal_levels
= 0;
3285 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3288 signal_levels
|= DP_VOLTAGE_0_4
;
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3291 signal_levels
|= DP_VOLTAGE_0_6
;
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3294 signal_levels
|= DP_VOLTAGE_0_8
;
3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3297 signal_levels
|= DP_VOLTAGE_1_2
;
3300 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3301 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3303 signal_levels
|= DP_PRE_EMPHASIS_0
;
3305 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3306 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3308 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3309 signal_levels
|= DP_PRE_EMPHASIS_6
;
3311 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3312 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3315 return signal_levels
;
3318 /* Gen6's DP voltage swing and pre-emphasis control */
3320 intel_gen6_edp_signal_levels(uint8_t train_set
)
3322 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3323 DP_TRAIN_PRE_EMPHASIS_MASK
);
3324 switch (signal_levels
) {
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3327 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3328 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3329 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3332 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3335 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3338 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3340 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3341 "0x%x\n", signal_levels
);
3342 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3346 /* Gen7's DP voltage swing and pre-emphasis control */
3348 intel_gen7_edp_signal_levels(uint8_t train_set
)
3350 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3351 DP_TRAIN_PRE_EMPHASIS_MASK
);
3352 switch (signal_levels
) {
3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3354 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3355 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3356 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3357 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3358 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3360 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3361 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3362 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3363 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3365 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3366 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3367 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3368 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3371 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3372 "0x%x\n", signal_levels
);
3373 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3377 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3379 intel_hsw_signal_levels(uint8_t train_set
)
3381 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3382 DP_TRAIN_PRE_EMPHASIS_MASK
);
3383 switch (signal_levels
) {
3384 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3385 return DDI_BUF_TRANS_SELECT(0);
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3387 return DDI_BUF_TRANS_SELECT(1);
3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3389 return DDI_BUF_TRANS_SELECT(2);
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3391 return DDI_BUF_TRANS_SELECT(3);
3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3394 return DDI_BUF_TRANS_SELECT(4);
3395 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3396 return DDI_BUF_TRANS_SELECT(5);
3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3398 return DDI_BUF_TRANS_SELECT(6);
3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3401 return DDI_BUF_TRANS_SELECT(7);
3402 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3403 return DDI_BUF_TRANS_SELECT(8);
3405 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3406 "0x%x\n", signal_levels
);
3407 return DDI_BUF_TRANS_SELECT(0);
3411 /* Properly updates "DP" with the correct signal levels. */
3413 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3415 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3416 enum port port
= intel_dig_port
->port
;
3417 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3418 uint32_t signal_levels
, mask
;
3419 uint8_t train_set
= intel_dp
->train_set
[0];
3421 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
3422 signal_levels
= intel_hsw_signal_levels(train_set
);
3423 mask
= DDI_BUF_EMP_MASK
;
3424 } else if (IS_CHERRYVIEW(dev
)) {
3425 signal_levels
= intel_chv_signal_levels(intel_dp
);
3427 } else if (IS_VALLEYVIEW(dev
)) {
3428 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3430 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3431 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3432 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3433 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3434 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3435 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3437 signal_levels
= intel_gen4_signal_levels(train_set
);
3438 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3441 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3443 *DP
= (*DP
& ~mask
) | signal_levels
;
3447 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3449 uint8_t dp_train_pat
)
3451 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3452 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3454 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3457 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3459 I915_WRITE(intel_dp
->output_reg
, *DP
);
3460 POSTING_READ(intel_dp
->output_reg
);
3462 buf
[0] = dp_train_pat
;
3463 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3464 DP_TRAINING_PATTERN_DISABLE
) {
3465 /* don't write DP_TRAINING_LANEx_SET on disable */
3468 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3469 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3470 len
= intel_dp
->lane_count
+ 1;
3473 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3480 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3481 uint8_t dp_train_pat
)
3483 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3484 intel_dp_set_signal_levels(intel_dp
, DP
);
3485 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3489 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3490 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3492 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3493 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3497 intel_get_adjust_train(intel_dp
, link_status
);
3498 intel_dp_set_signal_levels(intel_dp
, DP
);
3500 I915_WRITE(intel_dp
->output_reg
, *DP
);
3501 POSTING_READ(intel_dp
->output_reg
);
3503 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3504 intel_dp
->train_set
, intel_dp
->lane_count
);
3506 return ret
== intel_dp
->lane_count
;
3509 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3511 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3512 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3514 enum port port
= intel_dig_port
->port
;
3520 val
= I915_READ(DP_TP_CTL(port
));
3521 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3522 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3523 I915_WRITE(DP_TP_CTL(port
), val
);
3526 * On PORT_A we can have only eDP in SST mode. There the only reason
3527 * we need to set idle transmission mode is to work around a HW issue
3528 * where we enable the pipe while not in idle link-training mode.
3529 * In this case there is requirement to wait for a minimum number of
3530 * idle patterns to be sent.
3535 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3537 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3540 /* Enable corresponding port and start training pattern 1 */
3542 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3544 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3545 struct drm_device
*dev
= encoder
->dev
;
3548 int voltage_tries
, loop_tries
;
3549 uint32_t DP
= intel_dp
->DP
;
3550 uint8_t link_config
[2];
3553 intel_ddi_prepare_link_retrain(encoder
);
3555 /* Write the link configuration data */
3556 link_config
[0] = intel_dp
->link_bw
;
3557 link_config
[1] = intel_dp
->lane_count
;
3558 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3559 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3560 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3563 link_config
[1] = DP_SET_ANSI_8B10B
;
3564 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3568 /* clock recovery */
3569 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3570 DP_TRAINING_PATTERN_1
|
3571 DP_LINK_SCRAMBLING_DISABLE
)) {
3572 DRM_ERROR("failed to enable link training\n");
3580 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3582 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3583 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3584 DRM_ERROR("failed to get link status\n");
3588 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3589 DRM_DEBUG_KMS("clock recovery OK\n");
3593 /* Check to see if we've tried the max voltage */
3594 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3595 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3597 if (i
== intel_dp
->lane_count
) {
3599 if (loop_tries
== 5) {
3600 DRM_ERROR("too many full retries, give up\n");
3603 intel_dp_reset_link_train(intel_dp
, &DP
,
3604 DP_TRAINING_PATTERN_1
|
3605 DP_LINK_SCRAMBLING_DISABLE
);
3610 /* Check to see if we've tried the same voltage 5 times */
3611 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3613 if (voltage_tries
== 5) {
3614 DRM_ERROR("too many voltage retries, give up\n");
3619 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3621 /* Update training set as requested by target */
3622 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3623 DRM_ERROR("failed to update link training\n");
3632 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3634 bool channel_eq
= false;
3635 int tries
, cr_tries
;
3636 uint32_t DP
= intel_dp
->DP
;
3637 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3639 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3640 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3641 training_pattern
= DP_TRAINING_PATTERN_3
;
3643 /* channel equalization */
3644 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3646 DP_LINK_SCRAMBLING_DISABLE
)) {
3647 DRM_ERROR("failed to start channel equalization\n");
3655 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3658 DRM_ERROR("failed to train DP, aborting\n");
3662 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3663 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3664 DRM_ERROR("failed to get link status\n");
3668 /* Make sure clock is still ok */
3669 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3670 intel_dp_start_link_train(intel_dp
);
3671 intel_dp_set_link_train(intel_dp
, &DP
,
3673 DP_LINK_SCRAMBLING_DISABLE
);
3678 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3683 /* Try 5 times, then try clock recovery if that fails */
3685 intel_dp_link_down(intel_dp
);
3686 intel_dp_start_link_train(intel_dp
);
3687 intel_dp_set_link_train(intel_dp
, &DP
,
3689 DP_LINK_SCRAMBLING_DISABLE
);
3695 /* Update training set as requested by target */
3696 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3697 DRM_ERROR("failed to update link training\n");
3703 intel_dp_set_idle_link_train(intel_dp
);
3708 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3712 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3714 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3715 DP_TRAINING_PATTERN_DISABLE
);
3719 intel_dp_link_down(struct intel_dp
*intel_dp
)
3721 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3722 enum port port
= intel_dig_port
->port
;
3723 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3725 struct intel_crtc
*intel_crtc
=
3726 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3727 uint32_t DP
= intel_dp
->DP
;
3729 if (WARN_ON(HAS_DDI(dev
)))
3732 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3735 DRM_DEBUG_KMS("\n");
3737 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3738 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3739 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3741 if (IS_CHERRYVIEW(dev
))
3742 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3744 DP
&= ~DP_LINK_TRAIN_MASK
;
3745 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3747 POSTING_READ(intel_dp
->output_reg
);
3749 if (HAS_PCH_IBX(dev
) &&
3750 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3751 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3753 /* Hardware workaround: leaving our transcoder select
3754 * set to transcoder B while it's off will prevent the
3755 * corresponding HDMI output on transcoder A.
3757 * Combine this with another hardware workaround:
3758 * transcoder select bit can only be cleared while the
3761 DP
&= ~DP_PIPEB_SELECT
;
3762 I915_WRITE(intel_dp
->output_reg
, DP
);
3764 /* Changes to enable or select take place the vblank
3765 * after being written.
3767 if (WARN_ON(crtc
== NULL
)) {
3768 /* We should never try to disable a port without a crtc
3769 * attached. For paranoia keep the code around for a
3771 POSTING_READ(intel_dp
->output_reg
);
3774 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3777 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3778 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3779 POSTING_READ(intel_dp
->output_reg
);
3780 msleep(intel_dp
->panel_power_down_delay
);
3784 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3786 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3787 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3790 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3791 sizeof(intel_dp
->dpcd
)) < 0)
3792 return false; /* aux transfer failed */
3794 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3796 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3797 return false; /* DPCD not present */
3799 /* Check if the panel supports PSR */
3800 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3801 if (is_edp(intel_dp
)) {
3802 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3804 sizeof(intel_dp
->psr_dpcd
));
3805 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3806 dev_priv
->psr
.sink_support
= true;
3807 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3811 /* Training Pattern 3 support */
3812 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3813 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3814 intel_dp
->use_tps3
= true;
3815 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3817 intel_dp
->use_tps3
= false;
3819 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3820 DP_DWN_STRM_PORT_PRESENT
))
3821 return true; /* native DP sink */
3823 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3824 return true; /* no per-port downstream info */
3826 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3827 intel_dp
->downstream_ports
,
3828 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3829 return false; /* downstream port status fetch failed */
3835 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3839 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3842 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3843 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3844 buf
[0], buf
[1], buf
[2]);
3846 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3847 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3848 buf
[0], buf
[1], buf
[2]);
3852 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3856 if (!intel_dp
->can_mst
)
3859 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3862 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3863 if (buf
[0] & DP_MST_CAP
) {
3864 DRM_DEBUG_KMS("Sink is MST capable\n");
3865 intel_dp
->is_mst
= true;
3867 DRM_DEBUG_KMS("Sink is not MST capable\n");
3868 intel_dp
->is_mst
= false;
3872 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3873 return intel_dp
->is_mst
;
3876 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3878 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3879 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3880 struct intel_crtc
*intel_crtc
=
3881 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3886 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3889 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3892 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3895 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3896 buf
| DP_TEST_SINK_START
) < 0)
3899 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3901 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
3904 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3905 DP_TEST_SINK_MISC
, &buf
) < 0)
3907 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3908 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
3910 if (attempts
== 0) {
3911 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3915 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3918 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3920 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3921 buf
& ~DP_TEST_SINK_START
) < 0)
3928 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3930 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3931 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3932 sink_irq_vector
, 1) == 1;
3936 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3940 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3942 sink_irq_vector
, 14);
3950 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3952 /* NAK by default */
3953 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3957 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3961 if (intel_dp
->is_mst
) {
3966 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3970 /* check link status - esi[10] = 0x200c */
3971 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3972 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3973 intel_dp_start_link_train(intel_dp
);
3974 intel_dp_complete_link_train(intel_dp
);
3975 intel_dp_stop_link_train(intel_dp
);
3978 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3979 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3982 for (retry
= 0; retry
< 3; retry
++) {
3984 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3985 DP_SINK_COUNT_ESI
+1,
3992 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3994 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
4002 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4003 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4004 intel_dp
->is_mst
= false;
4005 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4006 /* send a hotplug event */
4007 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4014 * According to DP spec
4017 * 2. Configure link according to Receiver Capabilities
4018 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4019 * 4. Check link status on receipt of hot-plug interrupt
4022 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4024 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4025 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4027 u8 link_status
[DP_LINK_STATUS_SIZE
];
4029 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4031 if (!intel_encoder
->connectors_active
)
4034 if (WARN_ON(!intel_encoder
->base
.crtc
))
4037 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4040 /* Try to read receiver status if the link appears to be up */
4041 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4045 /* Now read the DPCD to see if it's actually running */
4046 if (!intel_dp_get_dpcd(intel_dp
)) {
4050 /* Try to read the source of the interrupt */
4051 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4052 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4053 /* Clear interrupt source */
4054 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4055 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4058 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4059 intel_dp_handle_test_request(intel_dp
);
4060 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4061 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4064 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4065 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4066 intel_encoder
->base
.name
);
4067 intel_dp_start_link_train(intel_dp
);
4068 intel_dp_complete_link_train(intel_dp
);
4069 intel_dp_stop_link_train(intel_dp
);
4073 /* XXX this is probably wrong for multiple downstream ports */
4074 static enum drm_connector_status
4075 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4077 uint8_t *dpcd
= intel_dp
->dpcd
;
4080 if (!intel_dp_get_dpcd(intel_dp
))
4081 return connector_status_disconnected
;
4083 /* if there's no downstream port, we're done */
4084 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4085 return connector_status_connected
;
4087 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4088 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4089 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4092 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4094 return connector_status_unknown
;
4096 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4097 : connector_status_disconnected
;
4100 /* If no HPD, poke DDC gently */
4101 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4102 return connector_status_connected
;
4104 /* Well we tried, say unknown for unreliable port types */
4105 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4106 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4107 if (type
== DP_DS_PORT_TYPE_VGA
||
4108 type
== DP_DS_PORT_TYPE_NON_EDID
)
4109 return connector_status_unknown
;
4111 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4112 DP_DWN_STRM_PORT_TYPE_MASK
;
4113 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4114 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4115 return connector_status_unknown
;
4118 /* Anything else is out of spec, warn and ignore */
4119 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4120 return connector_status_disconnected
;
4123 static enum drm_connector_status
4124 edp_detect(struct intel_dp
*intel_dp
)
4126 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4127 enum drm_connector_status status
;
4129 status
= intel_panel_detect(dev
);
4130 if (status
== connector_status_unknown
)
4131 status
= connector_status_connected
;
4136 static enum drm_connector_status
4137 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4139 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4141 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4143 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4144 return connector_status_disconnected
;
4146 return intel_dp_detect_dpcd(intel_dp
);
4149 static int g4x_digital_port_connected(struct drm_device
*dev
,
4150 struct intel_digital_port
*intel_dig_port
)
4152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4155 if (IS_VALLEYVIEW(dev
)) {
4156 switch (intel_dig_port
->port
) {
4158 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4161 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4164 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4170 switch (intel_dig_port
->port
) {
4172 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4175 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4178 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4185 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4190 static enum drm_connector_status
4191 g4x_dp_detect(struct intel_dp
*intel_dp
)
4193 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4194 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4197 /* Can't disconnect eDP, but you can close the lid... */
4198 if (is_edp(intel_dp
)) {
4199 enum drm_connector_status status
;
4201 status
= intel_panel_detect(dev
);
4202 if (status
== connector_status_unknown
)
4203 status
= connector_status_connected
;
4207 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4209 return connector_status_unknown
;
4211 return connector_status_disconnected
;
4213 return intel_dp_detect_dpcd(intel_dp
);
4216 static struct edid
*
4217 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4219 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4221 /* use cached edid if we have one */
4222 if (intel_connector
->edid
) {
4224 if (IS_ERR(intel_connector
->edid
))
4227 return drm_edid_duplicate(intel_connector
->edid
);
4229 return drm_get_edid(&intel_connector
->base
,
4230 &intel_dp
->aux
.ddc
);
4234 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4236 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4239 edid
= intel_dp_get_edid(intel_dp
);
4240 intel_connector
->detect_edid
= edid
;
4242 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4243 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4245 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4249 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4251 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4253 kfree(intel_connector
->detect_edid
);
4254 intel_connector
->detect_edid
= NULL
;
4256 intel_dp
->has_audio
= false;
4259 static enum intel_display_power_domain
4260 intel_dp_power_get(struct intel_dp
*dp
)
4262 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4263 enum intel_display_power_domain power_domain
;
4265 power_domain
= intel_display_port_power_domain(encoder
);
4266 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4268 return power_domain
;
4272 intel_dp_power_put(struct intel_dp
*dp
,
4273 enum intel_display_power_domain power_domain
)
4275 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4276 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4279 static enum drm_connector_status
4280 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4282 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4283 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4284 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4285 struct drm_device
*dev
= connector
->dev
;
4286 enum drm_connector_status status
;
4287 enum intel_display_power_domain power_domain
;
4290 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4291 connector
->base
.id
, connector
->name
);
4292 intel_dp_unset_edid(intel_dp
);
4294 if (intel_dp
->is_mst
) {
4295 /* MST devices are disconnected from a monitor POV */
4296 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4297 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4298 return connector_status_disconnected
;
4301 power_domain
= intel_dp_power_get(intel_dp
);
4303 /* Can't disconnect eDP, but you can close the lid... */
4304 if (is_edp(intel_dp
))
4305 status
= edp_detect(intel_dp
);
4306 else if (HAS_PCH_SPLIT(dev
))
4307 status
= ironlake_dp_detect(intel_dp
);
4309 status
= g4x_dp_detect(intel_dp
);
4310 if (status
!= connector_status_connected
)
4313 intel_dp_probe_oui(intel_dp
);
4315 ret
= intel_dp_probe_mst(intel_dp
);
4317 /* if we are in MST mode then this connector
4318 won't appear connected or have anything with EDID on it */
4319 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4320 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4321 status
= connector_status_disconnected
;
4325 intel_dp_set_edid(intel_dp
);
4327 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4328 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4329 status
= connector_status_connected
;
4332 intel_dp_power_put(intel_dp
, power_domain
);
4337 intel_dp_force(struct drm_connector
*connector
)
4339 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4340 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4341 enum intel_display_power_domain power_domain
;
4343 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4344 connector
->base
.id
, connector
->name
);
4345 intel_dp_unset_edid(intel_dp
);
4347 if (connector
->status
!= connector_status_connected
)
4350 power_domain
= intel_dp_power_get(intel_dp
);
4352 intel_dp_set_edid(intel_dp
);
4354 intel_dp_power_put(intel_dp
, power_domain
);
4356 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4357 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4360 static int intel_dp_get_modes(struct drm_connector
*connector
)
4362 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4365 edid
= intel_connector
->detect_edid
;
4367 int ret
= intel_connector_update_modes(connector
, edid
);
4372 /* if eDP has no EDID, fall back to fixed mode */
4373 if (is_edp(intel_attached_dp(connector
)) &&
4374 intel_connector
->panel
.fixed_mode
) {
4375 struct drm_display_mode
*mode
;
4377 mode
= drm_mode_duplicate(connector
->dev
,
4378 intel_connector
->panel
.fixed_mode
);
4380 drm_mode_probed_add(connector
, mode
);
4389 intel_dp_detect_audio(struct drm_connector
*connector
)
4391 bool has_audio
= false;
4394 edid
= to_intel_connector(connector
)->detect_edid
;
4396 has_audio
= drm_detect_monitor_audio(edid
);
4402 intel_dp_set_property(struct drm_connector
*connector
,
4403 struct drm_property
*property
,
4406 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4407 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4408 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4409 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4412 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4416 if (property
== dev_priv
->force_audio_property
) {
4420 if (i
== intel_dp
->force_audio
)
4423 intel_dp
->force_audio
= i
;
4425 if (i
== HDMI_AUDIO_AUTO
)
4426 has_audio
= intel_dp_detect_audio(connector
);
4428 has_audio
= (i
== HDMI_AUDIO_ON
);
4430 if (has_audio
== intel_dp
->has_audio
)
4433 intel_dp
->has_audio
= has_audio
;
4437 if (property
== dev_priv
->broadcast_rgb_property
) {
4438 bool old_auto
= intel_dp
->color_range_auto
;
4439 uint32_t old_range
= intel_dp
->color_range
;
4442 case INTEL_BROADCAST_RGB_AUTO
:
4443 intel_dp
->color_range_auto
= true;
4445 case INTEL_BROADCAST_RGB_FULL
:
4446 intel_dp
->color_range_auto
= false;
4447 intel_dp
->color_range
= 0;
4449 case INTEL_BROADCAST_RGB_LIMITED
:
4450 intel_dp
->color_range_auto
= false;
4451 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4457 if (old_auto
== intel_dp
->color_range_auto
&&
4458 old_range
== intel_dp
->color_range
)
4464 if (is_edp(intel_dp
) &&
4465 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4466 if (val
== DRM_MODE_SCALE_NONE
) {
4467 DRM_DEBUG_KMS("no scaling not supported\n");
4471 if (intel_connector
->panel
.fitting_mode
== val
) {
4472 /* the eDP scaling property is not changed */
4475 intel_connector
->panel
.fitting_mode
= val
;
4483 if (intel_encoder
->base
.crtc
)
4484 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4490 intel_dp_connector_destroy(struct drm_connector
*connector
)
4492 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4494 kfree(intel_connector
->detect_edid
);
4496 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4497 kfree(intel_connector
->edid
);
4499 /* Can't call is_edp() since the encoder may have been destroyed
4501 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4502 intel_panel_fini(&intel_connector
->panel
);
4504 drm_connector_cleanup(connector
);
4508 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4510 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4511 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4513 drm_dp_aux_unregister(&intel_dp
->aux
);
4514 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4515 drm_encoder_cleanup(encoder
);
4516 if (is_edp(intel_dp
)) {
4517 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4519 * vdd might still be enabled do to the delayed vdd off.
4520 * Make sure vdd is actually turned off here.
4523 edp_panel_vdd_off_sync(intel_dp
);
4524 pps_unlock(intel_dp
);
4526 if (intel_dp
->edp_notifier
.notifier_call
) {
4527 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4528 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4531 kfree(intel_dig_port
);
4534 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4536 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4538 if (!is_edp(intel_dp
))
4542 * vdd might still be enabled do to the delayed vdd off.
4543 * Make sure vdd is actually turned off here.
4546 edp_panel_vdd_off_sync(intel_dp
);
4547 pps_unlock(intel_dp
);
4550 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4552 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4555 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4556 .dpms
= intel_connector_dpms
,
4557 .detect
= intel_dp_detect
,
4558 .force
= intel_dp_force
,
4559 .fill_modes
= drm_helper_probe_single_connector_modes
,
4560 .set_property
= intel_dp_set_property
,
4561 .destroy
= intel_dp_connector_destroy
,
4564 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4565 .get_modes
= intel_dp_get_modes
,
4566 .mode_valid
= intel_dp_mode_valid
,
4567 .best_encoder
= intel_best_encoder
,
4570 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4571 .reset
= intel_dp_encoder_reset
,
4572 .destroy
= intel_dp_encoder_destroy
,
4576 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4582 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4584 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4585 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4586 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4588 enum intel_display_power_domain power_domain
;
4591 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4592 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4594 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4595 port_name(intel_dig_port
->port
),
4596 long_hpd
? "long" : "short");
4598 power_domain
= intel_display_port_power_domain(intel_encoder
);
4599 intel_display_power_get(dev_priv
, power_domain
);
4603 if (HAS_PCH_SPLIT(dev
)) {
4604 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4607 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4611 if (!intel_dp_get_dpcd(intel_dp
)) {
4615 intel_dp_probe_oui(intel_dp
);
4617 if (!intel_dp_probe_mst(intel_dp
))
4621 if (intel_dp
->is_mst
) {
4622 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4626 if (!intel_dp
->is_mst
) {
4628 * we'll check the link status via the normal hot plug path later -
4629 * but for short hpds we should check it now
4631 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4632 intel_dp_check_link_status(intel_dp
);
4633 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4639 /* if we were in MST mode, and device is not there get out of MST mode */
4640 if (intel_dp
->is_mst
) {
4641 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4642 intel_dp
->is_mst
= false;
4643 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4646 intel_display_power_put(dev_priv
, power_domain
);
4651 /* Return which DP Port should be selected for Transcoder DP control */
4653 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4655 struct drm_device
*dev
= crtc
->dev
;
4656 struct intel_encoder
*intel_encoder
;
4657 struct intel_dp
*intel_dp
;
4659 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4660 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4662 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4663 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4664 return intel_dp
->output_reg
;
4670 /* check the VBT to see whether the eDP is on DP-D port */
4671 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4674 union child_device_config
*p_child
;
4676 static const short port_mapping
[] = {
4677 [PORT_B
] = PORT_IDPB
,
4678 [PORT_C
] = PORT_IDPC
,
4679 [PORT_D
] = PORT_IDPD
,
4685 if (!dev_priv
->vbt
.child_dev_num
)
4688 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4689 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4691 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4692 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4693 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4700 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4702 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4704 intel_attach_force_audio_property(connector
);
4705 intel_attach_broadcast_rgb_property(connector
);
4706 intel_dp
->color_range_auto
= true;
4708 if (is_edp(intel_dp
)) {
4709 drm_mode_create_scaling_mode_property(connector
->dev
);
4710 drm_object_attach_property(
4712 connector
->dev
->mode_config
.scaling_mode_property
,
4713 DRM_MODE_SCALE_ASPECT
);
4714 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4718 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4720 intel_dp
->last_power_cycle
= jiffies
;
4721 intel_dp
->last_power_on
= jiffies
;
4722 intel_dp
->last_backlight_off
= jiffies
;
4726 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4727 struct intel_dp
*intel_dp
)
4729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4730 struct edp_power_seq cur
, vbt
, spec
,
4731 *final
= &intel_dp
->pps_delays
;
4732 u32 pp_on
, pp_off
, pp_div
, pp
;
4733 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4735 lockdep_assert_held(&dev_priv
->pps_mutex
);
4737 /* already initialized? */
4738 if (final
->t11_t12
!= 0)
4741 if (HAS_PCH_SPLIT(dev
)) {
4742 pp_ctrl_reg
= PCH_PP_CONTROL
;
4743 pp_on_reg
= PCH_PP_ON_DELAYS
;
4744 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4745 pp_div_reg
= PCH_PP_DIVISOR
;
4747 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4749 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4750 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4751 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4752 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4755 /* Workaround: Need to write PP_CONTROL with the unlock key as
4756 * the very first thing. */
4757 pp
= ironlake_get_pp_control(intel_dp
);
4758 I915_WRITE(pp_ctrl_reg
, pp
);
4760 pp_on
= I915_READ(pp_on_reg
);
4761 pp_off
= I915_READ(pp_off_reg
);
4762 pp_div
= I915_READ(pp_div_reg
);
4764 /* Pull timing values out of registers */
4765 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4766 PANEL_POWER_UP_DELAY_SHIFT
;
4768 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4769 PANEL_LIGHT_ON_DELAY_SHIFT
;
4771 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4772 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4774 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4775 PANEL_POWER_DOWN_DELAY_SHIFT
;
4777 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4778 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4780 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4781 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4783 vbt
= dev_priv
->vbt
.edp_pps
;
4785 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4786 * our hw here, which are all in 100usec. */
4787 spec
.t1_t3
= 210 * 10;
4788 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4789 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4790 spec
.t10
= 500 * 10;
4791 /* This one is special and actually in units of 100ms, but zero
4792 * based in the hw (so we need to add 100 ms). But the sw vbt
4793 * table multiplies it with 1000 to make it in units of 100usec,
4795 spec
.t11_t12
= (510 + 100) * 10;
4797 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4798 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4800 /* Use the max of the register settings and vbt. If both are
4801 * unset, fall back to the spec limits. */
4802 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4804 max(cur.field, vbt.field))
4805 assign_final(t1_t3
);
4809 assign_final(t11_t12
);
4812 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4813 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4814 intel_dp
->backlight_on_delay
= get_delay(t8
);
4815 intel_dp
->backlight_off_delay
= get_delay(t9
);
4816 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4817 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4820 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4821 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4822 intel_dp
->panel_power_cycle_delay
);
4824 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4825 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4829 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4830 struct intel_dp
*intel_dp
)
4832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4833 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4834 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4835 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4836 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4837 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4839 lockdep_assert_held(&dev_priv
->pps_mutex
);
4841 if (HAS_PCH_SPLIT(dev
)) {
4842 pp_on_reg
= PCH_PP_ON_DELAYS
;
4843 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4844 pp_div_reg
= PCH_PP_DIVISOR
;
4846 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4848 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4849 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4850 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4854 * And finally store the new values in the power sequencer. The
4855 * backlight delays are set to 1 because we do manual waits on them. For
4856 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4857 * we'll end up waiting for the backlight off delay twice: once when we
4858 * do the manual sleep, and once when we disable the panel and wait for
4859 * the PP_STATUS bit to become zero.
4861 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4862 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4863 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4864 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4865 /* Compute the divisor for the pp clock, simply match the Bspec
4867 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4868 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4869 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4871 /* Haswell doesn't have any port selection bits for the panel
4872 * power sequencer any more. */
4873 if (IS_VALLEYVIEW(dev
)) {
4874 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4875 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4877 port_sel
= PANEL_PORT_SELECT_DPA
;
4879 port_sel
= PANEL_PORT_SELECT_DPD
;
4884 I915_WRITE(pp_on_reg
, pp_on
);
4885 I915_WRITE(pp_off_reg
, pp_off
);
4886 I915_WRITE(pp_div_reg
, pp_div
);
4888 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4889 I915_READ(pp_on_reg
),
4890 I915_READ(pp_off_reg
),
4891 I915_READ(pp_div_reg
));
4894 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4897 struct intel_encoder
*encoder
;
4898 struct intel_dp
*intel_dp
= NULL
;
4899 struct intel_crtc_config
*config
= NULL
;
4900 struct intel_crtc
*intel_crtc
= NULL
;
4901 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4903 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4905 if (refresh_rate
<= 0) {
4906 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4910 if (intel_connector
== NULL
) {
4911 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4916 * FIXME: This needs proper synchronization with psr state. But really
4917 * hard to tell without seeing the user of this function of this code.
4918 * Check locking and ordering once that lands.
4920 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4921 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4925 encoder
= intel_attached_encoder(&intel_connector
->base
);
4926 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4927 intel_crtc
= encoder
->new_crtc
;
4930 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4934 config
= &intel_crtc
->config
;
4936 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4937 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4941 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4942 index
= DRRS_LOW_RR
;
4944 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4946 "DRRS requested for previously set RR...ignoring\n");
4950 if (!intel_crtc
->active
) {
4951 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4955 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4956 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4957 val
= I915_READ(reg
);
4958 if (index
> DRRS_HIGH_RR
) {
4959 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4960 intel_dp_set_m_n(intel_crtc
);
4962 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4964 I915_WRITE(reg
, val
);
4968 * mutex taken to ensure that there is no race between differnt
4969 * drrs calls trying to update refresh rate. This scenario may occur
4970 * in future when idleness detection based DRRS in kernel and
4971 * possible calls from user space to set differnt RR are made.
4974 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4976 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4978 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4980 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4983 static struct drm_display_mode
*
4984 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4985 struct intel_connector
*intel_connector
,
4986 struct drm_display_mode
*fixed_mode
)
4988 struct drm_connector
*connector
= &intel_connector
->base
;
4989 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4990 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4992 struct drm_display_mode
*downclock_mode
= NULL
;
4994 if (INTEL_INFO(dev
)->gen
<= 6) {
4995 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4999 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5000 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5004 downclock_mode
= intel_find_panel_downclock
5005 (dev
, fixed_mode
, connector
);
5007 if (!downclock_mode
) {
5008 DRM_DEBUG_KMS("DRRS not supported\n");
5012 dev_priv
->drrs
.connector
= intel_connector
;
5014 mutex_init(&intel_dp
->drrs_state
.mutex
);
5016 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
5018 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
5019 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5020 return downclock_mode
;
5023 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
5025 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5027 struct intel_dp
*intel_dp
;
5028 enum intel_display_power_domain power_domain
;
5030 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
5033 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5037 if (!edp_have_panel_vdd(intel_dp
))
5040 * The VDD bit needs a power domain reference, so if the bit is
5041 * already enabled when we boot or resume, grab this reference and
5042 * schedule a vdd off, so we don't hold on to the reference
5045 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5046 power_domain
= intel_display_port_power_domain(intel_encoder
);
5047 intel_display_power_get(dev_priv
, power_domain
);
5049 edp_panel_vdd_schedule_off(intel_dp
);
5051 pps_unlock(intel_dp
);
5054 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5055 struct intel_connector
*intel_connector
)
5057 struct drm_connector
*connector
= &intel_connector
->base
;
5058 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5059 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5060 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5062 struct drm_display_mode
*fixed_mode
= NULL
;
5063 struct drm_display_mode
*downclock_mode
= NULL
;
5065 struct drm_display_mode
*scan
;
5068 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
5070 if (!is_edp(intel_dp
))
5073 intel_edp_panel_vdd_sanitize(intel_encoder
);
5075 /* Cache DPCD and EDID for edp. */
5076 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5079 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5080 dev_priv
->no_aux_handshake
=
5081 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5082 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5084 /* if this fails, presume the device is a ghost */
5085 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5089 /* We now know it's not a ghost, init power sequence regs. */
5091 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5092 pps_unlock(intel_dp
);
5094 mutex_lock(&dev
->mode_config
.mutex
);
5095 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5097 if (drm_add_edid_modes(connector
, edid
)) {
5098 drm_mode_connector_update_edid_property(connector
,
5100 drm_edid_to_eld(connector
, edid
);
5103 edid
= ERR_PTR(-EINVAL
);
5106 edid
= ERR_PTR(-ENOENT
);
5108 intel_connector
->edid
= edid
;
5110 /* prefer fixed mode from EDID if available */
5111 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5112 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5113 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5114 downclock_mode
= intel_dp_drrs_init(
5116 intel_connector
, fixed_mode
);
5121 /* fallback to VBT if available for eDP */
5122 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5123 fixed_mode
= drm_mode_duplicate(dev
,
5124 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5126 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5128 mutex_unlock(&dev
->mode_config
.mutex
);
5130 if (IS_VALLEYVIEW(dev
)) {
5131 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5132 register_reboot_notifier(&intel_dp
->edp_notifier
);
5135 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5136 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5137 intel_panel_setup_backlight(connector
);
5143 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5144 struct intel_connector
*intel_connector
)
5146 struct drm_connector
*connector
= &intel_connector
->base
;
5147 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5148 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5149 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5151 enum port port
= intel_dig_port
->port
;
5154 intel_dp
->pps_pipe
= INVALID_PIPE
;
5156 /* intel_dp vfuncs */
5157 if (INTEL_INFO(dev
)->gen
>= 9)
5158 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5159 else if (IS_VALLEYVIEW(dev
))
5160 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5161 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5162 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5163 else if (HAS_PCH_SPLIT(dev
))
5164 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5166 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5168 if (INTEL_INFO(dev
)->gen
>= 9)
5169 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5171 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5173 /* Preserve the current hw state. */
5174 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5175 intel_dp
->attached_connector
= intel_connector
;
5177 if (intel_dp_is_edp(dev
, port
))
5178 type
= DRM_MODE_CONNECTOR_eDP
;
5180 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5183 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5184 * for DP the encoder type can be set by the caller to
5185 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5187 if (type
== DRM_MODE_CONNECTOR_eDP
)
5188 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5190 /* eDP only on port B and/or C on vlv/chv */
5191 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5192 port
!= PORT_B
&& port
!= PORT_C
))
5195 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5196 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5199 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5200 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5202 connector
->interlace_allowed
= true;
5203 connector
->doublescan_allowed
= 0;
5205 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5206 edp_panel_vdd_work
);
5208 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5209 drm_connector_register(connector
);
5212 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5214 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5215 intel_connector
->unregister
= intel_dp_connector_unregister
;
5217 /* Set up the hotplug pin. */
5220 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5223 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5226 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5229 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5235 if (is_edp(intel_dp
)) {
5237 if (IS_VALLEYVIEW(dev
)) {
5238 vlv_initial_power_sequencer_setup(intel_dp
);
5240 intel_dp_init_panel_power_timestamps(intel_dp
);
5241 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5243 pps_unlock(intel_dp
);
5246 intel_dp_aux_init(intel_dp
, intel_connector
);
5248 /* init MST on ports that can support it */
5249 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5250 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5251 intel_dp_mst_encoder_init(intel_dig_port
,
5252 intel_connector
->base
.base
.id
);
5256 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5257 drm_dp_aux_unregister(&intel_dp
->aux
);
5258 if (is_edp(intel_dp
)) {
5259 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5261 * vdd might still be enabled do to the delayed vdd off.
5262 * Make sure vdd is actually turned off here.
5265 edp_panel_vdd_off_sync(intel_dp
);
5266 pps_unlock(intel_dp
);
5268 drm_connector_unregister(connector
);
5269 drm_connector_cleanup(connector
);
5273 intel_dp_add_properties(intel_dp
, connector
);
5275 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5276 * 0xd. Failure to do so will result in spurious interrupts being
5277 * generated on the port when a cable is not attached.
5279 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5280 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5281 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5288 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5291 struct intel_digital_port
*intel_dig_port
;
5292 struct intel_encoder
*intel_encoder
;
5293 struct drm_encoder
*encoder
;
5294 struct intel_connector
*intel_connector
;
5296 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5297 if (!intel_dig_port
)
5300 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5301 if (!intel_connector
) {
5302 kfree(intel_dig_port
);
5306 intel_encoder
= &intel_dig_port
->base
;
5307 encoder
= &intel_encoder
->base
;
5309 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5310 DRM_MODE_ENCODER_TMDS
);
5312 intel_encoder
->compute_config
= intel_dp_compute_config
;
5313 intel_encoder
->disable
= intel_disable_dp
;
5314 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5315 intel_encoder
->get_config
= intel_dp_get_config
;
5316 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5317 if (IS_CHERRYVIEW(dev
)) {
5318 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5319 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5320 intel_encoder
->enable
= vlv_enable_dp
;
5321 intel_encoder
->post_disable
= chv_post_disable_dp
;
5322 } else if (IS_VALLEYVIEW(dev
)) {
5323 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5324 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5325 intel_encoder
->enable
= vlv_enable_dp
;
5326 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5328 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5329 intel_encoder
->enable
= g4x_enable_dp
;
5330 if (INTEL_INFO(dev
)->gen
>= 5)
5331 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5334 intel_dig_port
->port
= port
;
5335 intel_dig_port
->dp
.output_reg
= output_reg
;
5337 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5338 if (IS_CHERRYVIEW(dev
)) {
5340 intel_encoder
->crtc_mask
= 1 << 2;
5342 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5344 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5346 intel_encoder
->cloneable
= 0;
5347 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5349 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5350 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5352 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5353 drm_encoder_cleanup(encoder
);
5354 kfree(intel_dig_port
);
5355 kfree(intel_connector
);
5359 void intel_dp_mst_suspend(struct drm_device
*dev
)
5361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5365 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5366 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5367 if (!intel_dig_port
)
5370 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5371 if (!intel_dig_port
->dp
.can_mst
)
5373 if (intel_dig_port
->dp
.is_mst
)
5374 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5379 void intel_dp_mst_resume(struct drm_device
*dev
)
5381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5384 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5385 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5386 if (!intel_dig_port
)
5388 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5391 if (!intel_dig_port
->dp
.can_mst
)
5394 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5396 intel_dp_check_mst_status(&intel_dig_port
->dp
);