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drm/i915: Warn about want_panel_vdd in edp_panel_vdd_off_sync()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46 };
47
48 static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 };
54
55 static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 };
61
62 static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67 };
68
69 /*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73 static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85 };
86
87 /**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94 static bool is_edp(struct intel_dp *intel_dp)
95 {
96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
99 }
100
101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
102 {
103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
106 }
107
108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109 {
110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
111 }
112
113 static void intel_dp_link_down(struct intel_dp *intel_dp);
114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
116
117 int
118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
119 {
120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
134 break;
135 default:
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142 }
143
144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145 {
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158 }
159
160 /*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
177 static int
178 intel_dp_link_required(int pixel_clock, int bpp)
179 {
180 return (pixel_clock * bpp + 9) / 10;
181 }
182
183 static int
184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185 {
186 return (max_link_clock * max_lanes * 8) / 10;
187 }
188
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192 {
193 struct intel_dp *intel_dp = intel_attached_dp(connector);
194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
198
199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
201 return MODE_PANEL;
202
203 if (mode->vdisplay > fixed_mode->vdisplay)
204 return MODE_PANEL;
205
206 target_clock = fixed_mode->clock;
207 }
208
209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
210 max_lanes = intel_dp_max_lane_count(intel_dp);
211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
216 return MODE_CLOCK_HIGH;
217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
224 return MODE_OK;
225 }
226
227 static uint32_t
228 pack_aux(uint8_t *src, int src_bytes)
229 {
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238 }
239
240 static void
241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242 {
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248 }
249
250 /* hrawclock is 1/4 the FSB frequency */
251 static int
252 intel_hrawclk(struct drm_device *dev)
253 {
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282 }
283
284 static void
285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288 static void
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293 static enum pipe
294 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295 {
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
311 if (port_sel == PANEL_PORT_SELECT_VLV(port))
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317 }
318
319 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320 {
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327 }
328
329 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330 {
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337 }
338
339 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
342 void *unused)
343 {
344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
345 edp_notifier);
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 u32 pp_div;
349 u32 pp_ctrl_reg, pp_div_reg;
350 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
351
352 if (!is_edp(intel_dp) || code != SYS_RESTART)
353 return 0;
354
355 if (IS_VALLEYVIEW(dev)) {
356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358 pp_div = I915_READ(pp_div_reg);
359 pp_div &= PP_REFERENCE_DIVIDER_MASK;
360
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg, pp_div | 0x1F);
363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364 msleep(intel_dp->panel_power_cycle_delay);
365 }
366
367 return 0;
368 }
369
370 static bool edp_have_panel_power(struct intel_dp *intel_dp)
371 {
372 struct drm_device *dev = intel_dp_to_dev(intel_dp);
373 struct drm_i915_private *dev_priv = dev->dev_private;
374
375 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
376 }
377
378 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
379 {
380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
381 struct drm_i915_private *dev_priv = dev->dev_private;
382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
383 struct intel_encoder *intel_encoder = &intel_dig_port->base;
384 enum intel_display_power_domain power_domain;
385
386 power_domain = intel_display_port_power_domain(intel_encoder);
387 return intel_display_power_enabled(dev_priv, power_domain) &&
388 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
389 }
390
391 static void
392 intel_dp_check_edp(struct intel_dp *intel_dp)
393 {
394 struct drm_device *dev = intel_dp_to_dev(intel_dp);
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (!is_edp(intel_dp))
398 return;
399
400 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
403 I915_READ(_pp_stat_reg(intel_dp)),
404 I915_READ(_pp_ctrl_reg(intel_dp)));
405 }
406 }
407
408 static uint32_t
409 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
410 {
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
415 uint32_t status;
416 bool done;
417
418 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
419 if (has_aux_irq)
420 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
421 msecs_to_jiffies_timeout(10));
422 else
423 done = wait_for_atomic(C, 10) == 0;
424 if (!done)
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
426 has_aux_irq);
427 #undef C
428
429 return status;
430 }
431
432 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
433 {
434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
436
437 /*
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
440 */
441 return index ? 0 : intel_hrawclk(dev) / 2;
442 }
443
444 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
445 {
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448
449 if (index)
450 return 0;
451
452 if (intel_dig_port->port == PORT_A) {
453 if (IS_GEN6(dev) || IS_GEN7(dev))
454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
455 else
456 return 225; /* eDP input clock at 450Mhz */
457 } else {
458 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
459 }
460 }
461
462 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
463 {
464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
465 struct drm_device *dev = intel_dig_port->base.base.dev;
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 if (intel_dig_port->port == PORT_A) {
469 if (index)
470 return 0;
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
472 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
473 /* Workaround for non-ULT HSW */
474 switch (index) {
475 case 0: return 63;
476 case 1: return 72;
477 default: return 0;
478 }
479 } else {
480 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
481 }
482 }
483
484 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
485 {
486 return index ? 0 : 100;
487 }
488
489 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
490 bool has_aux_irq,
491 int send_bytes,
492 uint32_t aux_clock_divider)
493 {
494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
495 struct drm_device *dev = intel_dig_port->base.base.dev;
496 uint32_t precharge, timeout;
497
498 if (IS_GEN6(dev))
499 precharge = 3;
500 else
501 precharge = 5;
502
503 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
504 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
505 else
506 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
507
508 return DP_AUX_CH_CTL_SEND_BUSY |
509 DP_AUX_CH_CTL_DONE |
510 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
511 DP_AUX_CH_CTL_TIME_OUT_ERROR |
512 timeout |
513 DP_AUX_CH_CTL_RECEIVE_ERROR |
514 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
515 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
516 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
517 }
518
519 static int
520 intel_dp_aux_ch(struct intel_dp *intel_dp,
521 uint8_t *send, int send_bytes,
522 uint8_t *recv, int recv_size)
523 {
524 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
525 struct drm_device *dev = intel_dig_port->base.base.dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
528 uint32_t ch_data = ch_ctl + 4;
529 uint32_t aux_clock_divider;
530 int i, ret, recv_bytes;
531 uint32_t status;
532 int try, clock = 0;
533 bool has_aux_irq = HAS_AUX_IRQ(dev);
534 bool vdd;
535
536 /*
537 * We will be called with VDD already enabled for dpcd/edid/oui reads.
538 * In such cases we want to leave VDD enabled and it's up to upper layers
539 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
540 * ourselves.
541 */
542 vdd = edp_panel_vdd_on(intel_dp);
543
544 /* dp aux is extremely sensitive to irq latency, hence request the
545 * lowest possible wakeup latency and so prevent the cpu from going into
546 * deep sleep states.
547 */
548 pm_qos_update_request(&dev_priv->pm_qos, 0);
549
550 intel_dp_check_edp(intel_dp);
551
552 intel_aux_display_runtime_get(dev_priv);
553
554 /* Try to wait for any previous AUX channel activity */
555 for (try = 0; try < 3; try++) {
556 status = I915_READ_NOTRACE(ch_ctl);
557 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
558 break;
559 msleep(1);
560 }
561
562 if (try == 3) {
563 WARN(1, "dp_aux_ch not started status 0x%08x\n",
564 I915_READ(ch_ctl));
565 ret = -EBUSY;
566 goto out;
567 }
568
569 /* Only 5 data registers! */
570 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
571 ret = -E2BIG;
572 goto out;
573 }
574
575 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
576 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
577 has_aux_irq,
578 send_bytes,
579 aux_clock_divider);
580
581 /* Must try at least 3 times according to DP spec */
582 for (try = 0; try < 5; try++) {
583 /* Load the send data into the aux channel data registers */
584 for (i = 0; i < send_bytes; i += 4)
585 I915_WRITE(ch_data + i,
586 pack_aux(send + i, send_bytes - i));
587
588 /* Send the command and wait for it to complete */
589 I915_WRITE(ch_ctl, send_ctl);
590
591 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
592
593 /* Clear done status and any errors */
594 I915_WRITE(ch_ctl,
595 status |
596 DP_AUX_CH_CTL_DONE |
597 DP_AUX_CH_CTL_TIME_OUT_ERROR |
598 DP_AUX_CH_CTL_RECEIVE_ERROR);
599
600 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
601 DP_AUX_CH_CTL_RECEIVE_ERROR))
602 continue;
603 if (status & DP_AUX_CH_CTL_DONE)
604 break;
605 }
606 if (status & DP_AUX_CH_CTL_DONE)
607 break;
608 }
609
610 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
611 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
612 ret = -EBUSY;
613 goto out;
614 }
615
616 /* Check for timeout or receive error.
617 * Timeouts occur when the sink is not connected
618 */
619 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
620 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
621 ret = -EIO;
622 goto out;
623 }
624
625 /* Timeouts occur when the device isn't connected, so they're
626 * "normal" -- don't fill the kernel log with these */
627 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
628 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
629 ret = -ETIMEDOUT;
630 goto out;
631 }
632
633 /* Unload any bytes sent back from the other side */
634 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
635 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
636 if (recv_bytes > recv_size)
637 recv_bytes = recv_size;
638
639 for (i = 0; i < recv_bytes; i += 4)
640 unpack_aux(I915_READ(ch_data + i),
641 recv + i, recv_bytes - i);
642
643 ret = recv_bytes;
644 out:
645 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
646 intel_aux_display_runtime_put(dev_priv);
647
648 if (vdd)
649 edp_panel_vdd_off(intel_dp, false);
650
651 return ret;
652 }
653
654 #define BARE_ADDRESS_SIZE 3
655 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
656 static ssize_t
657 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
658 {
659 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
660 uint8_t txbuf[20], rxbuf[20];
661 size_t txsize, rxsize;
662 int ret;
663
664 txbuf[0] = msg->request << 4;
665 txbuf[1] = msg->address >> 8;
666 txbuf[2] = msg->address & 0xff;
667 txbuf[3] = msg->size - 1;
668
669 switch (msg->request & ~DP_AUX_I2C_MOT) {
670 case DP_AUX_NATIVE_WRITE:
671 case DP_AUX_I2C_WRITE:
672 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
673 rxsize = 1;
674
675 if (WARN_ON(txsize > 20))
676 return -E2BIG;
677
678 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
679
680 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
681 if (ret > 0) {
682 msg->reply = rxbuf[0] >> 4;
683
684 /* Return payload size. */
685 ret = msg->size;
686 }
687 break;
688
689 case DP_AUX_NATIVE_READ:
690 case DP_AUX_I2C_READ:
691 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
692 rxsize = msg->size + 1;
693
694 if (WARN_ON(rxsize > 20))
695 return -E2BIG;
696
697 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
698 if (ret > 0) {
699 msg->reply = rxbuf[0] >> 4;
700 /*
701 * Assume happy day, and copy the data. The caller is
702 * expected to check msg->reply before touching it.
703 *
704 * Return payload size.
705 */
706 ret--;
707 memcpy(msg->buffer, rxbuf + 1, ret);
708 }
709 break;
710
711 default:
712 ret = -EINVAL;
713 break;
714 }
715
716 return ret;
717 }
718
719 static void
720 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
721 {
722 struct drm_device *dev = intel_dp_to_dev(intel_dp);
723 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
724 enum port port = intel_dig_port->port;
725 const char *name = NULL;
726 int ret;
727
728 switch (port) {
729 case PORT_A:
730 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
731 name = "DPDDC-A";
732 break;
733 case PORT_B:
734 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
735 name = "DPDDC-B";
736 break;
737 case PORT_C:
738 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
739 name = "DPDDC-C";
740 break;
741 case PORT_D:
742 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
743 name = "DPDDC-D";
744 break;
745 default:
746 BUG();
747 }
748
749 if (!HAS_DDI(dev))
750 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
751
752 intel_dp->aux.name = name;
753 intel_dp->aux.dev = dev->dev;
754 intel_dp->aux.transfer = intel_dp_aux_transfer;
755
756 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
757 connector->base.kdev->kobj.name);
758
759 ret = drm_dp_aux_register(&intel_dp->aux);
760 if (ret < 0) {
761 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
762 name, ret);
763 return;
764 }
765
766 ret = sysfs_create_link(&connector->base.kdev->kobj,
767 &intel_dp->aux.ddc.dev.kobj,
768 intel_dp->aux.ddc.dev.kobj.name);
769 if (ret < 0) {
770 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
771 drm_dp_aux_unregister(&intel_dp->aux);
772 }
773 }
774
775 static void
776 intel_dp_connector_unregister(struct intel_connector *intel_connector)
777 {
778 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
779
780 if (!intel_connector->mst_port)
781 sysfs_remove_link(&intel_connector->base.kdev->kobj,
782 intel_dp->aux.ddc.dev.kobj.name);
783 intel_connector_unregister(intel_connector);
784 }
785
786 static void
787 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
788 {
789 switch (link_bw) {
790 case DP_LINK_BW_1_62:
791 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
792 break;
793 case DP_LINK_BW_2_7:
794 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
795 break;
796 case DP_LINK_BW_5_4:
797 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
798 break;
799 }
800 }
801
802 static void
803 intel_dp_set_clock(struct intel_encoder *encoder,
804 struct intel_crtc_config *pipe_config, int link_bw)
805 {
806 struct drm_device *dev = encoder->base.dev;
807 const struct dp_link_dpll *divisor = NULL;
808 int i, count = 0;
809
810 if (IS_G4X(dev)) {
811 divisor = gen4_dpll;
812 count = ARRAY_SIZE(gen4_dpll);
813 } else if (HAS_PCH_SPLIT(dev)) {
814 divisor = pch_dpll;
815 count = ARRAY_SIZE(pch_dpll);
816 } else if (IS_CHERRYVIEW(dev)) {
817 divisor = chv_dpll;
818 count = ARRAY_SIZE(chv_dpll);
819 } else if (IS_VALLEYVIEW(dev)) {
820 divisor = vlv_dpll;
821 count = ARRAY_SIZE(vlv_dpll);
822 }
823
824 if (divisor && count) {
825 for (i = 0; i < count; i++) {
826 if (link_bw == divisor[i].link_bw) {
827 pipe_config->dpll = divisor[i].dpll;
828 pipe_config->clock_set = true;
829 break;
830 }
831 }
832 }
833 }
834
835 bool
836 intel_dp_compute_config(struct intel_encoder *encoder,
837 struct intel_crtc_config *pipe_config)
838 {
839 struct drm_device *dev = encoder->base.dev;
840 struct drm_i915_private *dev_priv = dev->dev_private;
841 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
843 enum port port = dp_to_dig_port(intel_dp)->port;
844 struct intel_crtc *intel_crtc = encoder->new_crtc;
845 struct intel_connector *intel_connector = intel_dp->attached_connector;
846 int lane_count, clock;
847 int min_lane_count = 1;
848 int max_lane_count = intel_dp_max_lane_count(intel_dp);
849 /* Conveniently, the link BW constants become indices with a shift...*/
850 int min_clock = 0;
851 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
852 int bpp, mode_rate;
853 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
854 int link_avail, link_clock;
855
856 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
857 pipe_config->has_pch_encoder = true;
858
859 pipe_config->has_dp_encoder = true;
860 pipe_config->has_drrs = false;
861 pipe_config->has_audio = intel_dp->has_audio;
862
863 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
864 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
865 adjusted_mode);
866 if (!HAS_PCH_SPLIT(dev))
867 intel_gmch_panel_fitting(intel_crtc, pipe_config,
868 intel_connector->panel.fitting_mode);
869 else
870 intel_pch_panel_fitting(intel_crtc, pipe_config,
871 intel_connector->panel.fitting_mode);
872 }
873
874 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
875 return false;
876
877 DRM_DEBUG_KMS("DP link computation with max lane count %i "
878 "max bw %02x pixel clock %iKHz\n",
879 max_lane_count, bws[max_clock],
880 adjusted_mode->crtc_clock);
881
882 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
883 * bpc in between. */
884 bpp = pipe_config->pipe_bpp;
885 if (is_edp(intel_dp)) {
886 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
887 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
888 dev_priv->vbt.edp_bpp);
889 bpp = dev_priv->vbt.edp_bpp;
890 }
891
892 if (IS_BROADWELL(dev)) {
893 /* Yes, it's an ugly hack. */
894 min_lane_count = max_lane_count;
895 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
896 min_lane_count);
897 } else if (dev_priv->vbt.edp_lanes) {
898 min_lane_count = min(dev_priv->vbt.edp_lanes,
899 max_lane_count);
900 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
901 min_lane_count);
902 }
903
904 if (dev_priv->vbt.edp_rate) {
905 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
906 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
907 bws[min_clock]);
908 }
909 }
910
911 for (; bpp >= 6*3; bpp -= 2*3) {
912 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
913 bpp);
914
915 for (clock = min_clock; clock <= max_clock; clock++) {
916 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
917 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
918 link_avail = intel_dp_max_data_rate(link_clock,
919 lane_count);
920
921 if (mode_rate <= link_avail) {
922 goto found;
923 }
924 }
925 }
926 }
927
928 return false;
929
930 found:
931 if (intel_dp->color_range_auto) {
932 /*
933 * See:
934 * CEA-861-E - 5.1 Default Encoding Parameters
935 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
936 */
937 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
938 intel_dp->color_range = DP_COLOR_RANGE_16_235;
939 else
940 intel_dp->color_range = 0;
941 }
942
943 if (intel_dp->color_range)
944 pipe_config->limited_color_range = true;
945
946 intel_dp->link_bw = bws[clock];
947 intel_dp->lane_count = lane_count;
948 pipe_config->pipe_bpp = bpp;
949 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
950
951 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
952 intel_dp->link_bw, intel_dp->lane_count,
953 pipe_config->port_clock, bpp);
954 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
955 mode_rate, link_avail);
956
957 intel_link_compute_m_n(bpp, lane_count,
958 adjusted_mode->crtc_clock,
959 pipe_config->port_clock,
960 &pipe_config->dp_m_n);
961
962 if (intel_connector->panel.downclock_mode != NULL &&
963 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
964 pipe_config->has_drrs = true;
965 intel_link_compute_m_n(bpp, lane_count,
966 intel_connector->panel.downclock_mode->clock,
967 pipe_config->port_clock,
968 &pipe_config->dp_m2_n2);
969 }
970
971 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
972 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
973 else
974 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
975
976 return true;
977 }
978
979 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
980 {
981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
982 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
983 struct drm_device *dev = crtc->base.dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 dpa_ctl;
986
987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
988 dpa_ctl = I915_READ(DP_A);
989 dpa_ctl &= ~DP_PLL_FREQ_MASK;
990
991 if (crtc->config.port_clock == 162000) {
992 /* For a long time we've carried around a ILK-DevA w/a for the
993 * 160MHz clock. If we're really unlucky, it's still required.
994 */
995 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
996 dpa_ctl |= DP_PLL_FREQ_160MHZ;
997 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
998 } else {
999 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1000 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1001 }
1002
1003 I915_WRITE(DP_A, dpa_ctl);
1004
1005 POSTING_READ(DP_A);
1006 udelay(500);
1007 }
1008
1009 static void intel_dp_prepare(struct intel_encoder *encoder)
1010 {
1011 struct drm_device *dev = encoder->base.dev;
1012 struct drm_i915_private *dev_priv = dev->dev_private;
1013 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1014 enum port port = dp_to_dig_port(intel_dp)->port;
1015 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1016 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1017
1018 /*
1019 * There are four kinds of DP registers:
1020 *
1021 * IBX PCH
1022 * SNB CPU
1023 * IVB CPU
1024 * CPT PCH
1025 *
1026 * IBX PCH and CPU are the same for almost everything,
1027 * except that the CPU DP PLL is configured in this
1028 * register
1029 *
1030 * CPT PCH is quite different, having many bits moved
1031 * to the TRANS_DP_CTL register instead. That
1032 * configuration happens (oddly) in ironlake_pch_enable
1033 */
1034
1035 /* Preserve the BIOS-computed detected bit. This is
1036 * supposed to be read-only.
1037 */
1038 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1039
1040 /* Handle DP bits in common between all three register formats */
1041 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1042 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1043
1044 if (crtc->config.has_audio) {
1045 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1046 pipe_name(crtc->pipe));
1047 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1048 intel_write_eld(&encoder->base, adjusted_mode);
1049 }
1050
1051 /* Split out the IBX/CPU vs CPT settings */
1052
1053 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1054 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1055 intel_dp->DP |= DP_SYNC_HS_HIGH;
1056 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1057 intel_dp->DP |= DP_SYNC_VS_HIGH;
1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059
1060 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1061 intel_dp->DP |= DP_ENHANCED_FRAMING;
1062
1063 intel_dp->DP |= crtc->pipe << 29;
1064 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1065 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1066 intel_dp->DP |= intel_dp->color_range;
1067
1068 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1069 intel_dp->DP |= DP_SYNC_HS_HIGH;
1070 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1071 intel_dp->DP |= DP_SYNC_VS_HIGH;
1072 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1073
1074 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1075 intel_dp->DP |= DP_ENHANCED_FRAMING;
1076
1077 if (!IS_CHERRYVIEW(dev)) {
1078 if (crtc->pipe == 1)
1079 intel_dp->DP |= DP_PIPEB_SELECT;
1080 } else {
1081 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1082 }
1083 } else {
1084 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1085 }
1086 }
1087
1088 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1089 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1090
1091 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1092 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1093
1094 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1095 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1096
1097 static void wait_panel_status(struct intel_dp *intel_dp,
1098 u32 mask,
1099 u32 value)
1100 {
1101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 u32 pp_stat_reg, pp_ctrl_reg;
1104
1105 pp_stat_reg = _pp_stat_reg(intel_dp);
1106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1107
1108 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1109 mask, value,
1110 I915_READ(pp_stat_reg),
1111 I915_READ(pp_ctrl_reg));
1112
1113 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1114 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1115 I915_READ(pp_stat_reg),
1116 I915_READ(pp_ctrl_reg));
1117 }
1118
1119 DRM_DEBUG_KMS("Wait complete\n");
1120 }
1121
1122 static void wait_panel_on(struct intel_dp *intel_dp)
1123 {
1124 DRM_DEBUG_KMS("Wait for panel power on\n");
1125 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1126 }
1127
1128 static void wait_panel_off(struct intel_dp *intel_dp)
1129 {
1130 DRM_DEBUG_KMS("Wait for panel power off time\n");
1131 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1132 }
1133
1134 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1135 {
1136 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1137
1138 /* When we disable the VDD override bit last we have to do the manual
1139 * wait. */
1140 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1141 intel_dp->panel_power_cycle_delay);
1142
1143 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1144 }
1145
1146 static void wait_backlight_on(struct intel_dp *intel_dp)
1147 {
1148 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1149 intel_dp->backlight_on_delay);
1150 }
1151
1152 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1153 {
1154 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1155 intel_dp->backlight_off_delay);
1156 }
1157
1158 /* Read the current pp_control value, unlocking the register if it
1159 * is locked
1160 */
1161
1162 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1163 {
1164 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 control;
1167
1168 control = I915_READ(_pp_ctrl_reg(intel_dp));
1169 control &= ~PANEL_UNLOCK_MASK;
1170 control |= PANEL_UNLOCK_REGS;
1171 return control;
1172 }
1173
1174 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1175 {
1176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 enum intel_display_power_domain power_domain;
1181 u32 pp;
1182 u32 pp_stat_reg, pp_ctrl_reg;
1183 bool need_to_disable = !intel_dp->want_panel_vdd;
1184
1185 if (!is_edp(intel_dp))
1186 return false;
1187
1188 intel_dp->want_panel_vdd = true;
1189
1190 if (edp_have_panel_vdd(intel_dp))
1191 return need_to_disable;
1192
1193 power_domain = intel_display_port_power_domain(intel_encoder);
1194 intel_display_power_get(dev_priv, power_domain);
1195
1196 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1197
1198 if (!edp_have_panel_power(intel_dp))
1199 wait_panel_power_cycle(intel_dp);
1200
1201 pp = ironlake_get_pp_control(intel_dp);
1202 pp |= EDP_FORCE_VDD;
1203
1204 pp_stat_reg = _pp_stat_reg(intel_dp);
1205 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1206
1207 I915_WRITE(pp_ctrl_reg, pp);
1208 POSTING_READ(pp_ctrl_reg);
1209 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1210 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1211 /*
1212 * If the panel wasn't on, delay before accessing aux channel
1213 */
1214 if (!edp_have_panel_power(intel_dp)) {
1215 DRM_DEBUG_KMS("eDP was not running\n");
1216 msleep(intel_dp->panel_power_up_delay);
1217 }
1218
1219 return need_to_disable;
1220 }
1221
1222 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1223 {
1224 if (is_edp(intel_dp)) {
1225 bool vdd = edp_panel_vdd_on(intel_dp);
1226
1227 WARN(!vdd, "eDP VDD already requested on\n");
1228 }
1229 }
1230
1231 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1232 {
1233 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 struct intel_digital_port *intel_dig_port =
1236 dp_to_dig_port(intel_dp);
1237 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1238 enum intel_display_power_domain power_domain;
1239 u32 pp;
1240 u32 pp_stat_reg, pp_ctrl_reg;
1241
1242 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1243
1244 WARN_ON(intel_dp->want_panel_vdd);
1245
1246 if (!edp_have_panel_vdd(intel_dp))
1247 return;
1248
1249 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1250
1251 pp = ironlake_get_pp_control(intel_dp);
1252 pp &= ~EDP_FORCE_VDD;
1253
1254 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1255 pp_stat_reg = _pp_stat_reg(intel_dp);
1256
1257 I915_WRITE(pp_ctrl_reg, pp);
1258 POSTING_READ(pp_ctrl_reg);
1259
1260 /* Make sure sequencer is idle before allowing subsequent activity */
1261 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1262 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1263
1264 if ((pp & POWER_TARGET_ON) == 0)
1265 intel_dp->last_power_cycle = jiffies;
1266
1267 power_domain = intel_display_port_power_domain(intel_encoder);
1268 intel_display_power_put(dev_priv, power_domain);
1269 }
1270
1271 static void edp_panel_vdd_work(struct work_struct *__work)
1272 {
1273 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1274 struct intel_dp, panel_vdd_work);
1275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1276
1277 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1278 if (!intel_dp->want_panel_vdd)
1279 edp_panel_vdd_off_sync(intel_dp);
1280 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1281 }
1282
1283 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1284 {
1285 unsigned long delay;
1286
1287 /*
1288 * Queue the timer to fire a long time from now (relative to the power
1289 * down delay) to keep the panel power up across a sequence of
1290 * operations.
1291 */
1292 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1293 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1294 }
1295
1296 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1297 {
1298 if (!is_edp(intel_dp))
1299 return;
1300
1301 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1302
1303 intel_dp->want_panel_vdd = false;
1304
1305 if (sync)
1306 edp_panel_vdd_off_sync(intel_dp);
1307 else
1308 edp_panel_vdd_schedule_off(intel_dp);
1309 }
1310
1311 static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1312 {
1313 edp_panel_vdd_off(intel_dp, sync);
1314 }
1315
1316 void intel_edp_panel_on(struct intel_dp *intel_dp)
1317 {
1318 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1319 struct drm_i915_private *dev_priv = dev->dev_private;
1320 u32 pp;
1321 u32 pp_ctrl_reg;
1322
1323 if (!is_edp(intel_dp))
1324 return;
1325
1326 DRM_DEBUG_KMS("Turn eDP power on\n");
1327
1328 if (edp_have_panel_power(intel_dp)) {
1329 DRM_DEBUG_KMS("eDP power already on\n");
1330 return;
1331 }
1332
1333 wait_panel_power_cycle(intel_dp);
1334
1335 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1336 pp = ironlake_get_pp_control(intel_dp);
1337 if (IS_GEN5(dev)) {
1338 /* ILK workaround: disable reset around power sequence */
1339 pp &= ~PANEL_POWER_RESET;
1340 I915_WRITE(pp_ctrl_reg, pp);
1341 POSTING_READ(pp_ctrl_reg);
1342 }
1343
1344 pp |= POWER_TARGET_ON;
1345 if (!IS_GEN5(dev))
1346 pp |= PANEL_POWER_RESET;
1347
1348 I915_WRITE(pp_ctrl_reg, pp);
1349 POSTING_READ(pp_ctrl_reg);
1350
1351 wait_panel_on(intel_dp);
1352 intel_dp->last_power_on = jiffies;
1353
1354 if (IS_GEN5(dev)) {
1355 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1356 I915_WRITE(pp_ctrl_reg, pp);
1357 POSTING_READ(pp_ctrl_reg);
1358 }
1359 }
1360
1361 void intel_edp_panel_off(struct intel_dp *intel_dp)
1362 {
1363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1364 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1365 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 enum intel_display_power_domain power_domain;
1368 u32 pp;
1369 u32 pp_ctrl_reg;
1370
1371 if (!is_edp(intel_dp))
1372 return;
1373
1374 DRM_DEBUG_KMS("Turn eDP power off\n");
1375
1376 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1377
1378 pp = ironlake_get_pp_control(intel_dp);
1379 /* We need to switch off panel power _and_ force vdd, for otherwise some
1380 * panels get very unhappy and cease to work. */
1381 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1382 EDP_BLC_ENABLE);
1383
1384 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1385
1386 intel_dp->want_panel_vdd = false;
1387
1388 I915_WRITE(pp_ctrl_reg, pp);
1389 POSTING_READ(pp_ctrl_reg);
1390
1391 intel_dp->last_power_cycle = jiffies;
1392 wait_panel_off(intel_dp);
1393
1394 /* We got a reference when we enabled the VDD. */
1395 power_domain = intel_display_port_power_domain(intel_encoder);
1396 intel_display_power_put(dev_priv, power_domain);
1397 }
1398
1399 /* Enable backlight in the panel power control. */
1400 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1401 {
1402 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1403 struct drm_device *dev = intel_dig_port->base.base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 u32 pp;
1406 u32 pp_ctrl_reg;
1407
1408 /*
1409 * If we enable the backlight right away following a panel power
1410 * on, we may see slight flicker as the panel syncs with the eDP
1411 * link. So delay a bit to make sure the image is solid before
1412 * allowing it to appear.
1413 */
1414 wait_backlight_on(intel_dp);
1415 pp = ironlake_get_pp_control(intel_dp);
1416 pp |= EDP_BLC_ENABLE;
1417
1418 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1419
1420 I915_WRITE(pp_ctrl_reg, pp);
1421 POSTING_READ(pp_ctrl_reg);
1422 }
1423
1424 /* Enable backlight PWM and backlight PP control. */
1425 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1426 {
1427 if (!is_edp(intel_dp))
1428 return;
1429
1430 DRM_DEBUG_KMS("\n");
1431
1432 intel_panel_enable_backlight(intel_dp->attached_connector);
1433 _intel_edp_backlight_on(intel_dp);
1434 }
1435
1436 /* Disable backlight in the panel power control. */
1437 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1438 {
1439 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 u32 pp;
1442 u32 pp_ctrl_reg;
1443
1444 pp = ironlake_get_pp_control(intel_dp);
1445 pp &= ~EDP_BLC_ENABLE;
1446
1447 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1448
1449 I915_WRITE(pp_ctrl_reg, pp);
1450 POSTING_READ(pp_ctrl_reg);
1451 intel_dp->last_backlight_off = jiffies;
1452
1453 edp_wait_backlight_off(intel_dp);
1454 }
1455
1456 /* Disable backlight PP control and backlight PWM. */
1457 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1458 {
1459 if (!is_edp(intel_dp))
1460 return;
1461
1462 DRM_DEBUG_KMS("\n");
1463
1464 _intel_edp_backlight_off(intel_dp);
1465 intel_panel_disable_backlight(intel_dp->attached_connector);
1466 }
1467
1468 /*
1469 * Hook for controlling the panel power control backlight through the bl_power
1470 * sysfs attribute. Take care to handle multiple calls.
1471 */
1472 static void intel_edp_backlight_power(struct intel_connector *connector,
1473 bool enable)
1474 {
1475 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1476 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1477
1478 if (is_enabled == enable)
1479 return;
1480
1481 DRM_DEBUG_KMS("\n");
1482
1483 if (enable)
1484 _intel_edp_backlight_on(intel_dp);
1485 else
1486 _intel_edp_backlight_off(intel_dp);
1487 }
1488
1489 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1490 {
1491 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1492 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1493 struct drm_device *dev = crtc->dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 u32 dpa_ctl;
1496
1497 assert_pipe_disabled(dev_priv,
1498 to_intel_crtc(crtc)->pipe);
1499
1500 DRM_DEBUG_KMS("\n");
1501 dpa_ctl = I915_READ(DP_A);
1502 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1503 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1504
1505 /* We don't adjust intel_dp->DP while tearing down the link, to
1506 * facilitate link retraining (e.g. after hotplug). Hence clear all
1507 * enable bits here to ensure that we don't enable too much. */
1508 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1509 intel_dp->DP |= DP_PLL_ENABLE;
1510 I915_WRITE(DP_A, intel_dp->DP);
1511 POSTING_READ(DP_A);
1512 udelay(200);
1513 }
1514
1515 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1516 {
1517 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1518 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1519 struct drm_device *dev = crtc->dev;
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 u32 dpa_ctl;
1522
1523 assert_pipe_disabled(dev_priv,
1524 to_intel_crtc(crtc)->pipe);
1525
1526 dpa_ctl = I915_READ(DP_A);
1527 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1528 "dp pll off, should be on\n");
1529 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1530
1531 /* We can't rely on the value tracked for the DP register in
1532 * intel_dp->DP because link_down must not change that (otherwise link
1533 * re-training will fail. */
1534 dpa_ctl &= ~DP_PLL_ENABLE;
1535 I915_WRITE(DP_A, dpa_ctl);
1536 POSTING_READ(DP_A);
1537 udelay(200);
1538 }
1539
1540 /* If the sink supports it, try to set the power state appropriately */
1541 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1542 {
1543 int ret, i;
1544
1545 /* Should have a valid DPCD by this point */
1546 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1547 return;
1548
1549 if (mode != DRM_MODE_DPMS_ON) {
1550 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1551 DP_SET_POWER_D3);
1552 if (ret != 1)
1553 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1554 } else {
1555 /*
1556 * When turning on, we need to retry for 1ms to give the sink
1557 * time to wake up.
1558 */
1559 for (i = 0; i < 3; i++) {
1560 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1561 DP_SET_POWER_D0);
1562 if (ret == 1)
1563 break;
1564 msleep(1);
1565 }
1566 }
1567 }
1568
1569 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1570 enum pipe *pipe)
1571 {
1572 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1573 enum port port = dp_to_dig_port(intel_dp)->port;
1574 struct drm_device *dev = encoder->base.dev;
1575 struct drm_i915_private *dev_priv = dev->dev_private;
1576 enum intel_display_power_domain power_domain;
1577 u32 tmp;
1578
1579 power_domain = intel_display_port_power_domain(encoder);
1580 if (!intel_display_power_enabled(dev_priv, power_domain))
1581 return false;
1582
1583 tmp = I915_READ(intel_dp->output_reg);
1584
1585 if (!(tmp & DP_PORT_EN))
1586 return false;
1587
1588 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1589 *pipe = PORT_TO_PIPE_CPT(tmp);
1590 } else if (IS_CHERRYVIEW(dev)) {
1591 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1592 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1593 *pipe = PORT_TO_PIPE(tmp);
1594 } else {
1595 u32 trans_sel;
1596 u32 trans_dp;
1597 int i;
1598
1599 switch (intel_dp->output_reg) {
1600 case PCH_DP_B:
1601 trans_sel = TRANS_DP_PORT_SEL_B;
1602 break;
1603 case PCH_DP_C:
1604 trans_sel = TRANS_DP_PORT_SEL_C;
1605 break;
1606 case PCH_DP_D:
1607 trans_sel = TRANS_DP_PORT_SEL_D;
1608 break;
1609 default:
1610 return true;
1611 }
1612
1613 for_each_pipe(dev_priv, i) {
1614 trans_dp = I915_READ(TRANS_DP_CTL(i));
1615 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1616 *pipe = i;
1617 return true;
1618 }
1619 }
1620
1621 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1622 intel_dp->output_reg);
1623 }
1624
1625 return true;
1626 }
1627
1628 static void intel_dp_get_config(struct intel_encoder *encoder,
1629 struct intel_crtc_config *pipe_config)
1630 {
1631 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1632 u32 tmp, flags = 0;
1633 struct drm_device *dev = encoder->base.dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 enum port port = dp_to_dig_port(intel_dp)->port;
1636 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1637 int dotclock;
1638
1639 tmp = I915_READ(intel_dp->output_reg);
1640 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1641 pipe_config->has_audio = true;
1642
1643 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1644 if (tmp & DP_SYNC_HS_HIGH)
1645 flags |= DRM_MODE_FLAG_PHSYNC;
1646 else
1647 flags |= DRM_MODE_FLAG_NHSYNC;
1648
1649 if (tmp & DP_SYNC_VS_HIGH)
1650 flags |= DRM_MODE_FLAG_PVSYNC;
1651 else
1652 flags |= DRM_MODE_FLAG_NVSYNC;
1653 } else {
1654 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1655 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1656 flags |= DRM_MODE_FLAG_PHSYNC;
1657 else
1658 flags |= DRM_MODE_FLAG_NHSYNC;
1659
1660 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1661 flags |= DRM_MODE_FLAG_PVSYNC;
1662 else
1663 flags |= DRM_MODE_FLAG_NVSYNC;
1664 }
1665
1666 pipe_config->adjusted_mode.flags |= flags;
1667
1668 pipe_config->has_dp_encoder = true;
1669
1670 intel_dp_get_m_n(crtc, pipe_config);
1671
1672 if (port == PORT_A) {
1673 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1674 pipe_config->port_clock = 162000;
1675 else
1676 pipe_config->port_clock = 270000;
1677 }
1678
1679 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1680 &pipe_config->dp_m_n);
1681
1682 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1683 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1684
1685 pipe_config->adjusted_mode.crtc_clock = dotclock;
1686
1687 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1688 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1689 /*
1690 * This is a big fat ugly hack.
1691 *
1692 * Some machines in UEFI boot mode provide us a VBT that has 18
1693 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1694 * unknown we fail to light up. Yet the same BIOS boots up with
1695 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1696 * max, not what it tells us to use.
1697 *
1698 * Note: This will still be broken if the eDP panel is not lit
1699 * up by the BIOS, and thus we can't get the mode at module
1700 * load.
1701 */
1702 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1703 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1704 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1705 }
1706 }
1707
1708 static bool is_edp_psr(struct intel_dp *intel_dp)
1709 {
1710 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1711 }
1712
1713 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1714 {
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716
1717 if (!HAS_PSR(dev))
1718 return false;
1719
1720 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1721 }
1722
1723 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1724 struct edp_vsc_psr *vsc_psr)
1725 {
1726 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1727 struct drm_device *dev = dig_port->base.base.dev;
1728 struct drm_i915_private *dev_priv = dev->dev_private;
1729 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1730 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1731 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1732 uint32_t *data = (uint32_t *) vsc_psr;
1733 unsigned int i;
1734
1735 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1736 the video DIP being updated before program video DIP data buffer
1737 registers for DIP being updated. */
1738 I915_WRITE(ctl_reg, 0);
1739 POSTING_READ(ctl_reg);
1740
1741 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1742 if (i < sizeof(struct edp_vsc_psr))
1743 I915_WRITE(data_reg + i, *data++);
1744 else
1745 I915_WRITE(data_reg + i, 0);
1746 }
1747
1748 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1749 POSTING_READ(ctl_reg);
1750 }
1751
1752 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1753 {
1754 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1755 struct drm_i915_private *dev_priv = dev->dev_private;
1756 struct edp_vsc_psr psr_vsc;
1757
1758 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1759 memset(&psr_vsc, 0, sizeof(psr_vsc));
1760 psr_vsc.sdp_header.HB0 = 0;
1761 psr_vsc.sdp_header.HB1 = 0x7;
1762 psr_vsc.sdp_header.HB2 = 0x2;
1763 psr_vsc.sdp_header.HB3 = 0x8;
1764 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1765
1766 /* Avoid continuous PSR exit by masking memup and hpd */
1767 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1768 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1769 }
1770
1771 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1772 {
1773 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1774 struct drm_device *dev = dig_port->base.base.dev;
1775 struct drm_i915_private *dev_priv = dev->dev_private;
1776 uint32_t aux_clock_divider;
1777 int precharge = 0x3;
1778 int msg_size = 5; /* Header(4) + Message(1) */
1779 bool only_standby = false;
1780
1781 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1782
1783 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1784 only_standby = true;
1785
1786 /* Enable PSR in sink */
1787 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1788 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1789 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1790 else
1791 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1792 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1793
1794 /* Setup AUX registers */
1795 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1796 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1797 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1798 DP_AUX_CH_CTL_TIME_OUT_400us |
1799 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1800 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1801 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1802 }
1803
1804 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1805 {
1806 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1807 struct drm_device *dev = dig_port->base.base.dev;
1808 struct drm_i915_private *dev_priv = dev->dev_private;
1809 uint32_t max_sleep_time = 0x1f;
1810 uint32_t idle_frames = 1;
1811 uint32_t val = 0x0;
1812 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1813 bool only_standby = false;
1814
1815 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1816 only_standby = true;
1817
1818 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1819 val |= EDP_PSR_LINK_STANDBY;
1820 val |= EDP_PSR_TP2_TP3_TIME_0us;
1821 val |= EDP_PSR_TP1_TIME_0us;
1822 val |= EDP_PSR_SKIP_AUX_EXIT;
1823 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1824 } else
1825 val |= EDP_PSR_LINK_DISABLE;
1826
1827 I915_WRITE(EDP_PSR_CTL(dev), val |
1828 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1829 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1830 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1831 EDP_PSR_ENABLE);
1832 }
1833
1834 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1835 {
1836 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1837 struct drm_device *dev = dig_port->base.base.dev;
1838 struct drm_i915_private *dev_priv = dev->dev_private;
1839 struct drm_crtc *crtc = dig_port->base.base.crtc;
1840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1841
1842 lockdep_assert_held(&dev_priv->psr.lock);
1843 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1844 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1845
1846 dev_priv->psr.source_ok = false;
1847
1848 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1849 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1850 return false;
1851 }
1852
1853 if (!i915.enable_psr) {
1854 DRM_DEBUG_KMS("PSR disable by flag\n");
1855 return false;
1856 }
1857
1858 /* Below limitations aren't valid for Broadwell */
1859 if (IS_BROADWELL(dev))
1860 goto out;
1861
1862 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1863 S3D_ENABLE) {
1864 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1865 return false;
1866 }
1867
1868 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1869 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1870 return false;
1871 }
1872
1873 out:
1874 dev_priv->psr.source_ok = true;
1875 return true;
1876 }
1877
1878 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1879 {
1880 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1881 struct drm_device *dev = intel_dig_port->base.base.dev;
1882 struct drm_i915_private *dev_priv = dev->dev_private;
1883
1884 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1885 WARN_ON(dev_priv->psr.active);
1886 lockdep_assert_held(&dev_priv->psr.lock);
1887
1888 /* Enable PSR on the panel */
1889 intel_edp_psr_enable_sink(intel_dp);
1890
1891 /* Enable PSR on the host */
1892 intel_edp_psr_enable_source(intel_dp);
1893
1894 dev_priv->psr.active = true;
1895 }
1896
1897 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1898 {
1899 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901
1902 if (!HAS_PSR(dev)) {
1903 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1904 return;
1905 }
1906
1907 if (!is_edp_psr(intel_dp)) {
1908 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1909 return;
1910 }
1911
1912 mutex_lock(&dev_priv->psr.lock);
1913 if (dev_priv->psr.enabled) {
1914 DRM_DEBUG_KMS("PSR already in use\n");
1915 mutex_unlock(&dev_priv->psr.lock);
1916 return;
1917 }
1918
1919 dev_priv->psr.busy_frontbuffer_bits = 0;
1920
1921 /* Setup PSR once */
1922 intel_edp_psr_setup(intel_dp);
1923
1924 if (intel_edp_psr_match_conditions(intel_dp))
1925 dev_priv->psr.enabled = intel_dp;
1926 mutex_unlock(&dev_priv->psr.lock);
1927 }
1928
1929 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1930 {
1931 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1932 struct drm_i915_private *dev_priv = dev->dev_private;
1933
1934 mutex_lock(&dev_priv->psr.lock);
1935 if (!dev_priv->psr.enabled) {
1936 mutex_unlock(&dev_priv->psr.lock);
1937 return;
1938 }
1939
1940 if (dev_priv->psr.active) {
1941 I915_WRITE(EDP_PSR_CTL(dev),
1942 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1943
1944 /* Wait till PSR is idle */
1945 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1946 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1947 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1948
1949 dev_priv->psr.active = false;
1950 } else {
1951 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1952 }
1953
1954 dev_priv->psr.enabled = NULL;
1955 mutex_unlock(&dev_priv->psr.lock);
1956
1957 cancel_delayed_work_sync(&dev_priv->psr.work);
1958 }
1959
1960 static void intel_edp_psr_work(struct work_struct *work)
1961 {
1962 struct drm_i915_private *dev_priv =
1963 container_of(work, typeof(*dev_priv), psr.work.work);
1964 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1965
1966 mutex_lock(&dev_priv->psr.lock);
1967 intel_dp = dev_priv->psr.enabled;
1968
1969 if (!intel_dp)
1970 goto unlock;
1971
1972 /*
1973 * The delayed work can race with an invalidate hence we need to
1974 * recheck. Since psr_flush first clears this and then reschedules we
1975 * won't ever miss a flush when bailing out here.
1976 */
1977 if (dev_priv->psr.busy_frontbuffer_bits)
1978 goto unlock;
1979
1980 intel_edp_psr_do_enable(intel_dp);
1981 unlock:
1982 mutex_unlock(&dev_priv->psr.lock);
1983 }
1984
1985 static void intel_edp_psr_do_exit(struct drm_device *dev)
1986 {
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988
1989 if (dev_priv->psr.active) {
1990 u32 val = I915_READ(EDP_PSR_CTL(dev));
1991
1992 WARN_ON(!(val & EDP_PSR_ENABLE));
1993
1994 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1995
1996 dev_priv->psr.active = false;
1997 }
1998
1999 }
2000
2001 void intel_edp_psr_invalidate(struct drm_device *dev,
2002 unsigned frontbuffer_bits)
2003 {
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct drm_crtc *crtc;
2006 enum pipe pipe;
2007
2008 mutex_lock(&dev_priv->psr.lock);
2009 if (!dev_priv->psr.enabled) {
2010 mutex_unlock(&dev_priv->psr.lock);
2011 return;
2012 }
2013
2014 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2015 pipe = to_intel_crtc(crtc)->pipe;
2016
2017 intel_edp_psr_do_exit(dev);
2018
2019 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2020
2021 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2022 mutex_unlock(&dev_priv->psr.lock);
2023 }
2024
2025 void intel_edp_psr_flush(struct drm_device *dev,
2026 unsigned frontbuffer_bits)
2027 {
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct drm_crtc *crtc;
2030 enum pipe pipe;
2031
2032 mutex_lock(&dev_priv->psr.lock);
2033 if (!dev_priv->psr.enabled) {
2034 mutex_unlock(&dev_priv->psr.lock);
2035 return;
2036 }
2037
2038 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2039 pipe = to_intel_crtc(crtc)->pipe;
2040 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2041
2042 /*
2043 * On Haswell sprite plane updates don't result in a psr invalidating
2044 * signal in the hardware. Which means we need to manually fake this in
2045 * software for all flushes, not just when we've seen a preceding
2046 * invalidation through frontbuffer rendering.
2047 */
2048 if (IS_HASWELL(dev) &&
2049 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2050 intel_edp_psr_do_exit(dev);
2051
2052 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2053 schedule_delayed_work(&dev_priv->psr.work,
2054 msecs_to_jiffies(100));
2055 mutex_unlock(&dev_priv->psr.lock);
2056 }
2057
2058 void intel_edp_psr_init(struct drm_device *dev)
2059 {
2060 struct drm_i915_private *dev_priv = dev->dev_private;
2061
2062 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2063 mutex_init(&dev_priv->psr.lock);
2064 }
2065
2066 static void intel_disable_dp(struct intel_encoder *encoder)
2067 {
2068 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2069 enum port port = dp_to_dig_port(intel_dp)->port;
2070 struct drm_device *dev = encoder->base.dev;
2071
2072 /* Make sure the panel is off before trying to change the mode. But also
2073 * ensure that we have vdd while we switch off the panel. */
2074 intel_edp_panel_vdd_on(intel_dp);
2075 intel_edp_backlight_off(intel_dp);
2076 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2077 intel_edp_panel_off(intel_dp);
2078
2079 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2080 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2081 intel_dp_link_down(intel_dp);
2082 }
2083
2084 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2085 {
2086 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2087 enum port port = dp_to_dig_port(intel_dp)->port;
2088
2089 if (port != PORT_A)
2090 return;
2091
2092 intel_dp_link_down(intel_dp);
2093 ironlake_edp_pll_off(intel_dp);
2094 }
2095
2096 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2097 {
2098 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2099
2100 intel_dp_link_down(intel_dp);
2101 }
2102
2103 static void chv_post_disable_dp(struct intel_encoder *encoder)
2104 {
2105 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2106 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2107 struct drm_device *dev = encoder->base.dev;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 struct intel_crtc *intel_crtc =
2110 to_intel_crtc(encoder->base.crtc);
2111 enum dpio_channel ch = vlv_dport_to_channel(dport);
2112 enum pipe pipe = intel_crtc->pipe;
2113 u32 val;
2114
2115 intel_dp_link_down(intel_dp);
2116
2117 mutex_lock(&dev_priv->dpio_lock);
2118
2119 /* Propagate soft reset to data lane reset */
2120 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2121 val |= CHV_PCS_REQ_SOFTRESET_EN;
2122 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2123
2124 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2125 val |= CHV_PCS_REQ_SOFTRESET_EN;
2126 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2127
2128 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2129 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2130 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2131
2132 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2133 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2134 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2135
2136 mutex_unlock(&dev_priv->dpio_lock);
2137 }
2138
2139 static void intel_enable_dp(struct intel_encoder *encoder)
2140 {
2141 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2142 struct drm_device *dev = encoder->base.dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2145
2146 if (WARN_ON(dp_reg & DP_PORT_EN))
2147 return;
2148
2149 intel_edp_panel_vdd_on(intel_dp);
2150 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2151 intel_dp_start_link_train(intel_dp);
2152 intel_edp_panel_on(intel_dp);
2153 intel_edp_panel_vdd_off(intel_dp, true);
2154 intel_dp_complete_link_train(intel_dp);
2155 intel_dp_stop_link_train(intel_dp);
2156 }
2157
2158 static void g4x_enable_dp(struct intel_encoder *encoder)
2159 {
2160 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2161
2162 intel_enable_dp(encoder);
2163 intel_edp_backlight_on(intel_dp);
2164 }
2165
2166 static void vlv_enable_dp(struct intel_encoder *encoder)
2167 {
2168 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2169
2170 intel_edp_backlight_on(intel_dp);
2171 }
2172
2173 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2174 {
2175 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2176 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2177
2178 intel_dp_prepare(encoder);
2179
2180 /* Only ilk+ has port A */
2181 if (dport->port == PORT_A) {
2182 ironlake_set_pll_cpu_edp(intel_dp);
2183 ironlake_edp_pll_on(intel_dp);
2184 }
2185 }
2186
2187 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2188 {
2189 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2190 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2191 struct drm_device *dev = encoder->base.dev;
2192 struct drm_i915_private *dev_priv = dev->dev_private;
2193 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2194 enum dpio_channel port = vlv_dport_to_channel(dport);
2195 int pipe = intel_crtc->pipe;
2196 struct edp_power_seq power_seq;
2197 u32 val;
2198
2199 mutex_lock(&dev_priv->dpio_lock);
2200
2201 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2202 val = 0;
2203 if (pipe)
2204 val |= (1<<21);
2205 else
2206 val &= ~(1<<21);
2207 val |= 0x001000c4;
2208 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2209 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2210 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2211
2212 mutex_unlock(&dev_priv->dpio_lock);
2213
2214 if (is_edp(intel_dp)) {
2215 /* init power sequencer on this pipe and port */
2216 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2217 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2218 &power_seq);
2219 }
2220
2221 intel_enable_dp(encoder);
2222
2223 vlv_wait_port_ready(dev_priv, dport);
2224 }
2225
2226 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2227 {
2228 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2229 struct drm_device *dev = encoder->base.dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 struct intel_crtc *intel_crtc =
2232 to_intel_crtc(encoder->base.crtc);
2233 enum dpio_channel port = vlv_dport_to_channel(dport);
2234 int pipe = intel_crtc->pipe;
2235
2236 intel_dp_prepare(encoder);
2237
2238 /* Program Tx lane resets to default */
2239 mutex_lock(&dev_priv->dpio_lock);
2240 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2241 DPIO_PCS_TX_LANE2_RESET |
2242 DPIO_PCS_TX_LANE1_RESET);
2243 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2244 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2245 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2246 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2247 DPIO_PCS_CLK_SOFT_RESET);
2248
2249 /* Fix up inter-pair skew failure */
2250 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2251 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2252 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2253 mutex_unlock(&dev_priv->dpio_lock);
2254 }
2255
2256 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2257 {
2258 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2259 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2260 struct drm_device *dev = encoder->base.dev;
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct edp_power_seq power_seq;
2263 struct intel_crtc *intel_crtc =
2264 to_intel_crtc(encoder->base.crtc);
2265 enum dpio_channel ch = vlv_dport_to_channel(dport);
2266 int pipe = intel_crtc->pipe;
2267 int data, i;
2268 u32 val;
2269
2270 mutex_lock(&dev_priv->dpio_lock);
2271
2272 /* Deassert soft data lane reset*/
2273 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2274 val |= CHV_PCS_REQ_SOFTRESET_EN;
2275 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2276
2277 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2278 val |= CHV_PCS_REQ_SOFTRESET_EN;
2279 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2280
2281 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2282 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2283 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2284
2285 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2286 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2287 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2288
2289 /* Program Tx lane latency optimal setting*/
2290 for (i = 0; i < 4; i++) {
2291 /* Set the latency optimal bit */
2292 data = (i == 1) ? 0x0 : 0x6;
2293 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2294 data << DPIO_FRC_LATENCY_SHFIT);
2295
2296 /* Set the upar bit */
2297 data = (i == 1) ? 0x0 : 0x1;
2298 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2299 data << DPIO_UPAR_SHIFT);
2300 }
2301
2302 /* Data lane stagger programming */
2303 /* FIXME: Fix up value only after power analysis */
2304
2305 mutex_unlock(&dev_priv->dpio_lock);
2306
2307 if (is_edp(intel_dp)) {
2308 /* init power sequencer on this pipe and port */
2309 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2310 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2311 &power_seq);
2312 }
2313
2314 intel_enable_dp(encoder);
2315
2316 vlv_wait_port_ready(dev_priv, dport);
2317 }
2318
2319 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2320 {
2321 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2322 struct drm_device *dev = encoder->base.dev;
2323 struct drm_i915_private *dev_priv = dev->dev_private;
2324 struct intel_crtc *intel_crtc =
2325 to_intel_crtc(encoder->base.crtc);
2326 enum dpio_channel ch = vlv_dport_to_channel(dport);
2327 enum pipe pipe = intel_crtc->pipe;
2328 u32 val;
2329
2330 intel_dp_prepare(encoder);
2331
2332 mutex_lock(&dev_priv->dpio_lock);
2333
2334 /* program left/right clock distribution */
2335 if (pipe != PIPE_B) {
2336 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2337 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2338 if (ch == DPIO_CH0)
2339 val |= CHV_BUFLEFTENA1_FORCE;
2340 if (ch == DPIO_CH1)
2341 val |= CHV_BUFRIGHTENA1_FORCE;
2342 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2343 } else {
2344 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2345 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2346 if (ch == DPIO_CH0)
2347 val |= CHV_BUFLEFTENA2_FORCE;
2348 if (ch == DPIO_CH1)
2349 val |= CHV_BUFRIGHTENA2_FORCE;
2350 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2351 }
2352
2353 /* program clock channel usage */
2354 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2355 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2356 if (pipe != PIPE_B)
2357 val &= ~CHV_PCS_USEDCLKCHANNEL;
2358 else
2359 val |= CHV_PCS_USEDCLKCHANNEL;
2360 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2361
2362 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2363 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2364 if (pipe != PIPE_B)
2365 val &= ~CHV_PCS_USEDCLKCHANNEL;
2366 else
2367 val |= CHV_PCS_USEDCLKCHANNEL;
2368 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2369
2370 /*
2371 * This a a bit weird since generally CL
2372 * matches the pipe, but here we need to
2373 * pick the CL based on the port.
2374 */
2375 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2376 if (pipe != PIPE_B)
2377 val &= ~CHV_CMN_USEDCLKCHANNEL;
2378 else
2379 val |= CHV_CMN_USEDCLKCHANNEL;
2380 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2381
2382 mutex_unlock(&dev_priv->dpio_lock);
2383 }
2384
2385 /*
2386 * Native read with retry for link status and receiver capability reads for
2387 * cases where the sink may still be asleep.
2388 *
2389 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2390 * supposed to retry 3 times per the spec.
2391 */
2392 static ssize_t
2393 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2394 void *buffer, size_t size)
2395 {
2396 ssize_t ret;
2397 int i;
2398
2399 for (i = 0; i < 3; i++) {
2400 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2401 if (ret == size)
2402 return ret;
2403 msleep(1);
2404 }
2405
2406 return ret;
2407 }
2408
2409 /*
2410 * Fetch AUX CH registers 0x202 - 0x207 which contain
2411 * link status information
2412 */
2413 static bool
2414 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2415 {
2416 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2417 DP_LANE0_1_STATUS,
2418 link_status,
2419 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2420 }
2421
2422 /* These are source-specific values. */
2423 static uint8_t
2424 intel_dp_voltage_max(struct intel_dp *intel_dp)
2425 {
2426 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2427 enum port port = dp_to_dig_port(intel_dp)->port;
2428
2429 if (IS_VALLEYVIEW(dev))
2430 return DP_TRAIN_VOLTAGE_SWING_1200;
2431 else if (IS_GEN7(dev) && port == PORT_A)
2432 return DP_TRAIN_VOLTAGE_SWING_800;
2433 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2434 return DP_TRAIN_VOLTAGE_SWING_1200;
2435 else
2436 return DP_TRAIN_VOLTAGE_SWING_800;
2437 }
2438
2439 static uint8_t
2440 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2441 {
2442 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2443 enum port port = dp_to_dig_port(intel_dp)->port;
2444
2445 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2446 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2447 case DP_TRAIN_VOLTAGE_SWING_400:
2448 return DP_TRAIN_PRE_EMPHASIS_9_5;
2449 case DP_TRAIN_VOLTAGE_SWING_600:
2450 return DP_TRAIN_PRE_EMPHASIS_6;
2451 case DP_TRAIN_VOLTAGE_SWING_800:
2452 return DP_TRAIN_PRE_EMPHASIS_3_5;
2453 case DP_TRAIN_VOLTAGE_SWING_1200:
2454 default:
2455 return DP_TRAIN_PRE_EMPHASIS_0;
2456 }
2457 } else if (IS_VALLEYVIEW(dev)) {
2458 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2459 case DP_TRAIN_VOLTAGE_SWING_400:
2460 return DP_TRAIN_PRE_EMPHASIS_9_5;
2461 case DP_TRAIN_VOLTAGE_SWING_600:
2462 return DP_TRAIN_PRE_EMPHASIS_6;
2463 case DP_TRAIN_VOLTAGE_SWING_800:
2464 return DP_TRAIN_PRE_EMPHASIS_3_5;
2465 case DP_TRAIN_VOLTAGE_SWING_1200:
2466 default:
2467 return DP_TRAIN_PRE_EMPHASIS_0;
2468 }
2469 } else if (IS_GEN7(dev) && port == PORT_A) {
2470 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2471 case DP_TRAIN_VOLTAGE_SWING_400:
2472 return DP_TRAIN_PRE_EMPHASIS_6;
2473 case DP_TRAIN_VOLTAGE_SWING_600:
2474 case DP_TRAIN_VOLTAGE_SWING_800:
2475 return DP_TRAIN_PRE_EMPHASIS_3_5;
2476 default:
2477 return DP_TRAIN_PRE_EMPHASIS_0;
2478 }
2479 } else {
2480 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2481 case DP_TRAIN_VOLTAGE_SWING_400:
2482 return DP_TRAIN_PRE_EMPHASIS_6;
2483 case DP_TRAIN_VOLTAGE_SWING_600:
2484 return DP_TRAIN_PRE_EMPHASIS_6;
2485 case DP_TRAIN_VOLTAGE_SWING_800:
2486 return DP_TRAIN_PRE_EMPHASIS_3_5;
2487 case DP_TRAIN_VOLTAGE_SWING_1200:
2488 default:
2489 return DP_TRAIN_PRE_EMPHASIS_0;
2490 }
2491 }
2492 }
2493
2494 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2495 {
2496 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2499 struct intel_crtc *intel_crtc =
2500 to_intel_crtc(dport->base.base.crtc);
2501 unsigned long demph_reg_value, preemph_reg_value,
2502 uniqtranscale_reg_value;
2503 uint8_t train_set = intel_dp->train_set[0];
2504 enum dpio_channel port = vlv_dport_to_channel(dport);
2505 int pipe = intel_crtc->pipe;
2506
2507 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2508 case DP_TRAIN_PRE_EMPHASIS_0:
2509 preemph_reg_value = 0x0004000;
2510 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2511 case DP_TRAIN_VOLTAGE_SWING_400:
2512 demph_reg_value = 0x2B405555;
2513 uniqtranscale_reg_value = 0x552AB83A;
2514 break;
2515 case DP_TRAIN_VOLTAGE_SWING_600:
2516 demph_reg_value = 0x2B404040;
2517 uniqtranscale_reg_value = 0x5548B83A;
2518 break;
2519 case DP_TRAIN_VOLTAGE_SWING_800:
2520 demph_reg_value = 0x2B245555;
2521 uniqtranscale_reg_value = 0x5560B83A;
2522 break;
2523 case DP_TRAIN_VOLTAGE_SWING_1200:
2524 demph_reg_value = 0x2B405555;
2525 uniqtranscale_reg_value = 0x5598DA3A;
2526 break;
2527 default:
2528 return 0;
2529 }
2530 break;
2531 case DP_TRAIN_PRE_EMPHASIS_3_5:
2532 preemph_reg_value = 0x0002000;
2533 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2534 case DP_TRAIN_VOLTAGE_SWING_400:
2535 demph_reg_value = 0x2B404040;
2536 uniqtranscale_reg_value = 0x5552B83A;
2537 break;
2538 case DP_TRAIN_VOLTAGE_SWING_600:
2539 demph_reg_value = 0x2B404848;
2540 uniqtranscale_reg_value = 0x5580B83A;
2541 break;
2542 case DP_TRAIN_VOLTAGE_SWING_800:
2543 demph_reg_value = 0x2B404040;
2544 uniqtranscale_reg_value = 0x55ADDA3A;
2545 break;
2546 default:
2547 return 0;
2548 }
2549 break;
2550 case DP_TRAIN_PRE_EMPHASIS_6:
2551 preemph_reg_value = 0x0000000;
2552 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2553 case DP_TRAIN_VOLTAGE_SWING_400:
2554 demph_reg_value = 0x2B305555;
2555 uniqtranscale_reg_value = 0x5570B83A;
2556 break;
2557 case DP_TRAIN_VOLTAGE_SWING_600:
2558 demph_reg_value = 0x2B2B4040;
2559 uniqtranscale_reg_value = 0x55ADDA3A;
2560 break;
2561 default:
2562 return 0;
2563 }
2564 break;
2565 case DP_TRAIN_PRE_EMPHASIS_9_5:
2566 preemph_reg_value = 0x0006000;
2567 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2568 case DP_TRAIN_VOLTAGE_SWING_400:
2569 demph_reg_value = 0x1B405555;
2570 uniqtranscale_reg_value = 0x55ADDA3A;
2571 break;
2572 default:
2573 return 0;
2574 }
2575 break;
2576 default:
2577 return 0;
2578 }
2579
2580 mutex_lock(&dev_priv->dpio_lock);
2581 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2582 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2583 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2584 uniqtranscale_reg_value);
2585 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2586 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2587 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2589 mutex_unlock(&dev_priv->dpio_lock);
2590
2591 return 0;
2592 }
2593
2594 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2595 {
2596 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2599 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2600 u32 deemph_reg_value, margin_reg_value, val;
2601 uint8_t train_set = intel_dp->train_set[0];
2602 enum dpio_channel ch = vlv_dport_to_channel(dport);
2603 enum pipe pipe = intel_crtc->pipe;
2604 int i;
2605
2606 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2607 case DP_TRAIN_PRE_EMPHASIS_0:
2608 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2609 case DP_TRAIN_VOLTAGE_SWING_400:
2610 deemph_reg_value = 128;
2611 margin_reg_value = 52;
2612 break;
2613 case DP_TRAIN_VOLTAGE_SWING_600:
2614 deemph_reg_value = 128;
2615 margin_reg_value = 77;
2616 break;
2617 case DP_TRAIN_VOLTAGE_SWING_800:
2618 deemph_reg_value = 128;
2619 margin_reg_value = 102;
2620 break;
2621 case DP_TRAIN_VOLTAGE_SWING_1200:
2622 deemph_reg_value = 128;
2623 margin_reg_value = 154;
2624 /* FIXME extra to set for 1200 */
2625 break;
2626 default:
2627 return 0;
2628 }
2629 break;
2630 case DP_TRAIN_PRE_EMPHASIS_3_5:
2631 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2632 case DP_TRAIN_VOLTAGE_SWING_400:
2633 deemph_reg_value = 85;
2634 margin_reg_value = 78;
2635 break;
2636 case DP_TRAIN_VOLTAGE_SWING_600:
2637 deemph_reg_value = 85;
2638 margin_reg_value = 116;
2639 break;
2640 case DP_TRAIN_VOLTAGE_SWING_800:
2641 deemph_reg_value = 85;
2642 margin_reg_value = 154;
2643 break;
2644 default:
2645 return 0;
2646 }
2647 break;
2648 case DP_TRAIN_PRE_EMPHASIS_6:
2649 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2650 case DP_TRAIN_VOLTAGE_SWING_400:
2651 deemph_reg_value = 64;
2652 margin_reg_value = 104;
2653 break;
2654 case DP_TRAIN_VOLTAGE_SWING_600:
2655 deemph_reg_value = 64;
2656 margin_reg_value = 154;
2657 break;
2658 default:
2659 return 0;
2660 }
2661 break;
2662 case DP_TRAIN_PRE_EMPHASIS_9_5:
2663 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2664 case DP_TRAIN_VOLTAGE_SWING_400:
2665 deemph_reg_value = 43;
2666 margin_reg_value = 154;
2667 break;
2668 default:
2669 return 0;
2670 }
2671 break;
2672 default:
2673 return 0;
2674 }
2675
2676 mutex_lock(&dev_priv->dpio_lock);
2677
2678 /* Clear calc init */
2679 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2680 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2681 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2682
2683 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2684 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2685 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2686
2687 /* Program swing deemph */
2688 for (i = 0; i < 4; i++) {
2689 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2690 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2691 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2692 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2693 }
2694
2695 /* Program swing margin */
2696 for (i = 0; i < 4; i++) {
2697 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2698 val &= ~DPIO_SWING_MARGIN000_MASK;
2699 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2700 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2701 }
2702
2703 /* Disable unique transition scale */
2704 for (i = 0; i < 4; i++) {
2705 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2706 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2707 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2708 }
2709
2710 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2711 == DP_TRAIN_PRE_EMPHASIS_0) &&
2712 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2713 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2714
2715 /*
2716 * The document said it needs to set bit 27 for ch0 and bit 26
2717 * for ch1. Might be a typo in the doc.
2718 * For now, for this unique transition scale selection, set bit
2719 * 27 for ch0 and ch1.
2720 */
2721 for (i = 0; i < 4; i++) {
2722 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2723 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2724 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2725 }
2726
2727 for (i = 0; i < 4; i++) {
2728 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2729 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2730 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2731 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2732 }
2733 }
2734
2735 /* Start swing calculation */
2736 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2737 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2738 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2739
2740 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2741 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2742 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2743
2744 /* LRC Bypass */
2745 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2746 val |= DPIO_LRC_BYPASS;
2747 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2748
2749 mutex_unlock(&dev_priv->dpio_lock);
2750
2751 return 0;
2752 }
2753
2754 static void
2755 intel_get_adjust_train(struct intel_dp *intel_dp,
2756 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2757 {
2758 uint8_t v = 0;
2759 uint8_t p = 0;
2760 int lane;
2761 uint8_t voltage_max;
2762 uint8_t preemph_max;
2763
2764 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2765 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2766 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2767
2768 if (this_v > v)
2769 v = this_v;
2770 if (this_p > p)
2771 p = this_p;
2772 }
2773
2774 voltage_max = intel_dp_voltage_max(intel_dp);
2775 if (v >= voltage_max)
2776 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2777
2778 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2779 if (p >= preemph_max)
2780 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2781
2782 for (lane = 0; lane < 4; lane++)
2783 intel_dp->train_set[lane] = v | p;
2784 }
2785
2786 static uint32_t
2787 intel_gen4_signal_levels(uint8_t train_set)
2788 {
2789 uint32_t signal_levels = 0;
2790
2791 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2792 case DP_TRAIN_VOLTAGE_SWING_400:
2793 default:
2794 signal_levels |= DP_VOLTAGE_0_4;
2795 break;
2796 case DP_TRAIN_VOLTAGE_SWING_600:
2797 signal_levels |= DP_VOLTAGE_0_6;
2798 break;
2799 case DP_TRAIN_VOLTAGE_SWING_800:
2800 signal_levels |= DP_VOLTAGE_0_8;
2801 break;
2802 case DP_TRAIN_VOLTAGE_SWING_1200:
2803 signal_levels |= DP_VOLTAGE_1_2;
2804 break;
2805 }
2806 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2807 case DP_TRAIN_PRE_EMPHASIS_0:
2808 default:
2809 signal_levels |= DP_PRE_EMPHASIS_0;
2810 break;
2811 case DP_TRAIN_PRE_EMPHASIS_3_5:
2812 signal_levels |= DP_PRE_EMPHASIS_3_5;
2813 break;
2814 case DP_TRAIN_PRE_EMPHASIS_6:
2815 signal_levels |= DP_PRE_EMPHASIS_6;
2816 break;
2817 case DP_TRAIN_PRE_EMPHASIS_9_5:
2818 signal_levels |= DP_PRE_EMPHASIS_9_5;
2819 break;
2820 }
2821 return signal_levels;
2822 }
2823
2824 /* Gen6's DP voltage swing and pre-emphasis control */
2825 static uint32_t
2826 intel_gen6_edp_signal_levels(uint8_t train_set)
2827 {
2828 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2829 DP_TRAIN_PRE_EMPHASIS_MASK);
2830 switch (signal_levels) {
2831 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2832 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2833 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2834 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2835 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2836 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2837 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2838 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2839 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2840 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2841 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2842 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2843 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2844 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2845 default:
2846 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2847 "0x%x\n", signal_levels);
2848 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2849 }
2850 }
2851
2852 /* Gen7's DP voltage swing and pre-emphasis control */
2853 static uint32_t
2854 intel_gen7_edp_signal_levels(uint8_t train_set)
2855 {
2856 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2857 DP_TRAIN_PRE_EMPHASIS_MASK);
2858 switch (signal_levels) {
2859 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2860 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2861 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2862 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2863 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2864 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2865
2866 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2867 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2868 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2869 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2870
2871 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2872 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2873 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2874 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2875
2876 default:
2877 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2878 "0x%x\n", signal_levels);
2879 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2880 }
2881 }
2882
2883 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2884 static uint32_t
2885 intel_hsw_signal_levels(uint8_t train_set)
2886 {
2887 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2888 DP_TRAIN_PRE_EMPHASIS_MASK);
2889 switch (signal_levels) {
2890 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2891 return DDI_BUF_EMP_400MV_0DB_HSW;
2892 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2893 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2894 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2895 return DDI_BUF_EMP_400MV_6DB_HSW;
2896 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2897 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2898
2899 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2900 return DDI_BUF_EMP_600MV_0DB_HSW;
2901 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2902 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2903 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2904 return DDI_BUF_EMP_600MV_6DB_HSW;
2905
2906 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2907 return DDI_BUF_EMP_800MV_0DB_HSW;
2908 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2909 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2910 default:
2911 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2912 "0x%x\n", signal_levels);
2913 return DDI_BUF_EMP_400MV_0DB_HSW;
2914 }
2915 }
2916
2917 /* Properly updates "DP" with the correct signal levels. */
2918 static void
2919 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2920 {
2921 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2922 enum port port = intel_dig_port->port;
2923 struct drm_device *dev = intel_dig_port->base.base.dev;
2924 uint32_t signal_levels, mask;
2925 uint8_t train_set = intel_dp->train_set[0];
2926
2927 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2928 signal_levels = intel_hsw_signal_levels(train_set);
2929 mask = DDI_BUF_EMP_MASK;
2930 } else if (IS_CHERRYVIEW(dev)) {
2931 signal_levels = intel_chv_signal_levels(intel_dp);
2932 mask = 0;
2933 } else if (IS_VALLEYVIEW(dev)) {
2934 signal_levels = intel_vlv_signal_levels(intel_dp);
2935 mask = 0;
2936 } else if (IS_GEN7(dev) && port == PORT_A) {
2937 signal_levels = intel_gen7_edp_signal_levels(train_set);
2938 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2939 } else if (IS_GEN6(dev) && port == PORT_A) {
2940 signal_levels = intel_gen6_edp_signal_levels(train_set);
2941 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2942 } else {
2943 signal_levels = intel_gen4_signal_levels(train_set);
2944 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2945 }
2946
2947 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2948
2949 *DP = (*DP & ~mask) | signal_levels;
2950 }
2951
2952 static bool
2953 intel_dp_set_link_train(struct intel_dp *intel_dp,
2954 uint32_t *DP,
2955 uint8_t dp_train_pat)
2956 {
2957 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2958 struct drm_device *dev = intel_dig_port->base.base.dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 enum port port = intel_dig_port->port;
2961 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2962 int ret, len;
2963
2964 if (HAS_DDI(dev)) {
2965 uint32_t temp = I915_READ(DP_TP_CTL(port));
2966
2967 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2968 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2969 else
2970 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2971
2972 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2973 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2974 case DP_TRAINING_PATTERN_DISABLE:
2975 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2976
2977 break;
2978 case DP_TRAINING_PATTERN_1:
2979 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2980 break;
2981 case DP_TRAINING_PATTERN_2:
2982 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2983 break;
2984 case DP_TRAINING_PATTERN_3:
2985 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2986 break;
2987 }
2988 I915_WRITE(DP_TP_CTL(port), temp);
2989
2990 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2991 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2992
2993 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2994 case DP_TRAINING_PATTERN_DISABLE:
2995 *DP |= DP_LINK_TRAIN_OFF_CPT;
2996 break;
2997 case DP_TRAINING_PATTERN_1:
2998 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2999 break;
3000 case DP_TRAINING_PATTERN_2:
3001 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3002 break;
3003 case DP_TRAINING_PATTERN_3:
3004 DRM_ERROR("DP training pattern 3 not supported\n");
3005 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3006 break;
3007 }
3008
3009 } else {
3010 if (IS_CHERRYVIEW(dev))
3011 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3012 else
3013 *DP &= ~DP_LINK_TRAIN_MASK;
3014
3015 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3016 case DP_TRAINING_PATTERN_DISABLE:
3017 *DP |= DP_LINK_TRAIN_OFF;
3018 break;
3019 case DP_TRAINING_PATTERN_1:
3020 *DP |= DP_LINK_TRAIN_PAT_1;
3021 break;
3022 case DP_TRAINING_PATTERN_2:
3023 *DP |= DP_LINK_TRAIN_PAT_2;
3024 break;
3025 case DP_TRAINING_PATTERN_3:
3026 if (IS_CHERRYVIEW(dev)) {
3027 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3028 } else {
3029 DRM_ERROR("DP training pattern 3 not supported\n");
3030 *DP |= DP_LINK_TRAIN_PAT_2;
3031 }
3032 break;
3033 }
3034 }
3035
3036 I915_WRITE(intel_dp->output_reg, *DP);
3037 POSTING_READ(intel_dp->output_reg);
3038
3039 buf[0] = dp_train_pat;
3040 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3041 DP_TRAINING_PATTERN_DISABLE) {
3042 /* don't write DP_TRAINING_LANEx_SET on disable */
3043 len = 1;
3044 } else {
3045 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3046 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3047 len = intel_dp->lane_count + 1;
3048 }
3049
3050 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3051 buf, len);
3052
3053 return ret == len;
3054 }
3055
3056 static bool
3057 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3058 uint8_t dp_train_pat)
3059 {
3060 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3061 intel_dp_set_signal_levels(intel_dp, DP);
3062 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3063 }
3064
3065 static bool
3066 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3067 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3068 {
3069 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3070 struct drm_device *dev = intel_dig_port->base.base.dev;
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072 int ret;
3073
3074 intel_get_adjust_train(intel_dp, link_status);
3075 intel_dp_set_signal_levels(intel_dp, DP);
3076
3077 I915_WRITE(intel_dp->output_reg, *DP);
3078 POSTING_READ(intel_dp->output_reg);
3079
3080 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3081 intel_dp->train_set, intel_dp->lane_count);
3082
3083 return ret == intel_dp->lane_count;
3084 }
3085
3086 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3087 {
3088 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3089 struct drm_device *dev = intel_dig_port->base.base.dev;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 enum port port = intel_dig_port->port;
3092 uint32_t val;
3093
3094 if (!HAS_DDI(dev))
3095 return;
3096
3097 val = I915_READ(DP_TP_CTL(port));
3098 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3099 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3100 I915_WRITE(DP_TP_CTL(port), val);
3101
3102 /*
3103 * On PORT_A we can have only eDP in SST mode. There the only reason
3104 * we need to set idle transmission mode is to work around a HW issue
3105 * where we enable the pipe while not in idle link-training mode.
3106 * In this case there is requirement to wait for a minimum number of
3107 * idle patterns to be sent.
3108 */
3109 if (port == PORT_A)
3110 return;
3111
3112 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3113 1))
3114 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3115 }
3116
3117 /* Enable corresponding port and start training pattern 1 */
3118 void
3119 intel_dp_start_link_train(struct intel_dp *intel_dp)
3120 {
3121 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3122 struct drm_device *dev = encoder->dev;
3123 int i;
3124 uint8_t voltage;
3125 int voltage_tries, loop_tries;
3126 uint32_t DP = intel_dp->DP;
3127 uint8_t link_config[2];
3128
3129 if (HAS_DDI(dev))
3130 intel_ddi_prepare_link_retrain(encoder);
3131
3132 /* Write the link configuration data */
3133 link_config[0] = intel_dp->link_bw;
3134 link_config[1] = intel_dp->lane_count;
3135 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3136 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3137 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3138
3139 link_config[0] = 0;
3140 link_config[1] = DP_SET_ANSI_8B10B;
3141 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3142
3143 DP |= DP_PORT_EN;
3144
3145 /* clock recovery */
3146 if (!intel_dp_reset_link_train(intel_dp, &DP,
3147 DP_TRAINING_PATTERN_1 |
3148 DP_LINK_SCRAMBLING_DISABLE)) {
3149 DRM_ERROR("failed to enable link training\n");
3150 return;
3151 }
3152
3153 voltage = 0xff;
3154 voltage_tries = 0;
3155 loop_tries = 0;
3156 for (;;) {
3157 uint8_t link_status[DP_LINK_STATUS_SIZE];
3158
3159 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3160 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3161 DRM_ERROR("failed to get link status\n");
3162 break;
3163 }
3164
3165 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3166 DRM_DEBUG_KMS("clock recovery OK\n");
3167 break;
3168 }
3169
3170 /* Check to see if we've tried the max voltage */
3171 for (i = 0; i < intel_dp->lane_count; i++)
3172 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3173 break;
3174 if (i == intel_dp->lane_count) {
3175 ++loop_tries;
3176 if (loop_tries == 5) {
3177 DRM_ERROR("too many full retries, give up\n");
3178 break;
3179 }
3180 intel_dp_reset_link_train(intel_dp, &DP,
3181 DP_TRAINING_PATTERN_1 |
3182 DP_LINK_SCRAMBLING_DISABLE);
3183 voltage_tries = 0;
3184 continue;
3185 }
3186
3187 /* Check to see if we've tried the same voltage 5 times */
3188 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3189 ++voltage_tries;
3190 if (voltage_tries == 5) {
3191 DRM_ERROR("too many voltage retries, give up\n");
3192 break;
3193 }
3194 } else
3195 voltage_tries = 0;
3196 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3197
3198 /* Update training set as requested by target */
3199 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3200 DRM_ERROR("failed to update link training\n");
3201 break;
3202 }
3203 }
3204
3205 intel_dp->DP = DP;
3206 }
3207
3208 void
3209 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3210 {
3211 bool channel_eq = false;
3212 int tries, cr_tries;
3213 uint32_t DP = intel_dp->DP;
3214 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3215
3216 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3217 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3218 training_pattern = DP_TRAINING_PATTERN_3;
3219
3220 /* channel equalization */
3221 if (!intel_dp_set_link_train(intel_dp, &DP,
3222 training_pattern |
3223 DP_LINK_SCRAMBLING_DISABLE)) {
3224 DRM_ERROR("failed to start channel equalization\n");
3225 return;
3226 }
3227
3228 tries = 0;
3229 cr_tries = 0;
3230 channel_eq = false;
3231 for (;;) {
3232 uint8_t link_status[DP_LINK_STATUS_SIZE];
3233
3234 if (cr_tries > 5) {
3235 DRM_ERROR("failed to train DP, aborting\n");
3236 break;
3237 }
3238
3239 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3240 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3241 DRM_ERROR("failed to get link status\n");
3242 break;
3243 }
3244
3245 /* Make sure clock is still ok */
3246 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3247 intel_dp_start_link_train(intel_dp);
3248 intel_dp_set_link_train(intel_dp, &DP,
3249 training_pattern |
3250 DP_LINK_SCRAMBLING_DISABLE);
3251 cr_tries++;
3252 continue;
3253 }
3254
3255 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3256 channel_eq = true;
3257 break;
3258 }
3259
3260 /* Try 5 times, then try clock recovery if that fails */
3261 if (tries > 5) {
3262 intel_dp_link_down(intel_dp);
3263 intel_dp_start_link_train(intel_dp);
3264 intel_dp_set_link_train(intel_dp, &DP,
3265 training_pattern |
3266 DP_LINK_SCRAMBLING_DISABLE);
3267 tries = 0;
3268 cr_tries++;
3269 continue;
3270 }
3271
3272 /* Update training set as requested by target */
3273 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3274 DRM_ERROR("failed to update link training\n");
3275 break;
3276 }
3277 ++tries;
3278 }
3279
3280 intel_dp_set_idle_link_train(intel_dp);
3281
3282 intel_dp->DP = DP;
3283
3284 if (channel_eq)
3285 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3286
3287 }
3288
3289 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3290 {
3291 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3292 DP_TRAINING_PATTERN_DISABLE);
3293 }
3294
3295 static void
3296 intel_dp_link_down(struct intel_dp *intel_dp)
3297 {
3298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3299 enum port port = intel_dig_port->port;
3300 struct drm_device *dev = intel_dig_port->base.base.dev;
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 struct intel_crtc *intel_crtc =
3303 to_intel_crtc(intel_dig_port->base.base.crtc);
3304 uint32_t DP = intel_dp->DP;
3305
3306 if (WARN_ON(HAS_DDI(dev)))
3307 return;
3308
3309 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3310 return;
3311
3312 DRM_DEBUG_KMS("\n");
3313
3314 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3315 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3316 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3317 } else {
3318 if (IS_CHERRYVIEW(dev))
3319 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3320 else
3321 DP &= ~DP_LINK_TRAIN_MASK;
3322 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3323 }
3324 POSTING_READ(intel_dp->output_reg);
3325
3326 if (HAS_PCH_IBX(dev) &&
3327 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3328 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3329
3330 /* Hardware workaround: leaving our transcoder select
3331 * set to transcoder B while it's off will prevent the
3332 * corresponding HDMI output on transcoder A.
3333 *
3334 * Combine this with another hardware workaround:
3335 * transcoder select bit can only be cleared while the
3336 * port is enabled.
3337 */
3338 DP &= ~DP_PIPEB_SELECT;
3339 I915_WRITE(intel_dp->output_reg, DP);
3340
3341 /* Changes to enable or select take place the vblank
3342 * after being written.
3343 */
3344 if (WARN_ON(crtc == NULL)) {
3345 /* We should never try to disable a port without a crtc
3346 * attached. For paranoia keep the code around for a
3347 * bit. */
3348 POSTING_READ(intel_dp->output_reg);
3349 msleep(50);
3350 } else
3351 intel_wait_for_vblank(dev, intel_crtc->pipe);
3352 }
3353
3354 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3356 POSTING_READ(intel_dp->output_reg);
3357 msleep(intel_dp->panel_power_down_delay);
3358 }
3359
3360 static bool
3361 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3362 {
3363 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3364 struct drm_device *dev = dig_port->base.base.dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366
3367 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3368
3369 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3370 sizeof(intel_dp->dpcd)) < 0)
3371 return false; /* aux transfer failed */
3372
3373 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3374 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3375 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3376
3377 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3378 return false; /* DPCD not present */
3379
3380 /* Check if the panel supports PSR */
3381 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3382 if (is_edp(intel_dp)) {
3383 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3384 intel_dp->psr_dpcd,
3385 sizeof(intel_dp->psr_dpcd));
3386 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3387 dev_priv->psr.sink_support = true;
3388 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3389 }
3390 }
3391
3392 /* Training Pattern 3 support */
3393 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3394 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3395 intel_dp->use_tps3 = true;
3396 DRM_DEBUG_KMS("Displayport TPS3 supported");
3397 } else
3398 intel_dp->use_tps3 = false;
3399
3400 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3401 DP_DWN_STRM_PORT_PRESENT))
3402 return true; /* native DP sink */
3403
3404 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3405 return true; /* no per-port downstream info */
3406
3407 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3408 intel_dp->downstream_ports,
3409 DP_MAX_DOWNSTREAM_PORTS) < 0)
3410 return false; /* downstream port status fetch failed */
3411
3412 return true;
3413 }
3414
3415 static void
3416 intel_dp_probe_oui(struct intel_dp *intel_dp)
3417 {
3418 u8 buf[3];
3419
3420 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3421 return;
3422
3423 intel_edp_panel_vdd_on(intel_dp);
3424
3425 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3426 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3427 buf[0], buf[1], buf[2]);
3428
3429 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3430 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3431 buf[0], buf[1], buf[2]);
3432
3433 intel_edp_panel_vdd_off(intel_dp, false);
3434 }
3435
3436 static bool
3437 intel_dp_probe_mst(struct intel_dp *intel_dp)
3438 {
3439 u8 buf[1];
3440
3441 if (!intel_dp->can_mst)
3442 return false;
3443
3444 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3445 return false;
3446
3447 intel_edp_panel_vdd_on(intel_dp);
3448 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3449 if (buf[0] & DP_MST_CAP) {
3450 DRM_DEBUG_KMS("Sink is MST capable\n");
3451 intel_dp->is_mst = true;
3452 } else {
3453 DRM_DEBUG_KMS("Sink is not MST capable\n");
3454 intel_dp->is_mst = false;
3455 }
3456 }
3457 intel_edp_panel_vdd_off(intel_dp, false);
3458
3459 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3460 return intel_dp->is_mst;
3461 }
3462
3463 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3464 {
3465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3466 struct drm_device *dev = intel_dig_port->base.base.dev;
3467 struct intel_crtc *intel_crtc =
3468 to_intel_crtc(intel_dig_port->base.base.crtc);
3469 u8 buf[1];
3470
3471 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3472 return -EAGAIN;
3473
3474 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3475 return -ENOTTY;
3476
3477 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3478 DP_TEST_SINK_START) < 0)
3479 return -EAGAIN;
3480
3481 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3482 intel_wait_for_vblank(dev, intel_crtc->pipe);
3483 intel_wait_for_vblank(dev, intel_crtc->pipe);
3484
3485 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3486 return -EAGAIN;
3487
3488 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3489 return 0;
3490 }
3491
3492 static bool
3493 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3494 {
3495 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3496 DP_DEVICE_SERVICE_IRQ_VECTOR,
3497 sink_irq_vector, 1) == 1;
3498 }
3499
3500 static bool
3501 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3502 {
3503 int ret;
3504
3505 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3506 DP_SINK_COUNT_ESI,
3507 sink_irq_vector, 14);
3508 if (ret != 14)
3509 return false;
3510
3511 return true;
3512 }
3513
3514 static void
3515 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3516 {
3517 /* NAK by default */
3518 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3519 }
3520
3521 static int
3522 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3523 {
3524 bool bret;
3525
3526 if (intel_dp->is_mst) {
3527 u8 esi[16] = { 0 };
3528 int ret = 0;
3529 int retry;
3530 bool handled;
3531 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3532 go_again:
3533 if (bret == true) {
3534
3535 /* check link status - esi[10] = 0x200c */
3536 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3537 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3538 intel_dp_start_link_train(intel_dp);
3539 intel_dp_complete_link_train(intel_dp);
3540 intel_dp_stop_link_train(intel_dp);
3541 }
3542
3543 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3544 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3545
3546 if (handled) {
3547 for (retry = 0; retry < 3; retry++) {
3548 int wret;
3549 wret = drm_dp_dpcd_write(&intel_dp->aux,
3550 DP_SINK_COUNT_ESI+1,
3551 &esi[1], 3);
3552 if (wret == 3) {
3553 break;
3554 }
3555 }
3556
3557 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3558 if (bret == true) {
3559 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3560 goto go_again;
3561 }
3562 } else
3563 ret = 0;
3564
3565 return ret;
3566 } else {
3567 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3568 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3569 intel_dp->is_mst = false;
3570 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3571 /* send a hotplug event */
3572 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3573 }
3574 }
3575 return -EINVAL;
3576 }
3577
3578 /*
3579 * According to DP spec
3580 * 5.1.2:
3581 * 1. Read DPCD
3582 * 2. Configure link according to Receiver Capabilities
3583 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3584 * 4. Check link status on receipt of hot-plug interrupt
3585 */
3586 void
3587 intel_dp_check_link_status(struct intel_dp *intel_dp)
3588 {
3589 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3590 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3591 u8 sink_irq_vector;
3592 u8 link_status[DP_LINK_STATUS_SIZE];
3593
3594 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3595
3596 if (!intel_encoder->connectors_active)
3597 return;
3598
3599 if (WARN_ON(!intel_encoder->base.crtc))
3600 return;
3601
3602 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3603 return;
3604
3605 /* Try to read receiver status if the link appears to be up */
3606 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3607 return;
3608 }
3609
3610 /* Now read the DPCD to see if it's actually running */
3611 if (!intel_dp_get_dpcd(intel_dp)) {
3612 return;
3613 }
3614
3615 /* Try to read the source of the interrupt */
3616 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3617 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3618 /* Clear interrupt source */
3619 drm_dp_dpcd_writeb(&intel_dp->aux,
3620 DP_DEVICE_SERVICE_IRQ_VECTOR,
3621 sink_irq_vector);
3622
3623 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3624 intel_dp_handle_test_request(intel_dp);
3625 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3626 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3627 }
3628
3629 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3630 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3631 intel_encoder->base.name);
3632 intel_dp_start_link_train(intel_dp);
3633 intel_dp_complete_link_train(intel_dp);
3634 intel_dp_stop_link_train(intel_dp);
3635 }
3636 }
3637
3638 /* XXX this is probably wrong for multiple downstream ports */
3639 static enum drm_connector_status
3640 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3641 {
3642 uint8_t *dpcd = intel_dp->dpcd;
3643 uint8_t type;
3644
3645 if (!intel_dp_get_dpcd(intel_dp))
3646 return connector_status_disconnected;
3647
3648 /* if there's no downstream port, we're done */
3649 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3650 return connector_status_connected;
3651
3652 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3653 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3654 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3655 uint8_t reg;
3656
3657 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3658 &reg, 1) < 0)
3659 return connector_status_unknown;
3660
3661 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3662 : connector_status_disconnected;
3663 }
3664
3665 /* If no HPD, poke DDC gently */
3666 if (drm_probe_ddc(&intel_dp->aux.ddc))
3667 return connector_status_connected;
3668
3669 /* Well we tried, say unknown for unreliable port types */
3670 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3671 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3672 if (type == DP_DS_PORT_TYPE_VGA ||
3673 type == DP_DS_PORT_TYPE_NON_EDID)
3674 return connector_status_unknown;
3675 } else {
3676 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3677 DP_DWN_STRM_PORT_TYPE_MASK;
3678 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3679 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3680 return connector_status_unknown;
3681 }
3682
3683 /* Anything else is out of spec, warn and ignore */
3684 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3685 return connector_status_disconnected;
3686 }
3687
3688 static enum drm_connector_status
3689 ironlake_dp_detect(struct intel_dp *intel_dp)
3690 {
3691 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3694 enum drm_connector_status status;
3695
3696 /* Can't disconnect eDP, but you can close the lid... */
3697 if (is_edp(intel_dp)) {
3698 status = intel_panel_detect(dev);
3699 if (status == connector_status_unknown)
3700 status = connector_status_connected;
3701 return status;
3702 }
3703
3704 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3705 return connector_status_disconnected;
3706
3707 return intel_dp_detect_dpcd(intel_dp);
3708 }
3709
3710 static enum drm_connector_status
3711 g4x_dp_detect(struct intel_dp *intel_dp)
3712 {
3713 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3716 uint32_t bit;
3717
3718 /* Can't disconnect eDP, but you can close the lid... */
3719 if (is_edp(intel_dp)) {
3720 enum drm_connector_status status;
3721
3722 status = intel_panel_detect(dev);
3723 if (status == connector_status_unknown)
3724 status = connector_status_connected;
3725 return status;
3726 }
3727
3728 if (IS_VALLEYVIEW(dev)) {
3729 switch (intel_dig_port->port) {
3730 case PORT_B:
3731 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3732 break;
3733 case PORT_C:
3734 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3735 break;
3736 case PORT_D:
3737 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3738 break;
3739 default:
3740 return connector_status_unknown;
3741 }
3742 } else {
3743 switch (intel_dig_port->port) {
3744 case PORT_B:
3745 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3746 break;
3747 case PORT_C:
3748 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3749 break;
3750 case PORT_D:
3751 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3752 break;
3753 default:
3754 return connector_status_unknown;
3755 }
3756 }
3757
3758 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3759 return connector_status_disconnected;
3760
3761 return intel_dp_detect_dpcd(intel_dp);
3762 }
3763
3764 static struct edid *
3765 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3766 {
3767 struct intel_connector *intel_connector = to_intel_connector(connector);
3768
3769 /* use cached edid if we have one */
3770 if (intel_connector->edid) {
3771 /* invalid edid */
3772 if (IS_ERR(intel_connector->edid))
3773 return NULL;
3774
3775 return drm_edid_duplicate(intel_connector->edid);
3776 }
3777
3778 return drm_get_edid(connector, adapter);
3779 }
3780
3781 static int
3782 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3783 {
3784 struct intel_connector *intel_connector = to_intel_connector(connector);
3785
3786 /* use cached edid if we have one */
3787 if (intel_connector->edid) {
3788 /* invalid edid */
3789 if (IS_ERR(intel_connector->edid))
3790 return 0;
3791
3792 return intel_connector_update_modes(connector,
3793 intel_connector->edid);
3794 }
3795
3796 return intel_ddc_get_modes(connector, adapter);
3797 }
3798
3799 static enum drm_connector_status
3800 intel_dp_detect(struct drm_connector *connector, bool force)
3801 {
3802 struct intel_dp *intel_dp = intel_attached_dp(connector);
3803 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3804 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3805 struct drm_device *dev = connector->dev;
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3807 enum drm_connector_status status;
3808 enum intel_display_power_domain power_domain;
3809 struct edid *edid = NULL;
3810 bool ret;
3811
3812 power_domain = intel_display_port_power_domain(intel_encoder);
3813 intel_display_power_get(dev_priv, power_domain);
3814
3815 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3816 connector->base.id, connector->name);
3817
3818 if (intel_dp->is_mst) {
3819 /* MST devices are disconnected from a monitor POV */
3820 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3821 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3822 status = connector_status_disconnected;
3823 goto out;
3824 }
3825
3826 intel_dp->has_audio = false;
3827
3828 if (HAS_PCH_SPLIT(dev))
3829 status = ironlake_dp_detect(intel_dp);
3830 else
3831 status = g4x_dp_detect(intel_dp);
3832
3833 if (status != connector_status_connected)
3834 goto out;
3835
3836 intel_dp_probe_oui(intel_dp);
3837
3838 ret = intel_dp_probe_mst(intel_dp);
3839 if (ret) {
3840 /* if we are in MST mode then this connector
3841 won't appear connected or have anything with EDID on it */
3842 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3843 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3844 status = connector_status_disconnected;
3845 goto out;
3846 }
3847
3848 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3849 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3850 } else {
3851 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3852 if (edid) {
3853 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3854 kfree(edid);
3855 }
3856 }
3857
3858 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3859 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3860 status = connector_status_connected;
3861
3862 out:
3863 intel_display_power_put(dev_priv, power_domain);
3864 return status;
3865 }
3866
3867 static int intel_dp_get_modes(struct drm_connector *connector)
3868 {
3869 struct intel_dp *intel_dp = intel_attached_dp(connector);
3870 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3871 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3872 struct intel_connector *intel_connector = to_intel_connector(connector);
3873 struct drm_device *dev = connector->dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875 enum intel_display_power_domain power_domain;
3876 int ret;
3877
3878 /* We should parse the EDID data and find out if it has an audio sink
3879 */
3880
3881 power_domain = intel_display_port_power_domain(intel_encoder);
3882 intel_display_power_get(dev_priv, power_domain);
3883
3884 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3885 intel_display_power_put(dev_priv, power_domain);
3886 if (ret)
3887 return ret;
3888
3889 /* if eDP has no EDID, fall back to fixed mode */
3890 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3891 struct drm_display_mode *mode;
3892 mode = drm_mode_duplicate(dev,
3893 intel_connector->panel.fixed_mode);
3894 if (mode) {
3895 drm_mode_probed_add(connector, mode);
3896 return 1;
3897 }
3898 }
3899 return 0;
3900 }
3901
3902 static bool
3903 intel_dp_detect_audio(struct drm_connector *connector)
3904 {
3905 struct intel_dp *intel_dp = intel_attached_dp(connector);
3906 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3907 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3908 struct drm_device *dev = connector->dev;
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 enum intel_display_power_domain power_domain;
3911 struct edid *edid;
3912 bool has_audio = false;
3913
3914 power_domain = intel_display_port_power_domain(intel_encoder);
3915 intel_display_power_get(dev_priv, power_domain);
3916
3917 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3918 if (edid) {
3919 has_audio = drm_detect_monitor_audio(edid);
3920 kfree(edid);
3921 }
3922
3923 intel_display_power_put(dev_priv, power_domain);
3924
3925 return has_audio;
3926 }
3927
3928 static int
3929 intel_dp_set_property(struct drm_connector *connector,
3930 struct drm_property *property,
3931 uint64_t val)
3932 {
3933 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3934 struct intel_connector *intel_connector = to_intel_connector(connector);
3935 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3936 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3937 int ret;
3938
3939 ret = drm_object_property_set_value(&connector->base, property, val);
3940 if (ret)
3941 return ret;
3942
3943 if (property == dev_priv->force_audio_property) {
3944 int i = val;
3945 bool has_audio;
3946
3947 if (i == intel_dp->force_audio)
3948 return 0;
3949
3950 intel_dp->force_audio = i;
3951
3952 if (i == HDMI_AUDIO_AUTO)
3953 has_audio = intel_dp_detect_audio(connector);
3954 else
3955 has_audio = (i == HDMI_AUDIO_ON);
3956
3957 if (has_audio == intel_dp->has_audio)
3958 return 0;
3959
3960 intel_dp->has_audio = has_audio;
3961 goto done;
3962 }
3963
3964 if (property == dev_priv->broadcast_rgb_property) {
3965 bool old_auto = intel_dp->color_range_auto;
3966 uint32_t old_range = intel_dp->color_range;
3967
3968 switch (val) {
3969 case INTEL_BROADCAST_RGB_AUTO:
3970 intel_dp->color_range_auto = true;
3971 break;
3972 case INTEL_BROADCAST_RGB_FULL:
3973 intel_dp->color_range_auto = false;
3974 intel_dp->color_range = 0;
3975 break;
3976 case INTEL_BROADCAST_RGB_LIMITED:
3977 intel_dp->color_range_auto = false;
3978 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3979 break;
3980 default:
3981 return -EINVAL;
3982 }
3983
3984 if (old_auto == intel_dp->color_range_auto &&
3985 old_range == intel_dp->color_range)
3986 return 0;
3987
3988 goto done;
3989 }
3990
3991 if (is_edp(intel_dp) &&
3992 property == connector->dev->mode_config.scaling_mode_property) {
3993 if (val == DRM_MODE_SCALE_NONE) {
3994 DRM_DEBUG_KMS("no scaling not supported\n");
3995 return -EINVAL;
3996 }
3997
3998 if (intel_connector->panel.fitting_mode == val) {
3999 /* the eDP scaling property is not changed */
4000 return 0;
4001 }
4002 intel_connector->panel.fitting_mode = val;
4003
4004 goto done;
4005 }
4006
4007 return -EINVAL;
4008
4009 done:
4010 if (intel_encoder->base.crtc)
4011 intel_crtc_restore_mode(intel_encoder->base.crtc);
4012
4013 return 0;
4014 }
4015
4016 static void
4017 intel_dp_connector_destroy(struct drm_connector *connector)
4018 {
4019 struct intel_connector *intel_connector = to_intel_connector(connector);
4020
4021 if (!IS_ERR_OR_NULL(intel_connector->edid))
4022 kfree(intel_connector->edid);
4023
4024 /* Can't call is_edp() since the encoder may have been destroyed
4025 * already. */
4026 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4027 intel_panel_fini(&intel_connector->panel);
4028
4029 drm_connector_cleanup(connector);
4030 kfree(connector);
4031 }
4032
4033 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4034 {
4035 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4036 struct intel_dp *intel_dp = &intel_dig_port->dp;
4037 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4038
4039 drm_dp_aux_unregister(&intel_dp->aux);
4040 intel_dp_mst_encoder_cleanup(intel_dig_port);
4041 drm_encoder_cleanup(encoder);
4042 if (is_edp(intel_dp)) {
4043 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4044 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4045 edp_panel_vdd_off_sync(intel_dp);
4046 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4047 if (intel_dp->edp_notifier.notifier_call) {
4048 unregister_reboot_notifier(&intel_dp->edp_notifier);
4049 intel_dp->edp_notifier.notifier_call = NULL;
4050 }
4051 }
4052 kfree(intel_dig_port);
4053 }
4054
4055 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4056 {
4057 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4058
4059 if (!is_edp(intel_dp))
4060 return;
4061
4062 edp_panel_vdd_off_sync(intel_dp);
4063 }
4064
4065 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4066 {
4067 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4068 }
4069
4070 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4071 .dpms = intel_connector_dpms,
4072 .detect = intel_dp_detect,
4073 .fill_modes = drm_helper_probe_single_connector_modes,
4074 .set_property = intel_dp_set_property,
4075 .destroy = intel_dp_connector_destroy,
4076 };
4077
4078 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4079 .get_modes = intel_dp_get_modes,
4080 .mode_valid = intel_dp_mode_valid,
4081 .best_encoder = intel_best_encoder,
4082 };
4083
4084 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4085 .reset = intel_dp_encoder_reset,
4086 .destroy = intel_dp_encoder_destroy,
4087 };
4088
4089 void
4090 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4091 {
4092 return;
4093 }
4094
4095 bool
4096 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4097 {
4098 struct intel_dp *intel_dp = &intel_dig_port->dp;
4099 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4100 struct drm_device *dev = intel_dig_port->base.base.dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 enum intel_display_power_domain power_domain;
4103 bool ret = true;
4104
4105 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4106 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4107
4108 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4109 port_name(intel_dig_port->port),
4110 long_hpd ? "long" : "short");
4111
4112 power_domain = intel_display_port_power_domain(intel_encoder);
4113 intel_display_power_get(dev_priv, power_domain);
4114
4115 if (long_hpd) {
4116 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4117 goto mst_fail;
4118
4119 if (!intel_dp_get_dpcd(intel_dp)) {
4120 goto mst_fail;
4121 }
4122
4123 intel_dp_probe_oui(intel_dp);
4124
4125 if (!intel_dp_probe_mst(intel_dp))
4126 goto mst_fail;
4127
4128 } else {
4129 if (intel_dp->is_mst) {
4130 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4131 goto mst_fail;
4132 }
4133
4134 if (!intel_dp->is_mst) {
4135 /*
4136 * we'll check the link status via the normal hot plug path later -
4137 * but for short hpds we should check it now
4138 */
4139 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4140 intel_dp_check_link_status(intel_dp);
4141 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4142 }
4143 }
4144 ret = false;
4145 goto put_power;
4146 mst_fail:
4147 /* if we were in MST mode, and device is not there get out of MST mode */
4148 if (intel_dp->is_mst) {
4149 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4150 intel_dp->is_mst = false;
4151 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4152 }
4153 put_power:
4154 intel_display_power_put(dev_priv, power_domain);
4155
4156 return ret;
4157 }
4158
4159 /* Return which DP Port should be selected for Transcoder DP control */
4160 int
4161 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4162 {
4163 struct drm_device *dev = crtc->dev;
4164 struct intel_encoder *intel_encoder;
4165 struct intel_dp *intel_dp;
4166
4167 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4168 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4169
4170 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4171 intel_encoder->type == INTEL_OUTPUT_EDP)
4172 return intel_dp->output_reg;
4173 }
4174
4175 return -1;
4176 }
4177
4178 /* check the VBT to see whether the eDP is on DP-D port */
4179 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4180 {
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 union child_device_config *p_child;
4183 int i;
4184 static const short port_mapping[] = {
4185 [PORT_B] = PORT_IDPB,
4186 [PORT_C] = PORT_IDPC,
4187 [PORT_D] = PORT_IDPD,
4188 };
4189
4190 if (port == PORT_A)
4191 return true;
4192
4193 if (!dev_priv->vbt.child_dev_num)
4194 return false;
4195
4196 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4197 p_child = dev_priv->vbt.child_dev + i;
4198
4199 if (p_child->common.dvo_port == port_mapping[port] &&
4200 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4201 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4202 return true;
4203 }
4204 return false;
4205 }
4206
4207 void
4208 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4209 {
4210 struct intel_connector *intel_connector = to_intel_connector(connector);
4211
4212 intel_attach_force_audio_property(connector);
4213 intel_attach_broadcast_rgb_property(connector);
4214 intel_dp->color_range_auto = true;
4215
4216 if (is_edp(intel_dp)) {
4217 drm_mode_create_scaling_mode_property(connector->dev);
4218 drm_object_attach_property(
4219 &connector->base,
4220 connector->dev->mode_config.scaling_mode_property,
4221 DRM_MODE_SCALE_ASPECT);
4222 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4223 }
4224 }
4225
4226 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4227 {
4228 intel_dp->last_power_cycle = jiffies;
4229 intel_dp->last_power_on = jiffies;
4230 intel_dp->last_backlight_off = jiffies;
4231 }
4232
4233 static void
4234 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4235 struct intel_dp *intel_dp,
4236 struct edp_power_seq *out)
4237 {
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 struct edp_power_seq cur, vbt, spec, final;
4240 u32 pp_on, pp_off, pp_div, pp;
4241 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4242
4243 if (HAS_PCH_SPLIT(dev)) {
4244 pp_ctrl_reg = PCH_PP_CONTROL;
4245 pp_on_reg = PCH_PP_ON_DELAYS;
4246 pp_off_reg = PCH_PP_OFF_DELAYS;
4247 pp_div_reg = PCH_PP_DIVISOR;
4248 } else {
4249 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4250
4251 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4252 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4253 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4254 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4255 }
4256
4257 /* Workaround: Need to write PP_CONTROL with the unlock key as
4258 * the very first thing. */
4259 pp = ironlake_get_pp_control(intel_dp);
4260 I915_WRITE(pp_ctrl_reg, pp);
4261
4262 pp_on = I915_READ(pp_on_reg);
4263 pp_off = I915_READ(pp_off_reg);
4264 pp_div = I915_READ(pp_div_reg);
4265
4266 /* Pull timing values out of registers */
4267 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4268 PANEL_POWER_UP_DELAY_SHIFT;
4269
4270 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4271 PANEL_LIGHT_ON_DELAY_SHIFT;
4272
4273 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4274 PANEL_LIGHT_OFF_DELAY_SHIFT;
4275
4276 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4277 PANEL_POWER_DOWN_DELAY_SHIFT;
4278
4279 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4280 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4281
4282 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4283 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4284
4285 vbt = dev_priv->vbt.edp_pps;
4286
4287 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4288 * our hw here, which are all in 100usec. */
4289 spec.t1_t3 = 210 * 10;
4290 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4291 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4292 spec.t10 = 500 * 10;
4293 /* This one is special and actually in units of 100ms, but zero
4294 * based in the hw (so we need to add 100 ms). But the sw vbt
4295 * table multiplies it with 1000 to make it in units of 100usec,
4296 * too. */
4297 spec.t11_t12 = (510 + 100) * 10;
4298
4299 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4300 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4301
4302 /* Use the max of the register settings and vbt. If both are
4303 * unset, fall back to the spec limits. */
4304 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4305 spec.field : \
4306 max(cur.field, vbt.field))
4307 assign_final(t1_t3);
4308 assign_final(t8);
4309 assign_final(t9);
4310 assign_final(t10);
4311 assign_final(t11_t12);
4312 #undef assign_final
4313
4314 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4315 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4316 intel_dp->backlight_on_delay = get_delay(t8);
4317 intel_dp->backlight_off_delay = get_delay(t9);
4318 intel_dp->panel_power_down_delay = get_delay(t10);
4319 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4320 #undef get_delay
4321
4322 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4323 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4324 intel_dp->panel_power_cycle_delay);
4325
4326 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4327 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4328
4329 if (out)
4330 *out = final;
4331 }
4332
4333 static void
4334 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4335 struct intel_dp *intel_dp,
4336 struct edp_power_seq *seq)
4337 {
4338 struct drm_i915_private *dev_priv = dev->dev_private;
4339 u32 pp_on, pp_off, pp_div, port_sel = 0;
4340 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4341 int pp_on_reg, pp_off_reg, pp_div_reg;
4342 enum port port = dp_to_dig_port(intel_dp)->port;
4343
4344 if (HAS_PCH_SPLIT(dev)) {
4345 pp_on_reg = PCH_PP_ON_DELAYS;
4346 pp_off_reg = PCH_PP_OFF_DELAYS;
4347 pp_div_reg = PCH_PP_DIVISOR;
4348 } else {
4349 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4350
4351 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4352 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4353 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4354 }
4355
4356 /*
4357 * And finally store the new values in the power sequencer. The
4358 * backlight delays are set to 1 because we do manual waits on them. For
4359 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4360 * we'll end up waiting for the backlight off delay twice: once when we
4361 * do the manual sleep, and once when we disable the panel and wait for
4362 * the PP_STATUS bit to become zero.
4363 */
4364 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4365 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4366 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4367 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4368 /* Compute the divisor for the pp clock, simply match the Bspec
4369 * formula. */
4370 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4371 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4372 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4373
4374 /* Haswell doesn't have any port selection bits for the panel
4375 * power sequencer any more. */
4376 if (IS_VALLEYVIEW(dev)) {
4377 port_sel = PANEL_PORT_SELECT_VLV(port);
4378 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4379 if (port == PORT_A)
4380 port_sel = PANEL_PORT_SELECT_DPA;
4381 else
4382 port_sel = PANEL_PORT_SELECT_DPD;
4383 }
4384
4385 pp_on |= port_sel;
4386
4387 I915_WRITE(pp_on_reg, pp_on);
4388 I915_WRITE(pp_off_reg, pp_off);
4389 I915_WRITE(pp_div_reg, pp_div);
4390
4391 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4392 I915_READ(pp_on_reg),
4393 I915_READ(pp_off_reg),
4394 I915_READ(pp_div_reg));
4395 }
4396
4397 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4398 {
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400 struct intel_encoder *encoder;
4401 struct intel_dp *intel_dp = NULL;
4402 struct intel_crtc_config *config = NULL;
4403 struct intel_crtc *intel_crtc = NULL;
4404 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4405 u32 reg, val;
4406 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4407
4408 if (refresh_rate <= 0) {
4409 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4410 return;
4411 }
4412
4413 if (intel_connector == NULL) {
4414 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4415 return;
4416 }
4417
4418 /*
4419 * FIXME: This needs proper synchronization with psr state. But really
4420 * hard to tell without seeing the user of this function of this code.
4421 * Check locking and ordering once that lands.
4422 */
4423 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4424 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4425 return;
4426 }
4427
4428 encoder = intel_attached_encoder(&intel_connector->base);
4429 intel_dp = enc_to_intel_dp(&encoder->base);
4430 intel_crtc = encoder->new_crtc;
4431
4432 if (!intel_crtc) {
4433 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4434 return;
4435 }
4436
4437 config = &intel_crtc->config;
4438
4439 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4440 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4441 return;
4442 }
4443
4444 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4445 index = DRRS_LOW_RR;
4446
4447 if (index == intel_dp->drrs_state.refresh_rate_type) {
4448 DRM_DEBUG_KMS(
4449 "DRRS requested for previously set RR...ignoring\n");
4450 return;
4451 }
4452
4453 if (!intel_crtc->active) {
4454 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4455 return;
4456 }
4457
4458 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4459 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4460 val = I915_READ(reg);
4461 if (index > DRRS_HIGH_RR) {
4462 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4463 intel_dp_set_m_n(intel_crtc);
4464 } else {
4465 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4466 }
4467 I915_WRITE(reg, val);
4468 }
4469
4470 /*
4471 * mutex taken to ensure that there is no race between differnt
4472 * drrs calls trying to update refresh rate. This scenario may occur
4473 * in future when idleness detection based DRRS in kernel and
4474 * possible calls from user space to set differnt RR are made.
4475 */
4476
4477 mutex_lock(&intel_dp->drrs_state.mutex);
4478
4479 intel_dp->drrs_state.refresh_rate_type = index;
4480
4481 mutex_unlock(&intel_dp->drrs_state.mutex);
4482
4483 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4484 }
4485
4486 static struct drm_display_mode *
4487 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4488 struct intel_connector *intel_connector,
4489 struct drm_display_mode *fixed_mode)
4490 {
4491 struct drm_connector *connector = &intel_connector->base;
4492 struct intel_dp *intel_dp = &intel_dig_port->dp;
4493 struct drm_device *dev = intel_dig_port->base.base.dev;
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 struct drm_display_mode *downclock_mode = NULL;
4496
4497 if (INTEL_INFO(dev)->gen <= 6) {
4498 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4499 return NULL;
4500 }
4501
4502 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4503 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4504 return NULL;
4505 }
4506
4507 downclock_mode = intel_find_panel_downclock
4508 (dev, fixed_mode, connector);
4509
4510 if (!downclock_mode) {
4511 DRM_DEBUG_KMS("DRRS not supported\n");
4512 return NULL;
4513 }
4514
4515 dev_priv->drrs.connector = intel_connector;
4516
4517 mutex_init(&intel_dp->drrs_state.mutex);
4518
4519 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4520
4521 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4522 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4523 return downclock_mode;
4524 }
4525
4526 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4527 {
4528 struct drm_device *dev = intel_encoder->base.dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct intel_dp *intel_dp;
4531 enum intel_display_power_domain power_domain;
4532
4533 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4534 return;
4535
4536 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4537 if (!edp_have_panel_vdd(intel_dp))
4538 return;
4539 /*
4540 * The VDD bit needs a power domain reference, so if the bit is
4541 * already enabled when we boot or resume, grab this reference and
4542 * schedule a vdd off, so we don't hold on to the reference
4543 * indefinitely.
4544 */
4545 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4546 power_domain = intel_display_port_power_domain(intel_encoder);
4547 intel_display_power_get(dev_priv, power_domain);
4548
4549 edp_panel_vdd_schedule_off(intel_dp);
4550 }
4551
4552 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4553 struct intel_connector *intel_connector,
4554 struct edp_power_seq *power_seq)
4555 {
4556 struct drm_connector *connector = &intel_connector->base;
4557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4558 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4559 struct drm_device *dev = intel_encoder->base.dev;
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561 struct drm_display_mode *fixed_mode = NULL;
4562 struct drm_display_mode *downclock_mode = NULL;
4563 bool has_dpcd;
4564 struct drm_display_mode *scan;
4565 struct edid *edid;
4566
4567 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4568
4569 if (!is_edp(intel_dp))
4570 return true;
4571
4572 intel_edp_panel_vdd_sanitize(intel_encoder);
4573
4574 /* Cache DPCD and EDID for edp. */
4575 intel_edp_panel_vdd_on(intel_dp);
4576 has_dpcd = intel_dp_get_dpcd(intel_dp);
4577 intel_edp_panel_vdd_off(intel_dp, false);
4578
4579 if (has_dpcd) {
4580 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4581 dev_priv->no_aux_handshake =
4582 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4583 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4584 } else {
4585 /* if this fails, presume the device is a ghost */
4586 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4587 return false;
4588 }
4589
4590 /* We now know it's not a ghost, init power sequence regs. */
4591 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4592
4593 mutex_lock(&dev->mode_config.mutex);
4594 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4595 if (edid) {
4596 if (drm_add_edid_modes(connector, edid)) {
4597 drm_mode_connector_update_edid_property(connector,
4598 edid);
4599 drm_edid_to_eld(connector, edid);
4600 } else {
4601 kfree(edid);
4602 edid = ERR_PTR(-EINVAL);
4603 }
4604 } else {
4605 edid = ERR_PTR(-ENOENT);
4606 }
4607 intel_connector->edid = edid;
4608
4609 /* prefer fixed mode from EDID if available */
4610 list_for_each_entry(scan, &connector->probed_modes, head) {
4611 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4612 fixed_mode = drm_mode_duplicate(dev, scan);
4613 downclock_mode = intel_dp_drrs_init(
4614 intel_dig_port,
4615 intel_connector, fixed_mode);
4616 break;
4617 }
4618 }
4619
4620 /* fallback to VBT if available for eDP */
4621 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4622 fixed_mode = drm_mode_duplicate(dev,
4623 dev_priv->vbt.lfp_lvds_vbt_mode);
4624 if (fixed_mode)
4625 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4626 }
4627 mutex_unlock(&dev->mode_config.mutex);
4628
4629 if (IS_VALLEYVIEW(dev)) {
4630 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4631 register_reboot_notifier(&intel_dp->edp_notifier);
4632 }
4633
4634 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4635 intel_connector->panel.backlight_power = intel_edp_backlight_power;
4636 intel_panel_setup_backlight(connector);
4637
4638 return true;
4639 }
4640
4641 bool
4642 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4643 struct intel_connector *intel_connector)
4644 {
4645 struct drm_connector *connector = &intel_connector->base;
4646 struct intel_dp *intel_dp = &intel_dig_port->dp;
4647 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4648 struct drm_device *dev = intel_encoder->base.dev;
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 enum port port = intel_dig_port->port;
4651 struct edp_power_seq power_seq = { 0 };
4652 int type;
4653
4654 /* intel_dp vfuncs */
4655 if (IS_VALLEYVIEW(dev))
4656 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4657 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4658 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4659 else if (HAS_PCH_SPLIT(dev))
4660 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4661 else
4662 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4663
4664 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4665
4666 /* Preserve the current hw state. */
4667 intel_dp->DP = I915_READ(intel_dp->output_reg);
4668 intel_dp->attached_connector = intel_connector;
4669
4670 if (intel_dp_is_edp(dev, port))
4671 type = DRM_MODE_CONNECTOR_eDP;
4672 else
4673 type = DRM_MODE_CONNECTOR_DisplayPort;
4674
4675 /*
4676 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4677 * for DP the encoder type can be set by the caller to
4678 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4679 */
4680 if (type == DRM_MODE_CONNECTOR_eDP)
4681 intel_encoder->type = INTEL_OUTPUT_EDP;
4682
4683 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4684 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4685 port_name(port));
4686
4687 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4688 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4689
4690 connector->interlace_allowed = true;
4691 connector->doublescan_allowed = 0;
4692
4693 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4694 edp_panel_vdd_work);
4695
4696 intel_connector_attach_encoder(intel_connector, intel_encoder);
4697 drm_connector_register(connector);
4698
4699 if (HAS_DDI(dev))
4700 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4701 else
4702 intel_connector->get_hw_state = intel_connector_get_hw_state;
4703 intel_connector->unregister = intel_dp_connector_unregister;
4704
4705 /* Set up the hotplug pin. */
4706 switch (port) {
4707 case PORT_A:
4708 intel_encoder->hpd_pin = HPD_PORT_A;
4709 break;
4710 case PORT_B:
4711 intel_encoder->hpd_pin = HPD_PORT_B;
4712 break;
4713 case PORT_C:
4714 intel_encoder->hpd_pin = HPD_PORT_C;
4715 break;
4716 case PORT_D:
4717 intel_encoder->hpd_pin = HPD_PORT_D;
4718 break;
4719 default:
4720 BUG();
4721 }
4722
4723 if (is_edp(intel_dp)) {
4724 intel_dp_init_panel_power_timestamps(intel_dp);
4725 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4726 }
4727
4728 intel_dp_aux_init(intel_dp, intel_connector);
4729
4730 /* init MST on ports that can support it */
4731 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4732 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4733 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4734 }
4735 }
4736
4737 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4738 drm_dp_aux_unregister(&intel_dp->aux);
4739 if (is_edp(intel_dp)) {
4740 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4741 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4742 edp_panel_vdd_off_sync(intel_dp);
4743 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4744 }
4745 drm_connector_unregister(connector);
4746 drm_connector_cleanup(connector);
4747 return false;
4748 }
4749
4750 intel_dp_add_properties(intel_dp, connector);
4751
4752 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4753 * 0xd. Failure to do so will result in spurious interrupts being
4754 * generated on the port when a cable is not attached.
4755 */
4756 if (IS_G4X(dev) && !IS_GM45(dev)) {
4757 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4758 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4759 }
4760
4761 return true;
4762 }
4763
4764 void
4765 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4766 {
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 struct intel_digital_port *intel_dig_port;
4769 struct intel_encoder *intel_encoder;
4770 struct drm_encoder *encoder;
4771 struct intel_connector *intel_connector;
4772
4773 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4774 if (!intel_dig_port)
4775 return;
4776
4777 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4778 if (!intel_connector) {
4779 kfree(intel_dig_port);
4780 return;
4781 }
4782
4783 intel_encoder = &intel_dig_port->base;
4784 encoder = &intel_encoder->base;
4785
4786 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4787 DRM_MODE_ENCODER_TMDS);
4788
4789 intel_encoder->compute_config = intel_dp_compute_config;
4790 intel_encoder->disable = intel_disable_dp;
4791 intel_encoder->get_hw_state = intel_dp_get_hw_state;
4792 intel_encoder->get_config = intel_dp_get_config;
4793 intel_encoder->suspend = intel_dp_encoder_suspend;
4794 if (IS_CHERRYVIEW(dev)) {
4795 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4796 intel_encoder->pre_enable = chv_pre_enable_dp;
4797 intel_encoder->enable = vlv_enable_dp;
4798 intel_encoder->post_disable = chv_post_disable_dp;
4799 } else if (IS_VALLEYVIEW(dev)) {
4800 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4801 intel_encoder->pre_enable = vlv_pre_enable_dp;
4802 intel_encoder->enable = vlv_enable_dp;
4803 intel_encoder->post_disable = vlv_post_disable_dp;
4804 } else {
4805 intel_encoder->pre_enable = g4x_pre_enable_dp;
4806 intel_encoder->enable = g4x_enable_dp;
4807 intel_encoder->post_disable = g4x_post_disable_dp;
4808 }
4809
4810 intel_dig_port->port = port;
4811 intel_dig_port->dp.output_reg = output_reg;
4812
4813 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4814 if (IS_CHERRYVIEW(dev)) {
4815 if (port == PORT_D)
4816 intel_encoder->crtc_mask = 1 << 2;
4817 else
4818 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4819 } else {
4820 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4821 }
4822 intel_encoder->cloneable = 0;
4823 intel_encoder->hot_plug = intel_dp_hot_plug;
4824
4825 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4826 dev_priv->hpd_irq_port[port] = intel_dig_port;
4827
4828 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4829 drm_encoder_cleanup(encoder);
4830 kfree(intel_dig_port);
4831 kfree(intel_connector);
4832 }
4833 }
4834
4835 void intel_dp_mst_suspend(struct drm_device *dev)
4836 {
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 int i;
4839
4840 /* disable MST */
4841 for (i = 0; i < I915_MAX_PORTS; i++) {
4842 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4843 if (!intel_dig_port)
4844 continue;
4845
4846 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4847 if (!intel_dig_port->dp.can_mst)
4848 continue;
4849 if (intel_dig_port->dp.is_mst)
4850 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4851 }
4852 }
4853 }
4854
4855 void intel_dp_mst_resume(struct drm_device *dev)
4856 {
4857 struct drm_i915_private *dev_priv = dev->dev_private;
4858 int i;
4859
4860 for (i = 0; i < I915_MAX_PORTS; i++) {
4861 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4862 if (!intel_dig_port)
4863 continue;
4864 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4865 int ret;
4866
4867 if (!intel_dig_port->dp.can_mst)
4868 continue;
4869
4870 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4871 if (ret != 0) {
4872 intel_dp_check_mst_status(&intel_dig_port->dp);
4873 }
4874 }
4875 }
4876 }
Linux kernel - Deliverables
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