2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
294 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
298 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 enum port port
= intel_dig_port
->port
;
303 /* modeset should have pipe */
305 return to_intel_crtc(crtc
)->pipe
;
307 /* init time, try to find a pipe with this port selected */
308 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
309 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
310 PANEL_PORT_SELECT_MASK
;
311 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
313 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
321 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
323 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
325 if (HAS_PCH_SPLIT(dev
))
326 return PCH_PP_CONTROL
;
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
331 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
333 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
335 if (HAS_PCH_SPLIT(dev
))
336 return PCH_PP_STATUS
;
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
341 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
346 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
348 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 u32 pp_ctrl_reg
, pp_div_reg
;
352 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
354 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
357 if (IS_VALLEYVIEW(dev
)) {
358 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
359 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
360 pp_div
= I915_READ(pp_div_reg
);
361 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
365 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
366 msleep(intel_dp
->panel_power_cycle_delay
);
372 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
374 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
380 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
382 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
384 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
385 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
386 enum intel_display_power_domain power_domain
;
388 power_domain
= intel_display_port_power_domain(intel_encoder
);
389 return intel_display_power_enabled(dev_priv
, power_domain
) &&
390 (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
394 intel_dp_check_edp(struct intel_dp
*intel_dp
)
396 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
399 if (!is_edp(intel_dp
))
402 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
405 I915_READ(_pp_stat_reg(intel_dp
)),
406 I915_READ(_pp_ctrl_reg(intel_dp
)));
411 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
413 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
414 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
420 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
422 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
423 msecs_to_jiffies_timeout(10));
425 done
= wait_for_atomic(C
, 10) == 0;
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
434 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
436 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
437 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
443 return index
? 0 : intel_hrawclk(dev
) / 2;
446 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
448 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
449 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
454 if (intel_dig_port
->port
== PORT_A
) {
455 if (IS_GEN6(dev
) || IS_GEN7(dev
))
456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
458 return 225; /* eDP input clock at 450Mhz */
460 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
464 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
466 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
467 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
470 if (intel_dig_port
->port
== PORT_A
) {
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
474 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
475 /* Workaround for non-ULT HSW */
482 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
486 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
488 return index
? 0 : 100;
491 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
494 uint32_t aux_clock_divider
)
496 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
497 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
498 uint32_t precharge
, timeout
;
505 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
506 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
508 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
510 return DP_AUX_CH_CTL_SEND_BUSY
|
512 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
513 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
515 DP_AUX_CH_CTL_RECEIVE_ERROR
|
516 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
517 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
518 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
522 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
523 uint8_t *send
, int send_bytes
,
524 uint8_t *recv
, int recv_size
)
526 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
527 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
529 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
530 uint32_t ch_data
= ch_ctl
+ 4;
531 uint32_t aux_clock_divider
;
532 int i
, ret
, recv_bytes
;
535 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
538 vdd
= _edp_panel_vdd_on(intel_dp
);
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
544 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
546 intel_dp_check_edp(intel_dp
);
548 intel_aux_display_runtime_get(dev_priv
);
550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
552 status
= I915_READ_NOTRACE(ch_ctl
);
553 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
571 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
572 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i
= 0; i
< send_bytes
; i
+= 4)
581 I915_WRITE(ch_data
+ i
,
582 pack_aux(send
+ i
, send_bytes
- i
));
584 /* Send the command and wait for it to complete */
585 I915_WRITE(ch_ctl
, send_ctl
);
587 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
589 /* Clear done status and any errors */
593 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
594 DP_AUX_CH_CTL_RECEIVE_ERROR
);
596 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
597 DP_AUX_CH_CTL_RECEIVE_ERROR
))
599 if (status
& DP_AUX_CH_CTL_DONE
)
602 if (status
& DP_AUX_CH_CTL_DONE
)
606 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
615 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
623 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
629 /* Unload any bytes sent back from the other side */
630 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
632 if (recv_bytes
> recv_size
)
633 recv_bytes
= recv_size
;
635 for (i
= 0; i
< recv_bytes
; i
+= 4)
636 unpack_aux(I915_READ(ch_data
+ i
),
637 recv
+ i
, recv_bytes
- i
);
641 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
642 intel_aux_display_runtime_put(dev_priv
);
645 edp_panel_vdd_off(intel_dp
, false);
650 #define BARE_ADDRESS_SIZE 3
651 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
653 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
655 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
656 uint8_t txbuf
[20], rxbuf
[20];
657 size_t txsize
, rxsize
;
660 txbuf
[0] = msg
->request
<< 4;
661 txbuf
[1] = msg
->address
>> 8;
662 txbuf
[2] = msg
->address
& 0xff;
663 txbuf
[3] = msg
->size
- 1;
665 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
666 case DP_AUX_NATIVE_WRITE
:
667 case DP_AUX_I2C_WRITE
:
668 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
671 if (WARN_ON(txsize
> 20))
674 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
676 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
678 msg
->reply
= rxbuf
[0] >> 4;
680 /* Return payload size. */
685 case DP_AUX_NATIVE_READ
:
686 case DP_AUX_I2C_READ
:
687 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
688 rxsize
= msg
->size
+ 1;
690 if (WARN_ON(rxsize
> 20))
693 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
695 msg
->reply
= rxbuf
[0] >> 4;
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
700 * Return payload size.
703 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
716 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
718 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
720 enum port port
= intel_dig_port
->port
;
721 const char *name
= NULL
;
726 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
730 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
734 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
738 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
746 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
748 intel_dp
->aux
.name
= name
;
749 intel_dp
->aux
.dev
= dev
->dev
;
750 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
752 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
753 connector
->base
.kdev
->kobj
.name
);
755 ret
= drm_dp_aux_register(&intel_dp
->aux
);
757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
762 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
763 &intel_dp
->aux
.ddc
.dev
.kobj
,
764 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
767 drm_dp_aux_unregister(&intel_dp
->aux
);
772 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
774 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
776 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
777 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
778 intel_connector_unregister(intel_connector
);
782 intel_dp_set_clock(struct intel_encoder
*encoder
,
783 struct intel_crtc_config
*pipe_config
, int link_bw
)
785 struct drm_device
*dev
= encoder
->base
.dev
;
786 const struct dp_link_dpll
*divisor
= NULL
;
791 count
= ARRAY_SIZE(gen4_dpll
);
792 } else if (IS_HASWELL(dev
)) {
793 /* Haswell has special-purpose DP DDI clocks. */
794 } else if (HAS_PCH_SPLIT(dev
)) {
796 count
= ARRAY_SIZE(pch_dpll
);
797 } else if (IS_CHERRYVIEW(dev
)) {
799 count
= ARRAY_SIZE(chv_dpll
);
800 } else if (IS_VALLEYVIEW(dev
)) {
802 count
= ARRAY_SIZE(vlv_dpll
);
805 if (divisor
&& count
) {
806 for (i
= 0; i
< count
; i
++) {
807 if (link_bw
== divisor
[i
].link_bw
) {
808 pipe_config
->dpll
= divisor
[i
].dpll
;
809 pipe_config
->clock_set
= true;
817 intel_dp_set_m2_n2(struct intel_crtc
*crtc
, struct intel_link_m_n
*m_n
)
819 struct drm_device
*dev
= crtc
->base
.dev
;
820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
821 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
823 I915_WRITE(PIPE_DATA_M2(transcoder
),
824 TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
825 I915_WRITE(PIPE_DATA_N2(transcoder
), m_n
->gmch_n
);
826 I915_WRITE(PIPE_LINK_M2(transcoder
), m_n
->link_m
);
827 I915_WRITE(PIPE_LINK_N2(transcoder
), m_n
->link_n
);
831 intel_dp_compute_config(struct intel_encoder
*encoder
,
832 struct intel_crtc_config
*pipe_config
)
834 struct drm_device
*dev
= encoder
->base
.dev
;
835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
836 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
837 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
838 enum port port
= dp_to_dig_port(intel_dp
)->port
;
839 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
840 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
841 int lane_count
, clock
;
842 int min_lane_count
= 1;
843 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
844 /* Conveniently, the link BW constants become indices with a shift...*/
846 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
848 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
849 int link_avail
, link_clock
;
851 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
852 pipe_config
->has_pch_encoder
= true;
854 pipe_config
->has_dp_encoder
= true;
855 pipe_config
->has_audio
= intel_dp
->has_audio
;
857 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
858 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
860 if (!HAS_PCH_SPLIT(dev
))
861 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
862 intel_connector
->panel
.fitting_mode
);
864 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
865 intel_connector
->panel
.fitting_mode
);
868 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
871 DRM_DEBUG_KMS("DP link computation with max lane count %i "
872 "max bw %02x pixel clock %iKHz\n",
873 max_lane_count
, bws
[max_clock
],
874 adjusted_mode
->crtc_clock
);
876 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
878 bpp
= pipe_config
->pipe_bpp
;
879 if (is_edp(intel_dp
)) {
880 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
881 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
882 dev_priv
->vbt
.edp_bpp
);
883 bpp
= dev_priv
->vbt
.edp_bpp
;
886 if (IS_BROADWELL(dev
)) {
887 /* Yes, it's an ugly hack. */
888 min_lane_count
= max_lane_count
;
889 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
891 } else if (dev_priv
->vbt
.edp_lanes
) {
892 min_lane_count
= min(dev_priv
->vbt
.edp_lanes
,
894 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
898 if (dev_priv
->vbt
.edp_rate
) {
899 min_clock
= min(dev_priv
->vbt
.edp_rate
>> 3, max_clock
);
900 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
905 for (; bpp
>= 6*3; bpp
-= 2*3) {
906 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
909 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
910 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
911 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
912 link_avail
= intel_dp_max_data_rate(link_clock
,
915 if (mode_rate
<= link_avail
) {
925 if (intel_dp
->color_range_auto
) {
928 * CEA-861-E - 5.1 Default Encoding Parameters
929 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
931 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
932 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
934 intel_dp
->color_range
= 0;
937 if (intel_dp
->color_range
)
938 pipe_config
->limited_color_range
= true;
940 intel_dp
->link_bw
= bws
[clock
];
941 intel_dp
->lane_count
= lane_count
;
942 pipe_config
->pipe_bpp
= bpp
;
943 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
945 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
946 intel_dp
->link_bw
, intel_dp
->lane_count
,
947 pipe_config
->port_clock
, bpp
);
948 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
949 mode_rate
, link_avail
);
951 intel_link_compute_m_n(bpp
, lane_count
,
952 adjusted_mode
->crtc_clock
,
953 pipe_config
->port_clock
,
954 &pipe_config
->dp_m_n
);
956 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
957 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
958 intel_link_compute_m_n(bpp
, lane_count
,
959 intel_connector
->panel
.downclock_mode
->clock
,
960 pipe_config
->port_clock
,
961 &pipe_config
->dp_m2_n2
);
964 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
969 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
971 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
972 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
973 struct drm_device
*dev
= crtc
->base
.dev
;
974 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
977 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
978 dpa_ctl
= I915_READ(DP_A
);
979 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
981 if (crtc
->config
.port_clock
== 162000) {
982 /* For a long time we've carried around a ILK-DevA w/a for the
983 * 160MHz clock. If we're really unlucky, it's still required.
985 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
986 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
987 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
989 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
990 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
993 I915_WRITE(DP_A
, dpa_ctl
);
999 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1001 struct drm_device
*dev
= encoder
->base
.dev
;
1002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1003 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1004 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1005 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1006 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1009 * There are four kinds of DP registers:
1016 * IBX PCH and CPU are the same for almost everything,
1017 * except that the CPU DP PLL is configured in this
1020 * CPT PCH is quite different, having many bits moved
1021 * to the TRANS_DP_CTL register instead. That
1022 * configuration happens (oddly) in ironlake_pch_enable
1025 /* Preserve the BIOS-computed detected bit. This is
1026 * supposed to be read-only.
1028 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1030 /* Handle DP bits in common between all three register formats */
1031 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1032 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1034 if (crtc
->config
.has_audio
) {
1035 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1036 pipe_name(crtc
->pipe
));
1037 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1038 intel_write_eld(&encoder
->base
, adjusted_mode
);
1041 /* Split out the IBX/CPU vs CPT settings */
1043 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1044 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1045 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1046 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1047 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1048 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1050 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1051 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1053 intel_dp
->DP
|= crtc
->pipe
<< 29;
1054 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1055 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1056 intel_dp
->DP
|= intel_dp
->color_range
;
1058 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1059 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1060 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1061 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1062 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1064 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1065 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1067 if (!IS_CHERRYVIEW(dev
)) {
1068 if (crtc
->pipe
== 1)
1069 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1071 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1074 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1078 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1079 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1081 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1082 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1084 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1085 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1087 static void wait_panel_status(struct intel_dp
*intel_dp
,
1091 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1093 u32 pp_stat_reg
, pp_ctrl_reg
;
1095 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1096 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1098 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1100 I915_READ(pp_stat_reg
),
1101 I915_READ(pp_ctrl_reg
));
1103 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1104 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1105 I915_READ(pp_stat_reg
),
1106 I915_READ(pp_ctrl_reg
));
1109 DRM_DEBUG_KMS("Wait complete\n");
1112 static void wait_panel_on(struct intel_dp
*intel_dp
)
1114 DRM_DEBUG_KMS("Wait for panel power on\n");
1115 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1118 static void wait_panel_off(struct intel_dp
*intel_dp
)
1120 DRM_DEBUG_KMS("Wait for panel power off time\n");
1121 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1124 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1126 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1128 /* When we disable the VDD override bit last we have to do the manual
1130 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1131 intel_dp
->panel_power_cycle_delay
);
1133 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1136 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1138 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1139 intel_dp
->backlight_on_delay
);
1142 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1144 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1145 intel_dp
->backlight_off_delay
);
1148 /* Read the current pp_control value, unlocking the register if it
1152 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1154 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1158 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1159 control
&= ~PANEL_UNLOCK_MASK
;
1160 control
|= PANEL_UNLOCK_REGS
;
1164 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1166 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1167 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1168 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1170 enum intel_display_power_domain power_domain
;
1172 u32 pp_stat_reg
, pp_ctrl_reg
;
1173 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1175 if (!is_edp(intel_dp
))
1178 intel_dp
->want_panel_vdd
= true;
1180 if (edp_have_panel_vdd(intel_dp
))
1181 return need_to_disable
;
1183 power_domain
= intel_display_port_power_domain(intel_encoder
);
1184 intel_display_power_get(dev_priv
, power_domain
);
1186 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1188 if (!edp_have_panel_power(intel_dp
))
1189 wait_panel_power_cycle(intel_dp
);
1191 pp
= ironlake_get_pp_control(intel_dp
);
1192 pp
|= EDP_FORCE_VDD
;
1194 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1195 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1197 I915_WRITE(pp_ctrl_reg
, pp
);
1198 POSTING_READ(pp_ctrl_reg
);
1199 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1200 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1202 * If the panel wasn't on, delay before accessing aux channel
1204 if (!edp_have_panel_power(intel_dp
)) {
1205 DRM_DEBUG_KMS("eDP was not running\n");
1206 msleep(intel_dp
->panel_power_up_delay
);
1209 return need_to_disable
;
1212 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1214 if (is_edp(intel_dp
)) {
1215 bool vdd
= _edp_panel_vdd_on(intel_dp
);
1217 WARN(!vdd
, "eDP VDD already requested on\n");
1221 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1223 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1226 u32 pp_stat_reg
, pp_ctrl_reg
;
1228 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1230 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1231 struct intel_digital_port
*intel_dig_port
=
1232 dp_to_dig_port(intel_dp
);
1233 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1234 enum intel_display_power_domain power_domain
;
1236 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1238 pp
= ironlake_get_pp_control(intel_dp
);
1239 pp
&= ~EDP_FORCE_VDD
;
1241 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1242 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1244 I915_WRITE(pp_ctrl_reg
, pp
);
1245 POSTING_READ(pp_ctrl_reg
);
1247 /* Make sure sequencer is idle before allowing subsequent activity */
1248 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1249 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1251 if ((pp
& POWER_TARGET_ON
) == 0)
1252 intel_dp
->last_power_cycle
= jiffies
;
1254 power_domain
= intel_display_port_power_domain(intel_encoder
);
1255 intel_display_power_put(dev_priv
, power_domain
);
1259 static void edp_panel_vdd_work(struct work_struct
*__work
)
1261 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1262 struct intel_dp
, panel_vdd_work
);
1263 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1265 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
1266 edp_panel_vdd_off_sync(intel_dp
);
1267 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
1270 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1272 if (!is_edp(intel_dp
))
1275 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1277 intel_dp
->want_panel_vdd
= false;
1280 edp_panel_vdd_off_sync(intel_dp
);
1283 * Queue the timer to fire a long
1284 * time from now (relative to the power down delay)
1285 * to keep the panel power up across a sequence of operations
1287 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1288 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1292 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1294 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1299 if (!is_edp(intel_dp
))
1302 DRM_DEBUG_KMS("Turn eDP power on\n");
1304 if (edp_have_panel_power(intel_dp
)) {
1305 DRM_DEBUG_KMS("eDP power already on\n");
1309 wait_panel_power_cycle(intel_dp
);
1311 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1312 pp
= ironlake_get_pp_control(intel_dp
);
1314 /* ILK workaround: disable reset around power sequence */
1315 pp
&= ~PANEL_POWER_RESET
;
1316 I915_WRITE(pp_ctrl_reg
, pp
);
1317 POSTING_READ(pp_ctrl_reg
);
1320 pp
|= POWER_TARGET_ON
;
1322 pp
|= PANEL_POWER_RESET
;
1324 I915_WRITE(pp_ctrl_reg
, pp
);
1325 POSTING_READ(pp_ctrl_reg
);
1327 wait_panel_on(intel_dp
);
1328 intel_dp
->last_power_on
= jiffies
;
1331 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1332 I915_WRITE(pp_ctrl_reg
, pp
);
1333 POSTING_READ(pp_ctrl_reg
);
1337 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1339 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1340 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1341 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1343 enum intel_display_power_domain power_domain
;
1347 if (!is_edp(intel_dp
))
1350 DRM_DEBUG_KMS("Turn eDP power off\n");
1352 edp_wait_backlight_off(intel_dp
);
1354 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1356 pp
= ironlake_get_pp_control(intel_dp
);
1357 /* We need to switch off panel power _and_ force vdd, for otherwise some
1358 * panels get very unhappy and cease to work. */
1359 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1362 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1364 intel_dp
->want_panel_vdd
= false;
1366 I915_WRITE(pp_ctrl_reg
, pp
);
1367 POSTING_READ(pp_ctrl_reg
);
1369 intel_dp
->last_power_cycle
= jiffies
;
1370 wait_panel_off(intel_dp
);
1372 /* We got a reference when we enabled the VDD. */
1373 power_domain
= intel_display_port_power_domain(intel_encoder
);
1374 intel_display_power_put(dev_priv
, power_domain
);
1377 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1379 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1380 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1385 if (!is_edp(intel_dp
))
1388 DRM_DEBUG_KMS("\n");
1390 * If we enable the backlight right away following a panel power
1391 * on, we may see slight flicker as the panel syncs with the eDP
1392 * link. So delay a bit to make sure the image is solid before
1393 * allowing it to appear.
1395 wait_backlight_on(intel_dp
);
1396 pp
= ironlake_get_pp_control(intel_dp
);
1397 pp
|= EDP_BLC_ENABLE
;
1399 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1401 I915_WRITE(pp_ctrl_reg
, pp
);
1402 POSTING_READ(pp_ctrl_reg
);
1404 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1407 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1409 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1414 if (!is_edp(intel_dp
))
1417 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1419 DRM_DEBUG_KMS("\n");
1420 pp
= ironlake_get_pp_control(intel_dp
);
1421 pp
&= ~EDP_BLC_ENABLE
;
1423 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1425 I915_WRITE(pp_ctrl_reg
, pp
);
1426 POSTING_READ(pp_ctrl_reg
);
1427 intel_dp
->last_backlight_off
= jiffies
;
1430 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1432 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1433 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1434 struct drm_device
*dev
= crtc
->dev
;
1435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1438 assert_pipe_disabled(dev_priv
,
1439 to_intel_crtc(crtc
)->pipe
);
1441 DRM_DEBUG_KMS("\n");
1442 dpa_ctl
= I915_READ(DP_A
);
1443 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1444 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1446 /* We don't adjust intel_dp->DP while tearing down the link, to
1447 * facilitate link retraining (e.g. after hotplug). Hence clear all
1448 * enable bits here to ensure that we don't enable too much. */
1449 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1450 intel_dp
->DP
|= DP_PLL_ENABLE
;
1451 I915_WRITE(DP_A
, intel_dp
->DP
);
1456 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1458 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1459 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1460 struct drm_device
*dev
= crtc
->dev
;
1461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1464 assert_pipe_disabled(dev_priv
,
1465 to_intel_crtc(crtc
)->pipe
);
1467 dpa_ctl
= I915_READ(DP_A
);
1468 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1469 "dp pll off, should be on\n");
1470 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1472 /* We can't rely on the value tracked for the DP register in
1473 * intel_dp->DP because link_down must not change that (otherwise link
1474 * re-training will fail. */
1475 dpa_ctl
&= ~DP_PLL_ENABLE
;
1476 I915_WRITE(DP_A
, dpa_ctl
);
1481 /* If the sink supports it, try to set the power state appropriately */
1482 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1486 /* Should have a valid DPCD by this point */
1487 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1490 if (mode
!= DRM_MODE_DPMS_ON
) {
1491 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1494 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1497 * When turning on, we need to retry for 1ms to give the sink
1500 for (i
= 0; i
< 3; i
++) {
1501 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1510 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1513 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1514 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1515 struct drm_device
*dev
= encoder
->base
.dev
;
1516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1517 enum intel_display_power_domain power_domain
;
1520 power_domain
= intel_display_port_power_domain(encoder
);
1521 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1524 tmp
= I915_READ(intel_dp
->output_reg
);
1526 if (!(tmp
& DP_PORT_EN
))
1529 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1530 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1531 } else if (IS_CHERRYVIEW(dev
)) {
1532 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1533 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1534 *pipe
= PORT_TO_PIPE(tmp
);
1540 switch (intel_dp
->output_reg
) {
1542 trans_sel
= TRANS_DP_PORT_SEL_B
;
1545 trans_sel
= TRANS_DP_PORT_SEL_C
;
1548 trans_sel
= TRANS_DP_PORT_SEL_D
;
1555 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1556 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1562 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1563 intel_dp
->output_reg
);
1569 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1570 struct intel_crtc_config
*pipe_config
)
1572 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1574 struct drm_device
*dev
= encoder
->base
.dev
;
1575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1576 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1577 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1580 tmp
= I915_READ(intel_dp
->output_reg
);
1581 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1582 pipe_config
->has_audio
= true;
1584 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1585 if (tmp
& DP_SYNC_HS_HIGH
)
1586 flags
|= DRM_MODE_FLAG_PHSYNC
;
1588 flags
|= DRM_MODE_FLAG_NHSYNC
;
1590 if (tmp
& DP_SYNC_VS_HIGH
)
1591 flags
|= DRM_MODE_FLAG_PVSYNC
;
1593 flags
|= DRM_MODE_FLAG_NVSYNC
;
1595 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1596 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1597 flags
|= DRM_MODE_FLAG_PHSYNC
;
1599 flags
|= DRM_MODE_FLAG_NHSYNC
;
1601 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1602 flags
|= DRM_MODE_FLAG_PVSYNC
;
1604 flags
|= DRM_MODE_FLAG_NVSYNC
;
1607 pipe_config
->adjusted_mode
.flags
|= flags
;
1609 pipe_config
->has_dp_encoder
= true;
1611 intel_dp_get_m_n(crtc
, pipe_config
);
1613 if (port
== PORT_A
) {
1614 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1615 pipe_config
->port_clock
= 162000;
1617 pipe_config
->port_clock
= 270000;
1620 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1621 &pipe_config
->dp_m_n
);
1623 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1624 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1626 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1628 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1629 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1631 * This is a big fat ugly hack.
1633 * Some machines in UEFI boot mode provide us a VBT that has 18
1634 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1635 * unknown we fail to light up. Yet the same BIOS boots up with
1636 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1637 * max, not what it tells us to use.
1639 * Note: This will still be broken if the eDP panel is not lit
1640 * up by the BIOS, and thus we can't get the mode at module
1643 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1644 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1645 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1649 static bool is_edp_psr(struct drm_device
*dev
)
1651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 return dev_priv
->psr
.sink_support
;
1656 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1663 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1666 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1667 struct edp_vsc_psr
*vsc_psr
)
1669 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1670 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1672 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1673 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1674 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1675 uint32_t *data
= (uint32_t *) vsc_psr
;
1678 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1679 the video DIP being updated before program video DIP data buffer
1680 registers for DIP being updated. */
1681 I915_WRITE(ctl_reg
, 0);
1682 POSTING_READ(ctl_reg
);
1684 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1685 if (i
< sizeof(struct edp_vsc_psr
))
1686 I915_WRITE(data_reg
+ i
, *data
++);
1688 I915_WRITE(data_reg
+ i
, 0);
1691 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1692 POSTING_READ(ctl_reg
);
1695 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1697 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1699 struct edp_vsc_psr psr_vsc
;
1701 if (intel_dp
->psr_setup_done
)
1704 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1705 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1706 psr_vsc
.sdp_header
.HB0
= 0;
1707 psr_vsc
.sdp_header
.HB1
= 0x7;
1708 psr_vsc
.sdp_header
.HB2
= 0x2;
1709 psr_vsc
.sdp_header
.HB3
= 0x8;
1710 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1712 /* Avoid continuous PSR exit by masking memup and hpd */
1713 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1714 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1716 intel_dp
->psr_setup_done
= true;
1719 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1721 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1723 uint32_t aux_clock_divider
;
1724 int precharge
= 0x3;
1725 int msg_size
= 5; /* Header(4) + Message(1) */
1727 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1729 /* Enable PSR in sink */
1730 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
)
1731 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1732 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1734 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1735 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1737 /* Setup AUX registers */
1738 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1739 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1740 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1741 DP_AUX_CH_CTL_TIME_OUT_400us
|
1742 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1743 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1744 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1747 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1749 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1751 uint32_t max_sleep_time
= 0x1f;
1752 uint32_t idle_frames
= 1;
1754 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1756 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
) {
1757 val
|= EDP_PSR_LINK_STANDBY
;
1758 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1759 val
|= EDP_PSR_TP1_TIME_0us
;
1760 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1762 val
|= EDP_PSR_LINK_DISABLE
;
1764 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1765 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
1766 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1767 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1771 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1773 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1774 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1776 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1777 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1778 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(crtc
->primary
->fb
)->obj
;
1779 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
1781 dev_priv
->psr
.source_ok
= false;
1783 if (!HAS_PSR(dev
)) {
1784 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1788 if ((intel_encoder
->type
!= INTEL_OUTPUT_EDP
) ||
1789 (dig_port
->port
!= PORT_A
)) {
1790 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1794 if (!i915
.enable_psr
) {
1795 DRM_DEBUG_KMS("PSR disable by flag\n");
1799 crtc
= dig_port
->base
.base
.crtc
;
1801 DRM_DEBUG_KMS("crtc not active for PSR\n");
1805 intel_crtc
= to_intel_crtc(crtc
);
1806 if (!intel_crtc_active(crtc
)) {
1807 DRM_DEBUG_KMS("crtc not active for PSR\n");
1811 obj
= to_intel_framebuffer(crtc
->primary
->fb
)->obj
;
1812 if (obj
->tiling_mode
!= I915_TILING_X
||
1813 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1814 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1818 if (I915_READ(SPRCTL(intel_crtc
->pipe
)) & SPRITE_ENABLE
) {
1819 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1823 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1825 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1829 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1830 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1834 dev_priv
->psr
.source_ok
= true;
1838 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1840 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1842 if (!intel_edp_psr_match_conditions(intel_dp
) ||
1843 intel_edp_is_psr_enabled(dev
))
1846 /* Setup PSR once */
1847 intel_edp_psr_setup(intel_dp
);
1849 /* Enable PSR on the panel */
1850 intel_edp_psr_enable_sink(intel_dp
);
1852 /* Enable PSR on the host */
1853 intel_edp_psr_enable_source(intel_dp
);
1856 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1858 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1860 if (intel_edp_psr_match_conditions(intel_dp
) &&
1861 !intel_edp_is_psr_enabled(dev
))
1862 intel_edp_psr_do_enable(intel_dp
);
1865 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1867 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1870 if (!intel_edp_is_psr_enabled(dev
))
1873 I915_WRITE(EDP_PSR_CTL(dev
),
1874 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1876 /* Wait till PSR is idle */
1877 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1878 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1879 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1882 void intel_edp_psr_update(struct drm_device
*dev
)
1884 struct intel_encoder
*encoder
;
1885 struct intel_dp
*intel_dp
= NULL
;
1887 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
)
1888 if (encoder
->type
== INTEL_OUTPUT_EDP
) {
1889 intel_dp
= enc_to_intel_dp(&encoder
->base
);
1891 if (!is_edp_psr(dev
))
1894 if (!intel_edp_psr_match_conditions(intel_dp
))
1895 intel_edp_psr_disable(intel_dp
);
1897 if (!intel_edp_is_psr_enabled(dev
))
1898 intel_edp_psr_do_enable(intel_dp
);
1902 static void intel_disable_dp(struct intel_encoder
*encoder
)
1904 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1905 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1906 struct drm_device
*dev
= encoder
->base
.dev
;
1908 /* Make sure the panel is off before trying to change the mode. But also
1909 * ensure that we have vdd while we switch off the panel. */
1910 intel_edp_panel_vdd_on(intel_dp
);
1911 intel_edp_backlight_off(intel_dp
);
1912 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1913 intel_edp_panel_off(intel_dp
);
1915 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1916 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
1917 intel_dp_link_down(intel_dp
);
1920 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
1922 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1923 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1928 intel_dp_link_down(intel_dp
);
1929 ironlake_edp_pll_off(intel_dp
);
1932 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
1934 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1936 intel_dp_link_down(intel_dp
);
1939 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
1941 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1942 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
1943 struct drm_device
*dev
= encoder
->base
.dev
;
1944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1945 struct intel_crtc
*intel_crtc
=
1946 to_intel_crtc(encoder
->base
.crtc
);
1947 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
1948 enum pipe pipe
= intel_crtc
->pipe
;
1951 intel_dp_link_down(intel_dp
);
1953 mutex_lock(&dev_priv
->dpio_lock
);
1955 /* Propagate soft reset to data lane reset */
1956 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
1957 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1958 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
1960 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
1961 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
1962 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
1964 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
1965 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1966 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
1968 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
1969 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
1970 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
1972 mutex_unlock(&dev_priv
->dpio_lock
);
1975 static void intel_enable_dp(struct intel_encoder
*encoder
)
1977 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1978 struct drm_device
*dev
= encoder
->base
.dev
;
1979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1980 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1982 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1985 intel_edp_panel_vdd_on(intel_dp
);
1986 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1987 intel_dp_start_link_train(intel_dp
);
1988 intel_edp_panel_on(intel_dp
);
1989 edp_panel_vdd_off(intel_dp
, true);
1990 intel_dp_complete_link_train(intel_dp
);
1991 intel_dp_stop_link_train(intel_dp
);
1994 static void g4x_enable_dp(struct intel_encoder
*encoder
)
1996 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1998 intel_enable_dp(encoder
);
1999 intel_edp_backlight_on(intel_dp
);
2002 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2004 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2006 intel_edp_backlight_on(intel_dp
);
2009 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2011 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2012 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2014 intel_dp_prepare(encoder
);
2016 /* Only ilk+ has port A */
2017 if (dport
->port
== PORT_A
) {
2018 ironlake_set_pll_cpu_edp(intel_dp
);
2019 ironlake_edp_pll_on(intel_dp
);
2023 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2025 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2026 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2027 struct drm_device
*dev
= encoder
->base
.dev
;
2028 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2029 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2030 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2031 int pipe
= intel_crtc
->pipe
;
2032 struct edp_power_seq power_seq
;
2035 mutex_lock(&dev_priv
->dpio_lock
);
2037 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2044 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2045 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2046 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2048 mutex_unlock(&dev_priv
->dpio_lock
);
2050 if (is_edp(intel_dp
)) {
2051 /* init power sequencer on this pipe and port */
2052 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2053 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2057 intel_enable_dp(encoder
);
2059 vlv_wait_port_ready(dev_priv
, dport
);
2062 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2064 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2065 struct drm_device
*dev
= encoder
->base
.dev
;
2066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2067 struct intel_crtc
*intel_crtc
=
2068 to_intel_crtc(encoder
->base
.crtc
);
2069 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2070 int pipe
= intel_crtc
->pipe
;
2072 intel_dp_prepare(encoder
);
2074 /* Program Tx lane resets to default */
2075 mutex_lock(&dev_priv
->dpio_lock
);
2076 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2077 DPIO_PCS_TX_LANE2_RESET
|
2078 DPIO_PCS_TX_LANE1_RESET
);
2079 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2080 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2081 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2082 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2083 DPIO_PCS_CLK_SOFT_RESET
);
2085 /* Fix up inter-pair skew failure */
2086 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2087 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2088 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2089 mutex_unlock(&dev_priv
->dpio_lock
);
2092 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2094 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2095 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2096 struct drm_device
*dev
= encoder
->base
.dev
;
2097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2098 struct edp_power_seq power_seq
;
2099 struct intel_crtc
*intel_crtc
=
2100 to_intel_crtc(encoder
->base
.crtc
);
2101 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2102 int pipe
= intel_crtc
->pipe
;
2106 mutex_lock(&dev_priv
->dpio_lock
);
2108 /* Deassert soft data lane reset*/
2109 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2110 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2111 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2113 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2114 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2115 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2117 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2118 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2119 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2121 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2122 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2123 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2125 /* Program Tx lane latency optimal setting*/
2126 for (i
= 0; i
< 4; i
++) {
2127 /* Set the latency optimal bit */
2128 data
= (i
== 1) ? 0x0 : 0x6;
2129 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2130 data
<< DPIO_FRC_LATENCY_SHFIT
);
2132 /* Set the upar bit */
2133 data
= (i
== 1) ? 0x0 : 0x1;
2134 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2135 data
<< DPIO_UPAR_SHIFT
);
2138 /* Data lane stagger programming */
2139 /* FIXME: Fix up value only after power analysis */
2141 mutex_unlock(&dev_priv
->dpio_lock
);
2143 if (is_edp(intel_dp
)) {
2144 /* init power sequencer on this pipe and port */
2145 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2146 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2150 intel_enable_dp(encoder
);
2152 vlv_wait_port_ready(dev_priv
, dport
);
2156 * Native read with retry for link status and receiver capability reads for
2157 * cases where the sink may still be asleep.
2159 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2160 * supposed to retry 3 times per the spec.
2163 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2164 void *buffer
, size_t size
)
2169 for (i
= 0; i
< 3; i
++) {
2170 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2180 * Fetch AUX CH registers 0x202 - 0x207 which contain
2181 * link status information
2184 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2186 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2189 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2193 * These are source-specific values; current Intel hardware supports
2194 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2198 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2200 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2201 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2203 if (IS_VALLEYVIEW(dev
) || IS_BROADWELL(dev
))
2204 return DP_TRAIN_VOLTAGE_SWING_1200
;
2205 else if (IS_GEN7(dev
) && port
== PORT_A
)
2206 return DP_TRAIN_VOLTAGE_SWING_800
;
2207 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2208 return DP_TRAIN_VOLTAGE_SWING_1200
;
2210 return DP_TRAIN_VOLTAGE_SWING_800
;
2214 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2216 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2217 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2219 if (IS_BROADWELL(dev
)) {
2220 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2221 case DP_TRAIN_VOLTAGE_SWING_400
:
2222 case DP_TRAIN_VOLTAGE_SWING_600
:
2223 return DP_TRAIN_PRE_EMPHASIS_6
;
2224 case DP_TRAIN_VOLTAGE_SWING_800
:
2225 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2226 case DP_TRAIN_VOLTAGE_SWING_1200
:
2228 return DP_TRAIN_PRE_EMPHASIS_0
;
2230 } else if (IS_HASWELL(dev
)) {
2231 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2232 case DP_TRAIN_VOLTAGE_SWING_400
:
2233 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2234 case DP_TRAIN_VOLTAGE_SWING_600
:
2235 return DP_TRAIN_PRE_EMPHASIS_6
;
2236 case DP_TRAIN_VOLTAGE_SWING_800
:
2237 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2238 case DP_TRAIN_VOLTAGE_SWING_1200
:
2240 return DP_TRAIN_PRE_EMPHASIS_0
;
2242 } else if (IS_VALLEYVIEW(dev
)) {
2243 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2244 case DP_TRAIN_VOLTAGE_SWING_400
:
2245 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2246 case DP_TRAIN_VOLTAGE_SWING_600
:
2247 return DP_TRAIN_PRE_EMPHASIS_6
;
2248 case DP_TRAIN_VOLTAGE_SWING_800
:
2249 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2250 case DP_TRAIN_VOLTAGE_SWING_1200
:
2252 return DP_TRAIN_PRE_EMPHASIS_0
;
2254 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2255 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2256 case DP_TRAIN_VOLTAGE_SWING_400
:
2257 return DP_TRAIN_PRE_EMPHASIS_6
;
2258 case DP_TRAIN_VOLTAGE_SWING_600
:
2259 case DP_TRAIN_VOLTAGE_SWING_800
:
2260 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2262 return DP_TRAIN_PRE_EMPHASIS_0
;
2265 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2266 case DP_TRAIN_VOLTAGE_SWING_400
:
2267 return DP_TRAIN_PRE_EMPHASIS_6
;
2268 case DP_TRAIN_VOLTAGE_SWING_600
:
2269 return DP_TRAIN_PRE_EMPHASIS_6
;
2270 case DP_TRAIN_VOLTAGE_SWING_800
:
2271 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2272 case DP_TRAIN_VOLTAGE_SWING_1200
:
2274 return DP_TRAIN_PRE_EMPHASIS_0
;
2279 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2281 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2283 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2284 struct intel_crtc
*intel_crtc
=
2285 to_intel_crtc(dport
->base
.base
.crtc
);
2286 unsigned long demph_reg_value
, preemph_reg_value
,
2287 uniqtranscale_reg_value
;
2288 uint8_t train_set
= intel_dp
->train_set
[0];
2289 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2290 int pipe
= intel_crtc
->pipe
;
2292 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2293 case DP_TRAIN_PRE_EMPHASIS_0
:
2294 preemph_reg_value
= 0x0004000;
2295 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2296 case DP_TRAIN_VOLTAGE_SWING_400
:
2297 demph_reg_value
= 0x2B405555;
2298 uniqtranscale_reg_value
= 0x552AB83A;
2300 case DP_TRAIN_VOLTAGE_SWING_600
:
2301 demph_reg_value
= 0x2B404040;
2302 uniqtranscale_reg_value
= 0x5548B83A;
2304 case DP_TRAIN_VOLTAGE_SWING_800
:
2305 demph_reg_value
= 0x2B245555;
2306 uniqtranscale_reg_value
= 0x5560B83A;
2308 case DP_TRAIN_VOLTAGE_SWING_1200
:
2309 demph_reg_value
= 0x2B405555;
2310 uniqtranscale_reg_value
= 0x5598DA3A;
2316 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2317 preemph_reg_value
= 0x0002000;
2318 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2319 case DP_TRAIN_VOLTAGE_SWING_400
:
2320 demph_reg_value
= 0x2B404040;
2321 uniqtranscale_reg_value
= 0x5552B83A;
2323 case DP_TRAIN_VOLTAGE_SWING_600
:
2324 demph_reg_value
= 0x2B404848;
2325 uniqtranscale_reg_value
= 0x5580B83A;
2327 case DP_TRAIN_VOLTAGE_SWING_800
:
2328 demph_reg_value
= 0x2B404040;
2329 uniqtranscale_reg_value
= 0x55ADDA3A;
2335 case DP_TRAIN_PRE_EMPHASIS_6
:
2336 preemph_reg_value
= 0x0000000;
2337 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2338 case DP_TRAIN_VOLTAGE_SWING_400
:
2339 demph_reg_value
= 0x2B305555;
2340 uniqtranscale_reg_value
= 0x5570B83A;
2342 case DP_TRAIN_VOLTAGE_SWING_600
:
2343 demph_reg_value
= 0x2B2B4040;
2344 uniqtranscale_reg_value
= 0x55ADDA3A;
2350 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2351 preemph_reg_value
= 0x0006000;
2352 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2353 case DP_TRAIN_VOLTAGE_SWING_400
:
2354 demph_reg_value
= 0x1B405555;
2355 uniqtranscale_reg_value
= 0x55ADDA3A;
2365 mutex_lock(&dev_priv
->dpio_lock
);
2366 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2367 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2368 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2369 uniqtranscale_reg_value
);
2370 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2371 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2372 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2373 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2374 mutex_unlock(&dev_priv
->dpio_lock
);
2379 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2381 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2383 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2384 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2385 u32 deemph_reg_value
, margin_reg_value
, val
;
2386 uint8_t train_set
= intel_dp
->train_set
[0];
2387 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2388 enum pipe pipe
= intel_crtc
->pipe
;
2391 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2392 case DP_TRAIN_PRE_EMPHASIS_0
:
2393 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2394 case DP_TRAIN_VOLTAGE_SWING_400
:
2395 deemph_reg_value
= 128;
2396 margin_reg_value
= 52;
2398 case DP_TRAIN_VOLTAGE_SWING_600
:
2399 deemph_reg_value
= 128;
2400 margin_reg_value
= 77;
2402 case DP_TRAIN_VOLTAGE_SWING_800
:
2403 deemph_reg_value
= 128;
2404 margin_reg_value
= 102;
2406 case DP_TRAIN_VOLTAGE_SWING_1200
:
2407 deemph_reg_value
= 128;
2408 margin_reg_value
= 154;
2409 /* FIXME extra to set for 1200 */
2415 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2416 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2417 case DP_TRAIN_VOLTAGE_SWING_400
:
2418 deemph_reg_value
= 85;
2419 margin_reg_value
= 78;
2421 case DP_TRAIN_VOLTAGE_SWING_600
:
2422 deemph_reg_value
= 85;
2423 margin_reg_value
= 116;
2425 case DP_TRAIN_VOLTAGE_SWING_800
:
2426 deemph_reg_value
= 85;
2427 margin_reg_value
= 154;
2433 case DP_TRAIN_PRE_EMPHASIS_6
:
2434 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2435 case DP_TRAIN_VOLTAGE_SWING_400
:
2436 deemph_reg_value
= 64;
2437 margin_reg_value
= 104;
2439 case DP_TRAIN_VOLTAGE_SWING_600
:
2440 deemph_reg_value
= 64;
2441 margin_reg_value
= 154;
2447 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2448 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2449 case DP_TRAIN_VOLTAGE_SWING_400
:
2450 deemph_reg_value
= 43;
2451 margin_reg_value
= 154;
2461 mutex_lock(&dev_priv
->dpio_lock
);
2463 /* Clear calc init */
2464 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2465 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2466 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2468 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2469 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2470 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2472 /* Program swing deemph */
2473 for (i
= 0; i
< 4; i
++) {
2474 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2475 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2476 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2477 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2480 /* Program swing margin */
2481 for (i
= 0; i
< 4; i
++) {
2482 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2483 val
&= ~DPIO_SWING_MARGIN_MASK
;
2484 val
|= margin_reg_value
<< DPIO_SWING_MARGIN_SHIFT
;
2485 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2488 /* Disable unique transition scale */
2489 for (i
= 0; i
< 4; i
++) {
2490 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2491 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2492 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2495 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
2496 == DP_TRAIN_PRE_EMPHASIS_0
) &&
2497 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
2498 == DP_TRAIN_VOLTAGE_SWING_1200
)) {
2501 * The document said it needs to set bit 27 for ch0 and bit 26
2502 * for ch1. Might be a typo in the doc.
2503 * For now, for this unique transition scale selection, set bit
2504 * 27 for ch0 and ch1.
2506 for (i
= 0; i
< 4; i
++) {
2507 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2508 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2509 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2512 for (i
= 0; i
< 4; i
++) {
2513 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2514 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2515 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2516 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2520 /* Start swing calculation */
2521 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2522 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2523 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2525 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2526 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2527 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2530 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
2531 val
|= DPIO_LRC_BYPASS
;
2532 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
2534 mutex_unlock(&dev_priv
->dpio_lock
);
2540 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2541 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2546 uint8_t voltage_max
;
2547 uint8_t preemph_max
;
2549 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2550 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2551 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2559 voltage_max
= intel_dp_voltage_max(intel_dp
);
2560 if (v
>= voltage_max
)
2561 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2563 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2564 if (p
>= preemph_max
)
2565 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2567 for (lane
= 0; lane
< 4; lane
++)
2568 intel_dp
->train_set
[lane
] = v
| p
;
2572 intel_gen4_signal_levels(uint8_t train_set
)
2574 uint32_t signal_levels
= 0;
2576 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2577 case DP_TRAIN_VOLTAGE_SWING_400
:
2579 signal_levels
|= DP_VOLTAGE_0_4
;
2581 case DP_TRAIN_VOLTAGE_SWING_600
:
2582 signal_levels
|= DP_VOLTAGE_0_6
;
2584 case DP_TRAIN_VOLTAGE_SWING_800
:
2585 signal_levels
|= DP_VOLTAGE_0_8
;
2587 case DP_TRAIN_VOLTAGE_SWING_1200
:
2588 signal_levels
|= DP_VOLTAGE_1_2
;
2591 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2592 case DP_TRAIN_PRE_EMPHASIS_0
:
2594 signal_levels
|= DP_PRE_EMPHASIS_0
;
2596 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2597 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2599 case DP_TRAIN_PRE_EMPHASIS_6
:
2600 signal_levels
|= DP_PRE_EMPHASIS_6
;
2602 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2603 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2606 return signal_levels
;
2609 /* Gen6's DP voltage swing and pre-emphasis control */
2611 intel_gen6_edp_signal_levels(uint8_t train_set
)
2613 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2614 DP_TRAIN_PRE_EMPHASIS_MASK
);
2615 switch (signal_levels
) {
2616 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2617 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2618 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2619 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2620 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2621 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2622 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2623 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2624 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2625 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2626 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2627 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2628 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2629 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2631 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2632 "0x%x\n", signal_levels
);
2633 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2637 /* Gen7's DP voltage swing and pre-emphasis control */
2639 intel_gen7_edp_signal_levels(uint8_t train_set
)
2641 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2642 DP_TRAIN_PRE_EMPHASIS_MASK
);
2643 switch (signal_levels
) {
2644 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2645 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2646 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2647 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2648 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2649 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2651 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2652 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2653 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2654 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2656 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2657 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2658 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2659 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2662 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2663 "0x%x\n", signal_levels
);
2664 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2668 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2670 intel_hsw_signal_levels(uint8_t train_set
)
2672 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2673 DP_TRAIN_PRE_EMPHASIS_MASK
);
2674 switch (signal_levels
) {
2675 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2676 return DDI_BUF_EMP_400MV_0DB_HSW
;
2677 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2678 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2679 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2680 return DDI_BUF_EMP_400MV_6DB_HSW
;
2681 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2682 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2684 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2685 return DDI_BUF_EMP_600MV_0DB_HSW
;
2686 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2687 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2688 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2689 return DDI_BUF_EMP_600MV_6DB_HSW
;
2691 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2692 return DDI_BUF_EMP_800MV_0DB_HSW
;
2693 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2694 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2696 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2697 "0x%x\n", signal_levels
);
2698 return DDI_BUF_EMP_400MV_0DB_HSW
;
2703 intel_bdw_signal_levels(uint8_t train_set
)
2705 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2706 DP_TRAIN_PRE_EMPHASIS_MASK
);
2707 switch (signal_levels
) {
2708 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2709 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2710 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2711 return DDI_BUF_EMP_400MV_3_5DB_BDW
; /* Sel1 */
2712 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2713 return DDI_BUF_EMP_400MV_6DB_BDW
; /* Sel2 */
2715 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2716 return DDI_BUF_EMP_600MV_0DB_BDW
; /* Sel3 */
2717 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2718 return DDI_BUF_EMP_600MV_3_5DB_BDW
; /* Sel4 */
2719 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2720 return DDI_BUF_EMP_600MV_6DB_BDW
; /* Sel5 */
2722 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2723 return DDI_BUF_EMP_800MV_0DB_BDW
; /* Sel6 */
2724 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2725 return DDI_BUF_EMP_800MV_3_5DB_BDW
; /* Sel7 */
2727 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2728 return DDI_BUF_EMP_1200MV_0DB_BDW
; /* Sel8 */
2731 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2732 "0x%x\n", signal_levels
);
2733 return DDI_BUF_EMP_400MV_0DB_BDW
; /* Sel0 */
2737 /* Properly updates "DP" with the correct signal levels. */
2739 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2741 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2742 enum port port
= intel_dig_port
->port
;
2743 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2744 uint32_t signal_levels
, mask
;
2745 uint8_t train_set
= intel_dp
->train_set
[0];
2747 if (IS_BROADWELL(dev
)) {
2748 signal_levels
= intel_bdw_signal_levels(train_set
);
2749 mask
= DDI_BUF_EMP_MASK
;
2750 } else if (IS_HASWELL(dev
)) {
2751 signal_levels
= intel_hsw_signal_levels(train_set
);
2752 mask
= DDI_BUF_EMP_MASK
;
2753 } else if (IS_CHERRYVIEW(dev
)) {
2754 signal_levels
= intel_chv_signal_levels(intel_dp
);
2756 } else if (IS_VALLEYVIEW(dev
)) {
2757 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2759 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2760 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2761 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2762 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2763 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2764 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2766 signal_levels
= intel_gen4_signal_levels(train_set
);
2767 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2770 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2772 *DP
= (*DP
& ~mask
) | signal_levels
;
2776 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2778 uint8_t dp_train_pat
)
2780 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2781 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2783 enum port port
= intel_dig_port
->port
;
2784 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2788 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2790 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2791 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2793 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2795 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2796 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2797 case DP_TRAINING_PATTERN_DISABLE
:
2798 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2801 case DP_TRAINING_PATTERN_1
:
2802 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2804 case DP_TRAINING_PATTERN_2
:
2805 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2807 case DP_TRAINING_PATTERN_3
:
2808 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2811 I915_WRITE(DP_TP_CTL(port
), temp
);
2813 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2814 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2816 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2817 case DP_TRAINING_PATTERN_DISABLE
:
2818 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2820 case DP_TRAINING_PATTERN_1
:
2821 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2823 case DP_TRAINING_PATTERN_2
:
2824 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2826 case DP_TRAINING_PATTERN_3
:
2827 DRM_ERROR("DP training pattern 3 not supported\n");
2828 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2833 *DP
&= ~DP_LINK_TRAIN_MASK
;
2835 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2836 case DP_TRAINING_PATTERN_DISABLE
:
2837 *DP
|= DP_LINK_TRAIN_OFF
;
2839 case DP_TRAINING_PATTERN_1
:
2840 *DP
|= DP_LINK_TRAIN_PAT_1
;
2842 case DP_TRAINING_PATTERN_2
:
2843 *DP
|= DP_LINK_TRAIN_PAT_2
;
2845 case DP_TRAINING_PATTERN_3
:
2846 DRM_ERROR("DP training pattern 3 not supported\n");
2847 *DP
|= DP_LINK_TRAIN_PAT_2
;
2852 I915_WRITE(intel_dp
->output_reg
, *DP
);
2853 POSTING_READ(intel_dp
->output_reg
);
2855 buf
[0] = dp_train_pat
;
2856 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2857 DP_TRAINING_PATTERN_DISABLE
) {
2858 /* don't write DP_TRAINING_LANEx_SET on disable */
2861 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2862 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
2863 len
= intel_dp
->lane_count
+ 1;
2866 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
2873 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2874 uint8_t dp_train_pat
)
2876 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
2877 intel_dp_set_signal_levels(intel_dp
, DP
);
2878 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
2882 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
2883 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2885 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2886 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2890 intel_get_adjust_train(intel_dp
, link_status
);
2891 intel_dp_set_signal_levels(intel_dp
, DP
);
2893 I915_WRITE(intel_dp
->output_reg
, *DP
);
2894 POSTING_READ(intel_dp
->output_reg
);
2896 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
2897 intel_dp
->train_set
, intel_dp
->lane_count
);
2899 return ret
== intel_dp
->lane_count
;
2902 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
2904 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2905 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2907 enum port port
= intel_dig_port
->port
;
2913 val
= I915_READ(DP_TP_CTL(port
));
2914 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2915 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
2916 I915_WRITE(DP_TP_CTL(port
), val
);
2919 * On PORT_A we can have only eDP in SST mode. There the only reason
2920 * we need to set idle transmission mode is to work around a HW issue
2921 * where we enable the pipe while not in idle link-training mode.
2922 * In this case there is requirement to wait for a minimum number of
2923 * idle patterns to be sent.
2928 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
2930 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2933 /* Enable corresponding port and start training pattern 1 */
2935 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
2937 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
2938 struct drm_device
*dev
= encoder
->dev
;
2941 int voltage_tries
, loop_tries
;
2942 uint32_t DP
= intel_dp
->DP
;
2943 uint8_t link_config
[2];
2946 intel_ddi_prepare_link_retrain(encoder
);
2948 /* Write the link configuration data */
2949 link_config
[0] = intel_dp
->link_bw
;
2950 link_config
[1] = intel_dp
->lane_count
;
2951 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2952 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
2953 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
2956 link_config
[1] = DP_SET_ANSI_8B10B
;
2957 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
2961 /* clock recovery */
2962 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
2963 DP_TRAINING_PATTERN_1
|
2964 DP_LINK_SCRAMBLING_DISABLE
)) {
2965 DRM_ERROR("failed to enable link training\n");
2973 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
2975 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
2976 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2977 DRM_ERROR("failed to get link status\n");
2981 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
2982 DRM_DEBUG_KMS("clock recovery OK\n");
2986 /* Check to see if we've tried the max voltage */
2987 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
2988 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
2990 if (i
== intel_dp
->lane_count
) {
2992 if (loop_tries
== 5) {
2993 DRM_ERROR("too many full retries, give up\n");
2996 intel_dp_reset_link_train(intel_dp
, &DP
,
2997 DP_TRAINING_PATTERN_1
|
2998 DP_LINK_SCRAMBLING_DISABLE
);
3003 /* Check to see if we've tried the same voltage 5 times */
3004 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3006 if (voltage_tries
== 5) {
3007 DRM_ERROR("too many voltage retries, give up\n");
3012 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3014 /* Update training set as requested by target */
3015 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3016 DRM_ERROR("failed to update link training\n");
3025 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3027 bool channel_eq
= false;
3028 int tries
, cr_tries
;
3029 uint32_t DP
= intel_dp
->DP
;
3030 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3032 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3033 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3034 training_pattern
= DP_TRAINING_PATTERN_3
;
3036 /* channel equalization */
3037 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3039 DP_LINK_SCRAMBLING_DISABLE
)) {
3040 DRM_ERROR("failed to start channel equalization\n");
3048 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3051 DRM_ERROR("failed to train DP, aborting\n");
3055 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3056 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3057 DRM_ERROR("failed to get link status\n");
3061 /* Make sure clock is still ok */
3062 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3063 intel_dp_start_link_train(intel_dp
);
3064 intel_dp_set_link_train(intel_dp
, &DP
,
3066 DP_LINK_SCRAMBLING_DISABLE
);
3071 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3076 /* Try 5 times, then try clock recovery if that fails */
3078 intel_dp_link_down(intel_dp
);
3079 intel_dp_start_link_train(intel_dp
);
3080 intel_dp_set_link_train(intel_dp
, &DP
,
3082 DP_LINK_SCRAMBLING_DISABLE
);
3088 /* Update training set as requested by target */
3089 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3090 DRM_ERROR("failed to update link training\n");
3096 intel_dp_set_idle_link_train(intel_dp
);
3101 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3105 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3107 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3108 DP_TRAINING_PATTERN_DISABLE
);
3112 intel_dp_link_down(struct intel_dp
*intel_dp
)
3114 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3115 enum port port
= intel_dig_port
->port
;
3116 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3118 struct intel_crtc
*intel_crtc
=
3119 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3120 uint32_t DP
= intel_dp
->DP
;
3122 if (WARN_ON(HAS_DDI(dev
)))
3125 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3128 DRM_DEBUG_KMS("\n");
3130 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3131 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3132 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3134 DP
&= ~DP_LINK_TRAIN_MASK
;
3135 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3137 POSTING_READ(intel_dp
->output_reg
);
3139 if (HAS_PCH_IBX(dev
) &&
3140 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3141 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3143 /* Hardware workaround: leaving our transcoder select
3144 * set to transcoder B while it's off will prevent the
3145 * corresponding HDMI output on transcoder A.
3147 * Combine this with another hardware workaround:
3148 * transcoder select bit can only be cleared while the
3151 DP
&= ~DP_PIPEB_SELECT
;
3152 I915_WRITE(intel_dp
->output_reg
, DP
);
3154 /* Changes to enable or select take place the vblank
3155 * after being written.
3157 if (WARN_ON(crtc
== NULL
)) {
3158 /* We should never try to disable a port without a crtc
3159 * attached. For paranoia keep the code around for a
3161 POSTING_READ(intel_dp
->output_reg
);
3164 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3167 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3168 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3169 POSTING_READ(intel_dp
->output_reg
);
3170 msleep(intel_dp
->panel_power_down_delay
);
3174 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3176 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3177 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3180 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
3182 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3183 sizeof(intel_dp
->dpcd
)) < 0)
3184 return false; /* aux transfer failed */
3186 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
3187 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
3188 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
3190 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3191 return false; /* DPCD not present */
3193 /* Check if the panel supports PSR */
3194 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3195 if (is_edp(intel_dp
)) {
3196 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3198 sizeof(intel_dp
->psr_dpcd
));
3199 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3200 dev_priv
->psr
.sink_support
= true;
3201 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3205 /* Training Pattern 3 support */
3206 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3207 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3208 intel_dp
->use_tps3
= true;
3209 DRM_DEBUG_KMS("Displayport TPS3 supported");
3211 intel_dp
->use_tps3
= false;
3213 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3214 DP_DWN_STRM_PORT_PRESENT
))
3215 return true; /* native DP sink */
3217 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3218 return true; /* no per-port downstream info */
3220 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3221 intel_dp
->downstream_ports
,
3222 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3223 return false; /* downstream port status fetch failed */
3229 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3233 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3236 intel_edp_panel_vdd_on(intel_dp
);
3238 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3239 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3240 buf
[0], buf
[1], buf
[2]);
3242 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3243 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3244 buf
[0], buf
[1], buf
[2]);
3246 edp_panel_vdd_off(intel_dp
, false);
3249 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3251 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3252 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3253 struct intel_crtc
*intel_crtc
=
3254 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3257 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3260 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3263 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3264 DP_TEST_SINK_START
) < 0)
3267 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3268 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3269 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3271 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3274 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3279 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3281 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3282 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3283 sink_irq_vector
, 1) == 1;
3287 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3289 /* NAK by default */
3290 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3294 * According to DP spec
3297 * 2. Configure link according to Receiver Capabilities
3298 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3299 * 4. Check link status on receipt of hot-plug interrupt
3303 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3305 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3307 u8 link_status
[DP_LINK_STATUS_SIZE
];
3309 /* FIXME: This access isn't protected by any locks. */
3310 if (!intel_encoder
->connectors_active
)
3313 if (WARN_ON(!intel_encoder
->base
.crtc
))
3316 /* Try to read receiver status if the link appears to be up */
3317 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3321 /* Now read the DPCD to see if it's actually running */
3322 if (!intel_dp_get_dpcd(intel_dp
)) {
3326 /* Try to read the source of the interrupt */
3327 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3328 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3329 /* Clear interrupt source */
3330 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3331 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3334 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3335 intel_dp_handle_test_request(intel_dp
);
3336 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3337 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3340 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3341 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3342 intel_encoder
->base
.name
);
3343 intel_dp_start_link_train(intel_dp
);
3344 intel_dp_complete_link_train(intel_dp
);
3345 intel_dp_stop_link_train(intel_dp
);
3349 /* XXX this is probably wrong for multiple downstream ports */
3350 static enum drm_connector_status
3351 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3353 uint8_t *dpcd
= intel_dp
->dpcd
;
3356 if (!intel_dp_get_dpcd(intel_dp
))
3357 return connector_status_disconnected
;
3359 /* if there's no downstream port, we're done */
3360 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3361 return connector_status_connected
;
3363 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3364 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3365 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3368 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3370 return connector_status_unknown
;
3372 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3373 : connector_status_disconnected
;
3376 /* If no HPD, poke DDC gently */
3377 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3378 return connector_status_connected
;
3380 /* Well we tried, say unknown for unreliable port types */
3381 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3382 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3383 if (type
== DP_DS_PORT_TYPE_VGA
||
3384 type
== DP_DS_PORT_TYPE_NON_EDID
)
3385 return connector_status_unknown
;
3387 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3388 DP_DWN_STRM_PORT_TYPE_MASK
;
3389 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3390 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3391 return connector_status_unknown
;
3394 /* Anything else is out of spec, warn and ignore */
3395 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3396 return connector_status_disconnected
;
3399 static enum drm_connector_status
3400 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3402 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3404 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3405 enum drm_connector_status status
;
3407 /* Can't disconnect eDP, but you can close the lid... */
3408 if (is_edp(intel_dp
)) {
3409 status
= intel_panel_detect(dev
);
3410 if (status
== connector_status_unknown
)
3411 status
= connector_status_connected
;
3415 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3416 return connector_status_disconnected
;
3418 return intel_dp_detect_dpcd(intel_dp
);
3421 static enum drm_connector_status
3422 g4x_dp_detect(struct intel_dp
*intel_dp
)
3424 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3426 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3429 /* Can't disconnect eDP, but you can close the lid... */
3430 if (is_edp(intel_dp
)) {
3431 enum drm_connector_status status
;
3433 status
= intel_panel_detect(dev
);
3434 if (status
== connector_status_unknown
)
3435 status
= connector_status_connected
;
3439 if (IS_VALLEYVIEW(dev
)) {
3440 switch (intel_dig_port
->port
) {
3442 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3445 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3448 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3451 return connector_status_unknown
;
3454 switch (intel_dig_port
->port
) {
3456 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3459 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3462 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3465 return connector_status_unknown
;
3469 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3470 return connector_status_disconnected
;
3472 return intel_dp_detect_dpcd(intel_dp
);
3475 static struct edid
*
3476 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3478 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3480 /* use cached edid if we have one */
3481 if (intel_connector
->edid
) {
3483 if (IS_ERR(intel_connector
->edid
))
3486 return drm_edid_duplicate(intel_connector
->edid
);
3489 return drm_get_edid(connector
, adapter
);
3493 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3495 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3497 /* use cached edid if we have one */
3498 if (intel_connector
->edid
) {
3500 if (IS_ERR(intel_connector
->edid
))
3503 return intel_connector_update_modes(connector
,
3504 intel_connector
->edid
);
3507 return intel_ddc_get_modes(connector
, adapter
);
3510 static enum drm_connector_status
3511 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3513 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3514 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3515 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3516 struct drm_device
*dev
= connector
->dev
;
3517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3518 enum drm_connector_status status
;
3519 enum intel_display_power_domain power_domain
;
3520 struct edid
*edid
= NULL
;
3522 intel_runtime_pm_get(dev_priv
);
3524 power_domain
= intel_display_port_power_domain(intel_encoder
);
3525 intel_display_power_get(dev_priv
, power_domain
);
3527 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3528 connector
->base
.id
, connector
->name
);
3530 intel_dp
->has_audio
= false;
3532 if (HAS_PCH_SPLIT(dev
))
3533 status
= ironlake_dp_detect(intel_dp
);
3535 status
= g4x_dp_detect(intel_dp
);
3537 if (status
!= connector_status_connected
)
3540 intel_dp_probe_oui(intel_dp
);
3542 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3543 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3545 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3547 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3552 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3553 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3554 status
= connector_status_connected
;
3557 intel_display_power_put(dev_priv
, power_domain
);
3559 intel_runtime_pm_put(dev_priv
);
3564 static int intel_dp_get_modes(struct drm_connector
*connector
)
3566 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3567 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3568 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3569 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3570 struct drm_device
*dev
= connector
->dev
;
3571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3572 enum intel_display_power_domain power_domain
;
3575 /* We should parse the EDID data and find out if it has an audio sink
3578 power_domain
= intel_display_port_power_domain(intel_encoder
);
3579 intel_display_power_get(dev_priv
, power_domain
);
3581 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3582 intel_display_power_put(dev_priv
, power_domain
);
3586 /* if eDP has no EDID, fall back to fixed mode */
3587 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3588 struct drm_display_mode
*mode
;
3589 mode
= drm_mode_duplicate(dev
,
3590 intel_connector
->panel
.fixed_mode
);
3592 drm_mode_probed_add(connector
, mode
);
3600 intel_dp_detect_audio(struct drm_connector
*connector
)
3602 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3603 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3604 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3605 struct drm_device
*dev
= connector
->dev
;
3606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3607 enum intel_display_power_domain power_domain
;
3609 bool has_audio
= false;
3611 power_domain
= intel_display_port_power_domain(intel_encoder
);
3612 intel_display_power_get(dev_priv
, power_domain
);
3614 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3616 has_audio
= drm_detect_monitor_audio(edid
);
3620 intel_display_power_put(dev_priv
, power_domain
);
3626 intel_dp_set_property(struct drm_connector
*connector
,
3627 struct drm_property
*property
,
3630 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3631 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3632 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3633 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3636 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3640 if (property
== dev_priv
->force_audio_property
) {
3644 if (i
== intel_dp
->force_audio
)
3647 intel_dp
->force_audio
= i
;
3649 if (i
== HDMI_AUDIO_AUTO
)
3650 has_audio
= intel_dp_detect_audio(connector
);
3652 has_audio
= (i
== HDMI_AUDIO_ON
);
3654 if (has_audio
== intel_dp
->has_audio
)
3657 intel_dp
->has_audio
= has_audio
;
3661 if (property
== dev_priv
->broadcast_rgb_property
) {
3662 bool old_auto
= intel_dp
->color_range_auto
;
3663 uint32_t old_range
= intel_dp
->color_range
;
3666 case INTEL_BROADCAST_RGB_AUTO
:
3667 intel_dp
->color_range_auto
= true;
3669 case INTEL_BROADCAST_RGB_FULL
:
3670 intel_dp
->color_range_auto
= false;
3671 intel_dp
->color_range
= 0;
3673 case INTEL_BROADCAST_RGB_LIMITED
:
3674 intel_dp
->color_range_auto
= false;
3675 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3681 if (old_auto
== intel_dp
->color_range_auto
&&
3682 old_range
== intel_dp
->color_range
)
3688 if (is_edp(intel_dp
) &&
3689 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3690 if (val
== DRM_MODE_SCALE_NONE
) {
3691 DRM_DEBUG_KMS("no scaling not supported\n");
3695 if (intel_connector
->panel
.fitting_mode
== val
) {
3696 /* the eDP scaling property is not changed */
3699 intel_connector
->panel
.fitting_mode
= val
;
3707 if (intel_encoder
->base
.crtc
)
3708 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3714 intel_dp_connector_destroy(struct drm_connector
*connector
)
3716 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3718 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3719 kfree(intel_connector
->edid
);
3721 /* Can't call is_edp() since the encoder may have been destroyed
3723 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3724 intel_panel_fini(&intel_connector
->panel
);
3726 drm_connector_cleanup(connector
);
3730 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3732 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3733 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3734 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3736 drm_dp_aux_unregister(&intel_dp
->aux
);
3737 drm_encoder_cleanup(encoder
);
3738 if (is_edp(intel_dp
)) {
3739 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3740 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
3741 edp_panel_vdd_off_sync(intel_dp
);
3742 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
3743 if (intel_dp
->edp_notifier
.notifier_call
) {
3744 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
3745 intel_dp
->edp_notifier
.notifier_call
= NULL
;
3748 kfree(intel_dig_port
);
3751 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
3752 .dpms
= intel_connector_dpms
,
3753 .detect
= intel_dp_detect
,
3754 .fill_modes
= drm_helper_probe_single_connector_modes
,
3755 .set_property
= intel_dp_set_property
,
3756 .destroy
= intel_dp_connector_destroy
,
3759 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
3760 .get_modes
= intel_dp_get_modes
,
3761 .mode_valid
= intel_dp_mode_valid
,
3762 .best_encoder
= intel_best_encoder
,
3765 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
3766 .destroy
= intel_dp_encoder_destroy
,
3770 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
3772 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3774 intel_dp_check_link_status(intel_dp
);
3777 /* Return which DP Port should be selected for Transcoder DP control */
3779 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
3781 struct drm_device
*dev
= crtc
->dev
;
3782 struct intel_encoder
*intel_encoder
;
3783 struct intel_dp
*intel_dp
;
3785 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3786 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3788 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
3789 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
3790 return intel_dp
->output_reg
;
3796 /* check the VBT to see whether the eDP is on DP-D port */
3797 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
3799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3800 union child_device_config
*p_child
;
3802 static const short port_mapping
[] = {
3803 [PORT_B
] = PORT_IDPB
,
3804 [PORT_C
] = PORT_IDPC
,
3805 [PORT_D
] = PORT_IDPD
,
3811 if (!dev_priv
->vbt
.child_dev_num
)
3814 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
3815 p_child
= dev_priv
->vbt
.child_dev
+ i
;
3817 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
3818 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
3819 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
3826 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
3828 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3830 intel_attach_force_audio_property(connector
);
3831 intel_attach_broadcast_rgb_property(connector
);
3832 intel_dp
->color_range_auto
= true;
3834 if (is_edp(intel_dp
)) {
3835 drm_mode_create_scaling_mode_property(connector
->dev
);
3836 drm_object_attach_property(
3838 connector
->dev
->mode_config
.scaling_mode_property
,
3839 DRM_MODE_SCALE_ASPECT
);
3840 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
3844 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
3846 intel_dp
->last_power_cycle
= jiffies
;
3847 intel_dp
->last_power_on
= jiffies
;
3848 intel_dp
->last_backlight_off
= jiffies
;
3852 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
3853 struct intel_dp
*intel_dp
,
3854 struct edp_power_seq
*out
)
3856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3857 struct edp_power_seq cur
, vbt
, spec
, final
;
3858 u32 pp_on
, pp_off
, pp_div
, pp
;
3859 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
3861 if (HAS_PCH_SPLIT(dev
)) {
3862 pp_ctrl_reg
= PCH_PP_CONTROL
;
3863 pp_on_reg
= PCH_PP_ON_DELAYS
;
3864 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3865 pp_div_reg
= PCH_PP_DIVISOR
;
3867 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3869 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
3870 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3871 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3872 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3875 /* Workaround: Need to write PP_CONTROL with the unlock key as
3876 * the very first thing. */
3877 pp
= ironlake_get_pp_control(intel_dp
);
3878 I915_WRITE(pp_ctrl_reg
, pp
);
3880 pp_on
= I915_READ(pp_on_reg
);
3881 pp_off
= I915_READ(pp_off_reg
);
3882 pp_div
= I915_READ(pp_div_reg
);
3884 /* Pull timing values out of registers */
3885 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
3886 PANEL_POWER_UP_DELAY_SHIFT
;
3888 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
3889 PANEL_LIGHT_ON_DELAY_SHIFT
;
3891 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
3892 PANEL_LIGHT_OFF_DELAY_SHIFT
;
3894 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
3895 PANEL_POWER_DOWN_DELAY_SHIFT
;
3897 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
3898 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
3900 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3901 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
3903 vbt
= dev_priv
->vbt
.edp_pps
;
3905 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3906 * our hw here, which are all in 100usec. */
3907 spec
.t1_t3
= 210 * 10;
3908 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
3909 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
3910 spec
.t10
= 500 * 10;
3911 /* This one is special and actually in units of 100ms, but zero
3912 * based in the hw (so we need to add 100 ms). But the sw vbt
3913 * table multiplies it with 1000 to make it in units of 100usec,
3915 spec
.t11_t12
= (510 + 100) * 10;
3917 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3918 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
3920 /* Use the max of the register settings and vbt. If both are
3921 * unset, fall back to the spec limits. */
3922 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3924 max(cur.field, vbt.field))
3925 assign_final(t1_t3
);
3929 assign_final(t11_t12
);
3932 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3933 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
3934 intel_dp
->backlight_on_delay
= get_delay(t8
);
3935 intel_dp
->backlight_off_delay
= get_delay(t9
);
3936 intel_dp
->panel_power_down_delay
= get_delay(t10
);
3937 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
3940 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3941 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
3942 intel_dp
->panel_power_cycle_delay
);
3944 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3945 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
3952 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
3953 struct intel_dp
*intel_dp
,
3954 struct edp_power_seq
*seq
)
3956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3957 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
3958 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
3959 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
3961 if (HAS_PCH_SPLIT(dev
)) {
3962 pp_on_reg
= PCH_PP_ON_DELAYS
;
3963 pp_off_reg
= PCH_PP_OFF_DELAYS
;
3964 pp_div_reg
= PCH_PP_DIVISOR
;
3966 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
3968 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
3969 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
3970 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
3974 * And finally store the new values in the power sequencer. The
3975 * backlight delays are set to 1 because we do manual waits on them. For
3976 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3977 * we'll end up waiting for the backlight off delay twice: once when we
3978 * do the manual sleep, and once when we disable the panel and wait for
3979 * the PP_STATUS bit to become zero.
3981 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
3982 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
3983 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
3984 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
3985 /* Compute the divisor for the pp clock, simply match the Bspec
3987 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
3988 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
3989 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
3991 /* Haswell doesn't have any port selection bits for the panel
3992 * power sequencer any more. */
3993 if (IS_VALLEYVIEW(dev
)) {
3994 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
3995 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
3997 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
3998 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
3999 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
4000 port_sel
= PANEL_PORT_SELECT_DPA
;
4002 port_sel
= PANEL_PORT_SELECT_DPD
;
4007 I915_WRITE(pp_on_reg
, pp_on
);
4008 I915_WRITE(pp_off_reg
, pp_off
);
4009 I915_WRITE(pp_div_reg
, pp_div
);
4011 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4012 I915_READ(pp_on_reg
),
4013 I915_READ(pp_off_reg
),
4014 I915_READ(pp_div_reg
));
4017 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4020 struct intel_encoder
*encoder
;
4021 struct intel_dp
*intel_dp
= NULL
;
4022 struct intel_crtc_config
*config
= NULL
;
4023 struct intel_crtc
*intel_crtc
= NULL
;
4024 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4026 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4028 if (refresh_rate
<= 0) {
4029 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4033 if (intel_connector
== NULL
) {
4034 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4038 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4039 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4043 encoder
= intel_attached_encoder(&intel_connector
->base
);
4044 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4045 intel_crtc
= encoder
->new_crtc
;
4048 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4052 config
= &intel_crtc
->config
;
4054 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4055 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4059 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4060 index
= DRRS_LOW_RR
;
4062 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4064 "DRRS requested for previously set RR...ignoring\n");
4068 if (!intel_crtc
->active
) {
4069 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4073 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4074 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4075 val
= I915_READ(reg
);
4076 if (index
> DRRS_HIGH_RR
) {
4077 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4078 intel_dp_set_m2_n2(intel_crtc
, &config
->dp_m2_n2
);
4080 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4082 I915_WRITE(reg
, val
);
4086 * mutex taken to ensure that there is no race between differnt
4087 * drrs calls trying to update refresh rate. This scenario may occur
4088 * in future when idleness detection based DRRS in kernel and
4089 * possible calls from user space to set differnt RR are made.
4092 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4094 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4096 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4098 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4101 static struct drm_display_mode
*
4102 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4103 struct intel_connector
*intel_connector
,
4104 struct drm_display_mode
*fixed_mode
)
4106 struct drm_connector
*connector
= &intel_connector
->base
;
4107 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4108 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4110 struct drm_display_mode
*downclock_mode
= NULL
;
4112 if (INTEL_INFO(dev
)->gen
<= 6) {
4113 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4117 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4118 DRM_INFO("VBT doesn't support DRRS\n");
4122 downclock_mode
= intel_find_panel_downclock
4123 (dev
, fixed_mode
, connector
);
4125 if (!downclock_mode
) {
4126 DRM_INFO("DRRS not supported\n");
4130 dev_priv
->drrs
.connector
= intel_connector
;
4132 mutex_init(&intel_dp
->drrs_state
.mutex
);
4134 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4136 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4137 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4138 return downclock_mode
;
4141 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4142 struct intel_connector
*intel_connector
,
4143 struct edp_power_seq
*power_seq
)
4145 struct drm_connector
*connector
= &intel_connector
->base
;
4146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4147 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4148 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4150 struct drm_display_mode
*fixed_mode
= NULL
;
4151 struct drm_display_mode
*downclock_mode
= NULL
;
4153 struct drm_display_mode
*scan
;
4156 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4158 if (!is_edp(intel_dp
))
4161 /* The VDD bit needs a power domain reference, so if the bit is already
4162 * enabled when we boot, grab this reference. */
4163 if (edp_have_panel_vdd(intel_dp
)) {
4164 enum intel_display_power_domain power_domain
;
4165 power_domain
= intel_display_port_power_domain(intel_encoder
);
4166 intel_display_power_get(dev_priv
, power_domain
);
4169 /* Cache DPCD and EDID for edp. */
4170 intel_edp_panel_vdd_on(intel_dp
);
4171 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4172 edp_panel_vdd_off(intel_dp
, false);
4175 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4176 dev_priv
->no_aux_handshake
=
4177 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4178 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4180 /* if this fails, presume the device is a ghost */
4181 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4185 /* We now know it's not a ghost, init power sequence regs. */
4186 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4188 mutex_lock(&dev
->mode_config
.mutex
);
4189 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4191 if (drm_add_edid_modes(connector
, edid
)) {
4192 drm_mode_connector_update_edid_property(connector
,
4194 drm_edid_to_eld(connector
, edid
);
4197 edid
= ERR_PTR(-EINVAL
);
4200 edid
= ERR_PTR(-ENOENT
);
4202 intel_connector
->edid
= edid
;
4204 /* prefer fixed mode from EDID if available */
4205 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4206 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4207 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4208 downclock_mode
= intel_dp_drrs_init(
4210 intel_connector
, fixed_mode
);
4215 /* fallback to VBT if available for eDP */
4216 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4217 fixed_mode
= drm_mode_duplicate(dev
,
4218 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4220 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4222 mutex_unlock(&dev
->mode_config
.mutex
);
4224 if (IS_VALLEYVIEW(dev
)) {
4225 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
4226 register_reboot_notifier(&intel_dp
->edp_notifier
);
4229 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4230 intel_panel_setup_backlight(connector
);
4236 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4237 struct intel_connector
*intel_connector
)
4239 struct drm_connector
*connector
= &intel_connector
->base
;
4240 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4241 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4242 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4244 enum port port
= intel_dig_port
->port
;
4245 struct edp_power_seq power_seq
= { 0 };
4248 /* intel_dp vfuncs */
4249 if (IS_VALLEYVIEW(dev
))
4250 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
4251 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4252 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
4253 else if (HAS_PCH_SPLIT(dev
))
4254 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
4256 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
4258 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
4260 /* Preserve the current hw state. */
4261 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4262 intel_dp
->attached_connector
= intel_connector
;
4264 if (intel_dp_is_edp(dev
, port
))
4265 type
= DRM_MODE_CONNECTOR_eDP
;
4267 type
= DRM_MODE_CONNECTOR_DisplayPort
;
4270 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4271 * for DP the encoder type can be set by the caller to
4272 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4274 if (type
== DRM_MODE_CONNECTOR_eDP
)
4275 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
4277 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4278 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
4281 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
4282 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
4284 connector
->interlace_allowed
= true;
4285 connector
->doublescan_allowed
= 0;
4287 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
4288 edp_panel_vdd_work
);
4290 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
4291 drm_sysfs_connector_add(connector
);
4294 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
4296 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
4297 intel_connector
->unregister
= intel_dp_connector_unregister
;
4299 /* Set up the hotplug pin. */
4302 intel_encoder
->hpd_pin
= HPD_PORT_A
;
4305 intel_encoder
->hpd_pin
= HPD_PORT_B
;
4308 intel_encoder
->hpd_pin
= HPD_PORT_C
;
4311 intel_encoder
->hpd_pin
= HPD_PORT_D
;
4317 if (is_edp(intel_dp
)) {
4318 intel_dp_init_panel_power_timestamps(intel_dp
);
4319 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
4322 intel_dp_aux_init(intel_dp
, intel_connector
);
4324 intel_dp
->psr_setup_done
= false;
4326 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
4327 drm_dp_aux_unregister(&intel_dp
->aux
);
4328 if (is_edp(intel_dp
)) {
4329 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4330 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4331 edp_panel_vdd_off_sync(intel_dp
);
4332 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4334 drm_sysfs_connector_remove(connector
);
4335 drm_connector_cleanup(connector
);
4339 intel_dp_add_properties(intel_dp
, connector
);
4341 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4342 * 0xd. Failure to do so will result in spurious interrupts being
4343 * generated on the port when a cable is not attached.
4345 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
4346 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
4347 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
4354 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
4356 struct intel_digital_port
*intel_dig_port
;
4357 struct intel_encoder
*intel_encoder
;
4358 struct drm_encoder
*encoder
;
4359 struct intel_connector
*intel_connector
;
4361 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
4362 if (!intel_dig_port
)
4365 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
4366 if (!intel_connector
) {
4367 kfree(intel_dig_port
);
4371 intel_encoder
= &intel_dig_port
->base
;
4372 encoder
= &intel_encoder
->base
;
4374 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
4375 DRM_MODE_ENCODER_TMDS
);
4377 intel_encoder
->compute_config
= intel_dp_compute_config
;
4378 intel_encoder
->disable
= intel_disable_dp
;
4379 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
4380 intel_encoder
->get_config
= intel_dp_get_config
;
4381 if (IS_CHERRYVIEW(dev
)) {
4382 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
4383 intel_encoder
->enable
= vlv_enable_dp
;
4384 intel_encoder
->post_disable
= chv_post_disable_dp
;
4385 } else if (IS_VALLEYVIEW(dev
)) {
4386 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
4387 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
4388 intel_encoder
->enable
= vlv_enable_dp
;
4389 intel_encoder
->post_disable
= vlv_post_disable_dp
;
4391 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
4392 intel_encoder
->enable
= g4x_enable_dp
;
4393 intel_encoder
->post_disable
= g4x_post_disable_dp
;
4396 intel_dig_port
->port
= port
;
4397 intel_dig_port
->dp
.output_reg
= output_reg
;
4399 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4400 if (IS_CHERRYVIEW(dev
)) {
4402 intel_encoder
->crtc_mask
= 1 << 2;
4404 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
4406 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
4408 intel_encoder
->cloneable
= 0;
4409 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4411 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4412 drm_encoder_cleanup(encoder
);
4413 kfree(intel_dig_port
);
4414 kfree(intel_connector
);