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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_STATUS_SIZE 6
40 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
41
42 /**
43 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
44 * @intel_dp: DP struct
45 *
46 * If a CPU or PCH DP output is attached to an eDP panel, this function
47 * will return true, and false otherwise.
48 */
49 static bool is_edp(struct intel_dp *intel_dp)
50 {
51 return intel_dp->base.type == INTEL_OUTPUT_EDP;
52 }
53
54 /**
55 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
56 * @intel_dp: DP struct
57 *
58 * Returns true if the given DP struct corresponds to a PCH DP port attached
59 * to an eDP panel, false otherwise. Helpful for determining whether we
60 * may need FDI resources for a given DP output or not.
61 */
62 static bool is_pch_edp(struct intel_dp *intel_dp)
63 {
64 return intel_dp->is_pch_edp;
65 }
66
67 /**
68 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
69 * @intel_dp: DP struct
70 *
71 * Returns true if the given DP struct corresponds to a CPU eDP port.
72 */
73 static bool is_cpu_edp(struct intel_dp *intel_dp)
74 {
75 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
76 }
77
78 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
79 {
80 return container_of(encoder, struct intel_dp, base.base);
81 }
82
83 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
84 {
85 return container_of(intel_attached_encoder(connector),
86 struct intel_dp, base);
87 }
88
89 /**
90 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
91 * @encoder: DRM encoder
92 *
93 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
94 * by intel_display.c.
95 */
96 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
97 {
98 struct intel_dp *intel_dp;
99
100 if (!encoder)
101 return false;
102
103 intel_dp = enc_to_intel_dp(encoder);
104
105 return is_pch_edp(intel_dp);
106 }
107
108 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
109 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
110 static void intel_dp_link_down(struct intel_dp *intel_dp);
111
112 void
113 intel_edp_link_config(struct intel_encoder *intel_encoder,
114 int *lane_num, int *link_bw)
115 {
116 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
117
118 *lane_num = intel_dp->lane_count;
119 if (intel_dp->link_bw == DP_LINK_BW_1_62)
120 *link_bw = 162000;
121 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
122 *link_bw = 270000;
123 }
124
125 int
126 intel_edp_target_clock(struct intel_encoder *intel_encoder,
127 struct drm_display_mode *mode)
128 {
129 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
130
131 if (intel_dp->panel_fixed_mode)
132 return intel_dp->panel_fixed_mode->clock;
133 else
134 return mode->clock;
135 }
136
137 static int
138 intel_dp_max_lane_count(struct intel_dp *intel_dp)
139 {
140 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
141 switch (max_lane_count) {
142 case 1: case 2: case 4:
143 break;
144 default:
145 max_lane_count = 4;
146 }
147 return max_lane_count;
148 }
149
150 static int
151 intel_dp_max_link_bw(struct intel_dp *intel_dp)
152 {
153 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
154
155 switch (max_link_bw) {
156 case DP_LINK_BW_1_62:
157 case DP_LINK_BW_2_7:
158 break;
159 default:
160 max_link_bw = DP_LINK_BW_1_62;
161 break;
162 }
163 return max_link_bw;
164 }
165
166 static int
167 intel_dp_link_clock(uint8_t link_bw)
168 {
169 if (link_bw == DP_LINK_BW_2_7)
170 return 270000;
171 else
172 return 162000;
173 }
174
175 /*
176 * The units on the numbers in the next two are... bizarre. Examples will
177 * make it clearer; this one parallels an example in the eDP spec.
178 *
179 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
180 *
181 * 270000 * 1 * 8 / 10 == 216000
182 *
183 * The actual data capacity of that configuration is 2.16Gbit/s, so the
184 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
185 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
186 * 119000. At 18bpp that's 2142000 kilobits per second.
187 *
188 * Thus the strange-looking division by 10 in intel_dp_link_required, to
189 * get the result in decakilobits instead of kilobits.
190 */
191
192 static int
193 intel_dp_link_required(int pixel_clock, int bpp)
194 {
195 return (pixel_clock * bpp + 9) / 10;
196 }
197
198 static int
199 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
200 {
201 return (max_link_clock * max_lanes * 8) / 10;
202 }
203
204 static bool
205 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
206 struct drm_display_mode *mode,
207 bool adjust_mode)
208 {
209 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
210 int max_lanes = intel_dp_max_lane_count(intel_dp);
211 int max_rate, mode_rate;
212
213 mode_rate = intel_dp_link_required(mode->clock, 24);
214 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
215
216 if (mode_rate > max_rate) {
217 mode_rate = intel_dp_link_required(mode->clock, 18);
218 if (mode_rate > max_rate)
219 return false;
220
221 if (adjust_mode)
222 mode->private_flags
223 |= INTEL_MODE_DP_FORCE_6BPC;
224
225 return true;
226 }
227
228 return true;
229 }
230
231 static int
232 intel_dp_mode_valid(struct drm_connector *connector,
233 struct drm_display_mode *mode)
234 {
235 struct intel_dp *intel_dp = intel_attached_dp(connector);
236
237 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
238 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
239 return MODE_PANEL;
240
241 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
242 return MODE_PANEL;
243 }
244
245 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
246 return MODE_CLOCK_HIGH;
247
248 if (mode->clock < 10000)
249 return MODE_CLOCK_LOW;
250
251 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
252 return MODE_H_ILLEGAL;
253
254 return MODE_OK;
255 }
256
257 static uint32_t
258 pack_aux(uint8_t *src, int src_bytes)
259 {
260 int i;
261 uint32_t v = 0;
262
263 if (src_bytes > 4)
264 src_bytes = 4;
265 for (i = 0; i < src_bytes; i++)
266 v |= ((uint32_t) src[i]) << ((3-i) * 8);
267 return v;
268 }
269
270 static void
271 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
272 {
273 int i;
274 if (dst_bytes > 4)
275 dst_bytes = 4;
276 for (i = 0; i < dst_bytes; i++)
277 dst[i] = src >> ((3-i) * 8);
278 }
279
280 /* hrawclock is 1/4 the FSB frequency */
281 static int
282 intel_hrawclk(struct drm_device *dev)
283 {
284 struct drm_i915_private *dev_priv = dev->dev_private;
285 uint32_t clkcfg;
286
287 clkcfg = I915_READ(CLKCFG);
288 switch (clkcfg & CLKCFG_FSB_MASK) {
289 case CLKCFG_FSB_400:
290 return 100;
291 case CLKCFG_FSB_533:
292 return 133;
293 case CLKCFG_FSB_667:
294 return 166;
295 case CLKCFG_FSB_800:
296 return 200;
297 case CLKCFG_FSB_1067:
298 return 266;
299 case CLKCFG_FSB_1333:
300 return 333;
301 /* these two are just a guess; one of them might be right */
302 case CLKCFG_FSB_1600:
303 case CLKCFG_FSB_1600_ALT:
304 return 400;
305 default:
306 return 133;
307 }
308 }
309
310 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
311 {
312 struct drm_device *dev = intel_dp->base.base.dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314
315 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
316 }
317
318 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
319 {
320 struct drm_device *dev = intel_dp->base.base.dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
322
323 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
324 }
325
326 static void
327 intel_dp_check_edp(struct intel_dp *intel_dp)
328 {
329 struct drm_device *dev = intel_dp->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331
332 if (!is_edp(intel_dp))
333 return;
334 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
335 WARN(1, "eDP powered off while attempting aux channel communication.\n");
336 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
337 I915_READ(PCH_PP_STATUS),
338 I915_READ(PCH_PP_CONTROL));
339 }
340 }
341
342 static int
343 intel_dp_aux_ch(struct intel_dp *intel_dp,
344 uint8_t *send, int send_bytes,
345 uint8_t *recv, int recv_size)
346 {
347 uint32_t output_reg = intel_dp->output_reg;
348 struct drm_device *dev = intel_dp->base.base.dev;
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 uint32_t ch_ctl = output_reg + 0x10;
351 uint32_t ch_data = ch_ctl + 4;
352 int i;
353 int recv_bytes;
354 uint32_t status;
355 uint32_t aux_clock_divider;
356 int try, precharge;
357
358 intel_dp_check_edp(intel_dp);
359 /* The clock divider is based off the hrawclk,
360 * and would like to run at 2MHz. So, take the
361 * hrawclk value and divide by 2 and use that
362 *
363 * Note that PCH attached eDP panels should use a 125MHz input
364 * clock divider.
365 */
366 if (is_cpu_edp(intel_dp)) {
367 if (IS_GEN6(dev) || IS_GEN7(dev))
368 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
369 else
370 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
371 } else if (HAS_PCH_SPLIT(dev))
372 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
373 else
374 aux_clock_divider = intel_hrawclk(dev) / 2;
375
376 if (IS_GEN6(dev))
377 precharge = 3;
378 else
379 precharge = 5;
380
381 /* Try to wait for any previous AUX channel activity */
382 for (try = 0; try < 3; try++) {
383 status = I915_READ(ch_ctl);
384 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
385 break;
386 msleep(1);
387 }
388
389 if (try == 3) {
390 WARN(1, "dp_aux_ch not started status 0x%08x\n",
391 I915_READ(ch_ctl));
392 return -EBUSY;
393 }
394
395 /* Must try at least 3 times according to DP spec */
396 for (try = 0; try < 5; try++) {
397 /* Load the send data into the aux channel data registers */
398 for (i = 0; i < send_bytes; i += 4)
399 I915_WRITE(ch_data + i,
400 pack_aux(send + i, send_bytes - i));
401
402 /* Send the command and wait for it to complete */
403 I915_WRITE(ch_ctl,
404 DP_AUX_CH_CTL_SEND_BUSY |
405 DP_AUX_CH_CTL_TIME_OUT_400us |
406 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
407 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
408 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
409 DP_AUX_CH_CTL_DONE |
410 DP_AUX_CH_CTL_TIME_OUT_ERROR |
411 DP_AUX_CH_CTL_RECEIVE_ERROR);
412 for (;;) {
413 status = I915_READ(ch_ctl);
414 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
415 break;
416 udelay(100);
417 }
418
419 /* Clear done status and any errors */
420 I915_WRITE(ch_ctl,
421 status |
422 DP_AUX_CH_CTL_DONE |
423 DP_AUX_CH_CTL_TIME_OUT_ERROR |
424 DP_AUX_CH_CTL_RECEIVE_ERROR);
425
426 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
427 DP_AUX_CH_CTL_RECEIVE_ERROR))
428 continue;
429 if (status & DP_AUX_CH_CTL_DONE)
430 break;
431 }
432
433 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
434 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
435 return -EBUSY;
436 }
437
438 /* Check for timeout or receive error.
439 * Timeouts occur when the sink is not connected
440 */
441 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
442 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
443 return -EIO;
444 }
445
446 /* Timeouts occur when the device isn't connected, so they're
447 * "normal" -- don't fill the kernel log with these */
448 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
449 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
450 return -ETIMEDOUT;
451 }
452
453 /* Unload any bytes sent back from the other side */
454 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
455 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
456 if (recv_bytes > recv_size)
457 recv_bytes = recv_size;
458
459 for (i = 0; i < recv_bytes; i += 4)
460 unpack_aux(I915_READ(ch_data + i),
461 recv + i, recv_bytes - i);
462
463 return recv_bytes;
464 }
465
466 /* Write data to the aux channel in native mode */
467 static int
468 intel_dp_aux_native_write(struct intel_dp *intel_dp,
469 uint16_t address, uint8_t *send, int send_bytes)
470 {
471 int ret;
472 uint8_t msg[20];
473 int msg_bytes;
474 uint8_t ack;
475
476 intel_dp_check_edp(intel_dp);
477 if (send_bytes > 16)
478 return -1;
479 msg[0] = AUX_NATIVE_WRITE << 4;
480 msg[1] = address >> 8;
481 msg[2] = address & 0xff;
482 msg[3] = send_bytes - 1;
483 memcpy(&msg[4], send, send_bytes);
484 msg_bytes = send_bytes + 4;
485 for (;;) {
486 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
487 if (ret < 0)
488 return ret;
489 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
490 break;
491 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
492 udelay(100);
493 else
494 return -EIO;
495 }
496 return send_bytes;
497 }
498
499 /* Write a single byte to the aux channel in native mode */
500 static int
501 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
502 uint16_t address, uint8_t byte)
503 {
504 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
505 }
506
507 /* read bytes from a native aux channel */
508 static int
509 intel_dp_aux_native_read(struct intel_dp *intel_dp,
510 uint16_t address, uint8_t *recv, int recv_bytes)
511 {
512 uint8_t msg[4];
513 int msg_bytes;
514 uint8_t reply[20];
515 int reply_bytes;
516 uint8_t ack;
517 int ret;
518
519 intel_dp_check_edp(intel_dp);
520 msg[0] = AUX_NATIVE_READ << 4;
521 msg[1] = address >> 8;
522 msg[2] = address & 0xff;
523 msg[3] = recv_bytes - 1;
524
525 msg_bytes = 4;
526 reply_bytes = recv_bytes + 1;
527
528 for (;;) {
529 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
530 reply, reply_bytes);
531 if (ret == 0)
532 return -EPROTO;
533 if (ret < 0)
534 return ret;
535 ack = reply[0];
536 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
537 memcpy(recv, reply + 1, ret - 1);
538 return ret - 1;
539 }
540 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
541 udelay(100);
542 else
543 return -EIO;
544 }
545 }
546
547 static int
548 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
549 uint8_t write_byte, uint8_t *read_byte)
550 {
551 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
552 struct intel_dp *intel_dp = container_of(adapter,
553 struct intel_dp,
554 adapter);
555 uint16_t address = algo_data->address;
556 uint8_t msg[5];
557 uint8_t reply[2];
558 unsigned retry;
559 int msg_bytes;
560 int reply_bytes;
561 int ret;
562
563 intel_dp_check_edp(intel_dp);
564 /* Set up the command byte */
565 if (mode & MODE_I2C_READ)
566 msg[0] = AUX_I2C_READ << 4;
567 else
568 msg[0] = AUX_I2C_WRITE << 4;
569
570 if (!(mode & MODE_I2C_STOP))
571 msg[0] |= AUX_I2C_MOT << 4;
572
573 msg[1] = address >> 8;
574 msg[2] = address;
575
576 switch (mode) {
577 case MODE_I2C_WRITE:
578 msg[3] = 0;
579 msg[4] = write_byte;
580 msg_bytes = 5;
581 reply_bytes = 1;
582 break;
583 case MODE_I2C_READ:
584 msg[3] = 0;
585 msg_bytes = 4;
586 reply_bytes = 2;
587 break;
588 default:
589 msg_bytes = 3;
590 reply_bytes = 1;
591 break;
592 }
593
594 for (retry = 0; retry < 5; retry++) {
595 ret = intel_dp_aux_ch(intel_dp,
596 msg, msg_bytes,
597 reply, reply_bytes);
598 if (ret < 0) {
599 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
600 return ret;
601 }
602
603 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
604 case AUX_NATIVE_REPLY_ACK:
605 /* I2C-over-AUX Reply field is only valid
606 * when paired with AUX ACK.
607 */
608 break;
609 case AUX_NATIVE_REPLY_NACK:
610 DRM_DEBUG_KMS("aux_ch native nack\n");
611 return -EREMOTEIO;
612 case AUX_NATIVE_REPLY_DEFER:
613 udelay(100);
614 continue;
615 default:
616 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
617 reply[0]);
618 return -EREMOTEIO;
619 }
620
621 switch (reply[0] & AUX_I2C_REPLY_MASK) {
622 case AUX_I2C_REPLY_ACK:
623 if (mode == MODE_I2C_READ) {
624 *read_byte = reply[1];
625 }
626 return reply_bytes - 1;
627 case AUX_I2C_REPLY_NACK:
628 DRM_DEBUG_KMS("aux_i2c nack\n");
629 return -EREMOTEIO;
630 case AUX_I2C_REPLY_DEFER:
631 DRM_DEBUG_KMS("aux_i2c defer\n");
632 udelay(100);
633 break;
634 default:
635 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
636 return -EREMOTEIO;
637 }
638 }
639
640 DRM_ERROR("too many retries, giving up\n");
641 return -EREMOTEIO;
642 }
643
644 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
645 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
646
647 static int
648 intel_dp_i2c_init(struct intel_dp *intel_dp,
649 struct intel_connector *intel_connector, const char *name)
650 {
651 int ret;
652
653 DRM_DEBUG_KMS("i2c_init %s\n", name);
654 intel_dp->algo.running = false;
655 intel_dp->algo.address = 0;
656 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
657
658 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
659 intel_dp->adapter.owner = THIS_MODULE;
660 intel_dp->adapter.class = I2C_CLASS_DDC;
661 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
662 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
663 intel_dp->adapter.algo_data = &intel_dp->algo;
664 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
665
666 ironlake_edp_panel_vdd_on(intel_dp);
667 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
668 ironlake_edp_panel_vdd_off(intel_dp, false);
669 return ret;
670 }
671
672 static bool
673 intel_dp_mode_fixup(struct drm_encoder *encoder,
674 const struct drm_display_mode *mode,
675 struct drm_display_mode *adjusted_mode)
676 {
677 struct drm_device *dev = encoder->dev;
678 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
679 int lane_count, clock;
680 int max_lane_count = intel_dp_max_lane_count(intel_dp);
681 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
682 int bpp, mode_rate;
683 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
684
685 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
686 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
687 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
688 mode, adjusted_mode);
689 }
690
691 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
692 return false;
693
694 DRM_DEBUG_KMS("DP link computation with max lane count %i "
695 "max bw %02x pixel clock %iKHz\n",
696 max_lane_count, bws[max_clock], adjusted_mode->clock);
697
698 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
699 return false;
700
701 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
702 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
703
704 for (clock = 0; clock <= max_clock; clock++) {
705 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
706 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
707
708 if (mode_rate <= link_avail) {
709 intel_dp->link_bw = bws[clock];
710 intel_dp->lane_count = lane_count;
711 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
712 DRM_DEBUG_KMS("DP link bw %02x lane "
713 "count %d clock %d bpp %d\n",
714 intel_dp->link_bw, intel_dp->lane_count,
715 adjusted_mode->clock, bpp);
716 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
717 mode_rate, link_avail);
718 return true;
719 }
720 }
721 }
722
723 return false;
724 }
725
726 struct intel_dp_m_n {
727 uint32_t tu;
728 uint32_t gmch_m;
729 uint32_t gmch_n;
730 uint32_t link_m;
731 uint32_t link_n;
732 };
733
734 static void
735 intel_reduce_ratio(uint32_t *num, uint32_t *den)
736 {
737 while (*num > 0xffffff || *den > 0xffffff) {
738 *num >>= 1;
739 *den >>= 1;
740 }
741 }
742
743 static void
744 intel_dp_compute_m_n(int bpp,
745 int nlanes,
746 int pixel_clock,
747 int link_clock,
748 struct intel_dp_m_n *m_n)
749 {
750 m_n->tu = 64;
751 m_n->gmch_m = (pixel_clock * bpp) >> 3;
752 m_n->gmch_n = link_clock * nlanes;
753 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
754 m_n->link_m = pixel_clock;
755 m_n->link_n = link_clock;
756 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
757 }
758
759 void
760 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
761 struct drm_display_mode *adjusted_mode)
762 {
763 struct drm_device *dev = crtc->dev;
764 struct intel_encoder *encoder;
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
767 int lane_count = 4;
768 struct intel_dp_m_n m_n;
769 int pipe = intel_crtc->pipe;
770
771 /*
772 * Find the lane count in the intel_encoder private
773 */
774 for_each_encoder_on_crtc(dev, crtc, encoder) {
775 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
776
777 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
778 intel_dp->base.type == INTEL_OUTPUT_EDP)
779 {
780 lane_count = intel_dp->lane_count;
781 break;
782 }
783 }
784
785 /*
786 * Compute the GMCH and Link ratios. The '3' here is
787 * the number of bytes_per_pixel post-LUT, which we always
788 * set up for 8-bits of R/G/B, or 3 bytes total.
789 */
790 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
791 mode->clock, adjusted_mode->clock, &m_n);
792
793 if (HAS_PCH_SPLIT(dev)) {
794 I915_WRITE(TRANSDATA_M1(pipe),
795 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
796 m_n.gmch_m);
797 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
798 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
799 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
800 } else {
801 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
802 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
803 m_n.gmch_m);
804 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
805 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
806 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
807 }
808 }
809
810 static void
811 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode)
813 {
814 struct drm_device *dev = encoder->dev;
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
817 struct drm_crtc *crtc = intel_dp->base.base.crtc;
818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
819
820 /*
821 * There are four kinds of DP registers:
822 *
823 * IBX PCH
824 * SNB CPU
825 * IVB CPU
826 * CPT PCH
827 *
828 * IBX PCH and CPU are the same for almost everything,
829 * except that the CPU DP PLL is configured in this
830 * register
831 *
832 * CPT PCH is quite different, having many bits moved
833 * to the TRANS_DP_CTL register instead. That
834 * configuration happens (oddly) in ironlake_pch_enable
835 */
836
837 /* Preserve the BIOS-computed detected bit. This is
838 * supposed to be read-only.
839 */
840 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
841
842 /* Handle DP bits in common between all three register formats */
843 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
844
845 switch (intel_dp->lane_count) {
846 case 1:
847 intel_dp->DP |= DP_PORT_WIDTH_1;
848 break;
849 case 2:
850 intel_dp->DP |= DP_PORT_WIDTH_2;
851 break;
852 case 4:
853 intel_dp->DP |= DP_PORT_WIDTH_4;
854 break;
855 }
856 if (intel_dp->has_audio) {
857 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
858 pipe_name(intel_crtc->pipe));
859 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
860 intel_write_eld(encoder, adjusted_mode);
861 }
862 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
863 intel_dp->link_configuration[0] = intel_dp->link_bw;
864 intel_dp->link_configuration[1] = intel_dp->lane_count;
865 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
866 /*
867 * Check for DPCD version > 1.1 and enhanced framing support
868 */
869 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
870 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
871 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
872 }
873
874 /* Split out the IBX/CPU vs CPT settings */
875
876 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
877 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
878 intel_dp->DP |= DP_SYNC_HS_HIGH;
879 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
880 intel_dp->DP |= DP_SYNC_VS_HIGH;
881 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
882
883 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
884 intel_dp->DP |= DP_ENHANCED_FRAMING;
885
886 intel_dp->DP |= intel_crtc->pipe << 29;
887
888 /* don't miss out required setting for eDP */
889 if (adjusted_mode->clock < 200000)
890 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
891 else
892 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
893 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
894 intel_dp->DP |= intel_dp->color_range;
895
896 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
897 intel_dp->DP |= DP_SYNC_HS_HIGH;
898 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
899 intel_dp->DP |= DP_SYNC_VS_HIGH;
900 intel_dp->DP |= DP_LINK_TRAIN_OFF;
901
902 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
903 intel_dp->DP |= DP_ENHANCED_FRAMING;
904
905 if (intel_crtc->pipe == 1)
906 intel_dp->DP |= DP_PIPEB_SELECT;
907
908 if (is_cpu_edp(intel_dp)) {
909 /* don't miss out required setting for eDP */
910 if (adjusted_mode->clock < 200000)
911 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
912 else
913 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
914 }
915 } else {
916 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
917 }
918 }
919
920 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
921 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
922
923 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
924 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
925
926 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
927 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
928
929 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
930 u32 mask,
931 u32 value)
932 {
933 struct drm_device *dev = intel_dp->base.base.dev;
934 struct drm_i915_private *dev_priv = dev->dev_private;
935
936 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
937 mask, value,
938 I915_READ(PCH_PP_STATUS),
939 I915_READ(PCH_PP_CONTROL));
940
941 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
942 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
943 I915_READ(PCH_PP_STATUS),
944 I915_READ(PCH_PP_CONTROL));
945 }
946 }
947
948 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
949 {
950 DRM_DEBUG_KMS("Wait for panel power on\n");
951 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
952 }
953
954 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
955 {
956 DRM_DEBUG_KMS("Wait for panel power off time\n");
957 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
958 }
959
960 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
961 {
962 DRM_DEBUG_KMS("Wait for panel power cycle\n");
963 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
964 }
965
966
967 /* Read the current pp_control value, unlocking the register if it
968 * is locked
969 */
970
971 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
972 {
973 u32 control = I915_READ(PCH_PP_CONTROL);
974
975 control &= ~PANEL_UNLOCK_MASK;
976 control |= PANEL_UNLOCK_REGS;
977 return control;
978 }
979
980 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
981 {
982 struct drm_device *dev = intel_dp->base.base.dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 u32 pp;
985
986 if (!is_edp(intel_dp))
987 return;
988 DRM_DEBUG_KMS("Turn eDP VDD on\n");
989
990 WARN(intel_dp->want_panel_vdd,
991 "eDP VDD already requested on\n");
992
993 intel_dp->want_panel_vdd = true;
994
995 if (ironlake_edp_have_panel_vdd(intel_dp)) {
996 DRM_DEBUG_KMS("eDP VDD already on\n");
997 return;
998 }
999
1000 if (!ironlake_edp_have_panel_power(intel_dp))
1001 ironlake_wait_panel_power_cycle(intel_dp);
1002
1003 pp = ironlake_get_pp_control(dev_priv);
1004 pp |= EDP_FORCE_VDD;
1005 I915_WRITE(PCH_PP_CONTROL, pp);
1006 POSTING_READ(PCH_PP_CONTROL);
1007 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1008 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1009
1010 /*
1011 * If the panel wasn't on, delay before accessing aux channel
1012 */
1013 if (!ironlake_edp_have_panel_power(intel_dp)) {
1014 DRM_DEBUG_KMS("eDP was not running\n");
1015 msleep(intel_dp->panel_power_up_delay);
1016 }
1017 }
1018
1019 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1020 {
1021 struct drm_device *dev = intel_dp->base.base.dev;
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 pp;
1024
1025 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1026 pp = ironlake_get_pp_control(dev_priv);
1027 pp &= ~EDP_FORCE_VDD;
1028 I915_WRITE(PCH_PP_CONTROL, pp);
1029 POSTING_READ(PCH_PP_CONTROL);
1030
1031 /* Make sure sequencer is idle before allowing subsequent activity */
1032 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1033 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1034
1035 msleep(intel_dp->panel_power_down_delay);
1036 }
1037 }
1038
1039 static void ironlake_panel_vdd_work(struct work_struct *__work)
1040 {
1041 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1042 struct intel_dp, panel_vdd_work);
1043 struct drm_device *dev = intel_dp->base.base.dev;
1044
1045 mutex_lock(&dev->mode_config.mutex);
1046 ironlake_panel_vdd_off_sync(intel_dp);
1047 mutex_unlock(&dev->mode_config.mutex);
1048 }
1049
1050 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1051 {
1052 if (!is_edp(intel_dp))
1053 return;
1054
1055 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1056 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1057
1058 intel_dp->want_panel_vdd = false;
1059
1060 if (sync) {
1061 ironlake_panel_vdd_off_sync(intel_dp);
1062 } else {
1063 /*
1064 * Queue the timer to fire a long
1065 * time from now (relative to the power down delay)
1066 * to keep the panel power up across a sequence of operations
1067 */
1068 schedule_delayed_work(&intel_dp->panel_vdd_work,
1069 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1070 }
1071 }
1072
1073 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1074 {
1075 struct drm_device *dev = intel_dp->base.base.dev;
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 u32 pp;
1078
1079 if (!is_edp(intel_dp))
1080 return;
1081
1082 DRM_DEBUG_KMS("Turn eDP power on\n");
1083
1084 if (ironlake_edp_have_panel_power(intel_dp)) {
1085 DRM_DEBUG_KMS("eDP power already on\n");
1086 return;
1087 }
1088
1089 ironlake_wait_panel_power_cycle(intel_dp);
1090
1091 pp = ironlake_get_pp_control(dev_priv);
1092 if (IS_GEN5(dev)) {
1093 /* ILK workaround: disable reset around power sequence */
1094 pp &= ~PANEL_POWER_RESET;
1095 I915_WRITE(PCH_PP_CONTROL, pp);
1096 POSTING_READ(PCH_PP_CONTROL);
1097 }
1098
1099 pp |= POWER_TARGET_ON;
1100 if (!IS_GEN5(dev))
1101 pp |= PANEL_POWER_RESET;
1102
1103 I915_WRITE(PCH_PP_CONTROL, pp);
1104 POSTING_READ(PCH_PP_CONTROL);
1105
1106 ironlake_wait_panel_on(intel_dp);
1107
1108 if (IS_GEN5(dev)) {
1109 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1110 I915_WRITE(PCH_PP_CONTROL, pp);
1111 POSTING_READ(PCH_PP_CONTROL);
1112 }
1113 }
1114
1115 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1116 {
1117 struct drm_device *dev = intel_dp->base.base.dev;
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 u32 pp;
1120
1121 if (!is_edp(intel_dp))
1122 return;
1123
1124 DRM_DEBUG_KMS("Turn eDP power off\n");
1125
1126 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1127
1128 pp = ironlake_get_pp_control(dev_priv);
1129 /* We need to switch off panel power _and_ force vdd, for otherwise some
1130 * panels get very unhappy and cease to work. */
1131 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1132 I915_WRITE(PCH_PP_CONTROL, pp);
1133 POSTING_READ(PCH_PP_CONTROL);
1134
1135 intel_dp->want_panel_vdd = false;
1136
1137 ironlake_wait_panel_off(intel_dp);
1138 }
1139
1140 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1141 {
1142 struct drm_device *dev = intel_dp->base.base.dev;
1143 struct drm_i915_private *dev_priv = dev->dev_private;
1144 u32 pp;
1145
1146 if (!is_edp(intel_dp))
1147 return;
1148
1149 DRM_DEBUG_KMS("\n");
1150 /*
1151 * If we enable the backlight right away following a panel power
1152 * on, we may see slight flicker as the panel syncs with the eDP
1153 * link. So delay a bit to make sure the image is solid before
1154 * allowing it to appear.
1155 */
1156 msleep(intel_dp->backlight_on_delay);
1157 pp = ironlake_get_pp_control(dev_priv);
1158 pp |= EDP_BLC_ENABLE;
1159 I915_WRITE(PCH_PP_CONTROL, pp);
1160 POSTING_READ(PCH_PP_CONTROL);
1161 }
1162
1163 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1164 {
1165 struct drm_device *dev = intel_dp->base.base.dev;
1166 struct drm_i915_private *dev_priv = dev->dev_private;
1167 u32 pp;
1168
1169 if (!is_edp(intel_dp))
1170 return;
1171
1172 DRM_DEBUG_KMS("\n");
1173 pp = ironlake_get_pp_control(dev_priv);
1174 pp &= ~EDP_BLC_ENABLE;
1175 I915_WRITE(PCH_PP_CONTROL, pp);
1176 POSTING_READ(PCH_PP_CONTROL);
1177 msleep(intel_dp->backlight_off_delay);
1178 }
1179
1180 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1181 {
1182 struct drm_device *dev = intel_dp->base.base.dev;
1183 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1184 struct drm_i915_private *dev_priv = dev->dev_private;
1185 u32 dpa_ctl;
1186
1187 assert_pipe_disabled(dev_priv,
1188 to_intel_crtc(crtc)->pipe);
1189
1190 DRM_DEBUG_KMS("\n");
1191 dpa_ctl = I915_READ(DP_A);
1192 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1193 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1194
1195 /* We don't adjust intel_dp->DP while tearing down the link, to
1196 * facilitate link retraining (e.g. after hotplug). Hence clear all
1197 * enable bits here to ensure that we don't enable too much. */
1198 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1199 intel_dp->DP |= DP_PLL_ENABLE;
1200 I915_WRITE(DP_A, intel_dp->DP);
1201 POSTING_READ(DP_A);
1202 udelay(200);
1203 }
1204
1205 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1206 {
1207 struct drm_device *dev = intel_dp->base.base.dev;
1208 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 u32 dpa_ctl;
1211
1212 assert_pipe_disabled(dev_priv,
1213 to_intel_crtc(crtc)->pipe);
1214
1215 dpa_ctl = I915_READ(DP_A);
1216 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1217 "dp pll off, should be on\n");
1218 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1219
1220 /* We can't rely on the value tracked for the DP register in
1221 * intel_dp->DP because link_down must not change that (otherwise link
1222 * re-training will fail. */
1223 dpa_ctl &= ~DP_PLL_ENABLE;
1224 I915_WRITE(DP_A, dpa_ctl);
1225 POSTING_READ(DP_A);
1226 udelay(200);
1227 }
1228
1229 /* If the sink supports it, try to set the power state appropriately */
1230 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1231 {
1232 int ret, i;
1233
1234 /* Should have a valid DPCD by this point */
1235 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1236 return;
1237
1238 if (mode != DRM_MODE_DPMS_ON) {
1239 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1240 DP_SET_POWER_D3);
1241 if (ret != 1)
1242 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1243 } else {
1244 /*
1245 * When turning on, we need to retry for 1ms to give the sink
1246 * time to wake up.
1247 */
1248 for (i = 0; i < 3; i++) {
1249 ret = intel_dp_aux_native_write_1(intel_dp,
1250 DP_SET_POWER,
1251 DP_SET_POWER_D0);
1252 if (ret == 1)
1253 break;
1254 msleep(1);
1255 }
1256 }
1257 }
1258
1259 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1260 enum pipe *pipe)
1261 {
1262 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1263 struct drm_device *dev = encoder->base.dev;
1264 struct drm_i915_private *dev_priv = dev->dev_private;
1265 u32 tmp = I915_READ(intel_dp->output_reg);
1266
1267 if (!(tmp & DP_PORT_EN))
1268 return false;
1269
1270 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1271 *pipe = PORT_TO_PIPE_CPT(tmp);
1272 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1273 *pipe = PORT_TO_PIPE(tmp);
1274 } else {
1275 u32 trans_sel;
1276 u32 trans_dp;
1277 int i;
1278
1279 switch (intel_dp->output_reg) {
1280 case PCH_DP_B:
1281 trans_sel = TRANS_DP_PORT_SEL_B;
1282 break;
1283 case PCH_DP_C:
1284 trans_sel = TRANS_DP_PORT_SEL_C;
1285 break;
1286 case PCH_DP_D:
1287 trans_sel = TRANS_DP_PORT_SEL_D;
1288 break;
1289 default:
1290 return true;
1291 }
1292
1293 for_each_pipe(i) {
1294 trans_dp = I915_READ(TRANS_DP_CTL(i));
1295 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1296 *pipe = i;
1297 return true;
1298 }
1299 }
1300 }
1301
1302 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1303
1304 return true;
1305 }
1306
1307 static void intel_disable_dp(struct intel_encoder *encoder)
1308 {
1309 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1310
1311 /* Make sure the panel is off before trying to change the mode. But also
1312 * ensure that we have vdd while we switch off the panel. */
1313 ironlake_edp_panel_vdd_on(intel_dp);
1314 ironlake_edp_backlight_off(intel_dp);
1315 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1316 ironlake_edp_panel_off(intel_dp);
1317
1318 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1319 if (!is_cpu_edp(intel_dp))
1320 intel_dp_link_down(intel_dp);
1321 }
1322
1323 static void intel_post_disable_dp(struct intel_encoder *encoder)
1324 {
1325 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1326
1327 if (is_cpu_edp(intel_dp)) {
1328 intel_dp_link_down(intel_dp);
1329 ironlake_edp_pll_off(intel_dp);
1330 }
1331 }
1332
1333 static void intel_enable_dp(struct intel_encoder *encoder)
1334 {
1335 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1336 struct drm_device *dev = encoder->base.dev;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1339
1340 if (WARN_ON(dp_reg & DP_PORT_EN))
1341 return;
1342
1343 ironlake_edp_panel_vdd_on(intel_dp);
1344 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1345 intel_dp_start_link_train(intel_dp);
1346 ironlake_edp_panel_on(intel_dp);
1347 ironlake_edp_panel_vdd_off(intel_dp, true);
1348 intel_dp_complete_link_train(intel_dp);
1349 ironlake_edp_backlight_on(intel_dp);
1350 }
1351
1352 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1353 {
1354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1355
1356 if (is_cpu_edp(intel_dp))
1357 ironlake_edp_pll_on(intel_dp);
1358 }
1359
1360 /*
1361 * Native read with retry for link status and receiver capability reads for
1362 * cases where the sink may still be asleep.
1363 */
1364 static bool
1365 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1366 uint8_t *recv, int recv_bytes)
1367 {
1368 int ret, i;
1369
1370 /*
1371 * Sinks are *supposed* to come up within 1ms from an off state,
1372 * but we're also supposed to retry 3 times per the spec.
1373 */
1374 for (i = 0; i < 3; i++) {
1375 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1376 recv_bytes);
1377 if (ret == recv_bytes)
1378 return true;
1379 msleep(1);
1380 }
1381
1382 return false;
1383 }
1384
1385 /*
1386 * Fetch AUX CH registers 0x202 - 0x207 which contain
1387 * link status information
1388 */
1389 static bool
1390 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1391 {
1392 return intel_dp_aux_native_read_retry(intel_dp,
1393 DP_LANE0_1_STATUS,
1394 link_status,
1395 DP_LINK_STATUS_SIZE);
1396 }
1397
1398 static uint8_t
1399 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1400 int r)
1401 {
1402 return link_status[r - DP_LANE0_1_STATUS];
1403 }
1404
1405 static uint8_t
1406 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1407 int lane)
1408 {
1409 int s = ((lane & 1) ?
1410 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1411 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1412 uint8_t l = adjust_request[lane>>1];
1413
1414 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1415 }
1416
1417 static uint8_t
1418 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1419 int lane)
1420 {
1421 int s = ((lane & 1) ?
1422 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1423 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1424 uint8_t l = adjust_request[lane>>1];
1425
1426 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1427 }
1428
1429
1430 #if 0
1431 static char *voltage_names[] = {
1432 "0.4V", "0.6V", "0.8V", "1.2V"
1433 };
1434 static char *pre_emph_names[] = {
1435 "0dB", "3.5dB", "6dB", "9.5dB"
1436 };
1437 static char *link_train_names[] = {
1438 "pattern 1", "pattern 2", "idle", "off"
1439 };
1440 #endif
1441
1442 /*
1443 * These are source-specific values; current Intel hardware supports
1444 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1445 */
1446
1447 static uint8_t
1448 intel_dp_voltage_max(struct intel_dp *intel_dp)
1449 {
1450 struct drm_device *dev = intel_dp->base.base.dev;
1451
1452 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1453 return DP_TRAIN_VOLTAGE_SWING_800;
1454 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1455 return DP_TRAIN_VOLTAGE_SWING_1200;
1456 else
1457 return DP_TRAIN_VOLTAGE_SWING_800;
1458 }
1459
1460 static uint8_t
1461 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1462 {
1463 struct drm_device *dev = intel_dp->base.base.dev;
1464
1465 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1466 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1467 case DP_TRAIN_VOLTAGE_SWING_400:
1468 return DP_TRAIN_PRE_EMPHASIS_6;
1469 case DP_TRAIN_VOLTAGE_SWING_600:
1470 case DP_TRAIN_VOLTAGE_SWING_800:
1471 return DP_TRAIN_PRE_EMPHASIS_3_5;
1472 default:
1473 return DP_TRAIN_PRE_EMPHASIS_0;
1474 }
1475 } else {
1476 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1477 case DP_TRAIN_VOLTAGE_SWING_400:
1478 return DP_TRAIN_PRE_EMPHASIS_6;
1479 case DP_TRAIN_VOLTAGE_SWING_600:
1480 return DP_TRAIN_PRE_EMPHASIS_6;
1481 case DP_TRAIN_VOLTAGE_SWING_800:
1482 return DP_TRAIN_PRE_EMPHASIS_3_5;
1483 case DP_TRAIN_VOLTAGE_SWING_1200:
1484 default:
1485 return DP_TRAIN_PRE_EMPHASIS_0;
1486 }
1487 }
1488 }
1489
1490 static void
1491 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1492 {
1493 uint8_t v = 0;
1494 uint8_t p = 0;
1495 int lane;
1496 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1497 uint8_t voltage_max;
1498 uint8_t preemph_max;
1499
1500 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1501 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1502 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1503
1504 if (this_v > v)
1505 v = this_v;
1506 if (this_p > p)
1507 p = this_p;
1508 }
1509
1510 voltage_max = intel_dp_voltage_max(intel_dp);
1511 if (v >= voltage_max)
1512 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1513
1514 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1515 if (p >= preemph_max)
1516 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1517
1518 for (lane = 0; lane < 4; lane++)
1519 intel_dp->train_set[lane] = v | p;
1520 }
1521
1522 static uint32_t
1523 intel_dp_signal_levels(uint8_t train_set)
1524 {
1525 uint32_t signal_levels = 0;
1526
1527 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1528 case DP_TRAIN_VOLTAGE_SWING_400:
1529 default:
1530 signal_levels |= DP_VOLTAGE_0_4;
1531 break;
1532 case DP_TRAIN_VOLTAGE_SWING_600:
1533 signal_levels |= DP_VOLTAGE_0_6;
1534 break;
1535 case DP_TRAIN_VOLTAGE_SWING_800:
1536 signal_levels |= DP_VOLTAGE_0_8;
1537 break;
1538 case DP_TRAIN_VOLTAGE_SWING_1200:
1539 signal_levels |= DP_VOLTAGE_1_2;
1540 break;
1541 }
1542 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1543 case DP_TRAIN_PRE_EMPHASIS_0:
1544 default:
1545 signal_levels |= DP_PRE_EMPHASIS_0;
1546 break;
1547 case DP_TRAIN_PRE_EMPHASIS_3_5:
1548 signal_levels |= DP_PRE_EMPHASIS_3_5;
1549 break;
1550 case DP_TRAIN_PRE_EMPHASIS_6:
1551 signal_levels |= DP_PRE_EMPHASIS_6;
1552 break;
1553 case DP_TRAIN_PRE_EMPHASIS_9_5:
1554 signal_levels |= DP_PRE_EMPHASIS_9_5;
1555 break;
1556 }
1557 return signal_levels;
1558 }
1559
1560 /* Gen6's DP voltage swing and pre-emphasis control */
1561 static uint32_t
1562 intel_gen6_edp_signal_levels(uint8_t train_set)
1563 {
1564 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1565 DP_TRAIN_PRE_EMPHASIS_MASK);
1566 switch (signal_levels) {
1567 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1568 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1569 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1570 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1571 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1572 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1573 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1574 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1575 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1576 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1577 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1578 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1579 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1580 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1581 default:
1582 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1583 "0x%x\n", signal_levels);
1584 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1585 }
1586 }
1587
1588 /* Gen7's DP voltage swing and pre-emphasis control */
1589 static uint32_t
1590 intel_gen7_edp_signal_levels(uint8_t train_set)
1591 {
1592 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1593 DP_TRAIN_PRE_EMPHASIS_MASK);
1594 switch (signal_levels) {
1595 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1596 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1597 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1598 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1599 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1600 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1601
1602 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1603 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1604 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1605 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1606
1607 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1608 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1609 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1610 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1611
1612 default:
1613 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1614 "0x%x\n", signal_levels);
1615 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1616 }
1617 }
1618
1619 static uint8_t
1620 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1621 int lane)
1622 {
1623 int s = (lane & 1) * 4;
1624 uint8_t l = link_status[lane>>1];
1625
1626 return (l >> s) & 0xf;
1627 }
1628
1629 /* Check for clock recovery is done on all channels */
1630 static bool
1631 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1632 {
1633 int lane;
1634 uint8_t lane_status;
1635
1636 for (lane = 0; lane < lane_count; lane++) {
1637 lane_status = intel_get_lane_status(link_status, lane);
1638 if ((lane_status & DP_LANE_CR_DONE) == 0)
1639 return false;
1640 }
1641 return true;
1642 }
1643
1644 /* Check to see if channel eq is done on all channels */
1645 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1646 DP_LANE_CHANNEL_EQ_DONE|\
1647 DP_LANE_SYMBOL_LOCKED)
1648 static bool
1649 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1650 {
1651 uint8_t lane_align;
1652 uint8_t lane_status;
1653 int lane;
1654
1655 lane_align = intel_dp_link_status(link_status,
1656 DP_LANE_ALIGN_STATUS_UPDATED);
1657 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1658 return false;
1659 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1660 lane_status = intel_get_lane_status(link_status, lane);
1661 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1662 return false;
1663 }
1664 return true;
1665 }
1666
1667 static bool
1668 intel_dp_set_link_train(struct intel_dp *intel_dp,
1669 uint32_t dp_reg_value,
1670 uint8_t dp_train_pat)
1671 {
1672 struct drm_device *dev = intel_dp->base.base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 int ret;
1675
1676 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1677 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1678
1679 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1680 case DP_TRAINING_PATTERN_DISABLE:
1681 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1682 break;
1683 case DP_TRAINING_PATTERN_1:
1684 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1685 break;
1686 case DP_TRAINING_PATTERN_2:
1687 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1688 break;
1689 case DP_TRAINING_PATTERN_3:
1690 DRM_ERROR("DP training pattern 3 not supported\n");
1691 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1692 break;
1693 }
1694
1695 } else {
1696 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1697
1698 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1699 case DP_TRAINING_PATTERN_DISABLE:
1700 dp_reg_value |= DP_LINK_TRAIN_OFF;
1701 break;
1702 case DP_TRAINING_PATTERN_1:
1703 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1704 break;
1705 case DP_TRAINING_PATTERN_2:
1706 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1707 break;
1708 case DP_TRAINING_PATTERN_3:
1709 DRM_ERROR("DP training pattern 3 not supported\n");
1710 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1711 break;
1712 }
1713 }
1714
1715 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1716 POSTING_READ(intel_dp->output_reg);
1717
1718 intel_dp_aux_native_write_1(intel_dp,
1719 DP_TRAINING_PATTERN_SET,
1720 dp_train_pat);
1721
1722 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1723 DP_TRAINING_PATTERN_DISABLE) {
1724 ret = intel_dp_aux_native_write(intel_dp,
1725 DP_TRAINING_LANE0_SET,
1726 intel_dp->train_set,
1727 intel_dp->lane_count);
1728 if (ret != intel_dp->lane_count)
1729 return false;
1730 }
1731
1732 return true;
1733 }
1734
1735 /* Enable corresponding port and start training pattern 1 */
1736 static void
1737 intel_dp_start_link_train(struct intel_dp *intel_dp)
1738 {
1739 struct drm_device *dev = intel_dp->base.base.dev;
1740 int i;
1741 uint8_t voltage;
1742 bool clock_recovery = false;
1743 int voltage_tries, loop_tries;
1744 uint32_t DP = intel_dp->DP;
1745
1746 /* Write the link configuration data */
1747 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1748 intel_dp->link_configuration,
1749 DP_LINK_CONFIGURATION_SIZE);
1750
1751 DP |= DP_PORT_EN;
1752
1753 memset(intel_dp->train_set, 0, 4);
1754 voltage = 0xff;
1755 voltage_tries = 0;
1756 loop_tries = 0;
1757 clock_recovery = false;
1758 for (;;) {
1759 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1760 uint8_t link_status[DP_LINK_STATUS_SIZE];
1761 uint32_t signal_levels;
1762
1763
1764 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1765 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1766 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1767 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1768 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1769 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1770 } else {
1771 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1772 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1773 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1774 }
1775
1776 if (!intel_dp_set_link_train(intel_dp, DP,
1777 DP_TRAINING_PATTERN_1 |
1778 DP_LINK_SCRAMBLING_DISABLE))
1779 break;
1780 /* Set training pattern 1 */
1781
1782 udelay(100);
1783 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1784 DRM_ERROR("failed to get link status\n");
1785 break;
1786 }
1787
1788 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1789 DRM_DEBUG_KMS("clock recovery OK\n");
1790 clock_recovery = true;
1791 break;
1792 }
1793
1794 /* Check to see if we've tried the max voltage */
1795 for (i = 0; i < intel_dp->lane_count; i++)
1796 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1797 break;
1798 if (i == intel_dp->lane_count && voltage_tries == 5) {
1799 ++loop_tries;
1800 if (loop_tries == 5) {
1801 DRM_DEBUG_KMS("too many full retries, give up\n");
1802 break;
1803 }
1804 memset(intel_dp->train_set, 0, 4);
1805 voltage_tries = 0;
1806 continue;
1807 }
1808
1809 /* Check to see if we've tried the same voltage 5 times */
1810 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1811 ++voltage_tries;
1812 if (voltage_tries == 5) {
1813 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1814 break;
1815 }
1816 } else
1817 voltage_tries = 0;
1818 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1819
1820 /* Compute new intel_dp->train_set as requested by target */
1821 intel_get_adjust_train(intel_dp, link_status);
1822 }
1823
1824 intel_dp->DP = DP;
1825 }
1826
1827 static void
1828 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1829 {
1830 struct drm_device *dev = intel_dp->base.base.dev;
1831 bool channel_eq = false;
1832 int tries, cr_tries;
1833 uint32_t DP = intel_dp->DP;
1834
1835 /* channel equalization */
1836 tries = 0;
1837 cr_tries = 0;
1838 channel_eq = false;
1839 for (;;) {
1840 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1841 uint32_t signal_levels;
1842 uint8_t link_status[DP_LINK_STATUS_SIZE];
1843
1844 if (cr_tries > 5) {
1845 DRM_ERROR("failed to train DP, aborting\n");
1846 intel_dp_link_down(intel_dp);
1847 break;
1848 }
1849
1850 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1851 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1852 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1853 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1854 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1855 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1856 } else {
1857 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1858 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1859 }
1860
1861 /* channel eq pattern */
1862 if (!intel_dp_set_link_train(intel_dp, DP,
1863 DP_TRAINING_PATTERN_2 |
1864 DP_LINK_SCRAMBLING_DISABLE))
1865 break;
1866
1867 udelay(400);
1868 if (!intel_dp_get_link_status(intel_dp, link_status))
1869 break;
1870
1871 /* Make sure clock is still ok */
1872 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1873 intel_dp_start_link_train(intel_dp);
1874 cr_tries++;
1875 continue;
1876 }
1877
1878 if (intel_channel_eq_ok(intel_dp, link_status)) {
1879 channel_eq = true;
1880 break;
1881 }
1882
1883 /* Try 5 times, then try clock recovery if that fails */
1884 if (tries > 5) {
1885 intel_dp_link_down(intel_dp);
1886 intel_dp_start_link_train(intel_dp);
1887 tries = 0;
1888 cr_tries++;
1889 continue;
1890 }
1891
1892 /* Compute new intel_dp->train_set as requested by target */
1893 intel_get_adjust_train(intel_dp, link_status);
1894 ++tries;
1895 }
1896
1897 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1898 }
1899
1900 static void
1901 intel_dp_link_down(struct intel_dp *intel_dp)
1902 {
1903 struct drm_device *dev = intel_dp->base.base.dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 uint32_t DP = intel_dp->DP;
1906
1907 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1908 return;
1909
1910 DRM_DEBUG_KMS("\n");
1911
1912 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1913 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1914 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1915 } else {
1916 DP &= ~DP_LINK_TRAIN_MASK;
1917 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1918 }
1919 POSTING_READ(intel_dp->output_reg);
1920
1921 msleep(17);
1922
1923 if (HAS_PCH_IBX(dev) &&
1924 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1925 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1926
1927 /* Hardware workaround: leaving our transcoder select
1928 * set to transcoder B while it's off will prevent the
1929 * corresponding HDMI output on transcoder A.
1930 *
1931 * Combine this with another hardware workaround:
1932 * transcoder select bit can only be cleared while the
1933 * port is enabled.
1934 */
1935 DP &= ~DP_PIPEB_SELECT;
1936 I915_WRITE(intel_dp->output_reg, DP);
1937
1938 /* Changes to enable or select take place the vblank
1939 * after being written.
1940 */
1941 if (crtc == NULL) {
1942 /* We can arrive here never having been attached
1943 * to a CRTC, for instance, due to inheriting
1944 * random state from the BIOS.
1945 *
1946 * If the pipe is not running, play safe and
1947 * wait for the clocks to stabilise before
1948 * continuing.
1949 */
1950 POSTING_READ(intel_dp->output_reg);
1951 msleep(50);
1952 } else
1953 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1954 }
1955
1956 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1957 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1958 POSTING_READ(intel_dp->output_reg);
1959 msleep(intel_dp->panel_power_down_delay);
1960 }
1961
1962 static bool
1963 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1964 {
1965 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1966 sizeof(intel_dp->dpcd)) &&
1967 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1968 return true;
1969 }
1970
1971 return false;
1972 }
1973
1974 static void
1975 intel_dp_probe_oui(struct intel_dp *intel_dp)
1976 {
1977 u8 buf[3];
1978
1979 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1980 return;
1981
1982 ironlake_edp_panel_vdd_on(intel_dp);
1983
1984 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1985 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1986 buf[0], buf[1], buf[2]);
1987
1988 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1989 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1990 buf[0], buf[1], buf[2]);
1991
1992 ironlake_edp_panel_vdd_off(intel_dp, false);
1993 }
1994
1995 static bool
1996 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1997 {
1998 int ret;
1999
2000 ret = intel_dp_aux_native_read_retry(intel_dp,
2001 DP_DEVICE_SERVICE_IRQ_VECTOR,
2002 sink_irq_vector, 1);
2003 if (!ret)
2004 return false;
2005
2006 return true;
2007 }
2008
2009 static void
2010 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2011 {
2012 /* NAK by default */
2013 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2014 }
2015
2016 /*
2017 * According to DP spec
2018 * 5.1.2:
2019 * 1. Read DPCD
2020 * 2. Configure link according to Receiver Capabilities
2021 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2022 * 4. Check link status on receipt of hot-plug interrupt
2023 */
2024
2025 static void
2026 intel_dp_check_link_status(struct intel_dp *intel_dp)
2027 {
2028 u8 sink_irq_vector;
2029 u8 link_status[DP_LINK_STATUS_SIZE];
2030
2031 if (!intel_dp->base.connectors_active)
2032 return;
2033
2034 if (WARN_ON(!intel_dp->base.base.crtc))
2035 return;
2036
2037 /* Try to read receiver status if the link appears to be up */
2038 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2039 intel_dp_link_down(intel_dp);
2040 return;
2041 }
2042
2043 /* Now read the DPCD to see if it's actually running */
2044 if (!intel_dp_get_dpcd(intel_dp)) {
2045 intel_dp_link_down(intel_dp);
2046 return;
2047 }
2048
2049 /* Try to read the source of the interrupt */
2050 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2051 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2052 /* Clear interrupt source */
2053 intel_dp_aux_native_write_1(intel_dp,
2054 DP_DEVICE_SERVICE_IRQ_VECTOR,
2055 sink_irq_vector);
2056
2057 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2058 intel_dp_handle_test_request(intel_dp);
2059 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2060 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2061 }
2062
2063 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2064 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2065 drm_get_encoder_name(&intel_dp->base.base));
2066 intel_dp_start_link_train(intel_dp);
2067 intel_dp_complete_link_train(intel_dp);
2068 }
2069 }
2070
2071 static enum drm_connector_status
2072 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2073 {
2074 if (intel_dp_get_dpcd(intel_dp))
2075 return connector_status_connected;
2076 return connector_status_disconnected;
2077 }
2078
2079 static enum drm_connector_status
2080 ironlake_dp_detect(struct intel_dp *intel_dp)
2081 {
2082 enum drm_connector_status status;
2083
2084 /* Can't disconnect eDP, but you can close the lid... */
2085 if (is_edp(intel_dp)) {
2086 status = intel_panel_detect(intel_dp->base.base.dev);
2087 if (status == connector_status_unknown)
2088 status = connector_status_connected;
2089 return status;
2090 }
2091
2092 return intel_dp_detect_dpcd(intel_dp);
2093 }
2094
2095 static enum drm_connector_status
2096 g4x_dp_detect(struct intel_dp *intel_dp)
2097 {
2098 struct drm_device *dev = intel_dp->base.base.dev;
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2100 uint32_t bit;
2101
2102 switch (intel_dp->output_reg) {
2103 case DP_B:
2104 bit = DPB_HOTPLUG_LIVE_STATUS;
2105 break;
2106 case DP_C:
2107 bit = DPC_HOTPLUG_LIVE_STATUS;
2108 break;
2109 case DP_D:
2110 bit = DPD_HOTPLUG_LIVE_STATUS;
2111 break;
2112 default:
2113 return connector_status_unknown;
2114 }
2115
2116 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2117 return connector_status_disconnected;
2118
2119 return intel_dp_detect_dpcd(intel_dp);
2120 }
2121
2122 static struct edid *
2123 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2124 {
2125 struct intel_dp *intel_dp = intel_attached_dp(connector);
2126 struct edid *edid;
2127 int size;
2128
2129 if (is_edp(intel_dp)) {
2130 if (!intel_dp->edid)
2131 return NULL;
2132
2133 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2134 edid = kmalloc(size, GFP_KERNEL);
2135 if (!edid)
2136 return NULL;
2137
2138 memcpy(edid, intel_dp->edid, size);
2139 return edid;
2140 }
2141
2142 edid = drm_get_edid(connector, adapter);
2143 return edid;
2144 }
2145
2146 static int
2147 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2148 {
2149 struct intel_dp *intel_dp = intel_attached_dp(connector);
2150 int ret;
2151
2152 if (is_edp(intel_dp)) {
2153 drm_mode_connector_update_edid_property(connector,
2154 intel_dp->edid);
2155 ret = drm_add_edid_modes(connector, intel_dp->edid);
2156 drm_edid_to_eld(connector,
2157 intel_dp->edid);
2158 return intel_dp->edid_mode_count;
2159 }
2160
2161 ret = intel_ddc_get_modes(connector, adapter);
2162 return ret;
2163 }
2164
2165
2166 /**
2167 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2168 *
2169 * \return true if DP port is connected.
2170 * \return false if DP port is disconnected.
2171 */
2172 static enum drm_connector_status
2173 intel_dp_detect(struct drm_connector *connector, bool force)
2174 {
2175 struct intel_dp *intel_dp = intel_attached_dp(connector);
2176 struct drm_device *dev = intel_dp->base.base.dev;
2177 enum drm_connector_status status;
2178 struct edid *edid = NULL;
2179
2180 intel_dp->has_audio = false;
2181
2182 if (HAS_PCH_SPLIT(dev))
2183 status = ironlake_dp_detect(intel_dp);
2184 else
2185 status = g4x_dp_detect(intel_dp);
2186
2187 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2188 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2189 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2190 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2191
2192 if (status != connector_status_connected)
2193 return status;
2194
2195 intel_dp_probe_oui(intel_dp);
2196
2197 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2198 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2199 } else {
2200 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2201 if (edid) {
2202 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2203 kfree(edid);
2204 }
2205 }
2206
2207 return connector_status_connected;
2208 }
2209
2210 static int intel_dp_get_modes(struct drm_connector *connector)
2211 {
2212 struct intel_dp *intel_dp = intel_attached_dp(connector);
2213 struct drm_device *dev = intel_dp->base.base.dev;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 int ret;
2216
2217 /* We should parse the EDID data and find out if it has an audio sink
2218 */
2219
2220 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2221 if (ret) {
2222 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2223 struct drm_display_mode *newmode;
2224 list_for_each_entry(newmode, &connector->probed_modes,
2225 head) {
2226 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2227 intel_dp->panel_fixed_mode =
2228 drm_mode_duplicate(dev, newmode);
2229 break;
2230 }
2231 }
2232 }
2233 return ret;
2234 }
2235
2236 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2237 if (is_edp(intel_dp)) {
2238 /* initialize panel mode from VBT if available for eDP */
2239 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2240 intel_dp->panel_fixed_mode =
2241 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2242 if (intel_dp->panel_fixed_mode) {
2243 intel_dp->panel_fixed_mode->type |=
2244 DRM_MODE_TYPE_PREFERRED;
2245 }
2246 }
2247 if (intel_dp->panel_fixed_mode) {
2248 struct drm_display_mode *mode;
2249 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2250 drm_mode_probed_add(connector, mode);
2251 return 1;
2252 }
2253 }
2254 return 0;
2255 }
2256
2257 static bool
2258 intel_dp_detect_audio(struct drm_connector *connector)
2259 {
2260 struct intel_dp *intel_dp = intel_attached_dp(connector);
2261 struct edid *edid;
2262 bool has_audio = false;
2263
2264 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2265 if (edid) {
2266 has_audio = drm_detect_monitor_audio(edid);
2267 kfree(edid);
2268 }
2269
2270 return has_audio;
2271 }
2272
2273 static int
2274 intel_dp_set_property(struct drm_connector *connector,
2275 struct drm_property *property,
2276 uint64_t val)
2277 {
2278 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2279 struct intel_dp *intel_dp = intel_attached_dp(connector);
2280 int ret;
2281
2282 ret = drm_connector_property_set_value(connector, property, val);
2283 if (ret)
2284 return ret;
2285
2286 if (property == dev_priv->force_audio_property) {
2287 int i = val;
2288 bool has_audio;
2289
2290 if (i == intel_dp->force_audio)
2291 return 0;
2292
2293 intel_dp->force_audio = i;
2294
2295 if (i == HDMI_AUDIO_AUTO)
2296 has_audio = intel_dp_detect_audio(connector);
2297 else
2298 has_audio = (i == HDMI_AUDIO_ON);
2299
2300 if (has_audio == intel_dp->has_audio)
2301 return 0;
2302
2303 intel_dp->has_audio = has_audio;
2304 goto done;
2305 }
2306
2307 if (property == dev_priv->broadcast_rgb_property) {
2308 if (val == !!intel_dp->color_range)
2309 return 0;
2310
2311 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2312 goto done;
2313 }
2314
2315 return -EINVAL;
2316
2317 done:
2318 if (intel_dp->base.base.crtc) {
2319 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2320 intel_set_mode(crtc, &crtc->mode,
2321 crtc->x, crtc->y, crtc->fb);
2322 }
2323
2324 return 0;
2325 }
2326
2327 static void
2328 intel_dp_destroy(struct drm_connector *connector)
2329 {
2330 struct drm_device *dev = connector->dev;
2331
2332 if (intel_dpd_is_edp(dev))
2333 intel_panel_destroy_backlight(dev);
2334
2335 drm_sysfs_connector_remove(connector);
2336 drm_connector_cleanup(connector);
2337 kfree(connector);
2338 }
2339
2340 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2341 {
2342 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2343
2344 i2c_del_adapter(&intel_dp->adapter);
2345 drm_encoder_cleanup(encoder);
2346 if (is_edp(intel_dp)) {
2347 kfree(intel_dp->edid);
2348 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2349 ironlake_panel_vdd_off_sync(intel_dp);
2350 }
2351 kfree(intel_dp);
2352 }
2353
2354 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2355 .mode_fixup = intel_dp_mode_fixup,
2356 .mode_set = intel_dp_mode_set,
2357 .disable = intel_encoder_noop,
2358 };
2359
2360 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2361 .dpms = intel_connector_dpms,
2362 .detect = intel_dp_detect,
2363 .fill_modes = drm_helper_probe_single_connector_modes,
2364 .set_property = intel_dp_set_property,
2365 .destroy = intel_dp_destroy,
2366 };
2367
2368 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2369 .get_modes = intel_dp_get_modes,
2370 .mode_valid = intel_dp_mode_valid,
2371 .best_encoder = intel_best_encoder,
2372 };
2373
2374 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2375 .destroy = intel_dp_encoder_destroy,
2376 };
2377
2378 static void
2379 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2380 {
2381 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2382
2383 intel_dp_check_link_status(intel_dp);
2384 }
2385
2386 /* Return which DP Port should be selected for Transcoder DP control */
2387 int
2388 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2389 {
2390 struct drm_device *dev = crtc->dev;
2391 struct intel_encoder *encoder;
2392
2393 for_each_encoder_on_crtc(dev, crtc, encoder) {
2394 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2395
2396 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2397 intel_dp->base.type == INTEL_OUTPUT_EDP)
2398 return intel_dp->output_reg;
2399 }
2400
2401 return -1;
2402 }
2403
2404 /* check the VBT to see whether the eDP is on DP-D port */
2405 bool intel_dpd_is_edp(struct drm_device *dev)
2406 {
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct child_device_config *p_child;
2409 int i;
2410
2411 if (!dev_priv->child_dev_num)
2412 return false;
2413
2414 for (i = 0; i < dev_priv->child_dev_num; i++) {
2415 p_child = dev_priv->child_dev + i;
2416
2417 if (p_child->dvo_port == PORT_IDPD &&
2418 p_child->device_type == DEVICE_TYPE_eDP)
2419 return true;
2420 }
2421 return false;
2422 }
2423
2424 static void
2425 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2426 {
2427 intel_attach_force_audio_property(connector);
2428 intel_attach_broadcast_rgb_property(connector);
2429 }
2430
2431 void
2432 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2433 {
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct drm_connector *connector;
2436 struct intel_dp *intel_dp;
2437 struct intel_encoder *intel_encoder;
2438 struct intel_connector *intel_connector;
2439 const char *name = NULL;
2440 int type;
2441
2442 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2443 if (!intel_dp)
2444 return;
2445
2446 intel_dp->output_reg = output_reg;
2447 intel_dp->port = port;
2448 /* Preserve the current hw state. */
2449 intel_dp->DP = I915_READ(intel_dp->output_reg);
2450
2451 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2452 if (!intel_connector) {
2453 kfree(intel_dp);
2454 return;
2455 }
2456 intel_encoder = &intel_dp->base;
2457
2458 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2459 if (intel_dpd_is_edp(dev))
2460 intel_dp->is_pch_edp = true;
2461
2462 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2463 type = DRM_MODE_CONNECTOR_eDP;
2464 intel_encoder->type = INTEL_OUTPUT_EDP;
2465 } else {
2466 type = DRM_MODE_CONNECTOR_DisplayPort;
2467 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2468 }
2469
2470 connector = &intel_connector->base;
2471 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2472 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2473
2474 connector->polled = DRM_CONNECTOR_POLL_HPD;
2475
2476 intel_encoder->cloneable = false;
2477
2478 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2479 ironlake_panel_vdd_work);
2480
2481 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2482
2483 connector->interlace_allowed = true;
2484 connector->doublescan_allowed = 0;
2485
2486 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2487 DRM_MODE_ENCODER_TMDS);
2488 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2489
2490 intel_connector_attach_encoder(intel_connector, intel_encoder);
2491 drm_sysfs_connector_add(connector);
2492
2493 intel_encoder->enable = intel_enable_dp;
2494 intel_encoder->pre_enable = intel_pre_enable_dp;
2495 intel_encoder->disable = intel_disable_dp;
2496 intel_encoder->post_disable = intel_post_disable_dp;
2497 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2498 intel_connector->get_hw_state = intel_connector_get_hw_state;
2499
2500 /* Set up the DDC bus. */
2501 switch (port) {
2502 case PORT_A:
2503 name = "DPDDC-A";
2504 break;
2505 case PORT_B:
2506 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2507 name = "DPDDC-B";
2508 break;
2509 case PORT_C:
2510 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2511 name = "DPDDC-C";
2512 break;
2513 case PORT_D:
2514 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2515 name = "DPDDC-D";
2516 break;
2517 default:
2518 WARN(1, "Invalid port %c\n", port_name(port));
2519 break;
2520 }
2521
2522 /* Cache some DPCD data in the eDP case */
2523 if (is_edp(intel_dp)) {
2524 struct edp_power_seq cur, vbt;
2525 u32 pp_on, pp_off, pp_div;
2526
2527 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2528 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2529 pp_div = I915_READ(PCH_PP_DIVISOR);
2530
2531 if (!pp_on || !pp_off || !pp_div) {
2532 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2533 intel_dp_encoder_destroy(&intel_dp->base.base);
2534 intel_dp_destroy(&intel_connector->base);
2535 return;
2536 }
2537
2538 /* Pull timing values out of registers */
2539 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2540 PANEL_POWER_UP_DELAY_SHIFT;
2541
2542 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2543 PANEL_LIGHT_ON_DELAY_SHIFT;
2544
2545 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2546 PANEL_LIGHT_OFF_DELAY_SHIFT;
2547
2548 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2549 PANEL_POWER_DOWN_DELAY_SHIFT;
2550
2551 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2552 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2553
2554 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2555 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2556
2557 vbt = dev_priv->edp.pps;
2558
2559 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2560 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2561
2562 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2563
2564 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2565 intel_dp->backlight_on_delay = get_delay(t8);
2566 intel_dp->backlight_off_delay = get_delay(t9);
2567 intel_dp->panel_power_down_delay = get_delay(t10);
2568 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2569
2570 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2571 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2572 intel_dp->panel_power_cycle_delay);
2573
2574 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2575 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2576 }
2577
2578 intel_dp_i2c_init(intel_dp, intel_connector, name);
2579
2580 if (is_edp(intel_dp)) {
2581 bool ret;
2582 struct edid *edid;
2583
2584 ironlake_edp_panel_vdd_on(intel_dp);
2585 ret = intel_dp_get_dpcd(intel_dp);
2586 ironlake_edp_panel_vdd_off(intel_dp, false);
2587
2588 if (ret) {
2589 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2590 dev_priv->no_aux_handshake =
2591 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2592 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2593 } else {
2594 /* if this fails, presume the device is a ghost */
2595 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2596 intel_dp_encoder_destroy(&intel_dp->base.base);
2597 intel_dp_destroy(&intel_connector->base);
2598 return;
2599 }
2600
2601 ironlake_edp_panel_vdd_on(intel_dp);
2602 edid = drm_get_edid(connector, &intel_dp->adapter);
2603 if (edid) {
2604 drm_mode_connector_update_edid_property(connector,
2605 edid);
2606 intel_dp->edid_mode_count =
2607 drm_add_edid_modes(connector, edid);
2608 drm_edid_to_eld(connector, edid);
2609 intel_dp->edid = edid;
2610 }
2611 ironlake_edp_panel_vdd_off(intel_dp, false);
2612 }
2613
2614 intel_encoder->hot_plug = intel_dp_hot_plug;
2615
2616 if (is_edp(intel_dp)) {
2617 dev_priv->int_edp_connector = connector;
2618 intel_panel_setup_backlight(dev);
2619 }
2620
2621 intel_dp_add_properties(intel_dp, connector);
2622
2623 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2624 * 0xd. Failure to do so will result in spurious interrupts being
2625 * generated on the port when a cable is not attached.
2626 */
2627 if (IS_G4X(dev) && !IS_GM45(dev)) {
2628 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2629 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2630 }
2631 }
Linux kernel - Deliverables
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