projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: clear up the fdi dotclock semantics for M/N computation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
56 {
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
60 }
61
62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63 {
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
65 }
66
67 static void intel_dp_link_down(struct intel_dp *intel_dp);
68
69 static int
70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
71 {
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 default:
79 max_link_bw = DP_LINK_BW_1_62;
80 break;
81 }
82 return max_link_bw;
83 }
84
85 /*
86 * The units on the numbers in the next two are... bizarre. Examples will
87 * make it clearer; this one parallels an example in the eDP spec.
88 *
89 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
90 *
91 * 270000 * 1 * 8 / 10 == 216000
92 *
93 * The actual data capacity of that configuration is 2.16Gbit/s, so the
94 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
95 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
96 * 119000. At 18bpp that's 2142000 kilobits per second.
97 *
98 * Thus the strange-looking division by 10 in intel_dp_link_required, to
99 * get the result in decakilobits instead of kilobits.
100 */
101
102 static int
103 intel_dp_link_required(int pixel_clock, int bpp)
104 {
105 return (pixel_clock * bpp + 9) / 10;
106 }
107
108 static int
109 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
110 {
111 return (max_link_clock * max_lanes * 8) / 10;
112 }
113
114 static int
115 intel_dp_mode_valid(struct drm_connector *connector,
116 struct drm_display_mode *mode)
117 {
118 struct intel_dp *intel_dp = intel_attached_dp(connector);
119 struct intel_connector *intel_connector = to_intel_connector(connector);
120 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
121 int target_clock = mode->clock;
122 int max_rate, mode_rate, max_lanes, max_link_clock;
123
124 if (is_edp(intel_dp) && fixed_mode) {
125 if (mode->hdisplay > fixed_mode->hdisplay)
126 return MODE_PANEL;
127
128 if (mode->vdisplay > fixed_mode->vdisplay)
129 return MODE_PANEL;
130
131 target_clock = fixed_mode->clock;
132 }
133
134 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
135 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
136
137 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
138 mode_rate = intel_dp_link_required(target_clock, 18);
139
140 if (mode_rate > max_rate)
141 return MODE_CLOCK_HIGH;
142
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
145
146 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
147 return MODE_H_ILLEGAL;
148
149 return MODE_OK;
150 }
151
152 static uint32_t
153 pack_aux(uint8_t *src, int src_bytes)
154 {
155 int i;
156 uint32_t v = 0;
157
158 if (src_bytes > 4)
159 src_bytes = 4;
160 for (i = 0; i < src_bytes; i++)
161 v |= ((uint32_t) src[i]) << ((3-i) * 8);
162 return v;
163 }
164
165 static void
166 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
167 {
168 int i;
169 if (dst_bytes > 4)
170 dst_bytes = 4;
171 for (i = 0; i < dst_bytes; i++)
172 dst[i] = src >> ((3-i) * 8);
173 }
174
175 /* hrawclock is 1/4 the FSB frequency */
176 static int
177 intel_hrawclk(struct drm_device *dev)
178 {
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 uint32_t clkcfg;
181
182 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
183 if (IS_VALLEYVIEW(dev))
184 return 200;
185
186 clkcfg = I915_READ(CLKCFG);
187 switch (clkcfg & CLKCFG_FSB_MASK) {
188 case CLKCFG_FSB_400:
189 return 100;
190 case CLKCFG_FSB_533:
191 return 133;
192 case CLKCFG_FSB_667:
193 return 166;
194 case CLKCFG_FSB_800:
195 return 200;
196 case CLKCFG_FSB_1067:
197 return 266;
198 case CLKCFG_FSB_1333:
199 return 333;
200 /* these two are just a guess; one of them might be right */
201 case CLKCFG_FSB_1600:
202 case CLKCFG_FSB_1600_ALT:
203 return 400;
204 default:
205 return 133;
206 }
207 }
208
209 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
210 {
211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
212 struct drm_i915_private *dev_priv = dev->dev_private;
213 u32 pp_stat_reg;
214
215 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
216 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
217 }
218
219 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
220 {
221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 u32 pp_ctrl_reg;
224
225 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
226 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
227 }
228
229 static void
230 intel_dp_check_edp(struct intel_dp *intel_dp)
231 {
232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
233 struct drm_i915_private *dev_priv = dev->dev_private;
234 u32 pp_stat_reg, pp_ctrl_reg;
235
236 if (!is_edp(intel_dp))
237 return;
238
239 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
240 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
241
242 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
243 WARN(1, "eDP powered off while attempting aux channel communication.\n");
244 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
245 I915_READ(pp_stat_reg),
246 I915_READ(pp_ctrl_reg));
247 }
248 }
249
250 static uint32_t
251 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
252 {
253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
257 uint32_t status;
258 bool done;
259
260 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
261 if (has_aux_irq)
262 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
263 msecs_to_jiffies(10));
264 else
265 done = wait_for_atomic(C, 10) == 0;
266 if (!done)
267 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
268 has_aux_irq);
269 #undef C
270
271 return status;
272 }
273
274 static int
275 intel_dp_aux_ch(struct intel_dp *intel_dp,
276 uint8_t *send, int send_bytes,
277 uint8_t *recv, int recv_size)
278 {
279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
280 struct drm_device *dev = intel_dig_port->base.base.dev;
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
283 uint32_t ch_data = ch_ctl + 4;
284 int i, ret, recv_bytes;
285 uint32_t status;
286 uint32_t aux_clock_divider;
287 int try, precharge;
288 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
289
290 /* dp aux is extremely sensitive to irq latency, hence request the
291 * lowest possible wakeup latency and so prevent the cpu from going into
292 * deep sleep states.
293 */
294 pm_qos_update_request(&dev_priv->pm_qos, 0);
295
296 intel_dp_check_edp(intel_dp);
297 /* The clock divider is based off the hrawclk,
298 * and would like to run at 2MHz. So, take the
299 * hrawclk value and divide by 2 and use that
300 *
301 * Note that PCH attached eDP panels should use a 125MHz input
302 * clock divider.
303 */
304 if (IS_VALLEYVIEW(dev)) {
305 aux_clock_divider = 100;
306 } else if (intel_dig_port->port == PORT_A) {
307 if (HAS_DDI(dev))
308 aux_clock_divider = DIV_ROUND_CLOSEST(
309 intel_ddi_get_cdclk_freq(dev_priv), 2000);
310 else if (IS_GEN6(dev) || IS_GEN7(dev))
311 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
312 else
313 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
314 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
315 /* Workaround for non-ULT HSW */
316 aux_clock_divider = 74;
317 } else if (HAS_PCH_SPLIT(dev)) {
318 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
319 } else {
320 aux_clock_divider = intel_hrawclk(dev) / 2;
321 }
322
323 if (IS_GEN6(dev))
324 precharge = 3;
325 else
326 precharge = 5;
327
328 /* Try to wait for any previous AUX channel activity */
329 for (try = 0; try < 3; try++) {
330 status = I915_READ_NOTRACE(ch_ctl);
331 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
332 break;
333 msleep(1);
334 }
335
336 if (try == 3) {
337 WARN(1, "dp_aux_ch not started status 0x%08x\n",
338 I915_READ(ch_ctl));
339 ret = -EBUSY;
340 goto out;
341 }
342
343 /* Must try at least 3 times according to DP spec */
344 for (try = 0; try < 5; try++) {
345 /* Load the send data into the aux channel data registers */
346 for (i = 0; i < send_bytes; i += 4)
347 I915_WRITE(ch_data + i,
348 pack_aux(send + i, send_bytes - i));
349
350 /* Send the command and wait for it to complete */
351 I915_WRITE(ch_ctl,
352 DP_AUX_CH_CTL_SEND_BUSY |
353 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
354 DP_AUX_CH_CTL_TIME_OUT_400us |
355 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
356 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
357 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
358 DP_AUX_CH_CTL_DONE |
359 DP_AUX_CH_CTL_TIME_OUT_ERROR |
360 DP_AUX_CH_CTL_RECEIVE_ERROR);
361
362 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
363
364 /* Clear done status and any errors */
365 I915_WRITE(ch_ctl,
366 status |
367 DP_AUX_CH_CTL_DONE |
368 DP_AUX_CH_CTL_TIME_OUT_ERROR |
369 DP_AUX_CH_CTL_RECEIVE_ERROR);
370
371 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
372 DP_AUX_CH_CTL_RECEIVE_ERROR))
373 continue;
374 if (status & DP_AUX_CH_CTL_DONE)
375 break;
376 }
377
378 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
379 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
380 ret = -EBUSY;
381 goto out;
382 }
383
384 /* Check for timeout or receive error.
385 * Timeouts occur when the sink is not connected
386 */
387 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
388 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
389 ret = -EIO;
390 goto out;
391 }
392
393 /* Timeouts occur when the device isn't connected, so they're
394 * "normal" -- don't fill the kernel log with these */
395 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
396 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
397 ret = -ETIMEDOUT;
398 goto out;
399 }
400
401 /* Unload any bytes sent back from the other side */
402 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
403 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
404 if (recv_bytes > recv_size)
405 recv_bytes = recv_size;
406
407 for (i = 0; i < recv_bytes; i += 4)
408 unpack_aux(I915_READ(ch_data + i),
409 recv + i, recv_bytes - i);
410
411 ret = recv_bytes;
412 out:
413 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
414
415 return ret;
416 }
417
418 /* Write data to the aux channel in native mode */
419 static int
420 intel_dp_aux_native_write(struct intel_dp *intel_dp,
421 uint16_t address, uint8_t *send, int send_bytes)
422 {
423 int ret;
424 uint8_t msg[20];
425 int msg_bytes;
426 uint8_t ack;
427
428 intel_dp_check_edp(intel_dp);
429 if (send_bytes > 16)
430 return -1;
431 msg[0] = AUX_NATIVE_WRITE << 4;
432 msg[1] = address >> 8;
433 msg[2] = address & 0xff;
434 msg[3] = send_bytes - 1;
435 memcpy(&msg[4], send, send_bytes);
436 msg_bytes = send_bytes + 4;
437 for (;;) {
438 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
439 if (ret < 0)
440 return ret;
441 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
442 break;
443 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
444 udelay(100);
445 else
446 return -EIO;
447 }
448 return send_bytes;
449 }
450
451 /* Write a single byte to the aux channel in native mode */
452 static int
453 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
454 uint16_t address, uint8_t byte)
455 {
456 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
457 }
458
459 /* read bytes from a native aux channel */
460 static int
461 intel_dp_aux_native_read(struct intel_dp *intel_dp,
462 uint16_t address, uint8_t *recv, int recv_bytes)
463 {
464 uint8_t msg[4];
465 int msg_bytes;
466 uint8_t reply[20];
467 int reply_bytes;
468 uint8_t ack;
469 int ret;
470
471 intel_dp_check_edp(intel_dp);
472 msg[0] = AUX_NATIVE_READ << 4;
473 msg[1] = address >> 8;
474 msg[2] = address & 0xff;
475 msg[3] = recv_bytes - 1;
476
477 msg_bytes = 4;
478 reply_bytes = recv_bytes + 1;
479
480 for (;;) {
481 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
482 reply, reply_bytes);
483 if (ret == 0)
484 return -EPROTO;
485 if (ret < 0)
486 return ret;
487 ack = reply[0];
488 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
489 memcpy(recv, reply + 1, ret - 1);
490 return ret - 1;
491 }
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 udelay(100);
494 else
495 return -EIO;
496 }
497 }
498
499 static int
500 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
501 uint8_t write_byte, uint8_t *read_byte)
502 {
503 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
504 struct intel_dp *intel_dp = container_of(adapter,
505 struct intel_dp,
506 adapter);
507 uint16_t address = algo_data->address;
508 uint8_t msg[5];
509 uint8_t reply[2];
510 unsigned retry;
511 int msg_bytes;
512 int reply_bytes;
513 int ret;
514
515 intel_dp_check_edp(intel_dp);
516 /* Set up the command byte */
517 if (mode & MODE_I2C_READ)
518 msg[0] = AUX_I2C_READ << 4;
519 else
520 msg[0] = AUX_I2C_WRITE << 4;
521
522 if (!(mode & MODE_I2C_STOP))
523 msg[0] |= AUX_I2C_MOT << 4;
524
525 msg[1] = address >> 8;
526 msg[2] = address;
527
528 switch (mode) {
529 case MODE_I2C_WRITE:
530 msg[3] = 0;
531 msg[4] = write_byte;
532 msg_bytes = 5;
533 reply_bytes = 1;
534 break;
535 case MODE_I2C_READ:
536 msg[3] = 0;
537 msg_bytes = 4;
538 reply_bytes = 2;
539 break;
540 default:
541 msg_bytes = 3;
542 reply_bytes = 1;
543 break;
544 }
545
546 for (retry = 0; retry < 5; retry++) {
547 ret = intel_dp_aux_ch(intel_dp,
548 msg, msg_bytes,
549 reply, reply_bytes);
550 if (ret < 0) {
551 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
552 return ret;
553 }
554
555 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
556 case AUX_NATIVE_REPLY_ACK:
557 /* I2C-over-AUX Reply field is only valid
558 * when paired with AUX ACK.
559 */
560 break;
561 case AUX_NATIVE_REPLY_NACK:
562 DRM_DEBUG_KMS("aux_ch native nack\n");
563 return -EREMOTEIO;
564 case AUX_NATIVE_REPLY_DEFER:
565 udelay(100);
566 continue;
567 default:
568 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
569 reply[0]);
570 return -EREMOTEIO;
571 }
572
573 switch (reply[0] & AUX_I2C_REPLY_MASK) {
574 case AUX_I2C_REPLY_ACK:
575 if (mode == MODE_I2C_READ) {
576 *read_byte = reply[1];
577 }
578 return reply_bytes - 1;
579 case AUX_I2C_REPLY_NACK:
580 DRM_DEBUG_KMS("aux_i2c nack\n");
581 return -EREMOTEIO;
582 case AUX_I2C_REPLY_DEFER:
583 DRM_DEBUG_KMS("aux_i2c defer\n");
584 udelay(100);
585 break;
586 default:
587 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
588 return -EREMOTEIO;
589 }
590 }
591
592 DRM_ERROR("too many retries, giving up\n");
593 return -EREMOTEIO;
594 }
595
596 static int
597 intel_dp_i2c_init(struct intel_dp *intel_dp,
598 struct intel_connector *intel_connector, const char *name)
599 {
600 int ret;
601
602 DRM_DEBUG_KMS("i2c_init %s\n", name);
603 intel_dp->algo.running = false;
604 intel_dp->algo.address = 0;
605 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
606
607 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
608 intel_dp->adapter.owner = THIS_MODULE;
609 intel_dp->adapter.class = I2C_CLASS_DDC;
610 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
611 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
612 intel_dp->adapter.algo_data = &intel_dp->algo;
613 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
614
615 ironlake_edp_panel_vdd_on(intel_dp);
616 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
617 ironlake_edp_panel_vdd_off(intel_dp, false);
618 return ret;
619 }
620
621 static void
622 intel_dp_set_clock(struct intel_encoder *encoder,
623 struct intel_crtc_config *pipe_config, int link_bw)
624 {
625 struct drm_device *dev = encoder->base.dev;
626
627 if (IS_G4X(dev)) {
628 if (link_bw == DP_LINK_BW_1_62) {
629 pipe_config->dpll.p1 = 2;
630 pipe_config->dpll.p2 = 10;
631 pipe_config->dpll.n = 2;
632 pipe_config->dpll.m1 = 23;
633 pipe_config->dpll.m2 = 8;
634 } else {
635 pipe_config->dpll.p1 = 1;
636 pipe_config->dpll.p2 = 10;
637 pipe_config->dpll.n = 1;
638 pipe_config->dpll.m1 = 14;
639 pipe_config->dpll.m2 = 2;
640 }
641 pipe_config->clock_set = true;
642 } else if (IS_HASWELL(dev)) {
643 /* Haswell has special-purpose DP DDI clocks. */
644 } else if (HAS_PCH_SPLIT(dev)) {
645 if (link_bw == DP_LINK_BW_1_62) {
646 pipe_config->dpll.n = 1;
647 pipe_config->dpll.p1 = 2;
648 pipe_config->dpll.p2 = 10;
649 pipe_config->dpll.m1 = 12;
650 pipe_config->dpll.m2 = 9;
651 } else {
652 pipe_config->dpll.n = 2;
653 pipe_config->dpll.p1 = 1;
654 pipe_config->dpll.p2 = 10;
655 pipe_config->dpll.m1 = 14;
656 pipe_config->dpll.m2 = 8;
657 }
658 pipe_config->clock_set = true;
659 } else if (IS_VALLEYVIEW(dev)) {
660 /* FIXME: Need to figure out optimized DP clocks for vlv. */
661 }
662 }
663
664 bool
665 intel_dp_compute_config(struct intel_encoder *encoder,
666 struct intel_crtc_config *pipe_config)
667 {
668 struct drm_device *dev = encoder->base.dev;
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
672 enum port port = dp_to_dig_port(intel_dp)->port;
673 struct intel_crtc *intel_crtc = encoder->new_crtc;
674 struct intel_connector *intel_connector = intel_dp->attached_connector;
675 int lane_count, clock;
676 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
677 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
678 int bpp, mode_rate;
679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
680 int target_clock, link_avail, link_clock;
681
682 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
683 pipe_config->has_pch_encoder = true;
684
685 pipe_config->has_dp_encoder = true;
686
687 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
688 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
689 adjusted_mode);
690 if (!HAS_PCH_SPLIT(dev))
691 intel_gmch_panel_fitting(intel_crtc, pipe_config,
692 intel_connector->panel.fitting_mode);
693 else
694 intel_pch_panel_fitting(intel_crtc, pipe_config,
695 intel_connector->panel.fitting_mode);
696 }
697 /* We need to take the panel's fixed mode into account. */
698 target_clock = adjusted_mode->clock;
699
700 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
701 return false;
702
703 DRM_DEBUG_KMS("DP link computation with max lane count %i "
704 "max bw %02x pixel clock %iKHz\n",
705 max_lane_count, bws[max_clock], adjusted_mode->clock);
706
707 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
708 * bpc in between. */
709 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
710 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
711 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
712
713 for (; bpp >= 6*3; bpp -= 2*3) {
714 mode_rate = intel_dp_link_required(target_clock, bpp);
715
716 for (clock = 0; clock <= max_clock; clock++) {
717 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
718 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
719 link_avail = intel_dp_max_data_rate(link_clock,
720 lane_count);
721
722 if (mode_rate <= link_avail) {
723 goto found;
724 }
725 }
726 }
727 }
728
729 return false;
730
731 found:
732 if (intel_dp->color_range_auto) {
733 /*
734 * See:
735 * CEA-861-E - 5.1 Default Encoding Parameters
736 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
737 */
738 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
739 intel_dp->color_range = DP_COLOR_RANGE_16_235;
740 else
741 intel_dp->color_range = 0;
742 }
743
744 if (intel_dp->color_range)
745 pipe_config->limited_color_range = true;
746
747 intel_dp->link_bw = bws[clock];
748 intel_dp->lane_count = lane_count;
749 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
750 pipe_config->pipe_bpp = bpp;
751 pipe_config->pixel_target_clock = target_clock;
752
753 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
754 intel_dp->link_bw, intel_dp->lane_count,
755 adjusted_mode->clock, bpp);
756 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
757 mode_rate, link_avail);
758
759 intel_link_compute_m_n(bpp, lane_count,
760 target_clock, adjusted_mode->clock,
761 &pipe_config->dp_m_n);
762
763 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
764
765 return true;
766 }
767
768 void intel_dp_init_link_config(struct intel_dp *intel_dp)
769 {
770 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
771 intel_dp->link_configuration[0] = intel_dp->link_bw;
772 intel_dp->link_configuration[1] = intel_dp->lane_count;
773 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
774 /*
775 * Check for DPCD version > 1.1 and enhanced framing support
776 */
777 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
778 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
779 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
780 }
781 }
782
783 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
784 {
785 struct drm_device *dev = crtc->dev;
786 struct drm_i915_private *dev_priv = dev->dev_private;
787 u32 dpa_ctl;
788
789 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
790 dpa_ctl = I915_READ(DP_A);
791 dpa_ctl &= ~DP_PLL_FREQ_MASK;
792
793 if (clock < 200000) {
794 /* For a long time we've carried around a ILK-DevA w/a for the
795 * 160MHz clock. If we're really unlucky, it's still required.
796 */
797 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
798 dpa_ctl |= DP_PLL_FREQ_160MHZ;
799 } else {
800 dpa_ctl |= DP_PLL_FREQ_270MHZ;
801 }
802
803 I915_WRITE(DP_A, dpa_ctl);
804
805 POSTING_READ(DP_A);
806 udelay(500);
807 }
808
809 static void
810 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
811 struct drm_display_mode *adjusted_mode)
812 {
813 struct drm_device *dev = encoder->dev;
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
816 enum port port = dp_to_dig_port(intel_dp)->port;
817 struct drm_crtc *crtc = encoder->crtc;
818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
819
820 /*
821 * There are four kinds of DP registers:
822 *
823 * IBX PCH
824 * SNB CPU
825 * IVB CPU
826 * CPT PCH
827 *
828 * IBX PCH and CPU are the same for almost everything,
829 * except that the CPU DP PLL is configured in this
830 * register
831 *
832 * CPT PCH is quite different, having many bits moved
833 * to the TRANS_DP_CTL register instead. That
834 * configuration happens (oddly) in ironlake_pch_enable
835 */
836
837 /* Preserve the BIOS-computed detected bit. This is
838 * supposed to be read-only.
839 */
840 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
841
842 /* Handle DP bits in common between all three register formats */
843 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
844 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
845
846 if (intel_dp->has_audio) {
847 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
848 pipe_name(intel_crtc->pipe));
849 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
850 intel_write_eld(encoder, adjusted_mode);
851 }
852
853 intel_dp_init_link_config(intel_dp);
854
855 /* Split out the IBX/CPU vs CPT settings */
856
857 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
858 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
859 intel_dp->DP |= DP_SYNC_HS_HIGH;
860 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
861 intel_dp->DP |= DP_SYNC_VS_HIGH;
862 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
863
864 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
865 intel_dp->DP |= DP_ENHANCED_FRAMING;
866
867 intel_dp->DP |= intel_crtc->pipe << 29;
868
869 /* don't miss out required setting for eDP */
870 if (adjusted_mode->clock < 200000)
871 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
872 else
873 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
874 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
875 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
876 intel_dp->DP |= intel_dp->color_range;
877
878 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
879 intel_dp->DP |= DP_SYNC_HS_HIGH;
880 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
881 intel_dp->DP |= DP_SYNC_VS_HIGH;
882 intel_dp->DP |= DP_LINK_TRAIN_OFF;
883
884 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
885 intel_dp->DP |= DP_ENHANCED_FRAMING;
886
887 if (intel_crtc->pipe == 1)
888 intel_dp->DP |= DP_PIPEB_SELECT;
889
890 if (port == PORT_A && !IS_VALLEYVIEW(dev)) {
891 /* don't miss out required setting for eDP */
892 if (adjusted_mode->clock < 200000)
893 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
894 else
895 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
896 }
897 } else {
898 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
899 }
900
901 if (port == PORT_A && !IS_VALLEYVIEW(dev))
902 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
903 }
904
905 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
906 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
907
908 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
909 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
910
911 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
912 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
913
914 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
915 u32 mask,
916 u32 value)
917 {
918 struct drm_device *dev = intel_dp_to_dev(intel_dp);
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 u32 pp_stat_reg, pp_ctrl_reg;
921
922 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
923 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
924
925 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
926 mask, value,
927 I915_READ(pp_stat_reg),
928 I915_READ(pp_ctrl_reg));
929
930 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
931 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
932 I915_READ(pp_stat_reg),
933 I915_READ(pp_ctrl_reg));
934 }
935 }
936
937 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
938 {
939 DRM_DEBUG_KMS("Wait for panel power on\n");
940 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
941 }
942
943 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
944 {
945 DRM_DEBUG_KMS("Wait for panel power off time\n");
946 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
947 }
948
949 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
950 {
951 DRM_DEBUG_KMS("Wait for panel power cycle\n");
952 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
953 }
954
955
956 /* Read the current pp_control value, unlocking the register if it
957 * is locked
958 */
959
960 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
961 {
962 struct drm_device *dev = intel_dp_to_dev(intel_dp);
963 struct drm_i915_private *dev_priv = dev->dev_private;
964 u32 control;
965 u32 pp_ctrl_reg;
966
967 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
968 control = I915_READ(pp_ctrl_reg);
969
970 control &= ~PANEL_UNLOCK_MASK;
971 control |= PANEL_UNLOCK_REGS;
972 return control;
973 }
974
975 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
976 {
977 struct drm_device *dev = intel_dp_to_dev(intel_dp);
978 struct drm_i915_private *dev_priv = dev->dev_private;
979 u32 pp;
980 u32 pp_stat_reg, pp_ctrl_reg;
981
982 if (!is_edp(intel_dp))
983 return;
984 DRM_DEBUG_KMS("Turn eDP VDD on\n");
985
986 WARN(intel_dp->want_panel_vdd,
987 "eDP VDD already requested on\n");
988
989 intel_dp->want_panel_vdd = true;
990
991 if (ironlake_edp_have_panel_vdd(intel_dp)) {
992 DRM_DEBUG_KMS("eDP VDD already on\n");
993 return;
994 }
995
996 if (!ironlake_edp_have_panel_power(intel_dp))
997 ironlake_wait_panel_power_cycle(intel_dp);
998
999 pp = ironlake_get_pp_control(intel_dp);
1000 pp |= EDP_FORCE_VDD;
1001
1002 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1003 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1004
1005 I915_WRITE(pp_ctrl_reg, pp);
1006 POSTING_READ(pp_ctrl_reg);
1007 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1008 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1009 /*
1010 * If the panel wasn't on, delay before accessing aux channel
1011 */
1012 if (!ironlake_edp_have_panel_power(intel_dp)) {
1013 DRM_DEBUG_KMS("eDP was not running\n");
1014 msleep(intel_dp->panel_power_up_delay);
1015 }
1016 }
1017
1018 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1019 {
1020 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1021 struct drm_i915_private *dev_priv = dev->dev_private;
1022 u32 pp;
1023 u32 pp_stat_reg, pp_ctrl_reg;
1024
1025 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1026
1027 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1028 pp = ironlake_get_pp_control(intel_dp);
1029 pp &= ~EDP_FORCE_VDD;
1030
1031 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1032 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1033
1034 I915_WRITE(pp_ctrl_reg, pp);
1035 POSTING_READ(pp_ctrl_reg);
1036
1037 /* Make sure sequencer is idle before allowing subsequent activity */
1038 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1039 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1040 msleep(intel_dp->panel_power_down_delay);
1041 }
1042 }
1043
1044 static void ironlake_panel_vdd_work(struct work_struct *__work)
1045 {
1046 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1047 struct intel_dp, panel_vdd_work);
1048 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1049
1050 mutex_lock(&dev->mode_config.mutex);
1051 ironlake_panel_vdd_off_sync(intel_dp);
1052 mutex_unlock(&dev->mode_config.mutex);
1053 }
1054
1055 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1056 {
1057 if (!is_edp(intel_dp))
1058 return;
1059
1060 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1061 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1062
1063 intel_dp->want_panel_vdd = false;
1064
1065 if (sync) {
1066 ironlake_panel_vdd_off_sync(intel_dp);
1067 } else {
1068 /*
1069 * Queue the timer to fire a long
1070 * time from now (relative to the power down delay)
1071 * to keep the panel power up across a sequence of operations
1072 */
1073 schedule_delayed_work(&intel_dp->panel_vdd_work,
1074 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1075 }
1076 }
1077
1078 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1079 {
1080 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 u32 pp;
1083 u32 pp_ctrl_reg;
1084
1085 if (!is_edp(intel_dp))
1086 return;
1087
1088 DRM_DEBUG_KMS("Turn eDP power on\n");
1089
1090 if (ironlake_edp_have_panel_power(intel_dp)) {
1091 DRM_DEBUG_KMS("eDP power already on\n");
1092 return;
1093 }
1094
1095 ironlake_wait_panel_power_cycle(intel_dp);
1096
1097 pp = ironlake_get_pp_control(intel_dp);
1098 if (IS_GEN5(dev)) {
1099 /* ILK workaround: disable reset around power sequence */
1100 pp &= ~PANEL_POWER_RESET;
1101 I915_WRITE(PCH_PP_CONTROL, pp);
1102 POSTING_READ(PCH_PP_CONTROL);
1103 }
1104
1105 pp |= POWER_TARGET_ON;
1106 if (!IS_GEN5(dev))
1107 pp |= PANEL_POWER_RESET;
1108
1109 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1110
1111 I915_WRITE(pp_ctrl_reg, pp);
1112 POSTING_READ(pp_ctrl_reg);
1113
1114 ironlake_wait_panel_on(intel_dp);
1115
1116 if (IS_GEN5(dev)) {
1117 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1118 I915_WRITE(PCH_PP_CONTROL, pp);
1119 POSTING_READ(PCH_PP_CONTROL);
1120 }
1121 }
1122
1123 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1124 {
1125 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1126 struct drm_i915_private *dev_priv = dev->dev_private;
1127 u32 pp;
1128 u32 pp_ctrl_reg;
1129
1130 if (!is_edp(intel_dp))
1131 return;
1132
1133 DRM_DEBUG_KMS("Turn eDP power off\n");
1134
1135 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1136
1137 pp = ironlake_get_pp_control(intel_dp);
1138 /* We need to switch off panel power _and_ force vdd, for otherwise some
1139 * panels get very unhappy and cease to work. */
1140 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1141
1142 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1143
1144 I915_WRITE(pp_ctrl_reg, pp);
1145 POSTING_READ(pp_ctrl_reg);
1146
1147 intel_dp->want_panel_vdd = false;
1148
1149 ironlake_wait_panel_off(intel_dp);
1150 }
1151
1152 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1153 {
1154 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1155 struct drm_device *dev = intel_dig_port->base.base.dev;
1156 struct drm_i915_private *dev_priv = dev->dev_private;
1157 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1158 u32 pp;
1159 u32 pp_ctrl_reg;
1160
1161 if (!is_edp(intel_dp))
1162 return;
1163
1164 DRM_DEBUG_KMS("\n");
1165 /*
1166 * If we enable the backlight right away following a panel power
1167 * on, we may see slight flicker as the panel syncs with the eDP
1168 * link. So delay a bit to make sure the image is solid before
1169 * allowing it to appear.
1170 */
1171 msleep(intel_dp->backlight_on_delay);
1172 pp = ironlake_get_pp_control(intel_dp);
1173 pp |= EDP_BLC_ENABLE;
1174
1175 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1176
1177 I915_WRITE(pp_ctrl_reg, pp);
1178 POSTING_READ(pp_ctrl_reg);
1179
1180 intel_panel_enable_backlight(dev, pipe);
1181 }
1182
1183 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1184 {
1185 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 u32 pp;
1188 u32 pp_ctrl_reg;
1189
1190 if (!is_edp(intel_dp))
1191 return;
1192
1193 intel_panel_disable_backlight(dev);
1194
1195 DRM_DEBUG_KMS("\n");
1196 pp = ironlake_get_pp_control(intel_dp);
1197 pp &= ~EDP_BLC_ENABLE;
1198
1199 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1200
1201 I915_WRITE(pp_ctrl_reg, pp);
1202 POSTING_READ(pp_ctrl_reg);
1203 msleep(intel_dp->backlight_off_delay);
1204 }
1205
1206 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1207 {
1208 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1209 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1210 struct drm_device *dev = crtc->dev;
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 u32 dpa_ctl;
1213
1214 assert_pipe_disabled(dev_priv,
1215 to_intel_crtc(crtc)->pipe);
1216
1217 DRM_DEBUG_KMS("\n");
1218 dpa_ctl = I915_READ(DP_A);
1219 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1220 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1221
1222 /* We don't adjust intel_dp->DP while tearing down the link, to
1223 * facilitate link retraining (e.g. after hotplug). Hence clear all
1224 * enable bits here to ensure that we don't enable too much. */
1225 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1226 intel_dp->DP |= DP_PLL_ENABLE;
1227 I915_WRITE(DP_A, intel_dp->DP);
1228 POSTING_READ(DP_A);
1229 udelay(200);
1230 }
1231
1232 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1233 {
1234 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1235 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1236 struct drm_device *dev = crtc->dev;
1237 struct drm_i915_private *dev_priv = dev->dev_private;
1238 u32 dpa_ctl;
1239
1240 assert_pipe_disabled(dev_priv,
1241 to_intel_crtc(crtc)->pipe);
1242
1243 dpa_ctl = I915_READ(DP_A);
1244 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1245 "dp pll off, should be on\n");
1246 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1247
1248 /* We can't rely on the value tracked for the DP register in
1249 * intel_dp->DP because link_down must not change that (otherwise link
1250 * re-training will fail. */
1251 dpa_ctl &= ~DP_PLL_ENABLE;
1252 I915_WRITE(DP_A, dpa_ctl);
1253 POSTING_READ(DP_A);
1254 udelay(200);
1255 }
1256
1257 /* If the sink supports it, try to set the power state appropriately */
1258 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1259 {
1260 int ret, i;
1261
1262 /* Should have a valid DPCD by this point */
1263 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1264 return;
1265
1266 if (mode != DRM_MODE_DPMS_ON) {
1267 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1268 DP_SET_POWER_D3);
1269 if (ret != 1)
1270 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1271 } else {
1272 /*
1273 * When turning on, we need to retry for 1ms to give the sink
1274 * time to wake up.
1275 */
1276 for (i = 0; i < 3; i++) {
1277 ret = intel_dp_aux_native_write_1(intel_dp,
1278 DP_SET_POWER,
1279 DP_SET_POWER_D0);
1280 if (ret == 1)
1281 break;
1282 msleep(1);
1283 }
1284 }
1285 }
1286
1287 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1288 enum pipe *pipe)
1289 {
1290 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1291 enum port port = dp_to_dig_port(intel_dp)->port;
1292 struct drm_device *dev = encoder->base.dev;
1293 struct drm_i915_private *dev_priv = dev->dev_private;
1294 u32 tmp = I915_READ(intel_dp->output_reg);
1295
1296 if (!(tmp & DP_PORT_EN))
1297 return false;
1298
1299 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1300 *pipe = PORT_TO_PIPE_CPT(tmp);
1301 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1302 *pipe = PORT_TO_PIPE(tmp);
1303 } else {
1304 u32 trans_sel;
1305 u32 trans_dp;
1306 int i;
1307
1308 switch (intel_dp->output_reg) {
1309 case PCH_DP_B:
1310 trans_sel = TRANS_DP_PORT_SEL_B;
1311 break;
1312 case PCH_DP_C:
1313 trans_sel = TRANS_DP_PORT_SEL_C;
1314 break;
1315 case PCH_DP_D:
1316 trans_sel = TRANS_DP_PORT_SEL_D;
1317 break;
1318 default:
1319 return true;
1320 }
1321
1322 for_each_pipe(i) {
1323 trans_dp = I915_READ(TRANS_DP_CTL(i));
1324 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1325 *pipe = i;
1326 return true;
1327 }
1328 }
1329
1330 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1331 intel_dp->output_reg);
1332 }
1333
1334 return true;
1335 }
1336
1337 static void intel_dp_get_config(struct intel_encoder *encoder,
1338 struct intel_crtc_config *pipe_config)
1339 {
1340 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1341 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1342 u32 tmp, flags = 0;
1343
1344 tmp = I915_READ(intel_dp->output_reg);
1345
1346 if (tmp & DP_SYNC_HS_HIGH)
1347 flags |= DRM_MODE_FLAG_PHSYNC;
1348 else
1349 flags |= DRM_MODE_FLAG_NHSYNC;
1350
1351 if (tmp & DP_SYNC_VS_HIGH)
1352 flags |= DRM_MODE_FLAG_PVSYNC;
1353 else
1354 flags |= DRM_MODE_FLAG_NVSYNC;
1355
1356 pipe_config->adjusted_mode.flags |= flags;
1357 }
1358
1359 static void intel_disable_dp(struct intel_encoder *encoder)
1360 {
1361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1362 enum port port = dp_to_dig_port(intel_dp)->port;
1363 struct drm_device *dev = encoder->base.dev;
1364
1365 /* Make sure the panel is off before trying to change the mode. But also
1366 * ensure that we have vdd while we switch off the panel. */
1367 ironlake_edp_panel_vdd_on(intel_dp);
1368 ironlake_edp_backlight_off(intel_dp);
1369 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1370 ironlake_edp_panel_off(intel_dp);
1371
1372 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1373 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1374 intel_dp_link_down(intel_dp);
1375 }
1376
1377 static void intel_post_disable_dp(struct intel_encoder *encoder)
1378 {
1379 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1380 enum port port = dp_to_dig_port(intel_dp)->port;
1381 struct drm_device *dev = encoder->base.dev;
1382
1383 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1384 intel_dp_link_down(intel_dp);
1385 if (!IS_VALLEYVIEW(dev))
1386 ironlake_edp_pll_off(intel_dp);
1387 }
1388 }
1389
1390 static void intel_enable_dp(struct intel_encoder *encoder)
1391 {
1392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1393 struct drm_device *dev = encoder->base.dev;
1394 struct drm_i915_private *dev_priv = dev->dev_private;
1395 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1396
1397 if (WARN_ON(dp_reg & DP_PORT_EN))
1398 return;
1399
1400 ironlake_edp_panel_vdd_on(intel_dp);
1401 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1402 intel_dp_start_link_train(intel_dp);
1403 ironlake_edp_panel_on(intel_dp);
1404 ironlake_edp_panel_vdd_off(intel_dp, true);
1405 intel_dp_complete_link_train(intel_dp);
1406 intel_dp_stop_link_train(intel_dp);
1407 ironlake_edp_backlight_on(intel_dp);
1408
1409 if (IS_VALLEYVIEW(dev)) {
1410 struct intel_digital_port *dport =
1411 enc_to_dig_port(&encoder->base);
1412 int channel = vlv_dport_to_channel(dport);
1413
1414 vlv_wait_port_ready(dev_priv, channel);
1415 }
1416 }
1417
1418 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1419 {
1420 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1421 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1422 struct drm_device *dev = encoder->base.dev;
1423 struct drm_i915_private *dev_priv = dev->dev_private;
1424
1425 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1426 ironlake_edp_pll_on(intel_dp);
1427
1428 if (IS_VALLEYVIEW(dev)) {
1429 struct intel_crtc *intel_crtc =
1430 to_intel_crtc(encoder->base.crtc);
1431 int port = vlv_dport_to_channel(dport);
1432 int pipe = intel_crtc->pipe;
1433 u32 val;
1434
1435 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1436 val = 0;
1437 if (pipe)
1438 val |= (1<<21);
1439 else
1440 val &= ~(1<<21);
1441 val |= 0x001000c4;
1442 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1443
1444 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1445 0x00760018);
1446 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1447 0x00400888);
1448 }
1449 }
1450
1451 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1452 {
1453 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1454 struct drm_device *dev = encoder->base.dev;
1455 struct drm_i915_private *dev_priv = dev->dev_private;
1456 int port = vlv_dport_to_channel(dport);
1457
1458 if (!IS_VALLEYVIEW(dev))
1459 return;
1460
1461 /* Program Tx lane resets to default */
1462 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1463 DPIO_PCS_TX_LANE2_RESET |
1464 DPIO_PCS_TX_LANE1_RESET);
1465 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1466 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1467 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1468 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1469 DPIO_PCS_CLK_SOFT_RESET);
1470
1471 /* Fix up inter-pair skew failure */
1472 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1473 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1474 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1475 }
1476
1477 /*
1478 * Native read with retry for link status and receiver capability reads for
1479 * cases where the sink may still be asleep.
1480 */
1481 static bool
1482 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1483 uint8_t *recv, int recv_bytes)
1484 {
1485 int ret, i;
1486
1487 /*
1488 * Sinks are *supposed* to come up within 1ms from an off state,
1489 * but we're also supposed to retry 3 times per the spec.
1490 */
1491 for (i = 0; i < 3; i++) {
1492 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1493 recv_bytes);
1494 if (ret == recv_bytes)
1495 return true;
1496 msleep(1);
1497 }
1498
1499 return false;
1500 }
1501
1502 /*
1503 * Fetch AUX CH registers 0x202 - 0x207 which contain
1504 * link status information
1505 */
1506 static bool
1507 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1508 {
1509 return intel_dp_aux_native_read_retry(intel_dp,
1510 DP_LANE0_1_STATUS,
1511 link_status,
1512 DP_LINK_STATUS_SIZE);
1513 }
1514
1515 #if 0
1516 static char *voltage_names[] = {
1517 "0.4V", "0.6V", "0.8V", "1.2V"
1518 };
1519 static char *pre_emph_names[] = {
1520 "0dB", "3.5dB", "6dB", "9.5dB"
1521 };
1522 static char *link_train_names[] = {
1523 "pattern 1", "pattern 2", "idle", "off"
1524 };
1525 #endif
1526
1527 /*
1528 * These are source-specific values; current Intel hardware supports
1529 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1530 */
1531
1532 static uint8_t
1533 intel_dp_voltage_max(struct intel_dp *intel_dp)
1534 {
1535 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1536 enum port port = dp_to_dig_port(intel_dp)->port;
1537
1538 if (IS_VALLEYVIEW(dev))
1539 return DP_TRAIN_VOLTAGE_SWING_1200;
1540 else if (IS_GEN7(dev) && port == PORT_A)
1541 return DP_TRAIN_VOLTAGE_SWING_800;
1542 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1543 return DP_TRAIN_VOLTAGE_SWING_1200;
1544 else
1545 return DP_TRAIN_VOLTAGE_SWING_800;
1546 }
1547
1548 static uint8_t
1549 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1550 {
1551 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1552 enum port port = dp_to_dig_port(intel_dp)->port;
1553
1554 if (HAS_DDI(dev)) {
1555 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1556 case DP_TRAIN_VOLTAGE_SWING_400:
1557 return DP_TRAIN_PRE_EMPHASIS_9_5;
1558 case DP_TRAIN_VOLTAGE_SWING_600:
1559 return DP_TRAIN_PRE_EMPHASIS_6;
1560 case DP_TRAIN_VOLTAGE_SWING_800:
1561 return DP_TRAIN_PRE_EMPHASIS_3_5;
1562 case DP_TRAIN_VOLTAGE_SWING_1200:
1563 default:
1564 return DP_TRAIN_PRE_EMPHASIS_0;
1565 }
1566 } else if (IS_VALLEYVIEW(dev)) {
1567 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1568 case DP_TRAIN_VOLTAGE_SWING_400:
1569 return DP_TRAIN_PRE_EMPHASIS_9_5;
1570 case DP_TRAIN_VOLTAGE_SWING_600:
1571 return DP_TRAIN_PRE_EMPHASIS_6;
1572 case DP_TRAIN_VOLTAGE_SWING_800:
1573 return DP_TRAIN_PRE_EMPHASIS_3_5;
1574 case DP_TRAIN_VOLTAGE_SWING_1200:
1575 default:
1576 return DP_TRAIN_PRE_EMPHASIS_0;
1577 }
1578 } else if (IS_GEN7(dev) && port == PORT_A) {
1579 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1580 case DP_TRAIN_VOLTAGE_SWING_400:
1581 return DP_TRAIN_PRE_EMPHASIS_6;
1582 case DP_TRAIN_VOLTAGE_SWING_600:
1583 case DP_TRAIN_VOLTAGE_SWING_800:
1584 return DP_TRAIN_PRE_EMPHASIS_3_5;
1585 default:
1586 return DP_TRAIN_PRE_EMPHASIS_0;
1587 }
1588 } else {
1589 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1590 case DP_TRAIN_VOLTAGE_SWING_400:
1591 return DP_TRAIN_PRE_EMPHASIS_6;
1592 case DP_TRAIN_VOLTAGE_SWING_600:
1593 return DP_TRAIN_PRE_EMPHASIS_6;
1594 case DP_TRAIN_VOLTAGE_SWING_800:
1595 return DP_TRAIN_PRE_EMPHASIS_3_5;
1596 case DP_TRAIN_VOLTAGE_SWING_1200:
1597 default:
1598 return DP_TRAIN_PRE_EMPHASIS_0;
1599 }
1600 }
1601 }
1602
1603 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1604 {
1605 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1606 struct drm_i915_private *dev_priv = dev->dev_private;
1607 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1608 unsigned long demph_reg_value, preemph_reg_value,
1609 uniqtranscale_reg_value;
1610 uint8_t train_set = intel_dp->train_set[0];
1611 int port = vlv_dport_to_channel(dport);
1612
1613 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1614 case DP_TRAIN_PRE_EMPHASIS_0:
1615 preemph_reg_value = 0x0004000;
1616 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1617 case DP_TRAIN_VOLTAGE_SWING_400:
1618 demph_reg_value = 0x2B405555;
1619 uniqtranscale_reg_value = 0x552AB83A;
1620 break;
1621 case DP_TRAIN_VOLTAGE_SWING_600:
1622 demph_reg_value = 0x2B404040;
1623 uniqtranscale_reg_value = 0x5548B83A;
1624 break;
1625 case DP_TRAIN_VOLTAGE_SWING_800:
1626 demph_reg_value = 0x2B245555;
1627 uniqtranscale_reg_value = 0x5560B83A;
1628 break;
1629 case DP_TRAIN_VOLTAGE_SWING_1200:
1630 demph_reg_value = 0x2B405555;
1631 uniqtranscale_reg_value = 0x5598DA3A;
1632 break;
1633 default:
1634 return 0;
1635 }
1636 break;
1637 case DP_TRAIN_PRE_EMPHASIS_3_5:
1638 preemph_reg_value = 0x0002000;
1639 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1640 case DP_TRAIN_VOLTAGE_SWING_400:
1641 demph_reg_value = 0x2B404040;
1642 uniqtranscale_reg_value = 0x5552B83A;
1643 break;
1644 case DP_TRAIN_VOLTAGE_SWING_600:
1645 demph_reg_value = 0x2B404848;
1646 uniqtranscale_reg_value = 0x5580B83A;
1647 break;
1648 case DP_TRAIN_VOLTAGE_SWING_800:
1649 demph_reg_value = 0x2B404040;
1650 uniqtranscale_reg_value = 0x55ADDA3A;
1651 break;
1652 default:
1653 return 0;
1654 }
1655 break;
1656 case DP_TRAIN_PRE_EMPHASIS_6:
1657 preemph_reg_value = 0x0000000;
1658 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1659 case DP_TRAIN_VOLTAGE_SWING_400:
1660 demph_reg_value = 0x2B305555;
1661 uniqtranscale_reg_value = 0x5570B83A;
1662 break;
1663 case DP_TRAIN_VOLTAGE_SWING_600:
1664 demph_reg_value = 0x2B2B4040;
1665 uniqtranscale_reg_value = 0x55ADDA3A;
1666 break;
1667 default:
1668 return 0;
1669 }
1670 break;
1671 case DP_TRAIN_PRE_EMPHASIS_9_5:
1672 preemph_reg_value = 0x0006000;
1673 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1674 case DP_TRAIN_VOLTAGE_SWING_400:
1675 demph_reg_value = 0x1B405555;
1676 uniqtranscale_reg_value = 0x55ADDA3A;
1677 break;
1678 default:
1679 return 0;
1680 }
1681 break;
1682 default:
1683 return 0;
1684 }
1685
1686 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1687 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1688 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1689 uniqtranscale_reg_value);
1690 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1691 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1692 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1693 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1694
1695 return 0;
1696 }
1697
1698 static void
1699 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1700 {
1701 uint8_t v = 0;
1702 uint8_t p = 0;
1703 int lane;
1704 uint8_t voltage_max;
1705 uint8_t preemph_max;
1706
1707 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1708 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1709 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1710
1711 if (this_v > v)
1712 v = this_v;
1713 if (this_p > p)
1714 p = this_p;
1715 }
1716
1717 voltage_max = intel_dp_voltage_max(intel_dp);
1718 if (v >= voltage_max)
1719 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1720
1721 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1722 if (p >= preemph_max)
1723 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1724
1725 for (lane = 0; lane < 4; lane++)
1726 intel_dp->train_set[lane] = v | p;
1727 }
1728
1729 static uint32_t
1730 intel_gen4_signal_levels(uint8_t train_set)
1731 {
1732 uint32_t signal_levels = 0;
1733
1734 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1735 case DP_TRAIN_VOLTAGE_SWING_400:
1736 default:
1737 signal_levels |= DP_VOLTAGE_0_4;
1738 break;
1739 case DP_TRAIN_VOLTAGE_SWING_600:
1740 signal_levels |= DP_VOLTAGE_0_6;
1741 break;
1742 case DP_TRAIN_VOLTAGE_SWING_800:
1743 signal_levels |= DP_VOLTAGE_0_8;
1744 break;
1745 case DP_TRAIN_VOLTAGE_SWING_1200:
1746 signal_levels |= DP_VOLTAGE_1_2;
1747 break;
1748 }
1749 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1750 case DP_TRAIN_PRE_EMPHASIS_0:
1751 default:
1752 signal_levels |= DP_PRE_EMPHASIS_0;
1753 break;
1754 case DP_TRAIN_PRE_EMPHASIS_3_5:
1755 signal_levels |= DP_PRE_EMPHASIS_3_5;
1756 break;
1757 case DP_TRAIN_PRE_EMPHASIS_6:
1758 signal_levels |= DP_PRE_EMPHASIS_6;
1759 break;
1760 case DP_TRAIN_PRE_EMPHASIS_9_5:
1761 signal_levels |= DP_PRE_EMPHASIS_9_5;
1762 break;
1763 }
1764 return signal_levels;
1765 }
1766
1767 /* Gen6's DP voltage swing and pre-emphasis control */
1768 static uint32_t
1769 intel_gen6_edp_signal_levels(uint8_t train_set)
1770 {
1771 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1772 DP_TRAIN_PRE_EMPHASIS_MASK);
1773 switch (signal_levels) {
1774 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1775 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1776 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1777 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1778 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1779 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1780 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1781 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1782 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1783 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1784 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1785 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1786 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1787 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1788 default:
1789 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1790 "0x%x\n", signal_levels);
1791 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1792 }
1793 }
1794
1795 /* Gen7's DP voltage swing and pre-emphasis control */
1796 static uint32_t
1797 intel_gen7_edp_signal_levels(uint8_t train_set)
1798 {
1799 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1800 DP_TRAIN_PRE_EMPHASIS_MASK);
1801 switch (signal_levels) {
1802 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1803 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1804 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1805 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1806 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1807 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1808
1809 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1810 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1811 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1812 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1813
1814 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1815 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1816 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1817 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1818
1819 default:
1820 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1821 "0x%x\n", signal_levels);
1822 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1823 }
1824 }
1825
1826 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1827 static uint32_t
1828 intel_hsw_signal_levels(uint8_t train_set)
1829 {
1830 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1831 DP_TRAIN_PRE_EMPHASIS_MASK);
1832 switch (signal_levels) {
1833 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1834 return DDI_BUF_EMP_400MV_0DB_HSW;
1835 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1836 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1837 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1838 return DDI_BUF_EMP_400MV_6DB_HSW;
1839 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1840 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1841
1842 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1843 return DDI_BUF_EMP_600MV_0DB_HSW;
1844 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1845 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1846 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1847 return DDI_BUF_EMP_600MV_6DB_HSW;
1848
1849 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1850 return DDI_BUF_EMP_800MV_0DB_HSW;
1851 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1852 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1853 default:
1854 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1855 "0x%x\n", signal_levels);
1856 return DDI_BUF_EMP_400MV_0DB_HSW;
1857 }
1858 }
1859
1860 /* Properly updates "DP" with the correct signal levels. */
1861 static void
1862 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1863 {
1864 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1865 enum port port = intel_dig_port->port;
1866 struct drm_device *dev = intel_dig_port->base.base.dev;
1867 uint32_t signal_levels, mask;
1868 uint8_t train_set = intel_dp->train_set[0];
1869
1870 if (HAS_DDI(dev)) {
1871 signal_levels = intel_hsw_signal_levels(train_set);
1872 mask = DDI_BUF_EMP_MASK;
1873 } else if (IS_VALLEYVIEW(dev)) {
1874 signal_levels = intel_vlv_signal_levels(intel_dp);
1875 mask = 0;
1876 } else if (IS_GEN7(dev) && port == PORT_A) {
1877 signal_levels = intel_gen7_edp_signal_levels(train_set);
1878 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1879 } else if (IS_GEN6(dev) && port == PORT_A) {
1880 signal_levels = intel_gen6_edp_signal_levels(train_set);
1881 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1882 } else {
1883 signal_levels = intel_gen4_signal_levels(train_set);
1884 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1885 }
1886
1887 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1888
1889 *DP = (*DP & ~mask) | signal_levels;
1890 }
1891
1892 static bool
1893 intel_dp_set_link_train(struct intel_dp *intel_dp,
1894 uint32_t dp_reg_value,
1895 uint8_t dp_train_pat)
1896 {
1897 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1898 struct drm_device *dev = intel_dig_port->base.base.dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 enum port port = intel_dig_port->port;
1901 int ret;
1902
1903 if (HAS_DDI(dev)) {
1904 uint32_t temp = I915_READ(DP_TP_CTL(port));
1905
1906 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1907 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1908 else
1909 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1910
1911 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1912 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1913 case DP_TRAINING_PATTERN_DISABLE:
1914 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1915
1916 break;
1917 case DP_TRAINING_PATTERN_1:
1918 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1919 break;
1920 case DP_TRAINING_PATTERN_2:
1921 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1922 break;
1923 case DP_TRAINING_PATTERN_3:
1924 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1925 break;
1926 }
1927 I915_WRITE(DP_TP_CTL(port), temp);
1928
1929 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
1930 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1931
1932 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1933 case DP_TRAINING_PATTERN_DISABLE:
1934 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1935 break;
1936 case DP_TRAINING_PATTERN_1:
1937 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1938 break;
1939 case DP_TRAINING_PATTERN_2:
1940 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1941 break;
1942 case DP_TRAINING_PATTERN_3:
1943 DRM_ERROR("DP training pattern 3 not supported\n");
1944 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1945 break;
1946 }
1947
1948 } else {
1949 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1950
1951 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1952 case DP_TRAINING_PATTERN_DISABLE:
1953 dp_reg_value |= DP_LINK_TRAIN_OFF;
1954 break;
1955 case DP_TRAINING_PATTERN_1:
1956 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1957 break;
1958 case DP_TRAINING_PATTERN_2:
1959 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1960 break;
1961 case DP_TRAINING_PATTERN_3:
1962 DRM_ERROR("DP training pattern 3 not supported\n");
1963 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1964 break;
1965 }
1966 }
1967
1968 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1969 POSTING_READ(intel_dp->output_reg);
1970
1971 intel_dp_aux_native_write_1(intel_dp,
1972 DP_TRAINING_PATTERN_SET,
1973 dp_train_pat);
1974
1975 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1976 DP_TRAINING_PATTERN_DISABLE) {
1977 ret = intel_dp_aux_native_write(intel_dp,
1978 DP_TRAINING_LANE0_SET,
1979 intel_dp->train_set,
1980 intel_dp->lane_count);
1981 if (ret != intel_dp->lane_count)
1982 return false;
1983 }
1984
1985 return true;
1986 }
1987
1988 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1989 {
1990 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1991 struct drm_device *dev = intel_dig_port->base.base.dev;
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1993 enum port port = intel_dig_port->port;
1994 uint32_t val;
1995
1996 if (!HAS_DDI(dev))
1997 return;
1998
1999 val = I915_READ(DP_TP_CTL(port));
2000 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2001 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2002 I915_WRITE(DP_TP_CTL(port), val);
2003
2004 /*
2005 * On PORT_A we can have only eDP in SST mode. There the only reason
2006 * we need to set idle transmission mode is to work around a HW issue
2007 * where we enable the pipe while not in idle link-training mode.
2008 * In this case there is requirement to wait for a minimum number of
2009 * idle patterns to be sent.
2010 */
2011 if (port == PORT_A)
2012 return;
2013
2014 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2015 1))
2016 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2017 }
2018
2019 /* Enable corresponding port and start training pattern 1 */
2020 void
2021 intel_dp_start_link_train(struct intel_dp *intel_dp)
2022 {
2023 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2024 struct drm_device *dev = encoder->dev;
2025 int i;
2026 uint8_t voltage;
2027 bool clock_recovery = false;
2028 int voltage_tries, loop_tries;
2029 uint32_t DP = intel_dp->DP;
2030
2031 if (HAS_DDI(dev))
2032 intel_ddi_prepare_link_retrain(encoder);
2033
2034 /* Write the link configuration data */
2035 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2036 intel_dp->link_configuration,
2037 DP_LINK_CONFIGURATION_SIZE);
2038
2039 DP |= DP_PORT_EN;
2040
2041 memset(intel_dp->train_set, 0, 4);
2042 voltage = 0xff;
2043 voltage_tries = 0;
2044 loop_tries = 0;
2045 clock_recovery = false;
2046 for (;;) {
2047 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2048 uint8_t link_status[DP_LINK_STATUS_SIZE];
2049
2050 intel_dp_set_signal_levels(intel_dp, &DP);
2051
2052 /* Set training pattern 1 */
2053 if (!intel_dp_set_link_train(intel_dp, DP,
2054 DP_TRAINING_PATTERN_1 |
2055 DP_LINK_SCRAMBLING_DISABLE))
2056 break;
2057
2058 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2059 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2060 DRM_ERROR("failed to get link status\n");
2061 break;
2062 }
2063
2064 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2065 DRM_DEBUG_KMS("clock recovery OK\n");
2066 clock_recovery = true;
2067 break;
2068 }
2069
2070 /* Check to see if we've tried the max voltage */
2071 for (i = 0; i < intel_dp->lane_count; i++)
2072 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2073 break;
2074 if (i == intel_dp->lane_count) {
2075 ++loop_tries;
2076 if (loop_tries == 5) {
2077 DRM_DEBUG_KMS("too many full retries, give up\n");
2078 break;
2079 }
2080 memset(intel_dp->train_set, 0, 4);
2081 voltage_tries = 0;
2082 continue;
2083 }
2084
2085 /* Check to see if we've tried the same voltage 5 times */
2086 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2087 ++voltage_tries;
2088 if (voltage_tries == 5) {
2089 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2090 break;
2091 }
2092 } else
2093 voltage_tries = 0;
2094 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2095
2096 /* Compute new intel_dp->train_set as requested by target */
2097 intel_get_adjust_train(intel_dp, link_status);
2098 }
2099
2100 intel_dp->DP = DP;
2101 }
2102
2103 void
2104 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2105 {
2106 bool channel_eq = false;
2107 int tries, cr_tries;
2108 uint32_t DP = intel_dp->DP;
2109
2110 /* channel equalization */
2111 tries = 0;
2112 cr_tries = 0;
2113 channel_eq = false;
2114 for (;;) {
2115 uint8_t link_status[DP_LINK_STATUS_SIZE];
2116
2117 if (cr_tries > 5) {
2118 DRM_ERROR("failed to train DP, aborting\n");
2119 intel_dp_link_down(intel_dp);
2120 break;
2121 }
2122
2123 intel_dp_set_signal_levels(intel_dp, &DP);
2124
2125 /* channel eq pattern */
2126 if (!intel_dp_set_link_train(intel_dp, DP,
2127 DP_TRAINING_PATTERN_2 |
2128 DP_LINK_SCRAMBLING_DISABLE))
2129 break;
2130
2131 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2132 if (!intel_dp_get_link_status(intel_dp, link_status))
2133 break;
2134
2135 /* Make sure clock is still ok */
2136 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2137 intel_dp_start_link_train(intel_dp);
2138 cr_tries++;
2139 continue;
2140 }
2141
2142 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2143 channel_eq = true;
2144 break;
2145 }
2146
2147 /* Try 5 times, then try clock recovery if that fails */
2148 if (tries > 5) {
2149 intel_dp_link_down(intel_dp);
2150 intel_dp_start_link_train(intel_dp);
2151 tries = 0;
2152 cr_tries++;
2153 continue;
2154 }
2155
2156 /* Compute new intel_dp->train_set as requested by target */
2157 intel_get_adjust_train(intel_dp, link_status);
2158 ++tries;
2159 }
2160
2161 intel_dp_set_idle_link_train(intel_dp);
2162
2163 intel_dp->DP = DP;
2164
2165 if (channel_eq)
2166 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2167
2168 }
2169
2170 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2171 {
2172 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2173 DP_TRAINING_PATTERN_DISABLE);
2174 }
2175
2176 static void
2177 intel_dp_link_down(struct intel_dp *intel_dp)
2178 {
2179 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2180 enum port port = intel_dig_port->port;
2181 struct drm_device *dev = intel_dig_port->base.base.dev;
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183 struct intel_crtc *intel_crtc =
2184 to_intel_crtc(intel_dig_port->base.base.crtc);
2185 uint32_t DP = intel_dp->DP;
2186
2187 /*
2188 * DDI code has a strict mode set sequence and we should try to respect
2189 * it, otherwise we might hang the machine in many different ways. So we
2190 * really should be disabling the port only on a complete crtc_disable
2191 * sequence. This function is just called under two conditions on DDI
2192 * code:
2193 * - Link train failed while doing crtc_enable, and on this case we
2194 * really should respect the mode set sequence and wait for a
2195 * crtc_disable.
2196 * - Someone turned the monitor off and intel_dp_check_link_status
2197 * called us. We don't need to disable the whole port on this case, so
2198 * when someone turns the monitor on again,
2199 * intel_ddi_prepare_link_retrain will take care of redoing the link
2200 * train.
2201 */
2202 if (HAS_DDI(dev))
2203 return;
2204
2205 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2206 return;
2207
2208 DRM_DEBUG_KMS("\n");
2209
2210 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2211 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2212 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2213 } else {
2214 DP &= ~DP_LINK_TRAIN_MASK;
2215 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2216 }
2217 POSTING_READ(intel_dp->output_reg);
2218
2219 /* We don't really know why we're doing this */
2220 intel_wait_for_vblank(dev, intel_crtc->pipe);
2221
2222 if (HAS_PCH_IBX(dev) &&
2223 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2224 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2225
2226 /* Hardware workaround: leaving our transcoder select
2227 * set to transcoder B while it's off will prevent the
2228 * corresponding HDMI output on transcoder A.
2229 *
2230 * Combine this with another hardware workaround:
2231 * transcoder select bit can only be cleared while the
2232 * port is enabled.
2233 */
2234 DP &= ~DP_PIPEB_SELECT;
2235 I915_WRITE(intel_dp->output_reg, DP);
2236
2237 /* Changes to enable or select take place the vblank
2238 * after being written.
2239 */
2240 if (WARN_ON(crtc == NULL)) {
2241 /* We should never try to disable a port without a crtc
2242 * attached. For paranoia keep the code around for a
2243 * bit. */
2244 POSTING_READ(intel_dp->output_reg);
2245 msleep(50);
2246 } else
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248 }
2249
2250 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2251 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2252 POSTING_READ(intel_dp->output_reg);
2253 msleep(intel_dp->panel_power_down_delay);
2254 }
2255
2256 static bool
2257 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2258 {
2259 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2260
2261 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2262 sizeof(intel_dp->dpcd)) == 0)
2263 return false; /* aux transfer failed */
2264
2265 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2266 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2267 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2268
2269 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2270 return false; /* DPCD not present */
2271
2272 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2273 DP_DWN_STRM_PORT_PRESENT))
2274 return true; /* native DP sink */
2275
2276 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2277 return true; /* no per-port downstream info */
2278
2279 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2280 intel_dp->downstream_ports,
2281 DP_MAX_DOWNSTREAM_PORTS) == 0)
2282 return false; /* downstream port status fetch failed */
2283
2284 return true;
2285 }
2286
2287 static void
2288 intel_dp_probe_oui(struct intel_dp *intel_dp)
2289 {
2290 u8 buf[3];
2291
2292 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2293 return;
2294
2295 ironlake_edp_panel_vdd_on(intel_dp);
2296
2297 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2298 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2299 buf[0], buf[1], buf[2]);
2300
2301 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2302 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2303 buf[0], buf[1], buf[2]);
2304
2305 ironlake_edp_panel_vdd_off(intel_dp, false);
2306 }
2307
2308 static bool
2309 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2310 {
2311 int ret;
2312
2313 ret = intel_dp_aux_native_read_retry(intel_dp,
2314 DP_DEVICE_SERVICE_IRQ_VECTOR,
2315 sink_irq_vector, 1);
2316 if (!ret)
2317 return false;
2318
2319 return true;
2320 }
2321
2322 static void
2323 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2324 {
2325 /* NAK by default */
2326 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2327 }
2328
2329 /*
2330 * According to DP spec
2331 * 5.1.2:
2332 * 1. Read DPCD
2333 * 2. Configure link according to Receiver Capabilities
2334 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2335 * 4. Check link status on receipt of hot-plug interrupt
2336 */
2337
2338 void
2339 intel_dp_check_link_status(struct intel_dp *intel_dp)
2340 {
2341 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2342 u8 sink_irq_vector;
2343 u8 link_status[DP_LINK_STATUS_SIZE];
2344
2345 if (!intel_encoder->connectors_active)
2346 return;
2347
2348 if (WARN_ON(!intel_encoder->base.crtc))
2349 return;
2350
2351 /* Try to read receiver status if the link appears to be up */
2352 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2353 intel_dp_link_down(intel_dp);
2354 return;
2355 }
2356
2357 /* Now read the DPCD to see if it's actually running */
2358 if (!intel_dp_get_dpcd(intel_dp)) {
2359 intel_dp_link_down(intel_dp);
2360 return;
2361 }
2362
2363 /* Try to read the source of the interrupt */
2364 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2365 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2366 /* Clear interrupt source */
2367 intel_dp_aux_native_write_1(intel_dp,
2368 DP_DEVICE_SERVICE_IRQ_VECTOR,
2369 sink_irq_vector);
2370
2371 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2372 intel_dp_handle_test_request(intel_dp);
2373 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2374 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2375 }
2376
2377 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2378 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2379 drm_get_encoder_name(&intel_encoder->base));
2380 intel_dp_start_link_train(intel_dp);
2381 intel_dp_complete_link_train(intel_dp);
2382 intel_dp_stop_link_train(intel_dp);
2383 }
2384 }
2385
2386 /* XXX this is probably wrong for multiple downstream ports */
2387 static enum drm_connector_status
2388 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2389 {
2390 uint8_t *dpcd = intel_dp->dpcd;
2391 bool hpd;
2392 uint8_t type;
2393
2394 if (!intel_dp_get_dpcd(intel_dp))
2395 return connector_status_disconnected;
2396
2397 /* if there's no downstream port, we're done */
2398 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2399 return connector_status_connected;
2400
2401 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2402 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2403 if (hpd) {
2404 uint8_t reg;
2405 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2406 &reg, 1))
2407 return connector_status_unknown;
2408 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2409 : connector_status_disconnected;
2410 }
2411
2412 /* If no HPD, poke DDC gently */
2413 if (drm_probe_ddc(&intel_dp->adapter))
2414 return connector_status_connected;
2415
2416 /* Well we tried, say unknown for unreliable port types */
2417 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2418 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2419 return connector_status_unknown;
2420
2421 /* Anything else is out of spec, warn and ignore */
2422 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2423 return connector_status_disconnected;
2424 }
2425
2426 static enum drm_connector_status
2427 ironlake_dp_detect(struct intel_dp *intel_dp)
2428 {
2429 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2432 enum drm_connector_status status;
2433
2434 /* Can't disconnect eDP, but you can close the lid... */
2435 if (is_edp(intel_dp)) {
2436 status = intel_panel_detect(dev);
2437 if (status == connector_status_unknown)
2438 status = connector_status_connected;
2439 return status;
2440 }
2441
2442 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2443 return connector_status_disconnected;
2444
2445 return intel_dp_detect_dpcd(intel_dp);
2446 }
2447
2448 static enum drm_connector_status
2449 g4x_dp_detect(struct intel_dp *intel_dp)
2450 {
2451 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2454 uint32_t bit;
2455
2456 /* Can't disconnect eDP, but you can close the lid... */
2457 if (is_edp(intel_dp)) {
2458 enum drm_connector_status status;
2459
2460 status = intel_panel_detect(dev);
2461 if (status == connector_status_unknown)
2462 status = connector_status_connected;
2463 return status;
2464 }
2465
2466 switch (intel_dig_port->port) {
2467 case PORT_B:
2468 bit = PORTB_HOTPLUG_LIVE_STATUS;
2469 break;
2470 case PORT_C:
2471 bit = PORTC_HOTPLUG_LIVE_STATUS;
2472 break;
2473 case PORT_D:
2474 bit = PORTD_HOTPLUG_LIVE_STATUS;
2475 break;
2476 default:
2477 return connector_status_unknown;
2478 }
2479
2480 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2481 return connector_status_disconnected;
2482
2483 return intel_dp_detect_dpcd(intel_dp);
2484 }
2485
2486 static struct edid *
2487 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2488 {
2489 struct intel_connector *intel_connector = to_intel_connector(connector);
2490
2491 /* use cached edid if we have one */
2492 if (intel_connector->edid) {
2493 struct edid *edid;
2494 int size;
2495
2496 /* invalid edid */
2497 if (IS_ERR(intel_connector->edid))
2498 return NULL;
2499
2500 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2501 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2502 if (!edid)
2503 return NULL;
2504
2505 return edid;
2506 }
2507
2508 return drm_get_edid(connector, adapter);
2509 }
2510
2511 static int
2512 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2513 {
2514 struct intel_connector *intel_connector = to_intel_connector(connector);
2515
2516 /* use cached edid if we have one */
2517 if (intel_connector->edid) {
2518 /* invalid edid */
2519 if (IS_ERR(intel_connector->edid))
2520 return 0;
2521
2522 return intel_connector_update_modes(connector,
2523 intel_connector->edid);
2524 }
2525
2526 return intel_ddc_get_modes(connector, adapter);
2527 }
2528
2529 static enum drm_connector_status
2530 intel_dp_detect(struct drm_connector *connector, bool force)
2531 {
2532 struct intel_dp *intel_dp = intel_attached_dp(connector);
2533 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2534 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2535 struct drm_device *dev = connector->dev;
2536 enum drm_connector_status status;
2537 struct edid *edid = NULL;
2538
2539 intel_dp->has_audio = false;
2540
2541 if (HAS_PCH_SPLIT(dev))
2542 status = ironlake_dp_detect(intel_dp);
2543 else
2544 status = g4x_dp_detect(intel_dp);
2545
2546 if (status != connector_status_connected)
2547 return status;
2548
2549 intel_dp_probe_oui(intel_dp);
2550
2551 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2552 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2553 } else {
2554 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2555 if (edid) {
2556 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2557 kfree(edid);
2558 }
2559 }
2560
2561 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2562 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2563 return connector_status_connected;
2564 }
2565
2566 static int intel_dp_get_modes(struct drm_connector *connector)
2567 {
2568 struct intel_dp *intel_dp = intel_attached_dp(connector);
2569 struct intel_connector *intel_connector = to_intel_connector(connector);
2570 struct drm_device *dev = connector->dev;
2571 int ret;
2572
2573 /* We should parse the EDID data and find out if it has an audio sink
2574 */
2575
2576 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2577 if (ret)
2578 return ret;
2579
2580 /* if eDP has no EDID, fall back to fixed mode */
2581 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2582 struct drm_display_mode *mode;
2583 mode = drm_mode_duplicate(dev,
2584 intel_connector->panel.fixed_mode);
2585 if (mode) {
2586 drm_mode_probed_add(connector, mode);
2587 return 1;
2588 }
2589 }
2590 return 0;
2591 }
2592
2593 static bool
2594 intel_dp_detect_audio(struct drm_connector *connector)
2595 {
2596 struct intel_dp *intel_dp = intel_attached_dp(connector);
2597 struct edid *edid;
2598 bool has_audio = false;
2599
2600 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2601 if (edid) {
2602 has_audio = drm_detect_monitor_audio(edid);
2603 kfree(edid);
2604 }
2605
2606 return has_audio;
2607 }
2608
2609 static int
2610 intel_dp_set_property(struct drm_connector *connector,
2611 struct drm_property *property,
2612 uint64_t val)
2613 {
2614 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2615 struct intel_connector *intel_connector = to_intel_connector(connector);
2616 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2617 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2618 int ret;
2619
2620 ret = drm_object_property_set_value(&connector->base, property, val);
2621 if (ret)
2622 return ret;
2623
2624 if (property == dev_priv->force_audio_property) {
2625 int i = val;
2626 bool has_audio;
2627
2628 if (i == intel_dp->force_audio)
2629 return 0;
2630
2631 intel_dp->force_audio = i;
2632
2633 if (i == HDMI_AUDIO_AUTO)
2634 has_audio = intel_dp_detect_audio(connector);
2635 else
2636 has_audio = (i == HDMI_AUDIO_ON);
2637
2638 if (has_audio == intel_dp->has_audio)
2639 return 0;
2640
2641 intel_dp->has_audio = has_audio;
2642 goto done;
2643 }
2644
2645 if (property == dev_priv->broadcast_rgb_property) {
2646 bool old_auto = intel_dp->color_range_auto;
2647 uint32_t old_range = intel_dp->color_range;
2648
2649 switch (val) {
2650 case INTEL_BROADCAST_RGB_AUTO:
2651 intel_dp->color_range_auto = true;
2652 break;
2653 case INTEL_BROADCAST_RGB_FULL:
2654 intel_dp->color_range_auto = false;
2655 intel_dp->color_range = 0;
2656 break;
2657 case INTEL_BROADCAST_RGB_LIMITED:
2658 intel_dp->color_range_auto = false;
2659 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2660 break;
2661 default:
2662 return -EINVAL;
2663 }
2664
2665 if (old_auto == intel_dp->color_range_auto &&
2666 old_range == intel_dp->color_range)
2667 return 0;
2668
2669 goto done;
2670 }
2671
2672 if (is_edp(intel_dp) &&
2673 property == connector->dev->mode_config.scaling_mode_property) {
2674 if (val == DRM_MODE_SCALE_NONE) {
2675 DRM_DEBUG_KMS("no scaling not supported\n");
2676 return -EINVAL;
2677 }
2678
2679 if (intel_connector->panel.fitting_mode == val) {
2680 /* the eDP scaling property is not changed */
2681 return 0;
2682 }
2683 intel_connector->panel.fitting_mode = val;
2684
2685 goto done;
2686 }
2687
2688 return -EINVAL;
2689
2690 done:
2691 if (intel_encoder->base.crtc)
2692 intel_crtc_restore_mode(intel_encoder->base.crtc);
2693
2694 return 0;
2695 }
2696
2697 static void
2698 intel_dp_destroy(struct drm_connector *connector)
2699 {
2700 struct intel_dp *intel_dp = intel_attached_dp(connector);
2701 struct intel_connector *intel_connector = to_intel_connector(connector);
2702
2703 if (!IS_ERR_OR_NULL(intel_connector->edid))
2704 kfree(intel_connector->edid);
2705
2706 if (is_edp(intel_dp))
2707 intel_panel_fini(&intel_connector->panel);
2708
2709 drm_sysfs_connector_remove(connector);
2710 drm_connector_cleanup(connector);
2711 kfree(connector);
2712 }
2713
2714 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2715 {
2716 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2717 struct intel_dp *intel_dp = &intel_dig_port->dp;
2718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2719
2720 i2c_del_adapter(&intel_dp->adapter);
2721 drm_encoder_cleanup(encoder);
2722 if (is_edp(intel_dp)) {
2723 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2724 mutex_lock(&dev->mode_config.mutex);
2725 ironlake_panel_vdd_off_sync(intel_dp);
2726 mutex_unlock(&dev->mode_config.mutex);
2727 }
2728 kfree(intel_dig_port);
2729 }
2730
2731 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2732 .mode_set = intel_dp_mode_set,
2733 };
2734
2735 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2736 .dpms = intel_connector_dpms,
2737 .detect = intel_dp_detect,
2738 .fill_modes = drm_helper_probe_single_connector_modes,
2739 .set_property = intel_dp_set_property,
2740 .destroy = intel_dp_destroy,
2741 };
2742
2743 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2744 .get_modes = intel_dp_get_modes,
2745 .mode_valid = intel_dp_mode_valid,
2746 .best_encoder = intel_best_encoder,
2747 };
2748
2749 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2750 .destroy = intel_dp_encoder_destroy,
2751 };
2752
2753 static void
2754 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2755 {
2756 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2757
2758 intel_dp_check_link_status(intel_dp);
2759 }
2760
2761 /* Return which DP Port should be selected for Transcoder DP control */
2762 int
2763 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2764 {
2765 struct drm_device *dev = crtc->dev;
2766 struct intel_encoder *intel_encoder;
2767 struct intel_dp *intel_dp;
2768
2769 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2770 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2771
2772 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2773 intel_encoder->type == INTEL_OUTPUT_EDP)
2774 return intel_dp->output_reg;
2775 }
2776
2777 return -1;
2778 }
2779
2780 /* check the VBT to see whether the eDP is on DP-D port */
2781 bool intel_dpd_is_edp(struct drm_device *dev)
2782 {
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct child_device_config *p_child;
2785 int i;
2786
2787 if (!dev_priv->vbt.child_dev_num)
2788 return false;
2789
2790 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2791 p_child = dev_priv->vbt.child_dev + i;
2792
2793 if (p_child->dvo_port == PORT_IDPD &&
2794 p_child->device_type == DEVICE_TYPE_eDP)
2795 return true;
2796 }
2797 return false;
2798 }
2799
2800 static void
2801 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2802 {
2803 struct intel_connector *intel_connector = to_intel_connector(connector);
2804
2805 intel_attach_force_audio_property(connector);
2806 intel_attach_broadcast_rgb_property(connector);
2807 intel_dp->color_range_auto = true;
2808
2809 if (is_edp(intel_dp)) {
2810 drm_mode_create_scaling_mode_property(connector->dev);
2811 drm_object_attach_property(
2812 &connector->base,
2813 connector->dev->mode_config.scaling_mode_property,
2814 DRM_MODE_SCALE_ASPECT);
2815 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2816 }
2817 }
2818
2819 static void
2820 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2821 struct intel_dp *intel_dp,
2822 struct edp_power_seq *out)
2823 {
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 struct edp_power_seq cur, vbt, spec, final;
2826 u32 pp_on, pp_off, pp_div, pp;
2827 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2828
2829 if (HAS_PCH_SPLIT(dev)) {
2830 pp_control_reg = PCH_PP_CONTROL;
2831 pp_on_reg = PCH_PP_ON_DELAYS;
2832 pp_off_reg = PCH_PP_OFF_DELAYS;
2833 pp_div_reg = PCH_PP_DIVISOR;
2834 } else {
2835 pp_control_reg = PIPEA_PP_CONTROL;
2836 pp_on_reg = PIPEA_PP_ON_DELAYS;
2837 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2838 pp_div_reg = PIPEA_PP_DIVISOR;
2839 }
2840
2841 /* Workaround: Need to write PP_CONTROL with the unlock key as
2842 * the very first thing. */
2843 pp = ironlake_get_pp_control(intel_dp);
2844 I915_WRITE(pp_control_reg, pp);
2845
2846 pp_on = I915_READ(pp_on_reg);
2847 pp_off = I915_READ(pp_off_reg);
2848 pp_div = I915_READ(pp_div_reg);
2849
2850 /* Pull timing values out of registers */
2851 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2852 PANEL_POWER_UP_DELAY_SHIFT;
2853
2854 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2855 PANEL_LIGHT_ON_DELAY_SHIFT;
2856
2857 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2858 PANEL_LIGHT_OFF_DELAY_SHIFT;
2859
2860 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2861 PANEL_POWER_DOWN_DELAY_SHIFT;
2862
2863 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2864 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2865
2866 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2867 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2868
2869 vbt = dev_priv->vbt.edp_pps;
2870
2871 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2872 * our hw here, which are all in 100usec. */
2873 spec.t1_t3 = 210 * 10;
2874 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2875 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2876 spec.t10 = 500 * 10;
2877 /* This one is special and actually in units of 100ms, but zero
2878 * based in the hw (so we need to add 100 ms). But the sw vbt
2879 * table multiplies it with 1000 to make it in units of 100usec,
2880 * too. */
2881 spec.t11_t12 = (510 + 100) * 10;
2882
2883 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2884 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2885
2886 /* Use the max of the register settings and vbt. If both are
2887 * unset, fall back to the spec limits. */
2888 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2889 spec.field : \
2890 max(cur.field, vbt.field))
2891 assign_final(t1_t3);
2892 assign_final(t8);
2893 assign_final(t9);
2894 assign_final(t10);
2895 assign_final(t11_t12);
2896 #undef assign_final
2897
2898 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2899 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2900 intel_dp->backlight_on_delay = get_delay(t8);
2901 intel_dp->backlight_off_delay = get_delay(t9);
2902 intel_dp->panel_power_down_delay = get_delay(t10);
2903 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2904 #undef get_delay
2905
2906 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2907 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2908 intel_dp->panel_power_cycle_delay);
2909
2910 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2911 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2912
2913 if (out)
2914 *out = final;
2915 }
2916
2917 static void
2918 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2919 struct intel_dp *intel_dp,
2920 struct edp_power_seq *seq)
2921 {
2922 struct drm_i915_private *dev_priv = dev->dev_private;
2923 u32 pp_on, pp_off, pp_div, port_sel = 0;
2924 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2925 int pp_on_reg, pp_off_reg, pp_div_reg;
2926
2927 if (HAS_PCH_SPLIT(dev)) {
2928 pp_on_reg = PCH_PP_ON_DELAYS;
2929 pp_off_reg = PCH_PP_OFF_DELAYS;
2930 pp_div_reg = PCH_PP_DIVISOR;
2931 } else {
2932 pp_on_reg = PIPEA_PP_ON_DELAYS;
2933 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2934 pp_div_reg = PIPEA_PP_DIVISOR;
2935 }
2936
2937 /* And finally store the new values in the power sequencer. */
2938 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2939 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2940 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2941 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2942 /* Compute the divisor for the pp clock, simply match the Bspec
2943 * formula. */
2944 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2945 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2946 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2947
2948 /* Haswell doesn't have any port selection bits for the panel
2949 * power sequencer any more. */
2950 if (IS_VALLEYVIEW(dev)) {
2951 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2952 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2953 if (dp_to_dig_port(intel_dp)->port == PORT_A)
2954 port_sel = PANEL_POWER_PORT_DP_A;
2955 else
2956 port_sel = PANEL_POWER_PORT_DP_D;
2957 }
2958
2959 pp_on |= port_sel;
2960
2961 I915_WRITE(pp_on_reg, pp_on);
2962 I915_WRITE(pp_off_reg, pp_off);
2963 I915_WRITE(pp_div_reg, pp_div);
2964
2965 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2966 I915_READ(pp_on_reg),
2967 I915_READ(pp_off_reg),
2968 I915_READ(pp_div_reg));
2969 }
2970
2971 void
2972 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2973 struct intel_connector *intel_connector)
2974 {
2975 struct drm_connector *connector = &intel_connector->base;
2976 struct intel_dp *intel_dp = &intel_dig_port->dp;
2977 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2978 struct drm_device *dev = intel_encoder->base.dev;
2979 struct drm_i915_private *dev_priv = dev->dev_private;
2980 struct drm_display_mode *fixed_mode = NULL;
2981 struct edp_power_seq power_seq = { 0 };
2982 enum port port = intel_dig_port->port;
2983 const char *name = NULL;
2984 int type;
2985
2986 /* Preserve the current hw state. */
2987 intel_dp->DP = I915_READ(intel_dp->output_reg);
2988 intel_dp->attached_connector = intel_connector;
2989
2990 type = DRM_MODE_CONNECTOR_DisplayPort;
2991 /*
2992 * FIXME : We need to initialize built-in panels before external panels.
2993 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2994 */
2995 switch (port) {
2996 case PORT_A:
2997 type = DRM_MODE_CONNECTOR_eDP;
2998 break;
2999 case PORT_C:
3000 if (IS_VALLEYVIEW(dev))
3001 type = DRM_MODE_CONNECTOR_eDP;
3002 break;
3003 case PORT_D:
3004 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3005 type = DRM_MODE_CONNECTOR_eDP;
3006 break;
3007 default: /* silence GCC warning */
3008 break;
3009 }
3010
3011 /*
3012 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3013 * for DP the encoder type can be set by the caller to
3014 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3015 */
3016 if (type == DRM_MODE_CONNECTOR_eDP)
3017 intel_encoder->type = INTEL_OUTPUT_EDP;
3018
3019 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3020 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3021 port_name(port));
3022
3023 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3024 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3025
3026 connector->interlace_allowed = true;
3027 connector->doublescan_allowed = 0;
3028
3029 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3030 ironlake_panel_vdd_work);
3031
3032 intel_connector_attach_encoder(intel_connector, intel_encoder);
3033 drm_sysfs_connector_add(connector);
3034
3035 if (HAS_DDI(dev))
3036 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3037 else
3038 intel_connector->get_hw_state = intel_connector_get_hw_state;
3039
3040 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3041 if (HAS_DDI(dev)) {
3042 switch (intel_dig_port->port) {
3043 case PORT_A:
3044 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3045 break;
3046 case PORT_B:
3047 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3048 break;
3049 case PORT_C:
3050 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3051 break;
3052 case PORT_D:
3053 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3054 break;
3055 default:
3056 BUG();
3057 }
3058 }
3059
3060 /* Set up the DDC bus. */
3061 switch (port) {
3062 case PORT_A:
3063 intel_encoder->hpd_pin = HPD_PORT_A;
3064 name = "DPDDC-A";
3065 break;
3066 case PORT_B:
3067 intel_encoder->hpd_pin = HPD_PORT_B;
3068 name = "DPDDC-B";
3069 break;
3070 case PORT_C:
3071 intel_encoder->hpd_pin = HPD_PORT_C;
3072 name = "DPDDC-C";
3073 break;
3074 case PORT_D:
3075 intel_encoder->hpd_pin = HPD_PORT_D;
3076 name = "DPDDC-D";
3077 break;
3078 default:
3079 BUG();
3080 }
3081
3082 if (is_edp(intel_dp))
3083 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3084
3085 intel_dp_i2c_init(intel_dp, intel_connector, name);
3086
3087 /* Cache DPCD and EDID for edp. */
3088 if (is_edp(intel_dp)) {
3089 bool ret;
3090 struct drm_display_mode *scan;
3091 struct edid *edid;
3092
3093 ironlake_edp_panel_vdd_on(intel_dp);
3094 ret = intel_dp_get_dpcd(intel_dp);
3095 ironlake_edp_panel_vdd_off(intel_dp, false);
3096
3097 if (ret) {
3098 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3099 dev_priv->no_aux_handshake =
3100 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3101 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3102 } else {
3103 /* if this fails, presume the device is a ghost */
3104 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3105 intel_dp_encoder_destroy(&intel_encoder->base);
3106 intel_dp_destroy(connector);
3107 return;
3108 }
3109
3110 /* We now know it's not a ghost, init power sequence regs. */
3111 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3112 &power_seq);
3113
3114 ironlake_edp_panel_vdd_on(intel_dp);
3115 edid = drm_get_edid(connector, &intel_dp->adapter);
3116 if (edid) {
3117 if (drm_add_edid_modes(connector, edid)) {
3118 drm_mode_connector_update_edid_property(connector, edid);
3119 drm_edid_to_eld(connector, edid);
3120 } else {
3121 kfree(edid);
3122 edid = ERR_PTR(-EINVAL);
3123 }
3124 } else {
3125 edid = ERR_PTR(-ENOENT);
3126 }
3127 intel_connector->edid = edid;
3128
3129 /* prefer fixed mode from EDID if available */
3130 list_for_each_entry(scan, &connector->probed_modes, head) {
3131 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3132 fixed_mode = drm_mode_duplicate(dev, scan);
3133 break;
3134 }
3135 }
3136
3137 /* fallback to VBT if available for eDP */
3138 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3139 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
3140 if (fixed_mode)
3141 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3142 }
3143
3144 ironlake_edp_panel_vdd_off(intel_dp, false);
3145 }
3146
3147 if (is_edp(intel_dp)) {
3148 intel_panel_init(&intel_connector->panel, fixed_mode);
3149 intel_panel_setup_backlight(connector);
3150 }
3151
3152 intel_dp_add_properties(intel_dp, connector);
3153
3154 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3155 * 0xd. Failure to do so will result in spurious interrupts being
3156 * generated on the port when a cable is not attached.
3157 */
3158 if (IS_G4X(dev) && !IS_GM45(dev)) {
3159 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3160 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3161 }
3162 }
3163
3164 void
3165 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3166 {
3167 struct intel_digital_port *intel_dig_port;
3168 struct intel_encoder *intel_encoder;
3169 struct drm_encoder *encoder;
3170 struct intel_connector *intel_connector;
3171
3172 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3173 if (!intel_dig_port)
3174 return;
3175
3176 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3177 if (!intel_connector) {
3178 kfree(intel_dig_port);
3179 return;
3180 }
3181
3182 intel_encoder = &intel_dig_port->base;
3183 encoder = &intel_encoder->base;
3184
3185 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3186 DRM_MODE_ENCODER_TMDS);
3187 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3188
3189 intel_encoder->compute_config = intel_dp_compute_config;
3190 intel_encoder->enable = intel_enable_dp;
3191 intel_encoder->pre_enable = intel_pre_enable_dp;
3192 intel_encoder->disable = intel_disable_dp;
3193 intel_encoder->post_disable = intel_post_disable_dp;
3194 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3195 intel_encoder->get_config = intel_dp_get_config;
3196 if (IS_VALLEYVIEW(dev))
3197 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3198
3199 intel_dig_port->port = port;
3200 intel_dig_port->dp.output_reg = output_reg;
3201
3202 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3203 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3204 intel_encoder->cloneable = false;
3205 intel_encoder->hot_plug = intel_dp_hot_plug;
3206
3207 intel_dp_init_connector(intel_dig_port, intel_connector);
3208 }
Linux kernel - Deliverables
This page took 0.103178 seconds and 6 git commands to generate.