2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
34 #include "drm_crtc_helper.h"
35 #include "intel_drv.h"
38 #include "drm_dp_helper.h"
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 #define DP_LINK_CONFIGURATION_SIZE 9
47 struct intel_encoder base
;
50 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
57 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
58 struct i2c_adapter adapter
;
59 struct i2c_algo_dp_aux_data algo
;
62 int panel_power_up_delay
;
63 int panel_power_down_delay
;
64 int panel_power_cycle_delay
;
65 int backlight_on_delay
;
66 int backlight_off_delay
;
67 struct drm_display_mode
*panel_fixed_mode
; /* for eDP */
68 struct delayed_work panel_vdd_work
;
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
79 static bool is_edp(struct intel_dp
*intel_dp
)
81 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
92 static bool is_pch_edp(struct intel_dp
*intel_dp
)
94 return intel_dp
->is_pch_edp
;
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
103 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
105 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
108 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
110 return container_of(encoder
, struct intel_dp
, base
.base
);
113 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
115 return container_of(intel_attached_encoder(connector
),
116 struct intel_dp
, base
);
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
126 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
128 struct intel_dp
*intel_dp
;
133 intel_dp
= enc_to_intel_dp(encoder
);
135 return is_pch_edp(intel_dp
);
138 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
139 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
140 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
143 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
144 int *lane_num
, int *link_bw
)
146 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
148 *lane_num
= intel_dp
->lane_count
;
149 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
151 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
156 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
158 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
159 switch (max_lane_count
) {
160 case 1: case 2: case 4:
165 return max_lane_count
;
169 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
171 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
173 switch (max_link_bw
) {
174 case DP_LINK_BW_1_62
:
178 max_link_bw
= DP_LINK_BW_1_62
;
185 intel_dp_link_clock(uint8_t link_bw
)
187 if (link_bw
== DP_LINK_BW_2_7
)
194 * The units on the numbers in the next two are... bizarre. Examples will
195 * make it clearer; this one parallels an example in the eDP spec.
197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
199 * 270000 * 1 * 8 / 10 == 216000
201 * The actual data capacity of that configuration is 2.16Gbit/s, so the
202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
204 * 119000. At 18bpp that's 2142000 kilobits per second.
206 * Thus the strange-looking division by 10 in intel_dp_link_required, to
207 * get the result in decakilobits instead of kilobits.
211 intel_dp_link_required(struct intel_dp
*intel_dp
, int pixel_clock
, int check_bpp
)
213 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
220 bpp
= intel_crtc
->bpp
;
222 return (pixel_clock
* bpp
+ 9) / 10;
226 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
228 return (max_link_clock
* max_lanes
* 8) / 10;
232 intel_dp_mode_valid(struct drm_connector
*connector
,
233 struct drm_display_mode
*mode
)
235 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
236 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
237 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
238 int max_rate
, mode_rate
;
240 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
241 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
244 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
248 mode_rate
= intel_dp_link_required(intel_dp
, mode
->clock
, 0);
249 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
251 if (mode_rate
> max_rate
) {
252 mode_rate
= intel_dp_link_required(intel_dp
,
254 if (mode_rate
> max_rate
)
255 return MODE_CLOCK_HIGH
;
257 mode
->private_flags
|= INTEL_MODE_DP_FORCE_6BPC
;
260 if (mode
->clock
< 10000)
261 return MODE_CLOCK_LOW
;
267 pack_aux(uint8_t *src
, int src_bytes
)
274 for (i
= 0; i
< src_bytes
; i
++)
275 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
280 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
285 for (i
= 0; i
< dst_bytes
; i
++)
286 dst
[i
] = src
>> ((3-i
) * 8);
289 /* hrawclock is 1/4 the FSB frequency */
291 intel_hrawclk(struct drm_device
*dev
)
293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
296 clkcfg
= I915_READ(CLKCFG
);
297 switch (clkcfg
& CLKCFG_FSB_MASK
) {
306 case CLKCFG_FSB_1067
:
308 case CLKCFG_FSB_1333
:
310 /* these two are just a guess; one of them might be right */
311 case CLKCFG_FSB_1600
:
312 case CLKCFG_FSB_1600_ALT
:
319 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
321 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
327 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
329 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
332 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
336 intel_dp_check_edp(struct intel_dp
*intel_dp
)
338 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
341 if (!is_edp(intel_dp
))
343 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
344 WARN(1, "eDP powered off while attempting aux channel communication.\n");
345 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
346 I915_READ(PCH_PP_STATUS
),
347 I915_READ(PCH_PP_CONTROL
));
352 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
353 uint8_t *send
, int send_bytes
,
354 uint8_t *recv
, int recv_size
)
356 uint32_t output_reg
= intel_dp
->output_reg
;
357 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
359 uint32_t ch_ctl
= output_reg
+ 0x10;
360 uint32_t ch_data
= ch_ctl
+ 4;
364 uint32_t aux_clock_divider
;
367 intel_dp_check_edp(intel_dp
);
368 /* The clock divider is based off the hrawclk,
369 * and would like to run at 2MHz. So, take the
370 * hrawclk value and divide by 2 and use that
372 * Note that PCH attached eDP panels should use a 125MHz input
375 if (is_cpu_edp(intel_dp
)) {
376 if (IS_GEN6(dev
) || IS_GEN7(dev
))
377 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
379 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
380 } else if (HAS_PCH_SPLIT(dev
))
381 aux_clock_divider
= 62; /* IRL input clock fixed at 125Mhz */
383 aux_clock_divider
= intel_hrawclk(dev
) / 2;
390 /* Try to wait for any previous AUX channel activity */
391 for (try = 0; try < 3; try++) {
392 status
= I915_READ(ch_ctl
);
393 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
399 WARN(1, "dp_aux_ch not started status 0x%08x\n",
404 /* Must try at least 3 times according to DP spec */
405 for (try = 0; try < 5; try++) {
406 /* Load the send data into the aux channel data registers */
407 for (i
= 0; i
< send_bytes
; i
+= 4)
408 I915_WRITE(ch_data
+ i
,
409 pack_aux(send
+ i
, send_bytes
- i
));
411 /* Send the command and wait for it to complete */
413 DP_AUX_CH_CTL_SEND_BUSY
|
414 DP_AUX_CH_CTL_TIME_OUT_400us
|
415 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
416 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
417 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
419 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
420 DP_AUX_CH_CTL_RECEIVE_ERROR
);
422 status
= I915_READ(ch_ctl
);
423 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
428 /* Clear done status and any errors */
432 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
433 DP_AUX_CH_CTL_RECEIVE_ERROR
);
434 if (status
& DP_AUX_CH_CTL_DONE
)
438 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
439 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
443 /* Check for timeout or receive error.
444 * Timeouts occur when the sink is not connected
446 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
447 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
451 /* Timeouts occur when the device isn't connected, so they're
452 * "normal" -- don't fill the kernel log with these */
453 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
454 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
458 /* Unload any bytes sent back from the other side */
459 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
460 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
461 if (recv_bytes
> recv_size
)
462 recv_bytes
= recv_size
;
464 for (i
= 0; i
< recv_bytes
; i
+= 4)
465 unpack_aux(I915_READ(ch_data
+ i
),
466 recv
+ i
, recv_bytes
- i
);
471 /* Write data to the aux channel in native mode */
473 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
474 uint16_t address
, uint8_t *send
, int send_bytes
)
481 intel_dp_check_edp(intel_dp
);
484 msg
[0] = AUX_NATIVE_WRITE
<< 4;
485 msg
[1] = address
>> 8;
486 msg
[2] = address
& 0xff;
487 msg
[3] = send_bytes
- 1;
488 memcpy(&msg
[4], send
, send_bytes
);
489 msg_bytes
= send_bytes
+ 4;
491 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
494 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
496 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
504 /* Write a single byte to the aux channel in native mode */
506 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
507 uint16_t address
, uint8_t byte
)
509 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
512 /* read bytes from a native aux channel */
514 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
515 uint16_t address
, uint8_t *recv
, int recv_bytes
)
524 intel_dp_check_edp(intel_dp
);
525 msg
[0] = AUX_NATIVE_READ
<< 4;
526 msg
[1] = address
>> 8;
527 msg
[2] = address
& 0xff;
528 msg
[3] = recv_bytes
- 1;
531 reply_bytes
= recv_bytes
+ 1;
534 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
541 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
542 memcpy(recv
, reply
+ 1, ret
- 1);
545 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
553 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
554 uint8_t write_byte
, uint8_t *read_byte
)
556 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
557 struct intel_dp
*intel_dp
= container_of(adapter
,
560 uint16_t address
= algo_data
->address
;
568 intel_dp_check_edp(intel_dp
);
569 /* Set up the command byte */
570 if (mode
& MODE_I2C_READ
)
571 msg
[0] = AUX_I2C_READ
<< 4;
573 msg
[0] = AUX_I2C_WRITE
<< 4;
575 if (!(mode
& MODE_I2C_STOP
))
576 msg
[0] |= AUX_I2C_MOT
<< 4;
578 msg
[1] = address
>> 8;
599 for (retry
= 0; retry
< 5; retry
++) {
600 ret
= intel_dp_aux_ch(intel_dp
,
604 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
608 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
609 case AUX_NATIVE_REPLY_ACK
:
610 /* I2C-over-AUX Reply field is only valid
611 * when paired with AUX ACK.
614 case AUX_NATIVE_REPLY_NACK
:
615 DRM_DEBUG_KMS("aux_ch native nack\n");
617 case AUX_NATIVE_REPLY_DEFER
:
621 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
626 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
627 case AUX_I2C_REPLY_ACK
:
628 if (mode
== MODE_I2C_READ
) {
629 *read_byte
= reply
[1];
631 return reply_bytes
- 1;
632 case AUX_I2C_REPLY_NACK
:
633 DRM_DEBUG_KMS("aux_i2c nack\n");
635 case AUX_I2C_REPLY_DEFER
:
636 DRM_DEBUG_KMS("aux_i2c defer\n");
640 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
645 DRM_ERROR("too many retries, giving up\n");
649 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
650 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
653 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
654 struct intel_connector
*intel_connector
, const char *name
)
658 DRM_DEBUG_KMS("i2c_init %s\n", name
);
659 intel_dp
->algo
.running
= false;
660 intel_dp
->algo
.address
= 0;
661 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
663 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
664 intel_dp
->adapter
.owner
= THIS_MODULE
;
665 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
666 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
667 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
668 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
669 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
671 ironlake_edp_panel_vdd_on(intel_dp
);
672 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
673 ironlake_edp_panel_vdd_off(intel_dp
, false);
678 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
679 struct drm_display_mode
*adjusted_mode
)
681 struct drm_device
*dev
= encoder
->dev
;
682 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
683 int lane_count
, clock
;
684 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
685 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
686 int bpp
= mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 0;
687 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
689 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
690 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
691 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
692 mode
, adjusted_mode
);
694 * the mode->clock is used to calculate the Data&Link M/N
695 * of the pipe. For the eDP the fixed clock should be used.
697 mode
->clock
= intel_dp
->panel_fixed_mode
->clock
;
700 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
701 for (clock
= 0; clock
<= max_clock
; clock
++) {
702 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
704 if (intel_dp_link_required(intel_dp
, mode
->clock
, bpp
)
706 intel_dp
->link_bw
= bws
[clock
];
707 intel_dp
->lane_count
= lane_count
;
708 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
709 DRM_DEBUG_KMS("Display port link bw %02x lane "
710 "count %d clock %d\n",
711 intel_dp
->link_bw
, intel_dp
->lane_count
,
712 adjusted_mode
->clock
);
721 struct intel_dp_m_n
{
730 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
732 while (*num
> 0xffffff || *den
> 0xffffff) {
739 intel_dp_compute_m_n(int bpp
,
743 struct intel_dp_m_n
*m_n
)
746 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
747 m_n
->gmch_n
= link_clock
* nlanes
;
748 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
749 m_n
->link_m
= pixel_clock
;
750 m_n
->link_n
= link_clock
;
751 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
755 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
756 struct drm_display_mode
*adjusted_mode
)
758 struct drm_device
*dev
= crtc
->dev
;
759 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
760 struct drm_encoder
*encoder
;
761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
762 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
764 struct intel_dp_m_n m_n
;
765 int pipe
= intel_crtc
->pipe
;
768 * Find the lane count in the intel_encoder private
770 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
771 struct intel_dp
*intel_dp
;
773 if (encoder
->crtc
!= crtc
)
776 intel_dp
= enc_to_intel_dp(encoder
);
777 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
778 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
780 lane_count
= intel_dp
->lane_count
;
786 * Compute the GMCH and Link ratios. The '3' here is
787 * the number of bytes_per_pixel post-LUT, which we always
788 * set up for 8-bits of R/G/B, or 3 bytes total.
790 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
791 mode
->clock
, adjusted_mode
->clock
, &m_n
);
793 if (HAS_PCH_SPLIT(dev
)) {
794 I915_WRITE(TRANSDATA_M1(pipe
),
795 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
797 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
798 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
799 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
801 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
802 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
804 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
805 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
806 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
810 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
);
811 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
);
814 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
815 struct drm_display_mode
*adjusted_mode
)
817 struct drm_device
*dev
= encoder
->dev
;
818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
819 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
820 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
821 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
823 /* Turn on the eDP PLL if needed */
824 if (is_edp(intel_dp
)) {
825 if (!is_pch_edp(intel_dp
))
826 ironlake_edp_pll_on(encoder
);
828 ironlake_edp_pll_off(encoder
);
832 * There are four kinds of DP registers:
839 * IBX PCH and CPU are the same for almost everything,
840 * except that the CPU DP PLL is configured in this
843 * CPT PCH is quite different, having many bits moved
844 * to the TRANS_DP_CTL register instead. That
845 * configuration happens (oddly) in ironlake_pch_enable
848 /* Preserve the BIOS-computed detected bit. This is
849 * supposed to be read-only.
851 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
852 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
854 /* Handle DP bits in common between all three register formats */
856 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
858 switch (intel_dp
->lane_count
) {
860 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
863 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
866 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
869 if (intel_dp
->has_audio
) {
870 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
871 pipe_name(intel_crtc
->pipe
));
872 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
873 intel_write_eld(encoder
, adjusted_mode
);
875 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
876 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
877 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
878 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
880 * Check for DPCD version > 1.1 and enhanced framing support
882 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
883 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
884 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
887 /* Split out the IBX/CPU vs CPT settings */
889 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
890 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
891 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
892 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
893 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
894 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
896 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
897 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
899 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
901 /* don't miss out required setting for eDP */
902 intel_dp
->DP
|= DP_PLL_ENABLE
;
903 if (adjusted_mode
->clock
< 200000)
904 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
906 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
907 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
908 intel_dp
->DP
|= intel_dp
->color_range
;
910 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
911 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
912 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
913 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
914 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
916 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
917 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
919 if (intel_crtc
->pipe
== 1)
920 intel_dp
->DP
|= DP_PIPEB_SELECT
;
922 if (is_cpu_edp(intel_dp
)) {
923 /* don't miss out required setting for eDP */
924 intel_dp
->DP
|= DP_PLL_ENABLE
;
925 if (adjusted_mode
->clock
< 200000)
926 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
928 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
931 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
935 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
936 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
938 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
939 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
941 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
942 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
944 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
948 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
951 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
953 I915_READ(PCH_PP_STATUS
),
954 I915_READ(PCH_PP_CONTROL
));
956 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
957 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
958 I915_READ(PCH_PP_STATUS
),
959 I915_READ(PCH_PP_CONTROL
));
963 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
965 DRM_DEBUG_KMS("Wait for panel power on\n");
966 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
969 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
971 DRM_DEBUG_KMS("Wait for panel power off time\n");
972 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
975 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
977 DRM_DEBUG_KMS("Wait for panel power cycle\n");
978 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
982 /* Read the current pp_control value, unlocking the register if it
986 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
988 u32 control
= I915_READ(PCH_PP_CONTROL
);
990 control
&= ~PANEL_UNLOCK_MASK
;
991 control
|= PANEL_UNLOCK_REGS
;
995 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
997 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1001 if (!is_edp(intel_dp
))
1003 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1005 WARN(intel_dp
->want_panel_vdd
,
1006 "eDP VDD already requested on\n");
1008 intel_dp
->want_panel_vdd
= true;
1010 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1011 DRM_DEBUG_KMS("eDP VDD already on\n");
1015 if (!ironlake_edp_have_panel_power(intel_dp
))
1016 ironlake_wait_panel_power_cycle(intel_dp
);
1018 pp
= ironlake_get_pp_control(dev_priv
);
1019 pp
|= EDP_FORCE_VDD
;
1020 I915_WRITE(PCH_PP_CONTROL
, pp
);
1021 POSTING_READ(PCH_PP_CONTROL
);
1022 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1023 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1026 * If the panel wasn't on, delay before accessing aux channel
1028 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1029 DRM_DEBUG_KMS("eDP was not running\n");
1030 msleep(intel_dp
->panel_power_up_delay
);
1034 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1036 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1041 pp
= ironlake_get_pp_control(dev_priv
);
1042 pp
&= ~EDP_FORCE_VDD
;
1043 I915_WRITE(PCH_PP_CONTROL
, pp
);
1044 POSTING_READ(PCH_PP_CONTROL
);
1046 /* Make sure sequencer is idle before allowing subsequent activity */
1047 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1048 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1050 msleep(intel_dp
->panel_power_down_delay
);
1054 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1056 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1057 struct intel_dp
, panel_vdd_work
);
1058 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1060 mutex_lock(&dev
->mode_config
.mutex
);
1061 ironlake_panel_vdd_off_sync(intel_dp
);
1062 mutex_unlock(&dev
->mode_config
.mutex
);
1065 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1067 if (!is_edp(intel_dp
))
1070 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1071 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1073 intel_dp
->want_panel_vdd
= false;
1076 ironlake_panel_vdd_off_sync(intel_dp
);
1079 * Queue the timer to fire a long
1080 * time from now (relative to the power down delay)
1081 * to keep the panel power up across a sequence of operations
1083 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1084 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1088 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1090 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1094 if (!is_edp(intel_dp
))
1097 DRM_DEBUG_KMS("Turn eDP power on\n");
1099 if (ironlake_edp_have_panel_power(intel_dp
)) {
1100 DRM_DEBUG_KMS("eDP power already on\n");
1104 ironlake_wait_panel_power_cycle(intel_dp
);
1106 pp
= ironlake_get_pp_control(dev_priv
);
1108 /* ILK workaround: disable reset around power sequence */
1109 pp
&= ~PANEL_POWER_RESET
;
1110 I915_WRITE(PCH_PP_CONTROL
, pp
);
1111 POSTING_READ(PCH_PP_CONTROL
);
1114 pp
|= POWER_TARGET_ON
;
1116 pp
|= PANEL_POWER_RESET
;
1118 I915_WRITE(PCH_PP_CONTROL
, pp
);
1119 POSTING_READ(PCH_PP_CONTROL
);
1121 ironlake_wait_panel_on(intel_dp
);
1124 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1125 I915_WRITE(PCH_PP_CONTROL
, pp
);
1126 POSTING_READ(PCH_PP_CONTROL
);
1130 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1132 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1136 if (!is_edp(intel_dp
))
1139 DRM_DEBUG_KMS("Turn eDP power off\n");
1141 WARN(intel_dp
->want_panel_vdd
, "Cannot turn power off while VDD is on\n");
1143 pp
= ironlake_get_pp_control(dev_priv
);
1144 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1145 I915_WRITE(PCH_PP_CONTROL
, pp
);
1146 POSTING_READ(PCH_PP_CONTROL
);
1148 ironlake_wait_panel_off(intel_dp
);
1151 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1153 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1157 if (!is_edp(intel_dp
))
1160 DRM_DEBUG_KMS("\n");
1162 * If we enable the backlight right away following a panel power
1163 * on, we may see slight flicker as the panel syncs with the eDP
1164 * link. So delay a bit to make sure the image is solid before
1165 * allowing it to appear.
1167 msleep(intel_dp
->backlight_on_delay
);
1168 pp
= ironlake_get_pp_control(dev_priv
);
1169 pp
|= EDP_BLC_ENABLE
;
1170 I915_WRITE(PCH_PP_CONTROL
, pp
);
1171 POSTING_READ(PCH_PP_CONTROL
);
1174 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1176 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 if (!is_edp(intel_dp
))
1183 DRM_DEBUG_KMS("\n");
1184 pp
= ironlake_get_pp_control(dev_priv
);
1185 pp
&= ~EDP_BLC_ENABLE
;
1186 I915_WRITE(PCH_PP_CONTROL
, pp
);
1187 POSTING_READ(PCH_PP_CONTROL
);
1188 msleep(intel_dp
->backlight_off_delay
);
1191 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
1193 struct drm_device
*dev
= encoder
->dev
;
1194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1197 DRM_DEBUG_KMS("\n");
1198 dpa_ctl
= I915_READ(DP_A
);
1199 dpa_ctl
|= DP_PLL_ENABLE
;
1200 I915_WRITE(DP_A
, dpa_ctl
);
1205 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
1207 struct drm_device
*dev
= encoder
->dev
;
1208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1211 dpa_ctl
= I915_READ(DP_A
);
1212 dpa_ctl
&= ~DP_PLL_ENABLE
;
1213 I915_WRITE(DP_A
, dpa_ctl
);
1218 /* If the sink supports it, try to set the power state appropriately */
1219 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1223 /* Should have a valid DPCD by this point */
1224 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1227 if (mode
!= DRM_MODE_DPMS_ON
) {
1228 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1231 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1234 * When turning on, we need to retry for 1ms to give the sink
1237 for (i
= 0; i
< 3; i
++) {
1238 ret
= intel_dp_aux_native_write_1(intel_dp
,
1248 static void intel_dp_prepare(struct drm_encoder
*encoder
)
1250 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1252 ironlake_edp_backlight_off(intel_dp
);
1253 ironlake_edp_panel_off(intel_dp
);
1255 /* Wake up the sink first */
1256 ironlake_edp_panel_vdd_on(intel_dp
);
1257 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1258 intel_dp_link_down(intel_dp
);
1259 ironlake_edp_panel_vdd_off(intel_dp
, false);
1261 /* Make sure the panel is off before trying to
1266 static void intel_dp_commit(struct drm_encoder
*encoder
)
1268 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1269 struct drm_device
*dev
= encoder
->dev
;
1270 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1272 ironlake_edp_panel_vdd_on(intel_dp
);
1273 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1274 intel_dp_start_link_train(intel_dp
);
1275 ironlake_edp_panel_on(intel_dp
);
1276 ironlake_edp_panel_vdd_off(intel_dp
, true);
1277 intel_dp_complete_link_train(intel_dp
);
1278 ironlake_edp_backlight_on(intel_dp
);
1280 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1282 if (HAS_PCH_CPT(dev
))
1283 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
1287 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
1289 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1290 struct drm_device
*dev
= encoder
->dev
;
1291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1292 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1294 if (mode
!= DRM_MODE_DPMS_ON
) {
1295 ironlake_edp_backlight_off(intel_dp
);
1296 ironlake_edp_panel_off(intel_dp
);
1298 ironlake_edp_panel_vdd_on(intel_dp
);
1299 intel_dp_sink_dpms(intel_dp
, mode
);
1300 intel_dp_link_down(intel_dp
);
1301 ironlake_edp_panel_vdd_off(intel_dp
, false);
1303 if (is_cpu_edp(intel_dp
))
1304 ironlake_edp_pll_off(encoder
);
1306 if (is_cpu_edp(intel_dp
))
1307 ironlake_edp_pll_on(encoder
);
1309 ironlake_edp_panel_vdd_on(intel_dp
);
1310 intel_dp_sink_dpms(intel_dp
, mode
);
1311 if (!(dp_reg
& DP_PORT_EN
)) {
1312 intel_dp_start_link_train(intel_dp
);
1313 ironlake_edp_panel_on(intel_dp
);
1314 ironlake_edp_panel_vdd_off(intel_dp
, true);
1315 intel_dp_complete_link_train(intel_dp
);
1317 ironlake_edp_panel_vdd_off(intel_dp
, false);
1318 ironlake_edp_backlight_on(intel_dp
);
1320 intel_dp
->dpms_mode
= mode
;
1324 * Native read with retry for link status and receiver capability reads for
1325 * cases where the sink may still be asleep.
1328 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1329 uint8_t *recv
, int recv_bytes
)
1334 * Sinks are *supposed* to come up within 1ms from an off state,
1335 * but we're also supposed to retry 3 times per the spec.
1337 for (i
= 0; i
< 3; i
++) {
1338 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1340 if (ret
== recv_bytes
)
1349 * Fetch AUX CH registers 0x202 - 0x207 which contain
1350 * link status information
1353 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1355 return intel_dp_aux_native_read_retry(intel_dp
,
1358 DP_LINK_STATUS_SIZE
);
1362 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1365 return link_status
[r
- DP_LANE0_1_STATUS
];
1369 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1372 int s
= ((lane
& 1) ?
1373 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1374 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1375 uint8_t l
= adjust_request
[lane
>>1];
1377 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1381 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1384 int s
= ((lane
& 1) ?
1385 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1386 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1387 uint8_t l
= adjust_request
[lane
>>1];
1389 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1394 static char *voltage_names
[] = {
1395 "0.4V", "0.6V", "0.8V", "1.2V"
1397 static char *pre_emph_names
[] = {
1398 "0dB", "3.5dB", "6dB", "9.5dB"
1400 static char *link_train_names
[] = {
1401 "pattern 1", "pattern 2", "idle", "off"
1406 * These are source-specific values; current Intel hardware supports
1407 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1411 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1413 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1415 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1416 return DP_TRAIN_VOLTAGE_SWING_800
;
1417 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1418 return DP_TRAIN_VOLTAGE_SWING_1200
;
1420 return DP_TRAIN_VOLTAGE_SWING_800
;
1424 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1426 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1428 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1429 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1430 case DP_TRAIN_VOLTAGE_SWING_400
:
1431 return DP_TRAIN_PRE_EMPHASIS_6
;
1432 case DP_TRAIN_VOLTAGE_SWING_600
:
1433 case DP_TRAIN_VOLTAGE_SWING_800
:
1434 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1436 return DP_TRAIN_PRE_EMPHASIS_0
;
1439 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1440 case DP_TRAIN_VOLTAGE_SWING_400
:
1441 return DP_TRAIN_PRE_EMPHASIS_6
;
1442 case DP_TRAIN_VOLTAGE_SWING_600
:
1443 return DP_TRAIN_PRE_EMPHASIS_6
;
1444 case DP_TRAIN_VOLTAGE_SWING_800
:
1445 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1446 case DP_TRAIN_VOLTAGE_SWING_1200
:
1448 return DP_TRAIN_PRE_EMPHASIS_0
;
1454 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1459 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1460 uint8_t voltage_max
;
1461 uint8_t preemph_max
;
1463 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1464 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1465 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1473 voltage_max
= intel_dp_voltage_max(intel_dp
);
1474 if (v
>= voltage_max
)
1475 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1477 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1478 if (p
>= preemph_max
)
1479 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1481 for (lane
= 0; lane
< 4; lane
++)
1482 intel_dp
->train_set
[lane
] = v
| p
;
1486 intel_dp_signal_levels(uint8_t train_set
)
1488 uint32_t signal_levels
= 0;
1490 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1491 case DP_TRAIN_VOLTAGE_SWING_400
:
1493 signal_levels
|= DP_VOLTAGE_0_4
;
1495 case DP_TRAIN_VOLTAGE_SWING_600
:
1496 signal_levels
|= DP_VOLTAGE_0_6
;
1498 case DP_TRAIN_VOLTAGE_SWING_800
:
1499 signal_levels
|= DP_VOLTAGE_0_8
;
1501 case DP_TRAIN_VOLTAGE_SWING_1200
:
1502 signal_levels
|= DP_VOLTAGE_1_2
;
1505 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1506 case DP_TRAIN_PRE_EMPHASIS_0
:
1508 signal_levels
|= DP_PRE_EMPHASIS_0
;
1510 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1511 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1513 case DP_TRAIN_PRE_EMPHASIS_6
:
1514 signal_levels
|= DP_PRE_EMPHASIS_6
;
1516 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1517 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1520 return signal_levels
;
1523 /* Gen6's DP voltage swing and pre-emphasis control */
1525 intel_gen6_edp_signal_levels(uint8_t train_set
)
1527 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1528 DP_TRAIN_PRE_EMPHASIS_MASK
);
1529 switch (signal_levels
) {
1530 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1531 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1532 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1533 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1534 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1535 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1536 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1537 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1538 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1539 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1540 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1541 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1542 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1543 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1545 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1546 "0x%x\n", signal_levels
);
1547 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1551 /* Gen7's DP voltage swing and pre-emphasis control */
1553 intel_gen7_edp_signal_levels(uint8_t train_set
)
1555 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1556 DP_TRAIN_PRE_EMPHASIS_MASK
);
1557 switch (signal_levels
) {
1558 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1559 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1560 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1561 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1562 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1563 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1565 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1566 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1567 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1568 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1570 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1571 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1572 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1573 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1576 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1577 "0x%x\n", signal_levels
);
1578 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1583 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1586 int s
= (lane
& 1) * 4;
1587 uint8_t l
= link_status
[lane
>>1];
1589 return (l
>> s
) & 0xf;
1592 /* Check for clock recovery is done on all channels */
1594 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1597 uint8_t lane_status
;
1599 for (lane
= 0; lane
< lane_count
; lane
++) {
1600 lane_status
= intel_get_lane_status(link_status
, lane
);
1601 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1607 /* Check to see if channel eq is done on all channels */
1608 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1609 DP_LANE_CHANNEL_EQ_DONE|\
1610 DP_LANE_SYMBOL_LOCKED)
1612 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1615 uint8_t lane_status
;
1618 lane_align
= intel_dp_link_status(link_status
,
1619 DP_LANE_ALIGN_STATUS_UPDATED
);
1620 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1622 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1623 lane_status
= intel_get_lane_status(link_status
, lane
);
1624 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1631 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1632 uint32_t dp_reg_value
,
1633 uint8_t dp_train_pat
)
1635 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1639 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1640 POSTING_READ(intel_dp
->output_reg
);
1642 intel_dp_aux_native_write_1(intel_dp
,
1643 DP_TRAINING_PATTERN_SET
,
1646 ret
= intel_dp_aux_native_write(intel_dp
,
1647 DP_TRAINING_LANE0_SET
,
1648 intel_dp
->train_set
,
1649 intel_dp
->lane_count
);
1650 if (ret
!= intel_dp
->lane_count
)
1656 /* Enable corresponding port and start training pattern 1 */
1658 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1660 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1662 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1665 bool clock_recovery
= false;
1666 int voltage_tries
, loop_tries
;
1668 uint32_t DP
= intel_dp
->DP
;
1671 * On CPT we have to enable the port in training pattern 1, which
1672 * will happen below in intel_dp_set_link_train. Otherwise, enable
1673 * the port and wait for it to become active.
1675 if (!HAS_PCH_CPT(dev
)) {
1676 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
1677 POSTING_READ(intel_dp
->output_reg
);
1678 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1681 /* Write the link configuration data */
1682 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1683 intel_dp
->link_configuration
,
1684 DP_LINK_CONFIGURATION_SIZE
);
1688 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1689 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1691 DP
&= ~DP_LINK_TRAIN_MASK
;
1692 memset(intel_dp
->train_set
, 0, 4);
1696 clock_recovery
= false;
1698 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1699 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1700 uint32_t signal_levels
;
1703 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1704 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1705 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1706 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1707 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1708 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1710 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1711 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels
);
1712 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1715 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1716 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1718 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1720 if (!intel_dp_set_link_train(intel_dp
, reg
,
1721 DP_TRAINING_PATTERN_1
|
1722 DP_LINK_SCRAMBLING_DISABLE
))
1724 /* Set training pattern 1 */
1727 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1728 DRM_ERROR("failed to get link status\n");
1732 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1733 DRM_DEBUG_KMS("clock recovery OK\n");
1734 clock_recovery
= true;
1738 /* Check to see if we've tried the max voltage */
1739 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1740 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1742 if (i
== intel_dp
->lane_count
) {
1744 if (loop_tries
== 5) {
1745 DRM_DEBUG_KMS("too many full retries, give up\n");
1748 memset(intel_dp
->train_set
, 0, 4);
1753 /* Check to see if we've tried the same voltage 5 times */
1754 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1756 if (voltage_tries
== 5) {
1757 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1762 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1764 /* Compute new intel_dp->train_set as requested by target */
1765 intel_get_adjust_train(intel_dp
, link_status
);
1772 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1774 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1776 bool channel_eq
= false;
1777 int tries
, cr_tries
;
1779 uint32_t DP
= intel_dp
->DP
;
1781 /* channel equalization */
1786 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1787 uint32_t signal_levels
;
1788 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1791 DRM_ERROR("failed to train DP, aborting\n");
1792 intel_dp_link_down(intel_dp
);
1796 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1797 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1798 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1799 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1800 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1801 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1803 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1804 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1807 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1808 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1810 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1812 /* channel eq pattern */
1813 if (!intel_dp_set_link_train(intel_dp
, reg
,
1814 DP_TRAINING_PATTERN_2
|
1815 DP_LINK_SCRAMBLING_DISABLE
))
1819 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1822 /* Make sure clock is still ok */
1823 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1824 intel_dp_start_link_train(intel_dp
);
1829 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
1834 /* Try 5 times, then try clock recovery if that fails */
1836 intel_dp_link_down(intel_dp
);
1837 intel_dp_start_link_train(intel_dp
);
1843 /* Compute new intel_dp->train_set as requested by target */
1844 intel_get_adjust_train(intel_dp
, link_status
);
1848 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1849 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1851 reg
= DP
| DP_LINK_TRAIN_OFF
;
1853 I915_WRITE(intel_dp
->output_reg
, reg
);
1854 POSTING_READ(intel_dp
->output_reg
);
1855 intel_dp_aux_native_write_1(intel_dp
,
1856 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1860 intel_dp_link_down(struct intel_dp
*intel_dp
)
1862 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 uint32_t DP
= intel_dp
->DP
;
1866 if ((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0)
1869 DRM_DEBUG_KMS("\n");
1871 if (is_edp(intel_dp
)) {
1872 DP
&= ~DP_PLL_ENABLE
;
1873 I915_WRITE(intel_dp
->output_reg
, DP
);
1874 POSTING_READ(intel_dp
->output_reg
);
1878 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1879 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1880 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1882 DP
&= ~DP_LINK_TRAIN_MASK
;
1883 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1885 POSTING_READ(intel_dp
->output_reg
);
1889 if (is_edp(intel_dp
)) {
1890 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1891 DP
|= DP_LINK_TRAIN_OFF_CPT
;
1893 DP
|= DP_LINK_TRAIN_OFF
;
1896 if (!HAS_PCH_CPT(dev
) &&
1897 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1898 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1900 /* Hardware workaround: leaving our transcoder select
1901 * set to transcoder B while it's off will prevent the
1902 * corresponding HDMI output on transcoder A.
1904 * Combine this with another hardware workaround:
1905 * transcoder select bit can only be cleared while the
1908 DP
&= ~DP_PIPEB_SELECT
;
1909 I915_WRITE(intel_dp
->output_reg
, DP
);
1911 /* Changes to enable or select take place the vblank
1912 * after being written.
1915 /* We can arrive here never having been attached
1916 * to a CRTC, for instance, due to inheriting
1917 * random state from the BIOS.
1919 * If the pipe is not running, play safe and
1920 * wait for the clocks to stabilise before
1923 POSTING_READ(intel_dp
->output_reg
);
1926 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
1929 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1930 POSTING_READ(intel_dp
->output_reg
);
1931 msleep(intel_dp
->panel_power_down_delay
);
1935 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
1937 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
1938 sizeof(intel_dp
->dpcd
)) &&
1939 (intel_dp
->dpcd
[DP_DPCD_REV
] != 0)) {
1947 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
1951 ret
= intel_dp_aux_native_read_retry(intel_dp
,
1952 DP_DEVICE_SERVICE_IRQ_VECTOR
,
1953 sink_irq_vector
, 1);
1961 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
1963 /* NAK by default */
1964 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
1968 * According to DP spec
1971 * 2. Configure link according to Receiver Capabilities
1972 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1973 * 4. Check link status on receipt of hot-plug interrupt
1977 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
1980 u8 link_status
[DP_LINK_STATUS_SIZE
];
1982 if (intel_dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
1985 if (!intel_dp
->base
.base
.crtc
)
1988 /* Try to read receiver status if the link appears to be up */
1989 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1990 intel_dp_link_down(intel_dp
);
1994 /* Now read the DPCD to see if it's actually running */
1995 if (!intel_dp_get_dpcd(intel_dp
)) {
1996 intel_dp_link_down(intel_dp
);
2000 /* Try to read the source of the interrupt */
2001 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2002 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2003 /* Clear interrupt source */
2004 intel_dp_aux_native_write_1(intel_dp
,
2005 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2008 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2009 intel_dp_handle_test_request(intel_dp
);
2010 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2011 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2014 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
2015 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2016 drm_get_encoder_name(&intel_dp
->base
.base
));
2017 intel_dp_start_link_train(intel_dp
);
2018 intel_dp_complete_link_train(intel_dp
);
2022 static enum drm_connector_status
2023 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2025 if (intel_dp_get_dpcd(intel_dp
))
2026 return connector_status_connected
;
2027 return connector_status_disconnected
;
2030 static enum drm_connector_status
2031 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2033 enum drm_connector_status status
;
2035 /* Can't disconnect eDP, but you can close the lid... */
2036 if (is_edp(intel_dp
)) {
2037 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2038 if (status
== connector_status_unknown
)
2039 status
= connector_status_connected
;
2043 return intel_dp_detect_dpcd(intel_dp
);
2046 static enum drm_connector_status
2047 g4x_dp_detect(struct intel_dp
*intel_dp
)
2049 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2053 switch (intel_dp
->output_reg
) {
2055 bit
= DPB_HOTPLUG_INT_STATUS
;
2058 bit
= DPC_HOTPLUG_INT_STATUS
;
2061 bit
= DPD_HOTPLUG_INT_STATUS
;
2064 return connector_status_unknown
;
2067 temp
= I915_READ(PORT_HOTPLUG_STAT
);
2069 if ((temp
& bit
) == 0)
2070 return connector_status_disconnected
;
2072 return intel_dp_detect_dpcd(intel_dp
);
2075 static struct edid
*
2076 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2078 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2081 ironlake_edp_panel_vdd_on(intel_dp
);
2082 edid
= drm_get_edid(connector
, adapter
);
2083 ironlake_edp_panel_vdd_off(intel_dp
, false);
2088 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2090 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2093 ironlake_edp_panel_vdd_on(intel_dp
);
2094 ret
= intel_ddc_get_modes(connector
, adapter
);
2095 ironlake_edp_panel_vdd_off(intel_dp
, false);
2101 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2103 * \return true if DP port is connected.
2104 * \return false if DP port is disconnected.
2106 static enum drm_connector_status
2107 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2109 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2110 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2111 enum drm_connector_status status
;
2112 struct edid
*edid
= NULL
;
2114 intel_dp
->has_audio
= false;
2116 if (HAS_PCH_SPLIT(dev
))
2117 status
= ironlake_dp_detect(intel_dp
);
2119 status
= g4x_dp_detect(intel_dp
);
2121 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2122 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2123 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2124 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2126 if (status
!= connector_status_connected
)
2129 if (intel_dp
->force_audio
) {
2130 intel_dp
->has_audio
= intel_dp
->force_audio
> 0;
2132 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2134 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2135 connector
->display_info
.raw_edid
= NULL
;
2140 return connector_status_connected
;
2143 static int intel_dp_get_modes(struct drm_connector
*connector
)
2145 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2146 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2150 /* We should parse the EDID data and find out if it has an audio sink
2153 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2155 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2156 struct drm_display_mode
*newmode
;
2157 list_for_each_entry(newmode
, &connector
->probed_modes
,
2159 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2160 intel_dp
->panel_fixed_mode
=
2161 drm_mode_duplicate(dev
, newmode
);
2169 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2170 if (is_edp(intel_dp
)) {
2171 /* initialize panel mode from VBT if available for eDP */
2172 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2173 intel_dp
->panel_fixed_mode
=
2174 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2175 if (intel_dp
->panel_fixed_mode
) {
2176 intel_dp
->panel_fixed_mode
->type
|=
2177 DRM_MODE_TYPE_PREFERRED
;
2180 if (intel_dp
->panel_fixed_mode
) {
2181 struct drm_display_mode
*mode
;
2182 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2183 drm_mode_probed_add(connector
, mode
);
2191 intel_dp_detect_audio(struct drm_connector
*connector
)
2193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2195 bool has_audio
= false;
2197 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2199 has_audio
= drm_detect_monitor_audio(edid
);
2201 connector
->display_info
.raw_edid
= NULL
;
2209 intel_dp_set_property(struct drm_connector
*connector
,
2210 struct drm_property
*property
,
2213 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2214 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2217 ret
= drm_connector_property_set_value(connector
, property
, val
);
2221 if (property
== dev_priv
->force_audio_property
) {
2225 if (i
== intel_dp
->force_audio
)
2228 intel_dp
->force_audio
= i
;
2231 has_audio
= intel_dp_detect_audio(connector
);
2235 if (has_audio
== intel_dp
->has_audio
)
2238 intel_dp
->has_audio
= has_audio
;
2242 if (property
== dev_priv
->broadcast_rgb_property
) {
2243 if (val
== !!intel_dp
->color_range
)
2246 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2253 if (intel_dp
->base
.base
.crtc
) {
2254 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2255 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
2264 intel_dp_destroy(struct drm_connector
*connector
)
2266 struct drm_device
*dev
= connector
->dev
;
2268 if (intel_dpd_is_edp(dev
))
2269 intel_panel_destroy_backlight(dev
);
2271 drm_sysfs_connector_remove(connector
);
2272 drm_connector_cleanup(connector
);
2276 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2278 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2280 i2c_del_adapter(&intel_dp
->adapter
);
2281 drm_encoder_cleanup(encoder
);
2282 if (is_edp(intel_dp
)) {
2283 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2284 ironlake_panel_vdd_off_sync(intel_dp
);
2289 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2290 .dpms
= intel_dp_dpms
,
2291 .mode_fixup
= intel_dp_mode_fixup
,
2292 .prepare
= intel_dp_prepare
,
2293 .mode_set
= intel_dp_mode_set
,
2294 .commit
= intel_dp_commit
,
2297 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2298 .dpms
= drm_helper_connector_dpms
,
2299 .detect
= intel_dp_detect
,
2300 .fill_modes
= drm_helper_probe_single_connector_modes
,
2301 .set_property
= intel_dp_set_property
,
2302 .destroy
= intel_dp_destroy
,
2305 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2306 .get_modes
= intel_dp_get_modes
,
2307 .mode_valid
= intel_dp_mode_valid
,
2308 .best_encoder
= intel_best_encoder
,
2311 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2312 .destroy
= intel_dp_encoder_destroy
,
2316 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2318 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2320 intel_dp_check_link_status(intel_dp
);
2323 /* Return which DP Port should be selected for Transcoder DP control */
2325 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2327 struct drm_device
*dev
= crtc
->dev
;
2328 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2329 struct drm_encoder
*encoder
;
2331 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
2332 struct intel_dp
*intel_dp
;
2334 if (encoder
->crtc
!= crtc
)
2337 intel_dp
= enc_to_intel_dp(encoder
);
2338 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2339 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2340 return intel_dp
->output_reg
;
2346 /* check the VBT to see whether the eDP is on DP-D port */
2347 bool intel_dpd_is_edp(struct drm_device
*dev
)
2349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2350 struct child_device_config
*p_child
;
2353 if (!dev_priv
->child_dev_num
)
2356 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2357 p_child
= dev_priv
->child_dev
+ i
;
2359 if (p_child
->dvo_port
== PORT_IDPD
&&
2360 p_child
->device_type
== DEVICE_TYPE_eDP
)
2367 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2369 intel_attach_force_audio_property(connector
);
2370 intel_attach_broadcast_rgb_property(connector
);
2374 intel_dp_init(struct drm_device
*dev
, int output_reg
)
2376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2377 struct drm_connector
*connector
;
2378 struct intel_dp
*intel_dp
;
2379 struct intel_encoder
*intel_encoder
;
2380 struct intel_connector
*intel_connector
;
2381 const char *name
= NULL
;
2384 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2388 intel_dp
->output_reg
= output_reg
;
2389 intel_dp
->dpms_mode
= -1;
2391 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2392 if (!intel_connector
) {
2396 intel_encoder
= &intel_dp
->base
;
2398 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2399 if (intel_dpd_is_edp(dev
))
2400 intel_dp
->is_pch_edp
= true;
2402 if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2403 type
= DRM_MODE_CONNECTOR_eDP
;
2404 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2406 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2407 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2410 connector
= &intel_connector
->base
;
2411 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2412 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2414 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2416 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
2417 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
2418 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
2419 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
2420 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
2421 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
2423 if (is_edp(intel_dp
)) {
2424 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
2425 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2426 ironlake_panel_vdd_work
);
2429 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2430 connector
->interlace_allowed
= true;
2431 connector
->doublescan_allowed
= 0;
2433 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2434 DRM_MODE_ENCODER_TMDS
);
2435 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2437 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2438 drm_sysfs_connector_add(connector
);
2440 /* Set up the DDC bus. */
2441 switch (output_reg
) {
2447 dev_priv
->hotplug_supported_mask
|=
2448 HDMIB_HOTPLUG_INT_STATUS
;
2453 dev_priv
->hotplug_supported_mask
|=
2454 HDMIC_HOTPLUG_INT_STATUS
;
2459 dev_priv
->hotplug_supported_mask
|=
2460 HDMID_HOTPLUG_INT_STATUS
;
2465 /* Cache some DPCD data in the eDP case */
2466 if (is_edp(intel_dp
)) {
2468 struct edp_power_seq cur
, vbt
;
2469 u32 pp_on
, pp_off
, pp_div
;
2471 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2472 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2473 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2475 /* Pull timing values out of registers */
2476 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2477 PANEL_POWER_UP_DELAY_SHIFT
;
2479 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2480 PANEL_LIGHT_ON_DELAY_SHIFT
;
2482 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2483 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2485 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2486 PANEL_POWER_DOWN_DELAY_SHIFT
;
2488 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2489 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2491 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2492 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2494 vbt
= dev_priv
->edp
.pps
;
2496 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2497 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2499 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2501 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2502 intel_dp
->backlight_on_delay
= get_delay(t8
);
2503 intel_dp
->backlight_off_delay
= get_delay(t9
);
2504 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2505 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2507 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2508 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2509 intel_dp
->panel_power_cycle_delay
);
2511 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2512 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2514 ironlake_edp_panel_vdd_on(intel_dp
);
2515 ret
= intel_dp_get_dpcd(intel_dp
);
2516 ironlake_edp_panel_vdd_off(intel_dp
, false);
2519 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2520 dev_priv
->no_aux_handshake
=
2521 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2522 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2524 /* if this fails, presume the device is a ghost */
2525 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2526 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2527 intel_dp_destroy(&intel_connector
->base
);
2532 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2534 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2536 if (is_edp(intel_dp
)) {
2537 dev_priv
->int_edp_connector
= connector
;
2538 intel_panel_setup_backlight(dev
);
2541 intel_dp_add_properties(intel_dp
, connector
);
2543 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2544 * 0xd. Failure to do so will result in spurious interrupts being
2545 * generated on the port when a cable is not attached.
2547 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2548 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2549 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);