2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
293 static void pps_lock(struct intel_dp
*intel_dp
)
295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
296 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
297 struct drm_device
*dev
= encoder
->base
.dev
;
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 enum intel_display_power_domain power_domain
;
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
305 power_domain
= intel_display_port_power_domain(encoder
);
306 intel_display_power_get(dev_priv
, power_domain
);
308 mutex_lock(&dev_priv
->pps_mutex
);
311 static void pps_unlock(struct intel_dp
*intel_dp
)
313 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
314 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
315 struct drm_device
*dev
= encoder
->base
.dev
;
316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 enum intel_display_power_domain power_domain
;
319 mutex_unlock(&dev_priv
->pps_mutex
);
321 power_domain
= intel_display_port_power_domain(encoder
);
322 intel_display_power_put(dev_priv
, power_domain
);
326 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
328 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
329 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
331 struct intel_encoder
*encoder
;
332 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
333 struct edp_power_seq power_seq
;
335 lockdep_assert_held(&dev_priv
->pps_mutex
);
337 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
338 return intel_dp
->pps_pipe
;
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
344 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
346 struct intel_dp
*tmp
;
348 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
351 tmp
= enc_to_intel_dp(&encoder
->base
);
353 if (tmp
->pps_pipe
!= INVALID_PIPE
)
354 pipes
&= ~(1 << tmp
->pps_pipe
);
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
361 if (WARN_ON(pipes
== 0))
364 intel_dp
->pps_pipe
= ffs(pipes
) - 1;
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp
->pps_pipe
),
368 port_name(intel_dig_port
->port
));
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
372 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
375 return intel_dp
->pps_pipe
;
378 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
381 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
387 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
393 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
400 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
402 vlv_pipe_check pipe_check
)
406 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
407 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
408 PANEL_PORT_SELECT_MASK
;
410 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
413 if (!pipe_check(dev_priv
, pipe
))
423 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
425 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
426 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
428 struct edp_power_seq power_seq
;
429 enum port port
= intel_dig_port
->port
;
431 lockdep_assert_held(&dev_priv
->pps_mutex
);
433 /* try to find a pipe with this port selected */
434 /* first pick one where the panel is on */
435 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
439 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
440 vlv_pipe_has_vdd_on
);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
443 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
456 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
457 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
461 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
463 struct drm_device
*dev
= dev_priv
->dev
;
464 struct intel_encoder
*encoder
;
466 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
479 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
480 struct intel_dp
*intel_dp
;
482 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
485 intel_dp
= enc_to_intel_dp(&encoder
->base
);
486 intel_dp
->pps_pipe
= INVALID_PIPE
;
490 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
492 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
494 if (HAS_PCH_SPLIT(dev
))
495 return PCH_PP_CONTROL
;
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
500 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
502 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
504 if (HAS_PCH_SPLIT(dev
))
505 return PCH_PP_STATUS
;
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
510 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
515 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
517 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
520 u32 pp_ctrl_reg
, pp_div_reg
;
522 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
527 if (IS_VALLEYVIEW(dev
)) {
528 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
530 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
531 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
532 pp_div
= I915_READ(pp_div_reg
);
533 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
537 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
538 msleep(intel_dp
->panel_power_cycle_delay
);
541 pps_unlock(intel_dp
);
546 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
548 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
551 lockdep_assert_held(&dev_priv
->pps_mutex
);
553 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
556 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
558 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
561 lockdep_assert_held(&dev_priv
->pps_mutex
);
563 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
567 intel_dp_check_edp(struct intel_dp
*intel_dp
)
569 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
572 if (!is_edp(intel_dp
))
575 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
578 I915_READ(_pp_stat_reg(intel_dp
)),
579 I915_READ(_pp_ctrl_reg(intel_dp
)));
584 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
586 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
587 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
589 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
593 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
595 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
596 msecs_to_jiffies_timeout(10));
598 done
= wait_for_atomic(C
, 10) == 0;
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
607 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
609 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
610 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
616 return index
? 0 : intel_hrawclk(dev
) / 2;
619 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
621 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
622 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
627 if (intel_dig_port
->port
== PORT_A
) {
628 if (IS_GEN6(dev
) || IS_GEN7(dev
))
629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
631 return 225; /* eDP input clock at 450Mhz */
633 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
637 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
639 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
640 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
643 if (intel_dig_port
->port
== PORT_A
) {
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
647 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
648 /* Workaround for non-ULT HSW */
655 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
659 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
661 return index
? 0 : 100;
664 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
667 uint32_t aux_clock_divider
)
669 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
670 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
671 uint32_t precharge
, timeout
;
678 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
679 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
681 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
683 return DP_AUX_CH_CTL_SEND_BUSY
|
685 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
686 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
688 DP_AUX_CH_CTL_RECEIVE_ERROR
|
689 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
690 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
691 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
695 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
696 uint8_t *send
, int send_bytes
,
697 uint8_t *recv
, int recv_size
)
699 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
700 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
702 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
703 uint32_t ch_data
= ch_ctl
+ 4;
704 uint32_t aux_clock_divider
;
705 int i
, ret
, recv_bytes
;
708 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
719 vdd
= edp_panel_vdd_on(intel_dp
);
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
725 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
727 intel_dp_check_edp(intel_dp
);
729 intel_aux_display_runtime_get(dev_priv
);
731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
733 status
= I915_READ_NOTRACE(ch_ctl
);
734 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
752 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
753 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i
= 0; i
< send_bytes
; i
+= 4)
762 I915_WRITE(ch_data
+ i
,
763 pack_aux(send
+ i
, send_bytes
- i
));
765 /* Send the command and wait for it to complete */
766 I915_WRITE(ch_ctl
, send_ctl
);
768 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
770 /* Clear done status and any errors */
774 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
775 DP_AUX_CH_CTL_RECEIVE_ERROR
);
777 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
778 DP_AUX_CH_CTL_RECEIVE_ERROR
))
780 if (status
& DP_AUX_CH_CTL_DONE
)
783 if (status
& DP_AUX_CH_CTL_DONE
)
787 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
796 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
804 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
810 /* Unload any bytes sent back from the other side */
811 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
813 if (recv_bytes
> recv_size
)
814 recv_bytes
= recv_size
;
816 for (i
= 0; i
< recv_bytes
; i
+= 4)
817 unpack_aux(I915_READ(ch_data
+ i
),
818 recv
+ i
, recv_bytes
- i
);
822 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
823 intel_aux_display_runtime_put(dev_priv
);
826 edp_panel_vdd_off(intel_dp
, false);
828 pps_unlock(intel_dp
);
833 #define BARE_ADDRESS_SIZE 3
834 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
836 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
838 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
839 uint8_t txbuf
[20], rxbuf
[20];
840 size_t txsize
, rxsize
;
843 txbuf
[0] = msg
->request
<< 4;
844 txbuf
[1] = msg
->address
>> 8;
845 txbuf
[2] = msg
->address
& 0xff;
846 txbuf
[3] = msg
->size
- 1;
848 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
849 case DP_AUX_NATIVE_WRITE
:
850 case DP_AUX_I2C_WRITE
:
851 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
854 if (WARN_ON(txsize
> 20))
857 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
859 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
861 msg
->reply
= rxbuf
[0] >> 4;
863 /* Return payload size. */
868 case DP_AUX_NATIVE_READ
:
869 case DP_AUX_I2C_READ
:
870 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
871 rxsize
= msg
->size
+ 1;
873 if (WARN_ON(rxsize
> 20))
876 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
878 msg
->reply
= rxbuf
[0] >> 4;
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
883 * Return payload size.
886 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
899 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
901 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
902 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
903 enum port port
= intel_dig_port
->port
;
904 const char *name
= NULL
;
909 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
913 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
917 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
921 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
929 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
931 intel_dp
->aux
.name
= name
;
932 intel_dp
->aux
.dev
= dev
->dev
;
933 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
935 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
936 connector
->base
.kdev
->kobj
.name
);
938 ret
= drm_dp_aux_register(&intel_dp
->aux
);
940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
945 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
946 &intel_dp
->aux
.ddc
.dev
.kobj
,
947 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
950 drm_dp_aux_unregister(&intel_dp
->aux
);
955 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
957 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
959 if (!intel_connector
->mst_port
)
960 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
961 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
962 intel_connector_unregister(intel_connector
);
966 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
969 case DP_LINK_BW_1_62
:
970 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
973 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
976 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
982 intel_dp_set_clock(struct intel_encoder
*encoder
,
983 struct intel_crtc_config
*pipe_config
, int link_bw
)
985 struct drm_device
*dev
= encoder
->base
.dev
;
986 const struct dp_link_dpll
*divisor
= NULL
;
991 count
= ARRAY_SIZE(gen4_dpll
);
992 } else if (HAS_PCH_SPLIT(dev
)) {
994 count
= ARRAY_SIZE(pch_dpll
);
995 } else if (IS_CHERRYVIEW(dev
)) {
997 count
= ARRAY_SIZE(chv_dpll
);
998 } else if (IS_VALLEYVIEW(dev
)) {
1000 count
= ARRAY_SIZE(vlv_dpll
);
1003 if (divisor
&& count
) {
1004 for (i
= 0; i
< count
; i
++) {
1005 if (link_bw
== divisor
[i
].link_bw
) {
1006 pipe_config
->dpll
= divisor
[i
].dpll
;
1007 pipe_config
->clock_set
= true;
1015 intel_dp_compute_config(struct intel_encoder
*encoder
,
1016 struct intel_crtc_config
*pipe_config
)
1018 struct drm_device
*dev
= encoder
->base
.dev
;
1019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1020 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1021 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1022 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1023 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1024 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1025 int lane_count
, clock
;
1026 int min_lane_count
= 1;
1027 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1028 /* Conveniently, the link BW constants become indices with a shift...*/
1030 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1032 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1033 int link_avail
, link_clock
;
1035 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1036 pipe_config
->has_pch_encoder
= true;
1038 pipe_config
->has_dp_encoder
= true;
1039 pipe_config
->has_drrs
= false;
1040 pipe_config
->has_audio
= intel_dp
->has_audio
;
1042 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1043 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1045 if (!HAS_PCH_SPLIT(dev
))
1046 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1047 intel_connector
->panel
.fitting_mode
);
1049 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1050 intel_connector
->panel
.fitting_mode
);
1053 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
1058 max_lane_count
, bws
[max_clock
],
1059 adjusted_mode
->crtc_clock
);
1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
1063 bpp
= pipe_config
->pipe_bpp
;
1064 if (is_edp(intel_dp
)) {
1065 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv
->vbt
.edp_bpp
);
1068 bpp
= dev_priv
->vbt
.edp_bpp
;
1071 if (IS_BROADWELL(dev
)) {
1072 /* Yes, it's an ugly hack. */
1073 min_lane_count
= max_lane_count
;
1074 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1076 } else if (dev_priv
->vbt
.edp_lanes
) {
1077 min_lane_count
= min(dev_priv
->vbt
.edp_lanes
,
1079 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1083 if (dev_priv
->vbt
.edp_rate
) {
1084 min_clock
= min(dev_priv
->vbt
.edp_rate
>> 3, max_clock
);
1085 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1090 for (; bpp
>= 6*3; bpp
-= 2*3) {
1091 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1094 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1095 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1096 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1097 link_avail
= intel_dp_max_data_rate(link_clock
,
1100 if (mode_rate
<= link_avail
) {
1110 if (intel_dp
->color_range_auto
) {
1113 * CEA-861-E - 5.1 Default Encoding Parameters
1114 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1116 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1117 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1119 intel_dp
->color_range
= 0;
1122 if (intel_dp
->color_range
)
1123 pipe_config
->limited_color_range
= true;
1125 intel_dp
->link_bw
= bws
[clock
];
1126 intel_dp
->lane_count
= lane_count
;
1127 pipe_config
->pipe_bpp
= bpp
;
1128 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1130 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1131 intel_dp
->link_bw
, intel_dp
->lane_count
,
1132 pipe_config
->port_clock
, bpp
);
1133 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1134 mode_rate
, link_avail
);
1136 intel_link_compute_m_n(bpp
, lane_count
,
1137 adjusted_mode
->crtc_clock
,
1138 pipe_config
->port_clock
,
1139 &pipe_config
->dp_m_n
);
1141 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1142 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1143 pipe_config
->has_drrs
= true;
1144 intel_link_compute_m_n(bpp
, lane_count
,
1145 intel_connector
->panel
.downclock_mode
->clock
,
1146 pipe_config
->port_clock
,
1147 &pipe_config
->dp_m2_n2
);
1150 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1151 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1153 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1158 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1160 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1161 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1162 struct drm_device
*dev
= crtc
->base
.dev
;
1163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1166 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1167 dpa_ctl
= I915_READ(DP_A
);
1168 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1170 if (crtc
->config
.port_clock
== 162000) {
1171 /* For a long time we've carried around a ILK-DevA w/a for the
1172 * 160MHz clock. If we're really unlucky, it's still required.
1174 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1175 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1176 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1178 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1179 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1182 I915_WRITE(DP_A
, dpa_ctl
);
1188 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1190 struct drm_device
*dev
= encoder
->base
.dev
;
1191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1192 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1193 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1194 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1195 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1198 * There are four kinds of DP registers:
1205 * IBX PCH and CPU are the same for almost everything,
1206 * except that the CPU DP PLL is configured in this
1209 * CPT PCH is quite different, having many bits moved
1210 * to the TRANS_DP_CTL register instead. That
1211 * configuration happens (oddly) in ironlake_pch_enable
1214 /* Preserve the BIOS-computed detected bit. This is
1215 * supposed to be read-only.
1217 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1219 /* Handle DP bits in common between all three register formats */
1220 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1221 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1223 if (crtc
->config
.has_audio
) {
1224 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1225 pipe_name(crtc
->pipe
));
1226 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1227 intel_write_eld(&encoder
->base
, adjusted_mode
);
1230 /* Split out the IBX/CPU vs CPT settings */
1232 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1233 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1234 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1235 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1236 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1237 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1239 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1240 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1242 intel_dp
->DP
|= crtc
->pipe
<< 29;
1243 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1244 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1245 intel_dp
->DP
|= intel_dp
->color_range
;
1247 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1248 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1249 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1250 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1251 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1253 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1254 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1256 if (!IS_CHERRYVIEW(dev
)) {
1257 if (crtc
->pipe
== 1)
1258 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1260 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1263 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1267 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1268 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1270 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1271 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1273 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1274 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1276 static void wait_panel_status(struct intel_dp
*intel_dp
,
1280 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1282 u32 pp_stat_reg
, pp_ctrl_reg
;
1284 lockdep_assert_held(&dev_priv
->pps_mutex
);
1286 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1287 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1289 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1291 I915_READ(pp_stat_reg
),
1292 I915_READ(pp_ctrl_reg
));
1294 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1295 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1296 I915_READ(pp_stat_reg
),
1297 I915_READ(pp_ctrl_reg
));
1300 DRM_DEBUG_KMS("Wait complete\n");
1303 static void wait_panel_on(struct intel_dp
*intel_dp
)
1305 DRM_DEBUG_KMS("Wait for panel power on\n");
1306 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1309 static void wait_panel_off(struct intel_dp
*intel_dp
)
1311 DRM_DEBUG_KMS("Wait for panel power off time\n");
1312 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1315 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1317 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1319 /* When we disable the VDD override bit last we have to do the manual
1321 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1322 intel_dp
->panel_power_cycle_delay
);
1324 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1327 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1329 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1330 intel_dp
->backlight_on_delay
);
1333 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1335 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1336 intel_dp
->backlight_off_delay
);
1339 /* Read the current pp_control value, unlocking the register if it
1343 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1345 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1349 lockdep_assert_held(&dev_priv
->pps_mutex
);
1351 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1352 control
&= ~PANEL_UNLOCK_MASK
;
1353 control
|= PANEL_UNLOCK_REGS
;
1357 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1359 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1360 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1361 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1363 enum intel_display_power_domain power_domain
;
1365 u32 pp_stat_reg
, pp_ctrl_reg
;
1366 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1368 lockdep_assert_held(&dev_priv
->pps_mutex
);
1370 if (!is_edp(intel_dp
))
1373 intel_dp
->want_panel_vdd
= true;
1375 if (edp_have_panel_vdd(intel_dp
))
1376 return need_to_disable
;
1378 power_domain
= intel_display_port_power_domain(intel_encoder
);
1379 intel_display_power_get(dev_priv
, power_domain
);
1381 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1383 if (!edp_have_panel_power(intel_dp
))
1384 wait_panel_power_cycle(intel_dp
);
1386 pp
= ironlake_get_pp_control(intel_dp
);
1387 pp
|= EDP_FORCE_VDD
;
1389 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1390 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1392 I915_WRITE(pp_ctrl_reg
, pp
);
1393 POSTING_READ(pp_ctrl_reg
);
1394 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1395 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1397 * If the panel wasn't on, delay before accessing aux channel
1399 if (!edp_have_panel_power(intel_dp
)) {
1400 DRM_DEBUG_KMS("eDP was not running\n");
1401 msleep(intel_dp
->panel_power_up_delay
);
1404 return need_to_disable
;
1407 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1411 if (!is_edp(intel_dp
))
1415 vdd
= edp_panel_vdd_on(intel_dp
);
1416 pps_unlock(intel_dp
);
1418 WARN(!vdd
, "eDP VDD already requested on\n");
1421 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1423 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1425 struct intel_digital_port
*intel_dig_port
=
1426 dp_to_dig_port(intel_dp
);
1427 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1428 enum intel_display_power_domain power_domain
;
1430 u32 pp_stat_reg
, pp_ctrl_reg
;
1432 lockdep_assert_held(&dev_priv
->pps_mutex
);
1434 WARN_ON(intel_dp
->want_panel_vdd
);
1436 if (!edp_have_panel_vdd(intel_dp
))
1439 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1441 pp
= ironlake_get_pp_control(intel_dp
);
1442 pp
&= ~EDP_FORCE_VDD
;
1444 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1445 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1447 I915_WRITE(pp_ctrl_reg
, pp
);
1448 POSTING_READ(pp_ctrl_reg
);
1450 /* Make sure sequencer is idle before allowing subsequent activity */
1451 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1452 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1454 if ((pp
& POWER_TARGET_ON
) == 0)
1455 intel_dp
->last_power_cycle
= jiffies
;
1457 power_domain
= intel_display_port_power_domain(intel_encoder
);
1458 intel_display_power_put(dev_priv
, power_domain
);
1461 static void edp_panel_vdd_work(struct work_struct
*__work
)
1463 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1464 struct intel_dp
, panel_vdd_work
);
1467 if (!intel_dp
->want_panel_vdd
)
1468 edp_panel_vdd_off_sync(intel_dp
);
1469 pps_unlock(intel_dp
);
1472 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1474 unsigned long delay
;
1477 * Queue the timer to fire a long time from now (relative to the power
1478 * down delay) to keep the panel power up across a sequence of
1481 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1482 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1485 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1487 struct drm_i915_private
*dev_priv
=
1488 intel_dp_to_dev(intel_dp
)->dev_private
;
1490 lockdep_assert_held(&dev_priv
->pps_mutex
);
1492 if (!is_edp(intel_dp
))
1495 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1497 intel_dp
->want_panel_vdd
= false;
1500 edp_panel_vdd_off_sync(intel_dp
);
1502 edp_panel_vdd_schedule_off(intel_dp
);
1505 static void intel_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1507 if (!is_edp(intel_dp
))
1511 edp_panel_vdd_off(intel_dp
, sync
);
1512 pps_unlock(intel_dp
);
1515 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1517 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1522 if (!is_edp(intel_dp
))
1525 DRM_DEBUG_KMS("Turn eDP power on\n");
1529 if (edp_have_panel_power(intel_dp
)) {
1530 DRM_DEBUG_KMS("eDP power already on\n");
1534 wait_panel_power_cycle(intel_dp
);
1536 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1537 pp
= ironlake_get_pp_control(intel_dp
);
1539 /* ILK workaround: disable reset around power sequence */
1540 pp
&= ~PANEL_POWER_RESET
;
1541 I915_WRITE(pp_ctrl_reg
, pp
);
1542 POSTING_READ(pp_ctrl_reg
);
1545 pp
|= POWER_TARGET_ON
;
1547 pp
|= PANEL_POWER_RESET
;
1549 I915_WRITE(pp_ctrl_reg
, pp
);
1550 POSTING_READ(pp_ctrl_reg
);
1552 wait_panel_on(intel_dp
);
1553 intel_dp
->last_power_on
= jiffies
;
1556 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1557 I915_WRITE(pp_ctrl_reg
, pp
);
1558 POSTING_READ(pp_ctrl_reg
);
1562 pps_unlock(intel_dp
);
1565 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1567 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1568 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1569 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1571 enum intel_display_power_domain power_domain
;
1575 if (!is_edp(intel_dp
))
1578 DRM_DEBUG_KMS("Turn eDP power off\n");
1582 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1584 pp
= ironlake_get_pp_control(intel_dp
);
1585 /* We need to switch off panel power _and_ force vdd, for otherwise some
1586 * panels get very unhappy and cease to work. */
1587 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1590 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1592 intel_dp
->want_panel_vdd
= false;
1594 I915_WRITE(pp_ctrl_reg
, pp
);
1595 POSTING_READ(pp_ctrl_reg
);
1597 intel_dp
->last_power_cycle
= jiffies
;
1598 wait_panel_off(intel_dp
);
1600 /* We got a reference when we enabled the VDD. */
1601 power_domain
= intel_display_port_power_domain(intel_encoder
);
1602 intel_display_power_put(dev_priv
, power_domain
);
1604 pps_unlock(intel_dp
);
1607 /* Enable backlight in the panel power control. */
1608 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1610 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1611 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1617 * If we enable the backlight right away following a panel power
1618 * on, we may see slight flicker as the panel syncs with the eDP
1619 * link. So delay a bit to make sure the image is solid before
1620 * allowing it to appear.
1622 wait_backlight_on(intel_dp
);
1626 pp
= ironlake_get_pp_control(intel_dp
);
1627 pp
|= EDP_BLC_ENABLE
;
1629 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1631 I915_WRITE(pp_ctrl_reg
, pp
);
1632 POSTING_READ(pp_ctrl_reg
);
1634 pps_unlock(intel_dp
);
1637 /* Enable backlight PWM and backlight PP control. */
1638 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1640 if (!is_edp(intel_dp
))
1643 DRM_DEBUG_KMS("\n");
1645 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1646 _intel_edp_backlight_on(intel_dp
);
1649 /* Disable backlight in the panel power control. */
1650 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1652 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1657 if (!is_edp(intel_dp
))
1662 pp
= ironlake_get_pp_control(intel_dp
);
1663 pp
&= ~EDP_BLC_ENABLE
;
1665 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1667 I915_WRITE(pp_ctrl_reg
, pp
);
1668 POSTING_READ(pp_ctrl_reg
);
1670 pps_unlock(intel_dp
);
1672 intel_dp
->last_backlight_off
= jiffies
;
1673 edp_wait_backlight_off(intel_dp
);
1676 /* Disable backlight PP control and backlight PWM. */
1677 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1679 if (!is_edp(intel_dp
))
1682 DRM_DEBUG_KMS("\n");
1684 _intel_edp_backlight_off(intel_dp
);
1685 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1689 * Hook for controlling the panel power control backlight through the bl_power
1690 * sysfs attribute. Take care to handle multiple calls.
1692 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1695 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1699 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1700 pps_unlock(intel_dp
);
1702 if (is_enabled
== enable
)
1705 DRM_DEBUG_KMS("panel power control backlight %s\n",
1706 enable
? "enable" : "disable");
1709 _intel_edp_backlight_on(intel_dp
);
1711 _intel_edp_backlight_off(intel_dp
);
1714 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1716 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1717 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1718 struct drm_device
*dev
= crtc
->dev
;
1719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1722 assert_pipe_disabled(dev_priv
,
1723 to_intel_crtc(crtc
)->pipe
);
1725 DRM_DEBUG_KMS("\n");
1726 dpa_ctl
= I915_READ(DP_A
);
1727 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1728 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1730 /* We don't adjust intel_dp->DP while tearing down the link, to
1731 * facilitate link retraining (e.g. after hotplug). Hence clear all
1732 * enable bits here to ensure that we don't enable too much. */
1733 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1734 intel_dp
->DP
|= DP_PLL_ENABLE
;
1735 I915_WRITE(DP_A
, intel_dp
->DP
);
1740 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1742 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1743 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1744 struct drm_device
*dev
= crtc
->dev
;
1745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1748 assert_pipe_disabled(dev_priv
,
1749 to_intel_crtc(crtc
)->pipe
);
1751 dpa_ctl
= I915_READ(DP_A
);
1752 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1753 "dp pll off, should be on\n");
1754 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1756 /* We can't rely on the value tracked for the DP register in
1757 * intel_dp->DP because link_down must not change that (otherwise link
1758 * re-training will fail. */
1759 dpa_ctl
&= ~DP_PLL_ENABLE
;
1760 I915_WRITE(DP_A
, dpa_ctl
);
1765 /* If the sink supports it, try to set the power state appropriately */
1766 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1770 /* Should have a valid DPCD by this point */
1771 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1774 if (mode
!= DRM_MODE_DPMS_ON
) {
1775 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1779 * When turning on, we need to retry for 1ms to give the sink
1782 for (i
= 0; i
< 3; i
++) {
1783 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1792 DRM_DEBUG_KMS("failed to %s sink power state\n",
1793 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1796 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1799 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1800 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1801 struct drm_device
*dev
= encoder
->base
.dev
;
1802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1803 enum intel_display_power_domain power_domain
;
1806 power_domain
= intel_display_port_power_domain(encoder
);
1807 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1810 tmp
= I915_READ(intel_dp
->output_reg
);
1812 if (!(tmp
& DP_PORT_EN
))
1815 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1816 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1817 } else if (IS_CHERRYVIEW(dev
)) {
1818 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1819 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1820 *pipe
= PORT_TO_PIPE(tmp
);
1826 switch (intel_dp
->output_reg
) {
1828 trans_sel
= TRANS_DP_PORT_SEL_B
;
1831 trans_sel
= TRANS_DP_PORT_SEL_C
;
1834 trans_sel
= TRANS_DP_PORT_SEL_D
;
1840 for_each_pipe(dev_priv
, i
) {
1841 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1842 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1848 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1849 intel_dp
->output_reg
);
1855 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1856 struct intel_crtc_config
*pipe_config
)
1858 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1860 struct drm_device
*dev
= encoder
->base
.dev
;
1861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1862 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1863 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1866 tmp
= I915_READ(intel_dp
->output_reg
);
1867 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1868 pipe_config
->has_audio
= true;
1870 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1871 if (tmp
& DP_SYNC_HS_HIGH
)
1872 flags
|= DRM_MODE_FLAG_PHSYNC
;
1874 flags
|= DRM_MODE_FLAG_NHSYNC
;
1876 if (tmp
& DP_SYNC_VS_HIGH
)
1877 flags
|= DRM_MODE_FLAG_PVSYNC
;
1879 flags
|= DRM_MODE_FLAG_NVSYNC
;
1881 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1882 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1883 flags
|= DRM_MODE_FLAG_PHSYNC
;
1885 flags
|= DRM_MODE_FLAG_NHSYNC
;
1887 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1888 flags
|= DRM_MODE_FLAG_PVSYNC
;
1890 flags
|= DRM_MODE_FLAG_NVSYNC
;
1893 pipe_config
->adjusted_mode
.flags
|= flags
;
1895 pipe_config
->has_dp_encoder
= true;
1897 intel_dp_get_m_n(crtc
, pipe_config
);
1899 if (port
== PORT_A
) {
1900 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1901 pipe_config
->port_clock
= 162000;
1903 pipe_config
->port_clock
= 270000;
1906 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1907 &pipe_config
->dp_m_n
);
1909 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1910 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1912 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1914 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1915 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1917 * This is a big fat ugly hack.
1919 * Some machines in UEFI boot mode provide us a VBT that has 18
1920 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1921 * unknown we fail to light up. Yet the same BIOS boots up with
1922 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1923 * max, not what it tells us to use.
1925 * Note: This will still be broken if the eDP panel is not lit
1926 * up by the BIOS, and thus we can't get the mode at module
1929 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1930 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1931 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1935 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1937 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1940 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1947 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1950 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1951 struct edp_vsc_psr
*vsc_psr
)
1953 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1954 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1956 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1957 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1958 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1959 uint32_t *data
= (uint32_t *) vsc_psr
;
1962 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1963 the video DIP being updated before program video DIP data buffer
1964 registers for DIP being updated. */
1965 I915_WRITE(ctl_reg
, 0);
1966 POSTING_READ(ctl_reg
);
1968 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1969 if (i
< sizeof(struct edp_vsc_psr
))
1970 I915_WRITE(data_reg
+ i
, *data
++);
1972 I915_WRITE(data_reg
+ i
, 0);
1975 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1976 POSTING_READ(ctl_reg
);
1979 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1981 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1983 struct edp_vsc_psr psr_vsc
;
1985 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1986 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1987 psr_vsc
.sdp_header
.HB0
= 0;
1988 psr_vsc
.sdp_header
.HB1
= 0x7;
1989 psr_vsc
.sdp_header
.HB2
= 0x2;
1990 psr_vsc
.sdp_header
.HB3
= 0x8;
1991 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1993 /* Avoid continuous PSR exit by masking memup and hpd */
1994 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1995 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1998 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
2000 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2001 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2003 uint32_t aux_clock_divider
;
2004 int precharge
= 0x3;
2005 int msg_size
= 5; /* Header(4) + Message(1) */
2006 bool only_standby
= false;
2008 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
2010 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2011 only_standby
= true;
2013 /* Enable PSR in sink */
2014 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
2015 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2016 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
2018 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2019 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
2021 /* Setup AUX registers */
2022 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
2023 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
2024 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
2025 DP_AUX_CH_CTL_TIME_OUT_400us
|
2026 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
2027 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
2028 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
2031 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
2033 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2034 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2036 uint32_t max_sleep_time
= 0x1f;
2037 uint32_t idle_frames
= 1;
2039 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
2040 bool only_standby
= false;
2042 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2043 only_standby
= true;
2045 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
2046 val
|= EDP_PSR_LINK_STANDBY
;
2047 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
2048 val
|= EDP_PSR_TP1_TIME_0us
;
2049 val
|= EDP_PSR_SKIP_AUX_EXIT
;
2050 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
2052 val
|= EDP_PSR_LINK_DISABLE
;
2054 I915_WRITE(EDP_PSR_CTL(dev
), val
|
2055 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
2056 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
2057 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
2061 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
2063 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2064 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2066 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
2067 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2069 lockdep_assert_held(&dev_priv
->psr
.lock
);
2070 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
2071 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
2073 dev_priv
->psr
.source_ok
= false;
2075 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
2076 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2080 if (!i915
.enable_psr
) {
2081 DRM_DEBUG_KMS("PSR disable by flag\n");
2085 /* Below limitations aren't valid for Broadwell */
2086 if (IS_BROADWELL(dev
))
2089 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
2091 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2095 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2096 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2101 dev_priv
->psr
.source_ok
= true;
2105 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
2107 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2108 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2111 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2112 WARN_ON(dev_priv
->psr
.active
);
2113 lockdep_assert_held(&dev_priv
->psr
.lock
);
2115 /* Enable PSR on the panel */
2116 intel_edp_psr_enable_sink(intel_dp
);
2118 /* Enable PSR on the host */
2119 intel_edp_psr_enable_source(intel_dp
);
2121 dev_priv
->psr
.active
= true;
2124 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
2126 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2129 if (!HAS_PSR(dev
)) {
2130 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2134 if (!is_edp_psr(intel_dp
)) {
2135 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2139 mutex_lock(&dev_priv
->psr
.lock
);
2140 if (dev_priv
->psr
.enabled
) {
2141 DRM_DEBUG_KMS("PSR already in use\n");
2142 mutex_unlock(&dev_priv
->psr
.lock
);
2146 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
2148 /* Setup PSR once */
2149 intel_edp_psr_setup(intel_dp
);
2151 if (intel_edp_psr_match_conditions(intel_dp
))
2152 dev_priv
->psr
.enabled
= intel_dp
;
2153 mutex_unlock(&dev_priv
->psr
.lock
);
2156 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
2158 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2161 mutex_lock(&dev_priv
->psr
.lock
);
2162 if (!dev_priv
->psr
.enabled
) {
2163 mutex_unlock(&dev_priv
->psr
.lock
);
2167 if (dev_priv
->psr
.active
) {
2168 I915_WRITE(EDP_PSR_CTL(dev
),
2169 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
2171 /* Wait till PSR is idle */
2172 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
2173 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
2174 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2176 dev_priv
->psr
.active
= false;
2178 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2181 dev_priv
->psr
.enabled
= NULL
;
2182 mutex_unlock(&dev_priv
->psr
.lock
);
2184 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
2187 static void intel_edp_psr_work(struct work_struct
*work
)
2189 struct drm_i915_private
*dev_priv
=
2190 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
2191 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
2193 mutex_lock(&dev_priv
->psr
.lock
);
2194 intel_dp
= dev_priv
->psr
.enabled
;
2200 * The delayed work can race with an invalidate hence we need to
2201 * recheck. Since psr_flush first clears this and then reschedules we
2202 * won't ever miss a flush when bailing out here.
2204 if (dev_priv
->psr
.busy_frontbuffer_bits
)
2207 intel_edp_psr_do_enable(intel_dp
);
2209 mutex_unlock(&dev_priv
->psr
.lock
);
2212 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
2214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2216 if (dev_priv
->psr
.active
) {
2217 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
2219 WARN_ON(!(val
& EDP_PSR_ENABLE
));
2221 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
2223 dev_priv
->psr
.active
= false;
2228 void intel_edp_psr_invalidate(struct drm_device
*dev
,
2229 unsigned frontbuffer_bits
)
2231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2232 struct drm_crtc
*crtc
;
2235 mutex_lock(&dev_priv
->psr
.lock
);
2236 if (!dev_priv
->psr
.enabled
) {
2237 mutex_unlock(&dev_priv
->psr
.lock
);
2241 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2242 pipe
= to_intel_crtc(crtc
)->pipe
;
2244 intel_edp_psr_do_exit(dev
);
2246 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2248 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2249 mutex_unlock(&dev_priv
->psr
.lock
);
2252 void intel_edp_psr_flush(struct drm_device
*dev
,
2253 unsigned frontbuffer_bits
)
2255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2256 struct drm_crtc
*crtc
;
2259 mutex_lock(&dev_priv
->psr
.lock
);
2260 if (!dev_priv
->psr
.enabled
) {
2261 mutex_unlock(&dev_priv
->psr
.lock
);
2265 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2266 pipe
= to_intel_crtc(crtc
)->pipe
;
2267 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2270 * On Haswell sprite plane updates don't result in a psr invalidating
2271 * signal in the hardware. Which means we need to manually fake this in
2272 * software for all flushes, not just when we've seen a preceding
2273 * invalidation through frontbuffer rendering.
2275 if (IS_HASWELL(dev
) &&
2276 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2277 intel_edp_psr_do_exit(dev
);
2279 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2280 schedule_delayed_work(&dev_priv
->psr
.work
,
2281 msecs_to_jiffies(100));
2282 mutex_unlock(&dev_priv
->psr
.lock
);
2285 void intel_edp_psr_init(struct drm_device
*dev
)
2287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2289 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2290 mutex_init(&dev_priv
->psr
.lock
);
2293 static void intel_disable_dp(struct intel_encoder
*encoder
)
2295 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2296 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2297 struct drm_device
*dev
= encoder
->base
.dev
;
2299 /* Make sure the panel is off before trying to change the mode. But also
2300 * ensure that we have vdd while we switch off the panel. */
2301 intel_edp_panel_vdd_on(intel_dp
);
2302 intel_edp_backlight_off(intel_dp
);
2303 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2304 intel_edp_panel_off(intel_dp
);
2306 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2307 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
2308 intel_dp_link_down(intel_dp
);
2311 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
2313 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2314 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2319 intel_dp_link_down(intel_dp
);
2320 ironlake_edp_pll_off(intel_dp
);
2323 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2325 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2327 intel_dp_link_down(intel_dp
);
2330 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2332 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2333 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2334 struct drm_device
*dev
= encoder
->base
.dev
;
2335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2336 struct intel_crtc
*intel_crtc
=
2337 to_intel_crtc(encoder
->base
.crtc
);
2338 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2339 enum pipe pipe
= intel_crtc
->pipe
;
2342 intel_dp_link_down(intel_dp
);
2344 mutex_lock(&dev_priv
->dpio_lock
);
2346 /* Propagate soft reset to data lane reset */
2347 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2348 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2349 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2351 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2352 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2353 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2355 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2356 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2357 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2359 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2360 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2361 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2363 mutex_unlock(&dev_priv
->dpio_lock
);
2366 static void intel_enable_dp(struct intel_encoder
*encoder
)
2368 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2369 struct drm_device
*dev
= encoder
->base
.dev
;
2370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2371 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2373 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2376 intel_edp_panel_vdd_on(intel_dp
);
2377 intel_edp_panel_on(intel_dp
);
2378 intel_edp_panel_vdd_off(intel_dp
, true);
2379 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2380 intel_dp_start_link_train(intel_dp
);
2381 intel_dp_complete_link_train(intel_dp
);
2382 intel_dp_stop_link_train(intel_dp
);
2385 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2387 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2389 intel_enable_dp(encoder
);
2390 intel_edp_backlight_on(intel_dp
);
2393 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2395 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2397 intel_edp_backlight_on(intel_dp
);
2400 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2402 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2403 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2405 intel_dp_prepare(encoder
);
2407 /* Only ilk+ has port A */
2408 if (dport
->port
== PORT_A
) {
2409 ironlake_set_pll_cpu_edp(intel_dp
);
2410 ironlake_edp_pll_on(intel_dp
);
2414 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2418 struct intel_encoder
*encoder
;
2420 lockdep_assert_held(&dev_priv
->pps_mutex
);
2422 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2424 struct intel_dp
*intel_dp
;
2427 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2430 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2431 port
= dp_to_dig_port(intel_dp
)->port
;
2433 if (intel_dp
->pps_pipe
!= pipe
)
2436 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2437 pipe_name(pipe
), port_name(port
));
2439 /* make sure vdd is off before we steal it */
2440 edp_panel_vdd_off_sync(intel_dp
);
2442 intel_dp
->pps_pipe
= INVALID_PIPE
;
2446 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2448 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2449 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2450 struct drm_device
*dev
= encoder
->base
.dev
;
2451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2452 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2453 struct edp_power_seq power_seq
;
2455 lockdep_assert_held(&dev_priv
->pps_mutex
);
2457 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2461 * If another power sequencer was being used on this
2462 * port previously make sure to turn off vdd there while
2463 * we still have control of it.
2465 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2466 edp_panel_vdd_off_sync(intel_dp
);
2469 * We may be stealing the power
2470 * sequencer from another port.
2472 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2474 /* now it's all ours */
2475 intel_dp
->pps_pipe
= crtc
->pipe
;
2477 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2478 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2480 /* init power sequencer on this pipe and port */
2481 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2482 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2486 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2488 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2489 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2490 struct drm_device
*dev
= encoder
->base
.dev
;
2491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2492 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2493 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2494 int pipe
= intel_crtc
->pipe
;
2497 mutex_lock(&dev_priv
->dpio_lock
);
2499 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2506 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2507 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2508 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2510 mutex_unlock(&dev_priv
->dpio_lock
);
2512 if (is_edp(intel_dp
)) {
2514 vlv_init_panel_power_sequencer(intel_dp
);
2515 pps_unlock(intel_dp
);
2518 intel_enable_dp(encoder
);
2520 vlv_wait_port_ready(dev_priv
, dport
);
2523 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2525 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2526 struct drm_device
*dev
= encoder
->base
.dev
;
2527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2528 struct intel_crtc
*intel_crtc
=
2529 to_intel_crtc(encoder
->base
.crtc
);
2530 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2531 int pipe
= intel_crtc
->pipe
;
2533 intel_dp_prepare(encoder
);
2535 /* Program Tx lane resets to default */
2536 mutex_lock(&dev_priv
->dpio_lock
);
2537 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2538 DPIO_PCS_TX_LANE2_RESET
|
2539 DPIO_PCS_TX_LANE1_RESET
);
2540 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2541 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2542 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2543 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2544 DPIO_PCS_CLK_SOFT_RESET
);
2546 /* Fix up inter-pair skew failure */
2547 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2548 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2549 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2550 mutex_unlock(&dev_priv
->dpio_lock
);
2553 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2555 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2556 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2557 struct drm_device
*dev
= encoder
->base
.dev
;
2558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2559 struct intel_crtc
*intel_crtc
=
2560 to_intel_crtc(encoder
->base
.crtc
);
2561 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2562 int pipe
= intel_crtc
->pipe
;
2566 mutex_lock(&dev_priv
->dpio_lock
);
2568 /* Deassert soft data lane reset*/
2569 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2570 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2571 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2573 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2574 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2575 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2577 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2578 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2579 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2581 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2582 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2583 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2585 /* Program Tx lane latency optimal setting*/
2586 for (i
= 0; i
< 4; i
++) {
2587 /* Set the latency optimal bit */
2588 data
= (i
== 1) ? 0x0 : 0x6;
2589 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2590 data
<< DPIO_FRC_LATENCY_SHFIT
);
2592 /* Set the upar bit */
2593 data
= (i
== 1) ? 0x0 : 0x1;
2594 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2595 data
<< DPIO_UPAR_SHIFT
);
2598 /* Data lane stagger programming */
2599 /* FIXME: Fix up value only after power analysis */
2601 mutex_unlock(&dev_priv
->dpio_lock
);
2603 if (is_edp(intel_dp
)) {
2605 vlv_init_panel_power_sequencer(intel_dp
);
2606 pps_unlock(intel_dp
);
2609 intel_enable_dp(encoder
);
2611 vlv_wait_port_ready(dev_priv
, dport
);
2614 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2616 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2617 struct drm_device
*dev
= encoder
->base
.dev
;
2618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2619 struct intel_crtc
*intel_crtc
=
2620 to_intel_crtc(encoder
->base
.crtc
);
2621 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2622 enum pipe pipe
= intel_crtc
->pipe
;
2625 intel_dp_prepare(encoder
);
2627 mutex_lock(&dev_priv
->dpio_lock
);
2629 /* program left/right clock distribution */
2630 if (pipe
!= PIPE_B
) {
2631 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2632 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2634 val
|= CHV_BUFLEFTENA1_FORCE
;
2636 val
|= CHV_BUFRIGHTENA1_FORCE
;
2637 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2639 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2640 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2642 val
|= CHV_BUFLEFTENA2_FORCE
;
2644 val
|= CHV_BUFRIGHTENA2_FORCE
;
2645 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2648 /* program clock channel usage */
2649 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2650 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2652 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2654 val
|= CHV_PCS_USEDCLKCHANNEL
;
2655 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2657 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2658 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2660 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2662 val
|= CHV_PCS_USEDCLKCHANNEL
;
2663 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2666 * This a a bit weird since generally CL
2667 * matches the pipe, but here we need to
2668 * pick the CL based on the port.
2670 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2672 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2674 val
|= CHV_CMN_USEDCLKCHANNEL
;
2675 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2677 mutex_unlock(&dev_priv
->dpio_lock
);
2681 * Native read with retry for link status and receiver capability reads for
2682 * cases where the sink may still be asleep.
2684 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2685 * supposed to retry 3 times per the spec.
2688 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2689 void *buffer
, size_t size
)
2694 for (i
= 0; i
< 3; i
++) {
2695 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2705 * Fetch AUX CH registers 0x202 - 0x207 which contain
2706 * link status information
2709 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2711 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2714 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2717 /* These are source-specific values. */
2719 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2721 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2722 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2724 if (IS_VALLEYVIEW(dev
))
2725 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2726 else if (IS_GEN7(dev
) && port
== PORT_A
)
2727 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2728 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2729 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2731 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2735 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2737 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2738 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2740 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2741 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2742 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2743 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2744 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2745 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2746 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2747 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2748 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2750 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2752 } else if (IS_VALLEYVIEW(dev
)) {
2753 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2754 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2755 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2756 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2757 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2758 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2759 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2760 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2762 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2764 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2765 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2766 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2767 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2768 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2769 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2770 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2772 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2775 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2776 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2777 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2778 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2779 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2780 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2781 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2782 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2784 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2789 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2791 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2793 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2794 struct intel_crtc
*intel_crtc
=
2795 to_intel_crtc(dport
->base
.base
.crtc
);
2796 unsigned long demph_reg_value
, preemph_reg_value
,
2797 uniqtranscale_reg_value
;
2798 uint8_t train_set
= intel_dp
->train_set
[0];
2799 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2800 int pipe
= intel_crtc
->pipe
;
2802 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2803 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2804 preemph_reg_value
= 0x0004000;
2805 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2806 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2807 demph_reg_value
= 0x2B405555;
2808 uniqtranscale_reg_value
= 0x552AB83A;
2810 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2811 demph_reg_value
= 0x2B404040;
2812 uniqtranscale_reg_value
= 0x5548B83A;
2814 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2815 demph_reg_value
= 0x2B245555;
2816 uniqtranscale_reg_value
= 0x5560B83A;
2818 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2819 demph_reg_value
= 0x2B405555;
2820 uniqtranscale_reg_value
= 0x5598DA3A;
2826 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2827 preemph_reg_value
= 0x0002000;
2828 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2829 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2830 demph_reg_value
= 0x2B404040;
2831 uniqtranscale_reg_value
= 0x5552B83A;
2833 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2834 demph_reg_value
= 0x2B404848;
2835 uniqtranscale_reg_value
= 0x5580B83A;
2837 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2838 demph_reg_value
= 0x2B404040;
2839 uniqtranscale_reg_value
= 0x55ADDA3A;
2845 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2846 preemph_reg_value
= 0x0000000;
2847 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2848 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2849 demph_reg_value
= 0x2B305555;
2850 uniqtranscale_reg_value
= 0x5570B83A;
2852 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2853 demph_reg_value
= 0x2B2B4040;
2854 uniqtranscale_reg_value
= 0x55ADDA3A;
2860 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2861 preemph_reg_value
= 0x0006000;
2862 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2864 demph_reg_value
= 0x1B405555;
2865 uniqtranscale_reg_value
= 0x55ADDA3A;
2875 mutex_lock(&dev_priv
->dpio_lock
);
2876 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2877 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2878 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2879 uniqtranscale_reg_value
);
2880 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2881 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2882 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2883 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2884 mutex_unlock(&dev_priv
->dpio_lock
);
2889 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2891 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2893 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2894 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2895 u32 deemph_reg_value
, margin_reg_value
, val
;
2896 uint8_t train_set
= intel_dp
->train_set
[0];
2897 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2898 enum pipe pipe
= intel_crtc
->pipe
;
2901 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2902 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2903 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2904 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2905 deemph_reg_value
= 128;
2906 margin_reg_value
= 52;
2908 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2909 deemph_reg_value
= 128;
2910 margin_reg_value
= 77;
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2913 deemph_reg_value
= 128;
2914 margin_reg_value
= 102;
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2917 deemph_reg_value
= 128;
2918 margin_reg_value
= 154;
2919 /* FIXME extra to set for 1200 */
2925 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2926 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2928 deemph_reg_value
= 85;
2929 margin_reg_value
= 78;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2932 deemph_reg_value
= 85;
2933 margin_reg_value
= 116;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2936 deemph_reg_value
= 85;
2937 margin_reg_value
= 154;
2943 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2944 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2946 deemph_reg_value
= 64;
2947 margin_reg_value
= 104;
2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2950 deemph_reg_value
= 64;
2951 margin_reg_value
= 154;
2957 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2958 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2960 deemph_reg_value
= 43;
2961 margin_reg_value
= 154;
2971 mutex_lock(&dev_priv
->dpio_lock
);
2973 /* Clear calc init */
2974 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2975 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2976 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2978 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2979 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2980 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2982 /* Program swing deemph */
2983 for (i
= 0; i
< 4; i
++) {
2984 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2985 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2986 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2987 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2990 /* Program swing margin */
2991 for (i
= 0; i
< 4; i
++) {
2992 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2993 val
&= ~DPIO_SWING_MARGIN000_MASK
;
2994 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
2995 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2998 /* Disable unique transition scale */
2999 for (i
= 0; i
< 4; i
++) {
3000 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3001 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3002 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3005 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3006 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3007 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3008 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3011 * The document said it needs to set bit 27 for ch0 and bit 26
3012 * for ch1. Might be a typo in the doc.
3013 * For now, for this unique transition scale selection, set bit
3014 * 27 for ch0 and ch1.
3016 for (i
= 0; i
< 4; i
++) {
3017 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3018 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3019 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3022 for (i
= 0; i
< 4; i
++) {
3023 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3024 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3025 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3026 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3030 /* Start swing calculation */
3031 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3032 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3033 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3035 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3036 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3037 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3040 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3041 val
|= DPIO_LRC_BYPASS
;
3042 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3044 mutex_unlock(&dev_priv
->dpio_lock
);
3050 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3051 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3056 uint8_t voltage_max
;
3057 uint8_t preemph_max
;
3059 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3060 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3061 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3069 voltage_max
= intel_dp_voltage_max(intel_dp
);
3070 if (v
>= voltage_max
)
3071 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3073 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3074 if (p
>= preemph_max
)
3075 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3077 for (lane
= 0; lane
< 4; lane
++)
3078 intel_dp
->train_set
[lane
] = v
| p
;
3082 intel_gen4_signal_levels(uint8_t train_set
)
3084 uint32_t signal_levels
= 0;
3086 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3089 signal_levels
|= DP_VOLTAGE_0_4
;
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3092 signal_levels
|= DP_VOLTAGE_0_6
;
3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3095 signal_levels
|= DP_VOLTAGE_0_8
;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3098 signal_levels
|= DP_VOLTAGE_1_2
;
3101 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3102 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3104 signal_levels
|= DP_PRE_EMPHASIS_0
;
3106 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3107 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3109 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3110 signal_levels
|= DP_PRE_EMPHASIS_6
;
3112 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3113 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3116 return signal_levels
;
3119 /* Gen6's DP voltage swing and pre-emphasis control */
3121 intel_gen6_edp_signal_levels(uint8_t train_set
)
3123 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3124 DP_TRAIN_PRE_EMPHASIS_MASK
);
3125 switch (signal_levels
) {
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3128 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3130 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3133 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3136 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3139 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3141 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3142 "0x%x\n", signal_levels
);
3143 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3147 /* Gen7's DP voltage swing and pre-emphasis control */
3149 intel_gen7_edp_signal_levels(uint8_t train_set
)
3151 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3152 DP_TRAIN_PRE_EMPHASIS_MASK
);
3153 switch (signal_levels
) {
3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3155 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3157 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3159 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3162 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3164 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3167 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3169 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3172 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3173 "0x%x\n", signal_levels
);
3174 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3178 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3180 intel_hsw_signal_levels(uint8_t train_set
)
3182 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3183 DP_TRAIN_PRE_EMPHASIS_MASK
);
3184 switch (signal_levels
) {
3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3186 return DDI_BUF_TRANS_SELECT(0);
3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3188 return DDI_BUF_TRANS_SELECT(1);
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3190 return DDI_BUF_TRANS_SELECT(2);
3191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3192 return DDI_BUF_TRANS_SELECT(3);
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3195 return DDI_BUF_TRANS_SELECT(4);
3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3197 return DDI_BUF_TRANS_SELECT(5);
3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3199 return DDI_BUF_TRANS_SELECT(6);
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3202 return DDI_BUF_TRANS_SELECT(7);
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3204 return DDI_BUF_TRANS_SELECT(8);
3206 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3207 "0x%x\n", signal_levels
);
3208 return DDI_BUF_TRANS_SELECT(0);
3212 /* Properly updates "DP" with the correct signal levels. */
3214 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3216 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3217 enum port port
= intel_dig_port
->port
;
3218 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3219 uint32_t signal_levels
, mask
;
3220 uint8_t train_set
= intel_dp
->train_set
[0];
3222 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3223 signal_levels
= intel_hsw_signal_levels(train_set
);
3224 mask
= DDI_BUF_EMP_MASK
;
3225 } else if (IS_CHERRYVIEW(dev
)) {
3226 signal_levels
= intel_chv_signal_levels(intel_dp
);
3228 } else if (IS_VALLEYVIEW(dev
)) {
3229 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3231 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3232 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3233 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3234 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3235 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3236 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3238 signal_levels
= intel_gen4_signal_levels(train_set
);
3239 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3242 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3244 *DP
= (*DP
& ~mask
) | signal_levels
;
3248 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3250 uint8_t dp_train_pat
)
3252 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3253 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3255 enum port port
= intel_dig_port
->port
;
3256 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3260 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
3262 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
3263 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
3265 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
3267 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3268 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3269 case DP_TRAINING_PATTERN_DISABLE
:
3270 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
3273 case DP_TRAINING_PATTERN_1
:
3274 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
3276 case DP_TRAINING_PATTERN_2
:
3277 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
3279 case DP_TRAINING_PATTERN_3
:
3280 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
3283 I915_WRITE(DP_TP_CTL(port
), temp
);
3285 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3286 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3288 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3289 case DP_TRAINING_PATTERN_DISABLE
:
3290 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
3292 case DP_TRAINING_PATTERN_1
:
3293 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
3295 case DP_TRAINING_PATTERN_2
:
3296 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
3298 case DP_TRAINING_PATTERN_3
:
3299 DRM_ERROR("DP training pattern 3 not supported\n");
3300 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
3305 if (IS_CHERRYVIEW(dev
))
3306 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3308 *DP
&= ~DP_LINK_TRAIN_MASK
;
3310 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
3311 case DP_TRAINING_PATTERN_DISABLE
:
3312 *DP
|= DP_LINK_TRAIN_OFF
;
3314 case DP_TRAINING_PATTERN_1
:
3315 *DP
|= DP_LINK_TRAIN_PAT_1
;
3317 case DP_TRAINING_PATTERN_2
:
3318 *DP
|= DP_LINK_TRAIN_PAT_2
;
3320 case DP_TRAINING_PATTERN_3
:
3321 if (IS_CHERRYVIEW(dev
)) {
3322 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
3324 DRM_ERROR("DP training pattern 3 not supported\n");
3325 *DP
|= DP_LINK_TRAIN_PAT_2
;
3331 I915_WRITE(intel_dp
->output_reg
, *DP
);
3332 POSTING_READ(intel_dp
->output_reg
);
3334 buf
[0] = dp_train_pat
;
3335 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3336 DP_TRAINING_PATTERN_DISABLE
) {
3337 /* don't write DP_TRAINING_LANEx_SET on disable */
3340 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3341 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3342 len
= intel_dp
->lane_count
+ 1;
3345 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3352 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3353 uint8_t dp_train_pat
)
3355 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3356 intel_dp_set_signal_levels(intel_dp
, DP
);
3357 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3361 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3362 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3364 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3365 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3369 intel_get_adjust_train(intel_dp
, link_status
);
3370 intel_dp_set_signal_levels(intel_dp
, DP
);
3372 I915_WRITE(intel_dp
->output_reg
, *DP
);
3373 POSTING_READ(intel_dp
->output_reg
);
3375 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3376 intel_dp
->train_set
, intel_dp
->lane_count
);
3378 return ret
== intel_dp
->lane_count
;
3381 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3383 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3384 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3386 enum port port
= intel_dig_port
->port
;
3392 val
= I915_READ(DP_TP_CTL(port
));
3393 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3394 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3395 I915_WRITE(DP_TP_CTL(port
), val
);
3398 * On PORT_A we can have only eDP in SST mode. There the only reason
3399 * we need to set idle transmission mode is to work around a HW issue
3400 * where we enable the pipe while not in idle link-training mode.
3401 * In this case there is requirement to wait for a minimum number of
3402 * idle patterns to be sent.
3407 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3409 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3412 /* Enable corresponding port and start training pattern 1 */
3414 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3416 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3417 struct drm_device
*dev
= encoder
->dev
;
3420 int voltage_tries
, loop_tries
;
3421 uint32_t DP
= intel_dp
->DP
;
3422 uint8_t link_config
[2];
3425 intel_ddi_prepare_link_retrain(encoder
);
3427 /* Write the link configuration data */
3428 link_config
[0] = intel_dp
->link_bw
;
3429 link_config
[1] = intel_dp
->lane_count
;
3430 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3431 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3432 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3435 link_config
[1] = DP_SET_ANSI_8B10B
;
3436 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3440 /* clock recovery */
3441 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3442 DP_TRAINING_PATTERN_1
|
3443 DP_LINK_SCRAMBLING_DISABLE
)) {
3444 DRM_ERROR("failed to enable link training\n");
3452 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3454 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3455 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3456 DRM_ERROR("failed to get link status\n");
3460 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3461 DRM_DEBUG_KMS("clock recovery OK\n");
3465 /* Check to see if we've tried the max voltage */
3466 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3467 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3469 if (i
== intel_dp
->lane_count
) {
3471 if (loop_tries
== 5) {
3472 DRM_ERROR("too many full retries, give up\n");
3475 intel_dp_reset_link_train(intel_dp
, &DP
,
3476 DP_TRAINING_PATTERN_1
|
3477 DP_LINK_SCRAMBLING_DISABLE
);
3482 /* Check to see if we've tried the same voltage 5 times */
3483 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3485 if (voltage_tries
== 5) {
3486 DRM_ERROR("too many voltage retries, give up\n");
3491 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3493 /* Update training set as requested by target */
3494 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3495 DRM_ERROR("failed to update link training\n");
3504 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3506 bool channel_eq
= false;
3507 int tries
, cr_tries
;
3508 uint32_t DP
= intel_dp
->DP
;
3509 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3511 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3512 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3513 training_pattern
= DP_TRAINING_PATTERN_3
;
3515 /* channel equalization */
3516 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3518 DP_LINK_SCRAMBLING_DISABLE
)) {
3519 DRM_ERROR("failed to start channel equalization\n");
3527 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3530 DRM_ERROR("failed to train DP, aborting\n");
3534 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3535 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3536 DRM_ERROR("failed to get link status\n");
3540 /* Make sure clock is still ok */
3541 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3542 intel_dp_start_link_train(intel_dp
);
3543 intel_dp_set_link_train(intel_dp
, &DP
,
3545 DP_LINK_SCRAMBLING_DISABLE
);
3550 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3555 /* Try 5 times, then try clock recovery if that fails */
3557 intel_dp_link_down(intel_dp
);
3558 intel_dp_start_link_train(intel_dp
);
3559 intel_dp_set_link_train(intel_dp
, &DP
,
3561 DP_LINK_SCRAMBLING_DISABLE
);
3567 /* Update training set as requested by target */
3568 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3569 DRM_ERROR("failed to update link training\n");
3575 intel_dp_set_idle_link_train(intel_dp
);
3580 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3584 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3586 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3587 DP_TRAINING_PATTERN_DISABLE
);
3591 intel_dp_link_down(struct intel_dp
*intel_dp
)
3593 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3594 enum port port
= intel_dig_port
->port
;
3595 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3597 struct intel_crtc
*intel_crtc
=
3598 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3599 uint32_t DP
= intel_dp
->DP
;
3601 if (WARN_ON(HAS_DDI(dev
)))
3604 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3607 DRM_DEBUG_KMS("\n");
3609 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3610 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3611 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3613 if (IS_CHERRYVIEW(dev
))
3614 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3616 DP
&= ~DP_LINK_TRAIN_MASK
;
3617 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3619 POSTING_READ(intel_dp
->output_reg
);
3621 if (HAS_PCH_IBX(dev
) &&
3622 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3623 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3625 /* Hardware workaround: leaving our transcoder select
3626 * set to transcoder B while it's off will prevent the
3627 * corresponding HDMI output on transcoder A.
3629 * Combine this with another hardware workaround:
3630 * transcoder select bit can only be cleared while the
3633 DP
&= ~DP_PIPEB_SELECT
;
3634 I915_WRITE(intel_dp
->output_reg
, DP
);
3636 /* Changes to enable or select take place the vblank
3637 * after being written.
3639 if (WARN_ON(crtc
== NULL
)) {
3640 /* We should never try to disable a port without a crtc
3641 * attached. For paranoia keep the code around for a
3643 POSTING_READ(intel_dp
->output_reg
);
3646 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3649 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3650 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3651 POSTING_READ(intel_dp
->output_reg
);
3652 msleep(intel_dp
->panel_power_down_delay
);
3656 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3658 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3659 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3662 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3663 sizeof(intel_dp
->dpcd
)) < 0)
3664 return false; /* aux transfer failed */
3666 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3668 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3669 return false; /* DPCD not present */
3671 /* Check if the panel supports PSR */
3672 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3673 if (is_edp(intel_dp
)) {
3674 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3676 sizeof(intel_dp
->psr_dpcd
));
3677 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3678 dev_priv
->psr
.sink_support
= true;
3679 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3683 /* Training Pattern 3 support */
3684 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3685 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3686 intel_dp
->use_tps3
= true;
3687 DRM_DEBUG_KMS("Displayport TPS3 supported");
3689 intel_dp
->use_tps3
= false;
3691 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3692 DP_DWN_STRM_PORT_PRESENT
))
3693 return true; /* native DP sink */
3695 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3696 return true; /* no per-port downstream info */
3698 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3699 intel_dp
->downstream_ports
,
3700 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3701 return false; /* downstream port status fetch failed */
3707 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3711 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3714 intel_edp_panel_vdd_on(intel_dp
);
3716 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3717 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3718 buf
[0], buf
[1], buf
[2]);
3720 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3721 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3722 buf
[0], buf
[1], buf
[2]);
3724 intel_edp_panel_vdd_off(intel_dp
, false);
3728 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3732 if (!intel_dp
->can_mst
)
3735 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3738 intel_edp_panel_vdd_on(intel_dp
);
3739 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3740 if (buf
[0] & DP_MST_CAP
) {
3741 DRM_DEBUG_KMS("Sink is MST capable\n");
3742 intel_dp
->is_mst
= true;
3744 DRM_DEBUG_KMS("Sink is not MST capable\n");
3745 intel_dp
->is_mst
= false;
3748 intel_edp_panel_vdd_off(intel_dp
, false);
3750 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3751 return intel_dp
->is_mst
;
3754 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3756 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3757 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3758 struct intel_crtc
*intel_crtc
=
3759 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3762 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3765 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3768 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3769 DP_TEST_SINK_START
) < 0)
3772 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3773 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3774 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3776 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3779 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3784 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3786 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3787 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3788 sink_irq_vector
, 1) == 1;
3792 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3796 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3798 sink_irq_vector
, 14);
3806 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3808 /* NAK by default */
3809 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3813 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3817 if (intel_dp
->is_mst
) {
3822 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3826 /* check link status - esi[10] = 0x200c */
3827 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3828 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3829 intel_dp_start_link_train(intel_dp
);
3830 intel_dp_complete_link_train(intel_dp
);
3831 intel_dp_stop_link_train(intel_dp
);
3834 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3835 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3838 for (retry
= 0; retry
< 3; retry
++) {
3840 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3841 DP_SINK_COUNT_ESI
+1,
3848 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3850 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3858 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3859 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3860 intel_dp
->is_mst
= false;
3861 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3862 /* send a hotplug event */
3863 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3870 * According to DP spec
3873 * 2. Configure link according to Receiver Capabilities
3874 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3875 * 4. Check link status on receipt of hot-plug interrupt
3878 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3880 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3881 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3883 u8 link_status
[DP_LINK_STATUS_SIZE
];
3885 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3887 if (!intel_encoder
->connectors_active
)
3890 if (WARN_ON(!intel_encoder
->base
.crtc
))
3893 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3896 /* Try to read receiver status if the link appears to be up */
3897 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3901 /* Now read the DPCD to see if it's actually running */
3902 if (!intel_dp_get_dpcd(intel_dp
)) {
3906 /* Try to read the source of the interrupt */
3907 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3908 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3909 /* Clear interrupt source */
3910 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3911 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3914 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3915 intel_dp_handle_test_request(intel_dp
);
3916 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3917 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3920 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3921 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3922 intel_encoder
->base
.name
);
3923 intel_dp_start_link_train(intel_dp
);
3924 intel_dp_complete_link_train(intel_dp
);
3925 intel_dp_stop_link_train(intel_dp
);
3929 /* XXX this is probably wrong for multiple downstream ports */
3930 static enum drm_connector_status
3931 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3933 uint8_t *dpcd
= intel_dp
->dpcd
;
3936 if (!intel_dp_get_dpcd(intel_dp
))
3937 return connector_status_disconnected
;
3939 /* if there's no downstream port, we're done */
3940 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3941 return connector_status_connected
;
3943 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3944 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3945 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3948 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3950 return connector_status_unknown
;
3952 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3953 : connector_status_disconnected
;
3956 /* If no HPD, poke DDC gently */
3957 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3958 return connector_status_connected
;
3960 /* Well we tried, say unknown for unreliable port types */
3961 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3962 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3963 if (type
== DP_DS_PORT_TYPE_VGA
||
3964 type
== DP_DS_PORT_TYPE_NON_EDID
)
3965 return connector_status_unknown
;
3967 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3968 DP_DWN_STRM_PORT_TYPE_MASK
;
3969 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3970 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3971 return connector_status_unknown
;
3974 /* Anything else is out of spec, warn and ignore */
3975 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3976 return connector_status_disconnected
;
3979 static enum drm_connector_status
3980 edp_detect(struct intel_dp
*intel_dp
)
3982 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3983 enum drm_connector_status status
;
3985 status
= intel_panel_detect(dev
);
3986 if (status
== connector_status_unknown
)
3987 status
= connector_status_connected
;
3992 static enum drm_connector_status
3993 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3995 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3997 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3999 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4000 return connector_status_disconnected
;
4002 return intel_dp_detect_dpcd(intel_dp
);
4005 static enum drm_connector_status
4006 g4x_dp_detect(struct intel_dp
*intel_dp
)
4008 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4010 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4013 if (IS_VALLEYVIEW(dev
)) {
4014 switch (intel_dig_port
->port
) {
4016 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4019 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4022 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4025 return connector_status_unknown
;
4028 switch (intel_dig_port
->port
) {
4030 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4033 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4036 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4039 return connector_status_unknown
;
4043 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4044 return connector_status_disconnected
;
4046 return intel_dp_detect_dpcd(intel_dp
);
4049 static struct edid
*
4050 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4052 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4054 /* use cached edid if we have one */
4055 if (intel_connector
->edid
) {
4057 if (IS_ERR(intel_connector
->edid
))
4060 return drm_edid_duplicate(intel_connector
->edid
);
4062 return drm_get_edid(&intel_connector
->base
,
4063 &intel_dp
->aux
.ddc
);
4067 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4069 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4072 edid
= intel_dp_get_edid(intel_dp
);
4073 intel_connector
->detect_edid
= edid
;
4075 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4076 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4078 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4082 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4084 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4086 kfree(intel_connector
->detect_edid
);
4087 intel_connector
->detect_edid
= NULL
;
4089 intel_dp
->has_audio
= false;
4092 static enum intel_display_power_domain
4093 intel_dp_power_get(struct intel_dp
*dp
)
4095 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4096 enum intel_display_power_domain power_domain
;
4098 power_domain
= intel_display_port_power_domain(encoder
);
4099 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4101 return power_domain
;
4105 intel_dp_power_put(struct intel_dp
*dp
,
4106 enum intel_display_power_domain power_domain
)
4108 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4109 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4112 static enum drm_connector_status
4113 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4115 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4117 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4118 struct drm_device
*dev
= connector
->dev
;
4119 enum drm_connector_status status
;
4120 enum intel_display_power_domain power_domain
;
4123 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4124 connector
->base
.id
, connector
->name
);
4125 intel_dp_unset_edid(intel_dp
);
4127 if (intel_dp
->is_mst
) {
4128 /* MST devices are disconnected from a monitor POV */
4129 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4130 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4131 return connector_status_disconnected
;
4134 power_domain
= intel_dp_power_get(intel_dp
);
4136 /* Can't disconnect eDP, but you can close the lid... */
4137 if (is_edp(intel_dp
))
4138 status
= edp_detect(intel_dp
);
4139 else if (HAS_PCH_SPLIT(dev
))
4140 status
= ironlake_dp_detect(intel_dp
);
4142 status
= g4x_dp_detect(intel_dp
);
4143 if (status
!= connector_status_connected
)
4146 intel_dp_probe_oui(intel_dp
);
4148 ret
= intel_dp_probe_mst(intel_dp
);
4150 /* if we are in MST mode then this connector
4151 won't appear connected or have anything with EDID on it */
4152 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4153 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4154 status
= connector_status_disconnected
;
4158 intel_dp_set_edid(intel_dp
);
4160 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4161 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4162 status
= connector_status_connected
;
4165 intel_dp_power_put(intel_dp
, power_domain
);
4170 intel_dp_force(struct drm_connector
*connector
)
4172 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4173 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4174 enum intel_display_power_domain power_domain
;
4176 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4177 connector
->base
.id
, connector
->name
);
4178 intel_dp_unset_edid(intel_dp
);
4180 if (connector
->status
!= connector_status_connected
)
4183 power_domain
= intel_dp_power_get(intel_dp
);
4185 intel_dp_set_edid(intel_dp
);
4187 intel_dp_power_put(intel_dp
, power_domain
);
4189 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4190 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4193 static int intel_dp_get_modes(struct drm_connector
*connector
)
4195 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4198 edid
= intel_connector
->detect_edid
;
4200 int ret
= intel_connector_update_modes(connector
, edid
);
4205 /* if eDP has no EDID, fall back to fixed mode */
4206 if (is_edp(intel_attached_dp(connector
)) &&
4207 intel_connector
->panel
.fixed_mode
) {
4208 struct drm_display_mode
*mode
;
4210 mode
= drm_mode_duplicate(connector
->dev
,
4211 intel_connector
->panel
.fixed_mode
);
4213 drm_mode_probed_add(connector
, mode
);
4222 intel_dp_detect_audio(struct drm_connector
*connector
)
4224 bool has_audio
= false;
4227 edid
= to_intel_connector(connector
)->detect_edid
;
4229 has_audio
= drm_detect_monitor_audio(edid
);
4235 intel_dp_set_property(struct drm_connector
*connector
,
4236 struct drm_property
*property
,
4239 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4240 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4241 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4242 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4245 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4249 if (property
== dev_priv
->force_audio_property
) {
4253 if (i
== intel_dp
->force_audio
)
4256 intel_dp
->force_audio
= i
;
4258 if (i
== HDMI_AUDIO_AUTO
)
4259 has_audio
= intel_dp_detect_audio(connector
);
4261 has_audio
= (i
== HDMI_AUDIO_ON
);
4263 if (has_audio
== intel_dp
->has_audio
)
4266 intel_dp
->has_audio
= has_audio
;
4270 if (property
== dev_priv
->broadcast_rgb_property
) {
4271 bool old_auto
= intel_dp
->color_range_auto
;
4272 uint32_t old_range
= intel_dp
->color_range
;
4275 case INTEL_BROADCAST_RGB_AUTO
:
4276 intel_dp
->color_range_auto
= true;
4278 case INTEL_BROADCAST_RGB_FULL
:
4279 intel_dp
->color_range_auto
= false;
4280 intel_dp
->color_range
= 0;
4282 case INTEL_BROADCAST_RGB_LIMITED
:
4283 intel_dp
->color_range_auto
= false;
4284 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4290 if (old_auto
== intel_dp
->color_range_auto
&&
4291 old_range
== intel_dp
->color_range
)
4297 if (is_edp(intel_dp
) &&
4298 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4299 if (val
== DRM_MODE_SCALE_NONE
) {
4300 DRM_DEBUG_KMS("no scaling not supported\n");
4304 if (intel_connector
->panel
.fitting_mode
== val
) {
4305 /* the eDP scaling property is not changed */
4308 intel_connector
->panel
.fitting_mode
= val
;
4316 if (intel_encoder
->base
.crtc
)
4317 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4323 intel_dp_connector_destroy(struct drm_connector
*connector
)
4325 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4327 intel_dp_unset_edid(intel_attached_dp(connector
));
4329 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4330 kfree(intel_connector
->edid
);
4332 /* Can't call is_edp() since the encoder may have been destroyed
4334 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4335 intel_panel_fini(&intel_connector
->panel
);
4337 drm_connector_cleanup(connector
);
4341 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4343 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4344 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4346 drm_dp_aux_unregister(&intel_dp
->aux
);
4347 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4348 drm_encoder_cleanup(encoder
);
4349 if (is_edp(intel_dp
)) {
4350 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4352 edp_panel_vdd_off_sync(intel_dp
);
4353 pps_unlock(intel_dp
);
4355 if (intel_dp
->edp_notifier
.notifier_call
) {
4356 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4357 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4360 kfree(intel_dig_port
);
4363 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4365 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4367 if (!is_edp(intel_dp
))
4371 edp_panel_vdd_off_sync(intel_dp
);
4372 pps_unlock(intel_dp
);
4375 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4377 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4380 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4381 .dpms
= intel_connector_dpms
,
4382 .detect
= intel_dp_detect
,
4383 .force
= intel_dp_force
,
4384 .fill_modes
= drm_helper_probe_single_connector_modes
,
4385 .set_property
= intel_dp_set_property
,
4386 .destroy
= intel_dp_connector_destroy
,
4389 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4390 .get_modes
= intel_dp_get_modes
,
4391 .mode_valid
= intel_dp_mode_valid
,
4392 .best_encoder
= intel_best_encoder
,
4395 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4396 .reset
= intel_dp_encoder_reset
,
4397 .destroy
= intel_dp_encoder_destroy
,
4401 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4407 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4409 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4410 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4411 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4413 enum intel_display_power_domain power_domain
;
4416 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4417 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4419 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4420 port_name(intel_dig_port
->port
),
4421 long_hpd
? "long" : "short");
4423 power_domain
= intel_display_port_power_domain(intel_encoder
);
4424 intel_display_power_get(dev_priv
, power_domain
);
4427 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4430 if (!intel_dp_get_dpcd(intel_dp
)) {
4434 intel_dp_probe_oui(intel_dp
);
4436 if (!intel_dp_probe_mst(intel_dp
))
4440 if (intel_dp
->is_mst
) {
4441 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4445 if (!intel_dp
->is_mst
) {
4447 * we'll check the link status via the normal hot plug path later -
4448 * but for short hpds we should check it now
4450 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4451 intel_dp_check_link_status(intel_dp
);
4452 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4458 /* if we were in MST mode, and device is not there get out of MST mode */
4459 if (intel_dp
->is_mst
) {
4460 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4461 intel_dp
->is_mst
= false;
4462 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4465 intel_display_power_put(dev_priv
, power_domain
);
4470 /* Return which DP Port should be selected for Transcoder DP control */
4472 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4474 struct drm_device
*dev
= crtc
->dev
;
4475 struct intel_encoder
*intel_encoder
;
4476 struct intel_dp
*intel_dp
;
4478 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4479 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4481 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4482 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4483 return intel_dp
->output_reg
;
4489 /* check the VBT to see whether the eDP is on DP-D port */
4490 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4493 union child_device_config
*p_child
;
4495 static const short port_mapping
[] = {
4496 [PORT_B
] = PORT_IDPB
,
4497 [PORT_C
] = PORT_IDPC
,
4498 [PORT_D
] = PORT_IDPD
,
4504 if (!dev_priv
->vbt
.child_dev_num
)
4507 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4508 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4510 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4511 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4512 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4519 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4521 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4523 intel_attach_force_audio_property(connector
);
4524 intel_attach_broadcast_rgb_property(connector
);
4525 intel_dp
->color_range_auto
= true;
4527 if (is_edp(intel_dp
)) {
4528 drm_mode_create_scaling_mode_property(connector
->dev
);
4529 drm_object_attach_property(
4531 connector
->dev
->mode_config
.scaling_mode_property
,
4532 DRM_MODE_SCALE_ASPECT
);
4533 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4537 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4539 intel_dp
->last_power_cycle
= jiffies
;
4540 intel_dp
->last_power_on
= jiffies
;
4541 intel_dp
->last_backlight_off
= jiffies
;
4545 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4546 struct intel_dp
*intel_dp
,
4547 struct edp_power_seq
*out
)
4549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4550 struct edp_power_seq cur
, vbt
, spec
, final
;
4551 u32 pp_on
, pp_off
, pp_div
, pp
;
4552 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4554 lockdep_assert_held(&dev_priv
->pps_mutex
);
4556 if (HAS_PCH_SPLIT(dev
)) {
4557 pp_ctrl_reg
= PCH_PP_CONTROL
;
4558 pp_on_reg
= PCH_PP_ON_DELAYS
;
4559 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4560 pp_div_reg
= PCH_PP_DIVISOR
;
4562 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4564 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4565 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4566 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4567 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4570 /* Workaround: Need to write PP_CONTROL with the unlock key as
4571 * the very first thing. */
4572 pp
= ironlake_get_pp_control(intel_dp
);
4573 I915_WRITE(pp_ctrl_reg
, pp
);
4575 pp_on
= I915_READ(pp_on_reg
);
4576 pp_off
= I915_READ(pp_off_reg
);
4577 pp_div
= I915_READ(pp_div_reg
);
4579 /* Pull timing values out of registers */
4580 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4581 PANEL_POWER_UP_DELAY_SHIFT
;
4583 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4584 PANEL_LIGHT_ON_DELAY_SHIFT
;
4586 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4587 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4589 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4590 PANEL_POWER_DOWN_DELAY_SHIFT
;
4592 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4593 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4595 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4596 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4598 vbt
= dev_priv
->vbt
.edp_pps
;
4600 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4601 * our hw here, which are all in 100usec. */
4602 spec
.t1_t3
= 210 * 10;
4603 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4604 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4605 spec
.t10
= 500 * 10;
4606 /* This one is special and actually in units of 100ms, but zero
4607 * based in the hw (so we need to add 100 ms). But the sw vbt
4608 * table multiplies it with 1000 to make it in units of 100usec,
4610 spec
.t11_t12
= (510 + 100) * 10;
4612 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4613 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4615 /* Use the max of the register settings and vbt. If both are
4616 * unset, fall back to the spec limits. */
4617 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4619 max(cur.field, vbt.field))
4620 assign_final(t1_t3
);
4624 assign_final(t11_t12
);
4627 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4628 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4629 intel_dp
->backlight_on_delay
= get_delay(t8
);
4630 intel_dp
->backlight_off_delay
= get_delay(t9
);
4631 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4632 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4635 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4636 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4637 intel_dp
->panel_power_cycle_delay
);
4639 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4640 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4647 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4648 struct intel_dp
*intel_dp
,
4649 struct edp_power_seq
*seq
)
4651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4652 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4653 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4654 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4655 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4657 lockdep_assert_held(&dev_priv
->pps_mutex
);
4659 if (HAS_PCH_SPLIT(dev
)) {
4660 pp_on_reg
= PCH_PP_ON_DELAYS
;
4661 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4662 pp_div_reg
= PCH_PP_DIVISOR
;
4664 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4666 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4667 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4668 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4672 * And finally store the new values in the power sequencer. The
4673 * backlight delays are set to 1 because we do manual waits on them. For
4674 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4675 * we'll end up waiting for the backlight off delay twice: once when we
4676 * do the manual sleep, and once when we disable the panel and wait for
4677 * the PP_STATUS bit to become zero.
4679 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4680 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4681 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4682 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4683 /* Compute the divisor for the pp clock, simply match the Bspec
4685 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4686 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4687 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4689 /* Haswell doesn't have any port selection bits for the panel
4690 * power sequencer any more. */
4691 if (IS_VALLEYVIEW(dev
)) {
4692 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4693 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4695 port_sel
= PANEL_PORT_SELECT_DPA
;
4697 port_sel
= PANEL_PORT_SELECT_DPD
;
4702 I915_WRITE(pp_on_reg
, pp_on
);
4703 I915_WRITE(pp_off_reg
, pp_off
);
4704 I915_WRITE(pp_div_reg
, pp_div
);
4706 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4707 I915_READ(pp_on_reg
),
4708 I915_READ(pp_off_reg
),
4709 I915_READ(pp_div_reg
));
4712 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4715 struct intel_encoder
*encoder
;
4716 struct intel_dp
*intel_dp
= NULL
;
4717 struct intel_crtc_config
*config
= NULL
;
4718 struct intel_crtc
*intel_crtc
= NULL
;
4719 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4721 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4723 if (refresh_rate
<= 0) {
4724 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4728 if (intel_connector
== NULL
) {
4729 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4734 * FIXME: This needs proper synchronization with psr state. But really
4735 * hard to tell without seeing the user of this function of this code.
4736 * Check locking and ordering once that lands.
4738 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4739 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4743 encoder
= intel_attached_encoder(&intel_connector
->base
);
4744 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4745 intel_crtc
= encoder
->new_crtc
;
4748 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4752 config
= &intel_crtc
->config
;
4754 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4755 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4759 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4760 index
= DRRS_LOW_RR
;
4762 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4764 "DRRS requested for previously set RR...ignoring\n");
4768 if (!intel_crtc
->active
) {
4769 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4773 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4774 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4775 val
= I915_READ(reg
);
4776 if (index
> DRRS_HIGH_RR
) {
4777 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4778 intel_dp_set_m_n(intel_crtc
);
4780 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4782 I915_WRITE(reg
, val
);
4786 * mutex taken to ensure that there is no race between differnt
4787 * drrs calls trying to update refresh rate. This scenario may occur
4788 * in future when idleness detection based DRRS in kernel and
4789 * possible calls from user space to set differnt RR are made.
4792 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4794 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4796 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4798 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4801 static struct drm_display_mode
*
4802 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4803 struct intel_connector
*intel_connector
,
4804 struct drm_display_mode
*fixed_mode
)
4806 struct drm_connector
*connector
= &intel_connector
->base
;
4807 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4808 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4810 struct drm_display_mode
*downclock_mode
= NULL
;
4812 if (INTEL_INFO(dev
)->gen
<= 6) {
4813 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4817 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4818 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4822 downclock_mode
= intel_find_panel_downclock
4823 (dev
, fixed_mode
, connector
);
4825 if (!downclock_mode
) {
4826 DRM_DEBUG_KMS("DRRS not supported\n");
4830 dev_priv
->drrs
.connector
= intel_connector
;
4832 mutex_init(&intel_dp
->drrs_state
.mutex
);
4834 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4836 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4837 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4838 return downclock_mode
;
4841 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
4843 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4845 struct intel_dp
*intel_dp
;
4846 enum intel_display_power_domain power_domain
;
4848 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4851 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4855 if (!edp_have_panel_vdd(intel_dp
))
4858 * The VDD bit needs a power domain reference, so if the bit is
4859 * already enabled when we boot or resume, grab this reference and
4860 * schedule a vdd off, so we don't hold on to the reference
4863 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4864 power_domain
= intel_display_port_power_domain(intel_encoder
);
4865 intel_display_power_get(dev_priv
, power_domain
);
4867 edp_panel_vdd_schedule_off(intel_dp
);
4869 pps_unlock(intel_dp
);
4872 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4873 struct intel_connector
*intel_connector
,
4874 struct edp_power_seq
*power_seq
)
4876 struct drm_connector
*connector
= &intel_connector
->base
;
4877 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4878 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4879 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4881 struct drm_display_mode
*fixed_mode
= NULL
;
4882 struct drm_display_mode
*downclock_mode
= NULL
;
4884 struct drm_display_mode
*scan
;
4887 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4889 if (!is_edp(intel_dp
))
4892 intel_edp_panel_vdd_sanitize(intel_encoder
);
4894 /* Cache DPCD and EDID for edp. */
4895 intel_edp_panel_vdd_on(intel_dp
);
4896 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4897 intel_edp_panel_vdd_off(intel_dp
, false);
4900 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4901 dev_priv
->no_aux_handshake
=
4902 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4903 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4905 /* if this fails, presume the device is a ghost */
4906 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4910 /* We now know it's not a ghost, init power sequence regs. */
4912 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4913 pps_unlock(intel_dp
);
4915 mutex_lock(&dev
->mode_config
.mutex
);
4916 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4918 if (drm_add_edid_modes(connector
, edid
)) {
4919 drm_mode_connector_update_edid_property(connector
,
4921 drm_edid_to_eld(connector
, edid
);
4924 edid
= ERR_PTR(-EINVAL
);
4927 edid
= ERR_PTR(-ENOENT
);
4929 intel_connector
->edid
= edid
;
4931 /* prefer fixed mode from EDID if available */
4932 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4933 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4934 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4935 downclock_mode
= intel_dp_drrs_init(
4937 intel_connector
, fixed_mode
);
4942 /* fallback to VBT if available for eDP */
4943 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4944 fixed_mode
= drm_mode_duplicate(dev
,
4945 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4947 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4949 mutex_unlock(&dev
->mode_config
.mutex
);
4951 if (IS_VALLEYVIEW(dev
)) {
4952 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
4953 register_reboot_notifier(&intel_dp
->edp_notifier
);
4956 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4957 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
4958 intel_panel_setup_backlight(connector
);
4964 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4965 struct intel_connector
*intel_connector
)
4967 struct drm_connector
*connector
= &intel_connector
->base
;
4968 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4969 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4970 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4972 enum port port
= intel_dig_port
->port
;
4973 struct edp_power_seq power_seq
= { 0 };
4976 intel_dp
->pps_pipe
= INVALID_PIPE
;
4978 /* intel_dp vfuncs */
4979 if (IS_VALLEYVIEW(dev
))
4980 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
4981 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4982 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
4983 else if (HAS_PCH_SPLIT(dev
))
4984 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
4986 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
4988 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
4990 /* Preserve the current hw state. */
4991 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4992 intel_dp
->attached_connector
= intel_connector
;
4994 if (intel_dp_is_edp(dev
, port
))
4995 type
= DRM_MODE_CONNECTOR_eDP
;
4997 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5000 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5001 * for DP the encoder type can be set by the caller to
5002 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5004 if (type
== DRM_MODE_CONNECTOR_eDP
)
5005 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5007 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5008 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5011 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5012 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5014 connector
->interlace_allowed
= true;
5015 connector
->doublescan_allowed
= 0;
5017 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5018 edp_panel_vdd_work
);
5020 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5021 drm_connector_register(connector
);
5024 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5026 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5027 intel_connector
->unregister
= intel_dp_connector_unregister
;
5029 /* Set up the hotplug pin. */
5032 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5035 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5038 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5041 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5047 if (is_edp(intel_dp
)) {
5049 if (IS_VALLEYVIEW(dev
)) {
5050 vlv_initial_power_sequencer_setup(intel_dp
);
5052 intel_dp_init_panel_power_timestamps(intel_dp
);
5053 intel_dp_init_panel_power_sequencer(dev
, intel_dp
,
5056 pps_unlock(intel_dp
);
5059 intel_dp_aux_init(intel_dp
, intel_connector
);
5061 /* init MST on ports that can support it */
5062 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5063 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5064 intel_dp_mst_encoder_init(intel_dig_port
,
5065 intel_connector
->base
.base
.id
);
5069 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
5070 drm_dp_aux_unregister(&intel_dp
->aux
);
5071 if (is_edp(intel_dp
)) {
5072 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5074 edp_panel_vdd_off_sync(intel_dp
);
5075 pps_unlock(intel_dp
);
5077 drm_connector_unregister(connector
);
5078 drm_connector_cleanup(connector
);
5082 intel_dp_add_properties(intel_dp
, connector
);
5084 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5085 * 0xd. Failure to do so will result in spurious interrupts being
5086 * generated on the port when a cable is not attached.
5088 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5089 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5090 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5097 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5100 struct intel_digital_port
*intel_dig_port
;
5101 struct intel_encoder
*intel_encoder
;
5102 struct drm_encoder
*encoder
;
5103 struct intel_connector
*intel_connector
;
5105 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5106 if (!intel_dig_port
)
5109 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5110 if (!intel_connector
) {
5111 kfree(intel_dig_port
);
5115 intel_encoder
= &intel_dig_port
->base
;
5116 encoder
= &intel_encoder
->base
;
5118 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5119 DRM_MODE_ENCODER_TMDS
);
5121 intel_encoder
->compute_config
= intel_dp_compute_config
;
5122 intel_encoder
->disable
= intel_disable_dp
;
5123 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5124 intel_encoder
->get_config
= intel_dp_get_config
;
5125 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5126 if (IS_CHERRYVIEW(dev
)) {
5127 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5128 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5129 intel_encoder
->enable
= vlv_enable_dp
;
5130 intel_encoder
->post_disable
= chv_post_disable_dp
;
5131 } else if (IS_VALLEYVIEW(dev
)) {
5132 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5133 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5134 intel_encoder
->enable
= vlv_enable_dp
;
5135 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5137 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5138 intel_encoder
->enable
= g4x_enable_dp
;
5139 intel_encoder
->post_disable
= g4x_post_disable_dp
;
5142 intel_dig_port
->port
= port
;
5143 intel_dig_port
->dp
.output_reg
= output_reg
;
5145 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5146 if (IS_CHERRYVIEW(dev
)) {
5148 intel_encoder
->crtc_mask
= 1 << 2;
5150 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5152 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5154 intel_encoder
->cloneable
= 0;
5155 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5157 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5158 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5160 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5161 drm_encoder_cleanup(encoder
);
5162 kfree(intel_dig_port
);
5163 kfree(intel_connector
);
5167 void intel_dp_mst_suspend(struct drm_device
*dev
)
5169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5173 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5174 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5175 if (!intel_dig_port
)
5178 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5179 if (!intel_dig_port
->dp
.can_mst
)
5181 if (intel_dig_port
->dp
.is_mst
)
5182 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5187 void intel_dp_mst_resume(struct drm_device
*dev
)
5189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5192 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5193 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5194 if (!intel_dig_port
)
5196 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5199 if (!intel_dig_port
->dp
.can_mst
)
5202 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5204 intel_dp_check_mst_status(&intel_dig_port
->dp
);