2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int chv_rates
[] = { 162000, 202500, 210000, 216000,
99 243000, 270000, 324000, 405000,
100 420000, 432000, 540000 };
101 static const int default_rates
[] = { 162000, 270000, 540000 };
104 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
105 * @intel_dp: DP struct
107 * If a CPU or PCH DP output is attached to an eDP panel, this function
108 * will return true, and false otherwise.
110 static bool is_edp(struct intel_dp
*intel_dp
)
112 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
114 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
117 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
119 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
121 return intel_dig_port
->base
.base
.dev
;
124 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
126 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
129 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
130 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
131 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
132 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
133 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
137 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
139 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
141 switch (max_link_bw
) {
142 case DP_LINK_BW_1_62
:
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw
= DP_LINK_BW_1_62
;
155 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
157 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
158 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
159 u8 source_max
, sink_max
;
162 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
163 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
166 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
168 return min(source_max
, sink_max
);
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 * 270000 * 1 * 8 / 10 == 216000
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
189 intel_dp_link_required(int pixel_clock
, int bpp
)
191 return (pixel_clock
* bpp
+ 9) / 10;
195 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
197 return (max_link_clock
* max_lanes
* 8) / 10;
200 static enum drm_mode_status
201 intel_dp_mode_valid(struct drm_connector
*connector
,
202 struct drm_display_mode
*mode
)
204 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
205 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
206 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
207 int target_clock
= mode
->clock
;
208 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
210 if (is_edp(intel_dp
) && fixed_mode
) {
211 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
214 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
217 target_clock
= fixed_mode
->clock
;
220 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
221 max_lanes
= intel_dp_max_lane_count(intel_dp
);
223 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
224 mode_rate
= intel_dp_link_required(target_clock
, 18);
226 if (mode_rate
> max_rate
)
227 return MODE_CLOCK_HIGH
;
229 if (mode
->clock
< 10000)
230 return MODE_CLOCK_LOW
;
232 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
233 return MODE_H_ILLEGAL
;
238 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
245 for (i
= 0; i
< src_bytes
; i
++)
246 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
250 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
255 for (i
= 0; i
< dst_bytes
; i
++)
256 dst
[i
] = src
>> ((3-i
) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev
))
270 clkcfg
= I915_READ(CLKCFG
);
271 switch (clkcfg
& CLKCFG_FSB_MASK
) {
280 case CLKCFG_FSB_1067
:
282 case CLKCFG_FSB_1333
:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600
:
286 case CLKCFG_FSB_1600_ALT
:
294 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
295 struct intel_dp
*intel_dp
);
297 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
298 struct intel_dp
*intel_dp
);
300 static void pps_lock(struct intel_dp
*intel_dp
)
302 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
303 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
304 struct drm_device
*dev
= encoder
->base
.dev
;
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 enum intel_display_power_domain power_domain
;
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
312 power_domain
= intel_display_port_power_domain(encoder
);
313 intel_display_power_get(dev_priv
, power_domain
);
315 mutex_lock(&dev_priv
->pps_mutex
);
318 static void pps_unlock(struct intel_dp
*intel_dp
)
320 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
321 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
322 struct drm_device
*dev
= encoder
->base
.dev
;
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 enum intel_display_power_domain power_domain
;
326 mutex_unlock(&dev_priv
->pps_mutex
);
328 power_domain
= intel_display_port_power_domain(encoder
);
329 intel_display_power_put(dev_priv
, power_domain
);
333 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
336 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
338 enum pipe pipe
= intel_dp
->pps_pipe
;
342 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe
), port_name(intel_dig_port
->port
));
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
353 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
354 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
355 DP
|= DP_PORT_WIDTH(1);
356 DP
|= DP_LINK_TRAIN_PAT_1
;
358 if (IS_CHERRYVIEW(dev
))
359 DP
|= DP_PIPE_SELECT_CHV(pipe
);
360 else if (pipe
== PIPE_B
)
361 DP
|= DP_PIPEB_SELECT
;
363 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
370 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
371 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
379 I915_WRITE(intel_dp
->output_reg
, DP
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
385 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
386 POSTING_READ(intel_dp
->output_reg
);
389 vlv_force_pll_off(dev
, pipe
);
393 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
396 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
398 struct intel_encoder
*encoder
;
399 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
402 lockdep_assert_held(&dev_priv
->pps_mutex
);
404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp
));
407 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
408 return intel_dp
->pps_pipe
;
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
414 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
456 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
459 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
465 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
471 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
478 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
480 vlv_pipe_check pipe_check
)
484 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
485 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
486 PANEL_PORT_SELECT_MASK
;
488 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
491 if (!pipe_check(dev_priv
, pipe
))
501 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
503 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
504 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 enum port port
= intel_dig_port
->port
;
508 lockdep_assert_held(&dev_priv
->pps_mutex
);
510 /* try to find a pipe with this port selected */
511 /* first pick one where the panel is on */
512 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
516 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
517 vlv_pipe_has_vdd_on
);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
520 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
533 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
534 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
537 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
539 struct drm_device
*dev
= dev_priv
->dev
;
540 struct intel_encoder
*encoder
;
542 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
555 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
556 struct intel_dp
*intel_dp
;
558 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
561 intel_dp
= enc_to_intel_dp(&encoder
->base
);
562 intel_dp
->pps_pipe
= INVALID_PIPE
;
566 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
568 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
570 if (HAS_PCH_SPLIT(dev
))
571 return PCH_PP_CONTROL
;
573 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
576 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
578 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
580 if (HAS_PCH_SPLIT(dev
))
581 return PCH_PP_STATUS
;
583 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
586 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
587 This function only applicable when panel PM state is not to be tracked */
588 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
591 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
593 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
596 u32 pp_ctrl_reg
, pp_div_reg
;
598 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
603 if (IS_VALLEYVIEW(dev
)) {
604 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
606 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
607 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
608 pp_div
= I915_READ(pp_div_reg
);
609 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
611 /* 0x1F write to PP_DIV_REG sets max cycle delay */
612 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
613 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
614 msleep(intel_dp
->panel_power_cycle_delay
);
617 pps_unlock(intel_dp
);
622 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
624 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
627 lockdep_assert_held(&dev_priv
->pps_mutex
);
629 if (IS_VALLEYVIEW(dev
) &&
630 intel_dp
->pps_pipe
== INVALID_PIPE
)
633 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
636 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
638 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
641 lockdep_assert_held(&dev_priv
->pps_mutex
);
643 if (IS_VALLEYVIEW(dev
) &&
644 intel_dp
->pps_pipe
== INVALID_PIPE
)
647 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
651 intel_dp_check_edp(struct intel_dp
*intel_dp
)
653 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
656 if (!is_edp(intel_dp
))
659 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
660 WARN(1, "eDP powered off while attempting aux channel communication.\n");
661 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
662 I915_READ(_pp_stat_reg(intel_dp
)),
663 I915_READ(_pp_ctrl_reg(intel_dp
)));
668 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
670 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
671 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
673 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
677 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
679 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
680 msecs_to_jiffies_timeout(10));
682 done
= wait_for_atomic(C
, 10) == 0;
684 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
691 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
693 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
694 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
697 * The clock divider is based off the hrawclk, and would like to run at
698 * 2MHz. So, take the hrawclk value and divide by 2 and use that
700 return index
? 0 : intel_hrawclk(dev
) / 2;
703 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
705 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
706 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
712 if (intel_dig_port
->port
== PORT_A
) {
713 return DIV_ROUND_UP(dev_priv
->cdclk_freq
, 2000);
716 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
720 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
722 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
723 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
726 if (intel_dig_port
->port
== PORT_A
) {
729 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
730 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
731 /* Workaround for non-ULT HSW */
738 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
742 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
744 return index
? 0 : 100;
747 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
750 * SKL doesn't need us to program the AUX clock divider (Hardware will
751 * derive the clock from CDCLK automatically). We still implement the
752 * get_aux_clock_divider vfunc to plug-in into the existing code.
754 return index
? 0 : 1;
757 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
760 uint32_t aux_clock_divider
)
762 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
763 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
764 uint32_t precharge
, timeout
;
771 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
772 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
774 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
776 return DP_AUX_CH_CTL_SEND_BUSY
|
778 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
779 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
781 DP_AUX_CH_CTL_RECEIVE_ERROR
|
782 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
783 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
784 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
787 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
792 return DP_AUX_CH_CTL_SEND_BUSY
|
794 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
795 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
796 DP_AUX_CH_CTL_TIME_OUT_1600us
|
797 DP_AUX_CH_CTL_RECEIVE_ERROR
|
798 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
799 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
803 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
804 const uint8_t *send
, int send_bytes
,
805 uint8_t *recv
, int recv_size
)
807 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
808 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
810 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
811 uint32_t ch_data
= ch_ctl
+ 4;
812 uint32_t aux_clock_divider
;
813 int i
, ret
, recv_bytes
;
816 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
822 * We will be called with VDD already enabled for dpcd/edid/oui reads.
823 * In such cases we want to leave VDD enabled and it's up to upper layers
824 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
827 vdd
= edp_panel_vdd_on(intel_dp
);
829 /* dp aux is extremely sensitive to irq latency, hence request the
830 * lowest possible wakeup latency and so prevent the cpu from going into
833 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
835 intel_dp_check_edp(intel_dp
);
837 intel_aux_display_runtime_get(dev_priv
);
839 /* Try to wait for any previous AUX channel activity */
840 for (try = 0; try < 3; try++) {
841 status
= I915_READ_NOTRACE(ch_ctl
);
842 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
848 WARN(1, "dp_aux_ch not started status 0x%08x\n",
854 /* Only 5 data registers! */
855 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
860 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
861 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
866 /* Must try at least 3 times according to DP spec */
867 for (try = 0; try < 5; try++) {
868 /* Load the send data into the aux channel data registers */
869 for (i
= 0; i
< send_bytes
; i
+= 4)
870 I915_WRITE(ch_data
+ i
,
871 intel_dp_pack_aux(send
+ i
,
874 /* Send the command and wait for it to complete */
875 I915_WRITE(ch_ctl
, send_ctl
);
877 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
879 /* Clear done status and any errors */
883 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
884 DP_AUX_CH_CTL_RECEIVE_ERROR
);
886 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
889 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
890 * 400us delay required for errors and timeouts
891 * Timeout errors from the HW already meet this
892 * requirement so skip to next iteration
894 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
895 usleep_range(400, 500);
898 if (status
& DP_AUX_CH_CTL_DONE
)
901 if (status
& DP_AUX_CH_CTL_DONE
)
905 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
906 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
911 /* Check for timeout or receive error.
912 * Timeouts occur when the sink is not connected
914 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
915 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
920 /* Timeouts occur when the device isn't connected, so they're
921 * "normal" -- don't fill the kernel log with these */
922 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
923 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
928 /* Unload any bytes sent back from the other side */
929 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
930 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
931 if (recv_bytes
> recv_size
)
932 recv_bytes
= recv_size
;
934 for (i
= 0; i
< recv_bytes
; i
+= 4)
935 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
936 recv
+ i
, recv_bytes
- i
);
940 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
941 intel_aux_display_runtime_put(dev_priv
);
944 edp_panel_vdd_off(intel_dp
, false);
946 pps_unlock(intel_dp
);
951 #define BARE_ADDRESS_SIZE 3
952 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
954 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
956 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
957 uint8_t txbuf
[20], rxbuf
[20];
958 size_t txsize
, rxsize
;
961 txbuf
[0] = (msg
->request
<< 4) |
962 ((msg
->address
>> 16) & 0xf);
963 txbuf
[1] = (msg
->address
>> 8) & 0xff;
964 txbuf
[2] = msg
->address
& 0xff;
965 txbuf
[3] = msg
->size
- 1;
967 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
968 case DP_AUX_NATIVE_WRITE
:
969 case DP_AUX_I2C_WRITE
:
970 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
971 rxsize
= 2; /* 0 or 1 data bytes */
973 if (WARN_ON(txsize
> 20))
976 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
978 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
980 msg
->reply
= rxbuf
[0] >> 4;
983 /* Number of bytes written in a short write. */
984 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
986 /* Return payload size. */
992 case DP_AUX_NATIVE_READ
:
993 case DP_AUX_I2C_READ
:
994 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
995 rxsize
= msg
->size
+ 1;
997 if (WARN_ON(rxsize
> 20))
1000 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1002 msg
->reply
= rxbuf
[0] >> 4;
1004 * Assume happy day, and copy the data. The caller is
1005 * expected to check msg->reply before touching it.
1007 * Return payload size.
1010 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1023 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1025 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1026 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1027 enum port port
= intel_dig_port
->port
;
1028 const char *name
= NULL
;
1033 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1037 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1041 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1045 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1053 * The AUX_CTL register is usually DP_CTL + 0x10.
1055 * On Haswell and Broadwell though:
1056 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1057 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1059 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1061 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1062 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1064 intel_dp
->aux
.name
= name
;
1065 intel_dp
->aux
.dev
= dev
->dev
;
1066 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1068 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1069 connector
->base
.kdev
->kobj
.name
);
1071 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1073 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1078 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1079 &intel_dp
->aux
.ddc
.dev
.kobj
,
1080 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1082 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1083 drm_dp_aux_unregister(&intel_dp
->aux
);
1088 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1090 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1092 if (!intel_connector
->mst_port
)
1093 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1094 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1095 intel_connector_unregister(intel_connector
);
1099 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
, int link_clock
)
1103 memset(&pipe_config
->dpll_hw_state
, 0,
1104 sizeof(pipe_config
->dpll_hw_state
));
1106 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1107 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1108 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1110 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1111 switch (link_clock
/ 2) {
1113 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
1117 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
,
1121 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
,
1125 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
,
1128 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1129 results in CDCLK change. Need to handle the change of CDCLK by
1130 disabling pipes and re-enabling them */
1132 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
1136 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
,
1141 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1145 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
, int link_bw
)
1148 case DP_LINK_BW_1_62
:
1149 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1151 case DP_LINK_BW_2_7
:
1152 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1154 case DP_LINK_BW_5_4
:
1155 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1161 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1163 if (intel_dp
->num_sink_rates
) {
1164 *sink_rates
= intel_dp
->sink_rates
;
1165 return intel_dp
->num_sink_rates
;
1168 *sink_rates
= default_rates
;
1170 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1174 intel_dp_source_rates(struct drm_device
*dev
, const int **source_rates
)
1176 if (IS_BROXTON(dev
)) {
1177 *source_rates
= bxt_rates
;
1178 return ARRAY_SIZE(bxt_rates
);
1179 } else if (IS_SKYLAKE(dev
)) {
1180 *source_rates
= skl_rates
;
1181 return ARRAY_SIZE(skl_rates
);
1182 } else if (IS_CHERRYVIEW(dev
)) {
1183 *source_rates
= chv_rates
;
1184 return ARRAY_SIZE(chv_rates
);
1187 *source_rates
= default_rates
;
1189 if (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
)
1190 /* WaDisableHBR2:skl */
1191 return (DP_LINK_BW_2_7
>> 3) + 1;
1192 else if (INTEL_INFO(dev
)->gen
>= 8 ||
1193 (IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)))
1194 return (DP_LINK_BW_5_4
>> 3) + 1;
1196 return (DP_LINK_BW_2_7
>> 3) + 1;
1200 intel_dp_set_clock(struct intel_encoder
*encoder
,
1201 struct intel_crtc_state
*pipe_config
, int link_bw
)
1203 struct drm_device
*dev
= encoder
->base
.dev
;
1204 const struct dp_link_dpll
*divisor
= NULL
;
1208 divisor
= gen4_dpll
;
1209 count
= ARRAY_SIZE(gen4_dpll
);
1210 } else if (HAS_PCH_SPLIT(dev
)) {
1212 count
= ARRAY_SIZE(pch_dpll
);
1213 } else if (IS_CHERRYVIEW(dev
)) {
1215 count
= ARRAY_SIZE(chv_dpll
);
1216 } else if (IS_VALLEYVIEW(dev
)) {
1218 count
= ARRAY_SIZE(vlv_dpll
);
1221 if (divisor
&& count
) {
1222 for (i
= 0; i
< count
; i
++) {
1223 if (link_bw
== divisor
[i
].link_bw
) {
1224 pipe_config
->dpll
= divisor
[i
].dpll
;
1225 pipe_config
->clock_set
= true;
1232 static int intersect_rates(const int *source_rates
, int source_len
,
1233 const int *sink_rates
, int sink_len
,
1236 int i
= 0, j
= 0, k
= 0;
1238 while (i
< source_len
&& j
< sink_len
) {
1239 if (source_rates
[i
] == sink_rates
[j
]) {
1240 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1242 common_rates
[k
] = source_rates
[i
];
1246 } else if (source_rates
[i
] < sink_rates
[j
]) {
1255 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1258 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1259 const int *source_rates
, *sink_rates
;
1260 int source_len
, sink_len
;
1262 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1263 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1265 return intersect_rates(source_rates
, source_len
,
1266 sink_rates
, sink_len
,
1270 static void snprintf_int_array(char *str
, size_t len
,
1271 const int *array
, int nelem
)
1277 for (i
= 0; i
< nelem
; i
++) {
1278 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1286 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1288 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1289 const int *source_rates
, *sink_rates
;
1290 int source_len
, sink_len
, common_len
;
1291 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1292 char str
[128]; /* FIXME: too big for stack? */
1294 if ((drm_debug
& DRM_UT_KMS
) == 0)
1297 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1298 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1299 DRM_DEBUG_KMS("source rates: %s\n", str
);
1301 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1302 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1303 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1305 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1306 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1307 DRM_DEBUG_KMS("common rates: %s\n", str
);
1310 static int rate_to_index(int find
, const int *rates
)
1314 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1315 if (find
== rates
[i
])
1322 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1324 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1327 len
= intel_dp_common_rates(intel_dp
, rates
);
1328 if (WARN_ON(len
<= 0))
1331 return rates
[rate_to_index(0, rates
) - 1];
1334 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1336 return rate_to_index(rate
, intel_dp
->sink_rates
);
1340 intel_dp_compute_config(struct intel_encoder
*encoder
,
1341 struct intel_crtc_state
*pipe_config
)
1343 struct drm_device
*dev
= encoder
->base
.dev
;
1344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1345 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1346 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1347 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1348 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1349 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1350 int lane_count
, clock
;
1351 int min_lane_count
= 1;
1352 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1353 /* Conveniently, the link BW constants become indices with a shift...*/
1357 int link_avail
, link_clock
;
1358 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1361 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1363 /* No common link rates between source and sink */
1364 WARN_ON(common_len
<= 0);
1366 max_clock
= common_len
- 1;
1368 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1369 pipe_config
->has_pch_encoder
= true;
1371 pipe_config
->has_dp_encoder
= true;
1372 pipe_config
->has_drrs
= false;
1373 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1375 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1376 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1379 if (INTEL_INFO(dev
)->gen
>= 9) {
1381 ret
= skl_update_scaler_users(intel_crtc
, pipe_config
, NULL
, NULL
, 0);
1386 if (!HAS_PCH_SPLIT(dev
))
1387 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1388 intel_connector
->panel
.fitting_mode
);
1390 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1391 intel_connector
->panel
.fitting_mode
);
1394 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1397 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1398 "max bw %d pixel clock %iKHz\n",
1399 max_lane_count
, common_rates
[max_clock
],
1400 adjusted_mode
->crtc_clock
);
1402 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1403 * bpc in between. */
1404 bpp
= pipe_config
->pipe_bpp
;
1405 if (is_edp(intel_dp
)) {
1406 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1407 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1408 dev_priv
->vbt
.edp_bpp
);
1409 bpp
= dev_priv
->vbt
.edp_bpp
;
1413 * Use the maximum clock and number of lanes the eDP panel
1414 * advertizes being capable of. The panels are generally
1415 * designed to support only a single clock and lane
1416 * configuration, and typically these values correspond to the
1417 * native resolution of the panel.
1419 min_lane_count
= max_lane_count
;
1420 min_clock
= max_clock
;
1423 for (; bpp
>= 6*3; bpp
-= 2*3) {
1424 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1427 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1428 for (lane_count
= min_lane_count
;
1429 lane_count
<= max_lane_count
;
1432 link_clock
= common_rates
[clock
];
1433 link_avail
= intel_dp_max_data_rate(link_clock
,
1436 if (mode_rate
<= link_avail
) {
1446 if (intel_dp
->color_range_auto
) {
1449 * CEA-861-E - 5.1 Default Encoding Parameters
1450 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1452 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1453 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1455 intel_dp
->color_range
= 0;
1458 if (intel_dp
->color_range
)
1459 pipe_config
->limited_color_range
= true;
1461 intel_dp
->lane_count
= lane_count
;
1463 if (intel_dp
->num_sink_rates
) {
1464 intel_dp
->link_bw
= 0;
1465 intel_dp
->rate_select
=
1466 intel_dp_rate_select(intel_dp
, common_rates
[clock
]);
1469 drm_dp_link_rate_to_bw_code(common_rates
[clock
]);
1470 intel_dp
->rate_select
= 0;
1473 pipe_config
->pipe_bpp
= bpp
;
1474 pipe_config
->port_clock
= common_rates
[clock
];
1476 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1477 intel_dp
->link_bw
, intel_dp
->lane_count
,
1478 pipe_config
->port_clock
, bpp
);
1479 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1480 mode_rate
, link_avail
);
1482 intel_link_compute_m_n(bpp
, lane_count
,
1483 adjusted_mode
->crtc_clock
,
1484 pipe_config
->port_clock
,
1485 &pipe_config
->dp_m_n
);
1487 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1488 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1489 pipe_config
->has_drrs
= true;
1490 intel_link_compute_m_n(bpp
, lane_count
,
1491 intel_connector
->panel
.downclock_mode
->clock
,
1492 pipe_config
->port_clock
,
1493 &pipe_config
->dp_m2_n2
);
1496 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1497 skl_edp_set_pll_config(pipe_config
, common_rates
[clock
]);
1498 else if (IS_BROXTON(dev
))
1499 /* handled in ddi */;
1500 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1501 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1503 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1508 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1510 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1511 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1512 struct drm_device
*dev
= crtc
->base
.dev
;
1513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1516 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1517 crtc
->config
->port_clock
);
1518 dpa_ctl
= I915_READ(DP_A
);
1519 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1521 if (crtc
->config
->port_clock
== 162000) {
1522 /* For a long time we've carried around a ILK-DevA w/a for the
1523 * 160MHz clock. If we're really unlucky, it's still required.
1525 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1526 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1527 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1529 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1530 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1533 I915_WRITE(DP_A
, dpa_ctl
);
1539 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1541 struct drm_device
*dev
= encoder
->base
.dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1544 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1545 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1546 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1549 * There are four kinds of DP registers:
1556 * IBX PCH and CPU are the same for almost everything,
1557 * except that the CPU DP PLL is configured in this
1560 * CPT PCH is quite different, having many bits moved
1561 * to the TRANS_DP_CTL register instead. That
1562 * configuration happens (oddly) in ironlake_pch_enable
1565 /* Preserve the BIOS-computed detected bit. This is
1566 * supposed to be read-only.
1568 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1570 /* Handle DP bits in common between all three register formats */
1571 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1572 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1574 if (crtc
->config
->has_audio
)
1575 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1577 /* Split out the IBX/CPU vs CPT settings */
1579 if (IS_GEN7(dev
) && port
== PORT_A
) {
1580 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1581 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1582 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1583 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1584 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1586 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1587 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1589 intel_dp
->DP
|= crtc
->pipe
<< 29;
1590 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1593 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1595 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1596 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1597 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1599 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1600 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1602 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1603 intel_dp
->DP
|= intel_dp
->color_range
;
1605 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1606 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1607 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1608 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1609 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1611 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1612 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1614 if (IS_CHERRYVIEW(dev
))
1615 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1616 else if (crtc
->pipe
== PIPE_B
)
1617 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1621 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1622 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1624 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1625 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1627 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1628 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1630 static void wait_panel_status(struct intel_dp
*intel_dp
,
1634 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1636 u32 pp_stat_reg
, pp_ctrl_reg
;
1638 lockdep_assert_held(&dev_priv
->pps_mutex
);
1640 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1641 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1643 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1645 I915_READ(pp_stat_reg
),
1646 I915_READ(pp_ctrl_reg
));
1648 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1649 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1650 I915_READ(pp_stat_reg
),
1651 I915_READ(pp_ctrl_reg
));
1654 DRM_DEBUG_KMS("Wait complete\n");
1657 static void wait_panel_on(struct intel_dp
*intel_dp
)
1659 DRM_DEBUG_KMS("Wait for panel power on\n");
1660 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1663 static void wait_panel_off(struct intel_dp
*intel_dp
)
1665 DRM_DEBUG_KMS("Wait for panel power off time\n");
1666 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1669 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1671 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1673 /* When we disable the VDD override bit last we have to do the manual
1675 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1676 intel_dp
->panel_power_cycle_delay
);
1678 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1681 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1683 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1684 intel_dp
->backlight_on_delay
);
1687 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1689 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1690 intel_dp
->backlight_off_delay
);
1693 /* Read the current pp_control value, unlocking the register if it
1697 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1699 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 lockdep_assert_held(&dev_priv
->pps_mutex
);
1705 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1706 control
&= ~PANEL_UNLOCK_MASK
;
1707 control
|= PANEL_UNLOCK_REGS
;
1712 * Must be paired with edp_panel_vdd_off().
1713 * Must hold pps_mutex around the whole on/off sequence.
1714 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1716 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1718 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1720 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1722 enum intel_display_power_domain power_domain
;
1724 u32 pp_stat_reg
, pp_ctrl_reg
;
1725 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1727 lockdep_assert_held(&dev_priv
->pps_mutex
);
1729 if (!is_edp(intel_dp
))
1732 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1733 intel_dp
->want_panel_vdd
= true;
1735 if (edp_have_panel_vdd(intel_dp
))
1736 return need_to_disable
;
1738 power_domain
= intel_display_port_power_domain(intel_encoder
);
1739 intel_display_power_get(dev_priv
, power_domain
);
1741 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1742 port_name(intel_dig_port
->port
));
1744 if (!edp_have_panel_power(intel_dp
))
1745 wait_panel_power_cycle(intel_dp
);
1747 pp
= ironlake_get_pp_control(intel_dp
);
1748 pp
|= EDP_FORCE_VDD
;
1750 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1751 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1753 I915_WRITE(pp_ctrl_reg
, pp
);
1754 POSTING_READ(pp_ctrl_reg
);
1755 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1756 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1758 * If the panel wasn't on, delay before accessing aux channel
1760 if (!edp_have_panel_power(intel_dp
)) {
1761 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1762 port_name(intel_dig_port
->port
));
1763 msleep(intel_dp
->panel_power_up_delay
);
1766 return need_to_disable
;
1770 * Must be paired with intel_edp_panel_vdd_off() or
1771 * intel_edp_panel_off().
1772 * Nested calls to these functions are not allowed since
1773 * we drop the lock. Caller must use some higher level
1774 * locking to prevent nested calls from other threads.
1776 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1780 if (!is_edp(intel_dp
))
1784 vdd
= edp_panel_vdd_on(intel_dp
);
1785 pps_unlock(intel_dp
);
1787 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1788 port_name(dp_to_dig_port(intel_dp
)->port
));
1791 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1793 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1795 struct intel_digital_port
*intel_dig_port
=
1796 dp_to_dig_port(intel_dp
);
1797 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1798 enum intel_display_power_domain power_domain
;
1800 u32 pp_stat_reg
, pp_ctrl_reg
;
1802 lockdep_assert_held(&dev_priv
->pps_mutex
);
1804 WARN_ON(intel_dp
->want_panel_vdd
);
1806 if (!edp_have_panel_vdd(intel_dp
))
1809 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1810 port_name(intel_dig_port
->port
));
1812 pp
= ironlake_get_pp_control(intel_dp
);
1813 pp
&= ~EDP_FORCE_VDD
;
1815 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1816 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1818 I915_WRITE(pp_ctrl_reg
, pp
);
1819 POSTING_READ(pp_ctrl_reg
);
1821 /* Make sure sequencer is idle before allowing subsequent activity */
1822 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1823 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1825 if ((pp
& POWER_TARGET_ON
) == 0)
1826 intel_dp
->last_power_cycle
= jiffies
;
1828 power_domain
= intel_display_port_power_domain(intel_encoder
);
1829 intel_display_power_put(dev_priv
, power_domain
);
1832 static void edp_panel_vdd_work(struct work_struct
*__work
)
1834 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1835 struct intel_dp
, panel_vdd_work
);
1838 if (!intel_dp
->want_panel_vdd
)
1839 edp_panel_vdd_off_sync(intel_dp
);
1840 pps_unlock(intel_dp
);
1843 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1845 unsigned long delay
;
1848 * Queue the timer to fire a long time from now (relative to the power
1849 * down delay) to keep the panel power up across a sequence of
1852 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1853 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1857 * Must be paired with edp_panel_vdd_on().
1858 * Must hold pps_mutex around the whole on/off sequence.
1859 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1861 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1863 struct drm_i915_private
*dev_priv
=
1864 intel_dp_to_dev(intel_dp
)->dev_private
;
1866 lockdep_assert_held(&dev_priv
->pps_mutex
);
1868 if (!is_edp(intel_dp
))
1871 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1872 port_name(dp_to_dig_port(intel_dp
)->port
));
1874 intel_dp
->want_panel_vdd
= false;
1877 edp_panel_vdd_off_sync(intel_dp
);
1879 edp_panel_vdd_schedule_off(intel_dp
);
1882 static void edp_panel_on(struct intel_dp
*intel_dp
)
1884 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1889 lockdep_assert_held(&dev_priv
->pps_mutex
);
1891 if (!is_edp(intel_dp
))
1894 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1895 port_name(dp_to_dig_port(intel_dp
)->port
));
1897 if (WARN(edp_have_panel_power(intel_dp
),
1898 "eDP port %c panel power already on\n",
1899 port_name(dp_to_dig_port(intel_dp
)->port
)))
1902 wait_panel_power_cycle(intel_dp
);
1904 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1905 pp
= ironlake_get_pp_control(intel_dp
);
1907 /* ILK workaround: disable reset around power sequence */
1908 pp
&= ~PANEL_POWER_RESET
;
1909 I915_WRITE(pp_ctrl_reg
, pp
);
1910 POSTING_READ(pp_ctrl_reg
);
1913 pp
|= POWER_TARGET_ON
;
1915 pp
|= PANEL_POWER_RESET
;
1917 I915_WRITE(pp_ctrl_reg
, pp
);
1918 POSTING_READ(pp_ctrl_reg
);
1920 wait_panel_on(intel_dp
);
1921 intel_dp
->last_power_on
= jiffies
;
1924 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1925 I915_WRITE(pp_ctrl_reg
, pp
);
1926 POSTING_READ(pp_ctrl_reg
);
1930 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1932 if (!is_edp(intel_dp
))
1936 edp_panel_on(intel_dp
);
1937 pps_unlock(intel_dp
);
1941 static void edp_panel_off(struct intel_dp
*intel_dp
)
1943 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1944 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1945 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1947 enum intel_display_power_domain power_domain
;
1951 lockdep_assert_held(&dev_priv
->pps_mutex
);
1953 if (!is_edp(intel_dp
))
1956 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1957 port_name(dp_to_dig_port(intel_dp
)->port
));
1959 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1960 port_name(dp_to_dig_port(intel_dp
)->port
));
1962 pp
= ironlake_get_pp_control(intel_dp
);
1963 /* We need to switch off panel power _and_ force vdd, for otherwise some
1964 * panels get very unhappy and cease to work. */
1965 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1968 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1970 intel_dp
->want_panel_vdd
= false;
1972 I915_WRITE(pp_ctrl_reg
, pp
);
1973 POSTING_READ(pp_ctrl_reg
);
1975 intel_dp
->last_power_cycle
= jiffies
;
1976 wait_panel_off(intel_dp
);
1978 /* We got a reference when we enabled the VDD. */
1979 power_domain
= intel_display_port_power_domain(intel_encoder
);
1980 intel_display_power_put(dev_priv
, power_domain
);
1983 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1985 if (!is_edp(intel_dp
))
1989 edp_panel_off(intel_dp
);
1990 pps_unlock(intel_dp
);
1993 /* Enable backlight in the panel power control. */
1994 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1996 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1997 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2003 * If we enable the backlight right away following a panel power
2004 * on, we may see slight flicker as the panel syncs with the eDP
2005 * link. So delay a bit to make sure the image is solid before
2006 * allowing it to appear.
2008 wait_backlight_on(intel_dp
);
2012 pp
= ironlake_get_pp_control(intel_dp
);
2013 pp
|= EDP_BLC_ENABLE
;
2015 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2017 I915_WRITE(pp_ctrl_reg
, pp
);
2018 POSTING_READ(pp_ctrl_reg
);
2020 pps_unlock(intel_dp
);
2023 /* Enable backlight PWM and backlight PP control. */
2024 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2026 if (!is_edp(intel_dp
))
2029 DRM_DEBUG_KMS("\n");
2031 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2032 _intel_edp_backlight_on(intel_dp
);
2035 /* Disable backlight in the panel power control. */
2036 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2038 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2043 if (!is_edp(intel_dp
))
2048 pp
= ironlake_get_pp_control(intel_dp
);
2049 pp
&= ~EDP_BLC_ENABLE
;
2051 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2053 I915_WRITE(pp_ctrl_reg
, pp
);
2054 POSTING_READ(pp_ctrl_reg
);
2056 pps_unlock(intel_dp
);
2058 intel_dp
->last_backlight_off
= jiffies
;
2059 edp_wait_backlight_off(intel_dp
);
2062 /* Disable backlight PP control and backlight PWM. */
2063 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2065 if (!is_edp(intel_dp
))
2068 DRM_DEBUG_KMS("\n");
2070 _intel_edp_backlight_off(intel_dp
);
2071 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2075 * Hook for controlling the panel power control backlight through the bl_power
2076 * sysfs attribute. Take care to handle multiple calls.
2078 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2081 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2085 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2086 pps_unlock(intel_dp
);
2088 if (is_enabled
== enable
)
2091 DRM_DEBUG_KMS("panel power control backlight %s\n",
2092 enable
? "enable" : "disable");
2095 _intel_edp_backlight_on(intel_dp
);
2097 _intel_edp_backlight_off(intel_dp
);
2100 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2102 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2103 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2104 struct drm_device
*dev
= crtc
->dev
;
2105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2108 assert_pipe_disabled(dev_priv
,
2109 to_intel_crtc(crtc
)->pipe
);
2111 DRM_DEBUG_KMS("\n");
2112 dpa_ctl
= I915_READ(DP_A
);
2113 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
2114 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2116 /* We don't adjust intel_dp->DP while tearing down the link, to
2117 * facilitate link retraining (e.g. after hotplug). Hence clear all
2118 * enable bits here to ensure that we don't enable too much. */
2119 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
2120 intel_dp
->DP
|= DP_PLL_ENABLE
;
2121 I915_WRITE(DP_A
, intel_dp
->DP
);
2126 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2128 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2129 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2130 struct drm_device
*dev
= crtc
->dev
;
2131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2134 assert_pipe_disabled(dev_priv
,
2135 to_intel_crtc(crtc
)->pipe
);
2137 dpa_ctl
= I915_READ(DP_A
);
2138 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
2139 "dp pll off, should be on\n");
2140 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2142 /* We can't rely on the value tracked for the DP register in
2143 * intel_dp->DP because link_down must not change that (otherwise link
2144 * re-training will fail. */
2145 dpa_ctl
&= ~DP_PLL_ENABLE
;
2146 I915_WRITE(DP_A
, dpa_ctl
);
2151 /* If the sink supports it, try to set the power state appropriately */
2152 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2156 /* Should have a valid DPCD by this point */
2157 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2160 if (mode
!= DRM_MODE_DPMS_ON
) {
2161 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2165 * When turning on, we need to retry for 1ms to give the sink
2168 for (i
= 0; i
< 3; i
++) {
2169 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2178 DRM_DEBUG_KMS("failed to %s sink power state\n",
2179 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2182 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2185 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2186 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2187 struct drm_device
*dev
= encoder
->base
.dev
;
2188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2189 enum intel_display_power_domain power_domain
;
2192 power_domain
= intel_display_port_power_domain(encoder
);
2193 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2196 tmp
= I915_READ(intel_dp
->output_reg
);
2198 if (!(tmp
& DP_PORT_EN
))
2201 if (IS_GEN7(dev
) && port
== PORT_A
) {
2202 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2203 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2206 for_each_pipe(dev_priv
, p
) {
2207 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2208 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2214 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2215 intel_dp
->output_reg
);
2216 } else if (IS_CHERRYVIEW(dev
)) {
2217 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2219 *pipe
= PORT_TO_PIPE(tmp
);
2225 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2226 struct intel_crtc_state
*pipe_config
)
2228 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2230 struct drm_device
*dev
= encoder
->base
.dev
;
2231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2232 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2233 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2236 tmp
= I915_READ(intel_dp
->output_reg
);
2238 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2240 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2241 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2242 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2243 flags
|= DRM_MODE_FLAG_PHSYNC
;
2245 flags
|= DRM_MODE_FLAG_NHSYNC
;
2247 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2248 flags
|= DRM_MODE_FLAG_PVSYNC
;
2250 flags
|= DRM_MODE_FLAG_NVSYNC
;
2252 if (tmp
& DP_SYNC_HS_HIGH
)
2253 flags
|= DRM_MODE_FLAG_PHSYNC
;
2255 flags
|= DRM_MODE_FLAG_NHSYNC
;
2257 if (tmp
& DP_SYNC_VS_HIGH
)
2258 flags
|= DRM_MODE_FLAG_PVSYNC
;
2260 flags
|= DRM_MODE_FLAG_NVSYNC
;
2263 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2265 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2266 tmp
& DP_COLOR_RANGE_16_235
)
2267 pipe_config
->limited_color_range
= true;
2269 pipe_config
->has_dp_encoder
= true;
2271 intel_dp_get_m_n(crtc
, pipe_config
);
2273 if (port
== PORT_A
) {
2274 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2275 pipe_config
->port_clock
= 162000;
2277 pipe_config
->port_clock
= 270000;
2280 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2281 &pipe_config
->dp_m_n
);
2283 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2284 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2286 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2288 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2289 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2291 * This is a big fat ugly hack.
2293 * Some machines in UEFI boot mode provide us a VBT that has 18
2294 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2295 * unknown we fail to light up. Yet the same BIOS boots up with
2296 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2297 * max, not what it tells us to use.
2299 * Note: This will still be broken if the eDP panel is not lit
2300 * up by the BIOS, and thus we can't get the mode at module
2303 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2304 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2305 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2309 static void intel_disable_dp(struct intel_encoder
*encoder
)
2311 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2312 struct drm_device
*dev
= encoder
->base
.dev
;
2313 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2315 if (crtc
->config
->has_audio
)
2316 intel_audio_codec_disable(encoder
);
2318 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2319 intel_psr_disable(intel_dp
);
2321 /* Make sure the panel is off before trying to change the mode. But also
2322 * ensure that we have vdd while we switch off the panel. */
2323 intel_edp_panel_vdd_on(intel_dp
);
2324 intel_edp_backlight_off(intel_dp
);
2325 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2326 intel_edp_panel_off(intel_dp
);
2328 /* disable the port before the pipe on g4x */
2329 if (INTEL_INFO(dev
)->gen
< 5)
2330 intel_dp_link_down(intel_dp
);
2333 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2335 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2336 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2338 intel_dp_link_down(intel_dp
);
2340 ironlake_edp_pll_off(intel_dp
);
2343 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2345 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2347 intel_dp_link_down(intel_dp
);
2350 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2352 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2353 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2354 struct drm_device
*dev
= encoder
->base
.dev
;
2355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2356 struct intel_crtc
*intel_crtc
=
2357 to_intel_crtc(encoder
->base
.crtc
);
2358 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2359 enum pipe pipe
= intel_crtc
->pipe
;
2362 intel_dp_link_down(intel_dp
);
2364 mutex_lock(&dev_priv
->sb_lock
);
2366 /* Propagate soft reset to data lane reset */
2367 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2368 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2369 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2371 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2372 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2373 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2375 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2376 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2377 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2379 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2380 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2381 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2383 mutex_unlock(&dev_priv
->sb_lock
);
2387 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2389 uint8_t dp_train_pat
)
2391 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2392 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2394 enum port port
= intel_dig_port
->port
;
2397 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2399 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2400 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2402 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2404 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2405 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2406 case DP_TRAINING_PATTERN_DISABLE
:
2407 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2410 case DP_TRAINING_PATTERN_1
:
2411 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2413 case DP_TRAINING_PATTERN_2
:
2414 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2416 case DP_TRAINING_PATTERN_3
:
2417 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2420 I915_WRITE(DP_TP_CTL(port
), temp
);
2422 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2423 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2424 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2426 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2427 case DP_TRAINING_PATTERN_DISABLE
:
2428 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2430 case DP_TRAINING_PATTERN_1
:
2431 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2433 case DP_TRAINING_PATTERN_2
:
2434 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2436 case DP_TRAINING_PATTERN_3
:
2437 DRM_ERROR("DP training pattern 3 not supported\n");
2438 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2443 if (IS_CHERRYVIEW(dev
))
2444 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2446 *DP
&= ~DP_LINK_TRAIN_MASK
;
2448 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2449 case DP_TRAINING_PATTERN_DISABLE
:
2450 *DP
|= DP_LINK_TRAIN_OFF
;
2452 case DP_TRAINING_PATTERN_1
:
2453 *DP
|= DP_LINK_TRAIN_PAT_1
;
2455 case DP_TRAINING_PATTERN_2
:
2456 *DP
|= DP_LINK_TRAIN_PAT_2
;
2458 case DP_TRAINING_PATTERN_3
:
2459 if (IS_CHERRYVIEW(dev
)) {
2460 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2462 DRM_ERROR("DP training pattern 3 not supported\n");
2463 *DP
|= DP_LINK_TRAIN_PAT_2
;
2470 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2472 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2475 /* enable with pattern 1 (as per spec) */
2476 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2477 DP_TRAINING_PATTERN_1
);
2479 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2480 POSTING_READ(intel_dp
->output_reg
);
2483 * Magic for VLV/CHV. We _must_ first set up the register
2484 * without actually enabling the port, and then do another
2485 * write to enable the port. Otherwise link training will
2486 * fail when the power sequencer is freshly used for this port.
2488 intel_dp
->DP
|= DP_PORT_EN
;
2490 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2491 POSTING_READ(intel_dp
->output_reg
);
2494 static void intel_enable_dp(struct intel_encoder
*encoder
)
2496 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2497 struct drm_device
*dev
= encoder
->base
.dev
;
2498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2499 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2500 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2501 unsigned int lane_mask
= 0x0;
2503 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2508 if (IS_VALLEYVIEW(dev
))
2509 vlv_init_panel_power_sequencer(intel_dp
);
2511 intel_dp_enable_port(intel_dp
);
2513 edp_panel_vdd_on(intel_dp
);
2514 edp_panel_on(intel_dp
);
2515 edp_panel_vdd_off(intel_dp
, true);
2517 pps_unlock(intel_dp
);
2519 if (IS_VALLEYVIEW(dev
))
2520 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2523 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2524 intel_dp_start_link_train(intel_dp
);
2525 intel_dp_complete_link_train(intel_dp
);
2526 intel_dp_stop_link_train(intel_dp
);
2528 if (crtc
->config
->has_audio
) {
2529 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2530 pipe_name(crtc
->pipe
));
2531 intel_audio_codec_enable(encoder
);
2535 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2537 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2539 intel_enable_dp(encoder
);
2540 intel_edp_backlight_on(intel_dp
);
2543 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2545 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2547 intel_edp_backlight_on(intel_dp
);
2548 intel_psr_enable(intel_dp
);
2551 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2553 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2554 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2556 intel_dp_prepare(encoder
);
2558 /* Only ilk+ has port A */
2559 if (dport
->port
== PORT_A
) {
2560 ironlake_set_pll_cpu_edp(intel_dp
);
2561 ironlake_edp_pll_on(intel_dp
);
2565 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2567 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2568 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2569 enum pipe pipe
= intel_dp
->pps_pipe
;
2570 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2572 edp_panel_vdd_off_sync(intel_dp
);
2575 * VLV seems to get confused when multiple power seqeuencers
2576 * have the same port selected (even if only one has power/vdd
2577 * enabled). The failure manifests as vlv_wait_port_ready() failing
2578 * CHV on the other hand doesn't seem to mind having the same port
2579 * selected in multiple power seqeuencers, but let's clear the
2580 * port select always when logically disconnecting a power sequencer
2583 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2584 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2585 I915_WRITE(pp_on_reg
, 0);
2586 POSTING_READ(pp_on_reg
);
2588 intel_dp
->pps_pipe
= INVALID_PIPE
;
2591 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2595 struct intel_encoder
*encoder
;
2597 lockdep_assert_held(&dev_priv
->pps_mutex
);
2599 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2602 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2604 struct intel_dp
*intel_dp
;
2607 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2610 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2611 port
= dp_to_dig_port(intel_dp
)->port
;
2613 if (intel_dp
->pps_pipe
!= pipe
)
2616 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2617 pipe_name(pipe
), port_name(port
));
2619 WARN(encoder
->connectors_active
,
2620 "stealing pipe %c power sequencer from active eDP port %c\n",
2621 pipe_name(pipe
), port_name(port
));
2623 /* make sure vdd is off before we steal it */
2624 vlv_detach_power_sequencer(intel_dp
);
2628 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2630 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2631 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2632 struct drm_device
*dev
= encoder
->base
.dev
;
2633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2634 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2636 lockdep_assert_held(&dev_priv
->pps_mutex
);
2638 if (!is_edp(intel_dp
))
2641 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2645 * If another power sequencer was being used on this
2646 * port previously make sure to turn off vdd there while
2647 * we still have control of it.
2649 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2650 vlv_detach_power_sequencer(intel_dp
);
2653 * We may be stealing the power
2654 * sequencer from another port.
2656 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2658 /* now it's all ours */
2659 intel_dp
->pps_pipe
= crtc
->pipe
;
2661 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2662 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2664 /* init power sequencer on this pipe and port */
2665 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2666 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2669 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2671 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2672 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2673 struct drm_device
*dev
= encoder
->base
.dev
;
2674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2675 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2676 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2677 int pipe
= intel_crtc
->pipe
;
2680 mutex_lock(&dev_priv
->sb_lock
);
2682 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2689 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2690 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2691 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2693 mutex_unlock(&dev_priv
->sb_lock
);
2695 intel_enable_dp(encoder
);
2698 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2700 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2701 struct drm_device
*dev
= encoder
->base
.dev
;
2702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2703 struct intel_crtc
*intel_crtc
=
2704 to_intel_crtc(encoder
->base
.crtc
);
2705 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2706 int pipe
= intel_crtc
->pipe
;
2708 intel_dp_prepare(encoder
);
2710 /* Program Tx lane resets to default */
2711 mutex_lock(&dev_priv
->sb_lock
);
2712 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2713 DPIO_PCS_TX_LANE2_RESET
|
2714 DPIO_PCS_TX_LANE1_RESET
);
2715 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2716 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2717 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2718 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2719 DPIO_PCS_CLK_SOFT_RESET
);
2721 /* Fix up inter-pair skew failure */
2722 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2723 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2724 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2725 mutex_unlock(&dev_priv
->sb_lock
);
2728 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2730 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2731 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2732 struct drm_device
*dev
= encoder
->base
.dev
;
2733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2734 struct intel_crtc
*intel_crtc
=
2735 to_intel_crtc(encoder
->base
.crtc
);
2736 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2737 int pipe
= intel_crtc
->pipe
;
2738 int data
, i
, stagger
;
2741 mutex_lock(&dev_priv
->sb_lock
);
2743 /* allow hardware to manage TX FIFO reset source */
2744 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2745 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2746 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2748 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2749 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2750 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2752 /* Deassert soft data lane reset*/
2753 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2754 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2755 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2757 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2758 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2759 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2761 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2762 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2763 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2765 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2766 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2767 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2769 /* Program Tx lane latency optimal setting*/
2770 for (i
= 0; i
< 4; i
++) {
2771 /* Set the upar bit */
2772 data
= (i
== 1) ? 0x0 : 0x1;
2773 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2774 data
<< DPIO_UPAR_SHIFT
);
2777 /* Data lane stagger programming */
2778 if (intel_crtc
->config
->port_clock
> 270000)
2780 else if (intel_crtc
->config
->port_clock
> 135000)
2782 else if (intel_crtc
->config
->port_clock
> 67500)
2784 else if (intel_crtc
->config
->port_clock
> 33750)
2789 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2790 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2791 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2793 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2794 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2795 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2797 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
2798 DPIO_LANESTAGGER_STRAP(stagger
) |
2799 DPIO_LANESTAGGER_STRAP_OVRD
|
2800 DPIO_TX1_STAGGER_MASK(0x1f) |
2801 DPIO_TX1_STAGGER_MULT(6) |
2802 DPIO_TX2_STAGGER_MULT(0));
2804 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
2805 DPIO_LANESTAGGER_STRAP(stagger
) |
2806 DPIO_LANESTAGGER_STRAP_OVRD
|
2807 DPIO_TX1_STAGGER_MASK(0x1f) |
2808 DPIO_TX1_STAGGER_MULT(7) |
2809 DPIO_TX2_STAGGER_MULT(5));
2811 mutex_unlock(&dev_priv
->sb_lock
);
2813 intel_enable_dp(encoder
);
2816 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2818 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2819 struct drm_device
*dev
= encoder
->base
.dev
;
2820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2821 struct intel_crtc
*intel_crtc
=
2822 to_intel_crtc(encoder
->base
.crtc
);
2823 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2824 enum pipe pipe
= intel_crtc
->pipe
;
2827 intel_dp_prepare(encoder
);
2829 mutex_lock(&dev_priv
->sb_lock
);
2831 /* program left/right clock distribution */
2832 if (pipe
!= PIPE_B
) {
2833 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2834 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2836 val
|= CHV_BUFLEFTENA1_FORCE
;
2838 val
|= CHV_BUFRIGHTENA1_FORCE
;
2839 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2841 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2842 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2844 val
|= CHV_BUFLEFTENA2_FORCE
;
2846 val
|= CHV_BUFRIGHTENA2_FORCE
;
2847 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2850 /* program clock channel usage */
2851 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2852 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2854 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2856 val
|= CHV_PCS_USEDCLKCHANNEL
;
2857 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2859 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2860 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2862 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2864 val
|= CHV_PCS_USEDCLKCHANNEL
;
2865 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2868 * This a a bit weird since generally CL
2869 * matches the pipe, but here we need to
2870 * pick the CL based on the port.
2872 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2874 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2876 val
|= CHV_CMN_USEDCLKCHANNEL
;
2877 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2879 mutex_unlock(&dev_priv
->sb_lock
);
2883 * Native read with retry for link status and receiver capability reads for
2884 * cases where the sink may still be asleep.
2886 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2887 * supposed to retry 3 times per the spec.
2890 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2891 void *buffer
, size_t size
)
2897 * Sometime we just get the same incorrect byte repeated
2898 * over the entire buffer. Doing just one throw away read
2899 * initially seems to "solve" it.
2901 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2903 for (i
= 0; i
< 3; i
++) {
2904 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2914 * Fetch AUX CH registers 0x202 - 0x207 which contain
2915 * link status information
2918 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2920 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2923 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2926 /* These are source-specific values. */
2928 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2930 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2932 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2934 if (IS_BROXTON(dev
))
2935 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2936 else if (INTEL_INFO(dev
)->gen
>= 9) {
2937 if (dev_priv
->edp_low_vswing
&& port
== PORT_A
)
2938 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2939 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2940 } else if (IS_VALLEYVIEW(dev
))
2941 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2942 else if (IS_GEN7(dev
) && port
== PORT_A
)
2943 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2944 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2945 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2947 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2951 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2953 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2954 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2956 if (INTEL_INFO(dev
)->gen
>= 9) {
2957 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2965 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2967 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2969 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2970 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2972 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2974 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2976 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2979 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2981 } else if (IS_VALLEYVIEW(dev
)) {
2982 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2983 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2984 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2986 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2987 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2988 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2991 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2993 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2994 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2996 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2998 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2999 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3001 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3004 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3005 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3006 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3008 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3010 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3013 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3018 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3020 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3022 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3023 struct intel_crtc
*intel_crtc
=
3024 to_intel_crtc(dport
->base
.base
.crtc
);
3025 unsigned long demph_reg_value
, preemph_reg_value
,
3026 uniqtranscale_reg_value
;
3027 uint8_t train_set
= intel_dp
->train_set
[0];
3028 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3029 int pipe
= intel_crtc
->pipe
;
3031 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3032 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3033 preemph_reg_value
= 0x0004000;
3034 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3036 demph_reg_value
= 0x2B405555;
3037 uniqtranscale_reg_value
= 0x552AB83A;
3039 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3040 demph_reg_value
= 0x2B404040;
3041 uniqtranscale_reg_value
= 0x5548B83A;
3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3044 demph_reg_value
= 0x2B245555;
3045 uniqtranscale_reg_value
= 0x5560B83A;
3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3048 demph_reg_value
= 0x2B405555;
3049 uniqtranscale_reg_value
= 0x5598DA3A;
3055 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3056 preemph_reg_value
= 0x0002000;
3057 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3059 demph_reg_value
= 0x2B404040;
3060 uniqtranscale_reg_value
= 0x5552B83A;
3062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3063 demph_reg_value
= 0x2B404848;
3064 uniqtranscale_reg_value
= 0x5580B83A;
3066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3067 demph_reg_value
= 0x2B404040;
3068 uniqtranscale_reg_value
= 0x55ADDA3A;
3074 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3075 preemph_reg_value
= 0x0000000;
3076 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3078 demph_reg_value
= 0x2B305555;
3079 uniqtranscale_reg_value
= 0x5570B83A;
3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3082 demph_reg_value
= 0x2B2B4040;
3083 uniqtranscale_reg_value
= 0x55ADDA3A;
3089 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3090 preemph_reg_value
= 0x0006000;
3091 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3093 demph_reg_value
= 0x1B405555;
3094 uniqtranscale_reg_value
= 0x55ADDA3A;
3104 mutex_lock(&dev_priv
->sb_lock
);
3105 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3106 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3107 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3108 uniqtranscale_reg_value
);
3109 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3110 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3111 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3112 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3113 mutex_unlock(&dev_priv
->sb_lock
);
3118 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3120 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3122 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3123 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3124 u32 deemph_reg_value
, margin_reg_value
, val
;
3125 uint8_t train_set
= intel_dp
->train_set
[0];
3126 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3127 enum pipe pipe
= intel_crtc
->pipe
;
3130 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3131 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3132 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3134 deemph_reg_value
= 128;
3135 margin_reg_value
= 52;
3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3138 deemph_reg_value
= 128;
3139 margin_reg_value
= 77;
3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3142 deemph_reg_value
= 128;
3143 margin_reg_value
= 102;
3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3146 deemph_reg_value
= 128;
3147 margin_reg_value
= 154;
3148 /* FIXME extra to set for 1200 */
3154 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3155 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3157 deemph_reg_value
= 85;
3158 margin_reg_value
= 78;
3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3161 deemph_reg_value
= 85;
3162 margin_reg_value
= 116;
3164 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3165 deemph_reg_value
= 85;
3166 margin_reg_value
= 154;
3172 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3173 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3175 deemph_reg_value
= 64;
3176 margin_reg_value
= 104;
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3179 deemph_reg_value
= 64;
3180 margin_reg_value
= 154;
3186 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3187 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3189 deemph_reg_value
= 43;
3190 margin_reg_value
= 154;
3200 mutex_lock(&dev_priv
->sb_lock
);
3202 /* Clear calc init */
3203 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3204 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3205 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3206 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3207 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3209 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3210 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3211 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3212 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3213 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3215 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3216 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3217 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3218 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3220 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3221 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3222 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3223 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3225 /* Program swing deemph */
3226 for (i
= 0; i
< 4; i
++) {
3227 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3228 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3229 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3230 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3233 /* Program swing margin */
3234 for (i
= 0; i
< 4; i
++) {
3235 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3236 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3237 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3238 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3241 /* Disable unique transition scale */
3242 for (i
= 0; i
< 4; i
++) {
3243 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3244 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3245 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3248 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3249 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3250 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3251 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3254 * The document said it needs to set bit 27 for ch0 and bit 26
3255 * for ch1. Might be a typo in the doc.
3256 * For now, for this unique transition scale selection, set bit
3257 * 27 for ch0 and ch1.
3259 for (i
= 0; i
< 4; i
++) {
3260 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3261 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3262 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3265 for (i
= 0; i
< 4; i
++) {
3266 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3267 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3268 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3269 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3273 /* Start swing calculation */
3274 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3275 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3276 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3278 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3279 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3280 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3283 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3284 val
|= DPIO_LRC_BYPASS
;
3285 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3287 mutex_unlock(&dev_priv
->sb_lock
);
3293 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3294 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3299 uint8_t voltage_max
;
3300 uint8_t preemph_max
;
3302 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3303 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3304 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3312 voltage_max
= intel_dp_voltage_max(intel_dp
);
3313 if (v
>= voltage_max
)
3314 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3316 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3317 if (p
>= preemph_max
)
3318 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3320 for (lane
= 0; lane
< 4; lane
++)
3321 intel_dp
->train_set
[lane
] = v
| p
;
3325 gen4_signal_levels(uint8_t train_set
)
3327 uint32_t signal_levels
= 0;
3329 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3332 signal_levels
|= DP_VOLTAGE_0_4
;
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3335 signal_levels
|= DP_VOLTAGE_0_6
;
3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3338 signal_levels
|= DP_VOLTAGE_0_8
;
3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3341 signal_levels
|= DP_VOLTAGE_1_2
;
3344 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3345 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3347 signal_levels
|= DP_PRE_EMPHASIS_0
;
3349 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3350 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3352 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3353 signal_levels
|= DP_PRE_EMPHASIS_6
;
3355 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3356 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3359 return signal_levels
;
3362 /* Gen6's DP voltage swing and pre-emphasis control */
3364 gen6_edp_signal_levels(uint8_t train_set
)
3366 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3367 DP_TRAIN_PRE_EMPHASIS_MASK
);
3368 switch (signal_levels
) {
3369 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3370 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3371 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3372 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3373 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3376 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3378 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3379 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3381 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3382 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3384 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3385 "0x%x\n", signal_levels
);
3386 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3390 /* Gen7's DP voltage swing and pre-emphasis control */
3392 gen7_edp_signal_levels(uint8_t train_set
)
3394 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3395 DP_TRAIN_PRE_EMPHASIS_MASK
);
3396 switch (signal_levels
) {
3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3398 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3400 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3402 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3404 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3405 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3406 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3407 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3409 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3410 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3411 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3412 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3415 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3416 "0x%x\n", signal_levels
);
3417 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3421 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3423 hsw_signal_levels(uint8_t train_set
)
3425 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3426 DP_TRAIN_PRE_EMPHASIS_MASK
);
3427 switch (signal_levels
) {
3428 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3429 return DDI_BUF_TRANS_SELECT(0);
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3431 return DDI_BUF_TRANS_SELECT(1);
3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3433 return DDI_BUF_TRANS_SELECT(2);
3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3435 return DDI_BUF_TRANS_SELECT(3);
3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3438 return DDI_BUF_TRANS_SELECT(4);
3439 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3440 return DDI_BUF_TRANS_SELECT(5);
3441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3442 return DDI_BUF_TRANS_SELECT(6);
3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3445 return DDI_BUF_TRANS_SELECT(7);
3446 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3447 return DDI_BUF_TRANS_SELECT(8);
3449 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3450 return DDI_BUF_TRANS_SELECT(9);
3452 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3453 "0x%x\n", signal_levels
);
3454 return DDI_BUF_TRANS_SELECT(0);
3458 static void bxt_signal_levels(struct intel_dp
*intel_dp
)
3460 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3461 enum port port
= dport
->port
;
3462 struct drm_device
*dev
= dport
->base
.base
.dev
;
3463 struct intel_encoder
*encoder
= &dport
->base
;
3464 uint8_t train_set
= intel_dp
->train_set
[0];
3467 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3468 DP_TRAIN_PRE_EMPHASIS_MASK
);
3469 switch (signal_levels
) {
3471 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3472 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3475 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3478 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3481 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3484 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3487 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3490 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3493 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3496 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3499 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3504 bxt_ddi_vswing_sequence(dev
, level
, port
, encoder
->type
);
3507 /* Properly updates "DP" with the correct signal levels. */
3509 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3511 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3512 enum port port
= intel_dig_port
->port
;
3513 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3514 uint32_t signal_levels
, mask
;
3515 uint8_t train_set
= intel_dp
->train_set
[0];
3517 if (IS_BROXTON(dev
)) {
3519 bxt_signal_levels(intel_dp
);
3521 } else if (HAS_DDI(dev
)) {
3522 signal_levels
= hsw_signal_levels(train_set
);
3523 mask
= DDI_BUF_EMP_MASK
;
3524 } else if (IS_CHERRYVIEW(dev
)) {
3525 signal_levels
= chv_signal_levels(intel_dp
);
3527 } else if (IS_VALLEYVIEW(dev
)) {
3528 signal_levels
= vlv_signal_levels(intel_dp
);
3530 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3531 signal_levels
= gen7_edp_signal_levels(train_set
);
3532 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3533 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3534 signal_levels
= gen6_edp_signal_levels(train_set
);
3535 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3537 signal_levels
= gen4_signal_levels(train_set
);
3538 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3542 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3544 DRM_DEBUG_KMS("Using vswing level %d\n",
3545 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3546 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3547 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3548 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3550 *DP
= (*DP
& ~mask
) | signal_levels
;
3554 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3556 uint8_t dp_train_pat
)
3558 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3559 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3561 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3564 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3566 I915_WRITE(intel_dp
->output_reg
, *DP
);
3567 POSTING_READ(intel_dp
->output_reg
);
3569 buf
[0] = dp_train_pat
;
3570 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3571 DP_TRAINING_PATTERN_DISABLE
) {
3572 /* don't write DP_TRAINING_LANEx_SET on disable */
3575 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3576 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3577 len
= intel_dp
->lane_count
+ 1;
3580 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3587 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3588 uint8_t dp_train_pat
)
3590 if (!intel_dp
->train_set_valid
)
3591 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3592 intel_dp_set_signal_levels(intel_dp
, DP
);
3593 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3597 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3598 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3600 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3601 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3605 intel_get_adjust_train(intel_dp
, link_status
);
3606 intel_dp_set_signal_levels(intel_dp
, DP
);
3608 I915_WRITE(intel_dp
->output_reg
, *DP
);
3609 POSTING_READ(intel_dp
->output_reg
);
3611 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3612 intel_dp
->train_set
, intel_dp
->lane_count
);
3614 return ret
== intel_dp
->lane_count
;
3617 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3619 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3620 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3622 enum port port
= intel_dig_port
->port
;
3628 val
= I915_READ(DP_TP_CTL(port
));
3629 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3630 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3631 I915_WRITE(DP_TP_CTL(port
), val
);
3634 * On PORT_A we can have only eDP in SST mode. There the only reason
3635 * we need to set idle transmission mode is to work around a HW issue
3636 * where we enable the pipe while not in idle link-training mode.
3637 * In this case there is requirement to wait for a minimum number of
3638 * idle patterns to be sent.
3643 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3645 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3648 /* Enable corresponding port and start training pattern 1 */
3650 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3652 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3653 struct drm_device
*dev
= encoder
->dev
;
3656 int voltage_tries
, loop_tries
;
3657 uint32_t DP
= intel_dp
->DP
;
3658 uint8_t link_config
[2];
3661 intel_ddi_prepare_link_retrain(encoder
);
3663 /* Write the link configuration data */
3664 link_config
[0] = intel_dp
->link_bw
;
3665 link_config
[1] = intel_dp
->lane_count
;
3666 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3667 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3668 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3669 if (intel_dp
->num_sink_rates
)
3670 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_RATE_SET
,
3671 &intel_dp
->rate_select
, 1);
3674 link_config
[1] = DP_SET_ANSI_8B10B
;
3675 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3679 /* clock recovery */
3680 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3681 DP_TRAINING_PATTERN_1
|
3682 DP_LINK_SCRAMBLING_DISABLE
)) {
3683 DRM_ERROR("failed to enable link training\n");
3691 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3693 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3694 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3695 DRM_ERROR("failed to get link status\n");
3699 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3700 DRM_DEBUG_KMS("clock recovery OK\n");
3705 * if we used previously trained voltage and pre-emphasis values
3706 * and we don't get clock recovery, reset link training values
3708 if (intel_dp
->train_set_valid
) {
3709 DRM_DEBUG_KMS("clock recovery not ok, reset");
3710 /* clear the flag as we are not reusing train set */
3711 intel_dp
->train_set_valid
= false;
3712 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3713 DP_TRAINING_PATTERN_1
|
3714 DP_LINK_SCRAMBLING_DISABLE
)) {
3715 DRM_ERROR("failed to enable link training\n");
3721 /* Check to see if we've tried the max voltage */
3722 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3723 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3725 if (i
== intel_dp
->lane_count
) {
3727 if (loop_tries
== 5) {
3728 DRM_ERROR("too many full retries, give up\n");
3731 intel_dp_reset_link_train(intel_dp
, &DP
,
3732 DP_TRAINING_PATTERN_1
|
3733 DP_LINK_SCRAMBLING_DISABLE
);
3738 /* Check to see if we've tried the same voltage 5 times */
3739 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3741 if (voltage_tries
== 5) {
3742 DRM_ERROR("too many voltage retries, give up\n");
3747 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3749 /* Update training set as requested by target */
3750 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3751 DRM_ERROR("failed to update link training\n");
3760 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3762 bool channel_eq
= false;
3763 int tries
, cr_tries
;
3764 uint32_t DP
= intel_dp
->DP
;
3765 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3767 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3768 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3769 training_pattern
= DP_TRAINING_PATTERN_3
;
3771 /* channel equalization */
3772 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3774 DP_LINK_SCRAMBLING_DISABLE
)) {
3775 DRM_ERROR("failed to start channel equalization\n");
3783 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3786 DRM_ERROR("failed to train DP, aborting\n");
3790 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3791 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3792 DRM_ERROR("failed to get link status\n");
3796 /* Make sure clock is still ok */
3797 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3798 intel_dp
->train_set_valid
= false;
3799 intel_dp_start_link_train(intel_dp
);
3800 intel_dp_set_link_train(intel_dp
, &DP
,
3802 DP_LINK_SCRAMBLING_DISABLE
);
3807 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3812 /* Try 5 times, then try clock recovery if that fails */
3814 intel_dp
->train_set_valid
= false;
3815 intel_dp_start_link_train(intel_dp
);
3816 intel_dp_set_link_train(intel_dp
, &DP
,
3818 DP_LINK_SCRAMBLING_DISABLE
);
3824 /* Update training set as requested by target */
3825 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3826 DRM_ERROR("failed to update link training\n");
3832 intel_dp_set_idle_link_train(intel_dp
);
3837 intel_dp
->train_set_valid
= true;
3838 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3842 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3844 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3845 DP_TRAINING_PATTERN_DISABLE
);
3849 intel_dp_link_down(struct intel_dp
*intel_dp
)
3851 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3852 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3853 enum port port
= intel_dig_port
->port
;
3854 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3856 uint32_t DP
= intel_dp
->DP
;
3858 if (WARN_ON(HAS_DDI(dev
)))
3861 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3864 DRM_DEBUG_KMS("\n");
3866 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3867 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3868 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3869 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3871 if (IS_CHERRYVIEW(dev
))
3872 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3874 DP
&= ~DP_LINK_TRAIN_MASK
;
3875 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3877 I915_WRITE(intel_dp
->output_reg
, DP
);
3878 POSTING_READ(intel_dp
->output_reg
);
3880 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3881 I915_WRITE(intel_dp
->output_reg
, DP
);
3882 POSTING_READ(intel_dp
->output_reg
);
3885 * HW workaround for IBX, we need to move the port
3886 * to transcoder A after disabling it to allow the
3887 * matching HDMI port to be enabled on transcoder A.
3889 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3890 /* always enable with pattern 1 (as per spec) */
3891 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3892 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3893 I915_WRITE(intel_dp
->output_reg
, DP
);
3894 POSTING_READ(intel_dp
->output_reg
);
3897 I915_WRITE(intel_dp
->output_reg
, DP
);
3898 POSTING_READ(intel_dp
->output_reg
);
3901 msleep(intel_dp
->panel_power_down_delay
);
3905 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3907 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3908 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3912 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3913 sizeof(intel_dp
->dpcd
)) < 0)
3914 return false; /* aux transfer failed */
3916 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3918 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3919 return false; /* DPCD not present */
3921 /* Check if the panel supports PSR */
3922 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3923 if (is_edp(intel_dp
)) {
3924 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3926 sizeof(intel_dp
->psr_dpcd
));
3927 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3928 dev_priv
->psr
.sink_support
= true;
3929 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3932 if (INTEL_INFO(dev
)->gen
>= 9 &&
3933 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3934 uint8_t frame_sync_cap
;
3936 dev_priv
->psr
.sink_support
= true;
3937 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3938 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3939 &frame_sync_cap
, 1);
3940 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3941 /* PSR2 needs frame sync as well */
3942 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3943 DRM_DEBUG_KMS("PSR2 %s on sink",
3944 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3948 /* Training Pattern 3 support, both source and sink */
3949 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3950 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3951 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3952 intel_dp
->use_tps3
= true;
3953 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3955 intel_dp
->use_tps3
= false;
3957 /* Intermediate frequency support */
3958 if (is_edp(intel_dp
) &&
3959 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3960 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3961 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3962 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3965 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3966 DP_SUPPORTED_LINK_RATES
,
3968 sizeof(sink_rates
));
3970 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3971 int val
= le16_to_cpu(sink_rates
[i
]);
3976 /* Value read is in kHz while drm clock is saved in deca-kHz */
3977 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3979 intel_dp
->num_sink_rates
= i
;
3982 intel_dp_print_rates(intel_dp
);
3984 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3985 DP_DWN_STRM_PORT_PRESENT
))
3986 return true; /* native DP sink */
3988 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3989 return true; /* no per-port downstream info */
3991 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3992 intel_dp
->downstream_ports
,
3993 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3994 return false; /* downstream port status fetch failed */
4000 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
4004 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
4007 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
4008 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
4009 buf
[0], buf
[1], buf
[2]);
4011 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
4012 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
4013 buf
[0], buf
[1], buf
[2]);
4017 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
4021 if (!intel_dp
->can_mst
)
4024 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
4027 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
4028 if (buf
[0] & DP_MST_CAP
) {
4029 DRM_DEBUG_KMS("Sink is MST capable\n");
4030 intel_dp
->is_mst
= true;
4032 DRM_DEBUG_KMS("Sink is not MST capable\n");
4033 intel_dp
->is_mst
= false;
4037 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4038 return intel_dp
->is_mst
;
4041 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
4043 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4044 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4045 struct intel_crtc
*intel_crtc
=
4046 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
4052 hsw_disable_ips(intel_crtc
);
4054 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0) {
4059 if (!(buf
& DP_TEST_CRC_SUPPORTED
)) {
4064 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
4069 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4070 buf
| DP_TEST_SINK_START
) < 0) {
4075 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0) {
4080 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
4083 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4084 DP_TEST_SINK_MISC
, &buf
) < 0) {
4088 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4089 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
4091 if (attempts
== 0) {
4092 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4097 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
4102 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
4106 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4107 buf
& ~DP_TEST_SINK_START
) < 0) {
4112 hsw_enable_ips(intel_crtc
);
4117 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4119 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4120 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4121 sink_irq_vector
, 1) == 1;
4125 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4129 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4131 sink_irq_vector
, 14);
4138 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4140 uint8_t test_result
= DP_TEST_ACK
;
4144 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4146 uint8_t test_result
= DP_TEST_NAK
;
4150 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4152 uint8_t test_result
= DP_TEST_NAK
;
4153 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4154 struct drm_connector
*connector
= &intel_connector
->base
;
4156 if (intel_connector
->detect_edid
== NULL
||
4157 connector
->edid_corrupt
||
4158 intel_dp
->aux
.i2c_defer_count
> 6) {
4159 /* Check EDID read for NACKs, DEFERs and corruption
4160 * (DP CTS 1.2 Core r1.1)
4161 * 4.2.2.4 : Failed EDID read, I2C_NAK
4162 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4163 * 4.2.2.6 : EDID corruption detected
4164 * Use failsafe mode for all cases
4166 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4167 intel_dp
->aux
.i2c_defer_count
> 0)
4168 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4169 intel_dp
->aux
.i2c_nack_count
,
4170 intel_dp
->aux
.i2c_defer_count
);
4171 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
4173 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4174 DP_TEST_EDID_CHECKSUM
,
4175 &intel_connector
->detect_edid
->checksum
,
4177 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4179 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4180 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
4183 /* Set test active flag here so userspace doesn't interrupt things */
4184 intel_dp
->compliance_test_active
= 1;
4189 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4191 uint8_t test_result
= DP_TEST_NAK
;
4195 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4197 uint8_t response
= DP_TEST_NAK
;
4201 intel_dp
->compliance_test_active
= 0;
4202 intel_dp
->compliance_test_type
= 0;
4203 intel_dp
->compliance_test_data
= 0;
4205 intel_dp
->aux
.i2c_nack_count
= 0;
4206 intel_dp
->aux
.i2c_defer_count
= 0;
4208 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4210 DRM_DEBUG_KMS("Could not read test request from sink\n");
4215 case DP_TEST_LINK_TRAINING
:
4216 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4217 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4218 response
= intel_dp_autotest_link_training(intel_dp
);
4220 case DP_TEST_LINK_VIDEO_PATTERN
:
4221 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4222 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4223 response
= intel_dp_autotest_video_pattern(intel_dp
);
4225 case DP_TEST_LINK_EDID_READ
:
4226 DRM_DEBUG_KMS("EDID test requested\n");
4227 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4228 response
= intel_dp_autotest_edid(intel_dp
);
4230 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4231 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4232 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4233 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4236 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4241 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4245 DRM_DEBUG_KMS("Could not write test response to sink\n");
4249 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4253 if (intel_dp
->is_mst
) {
4258 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4262 /* check link status - esi[10] = 0x200c */
4263 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4264 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4265 intel_dp_start_link_train(intel_dp
);
4266 intel_dp_complete_link_train(intel_dp
);
4267 intel_dp_stop_link_train(intel_dp
);
4270 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4271 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4274 for (retry
= 0; retry
< 3; retry
++) {
4276 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4277 DP_SINK_COUNT_ESI
+1,
4284 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4286 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4294 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4295 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4296 intel_dp
->is_mst
= false;
4297 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4298 /* send a hotplug event */
4299 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4306 * According to DP spec
4309 * 2. Configure link according to Receiver Capabilities
4310 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4311 * 4. Check link status on receipt of hot-plug interrupt
4314 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4316 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4317 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4319 u8 link_status
[DP_LINK_STATUS_SIZE
];
4321 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4323 if (!intel_encoder
->connectors_active
)
4326 if (WARN_ON(!intel_encoder
->base
.crtc
))
4329 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4332 /* Try to read receiver status if the link appears to be up */
4333 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4337 /* Now read the DPCD to see if it's actually running */
4338 if (!intel_dp_get_dpcd(intel_dp
)) {
4342 /* Try to read the source of the interrupt */
4343 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4344 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4345 /* Clear interrupt source */
4346 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4347 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4350 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4351 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4352 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4353 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4356 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4357 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4358 intel_encoder
->base
.name
);
4359 intel_dp_start_link_train(intel_dp
);
4360 intel_dp_complete_link_train(intel_dp
);
4361 intel_dp_stop_link_train(intel_dp
);
4365 /* XXX this is probably wrong for multiple downstream ports */
4366 static enum drm_connector_status
4367 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4369 uint8_t *dpcd
= intel_dp
->dpcd
;
4372 if (!intel_dp_get_dpcd(intel_dp
))
4373 return connector_status_disconnected
;
4375 /* if there's no downstream port, we're done */
4376 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4377 return connector_status_connected
;
4379 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4380 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4381 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4384 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4386 return connector_status_unknown
;
4388 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4389 : connector_status_disconnected
;
4392 /* If no HPD, poke DDC gently */
4393 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4394 return connector_status_connected
;
4396 /* Well we tried, say unknown for unreliable port types */
4397 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4398 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4399 if (type
== DP_DS_PORT_TYPE_VGA
||
4400 type
== DP_DS_PORT_TYPE_NON_EDID
)
4401 return connector_status_unknown
;
4403 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4404 DP_DWN_STRM_PORT_TYPE_MASK
;
4405 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4406 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4407 return connector_status_unknown
;
4410 /* Anything else is out of spec, warn and ignore */
4411 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4412 return connector_status_disconnected
;
4415 static enum drm_connector_status
4416 edp_detect(struct intel_dp
*intel_dp
)
4418 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4419 enum drm_connector_status status
;
4421 status
= intel_panel_detect(dev
);
4422 if (status
== connector_status_unknown
)
4423 status
= connector_status_connected
;
4428 static enum drm_connector_status
4429 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4431 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4433 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4435 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4436 return connector_status_disconnected
;
4438 return intel_dp_detect_dpcd(intel_dp
);
4441 static int g4x_digital_port_connected(struct drm_device
*dev
,
4442 struct intel_digital_port
*intel_dig_port
)
4444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4447 if (IS_VALLEYVIEW(dev
)) {
4448 switch (intel_dig_port
->port
) {
4450 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4453 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4456 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4462 switch (intel_dig_port
->port
) {
4464 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4467 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4470 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4477 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4482 static enum drm_connector_status
4483 g4x_dp_detect(struct intel_dp
*intel_dp
)
4485 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4486 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4489 /* Can't disconnect eDP, but you can close the lid... */
4490 if (is_edp(intel_dp
)) {
4491 enum drm_connector_status status
;
4493 status
= intel_panel_detect(dev
);
4494 if (status
== connector_status_unknown
)
4495 status
= connector_status_connected
;
4499 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4501 return connector_status_unknown
;
4503 return connector_status_disconnected
;
4505 return intel_dp_detect_dpcd(intel_dp
);
4508 static struct edid
*
4509 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4511 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4513 /* use cached edid if we have one */
4514 if (intel_connector
->edid
) {
4516 if (IS_ERR(intel_connector
->edid
))
4519 return drm_edid_duplicate(intel_connector
->edid
);
4521 return drm_get_edid(&intel_connector
->base
,
4522 &intel_dp
->aux
.ddc
);
4526 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4528 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4531 edid
= intel_dp_get_edid(intel_dp
);
4532 intel_connector
->detect_edid
= edid
;
4534 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4535 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4537 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4541 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4543 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4545 kfree(intel_connector
->detect_edid
);
4546 intel_connector
->detect_edid
= NULL
;
4548 intel_dp
->has_audio
= false;
4551 static enum intel_display_power_domain
4552 intel_dp_power_get(struct intel_dp
*dp
)
4554 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4555 enum intel_display_power_domain power_domain
;
4557 power_domain
= intel_display_port_power_domain(encoder
);
4558 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4560 return power_domain
;
4564 intel_dp_power_put(struct intel_dp
*dp
,
4565 enum intel_display_power_domain power_domain
)
4567 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4568 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4571 static enum drm_connector_status
4572 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4574 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4575 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4576 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4577 struct drm_device
*dev
= connector
->dev
;
4578 enum drm_connector_status status
;
4579 enum intel_display_power_domain power_domain
;
4583 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4584 connector
->base
.id
, connector
->name
);
4585 intel_dp_unset_edid(intel_dp
);
4587 if (intel_dp
->is_mst
) {
4588 /* MST devices are disconnected from a monitor POV */
4589 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4590 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4591 return connector_status_disconnected
;
4594 power_domain
= intel_dp_power_get(intel_dp
);
4596 /* Can't disconnect eDP, but you can close the lid... */
4597 if (is_edp(intel_dp
))
4598 status
= edp_detect(intel_dp
);
4599 else if (HAS_PCH_SPLIT(dev
))
4600 status
= ironlake_dp_detect(intel_dp
);
4602 status
= g4x_dp_detect(intel_dp
);
4603 if (status
!= connector_status_connected
)
4606 intel_dp_probe_oui(intel_dp
);
4608 ret
= intel_dp_probe_mst(intel_dp
);
4610 /* if we are in MST mode then this connector
4611 won't appear connected or have anything with EDID on it */
4612 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4613 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4614 status
= connector_status_disconnected
;
4618 intel_dp_set_edid(intel_dp
);
4620 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4621 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4622 status
= connector_status_connected
;
4624 /* Try to read the source of the interrupt */
4625 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4626 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4627 /* Clear interrupt source */
4628 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4629 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4632 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4633 intel_dp_handle_test_request(intel_dp
);
4634 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4635 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4639 intel_dp_power_put(intel_dp
, power_domain
);
4644 intel_dp_force(struct drm_connector
*connector
)
4646 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4647 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4648 enum intel_display_power_domain power_domain
;
4650 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4651 connector
->base
.id
, connector
->name
);
4652 intel_dp_unset_edid(intel_dp
);
4654 if (connector
->status
!= connector_status_connected
)
4657 power_domain
= intel_dp_power_get(intel_dp
);
4659 intel_dp_set_edid(intel_dp
);
4661 intel_dp_power_put(intel_dp
, power_domain
);
4663 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4664 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4667 static int intel_dp_get_modes(struct drm_connector
*connector
)
4669 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4672 edid
= intel_connector
->detect_edid
;
4674 int ret
= intel_connector_update_modes(connector
, edid
);
4679 /* if eDP has no EDID, fall back to fixed mode */
4680 if (is_edp(intel_attached_dp(connector
)) &&
4681 intel_connector
->panel
.fixed_mode
) {
4682 struct drm_display_mode
*mode
;
4684 mode
= drm_mode_duplicate(connector
->dev
,
4685 intel_connector
->panel
.fixed_mode
);
4687 drm_mode_probed_add(connector
, mode
);
4696 intel_dp_detect_audio(struct drm_connector
*connector
)
4698 bool has_audio
= false;
4701 edid
= to_intel_connector(connector
)->detect_edid
;
4703 has_audio
= drm_detect_monitor_audio(edid
);
4709 intel_dp_set_property(struct drm_connector
*connector
,
4710 struct drm_property
*property
,
4713 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4714 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4715 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4716 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4719 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4723 if (property
== dev_priv
->force_audio_property
) {
4727 if (i
== intel_dp
->force_audio
)
4730 intel_dp
->force_audio
= i
;
4732 if (i
== HDMI_AUDIO_AUTO
)
4733 has_audio
= intel_dp_detect_audio(connector
);
4735 has_audio
= (i
== HDMI_AUDIO_ON
);
4737 if (has_audio
== intel_dp
->has_audio
)
4740 intel_dp
->has_audio
= has_audio
;
4744 if (property
== dev_priv
->broadcast_rgb_property
) {
4745 bool old_auto
= intel_dp
->color_range_auto
;
4746 uint32_t old_range
= intel_dp
->color_range
;
4749 case INTEL_BROADCAST_RGB_AUTO
:
4750 intel_dp
->color_range_auto
= true;
4752 case INTEL_BROADCAST_RGB_FULL
:
4753 intel_dp
->color_range_auto
= false;
4754 intel_dp
->color_range
= 0;
4756 case INTEL_BROADCAST_RGB_LIMITED
:
4757 intel_dp
->color_range_auto
= false;
4758 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4764 if (old_auto
== intel_dp
->color_range_auto
&&
4765 old_range
== intel_dp
->color_range
)
4771 if (is_edp(intel_dp
) &&
4772 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4773 if (val
== DRM_MODE_SCALE_NONE
) {
4774 DRM_DEBUG_KMS("no scaling not supported\n");
4778 if (intel_connector
->panel
.fitting_mode
== val
) {
4779 /* the eDP scaling property is not changed */
4782 intel_connector
->panel
.fitting_mode
= val
;
4790 if (intel_encoder
->base
.crtc
)
4791 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4797 intel_dp_connector_destroy(struct drm_connector
*connector
)
4799 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4801 kfree(intel_connector
->detect_edid
);
4803 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4804 kfree(intel_connector
->edid
);
4806 /* Can't call is_edp() since the encoder may have been destroyed
4808 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4809 intel_panel_fini(&intel_connector
->panel
);
4811 drm_connector_cleanup(connector
);
4815 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4817 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4818 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4820 drm_dp_aux_unregister(&intel_dp
->aux
);
4821 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4822 if (is_edp(intel_dp
)) {
4823 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4825 * vdd might still be enabled do to the delayed vdd off.
4826 * Make sure vdd is actually turned off here.
4829 edp_panel_vdd_off_sync(intel_dp
);
4830 pps_unlock(intel_dp
);
4832 if (intel_dp
->edp_notifier
.notifier_call
) {
4833 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4834 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4837 drm_encoder_cleanup(encoder
);
4838 kfree(intel_dig_port
);
4841 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4843 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4845 if (!is_edp(intel_dp
))
4849 * vdd might still be enabled do to the delayed vdd off.
4850 * Make sure vdd is actually turned off here.
4852 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4854 edp_panel_vdd_off_sync(intel_dp
);
4855 pps_unlock(intel_dp
);
4858 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4860 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4861 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4863 enum intel_display_power_domain power_domain
;
4865 lockdep_assert_held(&dev_priv
->pps_mutex
);
4867 if (!edp_have_panel_vdd(intel_dp
))
4871 * The VDD bit needs a power domain reference, so if the bit is
4872 * already enabled when we boot or resume, grab this reference and
4873 * schedule a vdd off, so we don't hold on to the reference
4876 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4877 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4878 intel_display_power_get(dev_priv
, power_domain
);
4880 edp_panel_vdd_schedule_off(intel_dp
);
4883 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4885 struct intel_dp
*intel_dp
;
4887 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4890 intel_dp
= enc_to_intel_dp(encoder
);
4895 * Read out the current power sequencer assignment,
4896 * in case the BIOS did something with it.
4898 if (IS_VALLEYVIEW(encoder
->dev
))
4899 vlv_initial_power_sequencer_setup(intel_dp
);
4901 intel_edp_panel_vdd_sanitize(intel_dp
);
4903 pps_unlock(intel_dp
);
4906 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4907 .dpms
= intel_connector_dpms
,
4908 .detect
= intel_dp_detect
,
4909 .force
= intel_dp_force
,
4910 .fill_modes
= drm_helper_probe_single_connector_modes
,
4911 .set_property
= intel_dp_set_property
,
4912 .atomic_get_property
= intel_connector_atomic_get_property
,
4913 .destroy
= intel_dp_connector_destroy
,
4914 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4915 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4918 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4919 .get_modes
= intel_dp_get_modes
,
4920 .mode_valid
= intel_dp_mode_valid
,
4921 .best_encoder
= intel_best_encoder
,
4924 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4925 .reset
= intel_dp_encoder_reset
,
4926 .destroy
= intel_dp_encoder_destroy
,
4930 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4932 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4933 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4934 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4936 enum intel_display_power_domain power_domain
;
4937 enum irqreturn ret
= IRQ_NONE
;
4939 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4940 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4942 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4944 * vdd off can generate a long pulse on eDP which
4945 * would require vdd on to handle it, and thus we
4946 * would end up in an endless cycle of
4947 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4949 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4950 port_name(intel_dig_port
->port
));
4954 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4955 port_name(intel_dig_port
->port
),
4956 long_hpd
? "long" : "short");
4958 power_domain
= intel_display_port_power_domain(intel_encoder
);
4959 intel_display_power_get(dev_priv
, power_domain
);
4962 /* indicate that we need to restart link training */
4963 intel_dp
->train_set_valid
= false;
4965 if (HAS_PCH_SPLIT(dev
)) {
4966 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4969 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4973 if (!intel_dp_get_dpcd(intel_dp
)) {
4977 intel_dp_probe_oui(intel_dp
);
4979 if (!intel_dp_probe_mst(intel_dp
))
4983 if (intel_dp
->is_mst
) {
4984 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4988 if (!intel_dp
->is_mst
) {
4990 * we'll check the link status via the normal hot plug path later -
4991 * but for short hpds we should check it now
4993 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4994 intel_dp_check_link_status(intel_dp
);
4995 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
5003 /* if we were in MST mode, and device is not there get out of MST mode */
5004 if (intel_dp
->is_mst
) {
5005 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
5006 intel_dp
->is_mst
= false;
5007 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
5010 intel_display_power_put(dev_priv
, power_domain
);
5015 /* Return which DP Port should be selected for Transcoder DP control */
5017 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
5019 struct drm_device
*dev
= crtc
->dev
;
5020 struct intel_encoder
*intel_encoder
;
5021 struct intel_dp
*intel_dp
;
5023 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5024 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5026 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
5027 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
5028 return intel_dp
->output_reg
;
5034 /* check the VBT to see whether the eDP is on DP-D port */
5035 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
5037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5038 union child_device_config
*p_child
;
5040 static const short port_mapping
[] = {
5041 [PORT_B
] = PORT_IDPB
,
5042 [PORT_C
] = PORT_IDPC
,
5043 [PORT_D
] = PORT_IDPD
,
5049 if (!dev_priv
->vbt
.child_dev_num
)
5052 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
5053 p_child
= dev_priv
->vbt
.child_dev
+ i
;
5055 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
5056 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
5057 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
5064 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5066 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5068 intel_attach_force_audio_property(connector
);
5069 intel_attach_broadcast_rgb_property(connector
);
5070 intel_dp
->color_range_auto
= true;
5072 if (is_edp(intel_dp
)) {
5073 drm_mode_create_scaling_mode_property(connector
->dev
);
5074 drm_object_attach_property(
5076 connector
->dev
->mode_config
.scaling_mode_property
,
5077 DRM_MODE_SCALE_ASPECT
);
5078 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5082 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5084 intel_dp
->last_power_cycle
= jiffies
;
5085 intel_dp
->last_power_on
= jiffies
;
5086 intel_dp
->last_backlight_off
= jiffies
;
5090 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5091 struct intel_dp
*intel_dp
)
5093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5094 struct edp_power_seq cur
, vbt
, spec
,
5095 *final
= &intel_dp
->pps_delays
;
5096 u32 pp_on
, pp_off
, pp_div
, pp
;
5097 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
5099 lockdep_assert_held(&dev_priv
->pps_mutex
);
5101 /* already initialized? */
5102 if (final
->t11_t12
!= 0)
5105 if (HAS_PCH_SPLIT(dev
)) {
5106 pp_ctrl_reg
= PCH_PP_CONTROL
;
5107 pp_on_reg
= PCH_PP_ON_DELAYS
;
5108 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5109 pp_div_reg
= PCH_PP_DIVISOR
;
5111 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5113 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
5114 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5115 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5116 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5119 /* Workaround: Need to write PP_CONTROL with the unlock key as
5120 * the very first thing. */
5121 pp
= ironlake_get_pp_control(intel_dp
);
5122 I915_WRITE(pp_ctrl_reg
, pp
);
5124 pp_on
= I915_READ(pp_on_reg
);
5125 pp_off
= I915_READ(pp_off_reg
);
5126 pp_div
= I915_READ(pp_div_reg
);
5128 /* Pull timing values out of registers */
5129 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5130 PANEL_POWER_UP_DELAY_SHIFT
;
5132 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5133 PANEL_LIGHT_ON_DELAY_SHIFT
;
5135 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5136 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5138 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5139 PANEL_POWER_DOWN_DELAY_SHIFT
;
5141 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5142 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5144 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5145 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5147 vbt
= dev_priv
->vbt
.edp_pps
;
5149 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5150 * our hw here, which are all in 100usec. */
5151 spec
.t1_t3
= 210 * 10;
5152 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5153 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5154 spec
.t10
= 500 * 10;
5155 /* This one is special and actually in units of 100ms, but zero
5156 * based in the hw (so we need to add 100 ms). But the sw vbt
5157 * table multiplies it with 1000 to make it in units of 100usec,
5159 spec
.t11_t12
= (510 + 100) * 10;
5161 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5162 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5164 /* Use the max of the register settings and vbt. If both are
5165 * unset, fall back to the spec limits. */
5166 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5168 max(cur.field, vbt.field))
5169 assign_final(t1_t3
);
5173 assign_final(t11_t12
);
5176 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5177 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5178 intel_dp
->backlight_on_delay
= get_delay(t8
);
5179 intel_dp
->backlight_off_delay
= get_delay(t9
);
5180 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5181 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5184 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5185 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5186 intel_dp
->panel_power_cycle_delay
);
5188 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5189 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5193 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5194 struct intel_dp
*intel_dp
)
5196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5197 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5198 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5199 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
5200 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5201 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5203 lockdep_assert_held(&dev_priv
->pps_mutex
);
5205 if (HAS_PCH_SPLIT(dev
)) {
5206 pp_on_reg
= PCH_PP_ON_DELAYS
;
5207 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5208 pp_div_reg
= PCH_PP_DIVISOR
;
5210 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5212 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5213 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5214 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5218 * And finally store the new values in the power sequencer. The
5219 * backlight delays are set to 1 because we do manual waits on them. For
5220 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5221 * we'll end up waiting for the backlight off delay twice: once when we
5222 * do the manual sleep, and once when we disable the panel and wait for
5223 * the PP_STATUS bit to become zero.
5225 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5226 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5227 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5228 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5229 /* Compute the divisor for the pp clock, simply match the Bspec
5231 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5232 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5233 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5235 /* Haswell doesn't have any port selection bits for the panel
5236 * power sequencer any more. */
5237 if (IS_VALLEYVIEW(dev
)) {
5238 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5239 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5241 port_sel
= PANEL_PORT_SELECT_DPA
;
5243 port_sel
= PANEL_PORT_SELECT_DPD
;
5248 I915_WRITE(pp_on_reg
, pp_on
);
5249 I915_WRITE(pp_off_reg
, pp_off
);
5250 I915_WRITE(pp_div_reg
, pp_div
);
5252 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5253 I915_READ(pp_on_reg
),
5254 I915_READ(pp_off_reg
),
5255 I915_READ(pp_div_reg
));
5259 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5261 * @refresh_rate: RR to be programmed
5263 * This function gets called when refresh rate (RR) has to be changed from
5264 * one frequency to another. Switches can be between high and low RR
5265 * supported by the panel or to any other RR based on media playback (in
5266 * this case, RR value needs to be passed from user space).
5268 * The caller of this function needs to take a lock on dev_priv->drrs.
5270 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5273 struct intel_encoder
*encoder
;
5274 struct intel_digital_port
*dig_port
= NULL
;
5275 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5276 struct intel_crtc_state
*config
= NULL
;
5277 struct intel_crtc
*intel_crtc
= NULL
;
5279 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5281 if (refresh_rate
<= 0) {
5282 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5286 if (intel_dp
== NULL
) {
5287 DRM_DEBUG_KMS("DRRS not supported.\n");
5292 * FIXME: This needs proper synchronization with psr state for some
5293 * platforms that cannot have PSR and DRRS enabled at the same time.
5296 dig_port
= dp_to_dig_port(intel_dp
);
5297 encoder
= &dig_port
->base
;
5298 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5301 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5305 config
= intel_crtc
->config
;
5307 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5308 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5312 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5314 index
= DRRS_LOW_RR
;
5316 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5318 "DRRS requested for previously set RR...ignoring\n");
5322 if (!intel_crtc
->active
) {
5323 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5327 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5330 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5333 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5337 DRM_ERROR("Unsupported refreshrate type\n");
5339 } else if (INTEL_INFO(dev
)->gen
> 6) {
5340 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5341 val
= I915_READ(reg
);
5343 if (index
> DRRS_HIGH_RR
) {
5344 if (IS_VALLEYVIEW(dev
))
5345 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5347 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5349 if (IS_VALLEYVIEW(dev
))
5350 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5352 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5354 I915_WRITE(reg
, val
);
5357 dev_priv
->drrs
.refresh_rate_type
= index
;
5359 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5363 * intel_edp_drrs_enable - init drrs struct if supported
5364 * @intel_dp: DP struct
5366 * Initializes frontbuffer_bits and drrs.dp
5368 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5370 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5372 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5373 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5374 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5376 if (!intel_crtc
->config
->has_drrs
) {
5377 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5381 mutex_lock(&dev_priv
->drrs
.mutex
);
5382 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5383 DRM_ERROR("DRRS already enabled\n");
5387 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5389 dev_priv
->drrs
.dp
= intel_dp
;
5392 mutex_unlock(&dev_priv
->drrs
.mutex
);
5396 * intel_edp_drrs_disable - Disable DRRS
5397 * @intel_dp: DP struct
5400 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5402 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5404 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5405 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5406 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5408 if (!intel_crtc
->config
->has_drrs
)
5411 mutex_lock(&dev_priv
->drrs
.mutex
);
5412 if (!dev_priv
->drrs
.dp
) {
5413 mutex_unlock(&dev_priv
->drrs
.mutex
);
5417 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5418 intel_dp_set_drrs_state(dev_priv
->dev
,
5419 intel_dp
->attached_connector
->panel
.
5420 fixed_mode
->vrefresh
);
5422 dev_priv
->drrs
.dp
= NULL
;
5423 mutex_unlock(&dev_priv
->drrs
.mutex
);
5425 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5428 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5430 struct drm_i915_private
*dev_priv
=
5431 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5432 struct intel_dp
*intel_dp
;
5434 mutex_lock(&dev_priv
->drrs
.mutex
);
5436 intel_dp
= dev_priv
->drrs
.dp
;
5442 * The delayed work can race with an invalidate hence we need to
5446 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5449 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5450 intel_dp_set_drrs_state(dev_priv
->dev
,
5451 intel_dp
->attached_connector
->panel
.
5452 downclock_mode
->vrefresh
);
5455 mutex_unlock(&dev_priv
->drrs
.mutex
);
5459 * intel_edp_drrs_invalidate - Invalidate DRRS
5461 * @frontbuffer_bits: frontbuffer plane tracking bits
5463 * When there is a disturbance on screen (due to cursor movement/time
5464 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5467 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5469 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5470 unsigned frontbuffer_bits
)
5472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5473 struct drm_crtc
*crtc
;
5476 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5479 cancel_delayed_work(&dev_priv
->drrs
.work
);
5481 mutex_lock(&dev_priv
->drrs
.mutex
);
5482 if (!dev_priv
->drrs
.dp
) {
5483 mutex_unlock(&dev_priv
->drrs
.mutex
);
5487 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5488 pipe
= to_intel_crtc(crtc
)->pipe
;
5490 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
) {
5491 intel_dp_set_drrs_state(dev_priv
->dev
,
5492 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5493 fixed_mode
->vrefresh
);
5496 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5498 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5499 mutex_unlock(&dev_priv
->drrs
.mutex
);
5503 * intel_edp_drrs_flush - Flush DRRS
5505 * @frontbuffer_bits: frontbuffer plane tracking bits
5507 * When there is no movement on screen, DRRS work can be scheduled.
5508 * This DRRS work is responsible for setting relevant registers after a
5509 * timeout of 1 second.
5511 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5513 void intel_edp_drrs_flush(struct drm_device
*dev
,
5514 unsigned frontbuffer_bits
)
5516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5517 struct drm_crtc
*crtc
;
5520 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5523 cancel_delayed_work(&dev_priv
->drrs
.work
);
5525 mutex_lock(&dev_priv
->drrs
.mutex
);
5526 if (!dev_priv
->drrs
.dp
) {
5527 mutex_unlock(&dev_priv
->drrs
.mutex
);
5531 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5532 pipe
= to_intel_crtc(crtc
)->pipe
;
5533 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5535 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
&&
5536 !dev_priv
->drrs
.busy_frontbuffer_bits
)
5537 schedule_delayed_work(&dev_priv
->drrs
.work
,
5538 msecs_to_jiffies(1000));
5539 mutex_unlock(&dev_priv
->drrs
.mutex
);
5543 * DOC: Display Refresh Rate Switching (DRRS)
5545 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5546 * which enables swtching between low and high refresh rates,
5547 * dynamically, based on the usage scenario. This feature is applicable
5548 * for internal panels.
5550 * Indication that the panel supports DRRS is given by the panel EDID, which
5551 * would list multiple refresh rates for one resolution.
5553 * DRRS is of 2 types - static and seamless.
5554 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5555 * (may appear as a blink on screen) and is used in dock-undock scenario.
5556 * Seamless DRRS involves changing RR without any visual effect to the user
5557 * and can be used during normal system usage. This is done by programming
5558 * certain registers.
5560 * Support for static/seamless DRRS may be indicated in the VBT based on
5561 * inputs from the panel spec.
5563 * DRRS saves power by switching to low RR based on usage scenarios.
5566 * The implementation is based on frontbuffer tracking implementation.
5567 * When there is a disturbance on the screen triggered by user activity or a
5568 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5569 * When there is no movement on screen, after a timeout of 1 second, a switch
5570 * to low RR is made.
5571 * For integration with frontbuffer tracking code,
5572 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5574 * DRRS can be further extended to support other internal panels and also
5575 * the scenario of video playback wherein RR is set based on the rate
5576 * requested by userspace.
5580 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5581 * @intel_connector: eDP connector
5582 * @fixed_mode: preferred mode of panel
5584 * This function is called only once at driver load to initialize basic
5588 * Downclock mode if panel supports it, else return NULL.
5589 * DRRS support is determined by the presence of downclock mode (apart
5590 * from VBT setting).
5592 static struct drm_display_mode
*
5593 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5594 struct drm_display_mode
*fixed_mode
)
5596 struct drm_connector
*connector
= &intel_connector
->base
;
5597 struct drm_device
*dev
= connector
->dev
;
5598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5599 struct drm_display_mode
*downclock_mode
= NULL
;
5601 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5602 mutex_init(&dev_priv
->drrs
.mutex
);
5604 if (INTEL_INFO(dev
)->gen
<= 6) {
5605 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5609 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5610 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5614 downclock_mode
= intel_find_panel_downclock
5615 (dev
, fixed_mode
, connector
);
5617 if (!downclock_mode
) {
5618 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5622 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5624 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5625 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5626 return downclock_mode
;
5629 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5630 struct intel_connector
*intel_connector
)
5632 struct drm_connector
*connector
= &intel_connector
->base
;
5633 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5634 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5635 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5637 struct drm_display_mode
*fixed_mode
= NULL
;
5638 struct drm_display_mode
*downclock_mode
= NULL
;
5640 struct drm_display_mode
*scan
;
5642 enum pipe pipe
= INVALID_PIPE
;
5644 if (!is_edp(intel_dp
))
5648 intel_edp_panel_vdd_sanitize(intel_dp
);
5649 pps_unlock(intel_dp
);
5651 /* Cache DPCD and EDID for edp. */
5652 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5655 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5656 dev_priv
->no_aux_handshake
=
5657 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5658 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5660 /* if this fails, presume the device is a ghost */
5661 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5665 /* We now know it's not a ghost, init power sequence regs. */
5667 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5668 pps_unlock(intel_dp
);
5670 mutex_lock(&dev
->mode_config
.mutex
);
5671 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5673 if (drm_add_edid_modes(connector
, edid
)) {
5674 drm_mode_connector_update_edid_property(connector
,
5676 drm_edid_to_eld(connector
, edid
);
5679 edid
= ERR_PTR(-EINVAL
);
5682 edid
= ERR_PTR(-ENOENT
);
5684 intel_connector
->edid
= edid
;
5686 /* prefer fixed mode from EDID if available */
5687 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5688 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5689 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5690 downclock_mode
= intel_dp_drrs_init(
5691 intel_connector
, fixed_mode
);
5696 /* fallback to VBT if available for eDP */
5697 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5698 fixed_mode
= drm_mode_duplicate(dev
,
5699 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5701 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5703 mutex_unlock(&dev
->mode_config
.mutex
);
5705 if (IS_VALLEYVIEW(dev
)) {
5706 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5707 register_reboot_notifier(&intel_dp
->edp_notifier
);
5710 * Figure out the current pipe for the initial backlight setup.
5711 * If the current pipe isn't valid, try the PPS pipe, and if that
5712 * fails just assume pipe A.
5714 if (IS_CHERRYVIEW(dev
))
5715 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5717 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5719 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5720 pipe
= intel_dp
->pps_pipe
;
5722 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5725 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5729 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5730 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5731 intel_panel_setup_backlight(connector
, pipe
);
5737 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5738 struct intel_connector
*intel_connector
)
5740 struct drm_connector
*connector
= &intel_connector
->base
;
5741 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5742 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5743 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5745 enum port port
= intel_dig_port
->port
;
5748 intel_dp
->pps_pipe
= INVALID_PIPE
;
5750 /* intel_dp vfuncs */
5751 if (INTEL_INFO(dev
)->gen
>= 9)
5752 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5753 else if (IS_VALLEYVIEW(dev
))
5754 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5755 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5756 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5757 else if (HAS_PCH_SPLIT(dev
))
5758 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5760 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5762 if (INTEL_INFO(dev
)->gen
>= 9)
5763 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5765 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5767 /* Preserve the current hw state. */
5768 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5769 intel_dp
->attached_connector
= intel_connector
;
5771 if (intel_dp_is_edp(dev
, port
))
5772 type
= DRM_MODE_CONNECTOR_eDP
;
5774 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5777 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5778 * for DP the encoder type can be set by the caller to
5779 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5781 if (type
== DRM_MODE_CONNECTOR_eDP
)
5782 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5784 /* eDP only on port B and/or C on vlv/chv */
5785 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5786 port
!= PORT_B
&& port
!= PORT_C
))
5789 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5790 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5793 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5794 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5796 connector
->interlace_allowed
= true;
5797 connector
->doublescan_allowed
= 0;
5799 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5800 edp_panel_vdd_work
);
5802 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5803 drm_connector_register(connector
);
5806 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5808 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5809 intel_connector
->unregister
= intel_dp_connector_unregister
;
5811 /* Set up the hotplug pin. */
5814 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5817 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5820 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5823 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5829 if (is_edp(intel_dp
)) {
5831 intel_dp_init_panel_power_timestamps(intel_dp
);
5832 if (IS_VALLEYVIEW(dev
))
5833 vlv_initial_power_sequencer_setup(intel_dp
);
5835 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5836 pps_unlock(intel_dp
);
5839 intel_dp_aux_init(intel_dp
, intel_connector
);
5841 /* init MST on ports that can support it */
5842 if (HAS_DP_MST(dev
) &&
5843 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5844 intel_dp_mst_encoder_init(intel_dig_port
,
5845 intel_connector
->base
.base
.id
);
5847 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5848 drm_dp_aux_unregister(&intel_dp
->aux
);
5849 if (is_edp(intel_dp
)) {
5850 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5852 * vdd might still be enabled do to the delayed vdd off.
5853 * Make sure vdd is actually turned off here.
5856 edp_panel_vdd_off_sync(intel_dp
);
5857 pps_unlock(intel_dp
);
5859 drm_connector_unregister(connector
);
5860 drm_connector_cleanup(connector
);
5864 intel_dp_add_properties(intel_dp
, connector
);
5866 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5867 * 0xd. Failure to do so will result in spurious interrupts being
5868 * generated on the port when a cable is not attached.
5870 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5871 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5872 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5875 i915_debugfs_connector_add(connector
);
5881 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5884 struct intel_digital_port
*intel_dig_port
;
5885 struct intel_encoder
*intel_encoder
;
5886 struct drm_encoder
*encoder
;
5887 struct intel_connector
*intel_connector
;
5889 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5890 if (!intel_dig_port
)
5893 intel_connector
= intel_connector_alloc();
5894 if (!intel_connector
) {
5895 kfree(intel_dig_port
);
5899 intel_encoder
= &intel_dig_port
->base
;
5900 encoder
= &intel_encoder
->base
;
5902 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5903 DRM_MODE_ENCODER_TMDS
);
5905 intel_encoder
->compute_config
= intel_dp_compute_config
;
5906 intel_encoder
->disable
= intel_disable_dp
;
5907 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5908 intel_encoder
->get_config
= intel_dp_get_config
;
5909 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5910 if (IS_CHERRYVIEW(dev
)) {
5911 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5912 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5913 intel_encoder
->enable
= vlv_enable_dp
;
5914 intel_encoder
->post_disable
= chv_post_disable_dp
;
5915 } else if (IS_VALLEYVIEW(dev
)) {
5916 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5917 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5918 intel_encoder
->enable
= vlv_enable_dp
;
5919 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5921 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5922 intel_encoder
->enable
= g4x_enable_dp
;
5923 if (INTEL_INFO(dev
)->gen
>= 5)
5924 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5927 intel_dig_port
->port
= port
;
5928 intel_dig_port
->dp
.output_reg
= output_reg
;
5930 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5931 if (IS_CHERRYVIEW(dev
)) {
5933 intel_encoder
->crtc_mask
= 1 << 2;
5935 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5937 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5939 intel_encoder
->cloneable
= 0;
5941 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5942 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5944 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5945 drm_encoder_cleanup(encoder
);
5946 kfree(intel_dig_port
);
5947 kfree(intel_connector
);
5951 void intel_dp_mst_suspend(struct drm_device
*dev
)
5953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5957 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5958 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5959 if (!intel_dig_port
)
5962 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5963 if (!intel_dig_port
->dp
.can_mst
)
5965 if (intel_dig_port
->dp
.is_mst
)
5966 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5971 void intel_dp_mst_resume(struct drm_device
*dev
)
5973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5976 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5977 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5978 if (!intel_dig_port
)
5980 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5983 if (!intel_dig_port
->dp
.can_mst
)
5986 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5988 intel_dp_check_mst_status(&intel_dig_port
->dp
);