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drm/i915: use TU_SIZE macro at intel_dp_set_m_n
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "drm_crtc_helper.h"
35 #include "drm_edid.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44 /**
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
47 *
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
50 */
51 static bool is_edp(struct intel_dp *intel_dp)
52 {
53 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54 }
55
56 /**
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
59 *
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
63 */
64 static bool is_pch_edp(struct intel_dp *intel_dp)
65 {
66 return intel_dp->is_pch_edp;
67 }
68
69 /**
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
72 *
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 */
75 static bool is_cpu_edp(struct intel_dp *intel_dp)
76 {
77 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78 }
79
80 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
81 {
82 return container_of(intel_attached_encoder(connector),
83 struct intel_dp, base);
84 }
85
86 /**
87 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
88 * @encoder: DRM encoder
89 *
90 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
91 * by intel_display.c.
92 */
93 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
94 {
95 struct intel_dp *intel_dp;
96
97 if (!encoder)
98 return false;
99
100 intel_dp = enc_to_intel_dp(encoder);
101
102 return is_pch_edp(intel_dp);
103 }
104
105 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
106 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
107 static void intel_dp_link_down(struct intel_dp *intel_dp);
108
109 void
110 intel_edp_link_config(struct intel_encoder *intel_encoder,
111 int *lane_num, int *link_bw)
112 {
113 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
114
115 *lane_num = intel_dp->lane_count;
116 if (intel_dp->link_bw == DP_LINK_BW_1_62)
117 *link_bw = 162000;
118 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
119 *link_bw = 270000;
120 }
121
122 int
123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125 {
126 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
127
128 if (intel_dp->panel_fixed_mode)
129 return intel_dp->panel_fixed_mode->clock;
130 else
131 return mode->clock;
132 }
133
134 static int
135 intel_dp_max_lane_count(struct intel_dp *intel_dp)
136 {
137 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
138 switch (max_lane_count) {
139 case 1: case 2: case 4:
140 break;
141 default:
142 max_lane_count = 4;
143 }
144 return max_lane_count;
145 }
146
147 static int
148 intel_dp_max_link_bw(struct intel_dp *intel_dp)
149 {
150 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
151
152 switch (max_link_bw) {
153 case DP_LINK_BW_1_62:
154 case DP_LINK_BW_2_7:
155 break;
156 default:
157 max_link_bw = DP_LINK_BW_1_62;
158 break;
159 }
160 return max_link_bw;
161 }
162
163 static int
164 intel_dp_link_clock(uint8_t link_bw)
165 {
166 if (link_bw == DP_LINK_BW_2_7)
167 return 270000;
168 else
169 return 162000;
170 }
171
172 /*
173 * The units on the numbers in the next two are... bizarre. Examples will
174 * make it clearer; this one parallels an example in the eDP spec.
175 *
176 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 *
178 * 270000 * 1 * 8 / 10 == 216000
179 *
180 * The actual data capacity of that configuration is 2.16Gbit/s, so the
181 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
182 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
183 * 119000. At 18bpp that's 2142000 kilobits per second.
184 *
185 * Thus the strange-looking division by 10 in intel_dp_link_required, to
186 * get the result in decakilobits instead of kilobits.
187 */
188
189 static int
190 intel_dp_link_required(int pixel_clock, int bpp)
191 {
192 return (pixel_clock * bpp + 9) / 10;
193 }
194
195 static int
196 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
197 {
198 return (max_link_clock * max_lanes * 8) / 10;
199 }
200
201 static bool
202 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
203 struct drm_display_mode *mode,
204 bool adjust_mode)
205 {
206 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
207 int max_lanes = intel_dp_max_lane_count(intel_dp);
208 int max_rate, mode_rate;
209
210 mode_rate = intel_dp_link_required(mode->clock, 24);
211 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
212
213 if (mode_rate > max_rate) {
214 mode_rate = intel_dp_link_required(mode->clock, 18);
215 if (mode_rate > max_rate)
216 return false;
217
218 if (adjust_mode)
219 mode->private_flags
220 |= INTEL_MODE_DP_FORCE_6BPC;
221
222 return true;
223 }
224
225 return true;
226 }
227
228 static int
229 intel_dp_mode_valid(struct drm_connector *connector,
230 struct drm_display_mode *mode)
231 {
232 struct intel_dp *intel_dp = intel_attached_dp(connector);
233
234 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
235 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
236 return MODE_PANEL;
237
238 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
239 return MODE_PANEL;
240 }
241
242 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
243 return MODE_CLOCK_HIGH;
244
245 if (mode->clock < 10000)
246 return MODE_CLOCK_LOW;
247
248 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
249 return MODE_H_ILLEGAL;
250
251 return MODE_OK;
252 }
253
254 static uint32_t
255 pack_aux(uint8_t *src, int src_bytes)
256 {
257 int i;
258 uint32_t v = 0;
259
260 if (src_bytes > 4)
261 src_bytes = 4;
262 for (i = 0; i < src_bytes; i++)
263 v |= ((uint32_t) src[i]) << ((3-i) * 8);
264 return v;
265 }
266
267 static void
268 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
269 {
270 int i;
271 if (dst_bytes > 4)
272 dst_bytes = 4;
273 for (i = 0; i < dst_bytes; i++)
274 dst[i] = src >> ((3-i) * 8);
275 }
276
277 /* hrawclock is 1/4 the FSB frequency */
278 static int
279 intel_hrawclk(struct drm_device *dev)
280 {
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t clkcfg;
283
284 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
285 if (IS_VALLEYVIEW(dev))
286 return 200;
287
288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
290 case CLKCFG_FSB_400:
291 return 100;
292 case CLKCFG_FSB_533:
293 return 133;
294 case CLKCFG_FSB_667:
295 return 166;
296 case CLKCFG_FSB_800:
297 return 200;
298 case CLKCFG_FSB_1067:
299 return 266;
300 case CLKCFG_FSB_1333:
301 return 333;
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
305 return 400;
306 default:
307 return 133;
308 }
309 }
310
311 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312 {
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317 }
318
319 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320 {
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325 }
326
327 static void
328 intel_dp_check_edp(struct intel_dp *intel_dp)
329 {
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
332
333 if (!is_edp(intel_dp))
334 return;
335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
338 I915_READ(PCH_PP_STATUS),
339 I915_READ(PCH_PP_CONTROL));
340 }
341 }
342
343 static int
344 intel_dp_aux_ch(struct intel_dp *intel_dp,
345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
347 {
348 uint32_t output_reg = intel_dp->output_reg;
349 struct drm_device *dev = intel_dp->base.base.dev;
350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
353 int i;
354 int recv_bytes;
355 uint32_t status;
356 uint32_t aux_clock_divider;
357 int try, precharge;
358
359 intel_dp_check_edp(intel_dp);
360 /* The clock divider is based off the hrawclk,
361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
363 *
364 * Note that PCH attached eDP panels should use a 125MHz input
365 * clock divider.
366 */
367 if (is_cpu_edp(intel_dp)) {
368 if (IS_VALLEYVIEW(dev))
369 aux_clock_divider = 100;
370 else if (IS_GEN6(dev) || IS_GEN7(dev))
371 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
372 else
373 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
374 } else if (HAS_PCH_SPLIT(dev))
375 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
376 else
377 aux_clock_divider = intel_hrawclk(dev) / 2;
378
379 if (IS_GEN6(dev))
380 precharge = 3;
381 else
382 precharge = 5;
383
384 /* Try to wait for any previous AUX channel activity */
385 for (try = 0; try < 3; try++) {
386 status = I915_READ(ch_ctl);
387 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
388 break;
389 msleep(1);
390 }
391
392 if (try == 3) {
393 WARN(1, "dp_aux_ch not started status 0x%08x\n",
394 I915_READ(ch_ctl));
395 return -EBUSY;
396 }
397
398 /* Must try at least 3 times according to DP spec */
399 for (try = 0; try < 5; try++) {
400 /* Load the send data into the aux channel data registers */
401 for (i = 0; i < send_bytes; i += 4)
402 I915_WRITE(ch_data + i,
403 pack_aux(send + i, send_bytes - i));
404
405 /* Send the command and wait for it to complete */
406 I915_WRITE(ch_ctl,
407 DP_AUX_CH_CTL_SEND_BUSY |
408 DP_AUX_CH_CTL_TIME_OUT_400us |
409 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
410 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
411 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
412 DP_AUX_CH_CTL_DONE |
413 DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR);
415 for (;;) {
416 status = I915_READ(ch_ctl);
417 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
418 break;
419 udelay(100);
420 }
421
422 /* Clear done status and any errors */
423 I915_WRITE(ch_ctl,
424 status |
425 DP_AUX_CH_CTL_DONE |
426 DP_AUX_CH_CTL_TIME_OUT_ERROR |
427 DP_AUX_CH_CTL_RECEIVE_ERROR);
428
429 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
430 DP_AUX_CH_CTL_RECEIVE_ERROR))
431 continue;
432 if (status & DP_AUX_CH_CTL_DONE)
433 break;
434 }
435
436 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
437 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
438 return -EBUSY;
439 }
440
441 /* Check for timeout or receive error.
442 * Timeouts occur when the sink is not connected
443 */
444 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
445 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
446 return -EIO;
447 }
448
449 /* Timeouts occur when the device isn't connected, so they're
450 * "normal" -- don't fill the kernel log with these */
451 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
452 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
453 return -ETIMEDOUT;
454 }
455
456 /* Unload any bytes sent back from the other side */
457 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
458 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
459 if (recv_bytes > recv_size)
460 recv_bytes = recv_size;
461
462 for (i = 0; i < recv_bytes; i += 4)
463 unpack_aux(I915_READ(ch_data + i),
464 recv + i, recv_bytes - i);
465
466 return recv_bytes;
467 }
468
469 /* Write data to the aux channel in native mode */
470 static int
471 intel_dp_aux_native_write(struct intel_dp *intel_dp,
472 uint16_t address, uint8_t *send, int send_bytes)
473 {
474 int ret;
475 uint8_t msg[20];
476 int msg_bytes;
477 uint8_t ack;
478
479 intel_dp_check_edp(intel_dp);
480 if (send_bytes > 16)
481 return -1;
482 msg[0] = AUX_NATIVE_WRITE << 4;
483 msg[1] = address >> 8;
484 msg[2] = address & 0xff;
485 msg[3] = send_bytes - 1;
486 memcpy(&msg[4], send, send_bytes);
487 msg_bytes = send_bytes + 4;
488 for (;;) {
489 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
490 if (ret < 0)
491 return ret;
492 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
493 break;
494 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
495 udelay(100);
496 else
497 return -EIO;
498 }
499 return send_bytes;
500 }
501
502 /* Write a single byte to the aux channel in native mode */
503 static int
504 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
505 uint16_t address, uint8_t byte)
506 {
507 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
508 }
509
510 /* read bytes from a native aux channel */
511 static int
512 intel_dp_aux_native_read(struct intel_dp *intel_dp,
513 uint16_t address, uint8_t *recv, int recv_bytes)
514 {
515 uint8_t msg[4];
516 int msg_bytes;
517 uint8_t reply[20];
518 int reply_bytes;
519 uint8_t ack;
520 int ret;
521
522 intel_dp_check_edp(intel_dp);
523 msg[0] = AUX_NATIVE_READ << 4;
524 msg[1] = address >> 8;
525 msg[2] = address & 0xff;
526 msg[3] = recv_bytes - 1;
527
528 msg_bytes = 4;
529 reply_bytes = recv_bytes + 1;
530
531 for (;;) {
532 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
533 reply, reply_bytes);
534 if (ret == 0)
535 return -EPROTO;
536 if (ret < 0)
537 return ret;
538 ack = reply[0];
539 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
540 memcpy(recv, reply + 1, ret - 1);
541 return ret - 1;
542 }
543 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
544 udelay(100);
545 else
546 return -EIO;
547 }
548 }
549
550 static int
551 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
552 uint8_t write_byte, uint8_t *read_byte)
553 {
554 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
555 struct intel_dp *intel_dp = container_of(adapter,
556 struct intel_dp,
557 adapter);
558 uint16_t address = algo_data->address;
559 uint8_t msg[5];
560 uint8_t reply[2];
561 unsigned retry;
562 int msg_bytes;
563 int reply_bytes;
564 int ret;
565
566 intel_dp_check_edp(intel_dp);
567 /* Set up the command byte */
568 if (mode & MODE_I2C_READ)
569 msg[0] = AUX_I2C_READ << 4;
570 else
571 msg[0] = AUX_I2C_WRITE << 4;
572
573 if (!(mode & MODE_I2C_STOP))
574 msg[0] |= AUX_I2C_MOT << 4;
575
576 msg[1] = address >> 8;
577 msg[2] = address;
578
579 switch (mode) {
580 case MODE_I2C_WRITE:
581 msg[3] = 0;
582 msg[4] = write_byte;
583 msg_bytes = 5;
584 reply_bytes = 1;
585 break;
586 case MODE_I2C_READ:
587 msg[3] = 0;
588 msg_bytes = 4;
589 reply_bytes = 2;
590 break;
591 default:
592 msg_bytes = 3;
593 reply_bytes = 1;
594 break;
595 }
596
597 for (retry = 0; retry < 5; retry++) {
598 ret = intel_dp_aux_ch(intel_dp,
599 msg, msg_bytes,
600 reply, reply_bytes);
601 if (ret < 0) {
602 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
603 return ret;
604 }
605
606 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
607 case AUX_NATIVE_REPLY_ACK:
608 /* I2C-over-AUX Reply field is only valid
609 * when paired with AUX ACK.
610 */
611 break;
612 case AUX_NATIVE_REPLY_NACK:
613 DRM_DEBUG_KMS("aux_ch native nack\n");
614 return -EREMOTEIO;
615 case AUX_NATIVE_REPLY_DEFER:
616 udelay(100);
617 continue;
618 default:
619 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
620 reply[0]);
621 return -EREMOTEIO;
622 }
623
624 switch (reply[0] & AUX_I2C_REPLY_MASK) {
625 case AUX_I2C_REPLY_ACK:
626 if (mode == MODE_I2C_READ) {
627 *read_byte = reply[1];
628 }
629 return reply_bytes - 1;
630 case AUX_I2C_REPLY_NACK:
631 DRM_DEBUG_KMS("aux_i2c nack\n");
632 return -EREMOTEIO;
633 case AUX_I2C_REPLY_DEFER:
634 DRM_DEBUG_KMS("aux_i2c defer\n");
635 udelay(100);
636 break;
637 default:
638 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
639 return -EREMOTEIO;
640 }
641 }
642
643 DRM_ERROR("too many retries, giving up\n");
644 return -EREMOTEIO;
645 }
646
647 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
648 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
649
650 static int
651 intel_dp_i2c_init(struct intel_dp *intel_dp,
652 struct intel_connector *intel_connector, const char *name)
653 {
654 int ret;
655
656 DRM_DEBUG_KMS("i2c_init %s\n", name);
657 intel_dp->algo.running = false;
658 intel_dp->algo.address = 0;
659 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
660
661 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
662 intel_dp->adapter.owner = THIS_MODULE;
663 intel_dp->adapter.class = I2C_CLASS_DDC;
664 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
665 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
666 intel_dp->adapter.algo_data = &intel_dp->algo;
667 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
668
669 ironlake_edp_panel_vdd_on(intel_dp);
670 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
671 ironlake_edp_panel_vdd_off(intel_dp, false);
672 return ret;
673 }
674
675 static bool
676 intel_dp_mode_fixup(struct drm_encoder *encoder,
677 const struct drm_display_mode *mode,
678 struct drm_display_mode *adjusted_mode)
679 {
680 struct drm_device *dev = encoder->dev;
681 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
682 int lane_count, clock;
683 int max_lane_count = intel_dp_max_lane_count(intel_dp);
684 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
685 int bpp, mode_rate;
686 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
687
688 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
689 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
690 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
691 mode, adjusted_mode);
692 }
693
694 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
695 return false;
696
697 DRM_DEBUG_KMS("DP link computation with max lane count %i "
698 "max bw %02x pixel clock %iKHz\n",
699 max_lane_count, bws[max_clock], adjusted_mode->clock);
700
701 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
702 return false;
703
704 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
705 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
706
707 for (clock = 0; clock <= max_clock; clock++) {
708 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
709 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
710
711 if (mode_rate <= link_avail) {
712 intel_dp->link_bw = bws[clock];
713 intel_dp->lane_count = lane_count;
714 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
715 DRM_DEBUG_KMS("DP link bw %02x lane "
716 "count %d clock %d bpp %d\n",
717 intel_dp->link_bw, intel_dp->lane_count,
718 adjusted_mode->clock, bpp);
719 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
720 mode_rate, link_avail);
721 return true;
722 }
723 }
724 }
725
726 return false;
727 }
728
729 struct intel_dp_m_n {
730 uint32_t tu;
731 uint32_t gmch_m;
732 uint32_t gmch_n;
733 uint32_t link_m;
734 uint32_t link_n;
735 };
736
737 static void
738 intel_reduce_ratio(uint32_t *num, uint32_t *den)
739 {
740 while (*num > 0xffffff || *den > 0xffffff) {
741 *num >>= 1;
742 *den >>= 1;
743 }
744 }
745
746 static void
747 intel_dp_compute_m_n(int bpp,
748 int nlanes,
749 int pixel_clock,
750 int link_clock,
751 struct intel_dp_m_n *m_n)
752 {
753 m_n->tu = 64;
754 m_n->gmch_m = (pixel_clock * bpp) >> 3;
755 m_n->gmch_n = link_clock * nlanes;
756 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
757 m_n->link_m = pixel_clock;
758 m_n->link_n = link_clock;
759 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
760 }
761
762 void
763 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
764 struct drm_display_mode *adjusted_mode)
765 {
766 struct drm_device *dev = crtc->dev;
767 struct intel_encoder *encoder;
768 struct drm_i915_private *dev_priv = dev->dev_private;
769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
770 int lane_count = 4;
771 struct intel_dp_m_n m_n;
772 int pipe = intel_crtc->pipe;
773
774 /*
775 * Find the lane count in the intel_encoder private
776 */
777 for_each_encoder_on_crtc(dev, crtc, encoder) {
778 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
779
780 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
781 intel_dp->base.type == INTEL_OUTPUT_EDP)
782 {
783 lane_count = intel_dp->lane_count;
784 break;
785 }
786 }
787
788 /*
789 * Compute the GMCH and Link ratios. The '3' here is
790 * the number of bytes_per_pixel post-LUT, which we always
791 * set up for 8-bits of R/G/B, or 3 bytes total.
792 */
793 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
794 mode->clock, adjusted_mode->clock, &m_n);
795
796 if (HAS_PCH_SPLIT(dev)) {
797 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
798 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
799 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
800 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
801 } else if (IS_VALLEYVIEW(dev)) {
802 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
803 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
804 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
805 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
806 } else {
807 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
808 TU_SIZE(m_n.tu) | m_n.gmch_m);
809 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
810 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
811 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
812 }
813 }
814
815 static void
816 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
817 struct drm_display_mode *adjusted_mode)
818 {
819 struct drm_device *dev = encoder->dev;
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
822 struct drm_crtc *crtc = intel_dp->base.base.crtc;
823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
824
825 /*
826 * There are four kinds of DP registers:
827 *
828 * IBX PCH
829 * SNB CPU
830 * IVB CPU
831 * CPT PCH
832 *
833 * IBX PCH and CPU are the same for almost everything,
834 * except that the CPU DP PLL is configured in this
835 * register
836 *
837 * CPT PCH is quite different, having many bits moved
838 * to the TRANS_DP_CTL register instead. That
839 * configuration happens (oddly) in ironlake_pch_enable
840 */
841
842 /* Preserve the BIOS-computed detected bit. This is
843 * supposed to be read-only.
844 */
845 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
846
847 /* Handle DP bits in common between all three register formats */
848 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
849
850 switch (intel_dp->lane_count) {
851 case 1:
852 intel_dp->DP |= DP_PORT_WIDTH_1;
853 break;
854 case 2:
855 intel_dp->DP |= DP_PORT_WIDTH_2;
856 break;
857 case 4:
858 intel_dp->DP |= DP_PORT_WIDTH_4;
859 break;
860 }
861 if (intel_dp->has_audio) {
862 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
863 pipe_name(intel_crtc->pipe));
864 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
865 intel_write_eld(encoder, adjusted_mode);
866 }
867 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
868 intel_dp->link_configuration[0] = intel_dp->link_bw;
869 intel_dp->link_configuration[1] = intel_dp->lane_count;
870 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
871 /*
872 * Check for DPCD version > 1.1 and enhanced framing support
873 */
874 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
875 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
876 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
877 }
878
879 /* Split out the IBX/CPU vs CPT settings */
880
881 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
882 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
883 intel_dp->DP |= DP_SYNC_HS_HIGH;
884 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
885 intel_dp->DP |= DP_SYNC_VS_HIGH;
886 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
887
888 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
889 intel_dp->DP |= DP_ENHANCED_FRAMING;
890
891 intel_dp->DP |= intel_crtc->pipe << 29;
892
893 /* don't miss out required setting for eDP */
894 if (adjusted_mode->clock < 200000)
895 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
896 else
897 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
898 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
899 intel_dp->DP |= intel_dp->color_range;
900
901 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
902 intel_dp->DP |= DP_SYNC_HS_HIGH;
903 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
904 intel_dp->DP |= DP_SYNC_VS_HIGH;
905 intel_dp->DP |= DP_LINK_TRAIN_OFF;
906
907 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
908 intel_dp->DP |= DP_ENHANCED_FRAMING;
909
910 if (intel_crtc->pipe == 1)
911 intel_dp->DP |= DP_PIPEB_SELECT;
912
913 if (is_cpu_edp(intel_dp)) {
914 /* don't miss out required setting for eDP */
915 if (adjusted_mode->clock < 200000)
916 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
917 else
918 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
919 }
920 } else {
921 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
922 }
923 }
924
925 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
926 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
927
928 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
929 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
930
931 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
932 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
933
934 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
935 u32 mask,
936 u32 value)
937 {
938 struct drm_device *dev = intel_dp->base.base.dev;
939 struct drm_i915_private *dev_priv = dev->dev_private;
940
941 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
942 mask, value,
943 I915_READ(PCH_PP_STATUS),
944 I915_READ(PCH_PP_CONTROL));
945
946 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
947 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
948 I915_READ(PCH_PP_STATUS),
949 I915_READ(PCH_PP_CONTROL));
950 }
951 }
952
953 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
954 {
955 DRM_DEBUG_KMS("Wait for panel power on\n");
956 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
957 }
958
959 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
960 {
961 DRM_DEBUG_KMS("Wait for panel power off time\n");
962 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
963 }
964
965 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
966 {
967 DRM_DEBUG_KMS("Wait for panel power cycle\n");
968 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
969 }
970
971
972 /* Read the current pp_control value, unlocking the register if it
973 * is locked
974 */
975
976 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
977 {
978 u32 control = I915_READ(PCH_PP_CONTROL);
979
980 control &= ~PANEL_UNLOCK_MASK;
981 control |= PANEL_UNLOCK_REGS;
982 return control;
983 }
984
985 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
986 {
987 struct drm_device *dev = intel_dp->base.base.dev;
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 pp;
990
991 if (!is_edp(intel_dp))
992 return;
993 DRM_DEBUG_KMS("Turn eDP VDD on\n");
994
995 WARN(intel_dp->want_panel_vdd,
996 "eDP VDD already requested on\n");
997
998 intel_dp->want_panel_vdd = true;
999
1000 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1001 DRM_DEBUG_KMS("eDP VDD already on\n");
1002 return;
1003 }
1004
1005 if (!ironlake_edp_have_panel_power(intel_dp))
1006 ironlake_wait_panel_power_cycle(intel_dp);
1007
1008 pp = ironlake_get_pp_control(dev_priv);
1009 pp |= EDP_FORCE_VDD;
1010 I915_WRITE(PCH_PP_CONTROL, pp);
1011 POSTING_READ(PCH_PP_CONTROL);
1012 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1013 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1014
1015 /*
1016 * If the panel wasn't on, delay before accessing aux channel
1017 */
1018 if (!ironlake_edp_have_panel_power(intel_dp)) {
1019 DRM_DEBUG_KMS("eDP was not running\n");
1020 msleep(intel_dp->panel_power_up_delay);
1021 }
1022 }
1023
1024 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1025 {
1026 struct drm_device *dev = intel_dp->base.base.dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 u32 pp;
1029
1030 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1031 pp = ironlake_get_pp_control(dev_priv);
1032 pp &= ~EDP_FORCE_VDD;
1033 I915_WRITE(PCH_PP_CONTROL, pp);
1034 POSTING_READ(PCH_PP_CONTROL);
1035
1036 /* Make sure sequencer is idle before allowing subsequent activity */
1037 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1038 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1039
1040 msleep(intel_dp->panel_power_down_delay);
1041 }
1042 }
1043
1044 static void ironlake_panel_vdd_work(struct work_struct *__work)
1045 {
1046 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1047 struct intel_dp, panel_vdd_work);
1048 struct drm_device *dev = intel_dp->base.base.dev;
1049
1050 mutex_lock(&dev->mode_config.mutex);
1051 ironlake_panel_vdd_off_sync(intel_dp);
1052 mutex_unlock(&dev->mode_config.mutex);
1053 }
1054
1055 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1056 {
1057 if (!is_edp(intel_dp))
1058 return;
1059
1060 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1061 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1062
1063 intel_dp->want_panel_vdd = false;
1064
1065 if (sync) {
1066 ironlake_panel_vdd_off_sync(intel_dp);
1067 } else {
1068 /*
1069 * Queue the timer to fire a long
1070 * time from now (relative to the power down delay)
1071 * to keep the panel power up across a sequence of operations
1072 */
1073 schedule_delayed_work(&intel_dp->panel_vdd_work,
1074 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1075 }
1076 }
1077
1078 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1079 {
1080 struct drm_device *dev = intel_dp->base.base.dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 u32 pp;
1083
1084 if (!is_edp(intel_dp))
1085 return;
1086
1087 DRM_DEBUG_KMS("Turn eDP power on\n");
1088
1089 if (ironlake_edp_have_panel_power(intel_dp)) {
1090 DRM_DEBUG_KMS("eDP power already on\n");
1091 return;
1092 }
1093
1094 ironlake_wait_panel_power_cycle(intel_dp);
1095
1096 pp = ironlake_get_pp_control(dev_priv);
1097 if (IS_GEN5(dev)) {
1098 /* ILK workaround: disable reset around power sequence */
1099 pp &= ~PANEL_POWER_RESET;
1100 I915_WRITE(PCH_PP_CONTROL, pp);
1101 POSTING_READ(PCH_PP_CONTROL);
1102 }
1103
1104 pp |= POWER_TARGET_ON;
1105 if (!IS_GEN5(dev))
1106 pp |= PANEL_POWER_RESET;
1107
1108 I915_WRITE(PCH_PP_CONTROL, pp);
1109 POSTING_READ(PCH_PP_CONTROL);
1110
1111 ironlake_wait_panel_on(intel_dp);
1112
1113 if (IS_GEN5(dev)) {
1114 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1115 I915_WRITE(PCH_PP_CONTROL, pp);
1116 POSTING_READ(PCH_PP_CONTROL);
1117 }
1118 }
1119
1120 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1121 {
1122 struct drm_device *dev = intel_dp->base.base.dev;
1123 struct drm_i915_private *dev_priv = dev->dev_private;
1124 u32 pp;
1125
1126 if (!is_edp(intel_dp))
1127 return;
1128
1129 DRM_DEBUG_KMS("Turn eDP power off\n");
1130
1131 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1132
1133 pp = ironlake_get_pp_control(dev_priv);
1134 /* We need to switch off panel power _and_ force vdd, for otherwise some
1135 * panels get very unhappy and cease to work. */
1136 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1137 I915_WRITE(PCH_PP_CONTROL, pp);
1138 POSTING_READ(PCH_PP_CONTROL);
1139
1140 intel_dp->want_panel_vdd = false;
1141
1142 ironlake_wait_panel_off(intel_dp);
1143 }
1144
1145 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1146 {
1147 struct drm_device *dev = intel_dp->base.base.dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 u32 pp;
1150
1151 if (!is_edp(intel_dp))
1152 return;
1153
1154 DRM_DEBUG_KMS("\n");
1155 /*
1156 * If we enable the backlight right away following a panel power
1157 * on, we may see slight flicker as the panel syncs with the eDP
1158 * link. So delay a bit to make sure the image is solid before
1159 * allowing it to appear.
1160 */
1161 msleep(intel_dp->backlight_on_delay);
1162 pp = ironlake_get_pp_control(dev_priv);
1163 pp |= EDP_BLC_ENABLE;
1164 I915_WRITE(PCH_PP_CONTROL, pp);
1165 POSTING_READ(PCH_PP_CONTROL);
1166 }
1167
1168 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1169 {
1170 struct drm_device *dev = intel_dp->base.base.dev;
1171 struct drm_i915_private *dev_priv = dev->dev_private;
1172 u32 pp;
1173
1174 if (!is_edp(intel_dp))
1175 return;
1176
1177 DRM_DEBUG_KMS("\n");
1178 pp = ironlake_get_pp_control(dev_priv);
1179 pp &= ~EDP_BLC_ENABLE;
1180 I915_WRITE(PCH_PP_CONTROL, pp);
1181 POSTING_READ(PCH_PP_CONTROL);
1182 msleep(intel_dp->backlight_off_delay);
1183 }
1184
1185 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1186 {
1187 struct drm_device *dev = intel_dp->base.base.dev;
1188 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 u32 dpa_ctl;
1191
1192 assert_pipe_disabled(dev_priv,
1193 to_intel_crtc(crtc)->pipe);
1194
1195 DRM_DEBUG_KMS("\n");
1196 dpa_ctl = I915_READ(DP_A);
1197 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1198 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1199
1200 /* We don't adjust intel_dp->DP while tearing down the link, to
1201 * facilitate link retraining (e.g. after hotplug). Hence clear all
1202 * enable bits here to ensure that we don't enable too much. */
1203 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1204 intel_dp->DP |= DP_PLL_ENABLE;
1205 I915_WRITE(DP_A, intel_dp->DP);
1206 POSTING_READ(DP_A);
1207 udelay(200);
1208 }
1209
1210 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1211 {
1212 struct drm_device *dev = intel_dp->base.base.dev;
1213 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1214 struct drm_i915_private *dev_priv = dev->dev_private;
1215 u32 dpa_ctl;
1216
1217 assert_pipe_disabled(dev_priv,
1218 to_intel_crtc(crtc)->pipe);
1219
1220 dpa_ctl = I915_READ(DP_A);
1221 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1222 "dp pll off, should be on\n");
1223 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1224
1225 /* We can't rely on the value tracked for the DP register in
1226 * intel_dp->DP because link_down must not change that (otherwise link
1227 * re-training will fail. */
1228 dpa_ctl &= ~DP_PLL_ENABLE;
1229 I915_WRITE(DP_A, dpa_ctl);
1230 POSTING_READ(DP_A);
1231 udelay(200);
1232 }
1233
1234 /* If the sink supports it, try to set the power state appropriately */
1235 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1236 {
1237 int ret, i;
1238
1239 /* Should have a valid DPCD by this point */
1240 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1241 return;
1242
1243 if (mode != DRM_MODE_DPMS_ON) {
1244 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1245 DP_SET_POWER_D3);
1246 if (ret != 1)
1247 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1248 } else {
1249 /*
1250 * When turning on, we need to retry for 1ms to give the sink
1251 * time to wake up.
1252 */
1253 for (i = 0; i < 3; i++) {
1254 ret = intel_dp_aux_native_write_1(intel_dp,
1255 DP_SET_POWER,
1256 DP_SET_POWER_D0);
1257 if (ret == 1)
1258 break;
1259 msleep(1);
1260 }
1261 }
1262 }
1263
1264 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1265 enum pipe *pipe)
1266 {
1267 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1268 struct drm_device *dev = encoder->base.dev;
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 u32 tmp = I915_READ(intel_dp->output_reg);
1271
1272 if (!(tmp & DP_PORT_EN))
1273 return false;
1274
1275 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1276 *pipe = PORT_TO_PIPE_CPT(tmp);
1277 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1278 *pipe = PORT_TO_PIPE(tmp);
1279 } else {
1280 u32 trans_sel;
1281 u32 trans_dp;
1282 int i;
1283
1284 switch (intel_dp->output_reg) {
1285 case PCH_DP_B:
1286 trans_sel = TRANS_DP_PORT_SEL_B;
1287 break;
1288 case PCH_DP_C:
1289 trans_sel = TRANS_DP_PORT_SEL_C;
1290 break;
1291 case PCH_DP_D:
1292 trans_sel = TRANS_DP_PORT_SEL_D;
1293 break;
1294 default:
1295 return true;
1296 }
1297
1298 for_each_pipe(i) {
1299 trans_dp = I915_READ(TRANS_DP_CTL(i));
1300 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1301 *pipe = i;
1302 return true;
1303 }
1304 }
1305 }
1306
1307 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1308
1309 return true;
1310 }
1311
1312 static void intel_disable_dp(struct intel_encoder *encoder)
1313 {
1314 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1315
1316 /* Make sure the panel is off before trying to change the mode. But also
1317 * ensure that we have vdd while we switch off the panel. */
1318 ironlake_edp_panel_vdd_on(intel_dp);
1319 ironlake_edp_backlight_off(intel_dp);
1320 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1321 ironlake_edp_panel_off(intel_dp);
1322
1323 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1324 if (!is_cpu_edp(intel_dp))
1325 intel_dp_link_down(intel_dp);
1326 }
1327
1328 static void intel_post_disable_dp(struct intel_encoder *encoder)
1329 {
1330 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1331
1332 if (is_cpu_edp(intel_dp)) {
1333 intel_dp_link_down(intel_dp);
1334 ironlake_edp_pll_off(intel_dp);
1335 }
1336 }
1337
1338 static void intel_enable_dp(struct intel_encoder *encoder)
1339 {
1340 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1341 struct drm_device *dev = encoder->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1344
1345 if (WARN_ON(dp_reg & DP_PORT_EN))
1346 return;
1347
1348 ironlake_edp_panel_vdd_on(intel_dp);
1349 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1350 intel_dp_start_link_train(intel_dp);
1351 ironlake_edp_panel_on(intel_dp);
1352 ironlake_edp_panel_vdd_off(intel_dp, true);
1353 intel_dp_complete_link_train(intel_dp);
1354 ironlake_edp_backlight_on(intel_dp);
1355 }
1356
1357 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1358 {
1359 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1360
1361 if (is_cpu_edp(intel_dp))
1362 ironlake_edp_pll_on(intel_dp);
1363 }
1364
1365 /*
1366 * Native read with retry for link status and receiver capability reads for
1367 * cases where the sink may still be asleep.
1368 */
1369 static bool
1370 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1371 uint8_t *recv, int recv_bytes)
1372 {
1373 int ret, i;
1374
1375 /*
1376 * Sinks are *supposed* to come up within 1ms from an off state,
1377 * but we're also supposed to retry 3 times per the spec.
1378 */
1379 for (i = 0; i < 3; i++) {
1380 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1381 recv_bytes);
1382 if (ret == recv_bytes)
1383 return true;
1384 msleep(1);
1385 }
1386
1387 return false;
1388 }
1389
1390 /*
1391 * Fetch AUX CH registers 0x202 - 0x207 which contain
1392 * link status information
1393 */
1394 static bool
1395 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1396 {
1397 return intel_dp_aux_native_read_retry(intel_dp,
1398 DP_LANE0_1_STATUS,
1399 link_status,
1400 DP_LINK_STATUS_SIZE);
1401 }
1402
1403 static uint8_t
1404 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1405 int r)
1406 {
1407 return link_status[r - DP_LANE0_1_STATUS];
1408 }
1409
1410 static uint8_t
1411 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1412 int lane)
1413 {
1414 int s = ((lane & 1) ?
1415 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1416 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1417 uint8_t l = adjust_request[lane>>1];
1418
1419 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1420 }
1421
1422 static uint8_t
1423 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1424 int lane)
1425 {
1426 int s = ((lane & 1) ?
1427 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1428 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1429 uint8_t l = adjust_request[lane>>1];
1430
1431 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1432 }
1433
1434
1435 #if 0
1436 static char *voltage_names[] = {
1437 "0.4V", "0.6V", "0.8V", "1.2V"
1438 };
1439 static char *pre_emph_names[] = {
1440 "0dB", "3.5dB", "6dB", "9.5dB"
1441 };
1442 static char *link_train_names[] = {
1443 "pattern 1", "pattern 2", "idle", "off"
1444 };
1445 #endif
1446
1447 /*
1448 * These are source-specific values; current Intel hardware supports
1449 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1450 */
1451
1452 static uint8_t
1453 intel_dp_voltage_max(struct intel_dp *intel_dp)
1454 {
1455 struct drm_device *dev = intel_dp->base.base.dev;
1456
1457 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1458 return DP_TRAIN_VOLTAGE_SWING_800;
1459 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1460 return DP_TRAIN_VOLTAGE_SWING_1200;
1461 else
1462 return DP_TRAIN_VOLTAGE_SWING_800;
1463 }
1464
1465 static uint8_t
1466 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1467 {
1468 struct drm_device *dev = intel_dp->base.base.dev;
1469
1470 if (IS_HASWELL(dev)) {
1471 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1472 case DP_TRAIN_VOLTAGE_SWING_400:
1473 return DP_TRAIN_PRE_EMPHASIS_9_5;
1474 case DP_TRAIN_VOLTAGE_SWING_600:
1475 return DP_TRAIN_PRE_EMPHASIS_6;
1476 case DP_TRAIN_VOLTAGE_SWING_800:
1477 return DP_TRAIN_PRE_EMPHASIS_3_5;
1478 case DP_TRAIN_VOLTAGE_SWING_1200:
1479 default:
1480 return DP_TRAIN_PRE_EMPHASIS_0;
1481 }
1482 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1483 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1484 case DP_TRAIN_VOLTAGE_SWING_400:
1485 return DP_TRAIN_PRE_EMPHASIS_6;
1486 case DP_TRAIN_VOLTAGE_SWING_600:
1487 case DP_TRAIN_VOLTAGE_SWING_800:
1488 return DP_TRAIN_PRE_EMPHASIS_3_5;
1489 default:
1490 return DP_TRAIN_PRE_EMPHASIS_0;
1491 }
1492 } else {
1493 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1494 case DP_TRAIN_VOLTAGE_SWING_400:
1495 return DP_TRAIN_PRE_EMPHASIS_6;
1496 case DP_TRAIN_VOLTAGE_SWING_600:
1497 return DP_TRAIN_PRE_EMPHASIS_6;
1498 case DP_TRAIN_VOLTAGE_SWING_800:
1499 return DP_TRAIN_PRE_EMPHASIS_3_5;
1500 case DP_TRAIN_VOLTAGE_SWING_1200:
1501 default:
1502 return DP_TRAIN_PRE_EMPHASIS_0;
1503 }
1504 }
1505 }
1506
1507 static void
1508 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1509 {
1510 uint8_t v = 0;
1511 uint8_t p = 0;
1512 int lane;
1513 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1514 uint8_t voltage_max;
1515 uint8_t preemph_max;
1516
1517 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1518 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1519 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1520
1521 if (this_v > v)
1522 v = this_v;
1523 if (this_p > p)
1524 p = this_p;
1525 }
1526
1527 voltage_max = intel_dp_voltage_max(intel_dp);
1528 if (v >= voltage_max)
1529 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1530
1531 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1532 if (p >= preemph_max)
1533 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1534
1535 for (lane = 0; lane < 4; lane++)
1536 intel_dp->train_set[lane] = v | p;
1537 }
1538
1539 static uint32_t
1540 intel_dp_signal_levels(uint8_t train_set)
1541 {
1542 uint32_t signal_levels = 0;
1543
1544 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1545 case DP_TRAIN_VOLTAGE_SWING_400:
1546 default:
1547 signal_levels |= DP_VOLTAGE_0_4;
1548 break;
1549 case DP_TRAIN_VOLTAGE_SWING_600:
1550 signal_levels |= DP_VOLTAGE_0_6;
1551 break;
1552 case DP_TRAIN_VOLTAGE_SWING_800:
1553 signal_levels |= DP_VOLTAGE_0_8;
1554 break;
1555 case DP_TRAIN_VOLTAGE_SWING_1200:
1556 signal_levels |= DP_VOLTAGE_1_2;
1557 break;
1558 }
1559 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1560 case DP_TRAIN_PRE_EMPHASIS_0:
1561 default:
1562 signal_levels |= DP_PRE_EMPHASIS_0;
1563 break;
1564 case DP_TRAIN_PRE_EMPHASIS_3_5:
1565 signal_levels |= DP_PRE_EMPHASIS_3_5;
1566 break;
1567 case DP_TRAIN_PRE_EMPHASIS_6:
1568 signal_levels |= DP_PRE_EMPHASIS_6;
1569 break;
1570 case DP_TRAIN_PRE_EMPHASIS_9_5:
1571 signal_levels |= DP_PRE_EMPHASIS_9_5;
1572 break;
1573 }
1574 return signal_levels;
1575 }
1576
1577 /* Gen6's DP voltage swing and pre-emphasis control */
1578 static uint32_t
1579 intel_gen6_edp_signal_levels(uint8_t train_set)
1580 {
1581 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1582 DP_TRAIN_PRE_EMPHASIS_MASK);
1583 switch (signal_levels) {
1584 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1585 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1586 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1587 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1588 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1589 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1590 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1591 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1592 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1593 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1595 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1596 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1597 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1598 default:
1599 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1600 "0x%x\n", signal_levels);
1601 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1602 }
1603 }
1604
1605 /* Gen7's DP voltage swing and pre-emphasis control */
1606 static uint32_t
1607 intel_gen7_edp_signal_levels(uint8_t train_set)
1608 {
1609 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1610 DP_TRAIN_PRE_EMPHASIS_MASK);
1611 switch (signal_levels) {
1612 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1613 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1614 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1615 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1616 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1617 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1618
1619 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1620 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1621 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1622 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1623
1624 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1625 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1626 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1627 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1628
1629 default:
1630 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1631 "0x%x\n", signal_levels);
1632 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1633 }
1634 }
1635
1636 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1637 static uint32_t
1638 intel_dp_signal_levels_hsw(uint8_t train_set)
1639 {
1640 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1641 DP_TRAIN_PRE_EMPHASIS_MASK);
1642 switch (signal_levels) {
1643 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1644 return DDI_BUF_EMP_400MV_0DB_HSW;
1645 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1646 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1647 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1648 return DDI_BUF_EMP_400MV_6DB_HSW;
1649 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1650 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1651
1652 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1653 return DDI_BUF_EMP_600MV_0DB_HSW;
1654 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1655 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1656 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1657 return DDI_BUF_EMP_600MV_6DB_HSW;
1658
1659 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1660 return DDI_BUF_EMP_800MV_0DB_HSW;
1661 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1662 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1663 default:
1664 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1665 "0x%x\n", signal_levels);
1666 return DDI_BUF_EMP_400MV_0DB_HSW;
1667 }
1668 }
1669
1670 static uint8_t
1671 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1672 int lane)
1673 {
1674 int s = (lane & 1) * 4;
1675 uint8_t l = link_status[lane>>1];
1676
1677 return (l >> s) & 0xf;
1678 }
1679
1680 /* Check for clock recovery is done on all channels */
1681 static bool
1682 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1683 {
1684 int lane;
1685 uint8_t lane_status;
1686
1687 for (lane = 0; lane < lane_count; lane++) {
1688 lane_status = intel_get_lane_status(link_status, lane);
1689 if ((lane_status & DP_LANE_CR_DONE) == 0)
1690 return false;
1691 }
1692 return true;
1693 }
1694
1695 /* Check to see if channel eq is done on all channels */
1696 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1697 DP_LANE_CHANNEL_EQ_DONE|\
1698 DP_LANE_SYMBOL_LOCKED)
1699 static bool
1700 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1701 {
1702 uint8_t lane_align;
1703 uint8_t lane_status;
1704 int lane;
1705
1706 lane_align = intel_dp_link_status(link_status,
1707 DP_LANE_ALIGN_STATUS_UPDATED);
1708 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1709 return false;
1710 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1711 lane_status = intel_get_lane_status(link_status, lane);
1712 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1713 return false;
1714 }
1715 return true;
1716 }
1717
1718 static bool
1719 intel_dp_set_link_train(struct intel_dp *intel_dp,
1720 uint32_t dp_reg_value,
1721 uint8_t dp_train_pat)
1722 {
1723 struct drm_device *dev = intel_dp->base.base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 int ret;
1726 uint32_t temp;
1727
1728 if (IS_HASWELL(dev)) {
1729 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1730
1731 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1732 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1733 else
1734 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1735
1736 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1737 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1738 case DP_TRAINING_PATTERN_DISABLE:
1739 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1740 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1741
1742 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1743 DP_TP_STATUS_IDLE_DONE), 1))
1744 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1745
1746 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1747 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1748
1749 break;
1750 case DP_TRAINING_PATTERN_1:
1751 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1752 break;
1753 case DP_TRAINING_PATTERN_2:
1754 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1755 break;
1756 case DP_TRAINING_PATTERN_3:
1757 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1758 break;
1759 }
1760 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1761
1762 } else if (HAS_PCH_CPT(dev) &&
1763 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1764 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1765
1766 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1767 case DP_TRAINING_PATTERN_DISABLE:
1768 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1769 break;
1770 case DP_TRAINING_PATTERN_1:
1771 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1772 break;
1773 case DP_TRAINING_PATTERN_2:
1774 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1775 break;
1776 case DP_TRAINING_PATTERN_3:
1777 DRM_ERROR("DP training pattern 3 not supported\n");
1778 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1779 break;
1780 }
1781
1782 } else {
1783 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1784
1785 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1786 case DP_TRAINING_PATTERN_DISABLE:
1787 dp_reg_value |= DP_LINK_TRAIN_OFF;
1788 break;
1789 case DP_TRAINING_PATTERN_1:
1790 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1791 break;
1792 case DP_TRAINING_PATTERN_2:
1793 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1794 break;
1795 case DP_TRAINING_PATTERN_3:
1796 DRM_ERROR("DP training pattern 3 not supported\n");
1797 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1798 break;
1799 }
1800 }
1801
1802 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1803 POSTING_READ(intel_dp->output_reg);
1804
1805 intel_dp_aux_native_write_1(intel_dp,
1806 DP_TRAINING_PATTERN_SET,
1807 dp_train_pat);
1808
1809 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1810 DP_TRAINING_PATTERN_DISABLE) {
1811 ret = intel_dp_aux_native_write(intel_dp,
1812 DP_TRAINING_LANE0_SET,
1813 intel_dp->train_set,
1814 intel_dp->lane_count);
1815 if (ret != intel_dp->lane_count)
1816 return false;
1817 }
1818
1819 return true;
1820 }
1821
1822 /* Enable corresponding port and start training pattern 1 */
1823 static void
1824 intel_dp_start_link_train(struct intel_dp *intel_dp)
1825 {
1826 struct drm_device *dev = intel_dp->base.base.dev;
1827 int i;
1828 uint8_t voltage;
1829 bool clock_recovery = false;
1830 int voltage_tries, loop_tries;
1831 uint32_t DP = intel_dp->DP;
1832
1833 /* Write the link configuration data */
1834 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1835 intel_dp->link_configuration,
1836 DP_LINK_CONFIGURATION_SIZE);
1837
1838 DP |= DP_PORT_EN;
1839
1840 memset(intel_dp->train_set, 0, 4);
1841 voltage = 0xff;
1842 voltage_tries = 0;
1843 loop_tries = 0;
1844 clock_recovery = false;
1845 for (;;) {
1846 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1847 uint8_t link_status[DP_LINK_STATUS_SIZE];
1848 uint32_t signal_levels;
1849
1850 if (IS_HASWELL(dev)) {
1851 signal_levels = intel_dp_signal_levels_hsw(
1852 intel_dp->train_set[0]);
1853 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1854 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1855 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1856 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1857 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1858 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1859 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1860 } else {
1861 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1862 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1863 }
1864 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1865 signal_levels);
1866
1867 if (!intel_dp_set_link_train(intel_dp, DP,
1868 DP_TRAINING_PATTERN_1 |
1869 DP_LINK_SCRAMBLING_DISABLE))
1870 break;
1871 /* Set training pattern 1 */
1872
1873 udelay(100);
1874 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1875 DRM_ERROR("failed to get link status\n");
1876 break;
1877 }
1878
1879 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1880 DRM_DEBUG_KMS("clock recovery OK\n");
1881 clock_recovery = true;
1882 break;
1883 }
1884
1885 /* Check to see if we've tried the max voltage */
1886 for (i = 0; i < intel_dp->lane_count; i++)
1887 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1888 break;
1889 if (i == intel_dp->lane_count && voltage_tries == 5) {
1890 ++loop_tries;
1891 if (loop_tries == 5) {
1892 DRM_DEBUG_KMS("too many full retries, give up\n");
1893 break;
1894 }
1895 memset(intel_dp->train_set, 0, 4);
1896 voltage_tries = 0;
1897 continue;
1898 }
1899
1900 /* Check to see if we've tried the same voltage 5 times */
1901 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1902 ++voltage_tries;
1903 if (voltage_tries == 5) {
1904 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1905 break;
1906 }
1907 } else
1908 voltage_tries = 0;
1909 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1910
1911 /* Compute new intel_dp->train_set as requested by target */
1912 intel_get_adjust_train(intel_dp, link_status);
1913 }
1914
1915 intel_dp->DP = DP;
1916 }
1917
1918 static void
1919 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1920 {
1921 struct drm_device *dev = intel_dp->base.base.dev;
1922 bool channel_eq = false;
1923 int tries, cr_tries;
1924 uint32_t DP = intel_dp->DP;
1925
1926 /* channel equalization */
1927 tries = 0;
1928 cr_tries = 0;
1929 channel_eq = false;
1930 for (;;) {
1931 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1932 uint32_t signal_levels;
1933 uint8_t link_status[DP_LINK_STATUS_SIZE];
1934
1935 if (cr_tries > 5) {
1936 DRM_ERROR("failed to train DP, aborting\n");
1937 intel_dp_link_down(intel_dp);
1938 break;
1939 }
1940
1941 if (IS_HASWELL(dev)) {
1942 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1943 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1944 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1945 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1946 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1947 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1948 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1949 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1950 } else {
1951 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1952 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1953 }
1954
1955 /* channel eq pattern */
1956 if (!intel_dp_set_link_train(intel_dp, DP,
1957 DP_TRAINING_PATTERN_2 |
1958 DP_LINK_SCRAMBLING_DISABLE))
1959 break;
1960
1961 udelay(400);
1962 if (!intel_dp_get_link_status(intel_dp, link_status))
1963 break;
1964
1965 /* Make sure clock is still ok */
1966 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1967 intel_dp_start_link_train(intel_dp);
1968 cr_tries++;
1969 continue;
1970 }
1971
1972 if (intel_channel_eq_ok(intel_dp, link_status)) {
1973 channel_eq = true;
1974 break;
1975 }
1976
1977 /* Try 5 times, then try clock recovery if that fails */
1978 if (tries > 5) {
1979 intel_dp_link_down(intel_dp);
1980 intel_dp_start_link_train(intel_dp);
1981 tries = 0;
1982 cr_tries++;
1983 continue;
1984 }
1985
1986 /* Compute new intel_dp->train_set as requested by target */
1987 intel_get_adjust_train(intel_dp, link_status);
1988 ++tries;
1989 }
1990
1991 if (channel_eq)
1992 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1993
1994 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1995 }
1996
1997 static void
1998 intel_dp_link_down(struct intel_dp *intel_dp)
1999 {
2000 struct drm_device *dev = intel_dp->base.base.dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 uint32_t DP = intel_dp->DP;
2003
2004 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2005 return;
2006
2007 DRM_DEBUG_KMS("\n");
2008
2009 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2010 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2011 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2012 } else {
2013 DP &= ~DP_LINK_TRAIN_MASK;
2014 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2015 }
2016 POSTING_READ(intel_dp->output_reg);
2017
2018 msleep(17);
2019
2020 if (HAS_PCH_IBX(dev) &&
2021 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2022 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2023
2024 /* Hardware workaround: leaving our transcoder select
2025 * set to transcoder B while it's off will prevent the
2026 * corresponding HDMI output on transcoder A.
2027 *
2028 * Combine this with another hardware workaround:
2029 * transcoder select bit can only be cleared while the
2030 * port is enabled.
2031 */
2032 DP &= ~DP_PIPEB_SELECT;
2033 I915_WRITE(intel_dp->output_reg, DP);
2034
2035 /* Changes to enable or select take place the vblank
2036 * after being written.
2037 */
2038 if (crtc == NULL) {
2039 /* We can arrive here never having been attached
2040 * to a CRTC, for instance, due to inheriting
2041 * random state from the BIOS.
2042 *
2043 * If the pipe is not running, play safe and
2044 * wait for the clocks to stabilise before
2045 * continuing.
2046 */
2047 POSTING_READ(intel_dp->output_reg);
2048 msleep(50);
2049 } else
2050 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2051 }
2052
2053 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2054 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2055 POSTING_READ(intel_dp->output_reg);
2056 msleep(intel_dp->panel_power_down_delay);
2057 }
2058
2059 static bool
2060 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2061 {
2062 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2063 sizeof(intel_dp->dpcd)) == 0)
2064 return false; /* aux transfer failed */
2065
2066 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2067 return false; /* DPCD not present */
2068
2069 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2070 DP_DWN_STRM_PORT_PRESENT))
2071 return true; /* native DP sink */
2072
2073 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2074 return true; /* no per-port downstream info */
2075
2076 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2077 intel_dp->downstream_ports,
2078 DP_MAX_DOWNSTREAM_PORTS) == 0)
2079 return false; /* downstream port status fetch failed */
2080
2081 return true;
2082 }
2083
2084 static void
2085 intel_dp_probe_oui(struct intel_dp *intel_dp)
2086 {
2087 u8 buf[3];
2088
2089 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2090 return;
2091
2092 ironlake_edp_panel_vdd_on(intel_dp);
2093
2094 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2095 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2096 buf[0], buf[1], buf[2]);
2097
2098 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2099 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2100 buf[0], buf[1], buf[2]);
2101
2102 ironlake_edp_panel_vdd_off(intel_dp, false);
2103 }
2104
2105 static bool
2106 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2107 {
2108 int ret;
2109
2110 ret = intel_dp_aux_native_read_retry(intel_dp,
2111 DP_DEVICE_SERVICE_IRQ_VECTOR,
2112 sink_irq_vector, 1);
2113 if (!ret)
2114 return false;
2115
2116 return true;
2117 }
2118
2119 static void
2120 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2121 {
2122 /* NAK by default */
2123 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2124 }
2125
2126 /*
2127 * According to DP spec
2128 * 5.1.2:
2129 * 1. Read DPCD
2130 * 2. Configure link according to Receiver Capabilities
2131 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2132 * 4. Check link status on receipt of hot-plug interrupt
2133 */
2134
2135 static void
2136 intel_dp_check_link_status(struct intel_dp *intel_dp)
2137 {
2138 u8 sink_irq_vector;
2139 u8 link_status[DP_LINK_STATUS_SIZE];
2140
2141 if (!intel_dp->base.connectors_active)
2142 return;
2143
2144 if (WARN_ON(!intel_dp->base.base.crtc))
2145 return;
2146
2147 /* Try to read receiver status if the link appears to be up */
2148 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2149 intel_dp_link_down(intel_dp);
2150 return;
2151 }
2152
2153 /* Now read the DPCD to see if it's actually running */
2154 if (!intel_dp_get_dpcd(intel_dp)) {
2155 intel_dp_link_down(intel_dp);
2156 return;
2157 }
2158
2159 /* Try to read the source of the interrupt */
2160 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2161 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2162 /* Clear interrupt source */
2163 intel_dp_aux_native_write_1(intel_dp,
2164 DP_DEVICE_SERVICE_IRQ_VECTOR,
2165 sink_irq_vector);
2166
2167 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2168 intel_dp_handle_test_request(intel_dp);
2169 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2170 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2171 }
2172
2173 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2174 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2175 drm_get_encoder_name(&intel_dp->base.base));
2176 intel_dp_start_link_train(intel_dp);
2177 intel_dp_complete_link_train(intel_dp);
2178 }
2179 }
2180
2181 /* XXX this is probably wrong for multiple downstream ports */
2182 static enum drm_connector_status
2183 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2184 {
2185 uint8_t *dpcd = intel_dp->dpcd;
2186 bool hpd;
2187 uint8_t type;
2188
2189 if (!intel_dp_get_dpcd(intel_dp))
2190 return connector_status_disconnected;
2191
2192 /* if there's no downstream port, we're done */
2193 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2194 return connector_status_connected;
2195
2196 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2197 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2198 if (hpd) {
2199 uint8_t reg;
2200 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2201 &reg, 1))
2202 return connector_status_unknown;
2203 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2204 : connector_status_disconnected;
2205 }
2206
2207 /* If no HPD, poke DDC gently */
2208 if (drm_probe_ddc(&intel_dp->adapter))
2209 return connector_status_connected;
2210
2211 /* Well we tried, say unknown for unreliable port types */
2212 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2213 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2214 return connector_status_unknown;
2215
2216 /* Anything else is out of spec, warn and ignore */
2217 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2218 return connector_status_disconnected;
2219 }
2220
2221 static enum drm_connector_status
2222 ironlake_dp_detect(struct intel_dp *intel_dp)
2223 {
2224 enum drm_connector_status status;
2225
2226 /* Can't disconnect eDP, but you can close the lid... */
2227 if (is_edp(intel_dp)) {
2228 status = intel_panel_detect(intel_dp->base.base.dev);
2229 if (status == connector_status_unknown)
2230 status = connector_status_connected;
2231 return status;
2232 }
2233
2234 return intel_dp_detect_dpcd(intel_dp);
2235 }
2236
2237 static enum drm_connector_status
2238 g4x_dp_detect(struct intel_dp *intel_dp)
2239 {
2240 struct drm_device *dev = intel_dp->base.base.dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 uint32_t bit;
2243
2244 switch (intel_dp->output_reg) {
2245 case DP_B:
2246 bit = DPB_HOTPLUG_LIVE_STATUS;
2247 break;
2248 case DP_C:
2249 bit = DPC_HOTPLUG_LIVE_STATUS;
2250 break;
2251 case DP_D:
2252 bit = DPD_HOTPLUG_LIVE_STATUS;
2253 break;
2254 default:
2255 return connector_status_unknown;
2256 }
2257
2258 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2259 return connector_status_disconnected;
2260
2261 return intel_dp_detect_dpcd(intel_dp);
2262 }
2263
2264 static struct edid *
2265 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2266 {
2267 struct intel_dp *intel_dp = intel_attached_dp(connector);
2268 struct edid *edid;
2269 int size;
2270
2271 if (is_edp(intel_dp)) {
2272 if (!intel_dp->edid)
2273 return NULL;
2274
2275 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2276 edid = kmalloc(size, GFP_KERNEL);
2277 if (!edid)
2278 return NULL;
2279
2280 memcpy(edid, intel_dp->edid, size);
2281 return edid;
2282 }
2283
2284 edid = drm_get_edid(connector, adapter);
2285 return edid;
2286 }
2287
2288 static int
2289 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2290 {
2291 struct intel_dp *intel_dp = intel_attached_dp(connector);
2292 int ret;
2293
2294 if (is_edp(intel_dp)) {
2295 drm_mode_connector_update_edid_property(connector,
2296 intel_dp->edid);
2297 ret = drm_add_edid_modes(connector, intel_dp->edid);
2298 drm_edid_to_eld(connector,
2299 intel_dp->edid);
2300 return intel_dp->edid_mode_count;
2301 }
2302
2303 ret = intel_ddc_get_modes(connector, adapter);
2304 return ret;
2305 }
2306
2307
2308 /**
2309 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2310 *
2311 * \return true if DP port is connected.
2312 * \return false if DP port is disconnected.
2313 */
2314 static enum drm_connector_status
2315 intel_dp_detect(struct drm_connector *connector, bool force)
2316 {
2317 struct intel_dp *intel_dp = intel_attached_dp(connector);
2318 struct drm_device *dev = intel_dp->base.base.dev;
2319 enum drm_connector_status status;
2320 struct edid *edid = NULL;
2321
2322 intel_dp->has_audio = false;
2323
2324 if (HAS_PCH_SPLIT(dev))
2325 status = ironlake_dp_detect(intel_dp);
2326 else
2327 status = g4x_dp_detect(intel_dp);
2328
2329 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2330 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2331 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2332 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2333
2334 if (status != connector_status_connected)
2335 return status;
2336
2337 intel_dp_probe_oui(intel_dp);
2338
2339 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2340 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2341 } else {
2342 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2343 if (edid) {
2344 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2345 kfree(edid);
2346 }
2347 }
2348
2349 return connector_status_connected;
2350 }
2351
2352 static int intel_dp_get_modes(struct drm_connector *connector)
2353 {
2354 struct intel_dp *intel_dp = intel_attached_dp(connector);
2355 struct drm_device *dev = intel_dp->base.base.dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 int ret;
2358
2359 /* We should parse the EDID data and find out if it has an audio sink
2360 */
2361
2362 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2363 if (ret) {
2364 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2365 struct drm_display_mode *newmode;
2366 list_for_each_entry(newmode, &connector->probed_modes,
2367 head) {
2368 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2369 intel_dp->panel_fixed_mode =
2370 drm_mode_duplicate(dev, newmode);
2371 break;
2372 }
2373 }
2374 }
2375 return ret;
2376 }
2377
2378 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2379 if (is_edp(intel_dp)) {
2380 /* initialize panel mode from VBT if available for eDP */
2381 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2382 intel_dp->panel_fixed_mode =
2383 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2384 if (intel_dp->panel_fixed_mode) {
2385 intel_dp->panel_fixed_mode->type |=
2386 DRM_MODE_TYPE_PREFERRED;
2387 }
2388 }
2389 if (intel_dp->panel_fixed_mode) {
2390 struct drm_display_mode *mode;
2391 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2392 drm_mode_probed_add(connector, mode);
2393 return 1;
2394 }
2395 }
2396 return 0;
2397 }
2398
2399 static bool
2400 intel_dp_detect_audio(struct drm_connector *connector)
2401 {
2402 struct intel_dp *intel_dp = intel_attached_dp(connector);
2403 struct edid *edid;
2404 bool has_audio = false;
2405
2406 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2407 if (edid) {
2408 has_audio = drm_detect_monitor_audio(edid);
2409 kfree(edid);
2410 }
2411
2412 return has_audio;
2413 }
2414
2415 static int
2416 intel_dp_set_property(struct drm_connector *connector,
2417 struct drm_property *property,
2418 uint64_t val)
2419 {
2420 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2421 struct intel_dp *intel_dp = intel_attached_dp(connector);
2422 int ret;
2423
2424 ret = drm_connector_property_set_value(connector, property, val);
2425 if (ret)
2426 return ret;
2427
2428 if (property == dev_priv->force_audio_property) {
2429 int i = val;
2430 bool has_audio;
2431
2432 if (i == intel_dp->force_audio)
2433 return 0;
2434
2435 intel_dp->force_audio = i;
2436
2437 if (i == HDMI_AUDIO_AUTO)
2438 has_audio = intel_dp_detect_audio(connector);
2439 else
2440 has_audio = (i == HDMI_AUDIO_ON);
2441
2442 if (has_audio == intel_dp->has_audio)
2443 return 0;
2444
2445 intel_dp->has_audio = has_audio;
2446 goto done;
2447 }
2448
2449 if (property == dev_priv->broadcast_rgb_property) {
2450 if (val == !!intel_dp->color_range)
2451 return 0;
2452
2453 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2454 goto done;
2455 }
2456
2457 return -EINVAL;
2458
2459 done:
2460 if (intel_dp->base.base.crtc) {
2461 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2462 intel_set_mode(crtc, &crtc->mode,
2463 crtc->x, crtc->y, crtc->fb);
2464 }
2465
2466 return 0;
2467 }
2468
2469 static void
2470 intel_dp_destroy(struct drm_connector *connector)
2471 {
2472 struct drm_device *dev = connector->dev;
2473
2474 if (intel_dpd_is_edp(dev))
2475 intel_panel_destroy_backlight(dev);
2476
2477 drm_sysfs_connector_remove(connector);
2478 drm_connector_cleanup(connector);
2479 kfree(connector);
2480 }
2481
2482 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2483 {
2484 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2485
2486 i2c_del_adapter(&intel_dp->adapter);
2487 drm_encoder_cleanup(encoder);
2488 if (is_edp(intel_dp)) {
2489 kfree(intel_dp->edid);
2490 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2491 ironlake_panel_vdd_off_sync(intel_dp);
2492 }
2493 kfree(intel_dp);
2494 }
2495
2496 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2497 .mode_fixup = intel_dp_mode_fixup,
2498 .mode_set = intel_dp_mode_set,
2499 .disable = intel_encoder_noop,
2500 };
2501
2502 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2503 .dpms = intel_connector_dpms,
2504 .detect = intel_dp_detect,
2505 .fill_modes = drm_helper_probe_single_connector_modes,
2506 .set_property = intel_dp_set_property,
2507 .destroy = intel_dp_destroy,
2508 };
2509
2510 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2511 .get_modes = intel_dp_get_modes,
2512 .mode_valid = intel_dp_mode_valid,
2513 .best_encoder = intel_best_encoder,
2514 };
2515
2516 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2517 .destroy = intel_dp_encoder_destroy,
2518 };
2519
2520 static void
2521 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2522 {
2523 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2524
2525 intel_dp_check_link_status(intel_dp);
2526 }
2527
2528 /* Return which DP Port should be selected for Transcoder DP control */
2529 int
2530 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2531 {
2532 struct drm_device *dev = crtc->dev;
2533 struct intel_encoder *encoder;
2534
2535 for_each_encoder_on_crtc(dev, crtc, encoder) {
2536 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2537
2538 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2539 intel_dp->base.type == INTEL_OUTPUT_EDP)
2540 return intel_dp->output_reg;
2541 }
2542
2543 return -1;
2544 }
2545
2546 /* check the VBT to see whether the eDP is on DP-D port */
2547 bool intel_dpd_is_edp(struct drm_device *dev)
2548 {
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550 struct child_device_config *p_child;
2551 int i;
2552
2553 if (!dev_priv->child_dev_num)
2554 return false;
2555
2556 for (i = 0; i < dev_priv->child_dev_num; i++) {
2557 p_child = dev_priv->child_dev + i;
2558
2559 if (p_child->dvo_port == PORT_IDPD &&
2560 p_child->device_type == DEVICE_TYPE_eDP)
2561 return true;
2562 }
2563 return false;
2564 }
2565
2566 static void
2567 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2568 {
2569 intel_attach_force_audio_property(connector);
2570 intel_attach_broadcast_rgb_property(connector);
2571 }
2572
2573 void
2574 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2575 {
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577 struct drm_connector *connector;
2578 struct intel_dp *intel_dp;
2579 struct intel_encoder *intel_encoder;
2580 struct intel_connector *intel_connector;
2581 const char *name = NULL;
2582 int type;
2583
2584 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2585 if (!intel_dp)
2586 return;
2587
2588 intel_dp->output_reg = output_reg;
2589 intel_dp->port = port;
2590 /* Preserve the current hw state. */
2591 intel_dp->DP = I915_READ(intel_dp->output_reg);
2592
2593 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2594 if (!intel_connector) {
2595 kfree(intel_dp);
2596 return;
2597 }
2598 intel_encoder = &intel_dp->base;
2599
2600 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2601 if (intel_dpd_is_edp(dev))
2602 intel_dp->is_pch_edp = true;
2603
2604 /*
2605 * FIXME : We need to initialize built-in panels before external panels.
2606 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2607 */
2608 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2609 type = DRM_MODE_CONNECTOR_eDP;
2610 intel_encoder->type = INTEL_OUTPUT_EDP;
2611 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2612 type = DRM_MODE_CONNECTOR_eDP;
2613 intel_encoder->type = INTEL_OUTPUT_EDP;
2614 } else {
2615 type = DRM_MODE_CONNECTOR_DisplayPort;
2616 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2617 }
2618
2619 connector = &intel_connector->base;
2620 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2621 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2622
2623 connector->polled = DRM_CONNECTOR_POLL_HPD;
2624
2625 intel_encoder->cloneable = false;
2626
2627 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2628 ironlake_panel_vdd_work);
2629
2630 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2631
2632 connector->interlace_allowed = true;
2633 connector->doublescan_allowed = 0;
2634
2635 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2636 DRM_MODE_ENCODER_TMDS);
2637 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2638
2639 intel_connector_attach_encoder(intel_connector, intel_encoder);
2640 drm_sysfs_connector_add(connector);
2641
2642 intel_encoder->enable = intel_enable_dp;
2643 intel_encoder->pre_enable = intel_pre_enable_dp;
2644 intel_encoder->disable = intel_disable_dp;
2645 intel_encoder->post_disable = intel_post_disable_dp;
2646 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2647 intel_connector->get_hw_state = intel_connector_get_hw_state;
2648
2649 /* Set up the DDC bus. */
2650 switch (port) {
2651 case PORT_A:
2652 name = "DPDDC-A";
2653 break;
2654 case PORT_B:
2655 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2656 name = "DPDDC-B";
2657 break;
2658 case PORT_C:
2659 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2660 name = "DPDDC-C";
2661 break;
2662 case PORT_D:
2663 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2664 name = "DPDDC-D";
2665 break;
2666 default:
2667 WARN(1, "Invalid port %c\n", port_name(port));
2668 break;
2669 }
2670
2671 /* Cache some DPCD data in the eDP case */
2672 if (is_edp(intel_dp)) {
2673 struct edp_power_seq cur, vbt;
2674 u32 pp_on, pp_off, pp_div;
2675
2676 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2677 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2678 pp_div = I915_READ(PCH_PP_DIVISOR);
2679
2680 if (!pp_on || !pp_off || !pp_div) {
2681 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2682 intel_dp_encoder_destroy(&intel_dp->base.base);
2683 intel_dp_destroy(&intel_connector->base);
2684 return;
2685 }
2686
2687 /* Pull timing values out of registers */
2688 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2689 PANEL_POWER_UP_DELAY_SHIFT;
2690
2691 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2692 PANEL_LIGHT_ON_DELAY_SHIFT;
2693
2694 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2695 PANEL_LIGHT_OFF_DELAY_SHIFT;
2696
2697 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2698 PANEL_POWER_DOWN_DELAY_SHIFT;
2699
2700 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2701 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2702
2703 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2704 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2705
2706 vbt = dev_priv->edp.pps;
2707
2708 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2709 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2710
2711 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2712
2713 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2714 intel_dp->backlight_on_delay = get_delay(t8);
2715 intel_dp->backlight_off_delay = get_delay(t9);
2716 intel_dp->panel_power_down_delay = get_delay(t10);
2717 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2718
2719 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2720 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2721 intel_dp->panel_power_cycle_delay);
2722
2723 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2724 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2725 }
2726
2727 intel_dp_i2c_init(intel_dp, intel_connector, name);
2728
2729 if (is_edp(intel_dp)) {
2730 bool ret;
2731 struct edid *edid;
2732
2733 ironlake_edp_panel_vdd_on(intel_dp);
2734 ret = intel_dp_get_dpcd(intel_dp);
2735 ironlake_edp_panel_vdd_off(intel_dp, false);
2736
2737 if (ret) {
2738 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2739 dev_priv->no_aux_handshake =
2740 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2741 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2742 } else {
2743 /* if this fails, presume the device is a ghost */
2744 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2745 intel_dp_encoder_destroy(&intel_dp->base.base);
2746 intel_dp_destroy(&intel_connector->base);
2747 return;
2748 }
2749
2750 ironlake_edp_panel_vdd_on(intel_dp);
2751 edid = drm_get_edid(connector, &intel_dp->adapter);
2752 if (edid) {
2753 drm_mode_connector_update_edid_property(connector,
2754 edid);
2755 intel_dp->edid_mode_count =
2756 drm_add_edid_modes(connector, edid);
2757 drm_edid_to_eld(connector, edid);
2758 intel_dp->edid = edid;
2759 }
2760 ironlake_edp_panel_vdd_off(intel_dp, false);
2761 }
2762
2763 intel_encoder->hot_plug = intel_dp_hot_plug;
2764
2765 if (is_edp(intel_dp)) {
2766 dev_priv->int_edp_connector = connector;
2767 intel_panel_setup_backlight(dev);
2768 }
2769
2770 intel_dp_add_properties(intel_dp, connector);
2771
2772 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2773 * 0xd. Failure to do so will result in spurious interrupts being
2774 * generated on the port when a cable is not attached.
2775 */
2776 if (IS_G4X(dev) && !IS_GM45(dev)) {
2777 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2778 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2779 }
2780 }
Linux kernel - Deliverables
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