2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
116 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
119 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
121 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
122 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
124 switch (max_link_bw
) {
125 case DP_LINK_BW_1_62
:
128 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
129 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
130 INTEL_INFO(dev
)->gen
>= 8) &&
131 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
132 max_link_bw
= DP_LINK_BW_5_4
;
134 max_link_bw
= DP_LINK_BW_2_7
;
137 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
139 max_link_bw
= DP_LINK_BW_1_62
;
145 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
147 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
148 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
149 u8 source_max
, sink_max
;
152 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
153 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
156 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
158 return min(source_max
, sink_max
);
162 * The units on the numbers in the next two are... bizarre. Examples will
163 * make it clearer; this one parallels an example in the eDP spec.
165 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
167 * 270000 * 1 * 8 / 10 == 216000
169 * The actual data capacity of that configuration is 2.16Gbit/s, so the
170 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
171 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
172 * 119000. At 18bpp that's 2142000 kilobits per second.
174 * Thus the strange-looking division by 10 in intel_dp_link_required, to
175 * get the result in decakilobits instead of kilobits.
179 intel_dp_link_required(int pixel_clock
, int bpp
)
181 return (pixel_clock
* bpp
+ 9) / 10;
185 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
187 return (max_link_clock
* max_lanes
* 8) / 10;
190 static enum drm_mode_status
191 intel_dp_mode_valid(struct drm_connector
*connector
,
192 struct drm_display_mode
*mode
)
194 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
195 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
196 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
197 int target_clock
= mode
->clock
;
198 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
200 if (is_edp(intel_dp
) && fixed_mode
) {
201 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
204 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
207 target_clock
= fixed_mode
->clock
;
210 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
211 max_lanes
= intel_dp_max_lane_count(intel_dp
);
213 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
214 mode_rate
= intel_dp_link_required(target_clock
, 18);
216 if (mode_rate
> max_rate
)
217 return MODE_CLOCK_HIGH
;
219 if (mode
->clock
< 10000)
220 return MODE_CLOCK_LOW
;
222 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
223 return MODE_H_ILLEGAL
;
229 pack_aux(const uint8_t *src
, int src_bytes
)
236 for (i
= 0; i
< src_bytes
; i
++)
237 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
242 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
247 for (i
= 0; i
< dst_bytes
; i
++)
248 dst
[i
] = src
>> ((3-i
) * 8);
251 /* hrawclock is 1/4 the FSB frequency */
253 intel_hrawclk(struct drm_device
*dev
)
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev
))
262 clkcfg
= I915_READ(CLKCFG
);
263 switch (clkcfg
& CLKCFG_FSB_MASK
) {
272 case CLKCFG_FSB_1067
:
274 case CLKCFG_FSB_1333
:
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600
:
278 case CLKCFG_FSB_1600_ALT
:
286 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
287 struct intel_dp
*intel_dp
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
);
292 static void pps_lock(struct intel_dp
*intel_dp
)
294 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
295 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
296 struct drm_device
*dev
= encoder
->base
.dev
;
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 enum intel_display_power_domain power_domain
;
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
304 power_domain
= intel_display_port_power_domain(encoder
);
305 intel_display_power_get(dev_priv
, power_domain
);
307 mutex_lock(&dev_priv
->pps_mutex
);
310 static void pps_unlock(struct intel_dp
*intel_dp
)
312 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
313 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
314 struct drm_device
*dev
= encoder
->base
.dev
;
315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 enum intel_display_power_domain power_domain
;
318 mutex_unlock(&dev_priv
->pps_mutex
);
320 power_domain
= intel_display_port_power_domain(encoder
);
321 intel_display_power_put(dev_priv
, power_domain
);
325 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
327 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
328 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
330 enum pipe pipe
= intel_dp
->pps_pipe
;
333 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
334 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
335 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
338 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
339 pipe_name(pipe
), port_name(intel_dig_port
->port
));
341 /* Preserve the BIOS-computed detected bit. This is
342 * supposed to be read-only.
344 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
345 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
346 DP
|= DP_PORT_WIDTH(1);
347 DP
|= DP_LINK_TRAIN_PAT_1
;
349 if (IS_CHERRYVIEW(dev
))
350 DP
|= DP_PIPE_SELECT_CHV(pipe
);
351 else if (pipe
== PIPE_B
)
352 DP
|= DP_PIPEB_SELECT
;
355 * Similar magic as in intel_dp_enable_port().
356 * We _must_ do this port enable + disable trick
357 * to make this power seqeuencer lock onto the port.
358 * Otherwise even VDD force bit won't work.
360 I915_WRITE(intel_dp
->output_reg
, DP
);
361 POSTING_READ(intel_dp
->output_reg
);
363 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
364 POSTING_READ(intel_dp
->output_reg
);
366 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
367 POSTING_READ(intel_dp
->output_reg
);
371 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
373 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
374 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
376 struct intel_encoder
*encoder
;
377 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
379 lockdep_assert_held(&dev_priv
->pps_mutex
);
381 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
382 return intel_dp
->pps_pipe
;
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
388 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
390 struct intel_dp
*tmp
;
392 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
395 tmp
= enc_to_intel_dp(&encoder
->base
);
397 if (tmp
->pps_pipe
!= INVALID_PIPE
)
398 pipes
&= ~(1 << tmp
->pps_pipe
);
402 * Didn't find one. This should not happen since there
403 * are two power sequencers and up to two eDP ports.
405 if (WARN_ON(pipes
== 0))
408 intel_dp
->pps_pipe
= ffs(pipes
) - 1;
410 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
411 pipe_name(intel_dp
->pps_pipe
),
412 port_name(intel_dig_port
->port
));
414 /* init power sequencer on this pipe and port */
415 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
416 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
419 * Even vdd force doesn't work until we've made
420 * the power sequencer lock in on the port.
422 vlv_power_sequencer_kick(intel_dp
);
424 return intel_dp
->pps_pipe
;
427 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
430 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
433 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
436 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
439 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
442 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
449 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
451 vlv_pipe_check pipe_check
)
455 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
456 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
457 PANEL_PORT_SELECT_MASK
;
459 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
462 if (!pipe_check(dev_priv
, pipe
))
472 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
474 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
475 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
477 enum port port
= intel_dig_port
->port
;
479 lockdep_assert_held(&dev_priv
->pps_mutex
);
481 /* try to find a pipe with this port selected */
482 /* first pick one where the panel is on */
483 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
485 /* didn't find one? pick one where vdd is on */
486 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
487 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
488 vlv_pipe_has_vdd_on
);
489 /* didn't find one? pick one with just the correct port */
490 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
491 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
494 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
495 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
496 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
501 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
502 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
504 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
505 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
508 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
510 struct drm_device
*dev
= dev_priv
->dev
;
511 struct intel_encoder
*encoder
;
513 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
517 * We can't grab pps_mutex here due to deadlock with power_domain
518 * mutex when power_domain functions are called while holding pps_mutex.
519 * That also means that in order to use pps_pipe the code needs to
520 * hold both a power domain reference and pps_mutex, and the power domain
521 * reference get/put must be done while _not_ holding pps_mutex.
522 * pps_{lock,unlock}() do these steps in the correct order, so one
523 * should use them always.
526 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
527 struct intel_dp
*intel_dp
;
529 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
532 intel_dp
= enc_to_intel_dp(&encoder
->base
);
533 intel_dp
->pps_pipe
= INVALID_PIPE
;
537 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
539 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
541 if (HAS_PCH_SPLIT(dev
))
542 return PCH_PP_CONTROL
;
544 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
547 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
549 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
551 if (HAS_PCH_SPLIT(dev
))
552 return PCH_PP_STATUS
;
554 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
557 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
558 This function only applicable when panel PM state is not to be tracked */
559 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
562 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
564 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
567 u32 pp_ctrl_reg
, pp_div_reg
;
569 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
574 if (IS_VALLEYVIEW(dev
)) {
575 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
577 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
578 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
579 pp_div
= I915_READ(pp_div_reg
);
580 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
582 /* 0x1F write to PP_DIV_REG sets max cycle delay */
583 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
584 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
585 msleep(intel_dp
->panel_power_cycle_delay
);
588 pps_unlock(intel_dp
);
593 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
595 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
598 lockdep_assert_held(&dev_priv
->pps_mutex
);
600 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
603 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
605 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
608 lockdep_assert_held(&dev_priv
->pps_mutex
);
610 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
614 intel_dp_check_edp(struct intel_dp
*intel_dp
)
616 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
619 if (!is_edp(intel_dp
))
622 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
623 WARN(1, "eDP powered off while attempting aux channel communication.\n");
624 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
625 I915_READ(_pp_stat_reg(intel_dp
)),
626 I915_READ(_pp_ctrl_reg(intel_dp
)));
631 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
633 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
634 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
636 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
640 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
642 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
643 msecs_to_jiffies_timeout(10));
645 done
= wait_for_atomic(C
, 10) == 0;
647 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
654 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
656 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
657 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
660 * The clock divider is based off the hrawclk, and would like to run at
661 * 2MHz. So, take the hrawclk value and divide by 2 and use that
663 return index
? 0 : intel_hrawclk(dev
) / 2;
666 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
668 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
669 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
674 if (intel_dig_port
->port
== PORT_A
) {
675 if (IS_GEN6(dev
) || IS_GEN7(dev
))
676 return 200; /* SNB & IVB eDP input clock at 400Mhz */
678 return 225; /* eDP input clock at 450Mhz */
680 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
684 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
686 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
687 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
690 if (intel_dig_port
->port
== PORT_A
) {
693 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
694 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
695 /* Workaround for non-ULT HSW */
702 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
706 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
708 return index
? 0 : 100;
711 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
714 * SKL doesn't need us to program the AUX clock divider (Hardware will
715 * derive the clock from CDCLK automatically). We still implement the
716 * get_aux_clock_divider vfunc to plug-in into the existing code.
718 return index
? 0 : 1;
721 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
724 uint32_t aux_clock_divider
)
726 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
727 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
728 uint32_t precharge
, timeout
;
735 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
736 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
738 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
740 return DP_AUX_CH_CTL_SEND_BUSY
|
742 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
743 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
745 DP_AUX_CH_CTL_RECEIVE_ERROR
|
746 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
747 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
748 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
751 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
756 return DP_AUX_CH_CTL_SEND_BUSY
|
758 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
759 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
760 DP_AUX_CH_CTL_TIME_OUT_1600us
|
761 DP_AUX_CH_CTL_RECEIVE_ERROR
|
762 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
763 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
767 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
768 const uint8_t *send
, int send_bytes
,
769 uint8_t *recv
, int recv_size
)
771 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
772 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
774 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
775 uint32_t ch_data
= ch_ctl
+ 4;
776 uint32_t aux_clock_divider
;
777 int i
, ret
, recv_bytes
;
780 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
786 * We will be called with VDD already enabled for dpcd/edid/oui reads.
787 * In such cases we want to leave VDD enabled and it's up to upper layers
788 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
791 vdd
= edp_panel_vdd_on(intel_dp
);
793 /* dp aux is extremely sensitive to irq latency, hence request the
794 * lowest possible wakeup latency and so prevent the cpu from going into
797 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
799 intel_dp_check_edp(intel_dp
);
801 intel_aux_display_runtime_get(dev_priv
);
803 /* Try to wait for any previous AUX channel activity */
804 for (try = 0; try < 3; try++) {
805 status
= I915_READ_NOTRACE(ch_ctl
);
806 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
812 WARN(1, "dp_aux_ch not started status 0x%08x\n",
818 /* Only 5 data registers! */
819 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
824 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
825 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
830 /* Must try at least 3 times according to DP spec */
831 for (try = 0; try < 5; try++) {
832 /* Load the send data into the aux channel data registers */
833 for (i
= 0; i
< send_bytes
; i
+= 4)
834 I915_WRITE(ch_data
+ i
,
835 pack_aux(send
+ i
, send_bytes
- i
));
837 /* Send the command and wait for it to complete */
838 I915_WRITE(ch_ctl
, send_ctl
);
840 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
842 /* Clear done status and any errors */
846 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
847 DP_AUX_CH_CTL_RECEIVE_ERROR
);
849 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
850 DP_AUX_CH_CTL_RECEIVE_ERROR
))
852 if (status
& DP_AUX_CH_CTL_DONE
)
855 if (status
& DP_AUX_CH_CTL_DONE
)
859 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
860 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
865 /* Check for timeout or receive error.
866 * Timeouts occur when the sink is not connected
868 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
869 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
874 /* Timeouts occur when the device isn't connected, so they're
875 * "normal" -- don't fill the kernel log with these */
876 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
877 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
882 /* Unload any bytes sent back from the other side */
883 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
884 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
885 if (recv_bytes
> recv_size
)
886 recv_bytes
= recv_size
;
888 for (i
= 0; i
< recv_bytes
; i
+= 4)
889 unpack_aux(I915_READ(ch_data
+ i
),
890 recv
+ i
, recv_bytes
- i
);
894 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
895 intel_aux_display_runtime_put(dev_priv
);
898 edp_panel_vdd_off(intel_dp
, false);
900 pps_unlock(intel_dp
);
905 #define BARE_ADDRESS_SIZE 3
906 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
908 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
910 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
911 uint8_t txbuf
[20], rxbuf
[20];
912 size_t txsize
, rxsize
;
915 txbuf
[0] = msg
->request
<< 4;
916 txbuf
[1] = msg
->address
>> 8;
917 txbuf
[2] = msg
->address
& 0xff;
918 txbuf
[3] = msg
->size
- 1;
920 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
921 case DP_AUX_NATIVE_WRITE
:
922 case DP_AUX_I2C_WRITE
:
923 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
926 if (WARN_ON(txsize
> 20))
929 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
931 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
933 msg
->reply
= rxbuf
[0] >> 4;
935 /* Return payload size. */
940 case DP_AUX_NATIVE_READ
:
941 case DP_AUX_I2C_READ
:
942 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
943 rxsize
= msg
->size
+ 1;
945 if (WARN_ON(rxsize
> 20))
948 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
950 msg
->reply
= rxbuf
[0] >> 4;
952 * Assume happy day, and copy the data. The caller is
953 * expected to check msg->reply before touching it.
955 * Return payload size.
958 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
971 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
973 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
974 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
975 enum port port
= intel_dig_port
->port
;
976 const char *name
= NULL
;
981 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
985 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
989 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
993 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1001 * The AUX_CTL register is usually DP_CTL + 0x10.
1003 * On Haswell and Broadwell though:
1004 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1005 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1007 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1009 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1010 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1012 intel_dp
->aux
.name
= name
;
1013 intel_dp
->aux
.dev
= dev
->dev
;
1014 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1016 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1017 connector
->base
.kdev
->kobj
.name
);
1019 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1021 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1026 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1027 &intel_dp
->aux
.ddc
.dev
.kobj
,
1028 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1030 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1031 drm_dp_aux_unregister(&intel_dp
->aux
);
1036 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1038 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1040 if (!intel_connector
->mst_port
)
1041 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1042 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1043 intel_connector_unregister(intel_connector
);
1047 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
1050 case DP_LINK_BW_1_62
:
1051 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1053 case DP_LINK_BW_2_7
:
1054 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1056 case DP_LINK_BW_5_4
:
1057 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1063 intel_dp_set_clock(struct intel_encoder
*encoder
,
1064 struct intel_crtc_config
*pipe_config
, int link_bw
)
1066 struct drm_device
*dev
= encoder
->base
.dev
;
1067 const struct dp_link_dpll
*divisor
= NULL
;
1071 divisor
= gen4_dpll
;
1072 count
= ARRAY_SIZE(gen4_dpll
);
1073 } else if (HAS_PCH_SPLIT(dev
)) {
1075 count
= ARRAY_SIZE(pch_dpll
);
1076 } else if (IS_CHERRYVIEW(dev
)) {
1078 count
= ARRAY_SIZE(chv_dpll
);
1079 } else if (IS_VALLEYVIEW(dev
)) {
1081 count
= ARRAY_SIZE(vlv_dpll
);
1084 if (divisor
&& count
) {
1085 for (i
= 0; i
< count
; i
++) {
1086 if (link_bw
== divisor
[i
].link_bw
) {
1087 pipe_config
->dpll
= divisor
[i
].dpll
;
1088 pipe_config
->clock_set
= true;
1096 intel_dp_compute_config(struct intel_encoder
*encoder
,
1097 struct intel_crtc_config
*pipe_config
)
1099 struct drm_device
*dev
= encoder
->base
.dev
;
1100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1101 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1102 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1103 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1104 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1105 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1106 int lane_count
, clock
;
1107 int min_lane_count
= 1;
1108 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1109 /* Conveniently, the link BW constants become indices with a shift...*/
1111 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1113 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1114 int link_avail
, link_clock
;
1116 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1117 pipe_config
->has_pch_encoder
= true;
1119 pipe_config
->has_dp_encoder
= true;
1120 pipe_config
->has_drrs
= false;
1121 pipe_config
->has_audio
= intel_dp
->has_audio
;
1123 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1124 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1126 if (!HAS_PCH_SPLIT(dev
))
1127 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1128 intel_connector
->panel
.fitting_mode
);
1130 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1131 intel_connector
->panel
.fitting_mode
);
1134 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1137 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1138 "max bw %02x pixel clock %iKHz\n",
1139 max_lane_count
, bws
[max_clock
],
1140 adjusted_mode
->crtc_clock
);
1142 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1143 * bpc in between. */
1144 bpp
= pipe_config
->pipe_bpp
;
1145 if (is_edp(intel_dp
)) {
1146 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1147 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1148 dev_priv
->vbt
.edp_bpp
);
1149 bpp
= dev_priv
->vbt
.edp_bpp
;
1153 * Use the maximum clock and number of lanes the eDP panel
1154 * advertizes being capable of. The panels are generally
1155 * designed to support only a single clock and lane
1156 * configuration, and typically these values correspond to the
1157 * native resolution of the panel.
1159 min_lane_count
= max_lane_count
;
1160 min_clock
= max_clock
;
1163 for (; bpp
>= 6*3; bpp
-= 2*3) {
1164 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1167 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1168 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1169 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1170 link_avail
= intel_dp_max_data_rate(link_clock
,
1173 if (mode_rate
<= link_avail
) {
1183 if (intel_dp
->color_range_auto
) {
1186 * CEA-861-E - 5.1 Default Encoding Parameters
1187 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1189 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1190 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1192 intel_dp
->color_range
= 0;
1195 if (intel_dp
->color_range
)
1196 pipe_config
->limited_color_range
= true;
1198 intel_dp
->link_bw
= bws
[clock
];
1199 intel_dp
->lane_count
= lane_count
;
1200 pipe_config
->pipe_bpp
= bpp
;
1201 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1203 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1204 intel_dp
->link_bw
, intel_dp
->lane_count
,
1205 pipe_config
->port_clock
, bpp
);
1206 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1207 mode_rate
, link_avail
);
1209 intel_link_compute_m_n(bpp
, lane_count
,
1210 adjusted_mode
->crtc_clock
,
1211 pipe_config
->port_clock
,
1212 &pipe_config
->dp_m_n
);
1214 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1215 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1216 pipe_config
->has_drrs
= true;
1217 intel_link_compute_m_n(bpp
, lane_count
,
1218 intel_connector
->panel
.downclock_mode
->clock
,
1219 pipe_config
->port_clock
,
1220 &pipe_config
->dp_m2_n2
);
1223 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1224 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1226 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1231 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1233 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1234 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1235 struct drm_device
*dev
= crtc
->base
.dev
;
1236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1239 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1240 dpa_ctl
= I915_READ(DP_A
);
1241 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1243 if (crtc
->config
.port_clock
== 162000) {
1244 /* For a long time we've carried around a ILK-DevA w/a for the
1245 * 160MHz clock. If we're really unlucky, it's still required.
1247 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1248 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1249 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1251 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1252 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1255 I915_WRITE(DP_A
, dpa_ctl
);
1261 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1263 struct drm_device
*dev
= encoder
->base
.dev
;
1264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1265 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1266 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1267 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1268 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1271 * There are four kinds of DP registers:
1278 * IBX PCH and CPU are the same for almost everything,
1279 * except that the CPU DP PLL is configured in this
1282 * CPT PCH is quite different, having many bits moved
1283 * to the TRANS_DP_CTL register instead. That
1284 * configuration happens (oddly) in ironlake_pch_enable
1287 /* Preserve the BIOS-computed detected bit. This is
1288 * supposed to be read-only.
1290 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1292 /* Handle DP bits in common between all three register formats */
1293 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1294 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1296 if (crtc
->config
.has_audio
) {
1297 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1298 pipe_name(crtc
->pipe
));
1299 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1300 intel_write_eld(encoder
);
1303 /* Split out the IBX/CPU vs CPT settings */
1305 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1306 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1307 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1308 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1309 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1310 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1312 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1313 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1315 intel_dp
->DP
|= crtc
->pipe
<< 29;
1316 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1317 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1318 intel_dp
->DP
|= intel_dp
->color_range
;
1320 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1321 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1322 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1323 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1324 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1326 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1327 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1329 if (!IS_CHERRYVIEW(dev
)) {
1330 if (crtc
->pipe
== 1)
1331 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1333 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1336 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1340 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1341 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1343 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1344 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1346 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1347 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1349 static void wait_panel_status(struct intel_dp
*intel_dp
,
1353 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1355 u32 pp_stat_reg
, pp_ctrl_reg
;
1357 lockdep_assert_held(&dev_priv
->pps_mutex
);
1359 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1360 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1362 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1364 I915_READ(pp_stat_reg
),
1365 I915_READ(pp_ctrl_reg
));
1367 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1368 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1369 I915_READ(pp_stat_reg
),
1370 I915_READ(pp_ctrl_reg
));
1373 DRM_DEBUG_KMS("Wait complete\n");
1376 static void wait_panel_on(struct intel_dp
*intel_dp
)
1378 DRM_DEBUG_KMS("Wait for panel power on\n");
1379 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1382 static void wait_panel_off(struct intel_dp
*intel_dp
)
1384 DRM_DEBUG_KMS("Wait for panel power off time\n");
1385 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1388 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1390 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1392 /* When we disable the VDD override bit last we have to do the manual
1394 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1395 intel_dp
->panel_power_cycle_delay
);
1397 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1400 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1402 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1403 intel_dp
->backlight_on_delay
);
1406 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1408 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1409 intel_dp
->backlight_off_delay
);
1412 /* Read the current pp_control value, unlocking the register if it
1416 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1418 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1422 lockdep_assert_held(&dev_priv
->pps_mutex
);
1424 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1425 control
&= ~PANEL_UNLOCK_MASK
;
1426 control
|= PANEL_UNLOCK_REGS
;
1431 * Must be paired with edp_panel_vdd_off().
1432 * Must hold pps_mutex around the whole on/off sequence.
1433 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1435 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1437 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1438 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1439 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1441 enum intel_display_power_domain power_domain
;
1443 u32 pp_stat_reg
, pp_ctrl_reg
;
1444 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1446 lockdep_assert_held(&dev_priv
->pps_mutex
);
1448 if (!is_edp(intel_dp
))
1451 intel_dp
->want_panel_vdd
= true;
1453 if (edp_have_panel_vdd(intel_dp
))
1454 return need_to_disable
;
1456 power_domain
= intel_display_port_power_domain(intel_encoder
);
1457 intel_display_power_get(dev_priv
, power_domain
);
1459 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1461 if (!edp_have_panel_power(intel_dp
))
1462 wait_panel_power_cycle(intel_dp
);
1464 pp
= ironlake_get_pp_control(intel_dp
);
1465 pp
|= EDP_FORCE_VDD
;
1467 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1468 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1470 I915_WRITE(pp_ctrl_reg
, pp
);
1471 POSTING_READ(pp_ctrl_reg
);
1472 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1473 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1475 * If the panel wasn't on, delay before accessing aux channel
1477 if (!edp_have_panel_power(intel_dp
)) {
1478 DRM_DEBUG_KMS("eDP was not running\n");
1479 msleep(intel_dp
->panel_power_up_delay
);
1482 return need_to_disable
;
1486 * Must be paired with intel_edp_panel_vdd_off() or
1487 * intel_edp_panel_off().
1488 * Nested calls to these functions are not allowed since
1489 * we drop the lock. Caller must use some higher level
1490 * locking to prevent nested calls from other threads.
1492 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1496 if (!is_edp(intel_dp
))
1500 vdd
= edp_panel_vdd_on(intel_dp
);
1501 pps_unlock(intel_dp
);
1503 WARN(!vdd
, "eDP VDD already requested on\n");
1506 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1508 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 struct intel_digital_port
*intel_dig_port
=
1511 dp_to_dig_port(intel_dp
);
1512 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1513 enum intel_display_power_domain power_domain
;
1515 u32 pp_stat_reg
, pp_ctrl_reg
;
1517 lockdep_assert_held(&dev_priv
->pps_mutex
);
1519 WARN_ON(intel_dp
->want_panel_vdd
);
1521 if (!edp_have_panel_vdd(intel_dp
))
1524 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1526 pp
= ironlake_get_pp_control(intel_dp
);
1527 pp
&= ~EDP_FORCE_VDD
;
1529 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1530 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1532 I915_WRITE(pp_ctrl_reg
, pp
);
1533 POSTING_READ(pp_ctrl_reg
);
1535 /* Make sure sequencer is idle before allowing subsequent activity */
1536 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1537 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1539 if ((pp
& POWER_TARGET_ON
) == 0)
1540 intel_dp
->last_power_cycle
= jiffies
;
1542 power_domain
= intel_display_port_power_domain(intel_encoder
);
1543 intel_display_power_put(dev_priv
, power_domain
);
1546 static void edp_panel_vdd_work(struct work_struct
*__work
)
1548 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1549 struct intel_dp
, panel_vdd_work
);
1552 if (!intel_dp
->want_panel_vdd
)
1553 edp_panel_vdd_off_sync(intel_dp
);
1554 pps_unlock(intel_dp
);
1557 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1559 unsigned long delay
;
1562 * Queue the timer to fire a long time from now (relative to the power
1563 * down delay) to keep the panel power up across a sequence of
1566 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1567 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1571 * Must be paired with edp_panel_vdd_on().
1572 * Must hold pps_mutex around the whole on/off sequence.
1573 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1575 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1577 struct drm_i915_private
*dev_priv
=
1578 intel_dp_to_dev(intel_dp
)->dev_private
;
1580 lockdep_assert_held(&dev_priv
->pps_mutex
);
1582 if (!is_edp(intel_dp
))
1585 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1587 intel_dp
->want_panel_vdd
= false;
1590 edp_panel_vdd_off_sync(intel_dp
);
1592 edp_panel_vdd_schedule_off(intel_dp
);
1595 static void edp_panel_on(struct intel_dp
*intel_dp
)
1597 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1602 lockdep_assert_held(&dev_priv
->pps_mutex
);
1604 if (!is_edp(intel_dp
))
1607 DRM_DEBUG_KMS("Turn eDP power on\n");
1609 if (edp_have_panel_power(intel_dp
)) {
1610 DRM_DEBUG_KMS("eDP power already on\n");
1614 wait_panel_power_cycle(intel_dp
);
1616 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1617 pp
= ironlake_get_pp_control(intel_dp
);
1619 /* ILK workaround: disable reset around power sequence */
1620 pp
&= ~PANEL_POWER_RESET
;
1621 I915_WRITE(pp_ctrl_reg
, pp
);
1622 POSTING_READ(pp_ctrl_reg
);
1625 pp
|= POWER_TARGET_ON
;
1627 pp
|= PANEL_POWER_RESET
;
1629 I915_WRITE(pp_ctrl_reg
, pp
);
1630 POSTING_READ(pp_ctrl_reg
);
1632 wait_panel_on(intel_dp
);
1633 intel_dp
->last_power_on
= jiffies
;
1636 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1637 I915_WRITE(pp_ctrl_reg
, pp
);
1638 POSTING_READ(pp_ctrl_reg
);
1642 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1644 if (!is_edp(intel_dp
))
1648 edp_panel_on(intel_dp
);
1649 pps_unlock(intel_dp
);
1653 static void edp_panel_off(struct intel_dp
*intel_dp
)
1655 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1656 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1657 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1659 enum intel_display_power_domain power_domain
;
1663 lockdep_assert_held(&dev_priv
->pps_mutex
);
1665 if (!is_edp(intel_dp
))
1668 DRM_DEBUG_KMS("Turn eDP power off\n");
1670 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1672 pp
= ironlake_get_pp_control(intel_dp
);
1673 /* We need to switch off panel power _and_ force vdd, for otherwise some
1674 * panels get very unhappy and cease to work. */
1675 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1678 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1680 intel_dp
->want_panel_vdd
= false;
1682 I915_WRITE(pp_ctrl_reg
, pp
);
1683 POSTING_READ(pp_ctrl_reg
);
1685 intel_dp
->last_power_cycle
= jiffies
;
1686 wait_panel_off(intel_dp
);
1688 /* We got a reference when we enabled the VDD. */
1689 power_domain
= intel_display_port_power_domain(intel_encoder
);
1690 intel_display_power_put(dev_priv
, power_domain
);
1693 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1695 if (!is_edp(intel_dp
))
1699 edp_panel_off(intel_dp
);
1700 pps_unlock(intel_dp
);
1703 /* Enable backlight in the panel power control. */
1704 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1706 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1707 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1713 * If we enable the backlight right away following a panel power
1714 * on, we may see slight flicker as the panel syncs with the eDP
1715 * link. So delay a bit to make sure the image is solid before
1716 * allowing it to appear.
1718 wait_backlight_on(intel_dp
);
1722 pp
= ironlake_get_pp_control(intel_dp
);
1723 pp
|= EDP_BLC_ENABLE
;
1725 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1727 I915_WRITE(pp_ctrl_reg
, pp
);
1728 POSTING_READ(pp_ctrl_reg
);
1730 pps_unlock(intel_dp
);
1733 /* Enable backlight PWM and backlight PP control. */
1734 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1736 if (!is_edp(intel_dp
))
1739 DRM_DEBUG_KMS("\n");
1741 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1742 _intel_edp_backlight_on(intel_dp
);
1745 /* Disable backlight in the panel power control. */
1746 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1748 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1753 if (!is_edp(intel_dp
))
1758 pp
= ironlake_get_pp_control(intel_dp
);
1759 pp
&= ~EDP_BLC_ENABLE
;
1761 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1763 I915_WRITE(pp_ctrl_reg
, pp
);
1764 POSTING_READ(pp_ctrl_reg
);
1766 pps_unlock(intel_dp
);
1768 intel_dp
->last_backlight_off
= jiffies
;
1769 edp_wait_backlight_off(intel_dp
);
1772 /* Disable backlight PP control and backlight PWM. */
1773 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1775 if (!is_edp(intel_dp
))
1778 DRM_DEBUG_KMS("\n");
1780 _intel_edp_backlight_off(intel_dp
);
1781 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1785 * Hook for controlling the panel power control backlight through the bl_power
1786 * sysfs attribute. Take care to handle multiple calls.
1788 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1791 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1795 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1796 pps_unlock(intel_dp
);
1798 if (is_enabled
== enable
)
1801 DRM_DEBUG_KMS("panel power control backlight %s\n",
1802 enable
? "enable" : "disable");
1805 _intel_edp_backlight_on(intel_dp
);
1807 _intel_edp_backlight_off(intel_dp
);
1810 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1812 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1813 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1814 struct drm_device
*dev
= crtc
->dev
;
1815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1818 assert_pipe_disabled(dev_priv
,
1819 to_intel_crtc(crtc
)->pipe
);
1821 DRM_DEBUG_KMS("\n");
1822 dpa_ctl
= I915_READ(DP_A
);
1823 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1824 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1826 /* We don't adjust intel_dp->DP while tearing down the link, to
1827 * facilitate link retraining (e.g. after hotplug). Hence clear all
1828 * enable bits here to ensure that we don't enable too much. */
1829 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1830 intel_dp
->DP
|= DP_PLL_ENABLE
;
1831 I915_WRITE(DP_A
, intel_dp
->DP
);
1836 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1838 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1839 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1840 struct drm_device
*dev
= crtc
->dev
;
1841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1844 assert_pipe_disabled(dev_priv
,
1845 to_intel_crtc(crtc
)->pipe
);
1847 dpa_ctl
= I915_READ(DP_A
);
1848 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1849 "dp pll off, should be on\n");
1850 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1852 /* We can't rely on the value tracked for the DP register in
1853 * intel_dp->DP because link_down must not change that (otherwise link
1854 * re-training will fail. */
1855 dpa_ctl
&= ~DP_PLL_ENABLE
;
1856 I915_WRITE(DP_A
, dpa_ctl
);
1861 /* If the sink supports it, try to set the power state appropriately */
1862 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1866 /* Should have a valid DPCD by this point */
1867 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1870 if (mode
!= DRM_MODE_DPMS_ON
) {
1871 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1875 * When turning on, we need to retry for 1ms to give the sink
1878 for (i
= 0; i
< 3; i
++) {
1879 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1888 DRM_DEBUG_KMS("failed to %s sink power state\n",
1889 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1892 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1895 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1896 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1897 struct drm_device
*dev
= encoder
->base
.dev
;
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1899 enum intel_display_power_domain power_domain
;
1902 power_domain
= intel_display_port_power_domain(encoder
);
1903 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1906 tmp
= I915_READ(intel_dp
->output_reg
);
1908 if (!(tmp
& DP_PORT_EN
))
1911 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1912 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1913 } else if (IS_CHERRYVIEW(dev
)) {
1914 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1915 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1916 *pipe
= PORT_TO_PIPE(tmp
);
1922 switch (intel_dp
->output_reg
) {
1924 trans_sel
= TRANS_DP_PORT_SEL_B
;
1927 trans_sel
= TRANS_DP_PORT_SEL_C
;
1930 trans_sel
= TRANS_DP_PORT_SEL_D
;
1936 for_each_pipe(dev_priv
, i
) {
1937 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1938 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1944 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1945 intel_dp
->output_reg
);
1951 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1952 struct intel_crtc_config
*pipe_config
)
1954 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1956 struct drm_device
*dev
= encoder
->base
.dev
;
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1958 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1959 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1962 tmp
= I915_READ(intel_dp
->output_reg
);
1963 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1964 pipe_config
->has_audio
= true;
1966 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1967 if (tmp
& DP_SYNC_HS_HIGH
)
1968 flags
|= DRM_MODE_FLAG_PHSYNC
;
1970 flags
|= DRM_MODE_FLAG_NHSYNC
;
1972 if (tmp
& DP_SYNC_VS_HIGH
)
1973 flags
|= DRM_MODE_FLAG_PVSYNC
;
1975 flags
|= DRM_MODE_FLAG_NVSYNC
;
1977 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1978 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1979 flags
|= DRM_MODE_FLAG_PHSYNC
;
1981 flags
|= DRM_MODE_FLAG_NHSYNC
;
1983 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1984 flags
|= DRM_MODE_FLAG_PVSYNC
;
1986 flags
|= DRM_MODE_FLAG_NVSYNC
;
1989 pipe_config
->adjusted_mode
.flags
|= flags
;
1991 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1992 tmp
& DP_COLOR_RANGE_16_235
)
1993 pipe_config
->limited_color_range
= true;
1995 pipe_config
->has_dp_encoder
= true;
1997 intel_dp_get_m_n(crtc
, pipe_config
);
1999 if (port
== PORT_A
) {
2000 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2001 pipe_config
->port_clock
= 162000;
2003 pipe_config
->port_clock
= 270000;
2006 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2007 &pipe_config
->dp_m_n
);
2009 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2010 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2012 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
2014 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2015 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2017 * This is a big fat ugly hack.
2019 * Some machines in UEFI boot mode provide us a VBT that has 18
2020 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2021 * unknown we fail to light up. Yet the same BIOS boots up with
2022 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2023 * max, not what it tells us to use.
2025 * Note: This will still be broken if the eDP panel is not lit
2026 * up by the BIOS, and thus we can't get the mode at module
2029 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2030 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2031 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2035 static bool is_edp_psr(struct intel_dp
*intel_dp
)
2037 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
2040 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
2042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2047 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2050 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
2051 struct edp_vsc_psr
*vsc_psr
)
2053 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2054 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2056 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
2057 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
2058 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
2059 uint32_t *data
= (uint32_t *) vsc_psr
;
2062 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2063 the video DIP being updated before program video DIP data buffer
2064 registers for DIP being updated. */
2065 I915_WRITE(ctl_reg
, 0);
2066 POSTING_READ(ctl_reg
);
2068 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
2069 if (i
< sizeof(struct edp_vsc_psr
))
2070 I915_WRITE(data_reg
+ i
, *data
++);
2072 I915_WRITE(data_reg
+ i
, 0);
2075 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
2076 POSTING_READ(ctl_reg
);
2079 static void intel_edp_psr_setup_vsc(struct intel_dp
*intel_dp
)
2081 struct edp_vsc_psr psr_vsc
;
2083 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2084 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
2085 psr_vsc
.sdp_header
.HB0
= 0;
2086 psr_vsc
.sdp_header
.HB1
= 0x7;
2087 psr_vsc
.sdp_header
.HB2
= 0x2;
2088 psr_vsc
.sdp_header
.HB3
= 0x8;
2089 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
2092 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
2094 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2095 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2097 uint32_t aux_clock_divider
;
2098 int precharge
= 0x3;
2099 bool only_standby
= false;
2100 static const uint8_t aux_msg
[] = {
2101 [0] = DP_AUX_NATIVE_WRITE
<< 4,
2102 [1] = DP_SET_POWER
>> 8,
2103 [2] = DP_SET_POWER
& 0xff,
2105 [4] = DP_SET_POWER_D0
,
2109 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
2111 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
2113 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2114 only_standby
= true;
2116 /* Enable PSR in sink */
2117 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
2118 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2119 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
2121 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2122 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
2124 /* Setup AUX registers */
2125 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
2126 I915_WRITE(EDP_PSR_AUX_DATA1(dev
) + i
,
2127 pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
2129 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
2130 DP_AUX_CH_CTL_TIME_OUT_400us
|
2131 (sizeof(aux_msg
) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
2132 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
2133 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
2136 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
2138 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2139 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2141 uint32_t max_sleep_time
= 0x1f;
2142 uint32_t idle_frames
= 1;
2144 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
2145 bool only_standby
= false;
2147 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2148 only_standby
= true;
2150 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
2151 val
|= EDP_PSR_LINK_STANDBY
;
2152 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
2153 val
|= EDP_PSR_TP1_TIME_0us
;
2154 val
|= EDP_PSR_SKIP_AUX_EXIT
;
2155 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
2157 val
|= EDP_PSR_LINK_DISABLE
;
2159 I915_WRITE(EDP_PSR_CTL(dev
), val
|
2160 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
2161 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
2162 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
2166 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
2168 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2169 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2171 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
2172 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2174 lockdep_assert_held(&dev_priv
->psr
.lock
);
2175 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
2176 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
2178 dev_priv
->psr
.source_ok
= false;
2180 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
2181 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2185 if (!i915
.enable_psr
) {
2186 DRM_DEBUG_KMS("PSR disable by flag\n");
2190 /* Below limitations aren't valid for Broadwell */
2191 if (IS_BROADWELL(dev
))
2194 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
2196 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2200 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2201 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2206 dev_priv
->psr
.source_ok
= true;
2210 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
2212 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2213 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2216 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2217 WARN_ON(dev_priv
->psr
.active
);
2218 lockdep_assert_held(&dev_priv
->psr
.lock
);
2220 /* Enable/Re-enable PSR on the host */
2221 intel_edp_psr_enable_source(intel_dp
);
2223 dev_priv
->psr
.active
= true;
2226 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
2228 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2231 if (!HAS_PSR(dev
)) {
2232 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2236 if (!is_edp_psr(intel_dp
)) {
2237 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2241 mutex_lock(&dev_priv
->psr
.lock
);
2242 if (dev_priv
->psr
.enabled
) {
2243 DRM_DEBUG_KMS("PSR already in use\n");
2247 if (!intel_edp_psr_match_conditions(intel_dp
))
2250 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
2252 intel_edp_psr_setup_vsc(intel_dp
);
2254 /* Avoid continuous PSR exit by masking memup and hpd */
2255 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
2256 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
2258 /* Enable PSR on the panel */
2259 intel_edp_psr_enable_sink(intel_dp
);
2261 dev_priv
->psr
.enabled
= intel_dp
;
2263 mutex_unlock(&dev_priv
->psr
.lock
);
2266 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
2268 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2271 mutex_lock(&dev_priv
->psr
.lock
);
2272 if (!dev_priv
->psr
.enabled
) {
2273 mutex_unlock(&dev_priv
->psr
.lock
);
2277 if (dev_priv
->psr
.active
) {
2278 I915_WRITE(EDP_PSR_CTL(dev
),
2279 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
2281 /* Wait till PSR is idle */
2282 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
2283 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
2284 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2286 dev_priv
->psr
.active
= false;
2288 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2291 dev_priv
->psr
.enabled
= NULL
;
2292 mutex_unlock(&dev_priv
->psr
.lock
);
2294 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
2297 static void intel_edp_psr_work(struct work_struct
*work
)
2299 struct drm_i915_private
*dev_priv
=
2300 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
2301 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
2303 /* We have to make sure PSR is ready for re-enable
2304 * otherwise it keeps disabled until next full enable/disable cycle.
2305 * PSR might take some time to get fully disabled
2306 * and be ready for re-enable.
2308 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv
->dev
)) &
2309 EDP_PSR_STATUS_STATE_MASK
) == 0, 50)) {
2310 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2314 mutex_lock(&dev_priv
->psr
.lock
);
2315 intel_dp
= dev_priv
->psr
.enabled
;
2321 * The delayed work can race with an invalidate hence we need to
2322 * recheck. Since psr_flush first clears this and then reschedules we
2323 * won't ever miss a flush when bailing out here.
2325 if (dev_priv
->psr
.busy_frontbuffer_bits
)
2328 intel_edp_psr_do_enable(intel_dp
);
2330 mutex_unlock(&dev_priv
->psr
.lock
);
2333 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
2335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2337 if (dev_priv
->psr
.active
) {
2338 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
2340 WARN_ON(!(val
& EDP_PSR_ENABLE
));
2342 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
2344 dev_priv
->psr
.active
= false;
2349 void intel_edp_psr_invalidate(struct drm_device
*dev
,
2350 unsigned frontbuffer_bits
)
2352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2353 struct drm_crtc
*crtc
;
2356 mutex_lock(&dev_priv
->psr
.lock
);
2357 if (!dev_priv
->psr
.enabled
) {
2358 mutex_unlock(&dev_priv
->psr
.lock
);
2362 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2363 pipe
= to_intel_crtc(crtc
)->pipe
;
2365 intel_edp_psr_do_exit(dev
);
2367 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2369 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2370 mutex_unlock(&dev_priv
->psr
.lock
);
2373 void intel_edp_psr_flush(struct drm_device
*dev
,
2374 unsigned frontbuffer_bits
)
2376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2377 struct drm_crtc
*crtc
;
2380 mutex_lock(&dev_priv
->psr
.lock
);
2381 if (!dev_priv
->psr
.enabled
) {
2382 mutex_unlock(&dev_priv
->psr
.lock
);
2386 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2387 pipe
= to_intel_crtc(crtc
)->pipe
;
2388 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2391 * On Haswell sprite plane updates don't result in a psr invalidating
2392 * signal in the hardware. Which means we need to manually fake this in
2393 * software for all flushes, not just when we've seen a preceding
2394 * invalidation through frontbuffer rendering.
2396 if (IS_HASWELL(dev
) &&
2397 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2398 intel_edp_psr_do_exit(dev
);
2400 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2401 schedule_delayed_work(&dev_priv
->psr
.work
,
2402 msecs_to_jiffies(100));
2403 mutex_unlock(&dev_priv
->psr
.lock
);
2406 void intel_edp_psr_init(struct drm_device
*dev
)
2408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2410 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2411 mutex_init(&dev_priv
->psr
.lock
);
2414 static void intel_disable_dp(struct intel_encoder
*encoder
)
2416 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2417 struct drm_device
*dev
= encoder
->base
.dev
;
2419 /* Make sure the panel is off before trying to change the mode. But also
2420 * ensure that we have vdd while we switch off the panel. */
2421 intel_edp_panel_vdd_on(intel_dp
);
2422 intel_edp_backlight_off(intel_dp
);
2423 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2424 intel_edp_panel_off(intel_dp
);
2426 /* disable the port before the pipe on g4x */
2427 if (INTEL_INFO(dev
)->gen
< 5)
2428 intel_dp_link_down(intel_dp
);
2431 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2433 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2434 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2436 intel_dp_link_down(intel_dp
);
2438 ironlake_edp_pll_off(intel_dp
);
2441 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2443 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2445 intel_dp_link_down(intel_dp
);
2448 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2450 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2451 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2452 struct drm_device
*dev
= encoder
->base
.dev
;
2453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2454 struct intel_crtc
*intel_crtc
=
2455 to_intel_crtc(encoder
->base
.crtc
);
2456 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2457 enum pipe pipe
= intel_crtc
->pipe
;
2460 intel_dp_link_down(intel_dp
);
2462 mutex_lock(&dev_priv
->dpio_lock
);
2464 /* Propagate soft reset to data lane reset */
2465 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2466 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2467 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2469 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2470 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2471 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2473 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2474 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2475 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2477 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2478 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2479 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2481 mutex_unlock(&dev_priv
->dpio_lock
);
2485 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2487 uint8_t dp_train_pat
)
2489 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2490 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2492 enum port port
= intel_dig_port
->port
;
2495 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2497 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2498 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2500 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2502 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2503 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2504 case DP_TRAINING_PATTERN_DISABLE
:
2505 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2508 case DP_TRAINING_PATTERN_1
:
2509 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2511 case DP_TRAINING_PATTERN_2
:
2512 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2514 case DP_TRAINING_PATTERN_3
:
2515 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2518 I915_WRITE(DP_TP_CTL(port
), temp
);
2520 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2521 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2523 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2524 case DP_TRAINING_PATTERN_DISABLE
:
2525 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2527 case DP_TRAINING_PATTERN_1
:
2528 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2530 case DP_TRAINING_PATTERN_2
:
2531 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2533 case DP_TRAINING_PATTERN_3
:
2534 DRM_ERROR("DP training pattern 3 not supported\n");
2535 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2540 if (IS_CHERRYVIEW(dev
))
2541 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2543 *DP
&= ~DP_LINK_TRAIN_MASK
;
2545 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2546 case DP_TRAINING_PATTERN_DISABLE
:
2547 *DP
|= DP_LINK_TRAIN_OFF
;
2549 case DP_TRAINING_PATTERN_1
:
2550 *DP
|= DP_LINK_TRAIN_PAT_1
;
2552 case DP_TRAINING_PATTERN_2
:
2553 *DP
|= DP_LINK_TRAIN_PAT_2
;
2555 case DP_TRAINING_PATTERN_3
:
2556 if (IS_CHERRYVIEW(dev
)) {
2557 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2559 DRM_ERROR("DP training pattern 3 not supported\n");
2560 *DP
|= DP_LINK_TRAIN_PAT_2
;
2567 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2569 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2572 /* enable with pattern 1 (as per spec) */
2573 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2574 DP_TRAINING_PATTERN_1
);
2576 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2577 POSTING_READ(intel_dp
->output_reg
);
2580 * Magic for VLV/CHV. We _must_ first set up the register
2581 * without actually enabling the port, and then do another
2582 * write to enable the port. Otherwise link training will
2583 * fail when the power sequencer is freshly used for this port.
2585 intel_dp
->DP
|= DP_PORT_EN
;
2587 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2588 POSTING_READ(intel_dp
->output_reg
);
2591 static void intel_enable_dp(struct intel_encoder
*encoder
)
2593 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2594 struct drm_device
*dev
= encoder
->base
.dev
;
2595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2596 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2598 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2603 if (IS_VALLEYVIEW(dev
))
2604 vlv_init_panel_power_sequencer(intel_dp
);
2606 intel_dp_enable_port(intel_dp
);
2608 edp_panel_vdd_on(intel_dp
);
2609 edp_panel_on(intel_dp
);
2610 edp_panel_vdd_off(intel_dp
, true);
2612 pps_unlock(intel_dp
);
2614 if (IS_VALLEYVIEW(dev
))
2615 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
));
2617 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2618 intel_dp_start_link_train(intel_dp
);
2619 intel_dp_complete_link_train(intel_dp
);
2620 intel_dp_stop_link_train(intel_dp
);
2623 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2625 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2627 intel_enable_dp(encoder
);
2628 intel_edp_backlight_on(intel_dp
);
2631 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2633 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2635 intel_edp_backlight_on(intel_dp
);
2638 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2640 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2641 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2643 intel_dp_prepare(encoder
);
2645 /* Only ilk+ has port A */
2646 if (dport
->port
== PORT_A
) {
2647 ironlake_set_pll_cpu_edp(intel_dp
);
2648 ironlake_edp_pll_on(intel_dp
);
2652 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2656 struct intel_encoder
*encoder
;
2658 lockdep_assert_held(&dev_priv
->pps_mutex
);
2660 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2662 struct intel_dp
*intel_dp
;
2665 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2668 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2669 port
= dp_to_dig_port(intel_dp
)->port
;
2671 if (intel_dp
->pps_pipe
!= pipe
)
2674 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2675 pipe_name(pipe
), port_name(port
));
2677 /* make sure vdd is off before we steal it */
2678 edp_panel_vdd_off_sync(intel_dp
);
2680 intel_dp
->pps_pipe
= INVALID_PIPE
;
2684 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2686 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2687 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2688 struct drm_device
*dev
= encoder
->base
.dev
;
2689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2690 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2692 lockdep_assert_held(&dev_priv
->pps_mutex
);
2694 if (!is_edp(intel_dp
))
2697 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2701 * If another power sequencer was being used on this
2702 * port previously make sure to turn off vdd there while
2703 * we still have control of it.
2705 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2706 edp_panel_vdd_off_sync(intel_dp
);
2709 * We may be stealing the power
2710 * sequencer from another port.
2712 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2714 /* now it's all ours */
2715 intel_dp
->pps_pipe
= crtc
->pipe
;
2717 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2718 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2720 /* init power sequencer on this pipe and port */
2721 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2722 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2725 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2727 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2728 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2729 struct drm_device
*dev
= encoder
->base
.dev
;
2730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2731 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2732 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2733 int pipe
= intel_crtc
->pipe
;
2736 mutex_lock(&dev_priv
->dpio_lock
);
2738 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2745 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2746 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2747 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2749 mutex_unlock(&dev_priv
->dpio_lock
);
2751 intel_enable_dp(encoder
);
2754 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2756 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2757 struct drm_device
*dev
= encoder
->base
.dev
;
2758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2759 struct intel_crtc
*intel_crtc
=
2760 to_intel_crtc(encoder
->base
.crtc
);
2761 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2762 int pipe
= intel_crtc
->pipe
;
2764 intel_dp_prepare(encoder
);
2766 /* Program Tx lane resets to default */
2767 mutex_lock(&dev_priv
->dpio_lock
);
2768 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2769 DPIO_PCS_TX_LANE2_RESET
|
2770 DPIO_PCS_TX_LANE1_RESET
);
2771 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2772 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2773 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2774 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2775 DPIO_PCS_CLK_SOFT_RESET
);
2777 /* Fix up inter-pair skew failure */
2778 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2779 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2780 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2781 mutex_unlock(&dev_priv
->dpio_lock
);
2784 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2786 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2787 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2788 struct drm_device
*dev
= encoder
->base
.dev
;
2789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2790 struct intel_crtc
*intel_crtc
=
2791 to_intel_crtc(encoder
->base
.crtc
);
2792 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2793 int pipe
= intel_crtc
->pipe
;
2797 mutex_lock(&dev_priv
->dpio_lock
);
2799 /* allow hardware to manage TX FIFO reset source */
2800 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2801 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2802 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2804 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2805 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2806 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2808 /* Deassert soft data lane reset*/
2809 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2810 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2811 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2813 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2814 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2815 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2817 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2818 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2819 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2821 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2822 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2823 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2825 /* Program Tx lane latency optimal setting*/
2826 for (i
= 0; i
< 4; i
++) {
2827 /* Set the latency optimal bit */
2828 data
= (i
== 1) ? 0x0 : 0x6;
2829 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2830 data
<< DPIO_FRC_LATENCY_SHFIT
);
2832 /* Set the upar bit */
2833 data
= (i
== 1) ? 0x0 : 0x1;
2834 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2835 data
<< DPIO_UPAR_SHIFT
);
2838 /* Data lane stagger programming */
2839 /* FIXME: Fix up value only after power analysis */
2841 mutex_unlock(&dev_priv
->dpio_lock
);
2843 intel_enable_dp(encoder
);
2846 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2848 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2849 struct drm_device
*dev
= encoder
->base
.dev
;
2850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2851 struct intel_crtc
*intel_crtc
=
2852 to_intel_crtc(encoder
->base
.crtc
);
2853 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2854 enum pipe pipe
= intel_crtc
->pipe
;
2857 intel_dp_prepare(encoder
);
2859 mutex_lock(&dev_priv
->dpio_lock
);
2861 /* program left/right clock distribution */
2862 if (pipe
!= PIPE_B
) {
2863 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2864 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2866 val
|= CHV_BUFLEFTENA1_FORCE
;
2868 val
|= CHV_BUFRIGHTENA1_FORCE
;
2869 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2871 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2872 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2874 val
|= CHV_BUFLEFTENA2_FORCE
;
2876 val
|= CHV_BUFRIGHTENA2_FORCE
;
2877 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2880 /* program clock channel usage */
2881 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2882 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2884 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2886 val
|= CHV_PCS_USEDCLKCHANNEL
;
2887 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2889 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2890 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2892 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2894 val
|= CHV_PCS_USEDCLKCHANNEL
;
2895 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2898 * This a a bit weird since generally CL
2899 * matches the pipe, but here we need to
2900 * pick the CL based on the port.
2902 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2904 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2906 val
|= CHV_CMN_USEDCLKCHANNEL
;
2907 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2909 mutex_unlock(&dev_priv
->dpio_lock
);
2913 * Native read with retry for link status and receiver capability reads for
2914 * cases where the sink may still be asleep.
2916 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2917 * supposed to retry 3 times per the spec.
2920 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2921 void *buffer
, size_t size
)
2926 for (i
= 0; i
< 3; i
++) {
2927 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2937 * Fetch AUX CH registers 0x202 - 0x207 which contain
2938 * link status information
2941 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2943 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2946 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2949 /* These are source-specific values. */
2951 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2953 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2954 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2956 if (INTEL_INFO(dev
)->gen
>= 9)
2957 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2958 else if (IS_VALLEYVIEW(dev
))
2959 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2960 else if (IS_GEN7(dev
) && port
== PORT_A
)
2961 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2962 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2963 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2965 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2969 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2971 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2972 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2974 if (INTEL_INFO(dev
)->gen
>= 9) {
2975 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2977 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2979 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2983 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2985 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2986 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2987 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2988 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2990 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2992 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2995 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2997 } else if (IS_VALLEYVIEW(dev
)) {
2998 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3000 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3002 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3004 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3005 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3009 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3010 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3015 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3017 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3020 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3022 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3026 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3029 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3034 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
3036 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3039 struct intel_crtc
*intel_crtc
=
3040 to_intel_crtc(dport
->base
.base
.crtc
);
3041 unsigned long demph_reg_value
, preemph_reg_value
,
3042 uniqtranscale_reg_value
;
3043 uint8_t train_set
= intel_dp
->train_set
[0];
3044 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3045 int pipe
= intel_crtc
->pipe
;
3047 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3048 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3049 preemph_reg_value
= 0x0004000;
3050 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3052 demph_reg_value
= 0x2B405555;
3053 uniqtranscale_reg_value
= 0x552AB83A;
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3056 demph_reg_value
= 0x2B404040;
3057 uniqtranscale_reg_value
= 0x5548B83A;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3060 demph_reg_value
= 0x2B245555;
3061 uniqtranscale_reg_value
= 0x5560B83A;
3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3064 demph_reg_value
= 0x2B405555;
3065 uniqtranscale_reg_value
= 0x5598DA3A;
3071 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3072 preemph_reg_value
= 0x0002000;
3073 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3074 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3075 demph_reg_value
= 0x2B404040;
3076 uniqtranscale_reg_value
= 0x5552B83A;
3078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3079 demph_reg_value
= 0x2B404848;
3080 uniqtranscale_reg_value
= 0x5580B83A;
3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3083 demph_reg_value
= 0x2B404040;
3084 uniqtranscale_reg_value
= 0x55ADDA3A;
3090 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3091 preemph_reg_value
= 0x0000000;
3092 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3094 demph_reg_value
= 0x2B305555;
3095 uniqtranscale_reg_value
= 0x5570B83A;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3098 demph_reg_value
= 0x2B2B4040;
3099 uniqtranscale_reg_value
= 0x55ADDA3A;
3105 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3106 preemph_reg_value
= 0x0006000;
3107 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3109 demph_reg_value
= 0x1B405555;
3110 uniqtranscale_reg_value
= 0x55ADDA3A;
3120 mutex_lock(&dev_priv
->dpio_lock
);
3121 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3122 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3123 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3124 uniqtranscale_reg_value
);
3125 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3126 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3127 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3128 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3129 mutex_unlock(&dev_priv
->dpio_lock
);
3134 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
3136 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3138 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3139 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3140 u32 deemph_reg_value
, margin_reg_value
, val
;
3141 uint8_t train_set
= intel_dp
->train_set
[0];
3142 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3143 enum pipe pipe
= intel_crtc
->pipe
;
3146 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3147 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3148 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3150 deemph_reg_value
= 128;
3151 margin_reg_value
= 52;
3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3154 deemph_reg_value
= 128;
3155 margin_reg_value
= 77;
3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3158 deemph_reg_value
= 128;
3159 margin_reg_value
= 102;
3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3162 deemph_reg_value
= 128;
3163 margin_reg_value
= 154;
3164 /* FIXME extra to set for 1200 */
3170 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3171 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3173 deemph_reg_value
= 85;
3174 margin_reg_value
= 78;
3176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3177 deemph_reg_value
= 85;
3178 margin_reg_value
= 116;
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3181 deemph_reg_value
= 85;
3182 margin_reg_value
= 154;
3188 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3189 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3191 deemph_reg_value
= 64;
3192 margin_reg_value
= 104;
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3195 deemph_reg_value
= 64;
3196 margin_reg_value
= 154;
3202 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3203 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3205 deemph_reg_value
= 43;
3206 margin_reg_value
= 154;
3216 mutex_lock(&dev_priv
->dpio_lock
);
3218 /* Clear calc init */
3219 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3220 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3221 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3222 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3223 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3225 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3226 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3227 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3228 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3229 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3231 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3232 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3233 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3234 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3236 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3237 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3238 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3239 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3241 /* Program swing deemph */
3242 for (i
= 0; i
< 4; i
++) {
3243 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3244 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3245 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3246 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3249 /* Program swing margin */
3250 for (i
= 0; i
< 4; i
++) {
3251 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3252 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3253 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3254 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3257 /* Disable unique transition scale */
3258 for (i
= 0; i
< 4; i
++) {
3259 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3260 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3261 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3264 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3265 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3266 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3267 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3270 * The document said it needs to set bit 27 for ch0 and bit 26
3271 * for ch1. Might be a typo in the doc.
3272 * For now, for this unique transition scale selection, set bit
3273 * 27 for ch0 and ch1.
3275 for (i
= 0; i
< 4; i
++) {
3276 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3277 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3278 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3281 for (i
= 0; i
< 4; i
++) {
3282 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3283 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3284 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3285 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3289 /* Start swing calculation */
3290 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3291 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3292 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3294 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3295 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3296 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3299 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3300 val
|= DPIO_LRC_BYPASS
;
3301 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3303 mutex_unlock(&dev_priv
->dpio_lock
);
3309 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3310 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3315 uint8_t voltage_max
;
3316 uint8_t preemph_max
;
3318 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3319 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3320 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3328 voltage_max
= intel_dp_voltage_max(intel_dp
);
3329 if (v
>= voltage_max
)
3330 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3332 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3333 if (p
>= preemph_max
)
3334 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3336 for (lane
= 0; lane
< 4; lane
++)
3337 intel_dp
->train_set
[lane
] = v
| p
;
3341 intel_gen4_signal_levels(uint8_t train_set
)
3343 uint32_t signal_levels
= 0;
3345 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3346 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3348 signal_levels
|= DP_VOLTAGE_0_4
;
3350 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3351 signal_levels
|= DP_VOLTAGE_0_6
;
3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3354 signal_levels
|= DP_VOLTAGE_0_8
;
3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3357 signal_levels
|= DP_VOLTAGE_1_2
;
3360 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3361 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3363 signal_levels
|= DP_PRE_EMPHASIS_0
;
3365 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3366 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3368 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3369 signal_levels
|= DP_PRE_EMPHASIS_6
;
3371 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3372 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3375 return signal_levels
;
3378 /* Gen6's DP voltage swing and pre-emphasis control */
3380 intel_gen6_edp_signal_levels(uint8_t train_set
)
3382 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3383 DP_TRAIN_PRE_EMPHASIS_MASK
);
3384 switch (signal_levels
) {
3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3387 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3389 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3391 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3392 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3395 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3398 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3400 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3401 "0x%x\n", signal_levels
);
3402 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3406 /* Gen7's DP voltage swing and pre-emphasis control */
3408 intel_gen7_edp_signal_levels(uint8_t train_set
)
3410 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3411 DP_TRAIN_PRE_EMPHASIS_MASK
);
3412 switch (signal_levels
) {
3413 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3414 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3416 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3418 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3421 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3423 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3426 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3427 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3428 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3431 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3432 "0x%x\n", signal_levels
);
3433 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3437 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3439 intel_hsw_signal_levels(uint8_t train_set
)
3441 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3442 DP_TRAIN_PRE_EMPHASIS_MASK
);
3443 switch (signal_levels
) {
3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3445 return DDI_BUF_TRANS_SELECT(0);
3446 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3447 return DDI_BUF_TRANS_SELECT(1);
3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3449 return DDI_BUF_TRANS_SELECT(2);
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3451 return DDI_BUF_TRANS_SELECT(3);
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3454 return DDI_BUF_TRANS_SELECT(4);
3455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3456 return DDI_BUF_TRANS_SELECT(5);
3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3458 return DDI_BUF_TRANS_SELECT(6);
3460 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3461 return DDI_BUF_TRANS_SELECT(7);
3462 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3463 return DDI_BUF_TRANS_SELECT(8);
3465 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3466 "0x%x\n", signal_levels
);
3467 return DDI_BUF_TRANS_SELECT(0);
3471 /* Properly updates "DP" with the correct signal levels. */
3473 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3475 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3476 enum port port
= intel_dig_port
->port
;
3477 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3478 uint32_t signal_levels
, mask
;
3479 uint8_t train_set
= intel_dp
->train_set
[0];
3481 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
3482 signal_levels
= intel_hsw_signal_levels(train_set
);
3483 mask
= DDI_BUF_EMP_MASK
;
3484 } else if (IS_CHERRYVIEW(dev
)) {
3485 signal_levels
= intel_chv_signal_levels(intel_dp
);
3487 } else if (IS_VALLEYVIEW(dev
)) {
3488 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3490 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3491 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3492 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3493 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3494 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3495 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3497 signal_levels
= intel_gen4_signal_levels(train_set
);
3498 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3501 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3503 *DP
= (*DP
& ~mask
) | signal_levels
;
3507 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3509 uint8_t dp_train_pat
)
3511 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3512 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3514 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3517 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3519 I915_WRITE(intel_dp
->output_reg
, *DP
);
3520 POSTING_READ(intel_dp
->output_reg
);
3522 buf
[0] = dp_train_pat
;
3523 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3524 DP_TRAINING_PATTERN_DISABLE
) {
3525 /* don't write DP_TRAINING_LANEx_SET on disable */
3528 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3529 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3530 len
= intel_dp
->lane_count
+ 1;
3533 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3540 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3541 uint8_t dp_train_pat
)
3543 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3544 intel_dp_set_signal_levels(intel_dp
, DP
);
3545 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3549 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3550 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3552 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3553 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3557 intel_get_adjust_train(intel_dp
, link_status
);
3558 intel_dp_set_signal_levels(intel_dp
, DP
);
3560 I915_WRITE(intel_dp
->output_reg
, *DP
);
3561 POSTING_READ(intel_dp
->output_reg
);
3563 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3564 intel_dp
->train_set
, intel_dp
->lane_count
);
3566 return ret
== intel_dp
->lane_count
;
3569 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3571 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3572 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3574 enum port port
= intel_dig_port
->port
;
3580 val
= I915_READ(DP_TP_CTL(port
));
3581 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3582 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3583 I915_WRITE(DP_TP_CTL(port
), val
);
3586 * On PORT_A we can have only eDP in SST mode. There the only reason
3587 * we need to set idle transmission mode is to work around a HW issue
3588 * where we enable the pipe while not in idle link-training mode.
3589 * In this case there is requirement to wait for a minimum number of
3590 * idle patterns to be sent.
3595 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3597 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3600 /* Enable corresponding port and start training pattern 1 */
3602 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3604 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3605 struct drm_device
*dev
= encoder
->dev
;
3608 int voltage_tries
, loop_tries
;
3609 uint32_t DP
= intel_dp
->DP
;
3610 uint8_t link_config
[2];
3613 intel_ddi_prepare_link_retrain(encoder
);
3615 /* Write the link configuration data */
3616 link_config
[0] = intel_dp
->link_bw
;
3617 link_config
[1] = intel_dp
->lane_count
;
3618 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3619 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3620 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3623 link_config
[1] = DP_SET_ANSI_8B10B
;
3624 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3628 /* clock recovery */
3629 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3630 DP_TRAINING_PATTERN_1
|
3631 DP_LINK_SCRAMBLING_DISABLE
)) {
3632 DRM_ERROR("failed to enable link training\n");
3640 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3642 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3643 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3644 DRM_ERROR("failed to get link status\n");
3648 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3649 DRM_DEBUG_KMS("clock recovery OK\n");
3653 /* Check to see if we've tried the max voltage */
3654 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3655 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3657 if (i
== intel_dp
->lane_count
) {
3659 if (loop_tries
== 5) {
3660 DRM_ERROR("too many full retries, give up\n");
3663 intel_dp_reset_link_train(intel_dp
, &DP
,
3664 DP_TRAINING_PATTERN_1
|
3665 DP_LINK_SCRAMBLING_DISABLE
);
3670 /* Check to see if we've tried the same voltage 5 times */
3671 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3673 if (voltage_tries
== 5) {
3674 DRM_ERROR("too many voltage retries, give up\n");
3679 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3681 /* Update training set as requested by target */
3682 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3683 DRM_ERROR("failed to update link training\n");
3692 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3694 bool channel_eq
= false;
3695 int tries
, cr_tries
;
3696 uint32_t DP
= intel_dp
->DP
;
3697 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3699 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3700 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3701 training_pattern
= DP_TRAINING_PATTERN_3
;
3703 /* channel equalization */
3704 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3706 DP_LINK_SCRAMBLING_DISABLE
)) {
3707 DRM_ERROR("failed to start channel equalization\n");
3715 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3718 DRM_ERROR("failed to train DP, aborting\n");
3722 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3723 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3724 DRM_ERROR("failed to get link status\n");
3728 /* Make sure clock is still ok */
3729 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3730 intel_dp_start_link_train(intel_dp
);
3731 intel_dp_set_link_train(intel_dp
, &DP
,
3733 DP_LINK_SCRAMBLING_DISABLE
);
3738 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3743 /* Try 5 times, then try clock recovery if that fails */
3745 intel_dp_link_down(intel_dp
);
3746 intel_dp_start_link_train(intel_dp
);
3747 intel_dp_set_link_train(intel_dp
, &DP
,
3749 DP_LINK_SCRAMBLING_DISABLE
);
3755 /* Update training set as requested by target */
3756 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3757 DRM_ERROR("failed to update link training\n");
3763 intel_dp_set_idle_link_train(intel_dp
);
3768 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3772 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3774 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3775 DP_TRAINING_PATTERN_DISABLE
);
3779 intel_dp_link_down(struct intel_dp
*intel_dp
)
3781 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3782 enum port port
= intel_dig_port
->port
;
3783 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3785 struct intel_crtc
*intel_crtc
=
3786 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3787 uint32_t DP
= intel_dp
->DP
;
3789 if (WARN_ON(HAS_DDI(dev
)))
3792 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3795 DRM_DEBUG_KMS("\n");
3797 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3798 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3799 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3801 if (IS_CHERRYVIEW(dev
))
3802 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3804 DP
&= ~DP_LINK_TRAIN_MASK
;
3805 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3807 POSTING_READ(intel_dp
->output_reg
);
3809 if (HAS_PCH_IBX(dev
) &&
3810 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3811 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3813 /* Hardware workaround: leaving our transcoder select
3814 * set to transcoder B while it's off will prevent the
3815 * corresponding HDMI output on transcoder A.
3817 * Combine this with another hardware workaround:
3818 * transcoder select bit can only be cleared while the
3821 DP
&= ~DP_PIPEB_SELECT
;
3822 I915_WRITE(intel_dp
->output_reg
, DP
);
3824 /* Changes to enable or select take place the vblank
3825 * after being written.
3827 if (WARN_ON(crtc
== NULL
)) {
3828 /* We should never try to disable a port without a crtc
3829 * attached. For paranoia keep the code around for a
3831 POSTING_READ(intel_dp
->output_reg
);
3834 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3837 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3838 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3839 POSTING_READ(intel_dp
->output_reg
);
3840 msleep(intel_dp
->panel_power_down_delay
);
3844 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3846 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3847 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3850 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3851 sizeof(intel_dp
->dpcd
)) < 0)
3852 return false; /* aux transfer failed */
3854 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3856 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3857 return false; /* DPCD not present */
3859 /* Check if the panel supports PSR */
3860 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3861 if (is_edp(intel_dp
)) {
3862 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3864 sizeof(intel_dp
->psr_dpcd
));
3865 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3866 dev_priv
->psr
.sink_support
= true;
3867 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3871 /* Training Pattern 3 support */
3872 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3873 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3874 intel_dp
->use_tps3
= true;
3875 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3877 intel_dp
->use_tps3
= false;
3879 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3880 DP_DWN_STRM_PORT_PRESENT
))
3881 return true; /* native DP sink */
3883 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3884 return true; /* no per-port downstream info */
3886 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3887 intel_dp
->downstream_ports
,
3888 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3889 return false; /* downstream port status fetch failed */
3895 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3899 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3902 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3903 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3904 buf
[0], buf
[1], buf
[2]);
3906 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3907 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3908 buf
[0], buf
[1], buf
[2]);
3912 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3916 if (!intel_dp
->can_mst
)
3919 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3922 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3923 if (buf
[0] & DP_MST_CAP
) {
3924 DRM_DEBUG_KMS("Sink is MST capable\n");
3925 intel_dp
->is_mst
= true;
3927 DRM_DEBUG_KMS("Sink is not MST capable\n");
3928 intel_dp
->is_mst
= false;
3932 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3933 return intel_dp
->is_mst
;
3936 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3938 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3939 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3940 struct intel_crtc
*intel_crtc
=
3941 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3946 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3949 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3952 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3955 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3956 buf
| DP_TEST_SINK_START
) < 0)
3959 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3961 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
3964 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3965 DP_TEST_SINK_MISC
, &buf
) < 0)
3967 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3968 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
3970 if (attempts
== 0) {
3971 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3975 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3978 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3980 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3981 buf
& ~DP_TEST_SINK_START
) < 0)
3988 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3990 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3991 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3992 sink_irq_vector
, 1) == 1;
3996 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4000 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4002 sink_irq_vector
, 14);
4010 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4012 /* NAK by default */
4013 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
4017 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4021 if (intel_dp
->is_mst
) {
4026 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4030 /* check link status - esi[10] = 0x200c */
4031 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4032 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4033 intel_dp_start_link_train(intel_dp
);
4034 intel_dp_complete_link_train(intel_dp
);
4035 intel_dp_stop_link_train(intel_dp
);
4038 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
4039 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4042 for (retry
= 0; retry
< 3; retry
++) {
4044 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4045 DP_SINK_COUNT_ESI
+1,
4052 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4054 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
4062 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4063 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4064 intel_dp
->is_mst
= false;
4065 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4066 /* send a hotplug event */
4067 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4074 * According to DP spec
4077 * 2. Configure link according to Receiver Capabilities
4078 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4079 * 4. Check link status on receipt of hot-plug interrupt
4082 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4084 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4085 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4087 u8 link_status
[DP_LINK_STATUS_SIZE
];
4089 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4091 if (!intel_encoder
->connectors_active
)
4094 if (WARN_ON(!intel_encoder
->base
.crtc
))
4097 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4100 /* Try to read receiver status if the link appears to be up */
4101 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4105 /* Now read the DPCD to see if it's actually running */
4106 if (!intel_dp_get_dpcd(intel_dp
)) {
4110 /* Try to read the source of the interrupt */
4111 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4112 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4113 /* Clear interrupt source */
4114 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4115 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4118 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4119 intel_dp_handle_test_request(intel_dp
);
4120 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4121 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4124 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4125 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4126 intel_encoder
->base
.name
);
4127 intel_dp_start_link_train(intel_dp
);
4128 intel_dp_complete_link_train(intel_dp
);
4129 intel_dp_stop_link_train(intel_dp
);
4133 /* XXX this is probably wrong for multiple downstream ports */
4134 static enum drm_connector_status
4135 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4137 uint8_t *dpcd
= intel_dp
->dpcd
;
4140 if (!intel_dp_get_dpcd(intel_dp
))
4141 return connector_status_disconnected
;
4143 /* if there's no downstream port, we're done */
4144 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4145 return connector_status_connected
;
4147 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4148 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4149 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4152 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4154 return connector_status_unknown
;
4156 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4157 : connector_status_disconnected
;
4160 /* If no HPD, poke DDC gently */
4161 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4162 return connector_status_connected
;
4164 /* Well we tried, say unknown for unreliable port types */
4165 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4166 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4167 if (type
== DP_DS_PORT_TYPE_VGA
||
4168 type
== DP_DS_PORT_TYPE_NON_EDID
)
4169 return connector_status_unknown
;
4171 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4172 DP_DWN_STRM_PORT_TYPE_MASK
;
4173 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4174 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4175 return connector_status_unknown
;
4178 /* Anything else is out of spec, warn and ignore */
4179 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4180 return connector_status_disconnected
;
4183 static enum drm_connector_status
4184 edp_detect(struct intel_dp
*intel_dp
)
4186 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4187 enum drm_connector_status status
;
4189 status
= intel_panel_detect(dev
);
4190 if (status
== connector_status_unknown
)
4191 status
= connector_status_connected
;
4196 static enum drm_connector_status
4197 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4199 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4201 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4203 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4204 return connector_status_disconnected
;
4206 return intel_dp_detect_dpcd(intel_dp
);
4209 static int g4x_digital_port_connected(struct drm_device
*dev
,
4210 struct intel_digital_port
*intel_dig_port
)
4212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4215 if (IS_VALLEYVIEW(dev
)) {
4216 switch (intel_dig_port
->port
) {
4218 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4221 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4224 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4230 switch (intel_dig_port
->port
) {
4232 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4235 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4238 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4245 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4250 static enum drm_connector_status
4251 g4x_dp_detect(struct intel_dp
*intel_dp
)
4253 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4254 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4257 /* Can't disconnect eDP, but you can close the lid... */
4258 if (is_edp(intel_dp
)) {
4259 enum drm_connector_status status
;
4261 status
= intel_panel_detect(dev
);
4262 if (status
== connector_status_unknown
)
4263 status
= connector_status_connected
;
4267 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4269 return connector_status_unknown
;
4271 return connector_status_disconnected
;
4273 return intel_dp_detect_dpcd(intel_dp
);
4276 static struct edid
*
4277 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4279 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4281 /* use cached edid if we have one */
4282 if (intel_connector
->edid
) {
4284 if (IS_ERR(intel_connector
->edid
))
4287 return drm_edid_duplicate(intel_connector
->edid
);
4289 return drm_get_edid(&intel_connector
->base
,
4290 &intel_dp
->aux
.ddc
);
4294 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4296 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4299 edid
= intel_dp_get_edid(intel_dp
);
4300 intel_connector
->detect_edid
= edid
;
4302 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4303 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4305 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4309 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4311 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4313 kfree(intel_connector
->detect_edid
);
4314 intel_connector
->detect_edid
= NULL
;
4316 intel_dp
->has_audio
= false;
4319 static enum intel_display_power_domain
4320 intel_dp_power_get(struct intel_dp
*dp
)
4322 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4323 enum intel_display_power_domain power_domain
;
4325 power_domain
= intel_display_port_power_domain(encoder
);
4326 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4328 return power_domain
;
4332 intel_dp_power_put(struct intel_dp
*dp
,
4333 enum intel_display_power_domain power_domain
)
4335 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4336 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4339 static enum drm_connector_status
4340 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4342 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4343 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4344 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4345 struct drm_device
*dev
= connector
->dev
;
4346 enum drm_connector_status status
;
4347 enum intel_display_power_domain power_domain
;
4350 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4351 connector
->base
.id
, connector
->name
);
4352 intel_dp_unset_edid(intel_dp
);
4354 if (intel_dp
->is_mst
) {
4355 /* MST devices are disconnected from a monitor POV */
4356 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4357 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4358 return connector_status_disconnected
;
4361 power_domain
= intel_dp_power_get(intel_dp
);
4363 /* Can't disconnect eDP, but you can close the lid... */
4364 if (is_edp(intel_dp
))
4365 status
= edp_detect(intel_dp
);
4366 else if (HAS_PCH_SPLIT(dev
))
4367 status
= ironlake_dp_detect(intel_dp
);
4369 status
= g4x_dp_detect(intel_dp
);
4370 if (status
!= connector_status_connected
)
4373 intel_dp_probe_oui(intel_dp
);
4375 ret
= intel_dp_probe_mst(intel_dp
);
4377 /* if we are in MST mode then this connector
4378 won't appear connected or have anything with EDID on it */
4379 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4380 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4381 status
= connector_status_disconnected
;
4385 intel_dp_set_edid(intel_dp
);
4387 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4388 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4389 status
= connector_status_connected
;
4392 intel_dp_power_put(intel_dp
, power_domain
);
4397 intel_dp_force(struct drm_connector
*connector
)
4399 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4400 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4401 enum intel_display_power_domain power_domain
;
4403 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4404 connector
->base
.id
, connector
->name
);
4405 intel_dp_unset_edid(intel_dp
);
4407 if (connector
->status
!= connector_status_connected
)
4410 power_domain
= intel_dp_power_get(intel_dp
);
4412 intel_dp_set_edid(intel_dp
);
4414 intel_dp_power_put(intel_dp
, power_domain
);
4416 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4417 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4420 static int intel_dp_get_modes(struct drm_connector
*connector
)
4422 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4425 edid
= intel_connector
->detect_edid
;
4427 int ret
= intel_connector_update_modes(connector
, edid
);
4432 /* if eDP has no EDID, fall back to fixed mode */
4433 if (is_edp(intel_attached_dp(connector
)) &&
4434 intel_connector
->panel
.fixed_mode
) {
4435 struct drm_display_mode
*mode
;
4437 mode
= drm_mode_duplicate(connector
->dev
,
4438 intel_connector
->panel
.fixed_mode
);
4440 drm_mode_probed_add(connector
, mode
);
4449 intel_dp_detect_audio(struct drm_connector
*connector
)
4451 bool has_audio
= false;
4454 edid
= to_intel_connector(connector
)->detect_edid
;
4456 has_audio
= drm_detect_monitor_audio(edid
);
4462 intel_dp_set_property(struct drm_connector
*connector
,
4463 struct drm_property
*property
,
4466 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4467 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4468 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4469 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4472 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4476 if (property
== dev_priv
->force_audio_property
) {
4480 if (i
== intel_dp
->force_audio
)
4483 intel_dp
->force_audio
= i
;
4485 if (i
== HDMI_AUDIO_AUTO
)
4486 has_audio
= intel_dp_detect_audio(connector
);
4488 has_audio
= (i
== HDMI_AUDIO_ON
);
4490 if (has_audio
== intel_dp
->has_audio
)
4493 intel_dp
->has_audio
= has_audio
;
4497 if (property
== dev_priv
->broadcast_rgb_property
) {
4498 bool old_auto
= intel_dp
->color_range_auto
;
4499 uint32_t old_range
= intel_dp
->color_range
;
4502 case INTEL_BROADCAST_RGB_AUTO
:
4503 intel_dp
->color_range_auto
= true;
4505 case INTEL_BROADCAST_RGB_FULL
:
4506 intel_dp
->color_range_auto
= false;
4507 intel_dp
->color_range
= 0;
4509 case INTEL_BROADCAST_RGB_LIMITED
:
4510 intel_dp
->color_range_auto
= false;
4511 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4517 if (old_auto
== intel_dp
->color_range_auto
&&
4518 old_range
== intel_dp
->color_range
)
4524 if (is_edp(intel_dp
) &&
4525 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4526 if (val
== DRM_MODE_SCALE_NONE
) {
4527 DRM_DEBUG_KMS("no scaling not supported\n");
4531 if (intel_connector
->panel
.fitting_mode
== val
) {
4532 /* the eDP scaling property is not changed */
4535 intel_connector
->panel
.fitting_mode
= val
;
4543 if (intel_encoder
->base
.crtc
)
4544 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4550 intel_dp_connector_destroy(struct drm_connector
*connector
)
4552 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4554 kfree(intel_connector
->detect_edid
);
4556 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4557 kfree(intel_connector
->edid
);
4559 /* Can't call is_edp() since the encoder may have been destroyed
4561 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4562 intel_panel_fini(&intel_connector
->panel
);
4564 drm_connector_cleanup(connector
);
4568 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4570 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4571 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4573 drm_dp_aux_unregister(&intel_dp
->aux
);
4574 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4575 drm_encoder_cleanup(encoder
);
4576 if (is_edp(intel_dp
)) {
4577 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4579 * vdd might still be enabled do to the delayed vdd off.
4580 * Make sure vdd is actually turned off here.
4583 edp_panel_vdd_off_sync(intel_dp
);
4584 pps_unlock(intel_dp
);
4586 if (intel_dp
->edp_notifier
.notifier_call
) {
4587 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4588 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4591 kfree(intel_dig_port
);
4594 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4596 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4598 if (!is_edp(intel_dp
))
4602 * vdd might still be enabled do to the delayed vdd off.
4603 * Make sure vdd is actually turned off here.
4606 edp_panel_vdd_off_sync(intel_dp
);
4607 pps_unlock(intel_dp
);
4610 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4612 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4615 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4616 .dpms
= intel_connector_dpms
,
4617 .detect
= intel_dp_detect
,
4618 .force
= intel_dp_force
,
4619 .fill_modes
= drm_helper_probe_single_connector_modes
,
4620 .set_property
= intel_dp_set_property
,
4621 .destroy
= intel_dp_connector_destroy
,
4624 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4625 .get_modes
= intel_dp_get_modes
,
4626 .mode_valid
= intel_dp_mode_valid
,
4627 .best_encoder
= intel_best_encoder
,
4630 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4631 .reset
= intel_dp_encoder_reset
,
4632 .destroy
= intel_dp_encoder_destroy
,
4636 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4642 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4644 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4645 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4646 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4648 enum intel_display_power_domain power_domain
;
4651 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4652 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4654 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4655 port_name(intel_dig_port
->port
),
4656 long_hpd
? "long" : "short");
4658 power_domain
= intel_display_port_power_domain(intel_encoder
);
4659 intel_display_power_get(dev_priv
, power_domain
);
4663 if (HAS_PCH_SPLIT(dev
)) {
4664 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4667 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4671 if (!intel_dp_get_dpcd(intel_dp
)) {
4675 intel_dp_probe_oui(intel_dp
);
4677 if (!intel_dp_probe_mst(intel_dp
))
4681 if (intel_dp
->is_mst
) {
4682 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4686 if (!intel_dp
->is_mst
) {
4688 * we'll check the link status via the normal hot plug path later -
4689 * but for short hpds we should check it now
4691 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4692 intel_dp_check_link_status(intel_dp
);
4693 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4699 /* if we were in MST mode, and device is not there get out of MST mode */
4700 if (intel_dp
->is_mst
) {
4701 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4702 intel_dp
->is_mst
= false;
4703 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4706 intel_display_power_put(dev_priv
, power_domain
);
4711 /* Return which DP Port should be selected for Transcoder DP control */
4713 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4715 struct drm_device
*dev
= crtc
->dev
;
4716 struct intel_encoder
*intel_encoder
;
4717 struct intel_dp
*intel_dp
;
4719 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4720 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4722 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4723 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4724 return intel_dp
->output_reg
;
4730 /* check the VBT to see whether the eDP is on DP-D port */
4731 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4734 union child_device_config
*p_child
;
4736 static const short port_mapping
[] = {
4737 [PORT_B
] = PORT_IDPB
,
4738 [PORT_C
] = PORT_IDPC
,
4739 [PORT_D
] = PORT_IDPD
,
4745 if (!dev_priv
->vbt
.child_dev_num
)
4748 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4749 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4751 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4752 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4753 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4760 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4762 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4764 intel_attach_force_audio_property(connector
);
4765 intel_attach_broadcast_rgb_property(connector
);
4766 intel_dp
->color_range_auto
= true;
4768 if (is_edp(intel_dp
)) {
4769 drm_mode_create_scaling_mode_property(connector
->dev
);
4770 drm_object_attach_property(
4772 connector
->dev
->mode_config
.scaling_mode_property
,
4773 DRM_MODE_SCALE_ASPECT
);
4774 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4778 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4780 intel_dp
->last_power_cycle
= jiffies
;
4781 intel_dp
->last_power_on
= jiffies
;
4782 intel_dp
->last_backlight_off
= jiffies
;
4786 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4787 struct intel_dp
*intel_dp
)
4789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4790 struct edp_power_seq cur
, vbt
, spec
,
4791 *final
= &intel_dp
->pps_delays
;
4792 u32 pp_on
, pp_off
, pp_div
, pp
;
4793 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4795 lockdep_assert_held(&dev_priv
->pps_mutex
);
4797 /* already initialized? */
4798 if (final
->t11_t12
!= 0)
4801 if (HAS_PCH_SPLIT(dev
)) {
4802 pp_ctrl_reg
= PCH_PP_CONTROL
;
4803 pp_on_reg
= PCH_PP_ON_DELAYS
;
4804 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4805 pp_div_reg
= PCH_PP_DIVISOR
;
4807 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4809 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4810 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4811 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4812 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4815 /* Workaround: Need to write PP_CONTROL with the unlock key as
4816 * the very first thing. */
4817 pp
= ironlake_get_pp_control(intel_dp
);
4818 I915_WRITE(pp_ctrl_reg
, pp
);
4820 pp_on
= I915_READ(pp_on_reg
);
4821 pp_off
= I915_READ(pp_off_reg
);
4822 pp_div
= I915_READ(pp_div_reg
);
4824 /* Pull timing values out of registers */
4825 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4826 PANEL_POWER_UP_DELAY_SHIFT
;
4828 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4829 PANEL_LIGHT_ON_DELAY_SHIFT
;
4831 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4832 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4834 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4835 PANEL_POWER_DOWN_DELAY_SHIFT
;
4837 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4838 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4840 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4841 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4843 vbt
= dev_priv
->vbt
.edp_pps
;
4845 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4846 * our hw here, which are all in 100usec. */
4847 spec
.t1_t3
= 210 * 10;
4848 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4849 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4850 spec
.t10
= 500 * 10;
4851 /* This one is special and actually in units of 100ms, but zero
4852 * based in the hw (so we need to add 100 ms). But the sw vbt
4853 * table multiplies it with 1000 to make it in units of 100usec,
4855 spec
.t11_t12
= (510 + 100) * 10;
4857 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4858 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4860 /* Use the max of the register settings and vbt. If both are
4861 * unset, fall back to the spec limits. */
4862 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4864 max(cur.field, vbt.field))
4865 assign_final(t1_t3
);
4869 assign_final(t11_t12
);
4872 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4873 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4874 intel_dp
->backlight_on_delay
= get_delay(t8
);
4875 intel_dp
->backlight_off_delay
= get_delay(t9
);
4876 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4877 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4880 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4881 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4882 intel_dp
->panel_power_cycle_delay
);
4884 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4885 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4889 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4890 struct intel_dp
*intel_dp
)
4892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4893 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4894 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4895 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4896 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4897 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4899 lockdep_assert_held(&dev_priv
->pps_mutex
);
4901 if (HAS_PCH_SPLIT(dev
)) {
4902 pp_on_reg
= PCH_PP_ON_DELAYS
;
4903 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4904 pp_div_reg
= PCH_PP_DIVISOR
;
4906 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4908 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4909 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4910 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4914 * And finally store the new values in the power sequencer. The
4915 * backlight delays are set to 1 because we do manual waits on them. For
4916 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4917 * we'll end up waiting for the backlight off delay twice: once when we
4918 * do the manual sleep, and once when we disable the panel and wait for
4919 * the PP_STATUS bit to become zero.
4921 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4922 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4923 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4924 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4925 /* Compute the divisor for the pp clock, simply match the Bspec
4927 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4928 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4929 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4931 /* Haswell doesn't have any port selection bits for the panel
4932 * power sequencer any more. */
4933 if (IS_VALLEYVIEW(dev
)) {
4934 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4935 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4937 port_sel
= PANEL_PORT_SELECT_DPA
;
4939 port_sel
= PANEL_PORT_SELECT_DPD
;
4944 I915_WRITE(pp_on_reg
, pp_on
);
4945 I915_WRITE(pp_off_reg
, pp_off
);
4946 I915_WRITE(pp_div_reg
, pp_div
);
4948 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4949 I915_READ(pp_on_reg
),
4950 I915_READ(pp_off_reg
),
4951 I915_READ(pp_div_reg
));
4954 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4957 struct intel_encoder
*encoder
;
4958 struct intel_dp
*intel_dp
= NULL
;
4959 struct intel_crtc_config
*config
= NULL
;
4960 struct intel_crtc
*intel_crtc
= NULL
;
4961 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4963 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4965 if (refresh_rate
<= 0) {
4966 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4970 if (intel_connector
== NULL
) {
4971 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4976 * FIXME: This needs proper synchronization with psr state. But really
4977 * hard to tell without seeing the user of this function of this code.
4978 * Check locking and ordering once that lands.
4980 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4981 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4985 encoder
= intel_attached_encoder(&intel_connector
->base
);
4986 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4987 intel_crtc
= encoder
->new_crtc
;
4990 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4994 config
= &intel_crtc
->config
;
4996 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4997 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5001 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
5002 index
= DRRS_LOW_RR
;
5004 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
5006 "DRRS requested for previously set RR...ignoring\n");
5010 if (!intel_crtc
->active
) {
5011 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5015 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
5016 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
5017 val
= I915_READ(reg
);
5018 if (index
> DRRS_HIGH_RR
) {
5019 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5020 intel_dp_set_m_n(intel_crtc
);
5022 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5024 I915_WRITE(reg
, val
);
5028 * mutex taken to ensure that there is no race between differnt
5029 * drrs calls trying to update refresh rate. This scenario may occur
5030 * in future when idleness detection based DRRS in kernel and
5031 * possible calls from user space to set differnt RR are made.
5034 mutex_lock(&intel_dp
->drrs_state
.mutex
);
5036 intel_dp
->drrs_state
.refresh_rate_type
= index
;
5038 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
5040 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5043 static struct drm_display_mode
*
5044 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
5045 struct intel_connector
*intel_connector
,
5046 struct drm_display_mode
*fixed_mode
)
5048 struct drm_connector
*connector
= &intel_connector
->base
;
5049 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5050 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
5051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5052 struct drm_display_mode
*downclock_mode
= NULL
;
5054 if (INTEL_INFO(dev
)->gen
<= 6) {
5055 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5059 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5060 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5064 downclock_mode
= intel_find_panel_downclock
5065 (dev
, fixed_mode
, connector
);
5067 if (!downclock_mode
) {
5068 DRM_DEBUG_KMS("DRRS not supported\n");
5072 dev_priv
->drrs
.connector
= intel_connector
;
5074 mutex_init(&intel_dp
->drrs_state
.mutex
);
5076 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
5078 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
5079 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5080 return downclock_mode
;
5083 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
5085 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5087 struct intel_dp
*intel_dp
;
5088 enum intel_display_power_domain power_domain
;
5090 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
5093 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
5097 if (!edp_have_panel_vdd(intel_dp
))
5100 * The VDD bit needs a power domain reference, so if the bit is
5101 * already enabled when we boot or resume, grab this reference and
5102 * schedule a vdd off, so we don't hold on to the reference
5105 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5106 power_domain
= intel_display_port_power_domain(intel_encoder
);
5107 intel_display_power_get(dev_priv
, power_domain
);
5109 edp_panel_vdd_schedule_off(intel_dp
);
5111 pps_unlock(intel_dp
);
5114 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5115 struct intel_connector
*intel_connector
)
5117 struct drm_connector
*connector
= &intel_connector
->base
;
5118 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5119 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5120 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5122 struct drm_display_mode
*fixed_mode
= NULL
;
5123 struct drm_display_mode
*downclock_mode
= NULL
;
5125 struct drm_display_mode
*scan
;
5128 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
5130 if (!is_edp(intel_dp
))
5133 intel_edp_panel_vdd_sanitize(intel_encoder
);
5135 /* Cache DPCD and EDID for edp. */
5136 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5139 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5140 dev_priv
->no_aux_handshake
=
5141 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5142 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5144 /* if this fails, presume the device is a ghost */
5145 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5149 /* We now know it's not a ghost, init power sequence regs. */
5151 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5152 pps_unlock(intel_dp
);
5154 mutex_lock(&dev
->mode_config
.mutex
);
5155 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5157 if (drm_add_edid_modes(connector
, edid
)) {
5158 drm_mode_connector_update_edid_property(connector
,
5160 drm_edid_to_eld(connector
, edid
);
5163 edid
= ERR_PTR(-EINVAL
);
5166 edid
= ERR_PTR(-ENOENT
);
5168 intel_connector
->edid
= edid
;
5170 /* prefer fixed mode from EDID if available */
5171 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5172 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5173 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5174 downclock_mode
= intel_dp_drrs_init(
5176 intel_connector
, fixed_mode
);
5181 /* fallback to VBT if available for eDP */
5182 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5183 fixed_mode
= drm_mode_duplicate(dev
,
5184 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5186 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5188 mutex_unlock(&dev
->mode_config
.mutex
);
5190 if (IS_VALLEYVIEW(dev
)) {
5191 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5192 register_reboot_notifier(&intel_dp
->edp_notifier
);
5195 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5196 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5197 intel_panel_setup_backlight(connector
);
5203 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5204 struct intel_connector
*intel_connector
)
5206 struct drm_connector
*connector
= &intel_connector
->base
;
5207 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5208 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5209 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5211 enum port port
= intel_dig_port
->port
;
5214 intel_dp
->pps_pipe
= INVALID_PIPE
;
5216 /* intel_dp vfuncs */
5217 if (INTEL_INFO(dev
)->gen
>= 9)
5218 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5219 else if (IS_VALLEYVIEW(dev
))
5220 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5221 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5222 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5223 else if (HAS_PCH_SPLIT(dev
))
5224 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5226 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5228 if (INTEL_INFO(dev
)->gen
>= 9)
5229 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5231 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5233 /* Preserve the current hw state. */
5234 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5235 intel_dp
->attached_connector
= intel_connector
;
5237 if (intel_dp_is_edp(dev
, port
))
5238 type
= DRM_MODE_CONNECTOR_eDP
;
5240 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5243 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5244 * for DP the encoder type can be set by the caller to
5245 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5247 if (type
== DRM_MODE_CONNECTOR_eDP
)
5248 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5250 /* eDP only on port B and/or C on vlv/chv */
5251 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5252 port
!= PORT_B
&& port
!= PORT_C
))
5255 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5256 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5259 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5260 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5262 connector
->interlace_allowed
= true;
5263 connector
->doublescan_allowed
= 0;
5265 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5266 edp_panel_vdd_work
);
5268 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5269 drm_connector_register(connector
);
5272 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5274 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5275 intel_connector
->unregister
= intel_dp_connector_unregister
;
5277 /* Set up the hotplug pin. */
5280 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5283 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5286 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5289 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5295 if (is_edp(intel_dp
)) {
5297 if (IS_VALLEYVIEW(dev
)) {
5298 vlv_initial_power_sequencer_setup(intel_dp
);
5300 intel_dp_init_panel_power_timestamps(intel_dp
);
5301 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5303 pps_unlock(intel_dp
);
5306 intel_dp_aux_init(intel_dp
, intel_connector
);
5308 /* init MST on ports that can support it */
5309 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5310 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5311 intel_dp_mst_encoder_init(intel_dig_port
,
5312 intel_connector
->base
.base
.id
);
5316 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5317 drm_dp_aux_unregister(&intel_dp
->aux
);
5318 if (is_edp(intel_dp
)) {
5319 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5321 * vdd might still be enabled do to the delayed vdd off.
5322 * Make sure vdd is actually turned off here.
5325 edp_panel_vdd_off_sync(intel_dp
);
5326 pps_unlock(intel_dp
);
5328 drm_connector_unregister(connector
);
5329 drm_connector_cleanup(connector
);
5333 intel_dp_add_properties(intel_dp
, connector
);
5335 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5336 * 0xd. Failure to do so will result in spurious interrupts being
5337 * generated on the port when a cable is not attached.
5339 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5340 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5341 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5348 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5351 struct intel_digital_port
*intel_dig_port
;
5352 struct intel_encoder
*intel_encoder
;
5353 struct drm_encoder
*encoder
;
5354 struct intel_connector
*intel_connector
;
5356 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5357 if (!intel_dig_port
)
5360 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5361 if (!intel_connector
) {
5362 kfree(intel_dig_port
);
5366 intel_encoder
= &intel_dig_port
->base
;
5367 encoder
= &intel_encoder
->base
;
5369 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5370 DRM_MODE_ENCODER_TMDS
);
5372 intel_encoder
->compute_config
= intel_dp_compute_config
;
5373 intel_encoder
->disable
= intel_disable_dp
;
5374 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5375 intel_encoder
->get_config
= intel_dp_get_config
;
5376 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5377 if (IS_CHERRYVIEW(dev
)) {
5378 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5379 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5380 intel_encoder
->enable
= vlv_enable_dp
;
5381 intel_encoder
->post_disable
= chv_post_disable_dp
;
5382 } else if (IS_VALLEYVIEW(dev
)) {
5383 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5384 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5385 intel_encoder
->enable
= vlv_enable_dp
;
5386 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5388 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5389 intel_encoder
->enable
= g4x_enable_dp
;
5390 if (INTEL_INFO(dev
)->gen
>= 5)
5391 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5394 intel_dig_port
->port
= port
;
5395 intel_dig_port
->dp
.output_reg
= output_reg
;
5397 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5398 if (IS_CHERRYVIEW(dev
)) {
5400 intel_encoder
->crtc_mask
= 1 << 2;
5402 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5404 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5406 intel_encoder
->cloneable
= 0;
5407 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5409 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5410 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5412 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5413 drm_encoder_cleanup(encoder
);
5414 kfree(intel_dig_port
);
5415 kfree(intel_connector
);
5419 void intel_dp_mst_suspend(struct drm_device
*dev
)
5421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5425 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5426 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5427 if (!intel_dig_port
)
5430 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5431 if (!intel_dig_port
->dp
.can_mst
)
5433 if (intel_dig_port
->dp
.is_mst
)
5434 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5439 void intel_dp_mst_resume(struct drm_device
*dev
)
5441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5444 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5445 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5446 if (!intel_dig_port
)
5448 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5451 if (!intel_dig_port
->dp
.can_mst
)
5454 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5456 intel_dp_check_mst_status(&intel_dig_port
->dp
);