2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
294 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
298 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
300 enum port port
= intel_dig_port
->port
;
303 /* modeset should have pipe */
305 return to_intel_crtc(crtc
)->pipe
;
307 /* init time, try to find a pipe with this port selected */
308 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
309 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
310 PANEL_PORT_SELECT_MASK
;
311 if (port_sel
== PANEL_PORT_SELECT_DPB_VLV
&& port
== PORT_B
)
313 if (port_sel
== PANEL_PORT_SELECT_DPC_VLV
&& port
== PORT_C
)
321 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
323 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
325 if (HAS_PCH_SPLIT(dev
))
326 return PCH_PP_CONTROL
;
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
331 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
333 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
335 if (HAS_PCH_SPLIT(dev
))
336 return PCH_PP_STATUS
;
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
341 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
346 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
348 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 u32 pp_ctrl_reg
, pp_div_reg
;
352 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
354 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
357 if (IS_VALLEYVIEW(dev
)) {
358 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
359 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
360 pp_div
= I915_READ(pp_div_reg
);
361 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
365 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
366 msleep(intel_dp
->panel_power_cycle_delay
);
372 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
374 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
380 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
382 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
384 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
385 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
386 enum intel_display_power_domain power_domain
;
388 power_domain
= intel_display_port_power_domain(intel_encoder
);
389 return intel_display_power_enabled(dev_priv
, power_domain
) &&
390 (I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
) != 0;
394 intel_dp_check_edp(struct intel_dp
*intel_dp
)
396 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
399 if (!is_edp(intel_dp
))
402 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
405 I915_READ(_pp_stat_reg(intel_dp
)),
406 I915_READ(_pp_ctrl_reg(intel_dp
)));
411 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
413 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
414 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
416 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
420 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
422 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
423 msecs_to_jiffies_timeout(10));
425 done
= wait_for_atomic(C
, 10) == 0;
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
434 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
436 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
437 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
443 return index
? 0 : intel_hrawclk(dev
) / 2;
446 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
448 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
449 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
454 if (intel_dig_port
->port
== PORT_A
) {
455 if (IS_GEN6(dev
) || IS_GEN7(dev
))
456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
458 return 225; /* eDP input clock at 450Mhz */
460 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
464 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
466 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
467 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
470 if (intel_dig_port
->port
== PORT_A
) {
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
474 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
475 /* Workaround for non-ULT HSW */
482 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
486 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
488 return index
? 0 : 100;
491 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
494 uint32_t aux_clock_divider
)
496 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
497 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
498 uint32_t precharge
, timeout
;
505 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
506 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
508 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
510 return DP_AUX_CH_CTL_SEND_BUSY
|
512 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
513 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
515 DP_AUX_CH_CTL_RECEIVE_ERROR
|
516 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
517 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
518 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
522 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
523 uint8_t *send
, int send_bytes
,
524 uint8_t *recv
, int recv_size
)
526 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
527 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
529 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
530 uint32_t ch_data
= ch_ctl
+ 4;
531 uint32_t aux_clock_divider
;
532 int i
, ret
, recv_bytes
;
535 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
538 vdd
= _edp_panel_vdd_on(intel_dp
);
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
544 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
546 intel_dp_check_edp(intel_dp
);
548 intel_aux_display_runtime_get(dev_priv
);
550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
552 status
= I915_READ_NOTRACE(ch_ctl
);
553 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
571 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
572 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i
= 0; i
< send_bytes
; i
+= 4)
581 I915_WRITE(ch_data
+ i
,
582 pack_aux(send
+ i
, send_bytes
- i
));
584 /* Send the command and wait for it to complete */
585 I915_WRITE(ch_ctl
, send_ctl
);
587 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
589 /* Clear done status and any errors */
593 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
594 DP_AUX_CH_CTL_RECEIVE_ERROR
);
596 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
597 DP_AUX_CH_CTL_RECEIVE_ERROR
))
599 if (status
& DP_AUX_CH_CTL_DONE
)
602 if (status
& DP_AUX_CH_CTL_DONE
)
606 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
615 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
623 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
629 /* Unload any bytes sent back from the other side */
630 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
632 if (recv_bytes
> recv_size
)
633 recv_bytes
= recv_size
;
635 for (i
= 0; i
< recv_bytes
; i
+= 4)
636 unpack_aux(I915_READ(ch_data
+ i
),
637 recv
+ i
, recv_bytes
- i
);
641 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
642 intel_aux_display_runtime_put(dev_priv
);
645 edp_panel_vdd_off(intel_dp
, false);
650 #define BARE_ADDRESS_SIZE 3
651 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
653 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
655 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
656 uint8_t txbuf
[20], rxbuf
[20];
657 size_t txsize
, rxsize
;
660 txbuf
[0] = msg
->request
<< 4;
661 txbuf
[1] = msg
->address
>> 8;
662 txbuf
[2] = msg
->address
& 0xff;
663 txbuf
[3] = msg
->size
- 1;
665 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
666 case DP_AUX_NATIVE_WRITE
:
667 case DP_AUX_I2C_WRITE
:
668 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
671 if (WARN_ON(txsize
> 20))
674 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
676 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
678 msg
->reply
= rxbuf
[0] >> 4;
680 /* Return payload size. */
685 case DP_AUX_NATIVE_READ
:
686 case DP_AUX_I2C_READ
:
687 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
688 rxsize
= msg
->size
+ 1;
690 if (WARN_ON(rxsize
> 20))
693 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
695 msg
->reply
= rxbuf
[0] >> 4;
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
700 * Return payload size.
703 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
716 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
718 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
719 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
720 enum port port
= intel_dig_port
->port
;
721 const char *name
= NULL
;
726 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
730 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
734 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
738 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
746 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
748 intel_dp
->aux
.name
= name
;
749 intel_dp
->aux
.dev
= dev
->dev
;
750 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
752 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
753 connector
->base
.kdev
->kobj
.name
);
755 ret
= drm_dp_aux_register(&intel_dp
->aux
);
757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
762 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
763 &intel_dp
->aux
.ddc
.dev
.kobj
,
764 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
767 drm_dp_aux_unregister(&intel_dp
->aux
);
772 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
774 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
776 if (!intel_connector
->mst_port
)
777 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
778 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
779 intel_connector_unregister(intel_connector
);
783 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
786 case DP_LINK_BW_1_62
:
787 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
790 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
793 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
799 intel_dp_set_clock(struct intel_encoder
*encoder
,
800 struct intel_crtc_config
*pipe_config
, int link_bw
)
802 struct drm_device
*dev
= encoder
->base
.dev
;
803 const struct dp_link_dpll
*divisor
= NULL
;
808 count
= ARRAY_SIZE(gen4_dpll
);
809 } else if (HAS_PCH_SPLIT(dev
)) {
811 count
= ARRAY_SIZE(pch_dpll
);
812 } else if (IS_CHERRYVIEW(dev
)) {
814 count
= ARRAY_SIZE(chv_dpll
);
815 } else if (IS_VALLEYVIEW(dev
)) {
817 count
= ARRAY_SIZE(vlv_dpll
);
820 if (divisor
&& count
) {
821 for (i
= 0; i
< count
; i
++) {
822 if (link_bw
== divisor
[i
].link_bw
) {
823 pipe_config
->dpll
= divisor
[i
].dpll
;
824 pipe_config
->clock_set
= true;
832 intel_dp_compute_config(struct intel_encoder
*encoder
,
833 struct intel_crtc_config
*pipe_config
)
835 struct drm_device
*dev
= encoder
->base
.dev
;
836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
837 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
838 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
839 enum port port
= dp_to_dig_port(intel_dp
)->port
;
840 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
841 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
842 int lane_count
, clock
;
843 int min_lane_count
= 1;
844 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
845 /* Conveniently, the link BW constants become indices with a shift...*/
847 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
849 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
850 int link_avail
, link_clock
;
852 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
853 pipe_config
->has_pch_encoder
= true;
855 pipe_config
->has_dp_encoder
= true;
856 pipe_config
->has_drrs
= false;
857 pipe_config
->has_audio
= intel_dp
->has_audio
;
859 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
860 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
862 if (!HAS_PCH_SPLIT(dev
))
863 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
864 intel_connector
->panel
.fitting_mode
);
866 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
867 intel_connector
->panel
.fitting_mode
);
870 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
873 DRM_DEBUG_KMS("DP link computation with max lane count %i "
874 "max bw %02x pixel clock %iKHz\n",
875 max_lane_count
, bws
[max_clock
],
876 adjusted_mode
->crtc_clock
);
878 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
880 bpp
= pipe_config
->pipe_bpp
;
881 if (is_edp(intel_dp
)) {
882 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
883 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
884 dev_priv
->vbt
.edp_bpp
);
885 bpp
= dev_priv
->vbt
.edp_bpp
;
888 if (IS_BROADWELL(dev
)) {
889 /* Yes, it's an ugly hack. */
890 min_lane_count
= max_lane_count
;
891 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
893 } else if (dev_priv
->vbt
.edp_lanes
) {
894 min_lane_count
= min(dev_priv
->vbt
.edp_lanes
,
896 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
900 if (dev_priv
->vbt
.edp_rate
) {
901 min_clock
= min(dev_priv
->vbt
.edp_rate
>> 3, max_clock
);
902 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
907 for (; bpp
>= 6*3; bpp
-= 2*3) {
908 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
911 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
912 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
913 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
914 link_avail
= intel_dp_max_data_rate(link_clock
,
917 if (mode_rate
<= link_avail
) {
927 if (intel_dp
->color_range_auto
) {
930 * CEA-861-E - 5.1 Default Encoding Parameters
931 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
933 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
934 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
936 intel_dp
->color_range
= 0;
939 if (intel_dp
->color_range
)
940 pipe_config
->limited_color_range
= true;
942 intel_dp
->link_bw
= bws
[clock
];
943 intel_dp
->lane_count
= lane_count
;
944 pipe_config
->pipe_bpp
= bpp
;
945 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
947 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
948 intel_dp
->link_bw
, intel_dp
->lane_count
,
949 pipe_config
->port_clock
, bpp
);
950 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
951 mode_rate
, link_avail
);
953 intel_link_compute_m_n(bpp
, lane_count
,
954 adjusted_mode
->crtc_clock
,
955 pipe_config
->port_clock
,
956 &pipe_config
->dp_m_n
);
958 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
959 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
960 pipe_config
->has_drrs
= true;
961 intel_link_compute_m_n(bpp
, lane_count
,
962 intel_connector
->panel
.downclock_mode
->clock
,
963 pipe_config
->port_clock
,
964 &pipe_config
->dp_m2_n2
);
967 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
968 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
970 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
975 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
977 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
978 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
979 struct drm_device
*dev
= crtc
->base
.dev
;
980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
983 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
984 dpa_ctl
= I915_READ(DP_A
);
985 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
987 if (crtc
->config
.port_clock
== 162000) {
988 /* For a long time we've carried around a ILK-DevA w/a for the
989 * 160MHz clock. If we're really unlucky, it's still required.
991 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
992 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
993 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
995 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
996 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
999 I915_WRITE(DP_A
, dpa_ctl
);
1005 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1007 struct drm_device
*dev
= encoder
->base
.dev
;
1008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1009 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1010 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1011 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1012 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1015 * There are four kinds of DP registers:
1022 * IBX PCH and CPU are the same for almost everything,
1023 * except that the CPU DP PLL is configured in this
1026 * CPT PCH is quite different, having many bits moved
1027 * to the TRANS_DP_CTL register instead. That
1028 * configuration happens (oddly) in ironlake_pch_enable
1031 /* Preserve the BIOS-computed detected bit. This is
1032 * supposed to be read-only.
1034 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1036 /* Handle DP bits in common between all three register formats */
1037 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1038 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1040 if (crtc
->config
.has_audio
) {
1041 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1042 pipe_name(crtc
->pipe
));
1043 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1044 intel_write_eld(&encoder
->base
, adjusted_mode
);
1047 /* Split out the IBX/CPU vs CPT settings */
1049 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1050 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1051 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1052 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1053 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1054 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1056 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1057 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1059 intel_dp
->DP
|= crtc
->pipe
<< 29;
1060 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1061 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1062 intel_dp
->DP
|= intel_dp
->color_range
;
1064 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1065 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1066 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1067 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1068 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1070 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1071 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1073 if (!IS_CHERRYVIEW(dev
)) {
1074 if (crtc
->pipe
== 1)
1075 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1077 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1080 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1084 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1085 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1087 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1088 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1090 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1091 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1093 static void wait_panel_status(struct intel_dp
*intel_dp
,
1097 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1099 u32 pp_stat_reg
, pp_ctrl_reg
;
1101 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1102 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1104 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1106 I915_READ(pp_stat_reg
),
1107 I915_READ(pp_ctrl_reg
));
1109 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1110 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1111 I915_READ(pp_stat_reg
),
1112 I915_READ(pp_ctrl_reg
));
1115 DRM_DEBUG_KMS("Wait complete\n");
1118 static void wait_panel_on(struct intel_dp
*intel_dp
)
1120 DRM_DEBUG_KMS("Wait for panel power on\n");
1121 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1124 static void wait_panel_off(struct intel_dp
*intel_dp
)
1126 DRM_DEBUG_KMS("Wait for panel power off time\n");
1127 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1130 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1132 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1134 /* When we disable the VDD override bit last we have to do the manual
1136 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1137 intel_dp
->panel_power_cycle_delay
);
1139 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1142 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1144 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1145 intel_dp
->backlight_on_delay
);
1148 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1150 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1151 intel_dp
->backlight_off_delay
);
1154 /* Read the current pp_control value, unlocking the register if it
1158 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1160 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1164 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1165 control
&= ~PANEL_UNLOCK_MASK
;
1166 control
|= PANEL_UNLOCK_REGS
;
1170 static bool _edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1172 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1173 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1174 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1176 enum intel_display_power_domain power_domain
;
1178 u32 pp_stat_reg
, pp_ctrl_reg
;
1179 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1181 if (!is_edp(intel_dp
))
1184 intel_dp
->want_panel_vdd
= true;
1186 if (edp_have_panel_vdd(intel_dp
))
1187 return need_to_disable
;
1189 power_domain
= intel_display_port_power_domain(intel_encoder
);
1190 intel_display_power_get(dev_priv
, power_domain
);
1192 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1194 if (!edp_have_panel_power(intel_dp
))
1195 wait_panel_power_cycle(intel_dp
);
1197 pp
= ironlake_get_pp_control(intel_dp
);
1198 pp
|= EDP_FORCE_VDD
;
1200 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1201 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1203 I915_WRITE(pp_ctrl_reg
, pp
);
1204 POSTING_READ(pp_ctrl_reg
);
1205 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1206 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1208 * If the panel wasn't on, delay before accessing aux channel
1210 if (!edp_have_panel_power(intel_dp
)) {
1211 DRM_DEBUG_KMS("eDP was not running\n");
1212 msleep(intel_dp
->panel_power_up_delay
);
1215 return need_to_disable
;
1218 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1220 if (is_edp(intel_dp
)) {
1221 bool vdd
= _edp_panel_vdd_on(intel_dp
);
1223 WARN(!vdd
, "eDP VDD already requested on\n");
1227 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1229 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1232 u32 pp_stat_reg
, pp_ctrl_reg
;
1234 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1236 if (!intel_dp
->want_panel_vdd
&& edp_have_panel_vdd(intel_dp
)) {
1237 struct intel_digital_port
*intel_dig_port
=
1238 dp_to_dig_port(intel_dp
);
1239 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1240 enum intel_display_power_domain power_domain
;
1242 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1244 pp
= ironlake_get_pp_control(intel_dp
);
1245 pp
&= ~EDP_FORCE_VDD
;
1247 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1248 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1250 I915_WRITE(pp_ctrl_reg
, pp
);
1251 POSTING_READ(pp_ctrl_reg
);
1253 /* Make sure sequencer is idle before allowing subsequent activity */
1254 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1255 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1257 if ((pp
& POWER_TARGET_ON
) == 0)
1258 intel_dp
->last_power_cycle
= jiffies
;
1260 power_domain
= intel_display_port_power_domain(intel_encoder
);
1261 intel_display_power_put(dev_priv
, power_domain
);
1265 static void edp_panel_vdd_work(struct work_struct
*__work
)
1267 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1268 struct intel_dp
, panel_vdd_work
);
1269 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1271 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
1272 edp_panel_vdd_off_sync(intel_dp
);
1273 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
1276 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1278 unsigned long delay
;
1281 * Queue the timer to fire a long time from now (relative to the power
1282 * down delay) to keep the panel power up across a sequence of
1285 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1286 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1289 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1291 if (!is_edp(intel_dp
))
1294 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1296 intel_dp
->want_panel_vdd
= false;
1299 edp_panel_vdd_off_sync(intel_dp
);
1301 edp_panel_vdd_schedule_off(intel_dp
);
1304 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1306 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1311 if (!is_edp(intel_dp
))
1314 DRM_DEBUG_KMS("Turn eDP power on\n");
1316 if (edp_have_panel_power(intel_dp
)) {
1317 DRM_DEBUG_KMS("eDP power already on\n");
1321 wait_panel_power_cycle(intel_dp
);
1323 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1324 pp
= ironlake_get_pp_control(intel_dp
);
1326 /* ILK workaround: disable reset around power sequence */
1327 pp
&= ~PANEL_POWER_RESET
;
1328 I915_WRITE(pp_ctrl_reg
, pp
);
1329 POSTING_READ(pp_ctrl_reg
);
1332 pp
|= POWER_TARGET_ON
;
1334 pp
|= PANEL_POWER_RESET
;
1336 I915_WRITE(pp_ctrl_reg
, pp
);
1337 POSTING_READ(pp_ctrl_reg
);
1339 wait_panel_on(intel_dp
);
1340 intel_dp
->last_power_on
= jiffies
;
1343 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1344 I915_WRITE(pp_ctrl_reg
, pp
);
1345 POSTING_READ(pp_ctrl_reg
);
1349 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1351 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1352 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1353 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1355 enum intel_display_power_domain power_domain
;
1359 if (!is_edp(intel_dp
))
1362 DRM_DEBUG_KMS("Turn eDP power off\n");
1364 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1366 pp
= ironlake_get_pp_control(intel_dp
);
1367 /* We need to switch off panel power _and_ force vdd, for otherwise some
1368 * panels get very unhappy and cease to work. */
1369 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1372 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1374 intel_dp
->want_panel_vdd
= false;
1376 I915_WRITE(pp_ctrl_reg
, pp
);
1377 POSTING_READ(pp_ctrl_reg
);
1379 intel_dp
->last_power_cycle
= jiffies
;
1380 wait_panel_off(intel_dp
);
1382 /* We got a reference when we enabled the VDD. */
1383 power_domain
= intel_display_port_power_domain(intel_encoder
);
1384 intel_display_power_put(dev_priv
, power_domain
);
1387 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1389 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1390 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1395 if (!is_edp(intel_dp
))
1398 DRM_DEBUG_KMS("\n");
1400 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1403 * If we enable the backlight right away following a panel power
1404 * on, we may see slight flicker as the panel syncs with the eDP
1405 * link. So delay a bit to make sure the image is solid before
1406 * allowing it to appear.
1408 wait_backlight_on(intel_dp
);
1409 pp
= ironlake_get_pp_control(intel_dp
);
1410 pp
|= EDP_BLC_ENABLE
;
1412 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1414 I915_WRITE(pp_ctrl_reg
, pp
);
1415 POSTING_READ(pp_ctrl_reg
);
1418 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1420 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1425 if (!is_edp(intel_dp
))
1428 DRM_DEBUG_KMS("\n");
1429 pp
= ironlake_get_pp_control(intel_dp
);
1430 pp
&= ~EDP_BLC_ENABLE
;
1432 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1434 I915_WRITE(pp_ctrl_reg
, pp
);
1435 POSTING_READ(pp_ctrl_reg
);
1436 intel_dp
->last_backlight_off
= jiffies
;
1438 edp_wait_backlight_off(intel_dp
);
1440 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1443 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1445 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1446 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1447 struct drm_device
*dev
= crtc
->dev
;
1448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1451 assert_pipe_disabled(dev_priv
,
1452 to_intel_crtc(crtc
)->pipe
);
1454 DRM_DEBUG_KMS("\n");
1455 dpa_ctl
= I915_READ(DP_A
);
1456 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1457 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1459 /* We don't adjust intel_dp->DP while tearing down the link, to
1460 * facilitate link retraining (e.g. after hotplug). Hence clear all
1461 * enable bits here to ensure that we don't enable too much. */
1462 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1463 intel_dp
->DP
|= DP_PLL_ENABLE
;
1464 I915_WRITE(DP_A
, intel_dp
->DP
);
1469 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1471 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1472 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1473 struct drm_device
*dev
= crtc
->dev
;
1474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1477 assert_pipe_disabled(dev_priv
,
1478 to_intel_crtc(crtc
)->pipe
);
1480 dpa_ctl
= I915_READ(DP_A
);
1481 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1482 "dp pll off, should be on\n");
1483 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1485 /* We can't rely on the value tracked for the DP register in
1486 * intel_dp->DP because link_down must not change that (otherwise link
1487 * re-training will fail. */
1488 dpa_ctl
&= ~DP_PLL_ENABLE
;
1489 I915_WRITE(DP_A
, dpa_ctl
);
1494 /* If the sink supports it, try to set the power state appropriately */
1495 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1499 /* Should have a valid DPCD by this point */
1500 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1503 if (mode
!= DRM_MODE_DPMS_ON
) {
1504 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1507 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1510 * When turning on, we need to retry for 1ms to give the sink
1513 for (i
= 0; i
< 3; i
++) {
1514 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1523 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1526 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1527 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1528 struct drm_device
*dev
= encoder
->base
.dev
;
1529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1530 enum intel_display_power_domain power_domain
;
1533 power_domain
= intel_display_port_power_domain(encoder
);
1534 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1537 tmp
= I915_READ(intel_dp
->output_reg
);
1539 if (!(tmp
& DP_PORT_EN
))
1542 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1543 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1544 } else if (IS_CHERRYVIEW(dev
)) {
1545 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1546 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1547 *pipe
= PORT_TO_PIPE(tmp
);
1553 switch (intel_dp
->output_reg
) {
1555 trans_sel
= TRANS_DP_PORT_SEL_B
;
1558 trans_sel
= TRANS_DP_PORT_SEL_C
;
1561 trans_sel
= TRANS_DP_PORT_SEL_D
;
1568 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1569 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1575 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1576 intel_dp
->output_reg
);
1582 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1583 struct intel_crtc_config
*pipe_config
)
1585 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1587 struct drm_device
*dev
= encoder
->base
.dev
;
1588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1589 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1590 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1593 tmp
= I915_READ(intel_dp
->output_reg
);
1594 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1595 pipe_config
->has_audio
= true;
1597 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1598 if (tmp
& DP_SYNC_HS_HIGH
)
1599 flags
|= DRM_MODE_FLAG_PHSYNC
;
1601 flags
|= DRM_MODE_FLAG_NHSYNC
;
1603 if (tmp
& DP_SYNC_VS_HIGH
)
1604 flags
|= DRM_MODE_FLAG_PVSYNC
;
1606 flags
|= DRM_MODE_FLAG_NVSYNC
;
1608 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1609 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1610 flags
|= DRM_MODE_FLAG_PHSYNC
;
1612 flags
|= DRM_MODE_FLAG_NHSYNC
;
1614 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1615 flags
|= DRM_MODE_FLAG_PVSYNC
;
1617 flags
|= DRM_MODE_FLAG_NVSYNC
;
1620 pipe_config
->adjusted_mode
.flags
|= flags
;
1622 pipe_config
->has_dp_encoder
= true;
1624 intel_dp_get_m_n(crtc
, pipe_config
);
1626 if (port
== PORT_A
) {
1627 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1628 pipe_config
->port_clock
= 162000;
1630 pipe_config
->port_clock
= 270000;
1633 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1634 &pipe_config
->dp_m_n
);
1636 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1637 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1639 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1641 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1642 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1644 * This is a big fat ugly hack.
1646 * Some machines in UEFI boot mode provide us a VBT that has 18
1647 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1648 * unknown we fail to light up. Yet the same BIOS boots up with
1649 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1650 * max, not what it tells us to use.
1652 * Note: This will still be broken if the eDP panel is not lit
1653 * up by the BIOS, and thus we can't get the mode at module
1656 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1657 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1658 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1662 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1664 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1667 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1674 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1677 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1678 struct edp_vsc_psr
*vsc_psr
)
1680 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1681 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1683 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1684 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1685 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1686 uint32_t *data
= (uint32_t *) vsc_psr
;
1689 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1690 the video DIP being updated before program video DIP data buffer
1691 registers for DIP being updated. */
1692 I915_WRITE(ctl_reg
, 0);
1693 POSTING_READ(ctl_reg
);
1695 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1696 if (i
< sizeof(struct edp_vsc_psr
))
1697 I915_WRITE(data_reg
+ i
, *data
++);
1699 I915_WRITE(data_reg
+ i
, 0);
1702 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1703 POSTING_READ(ctl_reg
);
1706 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
1708 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1710 struct edp_vsc_psr psr_vsc
;
1712 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1713 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
1714 psr_vsc
.sdp_header
.HB0
= 0;
1715 psr_vsc
.sdp_header
.HB1
= 0x7;
1716 psr_vsc
.sdp_header
.HB2
= 0x2;
1717 psr_vsc
.sdp_header
.HB3
= 0x8;
1718 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
1720 /* Avoid continuous PSR exit by masking memup and hpd */
1721 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
1722 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
1725 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
1727 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1728 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1730 uint32_t aux_clock_divider
;
1731 int precharge
= 0x3;
1732 int msg_size
= 5; /* Header(4) + Message(1) */
1733 bool only_standby
= false;
1735 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
1737 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1738 only_standby
= true;
1740 /* Enable PSR in sink */
1741 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
1742 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1743 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
1745 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
1746 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
1748 /* Setup AUX registers */
1749 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
1750 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
1751 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
1752 DP_AUX_CH_CTL_TIME_OUT_400us
|
1753 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
1754 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
1755 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
1758 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
1760 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1761 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1763 uint32_t max_sleep_time
= 0x1f;
1764 uint32_t idle_frames
= 1;
1766 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
1767 bool only_standby
= false;
1769 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
1770 only_standby
= true;
1772 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
1773 val
|= EDP_PSR_LINK_STANDBY
;
1774 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
1775 val
|= EDP_PSR_TP1_TIME_0us
;
1776 val
|= EDP_PSR_SKIP_AUX_EXIT
;
1777 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
1779 val
|= EDP_PSR_LINK_DISABLE
;
1781 I915_WRITE(EDP_PSR_CTL(dev
), val
|
1782 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
1783 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
1784 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
1788 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
1790 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1791 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1793 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
1794 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1796 lockdep_assert_held(&dev_priv
->psr
.lock
);
1797 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
1798 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
1800 dev_priv
->psr
.source_ok
= false;
1802 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
1803 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1807 if (!i915
.enable_psr
) {
1808 DRM_DEBUG_KMS("PSR disable by flag\n");
1812 /* Below limitations aren't valid for Broadwell */
1813 if (IS_BROADWELL(dev
))
1816 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
1818 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1822 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
1823 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1828 dev_priv
->psr
.source_ok
= true;
1832 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
1834 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1835 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1838 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1839 WARN_ON(dev_priv
->psr
.active
);
1840 lockdep_assert_held(&dev_priv
->psr
.lock
);
1842 /* Enable PSR on the panel */
1843 intel_edp_psr_enable_sink(intel_dp
);
1845 /* Enable PSR on the host */
1846 intel_edp_psr_enable_source(intel_dp
);
1848 dev_priv
->psr
.active
= true;
1851 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
1853 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1856 if (!HAS_PSR(dev
)) {
1857 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1861 if (!is_edp_psr(intel_dp
)) {
1862 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1866 mutex_lock(&dev_priv
->psr
.lock
);
1867 if (dev_priv
->psr
.enabled
) {
1868 DRM_DEBUG_KMS("PSR already in use\n");
1869 mutex_unlock(&dev_priv
->psr
.lock
);
1873 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
1875 /* Setup PSR once */
1876 intel_edp_psr_setup(intel_dp
);
1878 if (intel_edp_psr_match_conditions(intel_dp
))
1879 dev_priv
->psr
.enabled
= intel_dp
;
1880 mutex_unlock(&dev_priv
->psr
.lock
);
1883 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
1885 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1888 mutex_lock(&dev_priv
->psr
.lock
);
1889 if (!dev_priv
->psr
.enabled
) {
1890 mutex_unlock(&dev_priv
->psr
.lock
);
1894 if (dev_priv
->psr
.active
) {
1895 I915_WRITE(EDP_PSR_CTL(dev
),
1896 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
1898 /* Wait till PSR is idle */
1899 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
1900 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
1901 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1903 dev_priv
->psr
.active
= false;
1905 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
1908 dev_priv
->psr
.enabled
= NULL
;
1909 mutex_unlock(&dev_priv
->psr
.lock
);
1911 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
1914 static void intel_edp_psr_work(struct work_struct
*work
)
1916 struct drm_i915_private
*dev_priv
=
1917 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
1918 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
1920 mutex_lock(&dev_priv
->psr
.lock
);
1921 intel_dp
= dev_priv
->psr
.enabled
;
1927 * The delayed work can race with an invalidate hence we need to
1928 * recheck. Since psr_flush first clears this and then reschedules we
1929 * won't ever miss a flush when bailing out here.
1931 if (dev_priv
->psr
.busy_frontbuffer_bits
)
1934 intel_edp_psr_do_enable(intel_dp
);
1936 mutex_unlock(&dev_priv
->psr
.lock
);
1939 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
1941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1943 if (dev_priv
->psr
.active
) {
1944 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
1946 WARN_ON(!(val
& EDP_PSR_ENABLE
));
1948 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
1950 dev_priv
->psr
.active
= false;
1955 void intel_edp_psr_invalidate(struct drm_device
*dev
,
1956 unsigned frontbuffer_bits
)
1958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1959 struct drm_crtc
*crtc
;
1962 mutex_lock(&dev_priv
->psr
.lock
);
1963 if (!dev_priv
->psr
.enabled
) {
1964 mutex_unlock(&dev_priv
->psr
.lock
);
1968 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
1969 pipe
= to_intel_crtc(crtc
)->pipe
;
1971 intel_edp_psr_do_exit(dev
);
1973 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
1975 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
1976 mutex_unlock(&dev_priv
->psr
.lock
);
1979 void intel_edp_psr_flush(struct drm_device
*dev
,
1980 unsigned frontbuffer_bits
)
1982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1983 struct drm_crtc
*crtc
;
1986 mutex_lock(&dev_priv
->psr
.lock
);
1987 if (!dev_priv
->psr
.enabled
) {
1988 mutex_unlock(&dev_priv
->psr
.lock
);
1992 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
1993 pipe
= to_intel_crtc(crtc
)->pipe
;
1994 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
1997 * On Haswell sprite plane updates don't result in a psr invalidating
1998 * signal in the hardware. Which means we need to manually fake this in
1999 * software for all flushes, not just when we've seen a preceding
2000 * invalidation through frontbuffer rendering.
2002 if (IS_HASWELL(dev
) &&
2003 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2004 intel_edp_psr_do_exit(dev
);
2006 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2007 schedule_delayed_work(&dev_priv
->psr
.work
,
2008 msecs_to_jiffies(100));
2009 mutex_unlock(&dev_priv
->psr
.lock
);
2012 void intel_edp_psr_init(struct drm_device
*dev
)
2014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2016 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2017 mutex_init(&dev_priv
->psr
.lock
);
2020 static void intel_disable_dp(struct intel_encoder
*encoder
)
2022 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2023 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2024 struct drm_device
*dev
= encoder
->base
.dev
;
2026 /* Make sure the panel is off before trying to change the mode. But also
2027 * ensure that we have vdd while we switch off the panel. */
2028 intel_edp_panel_vdd_on(intel_dp
);
2029 intel_edp_backlight_off(intel_dp
);
2030 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2031 intel_edp_panel_off(intel_dp
);
2033 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2034 if (!(port
== PORT_A
|| IS_VALLEYVIEW(dev
)))
2035 intel_dp_link_down(intel_dp
);
2038 static void g4x_post_disable_dp(struct intel_encoder
*encoder
)
2040 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2041 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2046 intel_dp_link_down(intel_dp
);
2047 ironlake_edp_pll_off(intel_dp
);
2050 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2052 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2054 intel_dp_link_down(intel_dp
);
2057 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2059 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2060 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2061 struct drm_device
*dev
= encoder
->base
.dev
;
2062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2063 struct intel_crtc
*intel_crtc
=
2064 to_intel_crtc(encoder
->base
.crtc
);
2065 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2066 enum pipe pipe
= intel_crtc
->pipe
;
2069 intel_dp_link_down(intel_dp
);
2071 mutex_lock(&dev_priv
->dpio_lock
);
2073 /* Propagate soft reset to data lane reset */
2074 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2075 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2076 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2078 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2079 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2080 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2082 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2083 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2084 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2086 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2087 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2088 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2090 mutex_unlock(&dev_priv
->dpio_lock
);
2093 static void intel_enable_dp(struct intel_encoder
*encoder
)
2095 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2096 struct drm_device
*dev
= encoder
->base
.dev
;
2097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2098 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2100 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2103 intel_edp_panel_vdd_on(intel_dp
);
2104 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2105 intel_dp_start_link_train(intel_dp
);
2106 intel_edp_panel_on(intel_dp
);
2107 edp_panel_vdd_off(intel_dp
, true);
2108 intel_dp_complete_link_train(intel_dp
);
2109 intel_dp_stop_link_train(intel_dp
);
2112 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2114 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2116 intel_enable_dp(encoder
);
2117 intel_edp_backlight_on(intel_dp
);
2120 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2122 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2124 intel_edp_backlight_on(intel_dp
);
2127 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2129 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2130 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2132 intel_dp_prepare(encoder
);
2134 /* Only ilk+ has port A */
2135 if (dport
->port
== PORT_A
) {
2136 ironlake_set_pll_cpu_edp(intel_dp
);
2137 ironlake_edp_pll_on(intel_dp
);
2141 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2143 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2144 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2145 struct drm_device
*dev
= encoder
->base
.dev
;
2146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2147 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2148 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2149 int pipe
= intel_crtc
->pipe
;
2150 struct edp_power_seq power_seq
;
2153 mutex_lock(&dev_priv
->dpio_lock
);
2155 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2162 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2163 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2164 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2166 mutex_unlock(&dev_priv
->dpio_lock
);
2168 if (is_edp(intel_dp
)) {
2169 /* init power sequencer on this pipe and port */
2170 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2171 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2175 intel_enable_dp(encoder
);
2177 vlv_wait_port_ready(dev_priv
, dport
);
2180 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2182 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2183 struct drm_device
*dev
= encoder
->base
.dev
;
2184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2185 struct intel_crtc
*intel_crtc
=
2186 to_intel_crtc(encoder
->base
.crtc
);
2187 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2188 int pipe
= intel_crtc
->pipe
;
2190 intel_dp_prepare(encoder
);
2192 /* Program Tx lane resets to default */
2193 mutex_lock(&dev_priv
->dpio_lock
);
2194 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2195 DPIO_PCS_TX_LANE2_RESET
|
2196 DPIO_PCS_TX_LANE1_RESET
);
2197 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2198 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2199 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2200 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2201 DPIO_PCS_CLK_SOFT_RESET
);
2203 /* Fix up inter-pair skew failure */
2204 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2205 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2206 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2207 mutex_unlock(&dev_priv
->dpio_lock
);
2210 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2212 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2213 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2214 struct drm_device
*dev
= encoder
->base
.dev
;
2215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2216 struct edp_power_seq power_seq
;
2217 struct intel_crtc
*intel_crtc
=
2218 to_intel_crtc(encoder
->base
.crtc
);
2219 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2220 int pipe
= intel_crtc
->pipe
;
2224 mutex_lock(&dev_priv
->dpio_lock
);
2226 /* Deassert soft data lane reset*/
2227 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2228 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2229 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2231 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2232 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2233 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2235 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2236 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2237 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2239 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2240 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2241 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2243 /* Program Tx lane latency optimal setting*/
2244 for (i
= 0; i
< 4; i
++) {
2245 /* Set the latency optimal bit */
2246 data
= (i
== 1) ? 0x0 : 0x6;
2247 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2248 data
<< DPIO_FRC_LATENCY_SHFIT
);
2250 /* Set the upar bit */
2251 data
= (i
== 1) ? 0x0 : 0x1;
2252 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2253 data
<< DPIO_UPAR_SHIFT
);
2256 /* Data lane stagger programming */
2257 /* FIXME: Fix up value only after power analysis */
2259 mutex_unlock(&dev_priv
->dpio_lock
);
2261 if (is_edp(intel_dp
)) {
2262 /* init power sequencer on this pipe and port */
2263 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2264 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2268 intel_enable_dp(encoder
);
2270 vlv_wait_port_ready(dev_priv
, dport
);
2273 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2275 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2276 struct drm_device
*dev
= encoder
->base
.dev
;
2277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2278 struct intel_crtc
*intel_crtc
=
2279 to_intel_crtc(encoder
->base
.crtc
);
2280 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2281 enum pipe pipe
= intel_crtc
->pipe
;
2284 intel_dp_prepare(encoder
);
2286 mutex_lock(&dev_priv
->dpio_lock
);
2288 /* program left/right clock distribution */
2289 if (pipe
!= PIPE_B
) {
2290 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2291 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2293 val
|= CHV_BUFLEFTENA1_FORCE
;
2295 val
|= CHV_BUFRIGHTENA1_FORCE
;
2296 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2298 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2299 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2301 val
|= CHV_BUFLEFTENA2_FORCE
;
2303 val
|= CHV_BUFRIGHTENA2_FORCE
;
2304 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2307 /* program clock channel usage */
2308 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2309 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2311 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2313 val
|= CHV_PCS_USEDCLKCHANNEL
;
2314 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2316 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2317 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2319 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2321 val
|= CHV_PCS_USEDCLKCHANNEL
;
2322 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2325 * This a a bit weird since generally CL
2326 * matches the pipe, but here we need to
2327 * pick the CL based on the port.
2329 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2331 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2333 val
|= CHV_CMN_USEDCLKCHANNEL
;
2334 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2336 mutex_unlock(&dev_priv
->dpio_lock
);
2340 * Native read with retry for link status and receiver capability reads for
2341 * cases where the sink may still be asleep.
2343 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2344 * supposed to retry 3 times per the spec.
2347 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2348 void *buffer
, size_t size
)
2353 for (i
= 0; i
< 3; i
++) {
2354 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2364 * Fetch AUX CH registers 0x202 - 0x207 which contain
2365 * link status information
2368 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2370 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2373 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2376 /* These are source-specific values. */
2378 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2380 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2381 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2383 if (IS_VALLEYVIEW(dev
))
2384 return DP_TRAIN_VOLTAGE_SWING_1200
;
2385 else if (IS_GEN7(dev
) && port
== PORT_A
)
2386 return DP_TRAIN_VOLTAGE_SWING_800
;
2387 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2388 return DP_TRAIN_VOLTAGE_SWING_1200
;
2390 return DP_TRAIN_VOLTAGE_SWING_800
;
2394 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2396 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2397 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2399 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2400 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2401 case DP_TRAIN_VOLTAGE_SWING_400
:
2402 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2403 case DP_TRAIN_VOLTAGE_SWING_600
:
2404 return DP_TRAIN_PRE_EMPHASIS_6
;
2405 case DP_TRAIN_VOLTAGE_SWING_800
:
2406 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2407 case DP_TRAIN_VOLTAGE_SWING_1200
:
2409 return DP_TRAIN_PRE_EMPHASIS_0
;
2411 } else if (IS_VALLEYVIEW(dev
)) {
2412 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2413 case DP_TRAIN_VOLTAGE_SWING_400
:
2414 return DP_TRAIN_PRE_EMPHASIS_9_5
;
2415 case DP_TRAIN_VOLTAGE_SWING_600
:
2416 return DP_TRAIN_PRE_EMPHASIS_6
;
2417 case DP_TRAIN_VOLTAGE_SWING_800
:
2418 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2419 case DP_TRAIN_VOLTAGE_SWING_1200
:
2421 return DP_TRAIN_PRE_EMPHASIS_0
;
2423 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2424 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2425 case DP_TRAIN_VOLTAGE_SWING_400
:
2426 return DP_TRAIN_PRE_EMPHASIS_6
;
2427 case DP_TRAIN_VOLTAGE_SWING_600
:
2428 case DP_TRAIN_VOLTAGE_SWING_800
:
2429 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2431 return DP_TRAIN_PRE_EMPHASIS_0
;
2434 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2435 case DP_TRAIN_VOLTAGE_SWING_400
:
2436 return DP_TRAIN_PRE_EMPHASIS_6
;
2437 case DP_TRAIN_VOLTAGE_SWING_600
:
2438 return DP_TRAIN_PRE_EMPHASIS_6
;
2439 case DP_TRAIN_VOLTAGE_SWING_800
:
2440 return DP_TRAIN_PRE_EMPHASIS_3_5
;
2441 case DP_TRAIN_VOLTAGE_SWING_1200
:
2443 return DP_TRAIN_PRE_EMPHASIS_0
;
2448 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2450 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2452 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2453 struct intel_crtc
*intel_crtc
=
2454 to_intel_crtc(dport
->base
.base
.crtc
);
2455 unsigned long demph_reg_value
, preemph_reg_value
,
2456 uniqtranscale_reg_value
;
2457 uint8_t train_set
= intel_dp
->train_set
[0];
2458 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2459 int pipe
= intel_crtc
->pipe
;
2461 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2462 case DP_TRAIN_PRE_EMPHASIS_0
:
2463 preemph_reg_value
= 0x0004000;
2464 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2465 case DP_TRAIN_VOLTAGE_SWING_400
:
2466 demph_reg_value
= 0x2B405555;
2467 uniqtranscale_reg_value
= 0x552AB83A;
2469 case DP_TRAIN_VOLTAGE_SWING_600
:
2470 demph_reg_value
= 0x2B404040;
2471 uniqtranscale_reg_value
= 0x5548B83A;
2473 case DP_TRAIN_VOLTAGE_SWING_800
:
2474 demph_reg_value
= 0x2B245555;
2475 uniqtranscale_reg_value
= 0x5560B83A;
2477 case DP_TRAIN_VOLTAGE_SWING_1200
:
2478 demph_reg_value
= 0x2B405555;
2479 uniqtranscale_reg_value
= 0x5598DA3A;
2485 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2486 preemph_reg_value
= 0x0002000;
2487 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2488 case DP_TRAIN_VOLTAGE_SWING_400
:
2489 demph_reg_value
= 0x2B404040;
2490 uniqtranscale_reg_value
= 0x5552B83A;
2492 case DP_TRAIN_VOLTAGE_SWING_600
:
2493 demph_reg_value
= 0x2B404848;
2494 uniqtranscale_reg_value
= 0x5580B83A;
2496 case DP_TRAIN_VOLTAGE_SWING_800
:
2497 demph_reg_value
= 0x2B404040;
2498 uniqtranscale_reg_value
= 0x55ADDA3A;
2504 case DP_TRAIN_PRE_EMPHASIS_6
:
2505 preemph_reg_value
= 0x0000000;
2506 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2507 case DP_TRAIN_VOLTAGE_SWING_400
:
2508 demph_reg_value
= 0x2B305555;
2509 uniqtranscale_reg_value
= 0x5570B83A;
2511 case DP_TRAIN_VOLTAGE_SWING_600
:
2512 demph_reg_value
= 0x2B2B4040;
2513 uniqtranscale_reg_value
= 0x55ADDA3A;
2519 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2520 preemph_reg_value
= 0x0006000;
2521 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2522 case DP_TRAIN_VOLTAGE_SWING_400
:
2523 demph_reg_value
= 0x1B405555;
2524 uniqtranscale_reg_value
= 0x55ADDA3A;
2534 mutex_lock(&dev_priv
->dpio_lock
);
2535 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2536 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2537 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2538 uniqtranscale_reg_value
);
2539 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2540 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2541 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2542 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2543 mutex_unlock(&dev_priv
->dpio_lock
);
2548 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2550 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2552 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2553 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2554 u32 deemph_reg_value
, margin_reg_value
, val
;
2555 uint8_t train_set
= intel_dp
->train_set
[0];
2556 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2557 enum pipe pipe
= intel_crtc
->pipe
;
2560 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2561 case DP_TRAIN_PRE_EMPHASIS_0
:
2562 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2563 case DP_TRAIN_VOLTAGE_SWING_400
:
2564 deemph_reg_value
= 128;
2565 margin_reg_value
= 52;
2567 case DP_TRAIN_VOLTAGE_SWING_600
:
2568 deemph_reg_value
= 128;
2569 margin_reg_value
= 77;
2571 case DP_TRAIN_VOLTAGE_SWING_800
:
2572 deemph_reg_value
= 128;
2573 margin_reg_value
= 102;
2575 case DP_TRAIN_VOLTAGE_SWING_1200
:
2576 deemph_reg_value
= 128;
2577 margin_reg_value
= 154;
2578 /* FIXME extra to set for 1200 */
2584 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2585 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2586 case DP_TRAIN_VOLTAGE_SWING_400
:
2587 deemph_reg_value
= 85;
2588 margin_reg_value
= 78;
2590 case DP_TRAIN_VOLTAGE_SWING_600
:
2591 deemph_reg_value
= 85;
2592 margin_reg_value
= 116;
2594 case DP_TRAIN_VOLTAGE_SWING_800
:
2595 deemph_reg_value
= 85;
2596 margin_reg_value
= 154;
2602 case DP_TRAIN_PRE_EMPHASIS_6
:
2603 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2604 case DP_TRAIN_VOLTAGE_SWING_400
:
2605 deemph_reg_value
= 64;
2606 margin_reg_value
= 104;
2608 case DP_TRAIN_VOLTAGE_SWING_600
:
2609 deemph_reg_value
= 64;
2610 margin_reg_value
= 154;
2616 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2617 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2618 case DP_TRAIN_VOLTAGE_SWING_400
:
2619 deemph_reg_value
= 43;
2620 margin_reg_value
= 154;
2630 mutex_lock(&dev_priv
->dpio_lock
);
2632 /* Clear calc init */
2633 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2634 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2635 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2637 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2638 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2639 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2641 /* Program swing deemph */
2642 for (i
= 0; i
< 4; i
++) {
2643 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2644 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2645 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2646 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2649 /* Program swing margin */
2650 for (i
= 0; i
< 4; i
++) {
2651 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2652 val
&= ~DPIO_SWING_MARGIN000_MASK
;
2653 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
2654 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2657 /* Disable unique transition scale */
2658 for (i
= 0; i
< 4; i
++) {
2659 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2660 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2661 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2664 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
2665 == DP_TRAIN_PRE_EMPHASIS_0
) &&
2666 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
2667 == DP_TRAIN_VOLTAGE_SWING_1200
)) {
2670 * The document said it needs to set bit 27 for ch0 and bit 26
2671 * for ch1. Might be a typo in the doc.
2672 * For now, for this unique transition scale selection, set bit
2673 * 27 for ch0 and ch1.
2675 for (i
= 0; i
< 4; i
++) {
2676 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2677 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2678 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
2681 for (i
= 0; i
< 4; i
++) {
2682 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2683 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2684 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
2685 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2689 /* Start swing calculation */
2690 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2691 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2692 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2694 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2695 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
2696 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2699 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
2700 val
|= DPIO_LRC_BYPASS
;
2701 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
2703 mutex_unlock(&dev_priv
->dpio_lock
);
2709 intel_get_adjust_train(struct intel_dp
*intel_dp
,
2710 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2715 uint8_t voltage_max
;
2716 uint8_t preemph_max
;
2718 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
2719 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
2720 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
2728 voltage_max
= intel_dp_voltage_max(intel_dp
);
2729 if (v
>= voltage_max
)
2730 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
2732 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
2733 if (p
>= preemph_max
)
2734 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
2736 for (lane
= 0; lane
< 4; lane
++)
2737 intel_dp
->train_set
[lane
] = v
| p
;
2741 intel_gen4_signal_levels(uint8_t train_set
)
2743 uint32_t signal_levels
= 0;
2745 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2746 case DP_TRAIN_VOLTAGE_SWING_400
:
2748 signal_levels
|= DP_VOLTAGE_0_4
;
2750 case DP_TRAIN_VOLTAGE_SWING_600
:
2751 signal_levels
|= DP_VOLTAGE_0_6
;
2753 case DP_TRAIN_VOLTAGE_SWING_800
:
2754 signal_levels
|= DP_VOLTAGE_0_8
;
2756 case DP_TRAIN_VOLTAGE_SWING_1200
:
2757 signal_levels
|= DP_VOLTAGE_1_2
;
2760 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2761 case DP_TRAIN_PRE_EMPHASIS_0
:
2763 signal_levels
|= DP_PRE_EMPHASIS_0
;
2765 case DP_TRAIN_PRE_EMPHASIS_3_5
:
2766 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
2768 case DP_TRAIN_PRE_EMPHASIS_6
:
2769 signal_levels
|= DP_PRE_EMPHASIS_6
;
2771 case DP_TRAIN_PRE_EMPHASIS_9_5
:
2772 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
2775 return signal_levels
;
2778 /* Gen6's DP voltage swing and pre-emphasis control */
2780 intel_gen6_edp_signal_levels(uint8_t train_set
)
2782 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2783 DP_TRAIN_PRE_EMPHASIS_MASK
);
2784 switch (signal_levels
) {
2785 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2786 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2787 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2788 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2789 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
2790 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2791 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2792 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
2793 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2794 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2795 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
2796 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2797 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
2798 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
2800 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2801 "0x%x\n", signal_levels
);
2802 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
2806 /* Gen7's DP voltage swing and pre-emphasis control */
2808 intel_gen7_edp_signal_levels(uint8_t train_set
)
2810 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2811 DP_TRAIN_PRE_EMPHASIS_MASK
);
2812 switch (signal_levels
) {
2813 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2814 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
2815 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2816 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
2817 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2818 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
2820 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2821 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
2822 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2823 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
2825 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2826 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
2827 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2828 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
2831 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2832 "0x%x\n", signal_levels
);
2833 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
2837 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2839 intel_hsw_signal_levels(uint8_t train_set
)
2841 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2842 DP_TRAIN_PRE_EMPHASIS_MASK
);
2843 switch (signal_levels
) {
2844 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
2845 return DDI_BUF_EMP_400MV_0DB_HSW
;
2846 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2847 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
2848 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
2849 return DDI_BUF_EMP_400MV_6DB_HSW
;
2850 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
2851 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
2853 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
2854 return DDI_BUF_EMP_600MV_0DB_HSW
;
2855 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2856 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
2857 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
2858 return DDI_BUF_EMP_600MV_6DB_HSW
;
2860 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
2861 return DDI_BUF_EMP_800MV_0DB_HSW
;
2862 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
2863 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
2865 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2866 "0x%x\n", signal_levels
);
2867 return DDI_BUF_EMP_400MV_0DB_HSW
;
2871 /* Properly updates "DP" with the correct signal levels. */
2873 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
2875 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2876 enum port port
= intel_dig_port
->port
;
2877 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2878 uint32_t signal_levels
, mask
;
2879 uint8_t train_set
= intel_dp
->train_set
[0];
2881 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2882 signal_levels
= intel_hsw_signal_levels(train_set
);
2883 mask
= DDI_BUF_EMP_MASK
;
2884 } else if (IS_CHERRYVIEW(dev
)) {
2885 signal_levels
= intel_chv_signal_levels(intel_dp
);
2887 } else if (IS_VALLEYVIEW(dev
)) {
2888 signal_levels
= intel_vlv_signal_levels(intel_dp
);
2890 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2891 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
2892 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
2893 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
2894 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
2895 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
2897 signal_levels
= intel_gen4_signal_levels(train_set
);
2898 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
2901 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
2903 *DP
= (*DP
& ~mask
) | signal_levels
;
2907 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2909 uint8_t dp_train_pat
)
2911 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2912 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2914 enum port port
= intel_dig_port
->port
;
2915 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
2919 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2921 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2922 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2924 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2926 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2927 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2928 case DP_TRAINING_PATTERN_DISABLE
:
2929 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2932 case DP_TRAINING_PATTERN_1
:
2933 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2935 case DP_TRAINING_PATTERN_2
:
2936 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2938 case DP_TRAINING_PATTERN_3
:
2939 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2942 I915_WRITE(DP_TP_CTL(port
), temp
);
2944 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2945 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2947 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2948 case DP_TRAINING_PATTERN_DISABLE
:
2949 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2951 case DP_TRAINING_PATTERN_1
:
2952 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2954 case DP_TRAINING_PATTERN_2
:
2955 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2957 case DP_TRAINING_PATTERN_3
:
2958 DRM_ERROR("DP training pattern 3 not supported\n");
2959 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2964 if (IS_CHERRYVIEW(dev
))
2965 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2967 *DP
&= ~DP_LINK_TRAIN_MASK
;
2969 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2970 case DP_TRAINING_PATTERN_DISABLE
:
2971 *DP
|= DP_LINK_TRAIN_OFF
;
2973 case DP_TRAINING_PATTERN_1
:
2974 *DP
|= DP_LINK_TRAIN_PAT_1
;
2976 case DP_TRAINING_PATTERN_2
:
2977 *DP
|= DP_LINK_TRAIN_PAT_2
;
2979 case DP_TRAINING_PATTERN_3
:
2980 if (IS_CHERRYVIEW(dev
)) {
2981 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2983 DRM_ERROR("DP training pattern 3 not supported\n");
2984 *DP
|= DP_LINK_TRAIN_PAT_2
;
2990 I915_WRITE(intel_dp
->output_reg
, *DP
);
2991 POSTING_READ(intel_dp
->output_reg
);
2993 buf
[0] = dp_train_pat
;
2994 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
2995 DP_TRAINING_PATTERN_DISABLE
) {
2996 /* don't write DP_TRAINING_LANEx_SET on disable */
2999 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3000 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3001 len
= intel_dp
->lane_count
+ 1;
3004 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3011 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3012 uint8_t dp_train_pat
)
3014 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3015 intel_dp_set_signal_levels(intel_dp
, DP
);
3016 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3020 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3021 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3023 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3024 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3028 intel_get_adjust_train(intel_dp
, link_status
);
3029 intel_dp_set_signal_levels(intel_dp
, DP
);
3031 I915_WRITE(intel_dp
->output_reg
, *DP
);
3032 POSTING_READ(intel_dp
->output_reg
);
3034 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3035 intel_dp
->train_set
, intel_dp
->lane_count
);
3037 return ret
== intel_dp
->lane_count
;
3040 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3042 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3043 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3045 enum port port
= intel_dig_port
->port
;
3051 val
= I915_READ(DP_TP_CTL(port
));
3052 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3053 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3054 I915_WRITE(DP_TP_CTL(port
), val
);
3057 * On PORT_A we can have only eDP in SST mode. There the only reason
3058 * we need to set idle transmission mode is to work around a HW issue
3059 * where we enable the pipe while not in idle link-training mode.
3060 * In this case there is requirement to wait for a minimum number of
3061 * idle patterns to be sent.
3066 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3068 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3071 /* Enable corresponding port and start training pattern 1 */
3073 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3075 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3076 struct drm_device
*dev
= encoder
->dev
;
3079 int voltage_tries
, loop_tries
;
3080 uint32_t DP
= intel_dp
->DP
;
3081 uint8_t link_config
[2];
3084 intel_ddi_prepare_link_retrain(encoder
);
3086 /* Write the link configuration data */
3087 link_config
[0] = intel_dp
->link_bw
;
3088 link_config
[1] = intel_dp
->lane_count
;
3089 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3090 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3091 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3094 link_config
[1] = DP_SET_ANSI_8B10B
;
3095 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3099 /* clock recovery */
3100 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3101 DP_TRAINING_PATTERN_1
|
3102 DP_LINK_SCRAMBLING_DISABLE
)) {
3103 DRM_ERROR("failed to enable link training\n");
3111 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3113 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3114 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3115 DRM_ERROR("failed to get link status\n");
3119 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3120 DRM_DEBUG_KMS("clock recovery OK\n");
3124 /* Check to see if we've tried the max voltage */
3125 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3126 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3128 if (i
== intel_dp
->lane_count
) {
3130 if (loop_tries
== 5) {
3131 DRM_ERROR("too many full retries, give up\n");
3134 intel_dp_reset_link_train(intel_dp
, &DP
,
3135 DP_TRAINING_PATTERN_1
|
3136 DP_LINK_SCRAMBLING_DISABLE
);
3141 /* Check to see if we've tried the same voltage 5 times */
3142 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3144 if (voltage_tries
== 5) {
3145 DRM_ERROR("too many voltage retries, give up\n");
3150 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3152 /* Update training set as requested by target */
3153 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3154 DRM_ERROR("failed to update link training\n");
3163 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3165 bool channel_eq
= false;
3166 int tries
, cr_tries
;
3167 uint32_t DP
= intel_dp
->DP
;
3168 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3170 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3171 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3172 training_pattern
= DP_TRAINING_PATTERN_3
;
3174 /* channel equalization */
3175 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3177 DP_LINK_SCRAMBLING_DISABLE
)) {
3178 DRM_ERROR("failed to start channel equalization\n");
3186 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3189 DRM_ERROR("failed to train DP, aborting\n");
3193 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3194 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3195 DRM_ERROR("failed to get link status\n");
3199 /* Make sure clock is still ok */
3200 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3201 intel_dp_start_link_train(intel_dp
);
3202 intel_dp_set_link_train(intel_dp
, &DP
,
3204 DP_LINK_SCRAMBLING_DISABLE
);
3209 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3214 /* Try 5 times, then try clock recovery if that fails */
3216 intel_dp_link_down(intel_dp
);
3217 intel_dp_start_link_train(intel_dp
);
3218 intel_dp_set_link_train(intel_dp
, &DP
,
3220 DP_LINK_SCRAMBLING_DISABLE
);
3226 /* Update training set as requested by target */
3227 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3228 DRM_ERROR("failed to update link training\n");
3234 intel_dp_set_idle_link_train(intel_dp
);
3239 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3243 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3245 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3246 DP_TRAINING_PATTERN_DISABLE
);
3250 intel_dp_link_down(struct intel_dp
*intel_dp
)
3252 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3253 enum port port
= intel_dig_port
->port
;
3254 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3256 struct intel_crtc
*intel_crtc
=
3257 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3258 uint32_t DP
= intel_dp
->DP
;
3260 if (WARN_ON(HAS_DDI(dev
)))
3263 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3266 DRM_DEBUG_KMS("\n");
3268 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3269 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3270 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3272 if (IS_CHERRYVIEW(dev
))
3273 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3275 DP
&= ~DP_LINK_TRAIN_MASK
;
3276 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3278 POSTING_READ(intel_dp
->output_reg
);
3280 if (HAS_PCH_IBX(dev
) &&
3281 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3282 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3284 /* Hardware workaround: leaving our transcoder select
3285 * set to transcoder B while it's off will prevent the
3286 * corresponding HDMI output on transcoder A.
3288 * Combine this with another hardware workaround:
3289 * transcoder select bit can only be cleared while the
3292 DP
&= ~DP_PIPEB_SELECT
;
3293 I915_WRITE(intel_dp
->output_reg
, DP
);
3295 /* Changes to enable or select take place the vblank
3296 * after being written.
3298 if (WARN_ON(crtc
== NULL
)) {
3299 /* We should never try to disable a port without a crtc
3300 * attached. For paranoia keep the code around for a
3302 POSTING_READ(intel_dp
->output_reg
);
3305 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3308 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3309 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3310 POSTING_READ(intel_dp
->output_reg
);
3311 msleep(intel_dp
->panel_power_down_delay
);
3315 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3317 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3318 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3321 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
3323 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3324 sizeof(intel_dp
->dpcd
)) < 0)
3325 return false; /* aux transfer failed */
3327 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
3328 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
3329 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
3331 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3332 return false; /* DPCD not present */
3334 /* Check if the panel supports PSR */
3335 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3336 if (is_edp(intel_dp
)) {
3337 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3339 sizeof(intel_dp
->psr_dpcd
));
3340 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3341 dev_priv
->psr
.sink_support
= true;
3342 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3346 /* Training Pattern 3 support */
3347 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3348 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3349 intel_dp
->use_tps3
= true;
3350 DRM_DEBUG_KMS("Displayport TPS3 supported");
3352 intel_dp
->use_tps3
= false;
3354 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3355 DP_DWN_STRM_PORT_PRESENT
))
3356 return true; /* native DP sink */
3358 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3359 return true; /* no per-port downstream info */
3361 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3362 intel_dp
->downstream_ports
,
3363 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3364 return false; /* downstream port status fetch failed */
3370 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3374 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3377 intel_edp_panel_vdd_on(intel_dp
);
3379 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3380 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3381 buf
[0], buf
[1], buf
[2]);
3383 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3384 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3385 buf
[0], buf
[1], buf
[2]);
3387 edp_panel_vdd_off(intel_dp
, false);
3391 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3395 if (!intel_dp
->can_mst
)
3398 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3401 _edp_panel_vdd_on(intel_dp
);
3402 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3403 if (buf
[0] & DP_MST_CAP
) {
3404 DRM_DEBUG_KMS("Sink is MST capable\n");
3405 intel_dp
->is_mst
= true;
3407 DRM_DEBUG_KMS("Sink is not MST capable\n");
3408 intel_dp
->is_mst
= false;
3411 edp_panel_vdd_off(intel_dp
, false);
3413 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3414 return intel_dp
->is_mst
;
3417 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3419 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3420 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3421 struct intel_crtc
*intel_crtc
=
3422 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3425 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3428 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3431 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3432 DP_TEST_SINK_START
) < 0)
3435 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3436 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3437 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3439 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3442 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3447 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3449 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3450 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3451 sink_irq_vector
, 1) == 1;
3455 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3459 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3461 sink_irq_vector
, 14);
3469 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3471 /* NAK by default */
3472 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3476 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3480 if (intel_dp
->is_mst
) {
3485 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3489 /* check link status - esi[10] = 0x200c */
3490 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3491 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3492 intel_dp_start_link_train(intel_dp
);
3493 intel_dp_complete_link_train(intel_dp
);
3494 intel_dp_stop_link_train(intel_dp
);
3497 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3498 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3501 for (retry
= 0; retry
< 3; retry
++) {
3503 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3504 DP_SINK_COUNT_ESI
+1,
3511 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3513 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3521 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3522 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3523 intel_dp
->is_mst
= false;
3524 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3525 /* send a hotplug event */
3526 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3533 * According to DP spec
3536 * 2. Configure link according to Receiver Capabilities
3537 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3538 * 4. Check link status on receipt of hot-plug interrupt
3541 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3543 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3544 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3546 u8 link_status
[DP_LINK_STATUS_SIZE
];
3548 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3550 if (!intel_encoder
->connectors_active
)
3553 if (WARN_ON(!intel_encoder
->base
.crtc
))
3556 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3559 /* Try to read receiver status if the link appears to be up */
3560 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3564 /* Now read the DPCD to see if it's actually running */
3565 if (!intel_dp_get_dpcd(intel_dp
)) {
3569 /* Try to read the source of the interrupt */
3570 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3571 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3572 /* Clear interrupt source */
3573 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3574 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3577 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3578 intel_dp_handle_test_request(intel_dp
);
3579 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3580 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3583 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3584 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3585 intel_encoder
->base
.name
);
3586 intel_dp_start_link_train(intel_dp
);
3587 intel_dp_complete_link_train(intel_dp
);
3588 intel_dp_stop_link_train(intel_dp
);
3592 /* XXX this is probably wrong for multiple downstream ports */
3593 static enum drm_connector_status
3594 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3596 uint8_t *dpcd
= intel_dp
->dpcd
;
3599 if (!intel_dp_get_dpcd(intel_dp
))
3600 return connector_status_disconnected
;
3602 /* if there's no downstream port, we're done */
3603 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3604 return connector_status_connected
;
3606 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3607 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3608 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3611 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3613 return connector_status_unknown
;
3615 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3616 : connector_status_disconnected
;
3619 /* If no HPD, poke DDC gently */
3620 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3621 return connector_status_connected
;
3623 /* Well we tried, say unknown for unreliable port types */
3624 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3625 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3626 if (type
== DP_DS_PORT_TYPE_VGA
||
3627 type
== DP_DS_PORT_TYPE_NON_EDID
)
3628 return connector_status_unknown
;
3630 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3631 DP_DWN_STRM_PORT_TYPE_MASK
;
3632 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3633 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3634 return connector_status_unknown
;
3637 /* Anything else is out of spec, warn and ignore */
3638 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3639 return connector_status_disconnected
;
3642 static enum drm_connector_status
3643 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3645 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3647 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3648 enum drm_connector_status status
;
3650 /* Can't disconnect eDP, but you can close the lid... */
3651 if (is_edp(intel_dp
)) {
3652 status
= intel_panel_detect(dev
);
3653 if (status
== connector_status_unknown
)
3654 status
= connector_status_connected
;
3658 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3659 return connector_status_disconnected
;
3661 return intel_dp_detect_dpcd(intel_dp
);
3664 static enum drm_connector_status
3665 g4x_dp_detect(struct intel_dp
*intel_dp
)
3667 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3669 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3672 /* Can't disconnect eDP, but you can close the lid... */
3673 if (is_edp(intel_dp
)) {
3674 enum drm_connector_status status
;
3676 status
= intel_panel_detect(dev
);
3677 if (status
== connector_status_unknown
)
3678 status
= connector_status_connected
;
3682 if (IS_VALLEYVIEW(dev
)) {
3683 switch (intel_dig_port
->port
) {
3685 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3688 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3691 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3694 return connector_status_unknown
;
3697 switch (intel_dig_port
->port
) {
3699 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3702 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3705 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3708 return connector_status_unknown
;
3712 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3713 return connector_status_disconnected
;
3715 return intel_dp_detect_dpcd(intel_dp
);
3718 static struct edid
*
3719 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3721 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3723 /* use cached edid if we have one */
3724 if (intel_connector
->edid
) {
3726 if (IS_ERR(intel_connector
->edid
))
3729 return drm_edid_duplicate(intel_connector
->edid
);
3732 return drm_get_edid(connector
, adapter
);
3736 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
3738 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3740 /* use cached edid if we have one */
3741 if (intel_connector
->edid
) {
3743 if (IS_ERR(intel_connector
->edid
))
3746 return intel_connector_update_modes(connector
,
3747 intel_connector
->edid
);
3750 return intel_ddc_get_modes(connector
, adapter
);
3753 static enum drm_connector_status
3754 intel_dp_detect(struct drm_connector
*connector
, bool force
)
3756 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3757 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3758 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3759 struct drm_device
*dev
= connector
->dev
;
3760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3761 enum drm_connector_status status
;
3762 enum intel_display_power_domain power_domain
;
3763 struct edid
*edid
= NULL
;
3766 power_domain
= intel_display_port_power_domain(intel_encoder
);
3767 intel_display_power_get(dev_priv
, power_domain
);
3769 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3770 connector
->base
.id
, connector
->name
);
3772 if (intel_dp
->is_mst
) {
3773 /* MST devices are disconnected from a monitor POV */
3774 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3775 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3776 status
= connector_status_disconnected
;
3780 intel_dp
->has_audio
= false;
3782 if (HAS_PCH_SPLIT(dev
))
3783 status
= ironlake_dp_detect(intel_dp
);
3785 status
= g4x_dp_detect(intel_dp
);
3787 if (status
!= connector_status_connected
)
3790 intel_dp_probe_oui(intel_dp
);
3792 ret
= intel_dp_probe_mst(intel_dp
);
3794 /* if we are in MST mode then this connector
3795 won't appear connected or have anything with EDID on it */
3796 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3797 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3798 status
= connector_status_disconnected
;
3802 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
3803 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
3805 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3807 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
3812 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
3813 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
3814 status
= connector_status_connected
;
3817 intel_display_power_put(dev_priv
, power_domain
);
3821 static int intel_dp_get_modes(struct drm_connector
*connector
)
3823 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3824 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3825 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3826 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3827 struct drm_device
*dev
= connector
->dev
;
3828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3829 enum intel_display_power_domain power_domain
;
3832 /* We should parse the EDID data and find out if it has an audio sink
3835 power_domain
= intel_display_port_power_domain(intel_encoder
);
3836 intel_display_power_get(dev_priv
, power_domain
);
3838 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->aux
.ddc
);
3839 intel_display_power_put(dev_priv
, power_domain
);
3843 /* if eDP has no EDID, fall back to fixed mode */
3844 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
3845 struct drm_display_mode
*mode
;
3846 mode
= drm_mode_duplicate(dev
,
3847 intel_connector
->panel
.fixed_mode
);
3849 drm_mode_probed_add(connector
, mode
);
3857 intel_dp_detect_audio(struct drm_connector
*connector
)
3859 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
3860 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3861 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3862 struct drm_device
*dev
= connector
->dev
;
3863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3864 enum intel_display_power_domain power_domain
;
3866 bool has_audio
= false;
3868 power_domain
= intel_display_port_power_domain(intel_encoder
);
3869 intel_display_power_get(dev_priv
, power_domain
);
3871 edid
= intel_dp_get_edid(connector
, &intel_dp
->aux
.ddc
);
3873 has_audio
= drm_detect_monitor_audio(edid
);
3877 intel_display_power_put(dev_priv
, power_domain
);
3883 intel_dp_set_property(struct drm_connector
*connector
,
3884 struct drm_property
*property
,
3887 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
3888 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3889 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
3890 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
3893 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
3897 if (property
== dev_priv
->force_audio_property
) {
3901 if (i
== intel_dp
->force_audio
)
3904 intel_dp
->force_audio
= i
;
3906 if (i
== HDMI_AUDIO_AUTO
)
3907 has_audio
= intel_dp_detect_audio(connector
);
3909 has_audio
= (i
== HDMI_AUDIO_ON
);
3911 if (has_audio
== intel_dp
->has_audio
)
3914 intel_dp
->has_audio
= has_audio
;
3918 if (property
== dev_priv
->broadcast_rgb_property
) {
3919 bool old_auto
= intel_dp
->color_range_auto
;
3920 uint32_t old_range
= intel_dp
->color_range
;
3923 case INTEL_BROADCAST_RGB_AUTO
:
3924 intel_dp
->color_range_auto
= true;
3926 case INTEL_BROADCAST_RGB_FULL
:
3927 intel_dp
->color_range_auto
= false;
3928 intel_dp
->color_range
= 0;
3930 case INTEL_BROADCAST_RGB_LIMITED
:
3931 intel_dp
->color_range_auto
= false;
3932 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
3938 if (old_auto
== intel_dp
->color_range_auto
&&
3939 old_range
== intel_dp
->color_range
)
3945 if (is_edp(intel_dp
) &&
3946 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
3947 if (val
== DRM_MODE_SCALE_NONE
) {
3948 DRM_DEBUG_KMS("no scaling not supported\n");
3952 if (intel_connector
->panel
.fitting_mode
== val
) {
3953 /* the eDP scaling property is not changed */
3956 intel_connector
->panel
.fitting_mode
= val
;
3964 if (intel_encoder
->base
.crtc
)
3965 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
3971 intel_dp_connector_destroy(struct drm_connector
*connector
)
3973 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
3975 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
3976 kfree(intel_connector
->edid
);
3978 /* Can't call is_edp() since the encoder may have been destroyed
3980 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3981 intel_panel_fini(&intel_connector
->panel
);
3983 drm_connector_cleanup(connector
);
3987 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
3989 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
3990 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
3991 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3993 drm_dp_aux_unregister(&intel_dp
->aux
);
3994 intel_dp_mst_encoder_cleanup(intel_dig_port
);
3995 drm_encoder_cleanup(encoder
);
3996 if (is_edp(intel_dp
)) {
3997 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
3998 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
3999 edp_panel_vdd_off_sync(intel_dp
);
4000 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4001 if (intel_dp
->edp_notifier
.notifier_call
) {
4002 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4003 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4006 kfree(intel_dig_port
);
4009 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4011 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4013 if (!is_edp(intel_dp
))
4016 edp_panel_vdd_off_sync(intel_dp
);
4019 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4021 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4024 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4025 .dpms
= intel_connector_dpms
,
4026 .detect
= intel_dp_detect
,
4027 .fill_modes
= drm_helper_probe_single_connector_modes
,
4028 .set_property
= intel_dp_set_property
,
4029 .destroy
= intel_dp_connector_destroy
,
4032 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4033 .get_modes
= intel_dp_get_modes
,
4034 .mode_valid
= intel_dp_mode_valid
,
4035 .best_encoder
= intel_best_encoder
,
4038 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4039 .reset
= intel_dp_encoder_reset
,
4040 .destroy
= intel_dp_encoder_destroy
,
4044 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4050 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4052 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4053 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4054 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4056 enum intel_display_power_domain power_domain
;
4059 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4060 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4062 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4063 port_name(intel_dig_port
->port
),
4064 long_hpd
? "long" : "short");
4066 power_domain
= intel_display_port_power_domain(intel_encoder
);
4067 intel_display_power_get(dev_priv
, power_domain
);
4070 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4073 if (!intel_dp_get_dpcd(intel_dp
)) {
4077 intel_dp_probe_oui(intel_dp
);
4079 if (!intel_dp_probe_mst(intel_dp
))
4083 if (intel_dp
->is_mst
) {
4084 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4088 if (!intel_dp
->is_mst
) {
4090 * we'll check the link status via the normal hot plug path later -
4091 * but for short hpds we should check it now
4093 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4094 intel_dp_check_link_status(intel_dp
);
4095 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4101 /* if we were in MST mode, and device is not there get out of MST mode */
4102 if (intel_dp
->is_mst
) {
4103 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4104 intel_dp
->is_mst
= false;
4105 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4108 intel_display_power_put(dev_priv
, power_domain
);
4113 /* Return which DP Port should be selected for Transcoder DP control */
4115 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4117 struct drm_device
*dev
= crtc
->dev
;
4118 struct intel_encoder
*intel_encoder
;
4119 struct intel_dp
*intel_dp
;
4121 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4122 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4124 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4125 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4126 return intel_dp
->output_reg
;
4132 /* check the VBT to see whether the eDP is on DP-D port */
4133 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4136 union child_device_config
*p_child
;
4138 static const short port_mapping
[] = {
4139 [PORT_B
] = PORT_IDPB
,
4140 [PORT_C
] = PORT_IDPC
,
4141 [PORT_D
] = PORT_IDPD
,
4147 if (!dev_priv
->vbt
.child_dev_num
)
4150 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4151 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4153 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4154 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4155 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4162 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4164 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4166 intel_attach_force_audio_property(connector
);
4167 intel_attach_broadcast_rgb_property(connector
);
4168 intel_dp
->color_range_auto
= true;
4170 if (is_edp(intel_dp
)) {
4171 drm_mode_create_scaling_mode_property(connector
->dev
);
4172 drm_object_attach_property(
4174 connector
->dev
->mode_config
.scaling_mode_property
,
4175 DRM_MODE_SCALE_ASPECT
);
4176 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4180 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4182 intel_dp
->last_power_cycle
= jiffies
;
4183 intel_dp
->last_power_on
= jiffies
;
4184 intel_dp
->last_backlight_off
= jiffies
;
4188 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4189 struct intel_dp
*intel_dp
,
4190 struct edp_power_seq
*out
)
4192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4193 struct edp_power_seq cur
, vbt
, spec
, final
;
4194 u32 pp_on
, pp_off
, pp_div
, pp
;
4195 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4197 if (HAS_PCH_SPLIT(dev
)) {
4198 pp_ctrl_reg
= PCH_PP_CONTROL
;
4199 pp_on_reg
= PCH_PP_ON_DELAYS
;
4200 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4201 pp_div_reg
= PCH_PP_DIVISOR
;
4203 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4205 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4206 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4207 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4208 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4211 /* Workaround: Need to write PP_CONTROL with the unlock key as
4212 * the very first thing. */
4213 pp
= ironlake_get_pp_control(intel_dp
);
4214 I915_WRITE(pp_ctrl_reg
, pp
);
4216 pp_on
= I915_READ(pp_on_reg
);
4217 pp_off
= I915_READ(pp_off_reg
);
4218 pp_div
= I915_READ(pp_div_reg
);
4220 /* Pull timing values out of registers */
4221 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4222 PANEL_POWER_UP_DELAY_SHIFT
;
4224 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4225 PANEL_LIGHT_ON_DELAY_SHIFT
;
4227 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4228 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4230 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4231 PANEL_POWER_DOWN_DELAY_SHIFT
;
4233 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4234 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4236 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4237 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4239 vbt
= dev_priv
->vbt
.edp_pps
;
4241 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4242 * our hw here, which are all in 100usec. */
4243 spec
.t1_t3
= 210 * 10;
4244 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4245 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4246 spec
.t10
= 500 * 10;
4247 /* This one is special and actually in units of 100ms, but zero
4248 * based in the hw (so we need to add 100 ms). But the sw vbt
4249 * table multiplies it with 1000 to make it in units of 100usec,
4251 spec
.t11_t12
= (510 + 100) * 10;
4253 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4254 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4256 /* Use the max of the register settings and vbt. If both are
4257 * unset, fall back to the spec limits. */
4258 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4260 max(cur.field, vbt.field))
4261 assign_final(t1_t3
);
4265 assign_final(t11_t12
);
4268 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4269 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4270 intel_dp
->backlight_on_delay
= get_delay(t8
);
4271 intel_dp
->backlight_off_delay
= get_delay(t9
);
4272 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4273 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4276 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4277 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4278 intel_dp
->panel_power_cycle_delay
);
4280 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4281 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4288 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4289 struct intel_dp
*intel_dp
,
4290 struct edp_power_seq
*seq
)
4292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4293 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4294 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4295 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4297 if (HAS_PCH_SPLIT(dev
)) {
4298 pp_on_reg
= PCH_PP_ON_DELAYS
;
4299 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4300 pp_div_reg
= PCH_PP_DIVISOR
;
4302 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4304 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4305 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4306 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4310 * And finally store the new values in the power sequencer. The
4311 * backlight delays are set to 1 because we do manual waits on them. For
4312 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4313 * we'll end up waiting for the backlight off delay twice: once when we
4314 * do the manual sleep, and once when we disable the panel and wait for
4315 * the PP_STATUS bit to become zero.
4317 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4318 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4319 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4320 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4321 /* Compute the divisor for the pp clock, simply match the Bspec
4323 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4324 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4325 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4327 /* Haswell doesn't have any port selection bits for the panel
4328 * power sequencer any more. */
4329 if (IS_VALLEYVIEW(dev
)) {
4330 if (dp_to_dig_port(intel_dp
)->port
== PORT_B
)
4331 port_sel
= PANEL_PORT_SELECT_DPB_VLV
;
4333 port_sel
= PANEL_PORT_SELECT_DPC_VLV
;
4334 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4335 if (dp_to_dig_port(intel_dp
)->port
== PORT_A
)
4336 port_sel
= PANEL_PORT_SELECT_DPA
;
4338 port_sel
= PANEL_PORT_SELECT_DPD
;
4343 I915_WRITE(pp_on_reg
, pp_on
);
4344 I915_WRITE(pp_off_reg
, pp_off
);
4345 I915_WRITE(pp_div_reg
, pp_div
);
4347 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4348 I915_READ(pp_on_reg
),
4349 I915_READ(pp_off_reg
),
4350 I915_READ(pp_div_reg
));
4353 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4356 struct intel_encoder
*encoder
;
4357 struct intel_dp
*intel_dp
= NULL
;
4358 struct intel_crtc_config
*config
= NULL
;
4359 struct intel_crtc
*intel_crtc
= NULL
;
4360 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4362 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4364 if (refresh_rate
<= 0) {
4365 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4369 if (intel_connector
== NULL
) {
4370 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4375 * FIXME: This needs proper synchronization with psr state. But really
4376 * hard to tell without seeing the user of this function of this code.
4377 * Check locking and ordering once that lands.
4379 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4380 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4384 encoder
= intel_attached_encoder(&intel_connector
->base
);
4385 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4386 intel_crtc
= encoder
->new_crtc
;
4389 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4393 config
= &intel_crtc
->config
;
4395 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4396 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4400 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4401 index
= DRRS_LOW_RR
;
4403 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4405 "DRRS requested for previously set RR...ignoring\n");
4409 if (!intel_crtc
->active
) {
4410 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4414 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4415 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4416 val
= I915_READ(reg
);
4417 if (index
> DRRS_HIGH_RR
) {
4418 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4419 intel_dp_set_m_n(intel_crtc
);
4421 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4423 I915_WRITE(reg
, val
);
4427 * mutex taken to ensure that there is no race between differnt
4428 * drrs calls trying to update refresh rate. This scenario may occur
4429 * in future when idleness detection based DRRS in kernel and
4430 * possible calls from user space to set differnt RR are made.
4433 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4435 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4437 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4439 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4442 static struct drm_display_mode
*
4443 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4444 struct intel_connector
*intel_connector
,
4445 struct drm_display_mode
*fixed_mode
)
4447 struct drm_connector
*connector
= &intel_connector
->base
;
4448 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4449 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4451 struct drm_display_mode
*downclock_mode
= NULL
;
4453 if (INTEL_INFO(dev
)->gen
<= 6) {
4454 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4458 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4459 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4463 downclock_mode
= intel_find_panel_downclock
4464 (dev
, fixed_mode
, connector
);
4466 if (!downclock_mode
) {
4467 DRM_DEBUG_KMS("DRRS not supported\n");
4471 dev_priv
->drrs
.connector
= intel_connector
;
4473 mutex_init(&intel_dp
->drrs_state
.mutex
);
4475 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4477 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4478 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4479 return downclock_mode
;
4482 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
4484 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4486 struct intel_dp
*intel_dp
;
4487 enum intel_display_power_domain power_domain
;
4489 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4492 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4493 if (!edp_have_panel_vdd(intel_dp
))
4496 * The VDD bit needs a power domain reference, so if the bit is
4497 * already enabled when we boot or resume, grab this reference and
4498 * schedule a vdd off, so we don't hold on to the reference
4501 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4502 power_domain
= intel_display_port_power_domain(intel_encoder
);
4503 intel_display_power_get(dev_priv
, power_domain
);
4505 edp_panel_vdd_schedule_off(intel_dp
);
4508 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4509 struct intel_connector
*intel_connector
,
4510 struct edp_power_seq
*power_seq
)
4512 struct drm_connector
*connector
= &intel_connector
->base
;
4513 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4514 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4515 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4517 struct drm_display_mode
*fixed_mode
= NULL
;
4518 struct drm_display_mode
*downclock_mode
= NULL
;
4520 struct drm_display_mode
*scan
;
4523 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4525 if (!is_edp(intel_dp
))
4528 intel_edp_panel_vdd_sanitize(intel_encoder
);
4530 /* Cache DPCD and EDID for edp. */
4531 intel_edp_panel_vdd_on(intel_dp
);
4532 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4533 edp_panel_vdd_off(intel_dp
, false);
4536 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4537 dev_priv
->no_aux_handshake
=
4538 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4539 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4541 /* if this fails, presume the device is a ghost */
4542 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4546 /* We now know it's not a ghost, init power sequence regs. */
4547 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4549 mutex_lock(&dev
->mode_config
.mutex
);
4550 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4552 if (drm_add_edid_modes(connector
, edid
)) {
4553 drm_mode_connector_update_edid_property(connector
,
4555 drm_edid_to_eld(connector
, edid
);
4558 edid
= ERR_PTR(-EINVAL
);
4561 edid
= ERR_PTR(-ENOENT
);
4563 intel_connector
->edid
= edid
;
4565 /* prefer fixed mode from EDID if available */
4566 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4567 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4568 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4569 downclock_mode
= intel_dp_drrs_init(
4571 intel_connector
, fixed_mode
);
4576 /* fallback to VBT if available for eDP */
4577 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4578 fixed_mode
= drm_mode_duplicate(dev
,
4579 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4581 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4583 mutex_unlock(&dev
->mode_config
.mutex
);
4585 if (IS_VALLEYVIEW(dev
)) {
4586 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
4587 register_reboot_notifier(&intel_dp
->edp_notifier
);
4590 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4591 intel_panel_setup_backlight(connector
);
4597 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4598 struct intel_connector
*intel_connector
)
4600 struct drm_connector
*connector
= &intel_connector
->base
;
4601 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4602 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4603 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4605 enum port port
= intel_dig_port
->port
;
4606 struct edp_power_seq power_seq
= { 0 };
4609 /* intel_dp vfuncs */
4610 if (IS_VALLEYVIEW(dev
))
4611 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
4612 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4613 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
4614 else if (HAS_PCH_SPLIT(dev
))
4615 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
4617 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
4619 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
4621 /* Preserve the current hw state. */
4622 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4623 intel_dp
->attached_connector
= intel_connector
;
4625 if (intel_dp_is_edp(dev
, port
))
4626 type
= DRM_MODE_CONNECTOR_eDP
;
4628 type
= DRM_MODE_CONNECTOR_DisplayPort
;
4631 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4632 * for DP the encoder type can be set by the caller to
4633 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4635 if (type
== DRM_MODE_CONNECTOR_eDP
)
4636 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
4638 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4639 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
4642 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
4643 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
4645 connector
->interlace_allowed
= true;
4646 connector
->doublescan_allowed
= 0;
4648 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
4649 edp_panel_vdd_work
);
4651 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
4652 drm_connector_register(connector
);
4655 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
4657 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
4658 intel_connector
->unregister
= intel_dp_connector_unregister
;
4660 /* Set up the hotplug pin. */
4663 intel_encoder
->hpd_pin
= HPD_PORT_A
;
4666 intel_encoder
->hpd_pin
= HPD_PORT_B
;
4669 intel_encoder
->hpd_pin
= HPD_PORT_C
;
4672 intel_encoder
->hpd_pin
= HPD_PORT_D
;
4678 if (is_edp(intel_dp
)) {
4679 intel_dp_init_panel_power_timestamps(intel_dp
);
4680 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
4683 intel_dp_aux_init(intel_dp
, intel_connector
);
4685 /* init MST on ports that can support it */
4686 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4687 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
4688 intel_dp_mst_encoder_init(intel_dig_port
, intel_connector
->base
.base
.id
);
4692 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
4693 drm_dp_aux_unregister(&intel_dp
->aux
);
4694 if (is_edp(intel_dp
)) {
4695 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4696 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4697 edp_panel_vdd_off_sync(intel_dp
);
4698 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4700 drm_connector_unregister(connector
);
4701 drm_connector_cleanup(connector
);
4705 intel_dp_add_properties(intel_dp
, connector
);
4707 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4708 * 0xd. Failure to do so will result in spurious interrupts being
4709 * generated on the port when a cable is not attached.
4711 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
4712 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
4713 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
4720 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
4722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4723 struct intel_digital_port
*intel_dig_port
;
4724 struct intel_encoder
*intel_encoder
;
4725 struct drm_encoder
*encoder
;
4726 struct intel_connector
*intel_connector
;
4728 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
4729 if (!intel_dig_port
)
4732 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
4733 if (!intel_connector
) {
4734 kfree(intel_dig_port
);
4738 intel_encoder
= &intel_dig_port
->base
;
4739 encoder
= &intel_encoder
->base
;
4741 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
4742 DRM_MODE_ENCODER_TMDS
);
4744 intel_encoder
->compute_config
= intel_dp_compute_config
;
4745 intel_encoder
->disable
= intel_disable_dp
;
4746 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
4747 intel_encoder
->get_config
= intel_dp_get_config
;
4748 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
4749 if (IS_CHERRYVIEW(dev
)) {
4750 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
4751 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
4752 intel_encoder
->enable
= vlv_enable_dp
;
4753 intel_encoder
->post_disable
= chv_post_disable_dp
;
4754 } else if (IS_VALLEYVIEW(dev
)) {
4755 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
4756 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
4757 intel_encoder
->enable
= vlv_enable_dp
;
4758 intel_encoder
->post_disable
= vlv_post_disable_dp
;
4760 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
4761 intel_encoder
->enable
= g4x_enable_dp
;
4762 intel_encoder
->post_disable
= g4x_post_disable_dp
;
4765 intel_dig_port
->port
= port
;
4766 intel_dig_port
->dp
.output_reg
= output_reg
;
4768 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4769 if (IS_CHERRYVIEW(dev
)) {
4771 intel_encoder
->crtc_mask
= 1 << 2;
4773 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
4775 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
4777 intel_encoder
->cloneable
= 0;
4778 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
4780 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
4781 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
4783 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
4784 drm_encoder_cleanup(encoder
);
4785 kfree(intel_dig_port
);
4786 kfree(intel_connector
);
4790 void intel_dp_mst_suspend(struct drm_device
*dev
)
4792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4796 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4797 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4798 if (!intel_dig_port
)
4801 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4802 if (!intel_dig_port
->dp
.can_mst
)
4804 if (intel_dig_port
->dp
.is_mst
)
4805 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
4810 void intel_dp_mst_resume(struct drm_device
*dev
)
4812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4815 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
4816 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
4817 if (!intel_dig_port
)
4819 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
4822 if (!intel_dig_port
->dp
.can_mst
)
4825 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
4827 intel_dp_check_mst_status(&intel_dig_port
->dp
);